From 877a679b26750f6fe1b29273c79416c0d5e53541 Mon Sep 17 00:00:00 2001 From: yuanbin Date: Thu, 7 May 2015 18:57:43 +0800 Subject: [PATCH 01/18] netif find error --- components/net/lwip_dhcpd/dhcp_server.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/components/net/lwip_dhcpd/dhcp_server.c b/components/net/lwip_dhcpd/dhcp_server.c index 47547a598b..f242236606 100644 --- a/components/net/lwip_dhcpd/dhcp_server.c +++ b/components/net/lwip_dhcpd/dhcp_server.c @@ -376,13 +376,24 @@ static void dhcpd_thread_entry(void *parameter) void dhcpd_start(char* netif_name) { rt_thread_t thread; - struct netif *netif = RT_NULL; + struct netif *netif = netif_list; - /* find ethernet interface. */ - netif = netif_find(netif_name); - if (netif == RT_NULL) + if(strlen(netif_name) > sizeof(netif->name)) { - DEBUG_PRINTF("Not found network interface:%s\n", netif_name); + rt_kprintf("network interface name too long!\r\n"); + return; + } + while(netif != RT_NULL) + { + if(strncmp(netif_name, netif->name, sizeof(netif->name)) == 0) + break; + + netif = netif->next; + if( netif == RT_NULL ) + { + rt_kprintf("network interface: %s not found!\r\n", netif_name); + return; + } } thread = rt_thread_create("dhcpd", From d01bab0e3912dcb27f5b8920ca3e742e73f26810 Mon Sep 17 00:00:00 2001 From: pangwei <271372443@qq.com> Date: Fri, 8 May 2015 11:34:17 +0800 Subject: [PATCH 02/18] [bugfix] Open the #define RT_USING_LWIP in rtconfig.h , then build it , the stm32_eth.h can not find. Signed-off-by: pangwei <271372443@qq.com> --- bsp/stm32f40x/applications/application.c | 2 +- bsp/stm32f40x/drivers/SConscript | 18 +- bsp/stm32f40x/drivers/stm32f4xx_eth.c | 4038 ++++++++++++++++++++++ bsp/stm32f40x/drivers/stm32f4xx_eth.h | 1874 ++++++++++ 4 files changed, 5930 insertions(+), 2 deletions(-) create mode 100644 bsp/stm32f40x/drivers/stm32f4xx_eth.c create mode 100644 bsp/stm32f40x/drivers/stm32f4xx_eth.h diff --git a/bsp/stm32f40x/applications/application.c b/bsp/stm32f40x/applications/application.c index c5e5bcf296..bfa3428eca 100644 --- a/bsp/stm32f40x/applications/application.c +++ b/bsp/stm32f40x/applications/application.c @@ -20,7 +20,7 @@ #include #include #include -#include "stm32_eth.h" +#include "stm32f4xx_eth.h" #endif #ifdef RT_USING_GDB diff --git a/bsp/stm32f40x/drivers/SConscript b/bsp/stm32f40x/drivers/SConscript index 5bbef48785..8037c3ea5b 100644 --- a/bsp/stm32f40x/drivers/SConscript +++ b/bsp/stm32f40x/drivers/SConscript @@ -3,9 +3,25 @@ Import('rtconfig') from building import * cwd = os.path.join(str(Dir('#')), 'drivers') -src = Glob('*.c') + +# add the general drivers. +src = Split(""" +board.c +stm32f4xx_it.c +usart.c +""") + +# add Ethernet drivers. +if GetDepend('RT_USING_LWIP'): + src += ['stm32f4xx_eth.c'] + +# add gpio drivers. +if GetDepend('RT_USING_PIN'): + src += ['gpio.c'] + CPPPATH = [cwd] group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) Return('group') + diff --git a/bsp/stm32f40x/drivers/stm32f4xx_eth.c b/bsp/stm32f40x/drivers/stm32f4xx_eth.c new file mode 100644 index 0000000000..6b3a6fece1 --- /dev/null +++ b/bsp/stm32f40x/drivers/stm32f4xx_eth.c @@ -0,0 +1,4038 @@ +/** + ****************************************************************************** + * @file stm32f2xx_eth.c + * @author MCD Application Team + * @version V0.0.1 + * @date 10/21/2010 + * @brief This file provides all the ETH firmware functions for STM32F2xx devices. + * This driver is based on V1.1.0 of "stm32_eth.c" driver, and updated + * to support new feature added in STM32F2xx devices (Enhanced DMA descriptors) + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* + * Change Logs: + * Date Author Notes + * 2011-07-22 aozima first implementation. + * 2012-09-24 aozima update for stm32f4. + * 2012-09-26 aozima add phy monitor. +*/ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_eth.h" +#include "stm32f4xx_rcc.h" + +/* STM32F ETH dirver options */ +#define RMII_MODE /* MII_MODE or RMII_MODE */ +#define RMII_TX_GPIO_GROUP 2 /* 1:GPIOB or 2:GPIOG */ +#define CHECKSUM_BY_HARDWARE + +/** @addtogroup STM32F4XX_ETH_Driver + * @brief ETH driver modules + * @{ + */ + +/** @defgroup ETH_Private_TypesDefinitions + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Defines + * @{ + */ +/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */ +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; + +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) +/** + * @} + */ + +/** @defgroup ETH_Private_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_Variables + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @defgroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Deinitializes the ETHERNET peripheral registers to their default reset values. + * @param None + * @retval None + */ +void ETH_DeInit(void) +{ + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE); +} + +/** + * @brief Initializes the ETHERNET peripheral according to the specified + * parameters in the ETH_InitStruct . + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains + * the configuration information for the specified ETHERNET peripheral. + * @param PHYAddress: external PHY address + * @retval ETH_ERROR: Ethernet initialization failed + * ETH_SUCCESS: Ethernet successfully initialized + */ +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct) +{ + uint32_t tmpreg = 0; + __IO uint32_t i = 0; + RCC_ClocksTypeDef rcc_clocks; + uint32_t hclk = 60000000; + __IO uint32_t timeout = 0; + /* Check the parameters */ + /* MAC --------------------------*/ + assert_param(IS_ETH_AUTONEGOTIATION(ETH_InitStruct->ETH_AutoNegotiation)); + assert_param(IS_ETH_WATCHDOG(ETH_InitStruct->ETH_Watchdog)); + assert_param(IS_ETH_JABBER(ETH_InitStruct->ETH_Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(ETH_InitStruct->ETH_InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(ETH_InitStruct->ETH_CarrierSense)); + assert_param(IS_ETH_SPEED(ETH_InitStruct->ETH_Speed)); + assert_param(IS_ETH_RECEIVE_OWN(ETH_InitStruct->ETH_ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(ETH_InitStruct->ETH_LoopbackMode)); + assert_param(IS_ETH_DUPLEX_MODE(ETH_InitStruct->ETH_Mode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(ETH_InitStruct->ETH_ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(ETH_InitStruct->ETH_RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(ETH_InitStruct->ETH_AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(ETH_InitStruct->ETH_BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(ETH_InitStruct->ETH_DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(ETH_InitStruct->ETH_ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(ETH_InitStruct->ETH_SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(ETH_InitStruct->ETH_PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(ETH_InitStruct->ETH_BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(ETH_InitStruct->ETH_DestinationAddrFilter)); +// assert_param(IS_ETH_PROMISCIOUS_MODE(ETH_InitStruct->ETH_PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(ETH_InitStruct->ETH_MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(ETH_InitStruct->ETH_UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(ETH_InitStruct->ETH_PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(ETH_InitStruct->ETH_ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(ETH_InitStruct->ETH_PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(ETH_InitStruct->ETH_UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(ETH_InitStruct->ETH_ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(ETH_InitStruct->ETH_TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(ETH_InitStruct->ETH_VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(ETH_InitStruct->ETH_VLANTagIdentifier)); + /* DMA --------------------------*/ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(ETH_InitStruct->ETH_ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(ETH_InitStruct->ETH_FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(ETH_InitStruct->ETH_TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(ETH_InitStruct->ETH_TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(ETH_InitStruct->ETH_ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(ETH_InitStruct->ETH_ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(ETH_InitStruct->ETH_ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(ETH_InitStruct->ETH_SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(ETH_InitStruct->ETH_AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(ETH_InitStruct->ETH_FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(ETH_InitStruct->ETH_RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(ETH_InitStruct->ETH_TxDMABurstLength)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(ETH_InitStruct->ETH_DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(ETH_InitStruct->ETH_DMAArbitration)); + /*-------------------------------- MAC Config ------------------------------*/ + /*---------------------- ETHERNET MACMIIAR Configuration -------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= MACMIIAR_CR_MASK; + /* Get hclk frequency value */ + RCC_GetClocksFreq(&rcc_clocks); + hclk = rcc_clocks.HCLK_Frequency; + + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000)&&(hclk < 35000000)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000)&&(hclk < 60000000)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000)&&(hclk < 100000000)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if((hclk >= 100000000)&&(hclk < 150000000)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */ + { + /* CSR Clock Range between 150-168 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; + } + + /* Write to ETHERNET MAC MIIAR: configure the ETHERNET CSR Clock Range */ + ETH->MACMIIAR = (uint32_t)tmpreg; + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg = ETH->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg &= MACCR_CLEAR_MASK; + /* Set the WD bit according to ETH_Watchdog value */ + /* Set the JD: bit according to ETH_Jabber value */ + /* Set the IFG bit according to ETH_InterFrameGap value */ + /* Set the DCRS bit according to ETH_CarrierSense value */ + /* Set the FES bit according to ETH_Speed value */ + /* Set the DO bit according to ETH_ReceiveOwn value */ + /* Set the LM bit according to ETH_LoopbackMode value */ + /* Set the DM bit according to ETH_Mode value */ + /* Set the IPCO bit according to ETH_ChecksumOffload value */ + /* Set the DR bit according to ETH_RetryTransmission value */ + /* Set the ACS bit according to ETH_AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH_BackOffLimit value */ + /* Set the DC bit according to ETH_DeferralCheck value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_Watchdog | + ETH_InitStruct->ETH_Jabber | + ETH_InitStruct->ETH_InterFrameGap | + ETH_InitStruct->ETH_CarrierSense | + ETH_InitStruct->ETH_Speed | + ETH_InitStruct->ETH_ReceiveOwn | + ETH_InitStruct->ETH_LoopbackMode | + ETH_InitStruct->ETH_Mode | + ETH_InitStruct->ETH_ChecksumOffload | + ETH_InitStruct->ETH_RetryTransmission | + ETH_InitStruct->ETH_AutomaticPadCRCStrip | + ETH_InitStruct->ETH_BackOffLimit | + ETH_InitStruct->ETH_DeferralCheck); + /* Write to ETHERNET MACCR */ + ETH->MACCR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH_ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH_SourceAddrFilter value */ + /* Set the PCF bit according to ETH_PassControlFrames value */ + /* Set the DBF bit according to ETH_BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH_DestinationAddrFilter value */ + /* Set the PR bit according to ETH_PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH_MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH_UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + ETH->MACFFR = (uint32_t)(ETH_InitStruct->ETH_ReceiveAll | + ETH_InitStruct->ETH_SourceAddrFilter | + ETH_InitStruct->ETH_PassControlFrames | + ETH_InitStruct->ETH_BroadcastFramesReception | + ETH_InitStruct->ETH_DestinationAddrFilter | + ETH_InitStruct->ETH_PromiscuousMode | + ETH_InitStruct->ETH_MulticastFramesFilter | + ETH_InitStruct->ETH_UnicastFramesFilter); + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + ETH->MACHTHR = (uint32_t)ETH_InitStruct->ETH_HashTableHigh; + /* Write to ETHERNET MACHTLR */ + ETH->MACHTLR = (uint32_t)ETH_InitStruct->ETH_HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + /* Get the ETHERNET MACFCR value */ + tmpreg = ETH->MACFCR; + /* Clear xx bits */ + tmpreg &= MACFCR_CLEAR_MASK; + + /* Set the PT bit according to ETH_PauseTime value */ + /* Set the DZPQ bit according to ETH_ZeroQuantaPause value */ + /* Set the PLT bit according to ETH_PauseLowThreshold value */ + /* Set the UP bit according to ETH_UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH_ReceiveFlowControl value */ + /* Set the TFE bit according to ETH_TransmitFlowControl value */ + tmpreg |= (uint32_t)((ETH_InitStruct->ETH_PauseTime << 16) | + ETH_InitStruct->ETH_ZeroQuantaPause | + ETH_InitStruct->ETH_PauseLowThreshold | + ETH_InitStruct->ETH_UnicastPauseFrameDetect | + ETH_InitStruct->ETH_ReceiveFlowControl | + ETH_InitStruct->ETH_TransmitFlowControl); + /* Write to ETHERNET MACFCR */ + ETH->MACFCR = (uint32_t)tmpreg; + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + /* Set the ETV bit according to ETH_VLANTagComparison value */ + /* Set the VL bit according to ETH_VLANTagIdentifier value */ + ETH->MACVLANTR = (uint32_t)(ETH_InitStruct->ETH_VLANTagComparison | + ETH_InitStruct->ETH_VLANTagIdentifier); + + /*-------------------------------- DMA Config ------------------------------*/ + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg = ETH->DMAOMR; + /* Clear xx bits */ + tmpreg &= DMAOMR_CLEAR_MASK; + + /* Set the DT bit according to ETH_DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH_ReceiveStoreForward value */ + /* Set the DFF bit according to ETH_FlushReceivedFrame value */ + /* Set the TSF bit according to ETH_TransmitStoreForward value */ + /* Set the TTC bit according to ETH_TransmitThresholdControl value */ + /* Set the FEF bit according to ETH_ForwardErrorFrames value */ + /* Set the FUF bit according to ETH_ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH_ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH_SecondFrameOperate value */ + tmpreg |= (uint32_t)(ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame | + ETH_InitStruct->ETH_ReceiveStoreForward | + ETH_InitStruct->ETH_FlushReceivedFrame | + ETH_InitStruct->ETH_TransmitStoreForward | + ETH_InitStruct->ETH_TransmitThresholdControl | + ETH_InitStruct->ETH_ForwardErrorFrames | + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames | + ETH_InitStruct->ETH_ReceiveThresholdControl | + ETH_InitStruct->ETH_SecondFrameOperate); + /* Write to ETHERNET DMAOMR */ + ETH->DMAOMR = (uint32_t)tmpreg; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + /* Set the AAL bit according to ETH_AddressAlignedBeats value */ + /* Set the FB bit according to ETH_FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH_RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH_TxDMABurstLength value */ + /* Set the DSL bit according to ETH_DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH_DMAArbitration value */ + ETH->DMABMR = (uint32_t)(ETH_InitStruct->ETH_AddressAlignedBeats | + ETH_InitStruct->ETH_FixedBurst | + ETH_InitStruct->ETH_RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + ETH_InitStruct->ETH_TxDMABurstLength | + (ETH_InitStruct->ETH_DescriptorSkipLength << 2) | + ETH_InitStruct->ETH_DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + #ifdef USE_ENHANCED_DMA_DESCRIPTORS + /* Enable the Enhanced DMA descriptors */ + ETH->DMABMR |= ETH_DMABMR_EDE; + #endif /* USE_ENHANCED_DMA_DESCRIPTORS */ + + /* Return Ethernet configuration success */ + return ETH_SUCCESS; +} + +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct) +{ + /* ETH_InitStruct members default value */ + /*------------------------ MAC Configuration ---------------------------*/ + + /* PHY Auto-negotiation enabled */ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; + /* MAC watchdog enabled: cuts-off long frame */ + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + /* MAC Jabber enabled in Half-duplex mode */ + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + /* Ethernet interframe gap set to 96 bits */ + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + /* Carrier Sense Enabled in Half-Duplex mode */ + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + /* PHY speed configured to 100Mbit/s */ + ETH_InitStruct->ETH_Speed = ETH_Speed_100M; + /* Receive own Frames in Half-Duplex mode enabled */ + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + /* MAC MII loopback disabled */ + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + /* Full-Duplex mode selected */ + ETH_InitStruct->ETH_Mode = ETH_Mode_FullDuplex; + /* IPv4 and TCP/UDP/ICMP frame Checksum Offload disabled */ + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + /* Retry Transmission enabled for half-duplex mode */ + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + /* Automatic PAD/CRC strip disabled*/ + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + /* half-duplex mode retransmission Backoff time_limit = 10 slot times*/ + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + /* half-duplex mode Deferral check disabled */ + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + /* Receive all frames disabled */ + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + /* Source address filtering (on the optional MAC addresses) disabled */ + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + /* Do not forward control frames that do not pass the address filtering */ + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + /* Disable reception of Broadcast frames */ + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + /* Normal Destination address filtering (not reverse addressing) */ + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + /* Promiscuous address filtering mode disabled */ + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + /* Perfect address filtering for multicast addresses */ + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + /* Perfect address filtering for unicast addresses */ + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + /* Initialize hash table high and low regs */ + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + /* Flow control config (flow control disabled)*/ + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + /* VLANtag config (VLAN field not checked) */ + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + + /*---------------------- DMA Configuration -------------------------------*/ + + /* Drops frames with with TCP/IP checksum errors */ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + /* Store and forward mode enabled for receive */ + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + /* Flush received frame that created FIFO overflow */ + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + /* Store and forward mode enabled for transmit */ + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + /* Threshold TXFIFO level set to 64 bytes (used when threshold mode is enabled) */ + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + /* Disable forwarding frames with errors (short frames, CRC,...)*/ + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + /* Disable undersized good frames */ + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + /* Threshold RXFIFO level set to 64 bytes (used when Cut-through mode is enabled) */ + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + /* Disable Operate on second frame (transmit a second frame to FIFO without + waiting status of previous frame*/ + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + /* DMA works on 32-bit aligned start source and destinations addresses */ + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + /* Enabled Fixed Burst Mode (mix of INC4, INC8, INC16 and SINGLE DMA transactions */ + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Enable; + /* DMA transfer max burst length = 32 beats = 32 x 32bits */ + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + /* DMA Ring mode skip length = 0 */ + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + /* Equal priority (round-robin) between transmit and receive DMA engines */ + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/** + * @brief Enables ENET MAC and DMA reception/transmission + * @param None + * @retval None + */ +void ETH_Start(void) +{ + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionCmd(ENABLE); + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(); + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionCmd(ENABLE); + + /* Start DMA transmission */ + ETH_DMATransmissionCmd(ENABLE); + /* Start DMA reception */ + ETH_DMAReceptionCmd(ENABLE); +} + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * @param ppkt: pointer to the application's packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @retval ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt. + * @param ppkt: pointer to the application packet receive buffer. + * @retval ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); +} + +/** + * @brief Get the size of received the received packet. + * @param None + * @retval framelength: received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the size of the packet: including 4 bytes of the CRC */ + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + /* Return Frame Length */ + return frameLength; +} + +/** + * @brief Drop a Received packet (too small packet, etc...) + * @param None + * @retval None + */ +void ETH_DropRxPkt(void) +{ + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer read: this will + be the first Rx descriptor in this case */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +#ifdef USE_ENHANCED_DMA_DESCRIPTORS +/** + * @brief Enables or disables the Enhanced descriptor structure. + * @param NewState: new state of the Enhanced descriptor structure. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_EnhancedDescriptorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable enhanced descriptor structure */ + ETH->DMABMR |= ETH_DMABMR_EDE; + } + else + { + /* Disable enhanced descriptor structure */ + ETH->DMABMR &= ~ETH_DMABMR_EDE; + } +} +#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ +/*--------------------------------- PHY ------------------------------------*/ +/** + * @brief Read a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR: Tranceiver Basic Control Register + * @arg PHY_BSR: Tranceiver Basic Status Register + * @arg PHY_SR : Tranceiver Status Register + * @arg More PHY register could be read depending on the used PHY + * @retval ETH_ERROR: in case of timeout + * MAC MIIDR register value: Data read from the selected PHY register (correct read ) + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; +__IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_MASK; + /* Prepare the MII address register value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + /* Return data register value */ + return (uint16_t)(ETH->MACMIIDR); +} + +/** + * @brief Write to a PHY register + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: 0,..,31 + * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * @arg PHY_BCR : Tranceiver Control Register + * @arg More PHY register could be written depending on the used PHY + * @param PHYValue: the value to write + * @retval ETH_ERROR: in case of timeout + * ETH_SUCCESS: for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_ETH_PHY_REG(PHYReg)); + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = ETH->MACMIIAR; + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg &= ~MACMIIAR_CR_MASK; + /* Prepare the MII register address value */ + tmpreg |=(((uint32_t)PHYAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + /* Give the value to the MII data register */ + ETH->MACMIIDR = PHYValue; + /* Write the result value into the MII Address register */ + ETH->MACMIIAR = tmpreg; + /* Check for the Busy flag */ + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while ((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + /* Return ERROR in case of timeout */ + if(timeout == PHY_WRITE_TO) + { + return ETH_ERROR; + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Enables or disables the PHY loopBack mode. + * @Note: Don't be confused with ETH_MACLoopBackCmd function which enables internal + * loopback at MII level + * @param PHYAddress: PHY device address, is the index of one of supported 32 PHY devices. + * This parameter can be one of the following values: + * @param NewState: new state of the PHY loopBack mode. + * This parameter can be: ENABLE or DISABLE. + * @retval ETH_ERROR: in case of bad PHY configuration + * ETH_SUCCESS: for correct PHY configuration + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ETH_PHY_ADDRESS(PHYAddress)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the PHY configuration to update it */ + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if (NewState != DISABLE) + { + /* Enable the PHY loopback mode */ + tmpreg |= PHY_Loopback; + } + else + { + /* Disable the PHY loopback mode: normal mode */ + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + /* Update the PHY control register with the new configuration */ + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + /* Return SUCCESS */ + return ETH_ERROR; + } +} + +/*--------------------------------- MAC ------------------------------------*/ +/** + * @brief Enables or disables the MAC transmission. + * @param NewState: new state of the MAC transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC transmission */ + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + /* Disable the MAC transmission */ + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/** + * @brief Enables or disables the MAC reception. + * @param NewState: new state of the MAC reception. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC reception */ + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + /* Disable the MAC reception */ + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @param None + * @retval The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + /* The Flow Control register should not be written to until this bit is cleared */ + if ((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param None + * @retval None + */ +void ETH_InitiatePauseControlFrame(void) +{ + /* When Set In full duplex MAC initiates pause control frame */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/** + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * @param NewState: new state of the MAC BackPressure operation activation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Activate the MAC BackPressure operation */ + /* In Half duplex: during backpressure, when the MAC receives a new frame, + the transmitter starts sending a JAM pattern resulting in a collision */ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + /* Desactivate the MAC BackPressure operation */ + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param ETH_MAC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_FLAG(ETH_MAC_FLAG)); + if ((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * @param ETH_MAC_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_MMCT : MMC transmit interrupt + * @arg ETH_MAC_IT_MMCR : MMC receive interrupt + * @arg ETH_MAC_IT_MMC : MMC interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MAC_GET_IT(ETH_MAC_IT)); + if ((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * @param ETH_MAC_IT: specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @param NewState: new state of the specified ETHERNET MAC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_IT(ETH_MAC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC interrupts */ + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + /* Disable the selected ETHERNET MAC interrupts */ + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/** + * @brief configures the selected MAC address. + * @param MacAddr: The MAC addres to configure. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval None + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selectecd MAC address high register */ + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + /* Load the selectecd MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; + /* Calculate the selectecd MAC address low register */ + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + /* Load the selectecd MAC address low register */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; +} + +/** + * @brief Get the selected MAC address. + * @param MacAddr: The MAC addres to return. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0 : MAC Address0 + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Addr: Pointer on MAC address buffer data (6 bytes). + * @retval None + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Get the selectecd MAC address high register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)); + + /* Calculate the selectecd MAC address buffer */ + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + /* Load the selectecd MAC address low register */ + tmpreg =(*(__IO uint32_t *) (ETH_MAC_ADDR_LBASE + MacAddr)); + /* Calculate the selectecd MAC address buffer */ + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8 ) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/** + * @brief Enables or disables the Address filter module uses the specified + * ETHERNET MAC address for perfect filtering + * @param MacAddr: specifies the ETHERNET MAC address to be used for prfect filtering. + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param NewState: new state of the specified ETHERNET MAC address use. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + /* Disable the selected ETHERNET MAC address for perfect filtering */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_AE); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param Filter: specifies the used frame received field for comparaison + * This parameter can be one of the following values: + * @arg ETH_MAC_AddressFilter_SA : MAC Address is used to compare with the + * SA fields of the received frame. + * @arg ETH_MAC_AddressFilter_DA : MAC Address is used to compare with the + * DA fields of the received frame. + * @retval None + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_FILTER(Filter)); + + if (Filter != ETH_MAC_AddressFilter_DA) + { + /* The selected ETHERNET MAC address is used to compare with the SA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + /* The selected ETHERNET MAC address is used to compare with the DA fields of the + received frame. */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_SA); + } +} + +/** + * @brief Set the filter type for the specified ETHERNET MAC address + * @param MacAddr: specifies the ETHERNET MAC address + * This parameter can be one of the following values: + * @arg ETH_MAC_Address1 : MAC Address1 + * @arg ETH_MAC_Address2 : MAC Address2 + * @arg ETH_MAC_Address3 : MAC Address3 + * @param MaskByte: specifies the used address bytes for comparaison + * This parameter can be any combination of the following values: + * @arg ETH_MAC_AddressMask_Byte6 : Mask MAC Address high reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte5 : Mask MAC Address high reg bits [7:0]. + * @arg ETH_MAC_AddressMask_Byte4 : Mask MAC Address low reg bits [31:24]. + * @arg ETH_MAC_AddressMask_Byte3 : Mask MAC Address low reg bits [23:16]. + * @arg ETH_MAC_AddressMask_Byte2 : Mask MAC Address low reg bits [15:8]. + * @arg ETH_MAC_AddressMask_Byte1 : Mask MAC Address low reg bits [7:0]. + * @retval None + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS123(MacAddr)); + assert_param(IS_ETH_MAC_ADDRESS_MASK(MaskByte)); + + /* Clear MBC bits in the selected MAC address high register */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) &=(~(uint32_t)ETH_MACA1HR_MBC); + /* Set the selected Filetr mask bytes */ + (*(__IO uint32_t *) (ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; +} +/*------------------------ DMA Tx/Rx Desciptors -----------------------------*/ + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval None + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Second Address Chained bit */ + DMATxDesc->Status = ETH_DMATxDesc_TCH; + + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Initializes the DMA Tx descriptors in ring mode. + * @param DMATxDescTab: Pointer on the first Tx desc list + * @param TxBuff1: Pointer on the first TxBuffer1 list + * @param TxBuff2: Pointer on the first TxBuffer2 list + * @param TxBuffCount: Number of the used Tx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval None + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + DMATxDescToSet = DMATxDescTab; + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMATxDesc = DMATxDescTab + i; + /* Set Buffer1 address pointer */ + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Transmit End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (TxBuffCount-1)) + { + /* Set Transmit End of Ring bit */ + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMATxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param ETH_DMATxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_OWN : OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMATxDesc_IC : Interrupt on completetion + * @arg ETH_DMATxDesc_LS : Last Segment + * @arg ETH_DMATxDesc_FS : First Segment + * @arg ETH_DMATxDesc_DC : Disable CRC + * @arg ETH_DMATxDesc_DP : Disable Pad + * @arg ETH_DMATxDesc_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMATxDesc_CIC : Checksum insertion control + * @arg ETH_DMATxDesc_TER : Transmit End of Ring + * @arg ETH_DMATxDesc_TCH : Second Address Chained + * @arg ETH_DMATxDesc_TTSS: Tx Time Stamp Status + * @arg ETH_DMATxDesc_IHE : IP Header Error + * @arg ETH_DMATxDesc_ES : Error summary + * @arg ETH_DMATxDesc_JT : Jabber Timeout + * @arg ETH_DMATxDesc_FF : Frame Flushed: DMA/MTL flushed the frame due to SW flush + * @arg ETH_DMATxDesc_PCE : Payload Checksum Error + * @arg ETH_DMATxDesc_LCA : Loss of Carrier: carrier lost during tramsmission + * @arg ETH_DMATxDesc_NC : No Carrier: no carrier signal from the tranceiver + * @arg ETH_DMATxDesc_LCO : Late Collision: transmission aborted due to collision + * @arg ETH_DMATxDesc_EC : Excessive Collision: transmission aborted after 16 collisions + * @arg ETH_DMATxDesc_VF : VLAN Frame + * @arg ETH_DMATxDesc_CC : Collision Count + * @arg ETH_DMATxDesc_ED : Excessive Deferral + * @arg ETH_DMATxDesc_UF : Underflow Error: late data arrival from the memory + * @arg ETH_DMATxDesc_DB : Deferred Bit + * @retval The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_GET_FLAG(ETH_DMATxDescFlag)); + + if ((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @retval The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param DMATxDesc: Pointer on a Tx desc + * @retval None + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + /* Set the DMA Tx Desc Own bit */ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param NewState: new state of the DMA Tx Desc transmit interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + /* Disable the DMA Tx Desc Transmit interrupt */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/** + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * @param DMATxDesc: Pointer on a Tx desc + * @param DMATxDesc_FrameSegment: specifies is the actual Tx desc contain last or first segment. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_LastSegment : actual Tx desc contain last segment + * @arg ETH_DMATxDesc_FirstSegment : actual Tx desc contain first segment + * @retval None + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_SEGMENT(DMATxDesc_FrameSegment)); + + /* Selects the DMA Tx Desc Frame segment */ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param DMATxDesc_Checksum: specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATxDesc_ChecksumByPass : Checksum bypass + * @arg ETH_DMATxDesc_ChecksumIPV4Header : IPv4 header checksum + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPSegment : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATxDesc_ChecksumTCPUDPICMPFull : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval None + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_TXDESC_CHECKSUM(DMATxDesc_Checksum)); + + /* Set the selected DMA Tx desc checksum insertion control */ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/** + * @brief Enables or disables the DMA Tx Desc CRC. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc CRC. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc CRC */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + /* Disable the selected DMA Tx Desc CRC */ + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc end of ring. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + /* Disable the selected DMA Tx Desc end of ring */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc second address chained. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + /* Disable the selected DMA Tx Desc second address chained */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/** + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc padding for frame shorter than 64 bytes */ + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + /* Disable the selected DMA Tx Desc padding for frame shorter than 64 bytes*/ + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/** + * @brief Enables or disables the DMA Tx Desc time stamp. + * @param DMATxDesc: pointer on a DMA Tx descriptor + * @param NewState: new state of the specified DMA Tx Desc time stamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + /* Disable the selected DMA Tx Desc time stamp */ + DMATxDesc->Status &=(~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/** + * @brief configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * @param DMATxDesc: Pointer on a Tx desc + * @param BufferSize1: specifies the Tx desc buffer1 size. + * @param BufferSize2: specifies the Tx desc buffer2 size (put "0" if not used). + * @retval None + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize1)); + assert_param(IS_ETH_DMATxDESC_BUFFER_SIZE(BufferSize2)); + + /* Set the DMA Tx Desc buffer1 and buffer2 sizes values */ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval None + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in ring mode. + * @param DMARxDescTab: Pointer on the first Rx desc list + * @param RxBuff1: Pointer on the first RxBuffer1 list + * @param RxBuff2: Pointer on the first RxBuffer2 list + * @param RxBuffCount: Number of the used Rx desc in the list + * Note: see decriptor skip length defined in ETH_DMA_InitStruct + * for the number of Words to skip between two unchained descriptors. + * @retval None + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + /* Set the DMARxDescToGet pointer with the first one of the DMARxDescTab list */ + DMARxDescToGet = DMARxDescTab; + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARxDesc_OWN; + /* Set Buffer1 size */ + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i*ETH_MAX_PACKET_SIZE]); + + /* Set Buffer2 address pointer */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i*ETH_MAX_PACKET_SIZE]); + + /* Set Receive End of Ring bit for last descriptor: The DMA returns to the base + address of the list, creating a Desciptor Ring */ + if(i == (RxBuffCount-1)) + { + /* Set Receive End of Ring bit */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMARxDescTab; +} + +/** + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param ETH_DMARxDescFlag: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMARxDesc_OWN: OWN bit: descriptor is owned by DMA engine + * @arg ETH_DMARxDesc_AFM: DA Filter Fail for the rx frame + * @arg ETH_DMARxDesc_ES: Error summary + * @arg ETH_DMARxDesc_DE: Desciptor error: no more descriptors for receive frame + * @arg ETH_DMARxDesc_SAF: SA Filter Fail for the received frame + * @arg ETH_DMARxDesc_LE: Frame size not matching with length field + * @arg ETH_DMARxDesc_OE: Overflow Error: Frame was damaged due to buffer overflow + * @arg ETH_DMARxDesc_VLAN: VLAN Tag: received frame is a VLAN frame + * @arg ETH_DMARxDesc_FS: First descriptor of the frame + * @arg ETH_DMARxDesc_LS: Last descriptor of the frame + * @arg ETH_DMARxDesc_IPV4HCE: IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * @arg ETH_DMARxDesc_LC: Late collision occurred during reception + * @arg ETH_DMARxDesc_FT: Frame type - Ethernet, otherwise 802.3 + * @arg ETH_DMARxDesc_RWT: Receive Watchdog Timeout: watchdog timer expired during reception + * @arg ETH_DMARxDesc_RE: Receive error: error reported by MII interface + * @arg ETH_DMARxDesc_DE: Dribble bit error: frame contains non int multiple of 8 bits + * @arg ETH_DMARxDesc_CE: CRC error + * @arg ETH_DMARxDesc_MAMPCE: Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * @retval The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMARxDESC_GET_FLAG(ETH_DMARxDescFlag)); + if ((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +#ifdef USE_ENHANCED_DMA_DESCRIPTORS +/** + * @brief Checks whether the specified ETHERNET PTP Rx Desc extended flag is set or not. + * @param DMAPTPRxDesc: pointer on a DMA PTP Rx descriptor + * @param ETH_DMAPTPRxDescFlag: specifies the extended flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMAPTPRxDesc_PTPV: PTP version + * @arg ETH_DMAPTPRxDesc_PTPFT: PTP frame type + * @arg ETH_DMAPTPRxDesc_PTPMT: PTP message type + * @arg ETH_DMAPTPRxDesc_IPV6PR: IPv6 packet received + * @arg ETH_DMAPTPRxDesc_IPV4PR: IPv4 packet received + * @arg ETH_DMAPTPRxDesc_IPCB: IP checksum bypassed + * @arg ETH_DMAPTPRxDesc_IPPE: IP payload error + * @arg ETH_DMAPTPRxDesc_IPHE: IP header error + * @arg ETH_DMAPTPRxDesc_IPPT: IP payload type + * @retval The new state of ETH_DMAPTPRxDescExtendedFlag (SET or RESET). + */ +FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(ETH_DMAPTPRxDescExtendedFlag)); + + if ((DMAPTPRxDesc->ExtendedStatus & ETH_DMAPTPRxDescExtendedFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} +#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param DMARxDesc: Pointer on a Rx desc + * @retval None + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Set the DMA Rx Desc Own bit */ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/** + * @brief Returns the specified DMA Rx Desc frame length. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @retval The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + /* Return the Receive descriptor frame length */ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/** + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * @param DMARxDesc: Pointer on a Rx desc + * @param NewState: new state of the specified DMA Rx Desc interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + /* Disable the DMA Rx Desc receive interrupt */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/** + * @brief Enables or disables the DMA Rx Desc end of ring. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc end of ring. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + /* Disable the selected DMA Rx Desc end of ring */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/** + * @brief Enables or disables the DMA Rx Desc second address chained. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param NewState: new state of the specified DMA Rx Desc second address chained. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + /* Disable the selected DMA Rx Desc second address chained */ + DMARxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/** + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * @param DMARxDesc: pointer on a DMA Rx descriptor + * @param DMARxDesc_Buffer: specifies the DMA Rx Desc buffer. + * This parameter can be any one of the following values: + * @arg ETH_DMARxDesc_Buffer1 : DMA Rx Desc Buffer1 + * @arg ETH_DMARxDesc_Buffer2 : DMA Rx Desc Buffer2 + * @retval The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_RXDESC_BUFFER(DMARxDesc_Buffer)); + + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + /* Return the DMA Rx Desc buffer2 size */ + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } + else + { + /* Return the DMA Rx Desc buffer1 size */ + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/*--------------------------------- DMA ------------------------------------*/ +/** + * @brief Resets all MAC subsystem internal registers and logic. + * @param None + * @retval None + */ +void ETH_SoftwareReset(void) +{ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/** + * @brief Checks whether the ETHERNET software reset bit is set or not. + * @param None + * @retval The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param ETH_DMA_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_FLAG_TST : Time-stamp trigger flag + * @arg ETH_DMA_FLAG_PMT : PMT flag + * @arg ETH_DMA_FLAG_MMC : MMC flag + * @arg ETH_DMA_FLAG_DataTransferError : Error bits 0-data buffer, 1-desc. access + * @arg ETH_DMA_FLAG_ReadWriteError : Error bits 0-write trnsf, 1-read transfr + * @arg ETH_DMA_FLAG_AccessError : Error bits 0-Rx DMA, 1-Tx DMA + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ET : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Underflow flag + * @arg ETH_DMA_FLAG_RO : Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_FLAG)); + if ((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET¡¯s DMA pending flag. + * @param ETH_DMA_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_FLAG_NIS : Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS : Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ER : Early receive flag + * @arg ETH_DMA_FLAG_FBE : Fatal bus error flag + * @arg ETH_DMA_FLAG_ETI : Early transmit flag + * @arg ETH_DMA_FLAG_RWT : Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RPS : Receive process stopped flag + * @arg ETH_DMA_FLAG_RBU : Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_R : Receive flag + * @arg ETH_DMA_FLAG_TU : Transmit Underflow flag + * @arg ETH_DMA_FLAG_RO : Receive Overflow flag + * @arg ETH_DMA_FLAG_TJT : Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TBU : Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TPS : Transmit process stopped flag + * @arg ETH_DMA_FLAG_T : Transmit flag + * @retval None + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_FLAG(ETH_DMA_FLAG)); + + /* Clear the selected ETHERNET DMA FLAG */ + ETH->DMASR = (uint32_t) ETH_DMA_FLAG; +} + +/** + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * @param ETH_DMA_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_IT_TST : Time-stamp trigger interrupt + * @arg ETH_DMA_IT_PMT : PMT interrupt + * @arg ETH_DMA_IT_MMC : MMC interrupt + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_IT(ETH_DMA_IT)); + if ((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the ETHERNET¡¯s DMA IT pending bit. + * @param ETH_DMA_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ETI : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Transmit Underflow interrupt + * @arg ETH_DMA_IT_RO : Receive Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @retval None + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + + /* Clear the selected ETHERNET DMA IT */ + ETH->DMASR = (uint32_t) ETH_DMA_IT; +} + +/** + * @brief Returns the ETHERNET DMA Transmit Process State. + * @param None + * @retval The new ETHERNET DMA Transmit Process State: + * This can be one of the following values: + * - ETH_DMA_TransmitProcess_Stopped : Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TransmitProcess_Fetching : Running - fetching the Tx descriptor + * - ETH_DMA_TransmitProcess_Waiting : Running - waiting for status + * - ETH_DMA_TransmitProcess_Reading : unning - reading the data from host memory + * - ETH_DMA_TransmitProcess_Suspended : Suspended - Tx Desciptor unavailabe + * - ETH_DMA_TransmitProcess_Closing : Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/** + * @brief Returns the ETHERNET DMA Receive Process State. + * @param None + * @retval The new ETHERNET DMA Receive Process State: + * This can be one of the following values: + * - ETH_DMA_ReceiveProcess_Stopped : Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_ReceiveProcess_Fetching : Running - fetching the Rx descriptor + * - ETH_DMA_ReceiveProcess_Waiting : Running - waiting for packet + * - ETH_DMA_ReceiveProcess_Suspended : Suspended - Rx Desciptor unavailable + * - ETH_DMA_ReceiveProcess_Closing : Running - closing descriptor + * - ETH_DMA_ReceiveProcess_Queuing : Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param None + * @retval None + */ +void ETH_FlushTransmitFIFO(void) +{ + /* Set the Flush Transmit FIFO bit */ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/** + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * @param None + * @retval The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if ((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the DMA transmission. + * @param NewState: new state of the DMA transmission. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA transmission */ + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + /* Disable the DMA transmission */ + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/** + * @brief Enables or disables the DMA reception. + * @param NewState: new state of the DMA reception. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA reception */ + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + /* Disable the DMA reception */ + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/** + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * @param ETH_DMA_IT: specifies the ETHERNET DMA interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_DMA_IT_NIS : Normal interrupt summary + * @arg ETH_DMA_IT_AIS : Abnormal interrupt summary + * @arg ETH_DMA_IT_ER : Early receive interrupt + * @arg ETH_DMA_IT_FBE : Fatal bus error interrupt + * @arg ETH_DMA_IT_ET : Early transmit interrupt + * @arg ETH_DMA_IT_RWT : Receive watchdog timeout interrupt + * @arg ETH_DMA_IT_RPS : Receive process stopped interrupt + * @arg ETH_DMA_IT_RBU : Receive buffer unavailable interrupt + * @arg ETH_DMA_IT_R : Receive interrupt + * @arg ETH_DMA_IT_TU : Underflow interrupt + * @arg ETH_DMA_IT_RO : Overflow interrupt + * @arg ETH_DMA_IT_TJT : Transmit jabber timeout interrupt + * @arg ETH_DMA_IT_TBU : Transmit buffer unavailable interrupt + * @arg ETH_DMA_IT_TPS : Transmit process stopped interrupt + * @arg ETH_DMA_IT_T : Transmit interrupt + * @param NewState: new state of the specified ETHERNET DMA interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_DMA_IT(ETH_DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET DMA interrupts */ + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + /* Disable the selected ETHERNET DMA interrupts */ + ETH->DMAIER &=(~(uint32_t)ETH_DMA_IT); + } +} + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param ETH_DMA_Overflow: specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_Overflow_RxFIFOCounter : Overflow for FIFO Overflow Counter + * @arg ETH_DMA_Overflow_MissedFrameCounter : Overflow for Missed Frame Counter + * @retval The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_DMA_GET_OVERFLOW(ETH_DMA_Overflow)); + + if ((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * @param None + * @retval The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA)>>ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); +} + +/** + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * @param None + * @retval The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/** + * @brief Get the ETHERNET DMA DMACHTDR register value. + * @param None + * @retval The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRDR register value. + * @param None + * @retval The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * @param None + * @retval The value of the current Tx buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHTBAR)); +} + +/** + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * @param None + * @retval The value of the current Rx buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * (the data written could be anything). This forces the DMA to resume transmission. + * @param None + * @retval None. + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/** + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register + * (the data written could be anything). This forces the DMA to resume reception. + * @param None + * @retval None. + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/** + * @brief Set the DMA Receive status watchdog timer register value + * @param Value: DMA Receive status watchdog timer register value + * @retval None + */ +void ETH_SetReceiveWatchdogTimer(uint8_t Value) +{ + /* Set the DMA Receive status watchdog timer register */ + ETH->DMARSWTR = Value; +} + +/*--------------------------------- PMT ------------------------------------*/ +/** + * @brief Reset Wakeup frame filter register pointer. + * @param None + * @retval None + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + /* Resets the Remote Wake-up Frame Filter register pointer to 0x0000 */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/** + * @brief Populates the remote wakeup frame registers. + * @param Buffer: Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + * @retval None + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + /* Fill Remote Wake-up Frame Filter register with Buffer data */ + for(i =0; iMACRWUFFR = Buffer[i]; + } +} + +/** + * @brief Enables or disables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param NewState: new state of the MAC Global Unicast Wake-Up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + /* Disable the MAC Global Unicast Wake-Up */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param ETH_PMT_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Poniter Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_PMT_GET_FLAG(ETH_PMT_FLAG)); + + if ((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * @param NewState: new state of the MAC Wake-Up Frame Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + /* Disable the MAC Wake-Up Frame Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/** + * @brief Enables or disables the MAC Magic Packet Detection. + * @param NewState: new state of the MAC Magic Packet Detection. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Magic Packet Detection */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + /* Disable the MAC Magic Packet Detection */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/** + * @brief Enables or disables the MAC Power Down. + * @param NewState: new state of the MAC Power Down. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MAC Power Down */ + /* This puts the MAC in power down mode */ + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + /* Disable the MAC Power Down */ + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/*--------------------------------- MMC ------------------------------------*/ +/** + * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) + * @param None + * @retval None + */ +void ETH_MMCCounterFullPreset(void) +{ + /* Preset and Initialize the MMC counters to almost-full value */ + ETH->MMCCR |= ETH_MMCCR_MCFHP | ETH_MMCCR_MCP; +} + +/** + * @brief Preset and Initialize the MMC counters to almost-hal value: 0x7FFF_FFF0 (half - 16). + * @param None + * @retval None + */ +void ETH_MMCCounterHalfPreset(void) +{ + /* Preset the MMC counters to almost-full value */ + ETH->MMCCR &= ~ETH_MMCCR_MCFHP; + /* Initialize the MMC counters to almost-half value */ + ETH->MMCCR |= ETH_MMCCR_MCP; +} + +/** + * @brief Enables or disables the MMC Counter Freeze. + * @param NewState: new state of the MMC Counter Freeze. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter Freeze */ + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + /* Disable the MMC Counter Freeze */ + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/** + * @brief Enables or disables the MMC Reset On Read. + * @param NewState: new state of the MMC Reset On Read. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the MMC Counter reset on read */ + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + /* Disable the MMC Counter reset on read */ + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/** + * @brief Enables or disables the MMC Counter Stop Rollover. + * @param NewState: new state of the MMC Counter Stop Rollover. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable the MMC Counter Stop Rollover */ + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + /* Enable the MMC Counter Stop Rollover */ + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/** + * @brief Resets the MMC Counters. + * @param None + * @retval None + */ +void ETH_MMCCountersReset(void) +{ + /* Resets the MMC Counters */ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/** + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be any combination of Tx interrupt or + * any combination of Rx interrupt (but not both)of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @param NewState: new state of the specified ETHERNET MMC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_IT(ETH_MMC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* Remove register mak from IT */ + ETH_MMC_IT &= 0xEFFFFFFF; + + /* ETHERNET MMC Rx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + if (NewState != DISABLE) + { + /* Enable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR &=(~(uint32_t)ETH_MMC_IT); + } + else + { + /* Disable the selected ETHERNET MMC interrupts */ + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/** + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * @param ETH_MMC_IT: specifies the ETHERNET MMC interrupt. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TxFCGC: When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TxMCGC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TxSCGC: When Tx good single col counter reaches half the maximum value + * @arg ETH_MMC_IT_RxUGFC: When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RxAEC : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RxCEC : When Rx crc error counter reaches half the maximum value + * @retval The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_ETH_MMC_GET_IT(ETH_MMC_IT)); + + if ((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + /* ETHERNET MMC Rx interrupts selected */ + /* Check if the ETHERNET MMC Rx selected interrupt is enabled and occured */ + if ((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) == (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* ETHERNET MMC Tx interrupts selected */ + /* Check if the ETHERNET MMC Tx selected interrupt is enabled and occured */ + if ((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCTIMR & ETH_MMC_IT) == (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Get the specified ETHERNET MMC register value. + * @param ETH_MMCReg: specifies the ETHERNET MMC register. + * This parameter can be one of the following values: + * @arg ETH_MMCCR : MMC CR register + * @arg ETH_MMCRIR : MMC RIR register + * @arg ETH_MMCTIR : MMC TIR register + * @arg ETH_MMCRIMR : MMC RIMR register + * @arg ETH_MMCTIMR : MMC TIMR register + * @arg ETH_MMCTGFSCCR : MMC TGFSCCR register + * @arg ETH_MMCTGFMSCCR: MMC TGFMSCCR register + * @arg ETH_MMCTGFCR : MMC TGFCR register + * @arg ETH_MMCRFCECR : MMC RFCECR register + * @arg ETH_MMCRFAECR : MMC RFAECR register + * @arg ETH_MMCRGUFCR : MMC RGUFCRregister + * @retval The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_MMC_REGISTER(ETH_MMCReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} +/*--------------------------------- PTP ------------------------------------*/ +/** + * @brief Sets the PTP node clock type. + * @param ClockType: specifies the PTP node clock type. + * This parameter can be one of the following values: + * @arg ETH_PTP_OrdinaryClock : Ordinary Clock. + * @arg ETH_PTP_BoundaryClock : Boundary Clock. + * @arg ETH_PTP_EndToEndTransparentClock : End To End Transparent Clock. + * @arg ETH_PTP_PeerToPeerTransparentClock : Peer To Peer Transparent Clock. + * @retval None + */ +void ETH_PTPNodeClockTypeConfig(uint32_t ClockType) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_TYPE_CLOCK(ClockType)); + + /* Clear the PTP node clock type */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSCNT); + + /* Set the new PTP node clock type */ + ETH->PTPTSCR |= ClockType; +} + +/** + * @brief Enables or disables the selected PTP snapshot method. + * @param SnapshotMethod: specifies the PTP snapshot method. + * This parameter can be one of the following values: + * @arg ETH_PTP_SnapshotMasterMessage : snapshot for message relevant to master. + * @arg ETH_PTP_SnapshotEventMessage : snapshot for event message. + * @arg ETH_PTP_SnapshotIPV4Frames : snapshot for IPv4 frames. + * @arg ETH_PTP_SnapshotIPV6Frames : snapshot for IPv6 frames. + * @arg ETH_PTP_SnapshotPTPOverEthernetFrames : snapshot for PTP over ethernet frames. + * @arg ETH_PTP_SnapshotAllReceivedFrames : snapshot for all received frames. + * @param NewState: new state of the PTP snapshot method + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_PTPSnapshotCmd(uint32_t SnapshotMethod, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_SNAPSHOT(SnapshotMethod)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected PTP snapshot method */ + ETH->PTPTSCR |= SnapshotMethod; + } + else + { + /* Disable the selected PTP snapshot method */ + ETH->PTPTSCR &= (~(uint32_t)SnapshotMethod); + } +} + +/** + * @brief Enables or disables the PTP packet snooping version 2 format. + * @param NewState: new state of the PTP packet snooping version 2 format + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_PTPPacketSnoopingV2FormatCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP packet snooping version 2 format */ + ETH->PTPTSCR |= ETH_PTPTSSR_TSPTPPSV2E; + } + else + { + /* Disable the PTP packet snooping version 2 format */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSSR_TSPTPPSV2E); + } +} + +/** + * @brief Enables or disables the PTP Subsecond rollover. + * @param NewState: new state of the PTP Subsecond rollover + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_PTPSubSecondRolloverCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP Subsecond rollover */ + ETH->PTPTSCR |= ETH_PTPTSSR_TSSSR; + } + else + { + /* Disable the PTP Subsecond rollover */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSSR_TSSSR); + } +} + +/** + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. + * @param None + * @retval None + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + /* Enable the PTP block update with the Time Stamp Addend register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/** + * @brief Enable the PTP Time Stamp interrupt trigger + * @param None + * @retval None + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + /* Enable the PTP target time interrupt */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/** + * @brief Updated the PTP system time with the Time Stamp Update register value. + * @param None + * @retval None + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + /* Enable the PTP system time update with the Time Stamp Update register value */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/** + * @brief Initialize the PTP Time Stamp + * @param None + * @retval None + */ +void ETH_InitializePTPTimeStamp(void) +{ + /* Initialize the PTP Time Stamp */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/** + * @brief Selects the PTP Update method + * @param UpdateMethod: the PTP Update method + * This parameter can be one of the following values: + * @arg ETH_PTP_FineUpdate : Fine Update method + * @arg ETH_PTP_CoarseUpdate : Coarse Update method + * @retval None + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_UPDATE(UpdateMethod)); + + if (UpdateMethod != ETH_PTP_CoarseUpdate) + { + /* Enable the PTP Fine Update method */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + /* Disable the PTP Coarse Update method */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/** + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * @param NewState: new state of the PTP time stamp for transmit and receive frames + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + /* Disable the PTP time stamp for transmit and receive frames */ + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/** + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * @param ETH_PTP_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PTP_FLAG_TSARU : Addend Register Update + * @arg ETH_PTP_FLAG_TSITE : Time Stamp Interrupt Trigger Enable + * @arg ETH_PTP_FLAG_TSSTU : Time Stamp Update + * @arg ETH_PTP_FLAG_TSSTI : Time Stamp Initialize + * @retval The new state of ETHERNET PTP Flag (SET or RESET). + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + uint32_t flagpos = 0x0; + FlagStatus bitstatus = RESET; + uint32_t ethernetreg = 0x0; + + /* Check the parameters */ + assert_param(IS_ETH_PTP_GET_FLAG(ETH_PTP_FLAG)); + + /* Get the Flag position */ + flagpos &= 0xEFFFFFFF; + + /* Get the Ethernet register index */ + ethernetreg = (((uint32_t)ETH_PTP_FLAG) & 0x10000000); + + if (ethernetreg != (uint32_t)RESET) /* The flag is in PTPTSCR register */ + { + flagpos &= ETH->PTPTSCR; + } + else /* The IT is in PTPTSSR register */ + { + flagpos &= ETH->PTPTSSR; + } + + if (flagpos != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief Sets the system time Sub-Second Increment value. + * @param SubSecondValue: specifies the PTP Sub-Second Increment Register value. + * @retval None + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_SUBSECOND_INCREMENT(SubSecondValue)); + /* Set the PTP Sub-Second Increment Register */ + ETH->PTPSSIR = SubSecondValue; +} + +/** + * @brief Sets the Time Stamp update sign and values. + * @param Sign: specifies the PTP Time update value sign. + * This parameter can be one of the following values: + * @arg ETH_PTP_PositiveTime : positive time value. + * @arg ETH_PTP_NegativeTime : negative time value. + * @param SecondValue: specifies the PTP Time update second value. + * @param SubSecondValue: specifies the PTP Time update sub-second value. + * This parameter is a 31 bit value, bit32 correspond to the sign. + * @retval None + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_TIME_SIGN(Sign)); + assert_param(IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SubSecondValue)); + /* Set the PTP Time Update High Register */ + ETH->PTPTSHUR = SecondValue; + + /* Set the PTP Time Update Low Register with sign */ + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/** + * @brief Sets the Time Stamp Addend value. + * @param Value: specifies the PTP Time Stamp Addend Register value. + * @retval None + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/** + * @brief Sets the Target Time registers values. + * @param HighValue: specifies the PTP Target Time High Register value. + * @param LowValue: specifies the PTP Target Time Low Register value. + * @retval None + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + /* Set the PTP Target Time High Register */ + ETH->PTPTTHR = HighValue; + /* Set the PTP Target Time Low Register */ + ETH->PTPTTLR = LowValue; +} + +/** + * @brief Get the specified ETHERNET PTP register value. + * @param ETH_PTPReg: specifies the ETHERNET PTP register. + * This parameter can be one of the following values: + * @arg ETH_PTPTSCR : Sub-Second Increment Register + * @arg ETH_PTPSSIR : Sub-Second Increment Register + * @arg ETH_PTPTSHR : Time Stamp High Register + * @arg ETH_PTPTSLR : Time Stamp Low Register + * @arg ETH_PTPTSHUR : Time Stamp High Update Register + * @arg ETH_PTPTSLUR : Time Stamp Low Update Register + * @arg ETH_PTPTSAR : Time Stamp Addend Register + * @arg ETH_PTPTTHR : Target Time High Register + * @arg ETH_PTPTTLR : Target Time Low Register + * @retval The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + /* Check the parameters */ + assert_param(IS_ETH_PTP_REGISTER(ETH_PTPReg)); + + /* Return the selected register value */ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +#ifdef USE_ENHANCED_DMA_DESCRIPTORS +/** + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * @param DMAPTPTxDescTab: Pointer on the first Tx desc list + * @param TxBuff: Pointer on the first TxBuffer list + * @param TxBuffCount: Number of the used Tx desc in the list + * @retval None + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMAPTPTxDesc; + + /* Set the DMAPTPTxDescToSet pointer with the first one of the DMAPTPTxDescTab list */ + DMAPTPTxDescToSet = DMAPTPTxDescTab; + + /* Fill each DMAPTPTxDesc descriptor with the right values */ + for(i=0; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + DMAPTPTxDesc = DMAPTPTxDescTab + i; + + /* Set Second Address Chained bit */ + DMAPTPTxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + + /* Set Buffer1 address pointer */ + DMAPTPTxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (TxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMAPTPTxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPTxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMAPTPTxDesc->Buffer2NextDescAddr = (uint32_t) DMAPTPTxDescTab; + } + } + + /* Set Transmit Desciptor List Address Register */ + ETH->DMATDLAR = (uint32_t) DMAPTPTxDescTab; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param DMAPTPRxDescTab: Pointer on the first Rx desc list + * @param RxBuff: Pointer on the first RxBuffer list + * @param RxBuffCount: Number of the used Rx desc in the list + * @retval None + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMAPTPRxDesc; + + /* Set the DMAPTPRxDescToGet pointer with the first one of the DMAPTPRxDescTab list */ + DMAPTPRxDescToGet = DMAPTPRxDescTab; + + /* Fill each DMAPTPRxDesc descriptor with the right values */ + for(i=0; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMAPTPRxDesc = DMAPTPRxDescTab+i; + + /* Set Own bit of the Rx descriptor Status */ + DMAPTPRxDesc->Status = ETH_DMARxDesc_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMAPTPRxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + + /* Set Buffer1 address pointer */ + DMAPTPRxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_MAX_PACKET_SIZE]); + + /* Initialize the next descriptor with the Next Desciptor Polling Enable */ + if(i < (RxBuffCount-1)) + { + /* Set next descriptor address register with next descriptor base address */ + DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab+i+1); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMAPTPRxDesc->Buffer2NextDescAddr = (uint32_t)(DMAPTPRxDescTab); + } + } + + /* Set Receive Desciptor List Address Register */ + ETH->DMARDLAR = (uint32_t) DMAPTPRxDescTab; +} +#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ + +/** + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * @param ppkt: pointer to application packet buffer to transmit. + * @param FrameLength: Tx Packet size. + * @param PTPTxTab: Pointer on the first PTP Tx table to store Time stamp values. + * @retval ETH_ERROR: in case of Tx desc owned by DMA + * ETH_SUCCESS: for correct transmission + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + /* Return ERROR: OWN bit set */ + return ETH_ERROR; + } + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)) = (*(ppkt + offset)); + } + + /* Setting the Frame Length: bits[12:0] */ + DMAPTPTxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMAPTPTxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMAPTPTxDescToSet->Status |= ETH_DMATxDesc_OWN; + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Wait for ETH_DMATxDesc_TTSS flag to be set */ + do + { + timeout++; + } while (!(DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + + /* Return ERROR in case of timeout */ + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + + /* Clear the DMATxDescToSet status register TTSS flag */ + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + + *PTPTxTab++ = DMAPTPTxDescToSet->TimeStampLow; + *PTPTxTab = DMAPTPTxDescToSet->TimeStampHigh; + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (DMAPTPTxDescToSet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMAPTPTxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + /* Selects the first DMA Tx descriptor for next buffer to send: last Tx descriptor was used */ + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) (ETH->DMATDLAR); + } + else + { + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return SUCCESS */ + return ETH_SUCCESS; +} + +/** + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. + * @param ppkt: pointer to application packet receive buffer. + * @param PTPRxTab: Pointer on the first PTP Rx table to store Time stamp values. + * @retval ETH_ERROR: if there is error in reception + * framelength: received packet size if packet reception is correct + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + /* Return error: OWN bit set */ + return ETH_ERROR; + } + + if(((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMAPTPRxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + for(offset=0; offsetBuffer1Addr) + offset)); + } + } + else + { + /* Return ERROR */ + framelength = ETH_ERROR; + } + + *PTPRxTab++ = DMAPTPRxDescToGet->TimeStampLow; + *PTPRxTab = DMAPTPRxDescToGet->TimeStampHigh; + + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMAPTPRxDescToGet->Status = ETH_DMARxDesc_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMAPTPRxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (DMAPTPRxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMAPTPRxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMAPTPRxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + /* Return Frame Length/ERROR */ + return (framelength); +} + +/** + * @} + */ + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ +/* + * STM32 Eth Driver for RT-Thread + * Change Logs: + * Date Author Notes + * 2009-10-05 Bernard eth interface driver for STM32F107 CL + */ +#include +#include +#include "lwipopts.h" + +/* debug option */ +//#define ETH_DEBUG +//#define ETH_RX_DUMP +//#define ETH_TX_DUMP + +#ifdef ETH_DEBUG +#define STM32_ETH_PRINTF rt_kprintf +#else +#define STM32_ETH_PRINTF(...) +#endif + +#define ETH_RXBUFNB 4 +#define ETH_TXBUFNB 2 +static ETH_DMADESCTypeDef DMARxDscrTab[ETH_RXBUFNB], DMATxDscrTab[ETH_TXBUFNB]; +static rt_uint8_t Rx_Buff[ETH_RXBUFNB][ETH_MAX_PACKET_SIZE], Tx_Buff[ETH_TXBUFNB][ETH_MAX_PACKET_SIZE]; + +#define MAX_ADDR_LEN 6 +struct rt_stm32_eth +{ + /* inherit from ethernet device */ + struct eth_device parent; + + /* interface address info. */ + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ + + uint32_t ETH_Speed; /*!< @ref ETH_Speed */ + uint32_t ETH_Mode; /*!< @ref ETH_Duplex_Mode */ +}; +static struct rt_stm32_eth stm32_eth_device; +static struct rt_semaphore tx_wait; +static rt_bool_t tx_is_waiting = RT_FALSE; + +/* interrupt service routine */ +void ETH_IRQHandler(void) +{ + rt_uint32_t status, ier; + + /* enter interrupt */ + rt_interrupt_enter(); + + status = ETH->DMASR; + ier = ETH->DMAIER; + + if(status & ETH_DMA_IT_MMC) + { + STM32_ETH_PRINTF("ETH_DMA_IT_MMC\r\n"); + ETH_DMAClearITPendingBit(ETH_DMA_IT_MMC); + } + + if(status & ETH_DMA_IT_NIS) + { + rt_uint32_t nis_clear = ETH_DMA_IT_NIS; + + /* [0]:Transmit Interrupt. */ + if((status & ier) & ETH_DMA_IT_T) /* packet transmission */ + { + STM32_ETH_PRINTF("ETH_DMA_IT_T\r\n"); + + if (tx_is_waiting == RT_TRUE) + { + tx_is_waiting = RT_FALSE; + rt_sem_release(&tx_wait); + } + + nis_clear |= ETH_DMA_IT_T; + } + + /* [2]:Transmit Buffer Unavailable. */ + + /* [6]:Receive Interrupt. */ + if((status & ier) & ETH_DMA_IT_R) /* packet reception */ + { + STM32_ETH_PRINTF("ETH_DMA_IT_R\r\n"); + /* a frame has been received */ + eth_device_ready(&(stm32_eth_device.parent)); + + nis_clear |= ETH_DMA_IT_R; + } + + /* [14]:Early Receive Interrupt. */ + + ETH_DMAClearITPendingBit(nis_clear); + } + + if(status & ETH_DMA_IT_AIS) + { + rt_uint32_t ais_clear = ETH_DMA_IT_AIS; + STM32_ETH_PRINTF("ETH_DMA_IT_AIS\r\n"); + + /* [1]:Transmit Process Stopped. */ + if(status & ETH_DMA_IT_TPS) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_TPS\r\n"); + ais_clear |= ETH_DMA_IT_TPS; + } + + /* [3]:Transmit Jabber Timeout. */ + if(status & ETH_DMA_IT_TJT) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_TJT\r\n"); + ais_clear |= ETH_DMA_IT_TJT; + } + + /* [4]: Receive FIFO Overflow. */ + if(status & ETH_DMA_IT_RO) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_RO\r\n"); + ais_clear |= ETH_DMA_IT_RO; + } + + /* [5]: Transmit Underflow. */ + if(status & ETH_DMA_IT_TU) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_TU\r\n"); + ais_clear |= ETH_DMA_IT_TU; + } + + /* [7]: Receive Buffer Unavailable. */ + if(status & ETH_DMA_IT_RBU) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_RBU\r\n"); + ais_clear |= ETH_DMA_IT_RBU; + } + + /* [8]: Receive Process Stopped. */ + if(status & ETH_DMA_IT_RPS) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_RPS\r\n"); + ais_clear |= ETH_DMA_IT_RPS; + } + + /* [9]: Receive Watchdog Timeout. */ + if(status & ETH_DMA_IT_RWT) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_RWT\r\n"); + ais_clear |= ETH_DMA_IT_RWT; + } + + /* [10]: Early Transmit Interrupt. */ + + /* [13]: Fatal Bus Error. */ + if(status & ETH_DMA_IT_FBE) + { + STM32_ETH_PRINTF("AIS ETH_DMA_IT_FBE\r\n"); + ais_clear |= ETH_DMA_IT_FBE; + } + + ETH_DMAClearITPendingBit(ais_clear); + } + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/* RT-Thread Device Interface */ +#include +#include +#include +#include +#include "lwipopts.h" + +/* initialize the interface */ +static rt_err_t rt_stm32_eth_init(rt_device_t dev) +{ + struct rt_stm32_eth * stm32_eth = (struct rt_stm32_eth *)dev; + ETH_InitTypeDef ETH_InitStructure; + + /* Enable ETHERNET clock */ + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx | + RCC_AHB1Periph_ETH_MAC_Rx, ENABLE); + + SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII); + + /* Reset ETHERNET on AHB Bus */ + ETH_DeInit(); + + /* Software reset */ + ETH_SoftwareReset(); + + /* Wait for software reset */ + while (ETH_GetSoftwareResetStatus() == SET); + + /* ETHERNET Configuration --------------------------------------------------*/ + /* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */ + ETH_StructInit(Ð_InitStructure); + + /* Fill ETH_InitStructure parametrs */ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable; + ETH_InitStructure.ETH_Speed = stm32_eth->ETH_Speed; + ETH_InitStructure.ETH_Mode = stm32_eth->ETH_Mode; + + ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable; + ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable; + ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; +#ifdef CHECKSUM_BY_HARDWARE + ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable; +#endif + + /*------------------------ DMA -----------------------------------*/ + + /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: + the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, + if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */ + ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable; + ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + + ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable; + ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable; + ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat; + ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat; + ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1; + + /* configure Ethernet */ + ETH_Init(Ð_InitStructure); + + /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */ + ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R | ETH_DMA_IT_T, ENABLE); + + /* Initialize Tx Descriptors list: Chain Mode */ + ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB); + /* Initialize Rx Descriptors list: Chain Mode */ + ETH_DMARxDescChainInit(DMARxDscrTab, &Rx_Buff[0][0], ETH_RXBUFNB); + + /* MAC address configuration */ + ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&stm32_eth_device.dev_addr[0]); + + /* Enable MAC and DMA transmission and reception */ + ETH_Start(); + + return RT_EOK; +} + +static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag) +{ + return RT_EOK; +} + +static rt_err_t rt_stm32_eth_close(rt_device_t dev) +{ + return RT_EOK; +} + +static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_size_t rt_stm32_eth_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) +{ + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_stm32_eth_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + switch(cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if(args) rt_memcpy(args, stm32_eth_device.dev_addr, 6); + else return -RT_ERROR; + break; + + default : + break; + } + + return RT_EOK; +} + +/* ethernet device interface */ +/* transmit packet. */ +rt_err_t rt_stm32_eth_tx( rt_device_t dev, struct pbuf* p) +{ + struct pbuf* q; + rt_uint32_t offset; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + while ((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + rt_err_t result; + rt_uint32_t level; + + level = rt_hw_interrupt_disable(); + tx_is_waiting = RT_TRUE; + rt_hw_interrupt_enable(level); + + /* it's own bit set, wait it */ + result = rt_sem_take(&tx_wait, RT_WAITING_FOREVER); + if (result == RT_EOK) break; + if (result == -RT_ERROR) return -RT_ERROR; + } + + offset = 0; + for (q = p; q != NULL; q = q->next) + { + uint8_t *to; + + /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */ + to = (uint8_t*)((DMATxDescToSet->Buffer1Addr) + offset); + memcpy(to, q->payload, q->len); + offset += q->len; + } +#ifdef ETH_TX_DUMP + { + rt_uint32_t i; + rt_uint8_t *ptr = (rt_uint8_t*)(DMATxDescToSet->Buffer1Addr); + + STM32_ETH_PRINTF("tx_dump, len:%d\r\n", p->tot_len); + for(i=0; itot_len; i++) + { + STM32_ETH_PRINTF("%02x ",*ptr); + ptr++; + + if(((i+1)%8) == 0) + { + STM32_ETH_PRINTF(" "); + } + if(((i+1)%16) == 0) + { + STM32_ETH_PRINTF("\r\n"); + } + } + STM32_ETH_PRINTF("\r\ndump done!\r\n"); + } +#endif + + /* Setting the Frame Length: bits[12:0] */ + DMATxDescToSet->ControlBufferSize = (p->tot_len & ETH_DMATxDesc_TBS1); + /* Setting the last segment and first segment bits (in this case a frame is transmitted in one descriptor) */ + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + /* Enable TX Completion Interrupt */ + DMATxDescToSet->Status |= ETH_DMATxDesc_IC; +#ifdef CHECKSUM_BY_HARDWARE + DMATxDescToSet->Status |= ETH_DMATxDesc_ChecksumTCPUDPICMPFull; + /* clean ICMP checksum STM32F need */ + { + struct eth_hdr *ethhdr = (struct eth_hdr *)(DMATxDescToSet->Buffer1Addr); + /* is IP ? */ + if( ethhdr->type == htons(ETHTYPE_IP) ) + { + struct ip_hdr *iphdr = (struct ip_hdr *)(DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR); + /* is ICMP ? */ + if( IPH_PROTO(iphdr) == IP_PROTO_ICMP ) + { + struct icmp_echo_hdr *iecho = (struct icmp_echo_hdr *)(DMATxDescToSet->Buffer1Addr + SIZEOF_ETH_HDR + sizeof(struct ip_hdr) ); + iecho->chksum = 0; + } + } + } +#endif + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if ((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_TBUS; + /* Transmit Poll Demand to resume DMA transmission*/ + ETH->DMATPDR = 0; + } + + /* Update the ETHERNET DMA global Tx descriptor with next Tx decriptor */ + /* Chained Mode */ + /* Selects the next DMA Tx descriptor list for next buffer to send */ + DMATxDescToSet = (ETH_DMADESCTypeDef*) (DMATxDescToSet->Buffer2NextDescAddr); + + /* Return SUCCESS */ + return RT_EOK; +} + +/* reception packet. */ +struct pbuf *rt_stm32_eth_rx(rt_device_t dev) +{ + struct pbuf* p; + rt_uint32_t offset = 0, framelength = 0; + + /* init p pointer */ + p = RT_NULL; + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET)) + return p; + + if (((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + /* allocate buffer */ + p = pbuf_alloc(PBUF_LINK, framelength, PBUF_RAM); + if (p != RT_NULL) + { + struct pbuf* q; + + for (q = p; q != RT_NULL; q= q->next) + { + /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */ + memcpy(q->payload, (uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset), q->len); + offset += q->len; + } +#ifdef ETH_RX_DUMP + { + rt_uint32_t i; + rt_uint8_t *ptr = (rt_uint8_t*)(DMARxDescToGet->Buffer1Addr); + + STM32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len); + for(i=0; itot_len; i++) + { + STM32_ETH_PRINTF("%02x ", *ptr); + ptr++; + + if(((i+1)%8) == 0) + { + STM32_ETH_PRINTF(" "); + } + if(((i+1)%16) == 0) + { + STM32_ETH_PRINTF("\r\n"); + } + } + STM32_ETH_PRINTF("\r\ndump done!\r\n"); + } +#endif + } + } + + /* Set Own bit of the Rx descriptor Status: gives the buffer back to ETHERNET DMA */ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + /* When Rx Buffer unavailable flag is set: clear it and resume reception */ + if ((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + /* Clear RBUS ETHERNET DMA flag */ + ETH->DMASR = ETH_DMASR_RBUS; + /* Resume DMA reception */ + ETH->DMARPDR = 0; + } + + /* Update the ETHERNET DMA global Rx descriptor with next Rx decriptor */ + /* Chained Mode */ + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (DMARxDescToGet->Buffer2NextDescAddr); + } + else /* Ring Mode */ + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + /* Selects the first DMA Rx descriptor for next buffer to read: last Rx descriptor was used */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) (ETH->DMARDLAR); + } + else + { + /* Selects the next DMA Rx descriptor list for next buffer to read */ + DMARxDescToGet = (ETH_DMADESCTypeDef*) ((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return p; +} + +static void NVIC_Configuration(void) +{ + NVIC_InitTypeDef NVIC_InitStructure; + + /* Enable the Ethernet global Interrupt */ + NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); +} + +/* + * GPIO Configuration for ETH + */ +static void GPIO_Configuration(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + + /* Enable SYSCFG clock */ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC, ENABLE); + + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + /* config MDIO and MDC. */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH); /* config ETH_MDIO */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH); /* config ETH_MDC */ + /* config PA2: MDIO */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_Init(GPIOA, &GPIO_InitStructure); + /* config PC1: MDC */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + /* Ethernet pins configuration ************************************************/ +#if defined(MII_MODE) +/* + ETH_MDIO ------------> PA2 + ETH_MDC -------------> PC1 + + ETH_MII_CRS ---------> PA0 + ETH_MII_COL ---------> PA3 + + ETH_MII_RX_CLK ------> PA1 + ETH_MII_RX_ER -------> PB10 + ETH_MII_RX_ER -------> PI10 + ETH_MII_RX_DV -------> PA7 + ETH_MII_RXD0 --------> PC4 + ETH_MII_RXD1 --------> PC5 + ETH_MII_RXD2 --------> PB0 + ETH_MII_RXD3 --------> PB1 + + ETH_MII_TX_EN -------> PB11 + ETH_MII_TX_EN -------> PG11 + ETH_MII_TX_CLK ------> PC3 + ETH_MII_TXD0 --------> PB12 + ETH_MII_TXD0 --------> PG13 + ETH_MII_TXD1 --------> PB13 + ETH_MII_TXD1 --------> PG14 + ETH_MII_TXD2 --------> PC2 + ETH_MII_TXD3 --------> PB8 + ETH_MII_TXD3 -------> PE2 +*/ + +#error insert MII GPIO initial. +#elif defined(RMII_MODE) +/* + ETH_MDIO ------------> PA2 + ETH_MDC -------------> PC1 + + ETH_RMII_REF_CLK ----> PA1 + + ETH_RMII_CRS_DV -----> PA7 + ETH_RMII_RXD0 -------> PC4 + ETH_RMII_RXD1 -------> PC5 + + ETH_RMII_TX_EN ------> PG11 + ETH_RMII_TXD0 -------> PG13 + ETH_RMII_TXD1 -------> PG14 + + ETH_RMII_TX_EN ------> PB11 + ETH_RMII_TXD0 -------> PB12 + ETH_RMII_TXD1 -------> PB13 +*/ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH); /* RMII_REF_CLK */ + GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH); /* RMII_CRS_DV */ + + /* configure PA1:RMII_REF_CLK, PA7:RMII_CRS_DV. */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_7; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH); /* RMII_RXD0 */ + GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH); /* RMII_RXD1 */ + + /* configure PC4:RMII_RXD0, PC5:RMII_RXD1. */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOC, &GPIO_InitStructure); + +# if RMII_TX_GPIO_GROUP == 1 + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + + GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH); /* RMII_TX_EN */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH); /* RMII_TXD0 */ + GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH); /* RMII_TXD1 */ + + /* configure PB11:RMII_TX_EN, PB12:RMII_TXD0, PB13:RMII_TXD1 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13; + GPIO_Init(GPIOB, &GPIO_InitStructure); +# elif RMII_TX_GPIO_GROUP == 2 + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOG, ENABLE); + + GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH); /* RMII_TX_EN */ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH); /* RMII_TXD0 */ + GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH); /* RMII_TXD1 */ + + /* configure PG11:RMII_TX_EN, PG13:RMII_TXD0, PG14:RMII_TXD1 */ + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14; + GPIO_Init(GPIOG, &GPIO_InitStructure); +# else +# error RMII_TX_GPIO_GROUP setting error! +# endif /*RMII_TX_GPIO_GROUP */ +#endif /* RMII_MODE */ +} + +/* PHY: LAN8720 */ +static uint8_t phy_speed = 0; +#define PHY_LINK_MASK (1<<0) +#define PHY_100M_MASK (1<<1) +#define PHY_DUPLEX_MASK (1<<2) +static void phy_monitor_thread_entry(void *parameter) +{ + uint8_t phy_addr = 0xFF; + uint8_t phy_speed_new = 0; + + /* phy search */ + { + rt_uint32_t i; + rt_uint16_t temp; + + for(i=0; i<=0x1F; i++) + { + temp = ETH_ReadPHYRegister(i, 0x02); + + if( temp != 0xFFFF ) + { + phy_addr = i; + break; + } + } + } /* phy search */ + + if(phy_addr == 0xFF) + { + STM32_ETH_PRINTF("phy not probe!\r\n"); + return; + } + else + { + STM32_ETH_PRINTF("found a phy, address:0x%02X\r\n", phy_addr); + } + + /* RESET PHY */ + STM32_ETH_PRINTF("RESET PHY!\r\n"); + ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_Reset); + rt_thread_delay(RT_TICK_PER_SECOND * 2); + ETH_WritePHYRegister(phy_addr, PHY_BCR, PHY_AutoNegotiation); + + while(1) + { + uint16_t status = ETH_ReadPHYRegister(phy_addr, PHY_BSR); + STM32_ETH_PRINTF("LAN8720 status:0x%04X\r\n", status); + + phy_speed_new = 0; + + if(status & (PHY_AutoNego_Complete | PHY_Linked_Status)) + { + uint16_t SR; + + SR = ETH_ReadPHYRegister(phy_addr, 31); + STM32_ETH_PRINTF("LAN8720 REG 31:0x%04X\r\n", SR); + + SR = (SR >> 2) & 0x07; /* LAN8720, REG31[4:2], Speed Indication. */ + phy_speed_new = PHY_LINK_MASK; + + if((SR & 0x03) == 2) + { + phy_speed_new |= PHY_100M_MASK; + } + + if(SR & 0x04) + { + phy_speed_new |= PHY_DUPLEX_MASK; + } + } + + /* linkchange */ + if(phy_speed_new != phy_speed) + { + if(phy_speed_new & PHY_LINK_MASK) + { + STM32_ETH_PRINTF("link up "); + + if(phy_speed_new & PHY_100M_MASK) + { + STM32_ETH_PRINTF("100Mbps"); + stm32_eth_device.ETH_Speed = ETH_Speed_100M; + } + else + { + stm32_eth_device.ETH_Speed = ETH_Speed_10M; + STM32_ETH_PRINTF("10Mbps"); + } + + if(phy_speed_new & PHY_DUPLEX_MASK) + { + STM32_ETH_PRINTF(" full-duplex\r\n"); + stm32_eth_device.ETH_Mode = ETH_Mode_FullDuplex; + } + else + { + STM32_ETH_PRINTF(" half-duplex\r\n"); + stm32_eth_device.ETH_Mode = ETH_Mode_HalfDuplex; + } + rt_stm32_eth_init((rt_device_t)&stm32_eth_device); + + /* send link up. */ + eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE); + } /* link up. */ + else + { + STM32_ETH_PRINTF("link down\r\n"); + /* send link down. */ + eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE); + } /* link down. */ + + phy_speed = phy_speed_new; + } /* linkchange */ + + rt_thread_delay(RT_TICK_PER_SECOND); + } /* while(1) */ +} + +void rt_hw_stm32_eth_init(void) +{ + /* PHY RESET: PC0 */ + { + GPIO_InitTypeDef GPIO_InitStructure; + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; + + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOC, &GPIO_InitStructure); + + GPIO_ResetBits(GPIOC, GPIO_Pin_0); + rt_thread_delay(2); + GPIO_SetBits(GPIOC, GPIO_Pin_0); + rt_thread_delay(2); + } + + GPIO_Configuration(); + NVIC_Configuration(); + + stm32_eth_device.ETH_Speed = ETH_Speed_100M; + stm32_eth_device.ETH_Mode = ETH_Mode_FullDuplex; + + /* OUI 00-80-E1 STMICROELECTRONICS. */ + stm32_eth_device.dev_addr[0] = 0x00; + stm32_eth_device.dev_addr[1] = 0x80; + stm32_eth_device.dev_addr[2] = 0xE1; + /* generate MAC addr from 96bit unique ID (only for test). */ + stm32_eth_device.dev_addr[3] = *(rt_uint8_t*)(0x1FFF7A10+4); + stm32_eth_device.dev_addr[4] = *(rt_uint8_t*)(0x1FFF7A10+2); + stm32_eth_device.dev_addr[5] = *(rt_uint8_t*)(0x1FFF7A10+0); + + stm32_eth_device.parent.parent.init = rt_stm32_eth_init; + stm32_eth_device.parent.parent.open = rt_stm32_eth_open; + stm32_eth_device.parent.parent.close = rt_stm32_eth_close; + stm32_eth_device.parent.parent.read = rt_stm32_eth_read; + stm32_eth_device.parent.parent.write = rt_stm32_eth_write; + stm32_eth_device.parent.parent.control = rt_stm32_eth_control; + stm32_eth_device.parent.parent.user_data = RT_NULL; + + stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx; + stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx; + + /* init tx semaphore */ + rt_sem_init(&tx_wait, "tx_wait", 0, RT_IPC_FLAG_FIFO); + + /* register eth device */ + eth_device_init(&(stm32_eth_device.parent), "e0"); + + /* start phy monitor */ + { + rt_thread_t tid; + tid = rt_thread_create("phy", + phy_monitor_thread_entry, + RT_NULL, + 512, + RT_THREAD_PRIORITY_MAX - 2, + 2); + if (tid != RT_NULL) + rt_thread_startup(tid); + } +} diff --git a/bsp/stm32f40x/drivers/stm32f4xx_eth.h b/bsp/stm32f40x/drivers/stm32f4xx_eth.h new file mode 100644 index 0000000000..96f06b7dd2 --- /dev/null +++ b/bsp/stm32f40x/drivers/stm32f4xx_eth.h @@ -0,0 +1,1874 @@ +/** + ****************************************************************************** + * @file stm32f2xx_eth.h + * @author MCD Application Team + * @version V0.0.1 + * @date 10/21/2010 + * @brief This file contains all the functions prototypes for the Ethernet + * firmware library. + ****************************************************************************** + * @copy + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2010 STMicroelectronics

+ */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F2XX_ETH_H +#define __STM32F2XX_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/* Uncomment this line when using time stamping and/or IPv4 checksum offload */ +#define USE_ENHANCED_DMA_DESCRIPTORS + +/** + * @brief Uncomment the line below if you want to use user defined Delay function + * (for precise timing), otherwise default _eth_delay_ function defined within + * this driver is used (less precise timing). + */ +/* #define USE_Delay */ + +#ifdef USE_Delay +#include "main.h" + #define _eth_delay_ Delay /*!< User can provide more timing precise _eth_delay_ function */ +#else + #define _eth_delay_ ETH_Delay /*!< Default _eth_delay_ function with less precise timing */ +#endif + +/** @addtogroup STM32F2XX_ETH_Driver + * @{ + */ + +/** @defgroup ETH_Exported_Types + * @{ + */ + +/** + * @brief ETH MAC Init structure definition + * @note The user should not configure all the ETH_InitTypeDef structure's fields. + * By calling the ETH_StructInit function the structures fields are set to their default values. + * Only the parameters that will be set to a non-default value should be configured. + */ +typedef struct { +/** + * @brief / * MAC + */ + uint32_t ETH_AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t ETH_Watchdog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t ETH_Jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t ETH_InterFrameGap; /*!< Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t ETH_CarrierSense; /*!< Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ETH_Speed; /*!< Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref ETH_Speed */ + + uint32_t ETH_ReceiveOwn; /*!< Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t ETH_LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ETH_Mode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t ETH_ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t ETH_RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t ETH_AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t ETH_BackOffLimit; /*!< Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t ETH_DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ETH_ReceiveAll; /*!< Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t ETH_SourceAddrFilter; /*!< Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t ETH_PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t ETH_BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t ETH_DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t ETH_PromiscuousMode; /*!< Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t ETH_MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t ETH_UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t ETH_HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. */ + + uint32_t ETH_HashTableLow; /*!< This field holds the lower 32 bits of Hash table. */ + + uint32_t ETH_PauseTime; /*!< This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ETH_ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t ETH_PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t ETH_UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ETH_ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t ETH_TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t ETH_VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t ETH_VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ + +/** + * @brief / * DMA + */ + + uint32_t ETH_DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ETH_ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t ETH_FlushReceivedFrame; /*!< Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t ETH_TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t ETH_TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ETH_ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ETH_ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ETH_ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t ETH_SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t ETH_AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t ETH_FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t ETH_RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t ETH_TxDMABurstLength; /*!< Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t ETH_DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + + uint32_t ETH_DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ +}ETH_InitTypeDef; + +/**--------------------------------------------------------------------------**/ +/** + * @brief DMA descriptors types + */ +/**--------------------------------------------------------------------------**/ + +/** + * @brief ETH DMA Desciptors data structure definition + */ +typedef struct { + uint32_t Status; /*!< Status */ + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ +/* Enhanced ETHERNET DMA PTP Desciptors */ +#ifdef USE_ENHANCED_DMA_DESCRIPTORS + uint32_t ExtendedStatus; /* Extended status for PTP receive descriptor */ + uint32_t Reserved1; /* Reserved */ + uint32_t TimeStampLow; /* Time Stamp Low value for transmit and receive */ + uint32_t TimeStampHigh; /* Time Stamp High value for transmit and receive */ +#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ +} ETH_DMADESCTypeDef; + + +/** + * @} + */ + +/** @defgroup ETH_Exported_Constants + * @{ + */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief ETH Frames defines + */ +/**--------------------------------------------------------------------------**/ + +/** @defgroup ENET_Buffers_setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1520 /*!< ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /*!< Ethernet CRC */ +#define ETH_EXTRA 2 /*!< Extra bytes in some cases */ +#define VLAN_TAG 4 /*!< optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /*!< Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /*!< Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /*!< Jumbo frame payload size */ + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA descriptors registers bits definition + */ +/**--------------------------------------------------------------------------**/ + +/** +@code + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ----------------------------------------------------------------------------------------------- +@endcode +*/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /*!< First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /*!< Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /*!< Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /*!< IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /*!< VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /*!< Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + + /*--------------------------------------------------------------------------------------------- + TDES6 | Transmit Time Stmap Low [31:0] | + ----------------------------------------------------------------------------------------------- + TDES7 | Transmit Time Stmap High [31:0] | + ----------------------------------------------------------------------------------------------*/ + +/* Bit definition of TDES6 register */ + #define ETH_DMAPTPTxDesc_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stmap Low */ + +/* Bit definition of TDES7 register */ + #define ETH_DMAPTPTxDesc_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stmap High */ + +/** + * @} + */ + + +/** @defgroup DMA_Rx_descriptor + * @{ + */ + +/** +@code + DMA Rx Desciptor + -------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- +@endcode +*/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /*!< Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /*!< CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */ + +/*--------------------------------------------------------------------------------------------------------------------- + RDES4 | Reserved[31:15] | Extended Status [14:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES5 | Reserved[31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES6 | Receive Time Stmap Low [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES7 | Receive Time Stmap High [31:0] | + --------------------------------------------------------------------------------------------------------------------*/ + +/* Bit definition of RDES4 register */ +#define ETH_DMAPTPRxDesc_PTPV ((uint32_t)0x00002000) /* PTP Version */ +#define ETH_DMAPTPRxDesc_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */ +#define ETH_DMAPTPRxDesc_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */ + #define ETH_DMAPTPRxDesc_PTPMT_Sync ((uint32_t)0x00000100) /* SYNC message (all clock types) */ + #define ETH_DMAPTPRxDesc_PTPMT_FollowUp ((uint32_t)0x00000200) /* FollowUp message (all clock types) */ + #define ETH_DMAPTPRxDesc_PTPMT_DelayReq ((uint32_t)0x00000300) /* DelayReq message (all clock types) */ + #define ETH_DMAPTPRxDesc_PTPMT_DelayResp ((uint32_t)0x00000400) /* DelayResp message (all clock types) */ + #define ETH_DMAPTPRxDesc_PTPMT_PdelayReq_Announce ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ + #define ETH_DMAPTPRxDesc_PTPMT_PdelayResp_Manag ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ + #define ETH_DMAPTPRxDesc_PTPMT_PdelayRespFollowUp_Signal ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRxDesc_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */ +#define ETH_DMAPTPRxDesc_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */ +#define ETH_DMAPTPRxDesc_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */ +#define ETH_DMAPTPRxDesc_IPPE ((uint32_t)0x00000010) /* IP Payload Error */ +#define ETH_DMAPTPRxDesc_IPHE ((uint32_t)0x00000008) /* IP Header Error */ +#define ETH_DMAPTPRxDesc_IPPT ((uint32_t)0x00000007) /* IP Payload Type */ + #define ETH_DMAPTPRxDesc_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */ + #define ETH_DMAPTPRxDesc_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */ + #define ETH_DMAPTPRxDesc_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */ + +/* Bit definition of RDES6 register */ +#define ETH_DMAPTPRxDesc_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stmap Low */ + +/* Bit definition of RDES7 register */ +#define ETH_DMAPTPRxDesc_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stmap High */ + + +/**--------------------------------------------------------------------------**/ +/** + * @brief Desciption of common PHY registers + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup PHY_Read_write_Timeouts + * @{ + */ +#define PHY_READ_TO ((uint32_t)0x0004FFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/** + * @} + */ + +/** @defgroup PHY_Reset_Delay + * @{ + */ +#define PHY_ResetDelay ((uint32_t)0x000FFFFF) + +/** + * @} + */ + +/** @defgroup PHY_Config_Delay + * @{ + */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/** + * @} + */ + +/** @defgroup PHY_Register_address + * @{ + */ +#define PHY_BCR 0 /*!< Tranceiver Basic Control Register */ +#define PHY_BSR 1 /*!< Tranceiver Basic Status Register */ + +/** + * @} + */ + +/** @defgroup PHY_basic_Control_register + * @{ + */ +#define PHY_Reset ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +/** + * @} + */ + +/** @defgroup PHY_basic_status_register + * @{ + */ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /*!< Auto-Negotioation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /*!< Jabber condition detected */ + +/** + * @} + */ + +/** @defgroup PHY_status_register + * @{ + */ +/* The PHY status register value change from a PHY to another so the user have + to update this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +/*#define PHY_SR 31 */ /*!< Tranceiver Status Register */ + +/** + * @brief For DP83848 + */ +#define PHY_SR 16 /*!< Tranceiver Status Register */ + +/* The Speed and Duplex mask values change from a PHY to another so the user have to update + this value depending on the used external PHY */ +/** + * @brief For LAN8700 + */ +/*#define PHY_Speed_Status ((uint16_t)0x0004)*/ /*!< Configured information of Speed: 10Mbps */ +/*#define PHY_Duplex_Status ((uint16_t)0x0010)*/ /*!< Configured information of Duplex: Full-duplex */ + +/** + * @brief For DP83848 + */ +#define PHY_Speed_Status ((uint16_t)0x0002) /*!< Configured information of Speed: 10Mbps */ +#define PHY_Duplex_Status ((uint16_t)0x0004) /*!< Configured information of Duplex: Full-duplex */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) +#define IS_ETH_PHY_REG(REG) ((REG) <= 0x1F) + +/**--------------------------------------------------------------------------**/ +/** + * @brief MAC defines + */ +/**--------------------------------------------------------------------------**/ + +/** + * @} + */ + +/** @defgroup ETH_AutoNegotiation + * @{ + */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AutoNegotiation_Enable) || \ + ((CMD) == ETH_AutoNegotiation_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_watchdog + * @{ + */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_Watchdog_Enable) || \ + ((CMD) == ETH_Watchdog_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Jabber + * @{ + */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_Jabber_Enable) || \ + ((CMD) == ETH_Jabber_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap + * @{ + */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */ +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_InterFrameGap_96Bit) || \ + ((GAP) == ETH_InterFrameGap_88Bit) || \ + ((GAP) == ETH_InterFrameGap_80Bit) || \ + ((GAP) == ETH_InterFrameGap_72Bit) || \ + ((GAP) == ETH_InterFrameGap_64Bit) || \ + ((GAP) == ETH_InterFrameGap_56Bit) || \ + ((GAP) == ETH_InterFrameGap_48Bit) || \ + ((GAP) == ETH_InterFrameGap_40Bit)) + +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense + * @{ + */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CarrierSense_Enable) || \ + ((CMD) == ETH_CarrierSense_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Speed + * @{ + */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_Speed_10M) || \ + ((SPEED) == ETH_Speed_100M)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Own + * @{ + */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_ReceiveOwn_Enable) || \ + ((CMD) == ETH_ReceiveOwn_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Loop_Back_Mode + * @{ + */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LoopbackMode_Enable) || \ + ((CMD) == ETH_LoopbackMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Duplex_Mode + * @{ + */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_Mode_FullDuplex) || \ + ((MODE) == ETH_Mode_HalfDuplex)) + +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload + * @{ + */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_ChecksumOffload_Enable) || \ + ((CMD) == ETH_ChecksumOffload_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission + * @{ + */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RetryTransmission_Enable) || \ + ((CMD) == ETH_RetryTransmission_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip + * @{ + */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AutomaticPadCRCStrip_Enable) || \ + ((CMD) == ETH_AutomaticPadCRCStrip_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Back_Off_Limit + * @{ + */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BackOffLimit_10) || \ + ((LIMIT) == ETH_BackOffLimit_8) || \ + ((LIMIT) == ETH_BackOffLimit_4) || \ + ((LIMIT) == ETH_BackOffLimit_1)) + +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check + * @{ + */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DeferralCheck_Enable) || \ + ((CMD) == ETH_DeferralCheck_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_All + * @{ + */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_ReceiveAll_Enable) || \ + ((CMD) == ETH_ReceiveAll_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter + * @{ + */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SourceAddrFilter_Normal_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Inverse_Enable) || \ + ((CMD) == ETH_SourceAddrFilter_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames + * @{ + */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */ +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PassControlFrames_BlockAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardAll) || \ + ((PASS) == ETH_PassControlFrames_ForwardPassedAddrFilter)) + +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception + * @{ + */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BroadcastFramesReception_Enable) || \ + ((CMD) == ETH_BroadcastFramesReception_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter + * @{ + */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DestinationAddrFilter_Normal) || \ + ((FILTER) == ETH_DestinationAddrFilter_Inverse)) + +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode + * @{ + */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PromiscuousMode_Enable) || \ + ((CMD) == ETH_PromiscuousMode_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Multicast_Frames_Filter + * @{ + */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MulticastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_HashTable) || \ + ((FILTER) == ETH_MulticastFramesFilter_Perfect) || \ + ((FILTER) == ETH_MulticastFramesFilter_None)) + + +/** + * @} + */ + +/** @defgroup ETH_Unicast_Frames_Filter + * @{ + */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UnicastFramesFilter_PerfectHashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_HashTable) || \ + ((FILTER) == ETH_UnicastFramesFilter_Perfect)) + +/** + * @} + */ + +/** @defgroup ETH_Pause_Time + * @{ + */ +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause + * @{ + */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZeroQuantaPause_Enable) || \ + ((CMD) == ETH_ZeroQuantaPause_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold + * @{ + */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */ +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PauseLowThreshold_Minus4) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus28) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus144) || \ + ((THRESHOLD) == ETH_PauseLowThreshold_Minus256)) + +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect + * @{ + */ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UnicastPauseFrameDetect_Enable) || \ + ((CMD) == ETH_UnicastPauseFrameDetect_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control + * @{ + */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_ReceiveFlowControl_Enable) || \ + ((CMD) == ETH_ReceiveFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control + * @{ + */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TransmitFlowControl_Enable) || \ + ((CMD) == ETH_TransmitFlowControl_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison + * @{ + */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTagComparison_12Bit) || \ + ((COMPARISON) == ETH_VLANTagComparison_16Bit)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) + +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags + * @{ + */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */ +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts + * @{ + */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */ +#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses + * @{ + */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_Address0) || \ + ((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_Address1) || \ + ((ADDRESS) == ETH_MAC_Address2) || \ + ((ADDRESS) == ETH_MAC_Address3)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames + * @{ + */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_AddressFilter_SA) || \ + ((FILTER) == ETH_MAC_AddressFilter_DA)) +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_Mask_bytes + * @{ + */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */ +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_AddressMask_Byte6) || \ + ((MASK) == ETH_MAC_AddressMask_Byte5) || \ + ((MASK) == ETH_MAC_AddressMask_Byte4) || \ + ((MASK) == ETH_MAC_AddressMask_Byte3) || \ + ((MASK) == ETH_MAC_AddressMask_Byte2) || \ + ((MASK) == ETH_MAC_AddressMask_Byte1)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA Desciptors defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_flags + * @{ + */ +#define IS_ETH_DMATxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATxDesc_OWN) || \ + ((FLAG) == ETH_DMATxDesc_IC) || \ + ((FLAG) == ETH_DMATxDesc_LS) || \ + ((FLAG) == ETH_DMATxDesc_FS) || \ + ((FLAG) == ETH_DMATxDesc_DC) || \ + ((FLAG) == ETH_DMATxDesc_DP) || \ + ((FLAG) == ETH_DMATxDesc_TTSE) || \ + ((FLAG) == ETH_DMATxDesc_TER) || \ + ((FLAG) == ETH_DMATxDesc_TCH) || \ + ((FLAG) == ETH_DMATxDesc_TTSS) || \ + ((FLAG) == ETH_DMATxDesc_IHE) || \ + ((FLAG) == ETH_DMATxDesc_ES) || \ + ((FLAG) == ETH_DMATxDesc_JT) || \ + ((FLAG) == ETH_DMATxDesc_FF) || \ + ((FLAG) == ETH_DMATxDesc_PCE) || \ + ((FLAG) == ETH_DMATxDesc_LCA) || \ + ((FLAG) == ETH_DMATxDesc_NC) || \ + ((FLAG) == ETH_DMATxDesc_LCO) || \ + ((FLAG) == ETH_DMATxDesc_EC) || \ + ((FLAG) == ETH_DMATxDesc_VF) || \ + ((FLAG) == ETH_DMATxDesc_CC) || \ + ((FLAG) == ETH_DMATxDesc_ED) || \ + ((FLAG) == ETH_DMATxDesc_UF) || \ + ((FLAG) == ETH_DMATxDesc_DB)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment + * @{ + */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /*!< Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /*!< First Segment */ +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATxDesc_LastSegment) || \ + ((SEGMENT) == ETH_DMATxDesc_FirstSegment)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control + * @{ + */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /*!< Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATxDesc_ChecksumByPass) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumIPV4Header) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPSegment) || \ + ((CHECKSUM) == ETH_DMATxDesc_ChecksumTCPUDPICMPFull)) +/** + * @brief ETH DMA Tx Desciptor buffer size + */ +#define IS_ETH_DMATxDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_flags + * @{ + */ +#define IS_ETH_DMARxDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARxDesc_OWN) || \ + ((FLAG) == ETH_DMARxDesc_AFM) || \ + ((FLAG) == ETH_DMARxDesc_ES) || \ + ((FLAG) == ETH_DMARxDesc_DE) || \ + ((FLAG) == ETH_DMARxDesc_SAF) || \ + ((FLAG) == ETH_DMARxDesc_LE) || \ + ((FLAG) == ETH_DMARxDesc_OE) || \ + ((FLAG) == ETH_DMARxDesc_VLAN) || \ + ((FLAG) == ETH_DMARxDesc_FS) || \ + ((FLAG) == ETH_DMARxDesc_LS) || \ + ((FLAG) == ETH_DMARxDesc_IPV4HCE) || \ + ((FLAG) == ETH_DMARxDesc_LC) || \ + ((FLAG) == ETH_DMARxDesc_FT) || \ + ((FLAG) == ETH_DMARxDesc_RWT) || \ + ((FLAG) == ETH_DMARxDesc_RE) || \ + ((FLAG) == ETH_DMARxDesc_DBE) || \ + ((FLAG) == ETH_DMARxDesc_CE) || \ + ((FLAG) == ETH_DMARxDesc_MAMPCE)) + +/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/ +#define IS_ETH_DMAPTPRxDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRxDesc_PTPV) || \ + ((FLAG) == ETH_DMAPTPRxDesc_PTPFT) || \ + ((FLAG) == ETH_DMAPTPRxDesc_PTPMT) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPV6PR) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPV4PR) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPCB) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPPE) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPHE) || \ + ((FLAG) == ETH_DMAPTPRxDesc_IPPT)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers_ + * @{ + */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */ +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARxDesc_Buffer1) || \ + ((BUFFER) == ETH_DMARxDesc_Buffer2)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet DMA defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame + * @{ + */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DropTCPIPChecksumErrorFrame_Enable) || \ + ((CMD) == ETH_DropTCPIPChecksumErrorFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward + * @{ + */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_ReceiveStoreForward_Enable) || \ + ((CMD) == ETH_ReceiveStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame + * @{ + */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FlushReceivedFrame_Enable) || \ + ((CMD) == ETH_FlushReceivedFrame_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward + * @{ + */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TransmitStoreForward_Enable) || \ + ((CMD) == ETH_TransmitStoreForward_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control + * @{ + */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TransmitThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_128Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_192Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_256Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_40Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_24Bytes) || \ + ((THRESHOLD) == ETH_TransmitThresholdControl_16Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames + * @{ + */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_ForwardErrorFrames_Enable) || \ + ((CMD) == ETH_ForwardErrorFrames_Disable)) +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames + * @{ + */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_ForwardUndersizedGoodFrames_Enable) || \ + ((CMD) == ETH_ForwardUndersizedGoodFrames_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control + * @{ + */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_ReceiveThresholdControl_64Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_32Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_96Bytes) || \ + ((THRESHOLD) == ETH_ReceiveThresholdControl_128Bytes)) +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate + * @{ + */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SecondFrameOperate_Enable) || \ + ((CMD) == ETH_SecondFrameOperate_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats + * @{ + */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_AddressAlignedBeats_Enable) || \ + ((CMD) == ETH_AddressAlignedBeats_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst + * @{ + */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FixedBurst_Enable) || \ + ((CMD) == ETH_FixedBurst_Disable)) + +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length + * @{ + */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ + +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_RxDMABurstLength_4xPBL_128Beat)) + +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length + * @{ + */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TxDMABurstLength_1Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_2Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_4Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_8Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_16Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_32Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_64Beat) || \ + ((LENGTH) == ETH_TxDMABurstLength_4xPBL_128Beat)) +/** + * @brief ETH DMA Desciptor SkipLength + */ +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) + +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration + * @{ + */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_1_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_2_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_3_1) || \ + ((RATIO) == ETH_DMAArbitration_RoundRobin_RxTx_4_1) || \ + ((RATIO) == ETH_DMAArbitration_RxPriorTx)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags + * @{ + */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */ + +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFE1800) == 0x00) && ((FLAG) != 0x00)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DataTransferError) || \ + ((FLAG) == ETH_DMA_FLAG_ReadWriteError) || ((FLAG) == ETH_DMA_FLAG_AccessError) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts + * @{ + */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */ + +#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xFFFE1800) == 0x00) && ((IT) != 0x00)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) + +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state_ + * @{ + */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /*!< Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /*!< Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state_ + * @{ + */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /*!< Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /*!< Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /*!< Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /*!< Running - queuing the recieve frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow_ + * @{ + */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */ +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_Overflow_RxFIFOCounter) || \ + ((OVERFLOW) == ETH_DMA_Overflow_MissedFrameCounter)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PMT defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */ +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet MMC defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */ + +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */ +#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ + ((IT) != 0x00)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +/** + * @} + */ + +/** @defgroup ETH_MMC_Registers + * @{ + */ +#define ETH_MMCCR ((uint32_t)0x00000100) /*!< MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /*!< MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /*!< MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /*!< MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /*!< MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /*!< MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /*!< MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /*!< MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /*!< MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /*!< MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /*!< MMC RGUFCR register */ + +/** + * @brief ETH MMC registers + */ +#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) || ((REG) == ETH_MMCRIR) || \ + ((REG) == ETH_MMCTIR) || ((REG) == ETH_MMCRIMR) || \ + ((REG) == ETH_MMCTIMR) || ((REG) == ETH_MMCTGFSCCR) || \ + ((REG) == ETH_MMCTGFMSCCR) || ((REG) == ETH_MMCTGFCR) || \ + ((REG) == ETH_MMCRFCECR) || ((REG) == ETH_MMCRFAECR) || \ + ((REG) == ETH_MMCRGUFCR)) + +/**--------------------------------------------------------------------------**/ +/** + * @brief Ethernet PTP defines + */ +/**--------------------------------------------------------------------------**/ +/** + * @} + */ + +/** @defgroup ETH_PTP_time_update_method + * @{ + */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /*!< Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /*!< Coarse Update method */ +#define IS_ETH_PTP_UPDATE(UPDATE) (((UPDATE) == ETH_PTP_FineUpdate) || \ + ((UPDATE) == ETH_PTP_CoarseUpdate)) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_Flags + * @{ + */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /*!< Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /*!< Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /*!< Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /*!< Time Stamp Initialize */ + +#define ETH_PTP_FLAG_TSTTR ((uint32_t)0x10000002) /* Time stamp target time reached */ +#define ETH_PTP_FLAG_TSSO ((uint32_t)0x10000001) /* Time stamp seconds overflow */ + +#define IS_ETH_PTP_GET_FLAG(FLAG) (((FLAG) == ETH_PTP_FLAG_TSARU) || \ + ((FLAG) == ETH_PTP_FLAG_TSITE) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTU) || \ + ((FLAG) == ETH_PTP_FLAG_TSSTI) || \ + ((FLAG) == ETH_PTP_FLAG_TSTTR) || \ + ((FLAG) == ETH_PTP_FLAG_TSSO)) + +/** + * @brief ETH PTP subsecond increment + */ +#define IS_ETH_PTP_SUBSECOND_INCREMENT(SUBSECOND) ((SUBSECOND) <= 0xFF) + +/** + * @} + */ + + +/** @defgroup ETH_PTP_time_sign + * @{ + */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /*!< Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /*!< Negative time value */ +#define IS_ETH_PTP_TIME_SIGN(SIGN) (((SIGN) == ETH_PTP_PositiveTime) || \ + ((SIGN) == ETH_PTP_NegativeTime)) + +/** + * @brief ETH PTP time stamp low update + */ +#define IS_ETH_PTP_TIME_STAMP_UPDATE_SUBSECOND(SUBSECOND) ((SUBSECOND) <= 0x7FFFFFFF) + +/** + * @brief ETH PTP registers + */ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /*!< PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /*!< PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /*!< PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /*!< PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /*!< PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /*!< PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /*!< PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /*!< PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ + +#define ETH_PTPTSSR ((uint32_t)0x00000728) /* PTP TSSR register */ + +#define IS_ETH_PTP_REGISTER(REG) (((REG) == ETH_PTPTSCR) || ((REG) == ETH_PTPSSIR) || \ + ((REG) == ETH_PTPTSHR) || ((REG) == ETH_PTPTSLR) || \ + ((REG) == ETH_PTPTSHUR) || ((REG) == ETH_PTPTSLUR) || \ + ((REG) == ETH_PTPTSAR) || ((REG) == ETH_PTPTTHR) || \ + ((REG) == ETH_PTPTTLR) || ((REG) == ETH_PTPTSSR)) + +/** + * @brief ETHERNET PTP clock + */ +#define ETH_PTP_OrdinaryClock ((uint32_t)0x00000000) /* Ordinary Clock */ +#define ETH_PTP_BoundaryClock ((uint32_t)0x00010000) /* Boundary Clock */ +#define ETH_PTP_EndToEndTransparentClock ((uint32_t)0x00020000) /* End To End Transparent Clock */ +#define ETH_PTP_PeerToPeerTransparentClock ((uint32_t)0x00030000) /* Peer To Peer Transparent Clock */ + +#define IS_ETH_PTP_TYPE_CLOCK(CLOCK) (((CLOCK) == ETH_PTP_OrdinaryClock) || \ + ((CLOCK) == ETH_PTP_BoundaryClock) || \ + ((CLOCK) == ETH_PTP_EndToEndTransparentClock) || \ + ((CLOCK) == ETH_PTP_PeerToPeerTransparentClock)) +/** + * @brief ETHERNET snapshot + */ +#define ETH_PTP_SnapshotMasterMessage ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTP_SnapshotEventMessage ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTP_SnapshotIPV4Frames ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTP_SnapshotIPV6Frames ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTP_SnapshotPTPOverEthernetFrames ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTP_SnapshotAllReceivedFrames ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define IS_ETH_PTP_SNAPSHOT(SNAPSHOT) (((SNAPSHOT) == ETH_PTP_SnapshotMasterMessage) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotEventMessage) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotIPV4Frames) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotIPV6Frames) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotPTPOverEthernetFrames) || \ + ((SNAPSHOT) == ETH_PTP_SnapshotAllReceivedFrames)) + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup ETH_Exported_Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions + * @{ + */ +void ETH_DeInit(void); +uint32_t ETH_Init(ETH_InitTypeDef* ETH_InitStruct); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength); +uint32_t ETH_HandleRxPkt(uint8_t *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); + +#ifdef USE_ENHANCED_DMA_DESCRIPTORS + void ETH_EnhancedDescriptorCmd(FunctionalState NewState); +#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ + +/** + * @brief PHY + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); + +/** + * @brief MAC + */ +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +/** + * @brief DMA Tx/Rx descriptors + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +#ifdef USE_ENHANCED_DMA_DESCRIPTORS + FlagStatus ETH_GetDMAPTPRxDescExtendedFlagStatus(ETH_DMADESCTypeDef *DMAPTPRxDesc, uint32_t ETH_DMAPTPRxDescExtendedFlag); +#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +/** + * @brief DMA + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); +void ETH_SetReceiveWatchdogTimer(uint8_t Value); + + +/** + * @brief PMT + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +/** + * @brief MMC + */ +void ETH_MMCCounterFullPreset(void); +void ETH_MMCCounterHalfPreset(void); +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +/** + * @brief PTP + */ +void ETH_PTPNodeClockTypeConfig(uint32_t ClockType); +void ETH_PTPSnapshotCmd(uint32_t SnapshotMethod, FunctionalState NewState); +void ETH_PTPPacketSnoopingV2FormatCmd(FunctionalState NewState); +void ETH_PTPSubSecondRolloverCmd(FunctionalState NewState); +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab); +#ifdef USE_ENHANCED_DMA_DESCRIPTORS + void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); + void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +#endif /* USE_ENHANCED_DMA_DESCRIPTORS */ +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); + +/* STM32 ETH HW initialization */ +void rt_hw_stm32_eth_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F2XX_ETH_H */ +/** + * @} + */ + + +/** + * @} + */ + +/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ From e9c489d02bfaf2b8ea1b36ac1cc3bd8fa6f92605 Mon Sep 17 00:00:00 2001 From: yuanbin Date: Fri, 8 May 2015 18:49:25 +0800 Subject: [PATCH 03/18] modify indentation --- components/net/lwip_dhcpd/dhcp_server.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/net/lwip_dhcpd/dhcp_server.c b/components/net/lwip_dhcpd/dhcp_server.c index f242236606..cb3fc0f464 100644 --- a/components/net/lwip_dhcpd/dhcp_server.c +++ b/components/net/lwip_dhcpd/dhcp_server.c @@ -378,12 +378,12 @@ void dhcpd_start(char* netif_name) rt_thread_t thread; struct netif *netif = netif_list; - if(strlen(netif_name) > sizeof(netif->name)) + if(strlen(netif_name) > sizeof(netif->name)) { rt_kprintf("network interface name too long!\r\n"); return; } - while(netif != RT_NULL) + while(netif != RT_NULL) { if(strncmp(netif_name, netif->name, sizeof(netif->name)) == 0) break; From 42226779338716fbef7ab4eab6386fe3462912ae Mon Sep 17 00:00:00 2001 From: Adrian Huang Date: Mon, 11 May 2015 09:57:12 +0800 Subject: [PATCH 04/18] [libcpu][am335x] Fix the booting failure when enabling MMU Since the 16 domains are configured as the client domains in mmu_setttbase(), a Permission fault is generated if the XN bit (Execute-never) is set in the short-descriptor translation table (for section and supersection). This leads to the booting failure when enabling MMU for beagleboard bsp. Here is log: ---------------------------------------------------------------- SD/MMC found on device 0 reading uEnv.txt 117 bytes read in 3 ms (38.1 KiB/s) Loaded environment from uEnv.txt Importing environment from mmc ... Running uenvcmd ... reading rtthread.bin 162624 bytes read in 24 ms (6.5 MiB/s) \## Starting application at 0x80200000 ... ---------------------------------------------------------------- This commit removes the XN bit configuration in the section of the short-descriptor translation table. The OS can be booted successfully with applying this commit. --- libcpu/arm/am335x/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c index 46f2d6afd7..d3e505e76a 100644 --- a/libcpu/arm/am335x/mmu.c +++ b/libcpu/arm/am335x/mmu.c @@ -15,7 +15,7 @@ #include #include "am33xx.h" -#define DESC_SEC (0x2|(1<<4)) +#define DESC_SEC (0x2) #define CB (3<<2) //cache_on, write_back #define CNB (2<<2) //cache_on, write_through #define NCB (1<<2) //cache_off,WR_BUF on From 075fb45448243c621d098ad4f40e7f681ee1d08d Mon Sep 17 00:00:00 2001 From: BernardXiong Date: Mon, 11 May 2015 21:05:11 +0800 Subject: [PATCH 05/18] [BSP] update project for LPC176x --- bsp/lpc176x/project.uvproj | 525 +++++++++++++++++++++++-------------- 1 file changed, 327 insertions(+), 198 deletions(-) diff --git a/bsp/lpc176x/project.uvproj b/bsp/lpc176x/project.uvproj index f9754f3067..d7b1633680 100644 --- a/bsp/lpc176x/project.uvproj +++ b/bsp/lpc176x/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- RT-Thread LPC17xx @@ -15,25 +12,25 @@ LPC1768 NXP (founded by Philips) IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3") - + "STARTUP\NXP\startup_LPC17xx.s" ("NXP LPC17xx Startup Code") UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL040000) 4868 LPC17xx.H - - - - - - - - - - + + + + + + + + + + 0 - - - + + + NXP\ NXP\ @@ -57,31 +54,29 @@ 0 0 - - + + 0 0 - 0 - 0 0 0 - - + + 0 0 0 0 - - + + 0 0 0 - + 0 @@ -95,8 +90,8 @@ 0 0 3 - - + + SARMCM3.DLL @@ -117,7 +112,7 @@ 16 - 0 + 1 1 1 1 @@ -128,9 +123,9 @@ 0 - 1 + 0 1 - 1 + 0 1 1 1 @@ -138,20 +133,20 @@ 1 0 - 7 + 5 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -166,7 +161,7 @@ Segger\JL2CM3.dll "" () - + @@ -198,7 +193,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -329,7 +324,7 @@ 0x8000 - + 1 @@ -345,10 +340,10 @@ 0 0 - - - - .;..\..\components\CMSIS\Include;..\..\components\finsh;..\..\components\init;..\..\components\net\lwip\src;..\..\components\net\lwip\src\arch\include;..\..\components\net\lwip\src\include;..\..\components\net\lwip\src\include\ipv4;..\..\components\net\lwip\src\include\netif;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;CMSIS\CM3\DeviceSupport\NXP\LPC17xx;applications;drivers + + + + applications;.;drivers;CMSIS/CM3/DeviceSupport/NXP/LPC17xx;../../components/CMSIS/Include;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif @@ -360,10 +355,10 @@ 0 0 - - - - + + + + @@ -375,12 +370,12 @@ 0 0x00000000 0x10000000 - - - - --keep __fsym_* --keep __vsym_* - - + + + + --keep *.o(FSymTab) --keep *.o(VSymTab) + + @@ -391,32 +386,21 @@ application.c 1 - applications\application.c + applications/application.c + + platform.c 1 - applications\platform.c + applications/platform.c + + startup.c 1 - applications\startup.c - - - - - CMSIS - - - system_LPC17xx.c - 1 - CMSIS\CM3\DeviceSupport\NXP\LPC17xx\system_LPC17xx.c - - - startup_LPC17xx.s - 2 - CMSIS\CM3\DeviceSupport\NXP\LPC17xx\startup\arm\startup_LPC17xx.s + applications/startup.c @@ -426,27 +410,52 @@ board.c 1 - drivers\board.c + drivers/board.c + + emac.c 1 - drivers\emac.c + drivers/emac.c + + led.c 1 - drivers\led.c + drivers/led.c + + spi.c 1 - drivers\spi.c + drivers/spi.c + + uart.c 1 - drivers\uart.c + drivers/uart.c + + + + + CMSIS + + + system_LPC17xx.c + 1 + CMSIS/CM3/DeviceSupport/NXP/LPC17xx/system_LPC17xx.c + + + + + startup_LPC17xx.s + 2 + CMSIS/CM3/DeviceSupport/NXP/LPC17xx/startup/arm/startup_LPC17xx.s @@ -456,67 +465,98 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + device.c 1 - ..\..\src\device.c + ../../src/device.c + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + mem.c 1 - ..\..\src\mem.c + ../../src/mem.c + + memheap.c 1 - ..\..\src\memheap.c + ../../src/memheap.c + + mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -526,107 +566,129 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c + ../../libcpu/arm/cortex-m3/cpuport.c + + context_rvds.S 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S + ../../libcpu/arm/cortex-m3/context_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c finsh - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c + + symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c - - - Components - components.c + cmd.c 1 - ..\..\components\init\components.c + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c @@ -636,182 +698,249 @@ api_lib.c 1 - ..\..\components\net\lwip\src\api\api_lib.c + ../../components/net/lwip-1.4.1/src/api/api_lib.c + + api_msg.c 1 - ..\..\components\net\lwip\src\api\api_msg.c + ../../components/net/lwip-1.4.1/src/api/api_msg.c + + err.c 1 - ..\..\components\net\lwip\src\api\err.c + ../../components/net/lwip-1.4.1/src/api/err.c + + netbuf.c 1 - ..\..\components\net\lwip\src\api\netbuf.c + ../../components/net/lwip-1.4.1/src/api/netbuf.c + + netdb.c 1 - ..\..\components\net\lwip\src\api\netdb.c + ../../components/net/lwip-1.4.1/src/api/netdb.c + + netifapi.c 1 - ..\..\components\net\lwip\src\api\netifapi.c + ../../components/net/lwip-1.4.1/src/api/netifapi.c + + sockets.c 1 - ..\..\components\net\lwip\src\api\sockets.c + ../../components/net/lwip-1.4.1/src/api/sockets.c + + tcpip.c 1 - ..\..\components\net\lwip\src\api\tcpip.c + ../../components/net/lwip-1.4.1/src/api/tcpip.c + + sys_arch.c 1 - ..\..\components\net\lwip\src\arch\sys_arch.c + ../../components/net/lwip-1.4.1/src/arch/sys_arch.c + + def.c 1 - ..\..\components\net\lwip\src\core\def.c + ../../components/net/lwip-1.4.1/src/core/def.c + + dhcp.c 1 - ..\..\components\net\lwip\src\core\dhcp.c + ../../components/net/lwip-1.4.1/src/core/dhcp.c + + dns.c 1 - ..\..\components\net\lwip\src\core\dns.c + ../../components/net/lwip-1.4.1/src/core/dns.c + + init.c 1 - ..\..\components\net\lwip\src\core\init.c + ../../components/net/lwip-1.4.1/src/core/init.c + + memp.c 1 - ..\..\components\net\lwip\src\core\memp.c + ../../components/net/lwip-1.4.1/src/core/memp.c + + netif.c 1 - ..\..\components\net\lwip\src\core\netif.c + ../../components/net/lwip-1.4.1/src/core/netif.c + + pbuf.c 1 - ..\..\components\net\lwip\src\core\pbuf.c + ../../components/net/lwip-1.4.1/src/core/pbuf.c + + raw.c 1 - ..\..\components\net\lwip\src\core\raw.c + ../../components/net/lwip-1.4.1/src/core/raw.c + + stats.c 1 - ..\..\components\net\lwip\src\core\stats.c + ../../components/net/lwip-1.4.1/src/core/stats.c + + sys.c 1 - ..\..\components\net\lwip\src\core\sys.c + ../../components/net/lwip-1.4.1/src/core/sys.c + + tcp.c 1 - ..\..\components\net\lwip\src\core\tcp.c + ../../components/net/lwip-1.4.1/src/core/tcp.c + + tcp_in.c 1 - ..\..\components\net\lwip\src\core\tcp_in.c + ../../components/net/lwip-1.4.1/src/core/tcp_in.c + + tcp_out.c 1 - ..\..\components\net\lwip\src\core\tcp_out.c + ../../components/net/lwip-1.4.1/src/core/tcp_out.c + + timers.c 1 - ..\..\components\net\lwip\src\core\timers.c + ../../components/net/lwip-1.4.1/src/core/timers.c + + udp.c 1 - ..\..\components\net\lwip\src\core\udp.c + ../../components/net/lwip-1.4.1/src/core/udp.c + + autoip.c 1 - ..\..\components\net\lwip\src\core\ipv4\autoip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c + + icmp.c 1 - ..\..\components\net\lwip\src\core\ipv4\icmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c + + igmp.c 1 - ..\..\components\net\lwip\src\core\ipv4\igmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c + + inet.c 1 - ..\..\components\net\lwip\src\core\ipv4\inet.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c + + inet_chksum.c 1 - ..\..\components\net\lwip\src\core\ipv4\inet_chksum.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c + + ip.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + + ip_addr.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip_addr.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + + ip_frag.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip_frag.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + + etharp.c 1 - ..\..\components\net\lwip\src\netif\etharp.c + ../../components/net/lwip-1.4.1/src/netif/etharp.c + + ethernetif.c 1 - ..\..\components\net\lwip\src\netif\ethernetif.c + ../../components/net/lwip-1.4.1/src/netif/ethernetif.c + + slipif.c 1 - ..\..\components\net\lwip\src\netif\slipif.c + ../../components/net/lwip-1.4.1/src/netif/slipif.c - From e38f3aa39cfa1b8743853972841614565de46dcb Mon Sep 17 00:00:00 2001 From: BernardXiong Date: Mon, 11 May 2015 21:10:25 +0800 Subject: [PATCH 06/18] [BSP] Update Keil MDK project files. --- bsp/CME_M7/project.uvopt | 1443 +----------------------------- bsp/CME_M7/project.uvproj | 880 +++++++++++------- bsp/CME_M7/rtconfig.py | 2 +- bsp/asm9260t/project.uvproj | 930 +++++++++++++++++++ bsp/frdm-k64f/project.uvproj | 134 +-- bsp/lm4f232/project.uvproj | 644 +++++++------- bsp/lpc178x/project.uvproj | 416 +++++---- bsp/lpc2478/project.uvproj | 364 +++++--- bsp/lpc408x/project.uvproj | 1031 +++++++++++++++++++++ bsp/mb9bf506r/project.uvproj | 406 +++++---- bsp/mb9bf568r/project.uvproj | 682 ++++++++++++++ bsp/mini2440/project.Uv2 | 431 +++++++++ bsp/nrf51822/project.uvproj | 646 ++++++++++++++ bsp/sam7x/project.uvproj | 487 ++++++---- bsp/stm32f0x/project.uvproj | 642 ++++++++++---- bsp/stm32f107/project.uvopt | 1628 +--------------------------------- bsp/stm32f107/project.uvproj | 886 ++++++++++-------- bsp/stm32f10x/project.Uv2 | 145 ++- bsp/stm32f20x/project.uvproj | 691 ++++++++------- bsp/stm32f40x/project.uvproj | 177 ++-- bsp/tm4c129x/project.uvproj | 1210 +++++++++++++++++++++++++ 21 files changed, 8387 insertions(+), 5488 deletions(-) create mode 100644 bsp/asm9260t/project.uvproj create mode 100644 bsp/lpc408x/project.uvproj create mode 100644 bsp/mb9bf568r/project.uvproj create mode 100644 bsp/mini2440/project.Uv2 create mode 100644 bsp/nrf51822/project.uvproj create mode 100644 bsp/tm4c129x/project.uvproj diff --git a/bsp/CME_M7/project.uvopt b/bsp/CME_M7/project.uvopt index 930f62b502..21805b8fa9 100644 --- a/bsp/CME_M7/project.uvopt +++ b/bsp/CME_M7/project.uvopt @@ -113,26 +113,6 @@ CapitalMicro\BIN\cmagdi.dll - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - cmagdi - -U-O6 -O6 -S3 -C1 -J0 -H127.0.0.1 -P2508 -N00("M7") -D00(20EC06CB) -L00(10) -N01("Cortex-M3") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO0 -FD20000000 -FC800 -FN0 - - - 0 - DLGUARM - (105=-1,-1,-1,-1,0) - 0 UL2CM3 @@ -156,7 +136,7 @@ 0 0 0 - 1 + 0 0 0 0 @@ -180,1430 +160,11 @@ - Applications - 1 - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - 0 - applications\application.c - application.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 0 - 0 - applications\led.c - led.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - 0 - applications\startup.c - startup.c - 0 - 0 - - - - - CMSIS + Source Group 1 0 0 0 0 - - 2 - 4 - 1 - 0 - 0 - 0 - 0 - CMSIS\CME_M7\system_cmem7.c - system_cmem7.c - 0 - 0 - - - 2 - 5 - 2 - 0 - 0 - 0 - 0 - CMSIS\CME_M7\startup\arm\startup_cmem7.s - startup_cmem7.s - 0 - 0 - - - - - Drivers - 1 - 0 - 0 - 0 - - 3 - 6 - 1 - 0 - 0 - 0 - 0 - drivers\board.c - board.c - 0 - 0 - - - 3 - 7 - 1 - 0 - 0 - 0 - 0 - drivers\uart.c - uart.c - 0 - 0 - - - 3 - 8 - 1 - 0 - 0 - 0 - 0 - drivers\emac.c - emac.c - 0 - 0 - - - 3 - 9 - 1 - 0 - 0 - 0 - 0 - drivers\app_phy.c - app_phy.c - 0 - 0 - - - - - StdPeriph_Driver - 0 - 0 - 0 - 0 - - 4 - 10 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_adc.c - cmem7_adc.c - 0 - 0 - - - 4 - 11 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_aes.c - cmem7_aes.c - 0 - 0 - - - 4 - 12 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_can.c - cmem7_can.c - 0 - 0 - - - 4 - 13 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_ddr.c - cmem7_ddr.c - 0 - 0 - - - 4 - 14 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_dma.c - cmem7_dma.c - 0 - 0 - - - 4 - 15 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_efuse.c - cmem7_efuse.c - 0 - 0 - - - 4 - 16 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_eth.c - cmem7_eth.c - 0 - 0 - - - 4 - 17 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_flash.c - cmem7_flash.c - 0 - 0 - - - 4 - 18 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_gpio.c - cmem7_gpio.c - 0 - 0 - - - 4 - 19 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_i2c.c - cmem7_i2c.c - 0 - 0 - - - 4 - 20 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_misc.c - cmem7_misc.c - 0 - 0 - - - 4 - 21 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_rtc.c - cmem7_rtc.c - 0 - 0 - - - 4 - 22 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_spi.c - cmem7_spi.c - 0 - 0 - - - 4 - 23 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_tim.c - cmem7_tim.c - 0 - 0 - - - 4 - 24 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_uart.c - cmem7_uart.c - 0 - 0 - - - 4 - 25 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_usb.c - cmem7_usb.c - 0 - 0 - - - 4 - 26 - 1 - 0 - 0 - 0 - 0 - StdPeriph_Driver\src\cmem7_wdg.c - cmem7_wdg.c - 0 - 0 - - - - - Kernel - 0 - 0 - 0 - 0 - - 5 - 27 - 1 - 0 - 0 - 0 - 0 - ..\..\src\clock.c - clock.c - 0 - 0 - - - 5 - 28 - 1 - 0 - 0 - 0 - 0 - ..\..\src\device.c - device.c - 0 - 0 - - - 5 - 29 - 1 - 0 - 0 - 0 - 0 - ..\..\src\idle.c - idle.c - 0 - 0 - - - 5 - 30 - 1 - 0 - 0 - 0 - 0 - ..\..\src\ipc.c - ipc.c - 0 - 0 - - - 5 - 31 - 1 - 0 - 0 - 0 - 0 - ..\..\src\irq.c - irq.c - 0 - 0 - - - 5 - 32 - 1 - 0 - 0 - 0 - 0 - ..\..\src\kservice.c - kservice.c - 0 - 0 - - - 5 - 33 - 1 - 0 - 0 - 0 - 0 - ..\..\src\mem.c - mem.c - 0 - 0 - - - 5 - 34 - 1 - 0 - 0 - 0 - 0 - ..\..\src\mempool.c - mempool.c - 0 - 0 - - - 5 - 35 - 1 - 0 - 0 - 0 - 0 - ..\..\src\object.c - object.c - 0 - 0 - - - 5 - 36 - 1 - 0 - 0 - 0 - 0 - ..\..\src\scheduler.c - scheduler.c - 0 - 0 - - - 5 - 37 - 1 - 0 - 0 - 0 - 0 - ..\..\src\thread.c - thread.c - 0 - 0 - - - 5 - 38 - 1 - 0 - 0 - 0 - 0 - ..\..\src\timer.c - timer.c - 0 - 0 - - - - - CORTEX-M3 - 0 - 0 - 0 - 0 - - 6 - 39 - 1 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\cortex-m3\cpuport.c - cpuport.c - 0 - 0 - - - 6 - 40 - 2 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\cortex-m3\context_rvds.S - context_rvds.S - 0 - 0 - - - 6 - 41 - 1 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 6 - 42 - 1 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\common\div0.c - div0.c - 0 - 0 - - - 6 - 43 - 1 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\common\showmem.c - showmem.c - 0 - 0 - - - - - DeviceDrivers - 0 - 0 - 0 - 0 - - 7 - 44 - 1 - 0 - 0 - 0 - 0 - ..\..\components\drivers\serial\serial.c - serial.c - 0 - 0 - - - 7 - 45 - 1 - 0 - 0 - 0 - 0 - ..\..\components\drivers\src\completion.c - completion.c - 0 - 0 - - - 7 - 46 - 1 - 0 - 0 - 0 - 0 - ..\..\components\drivers\src\dataqueue.c - dataqueue.c - 0 - 0 - - - 7 - 47 - 1 - 0 - 0 - 0 - 0 - ..\..\components\drivers\src\pipe.c - pipe.c - 0 - 0 - - - 7 - 48 - 1 - 0 - 0 - 0 - 0 - ..\..\components\drivers\src\portal.c - portal.c - 0 - 0 - - - 7 - 49 - 1 - 0 - 0 - 0 - 0 - ..\..\components\drivers\src\ringbuffer.c - ringbuffer.c - 0 - 0 - - - 7 - 50 - 1 - 0 - 0 - 0 - 0 - ..\..\components\drivers\src\workqueue.c - workqueue.c - 0 - 0 - - - - - finsh - 0 - 0 - 0 - 0 - - 8 - 51 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\shell.c - shell.c - 0 - 0 - - - 8 - 52 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\symbol.c - symbol.c - 0 - 0 - - - 8 - 53 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\cmd.c - cmd.c - 0 - 0 - - - 8 - 54 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\msh_cmd.c - msh_cmd.c - 0 - 0 - - - 8 - 55 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\msh.c - msh.c - 0 - 0 - - - 8 - 56 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_compiler.c - finsh_compiler.c - 0 - 0 - - - 8 - 57 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_error.c - finsh_error.c - 0 - 0 - - - 8 - 58 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_heap.c - finsh_heap.c - 0 - 0 - - - 8 - 59 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_init.c - finsh_init.c - 0 - 0 - - - 8 - 60 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_node.c - finsh_node.c - 0 - 0 - - - 8 - 61 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_ops.c - finsh_ops.c - 0 - 0 - - - 8 - 62 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_parser.c - finsh_parser.c - 0 - 0 - - - 8 - 63 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_var.c - finsh_var.c - 0 - 0 - - - 8 - 64 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_vm.c - finsh_vm.c - 0 - 0 - - - 8 - 65 - 1 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_token.c - finsh_token.c - 0 - 0 - - - - - Components - 0 - 0 - 0 - 0 - - 9 - 66 - 1 - 0 - 0 - 0 - 0 - ..\..\components\init\components.c - components.c - 0 - 0 - - - - - libc - 0 - 0 - 0 - 0 - - 10 - 67 - 1 - 0 - 0 - 0 - 0 - ..\..\components\libc\armlibc\mem_std.c - mem_std.c - 0 - 0 - - - 10 - 68 - 1 - 0 - 0 - 0 - 0 - ..\..\components\libc\armlibc\stubs.c - stubs.c - 0 - 0 - - - - - LwIP - 0 - 0 - 0 - 0 - - 11 - 69 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\api_lib.c - api_lib.c - 0 - 0 - - - 11 - 70 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\api_msg.c - api_msg.c - 0 - 0 - - - 11 - 71 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\err.c - err.c - 0 - 0 - - - 11 - 72 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\netbuf.c - netbuf.c - 0 - 0 - - - 11 - 73 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\netdb.c - netdb.c - 0 - 0 - - - 11 - 74 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\netifapi.c - netifapi.c - 0 - 0 - - - 11 - 75 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\sockets.c - sockets.c - 0 - 0 - - - 11 - 76 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\api\tcpip.c - tcpip.c - 0 - 0 - - - 11 - 77 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\arch\sys_arch.c - sys_arch.c - 0 - 0 - - - 11 - 78 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\def.c - def.c - 0 - 0 - - - 11 - 79 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\dhcp.c - dhcp.c - 0 - 0 - - - 11 - 80 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\dns.c - dns.c - 0 - 0 - - - 11 - 81 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\init.c - init.c - 0 - 0 - - - 11 - 82 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\memp.c - memp.c - 0 - 0 - - - 11 - 83 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\netif.c - netif.c - 0 - 0 - - - 11 - 84 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\pbuf.c - pbuf.c - 0 - 0 - - - 11 - 85 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\raw.c - raw.c - 0 - 0 - - - 11 - 86 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\stats.c - stats.c - 0 - 0 - - - 11 - 87 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\sys.c - sys.c - 0 - 0 - - - 11 - 88 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\tcp.c - tcp.c - 0 - 0 - - - 11 - 89 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\tcp_in.c - tcp_in.c - 0 - 0 - - - 11 - 90 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\tcp_out.c - tcp_out.c - 0 - 0 - - - 11 - 91 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\timers.c - timers.c - 0 - 0 - - - 11 - 92 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\udp.c - udp.c - 0 - 0 - - - 11 - 93 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\autoip.c - autoip.c - 0 - 0 - - - 11 - 94 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\icmp.c - icmp.c - 0 - 0 - - - 11 - 95 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\igmp.c - igmp.c - 0 - 0 - - - 11 - 96 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\inet.c - inet.c - 0 - 0 - - - 11 - 97 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\inet_chksum.c - inet_chksum.c - 0 - 0 - - - 11 - 98 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\ip.c - ip.c - 0 - 0 - - - 11 - 99 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_addr.c - ip_addr.c - 0 - 0 - - - 11 - 100 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_frag.c - ip_frag.c - 0 - 0 - - - 11 - 101 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\netif\etharp.c - etharp.c - 0 - 0 - - - 11 - 102 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\netif\ethernetif.c - ethernetif.c - 0 - 0 - - - 11 - 103 - 1 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip-1.4.1\src\netif\slipif.c - slipif.c - 0 - 0 - diff --git a/bsp/CME_M7/project.uvproj b/bsp/CME_M7/project.uvproj index 2eba13d595..9a1283bdcc 100644 --- a/bsp/CME_M7/project.uvproj +++ b/bsp/CME_M7/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- rtthread @@ -14,28 +11,31 @@ ARMCM3 ARM + ARM.CMSIS.4.1.0 + http://www.keil.com/pack/ CPUTYPE("Cortex-M3") CLOCK(10000000) ESEL ELITTLE - - - + + + 0 $$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h - - - - - - - - - + + + + + + + + + $$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd + 0 0 - - - - - + + + + + 0 0 @@ -57,8 +57,8 @@ 0 0 - - + + 0 0 0 @@ -67,21 +67,23 @@ 0 0 - - + + 0 0 + 0 + 0 0 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 - + 0 @@ -95,8 +97,9 @@ 0 0 3 - - + + + 1 SARMCM3.DLL @@ -104,7 +107,7 @@ DCM.DLL -pCM3 SARMCM3.DLL - + TCM.DLL -pCM3 @@ -126,6 +129,7 @@ 1 1 0 + 1 1 @@ -137,22 +141,24 @@ 0 1 1 + 1 + 1 0 - -1 + 17 - - - - - + + + + + - - - - - + + + + + CapitalMicro\BIN\cmagdi.dll @@ -168,7 +174,11 @@ 0 BIN\UL2CM3.DLL "" () - + + + + + 0 @@ -200,7 +210,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -331,7 +341,7 @@ 0x0 - + 1 @@ -347,11 +357,13 @@ 2 0 0 + 0 + 0 - + RT_USING_ARM_LIBC - - applications;.;CMSIS\CME_M7;..\..\components\CMSIS\Include;drivers;StdPeriph_Driver\inc;..\..\include;..\..\libcpu\arm\cortex-m3;..\..\libcpu\arm\common;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\init;..\..\components\libc\armlibc;..\..\components\net\lwip-1.4.1\src;..\..\components\net\lwip-1.4.1\src\include;..\..\components\net\lwip-1.4.1\src\include\ipv4;..\..\components\net\lwip-1.4.1\src\arch\include;..\..\components\net\lwip-1.4.1\src\include\netif + + StdPeriph_Driver/inc;applications;.;drivers;CMSIS/CME_M7;../../components/CMSIS/Include;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/libc/armlibc;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif @@ -363,11 +375,12 @@ 0 0 0 + 0 - - - - + + + + @@ -379,48 +392,160 @@ 0 0x00000000 0x00000000 + CME_M7.sct - - - --keep __fsym_* --keep __vsym_* --keep __rt_init* - - + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + StdPeriph_Driver + + + cmem7_adc.c + 1 + StdPeriph_Driver/src/cmem7_adc.c + + + + + cmem7_aes.c + 1 + StdPeriph_Driver/src/cmem7_aes.c + + + + + cmem7_can.c + 1 + StdPeriph_Driver/src/cmem7_can.c + + + + + cmem7_ddr.c + 1 + StdPeriph_Driver/src/cmem7_ddr.c + + + + + cmem7_dma.c + 1 + StdPeriph_Driver/src/cmem7_dma.c + + + + + cmem7_efuse.c + 1 + StdPeriph_Driver/src/cmem7_efuse.c + + + + + cmem7_eth.c + 1 + StdPeriph_Driver/src/cmem7_eth.c + + + + + cmem7_flash.c + 1 + StdPeriph_Driver/src/cmem7_flash.c + + + + + cmem7_gpio.c + 1 + StdPeriph_Driver/src/cmem7_gpio.c + + + + + cmem7_i2c.c + 1 + StdPeriph_Driver/src/cmem7_i2c.c + + + + + cmem7_misc.c + 1 + StdPeriph_Driver/src/cmem7_misc.c + + + + + cmem7_rtc.c + 1 + StdPeriph_Driver/src/cmem7_rtc.c + + + + + cmem7_spi.c + 1 + StdPeriph_Driver/src/cmem7_spi.c + + + + + cmem7_tim.c + 1 + StdPeriph_Driver/src/cmem7_tim.c + + + + + cmem7_uart.c + 1 + StdPeriph_Driver/src/cmem7_uart.c + + + + + cmem7_usb.c + 1 + StdPeriph_Driver/src/cmem7_usb.c + + + + + cmem7_wdg.c + 1 + StdPeriph_Driver/src/cmem7_wdg.c + + + Applications application.c 1 - applications\application.c + applications/application.c + + led.c 1 - applications\led.c + applications/led.c + + startup.c 1 - applications\startup.c - - - - - CMSIS - - - system_cmem7.c - 1 - CMSIS\CME_M7\system_cmem7.c - - - startup_cmem7.s - 2 - CMSIS\CME_M7\startup\arm\startup_cmem7.s + applications/startup.c @@ -430,112 +555,45 @@ board.c 1 - drivers\board.c + drivers/board.c + + uart.c 1 - drivers\uart.c + drivers/uart.c + + emac.c 1 - drivers\emac.c + drivers/emac.c + + app_phy.c 1 - drivers\app_phy.c + drivers/app_phy.c - StdPeriph_Driver + CMSIS - cmem7_adc.c + system_cmem7.c 1 - StdPeriph_Driver\src\cmem7_adc.c + CMSIS/CME_M7/system_cmem7.c + + - cmem7_aes.c - 1 - StdPeriph_Driver\src\cmem7_aes.c - - - cmem7_can.c - 1 - StdPeriph_Driver\src\cmem7_can.c - - - cmem7_ddr.c - 1 - StdPeriph_Driver\src\cmem7_ddr.c - - - cmem7_dma.c - 1 - StdPeriph_Driver\src\cmem7_dma.c - - - cmem7_efuse.c - 1 - StdPeriph_Driver\src\cmem7_efuse.c - - - cmem7_eth.c - 1 - StdPeriph_Driver\src\cmem7_eth.c - - - cmem7_flash.c - 1 - StdPeriph_Driver\src\cmem7_flash.c - - - cmem7_gpio.c - 1 - StdPeriph_Driver\src\cmem7_gpio.c - - - cmem7_i2c.c - 1 - StdPeriph_Driver\src\cmem7_i2c.c - - - cmem7_misc.c - 1 - StdPeriph_Driver\src\cmem7_misc.c - - - cmem7_rtc.c - 1 - StdPeriph_Driver\src\cmem7_rtc.c - - - cmem7_spi.c - 1 - StdPeriph_Driver\src\cmem7_spi.c - - - cmem7_tim.c - 1 - StdPeriph_Driver\src\cmem7_tim.c - - - cmem7_uart.c - 1 - StdPeriph_Driver\src\cmem7_uart.c - - - cmem7_usb.c - 1 - StdPeriph_Driver\src\cmem7_usb.c - - - cmem7_wdg.c - 1 - StdPeriph_Driver\src\cmem7_wdg.c + startup_cmem7.s + 2 + CMSIS/CME_M7/startup/arm/startup_cmem7.s @@ -545,62 +603,91 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + device.c 1 - ..\..\src\device.c + ../../src/device.c + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + mem.c 1 - ..\..\src\mem.c + ../../src/mem.c + + mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -610,157 +697,35 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c + ../../libcpu/arm/cortex-m3/cpuport.c + + context_rvds.S 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S + ../../libcpu/arm/cortex-m3/context_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c - - - - - DeviceDrivers - - - serial.c - 1 - ..\..\components\drivers\serial\serial.c - - - completion.c - 1 - ..\..\components\drivers\src\completion.c - - - dataqueue.c - 1 - ..\..\components\drivers\src\dataqueue.c - - - pipe.c - 1 - ..\..\components\drivers\src\pipe.c - - - portal.c - 1 - ..\..\components\drivers\src\portal.c - - - ringbuffer.c - 1 - ..\..\components\drivers\src\ringbuffer.c - - - workqueue.c - 1 - ..\..\components\drivers\src\workqueue.c - - - - - finsh - - - shell.c - 1 - ..\..\components\finsh\shell.c - - - symbol.c - 1 - ..\..\components\finsh\symbol.c - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - msh_cmd.c - 1 - ..\..\components\finsh\msh_cmd.c - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - - - Components - - - components.c - 1 - ..\..\components\init\components.c + ../../libcpu/arm/common/showmem.c @@ -770,12 +735,174 @@ mem_std.c 1 - ..\..\components\libc\armlibc\mem_std.c + ../../components/libc/armlibc/mem_std.c + + stubs.c 1 - ..\..\components\libc\armlibc\stubs.c + ../../components/libc/armlibc/stubs.c + + + + + DeviceDrivers + + + serial.c + 1 + ../../components/drivers/serial/serial.c + + + + + completion.c + 1 + ../../components/drivers/src/completion.c + + + + + dataqueue.c + 1 + ../../components/drivers/src/dataqueue.c + + + + + pipe.c + 1 + ../../components/drivers/src/pipe.c + + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + + + ringbuffer.c + 1 + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c + + + + + finsh + + + shell.c + 1 + ../../components/finsh/shell.c + + + + + symbol.c + 1 + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + msh_cmd.c + 1 + ../../components/finsh/msh_cmd.c + + + + + msh.c + 1 + ../../components/finsh/msh.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c @@ -785,182 +912,249 @@ api_lib.c 1 - ..\..\components\net\lwip-1.4.1\src\api\api_lib.c + ../../components/net/lwip-1.4.1/src/api/api_lib.c + + api_msg.c 1 - ..\..\components\net\lwip-1.4.1\src\api\api_msg.c + ../../components/net/lwip-1.4.1/src/api/api_msg.c + + err.c 1 - ..\..\components\net\lwip-1.4.1\src\api\err.c + ../../components/net/lwip-1.4.1/src/api/err.c + + netbuf.c 1 - ..\..\components\net\lwip-1.4.1\src\api\netbuf.c + ../../components/net/lwip-1.4.1/src/api/netbuf.c + + netdb.c 1 - ..\..\components\net\lwip-1.4.1\src\api\netdb.c + ../../components/net/lwip-1.4.1/src/api/netdb.c + + netifapi.c 1 - ..\..\components\net\lwip-1.4.1\src\api\netifapi.c + ../../components/net/lwip-1.4.1/src/api/netifapi.c + + sockets.c 1 - ..\..\components\net\lwip-1.4.1\src\api\sockets.c + ../../components/net/lwip-1.4.1/src/api/sockets.c + + tcpip.c 1 - ..\..\components\net\lwip-1.4.1\src\api\tcpip.c + ../../components/net/lwip-1.4.1/src/api/tcpip.c + + sys_arch.c 1 - ..\..\components\net\lwip-1.4.1\src\arch\sys_arch.c + ../../components/net/lwip-1.4.1/src/arch/sys_arch.c + + def.c 1 - ..\..\components\net\lwip-1.4.1\src\core\def.c + ../../components/net/lwip-1.4.1/src/core/def.c + + dhcp.c 1 - ..\..\components\net\lwip-1.4.1\src\core\dhcp.c + ../../components/net/lwip-1.4.1/src/core/dhcp.c + + dns.c 1 - ..\..\components\net\lwip-1.4.1\src\core\dns.c + ../../components/net/lwip-1.4.1/src/core/dns.c + + init.c 1 - ..\..\components\net\lwip-1.4.1\src\core\init.c + ../../components/net/lwip-1.4.1/src/core/init.c + + memp.c 1 - ..\..\components\net\lwip-1.4.1\src\core\memp.c + ../../components/net/lwip-1.4.1/src/core/memp.c + + netif.c 1 - ..\..\components\net\lwip-1.4.1\src\core\netif.c + ../../components/net/lwip-1.4.1/src/core/netif.c + + pbuf.c 1 - ..\..\components\net\lwip-1.4.1\src\core\pbuf.c + ../../components/net/lwip-1.4.1/src/core/pbuf.c + + raw.c 1 - ..\..\components\net\lwip-1.4.1\src\core\raw.c + ../../components/net/lwip-1.4.1/src/core/raw.c + + stats.c 1 - ..\..\components\net\lwip-1.4.1\src\core\stats.c + ../../components/net/lwip-1.4.1/src/core/stats.c + + sys.c 1 - ..\..\components\net\lwip-1.4.1\src\core\sys.c + ../../components/net/lwip-1.4.1/src/core/sys.c + + tcp.c 1 - ..\..\components\net\lwip-1.4.1\src\core\tcp.c + ../../components/net/lwip-1.4.1/src/core/tcp.c + + tcp_in.c 1 - ..\..\components\net\lwip-1.4.1\src\core\tcp_in.c + ../../components/net/lwip-1.4.1/src/core/tcp_in.c + + tcp_out.c 1 - ..\..\components\net\lwip-1.4.1\src\core\tcp_out.c + ../../components/net/lwip-1.4.1/src/core/tcp_out.c + + timers.c 1 - ..\..\components\net\lwip-1.4.1\src\core\timers.c + ../../components/net/lwip-1.4.1/src/core/timers.c + + udp.c 1 - ..\..\components\net\lwip-1.4.1\src\core\udp.c + ../../components/net/lwip-1.4.1/src/core/udp.c + + autoip.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\autoip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c + + icmp.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\icmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c + + igmp.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\igmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c + + inet.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\inet.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c + + inet_chksum.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\inet_chksum.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c + + ip.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\ip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + + ip_addr.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_addr.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + + ip_frag.c 1 - ..\..\components\net\lwip-1.4.1\src\core\ipv4\ip_frag.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + + etharp.c 1 - ..\..\components\net\lwip-1.4.1\src\netif\etharp.c + ../../components/net/lwip-1.4.1/src/netif/etharp.c + + ethernetif.c 1 - ..\..\components\net\lwip-1.4.1\src\netif\ethernetif.c + ../../components/net/lwip-1.4.1/src/netif/ethernetif.c + + slipif.c 1 - ..\..\components\net\lwip-1.4.1\src\netif\slipif.c + ../../components/net/lwip-1.4.1/src/netif/slipif.c - diff --git a/bsp/CME_M7/rtconfig.py b/bsp/CME_M7/rtconfig.py index ea750bc4f7..57d162ffd2 100644 --- a/bsp/CME_M7/rtconfig.py +++ b/bsp/CME_M7/rtconfig.py @@ -24,7 +24,7 @@ if os.getenv('RTT_EXEC_PATH'): if os.getenv('RTT_ROOT'): RTT_ROOT = os.getenv('RTT_ROOT') else: - RTT_ROOT = os.path.normpath(os.getcwd()) + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') BUILD = 'debug' diff --git a/bsp/asm9260t/project.uvproj b/bsp/asm9260t/project.uvproj new file mode 100644 index 0000000000..8d44d7636b --- /dev/null +++ b/bsp/asm9260t/project.uvproj @@ -0,0 +1,930 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rtthread + 0x4 + ARM-ADS + + + AT91SAM9260 + Atmel + IRAM(0x200000-0x200FFF) IRAM2(0x300000-0x300FFF) IROM(0x100000-0x107FFF) CLOCK(18432000) CPUTYPE(ARM926EJ-S) + + "STARTUP\Atmel\SAM9260.s" ("Atmel AT91SAM9260 Startup Code") + UL2ARM(-UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00) + 4210 + AT91SAM9260.H + + + + + + + + + + + 0 + 0 + + + + Atmel\SAM9260\ + Atmel\SAM9260\ + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + template + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARM.DLL + -cAT91SAM9260 + DARMATS9.DLL + -p91SAM9260 + SARM.DLL + + TARMATS9.DLL + -p91SAM9260 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 0 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 5 + + + + + + + + + + + + + .\jlink\at91sam9260.ini + Segger\JLTAgdi.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4096 + + 1 + BIN\UL2ARM.DLL + "" () + .\jlink\at91sam9260.ini + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + ARM926EJ-S + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x200000 + 0x1000 + + + 1 + 0x100000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x20000000 + 0x800000 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x100000 + 0x8000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x20800000 + 0x1800000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x200000 + 0x1000 + + + 0 + 0x300000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + RT_USING_ARM_LIBC + + applications;.;drivers;platform;../../include;../../libcpu/arm/arm926;../../libcpu/arm/common;../../components/pthreads;../../components/libc/armlibc;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/finsh + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x20000000 + 0x20800000 + + .\at91sam9260_ram.scat + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + Applications + + + application.c + 1 + applications/application.c + + + + + startup.c + 1 + applications/startup.c + + + + + Drivers + + + board.c + 1 + drivers/board.c + + + + + usart.c + 1 + drivers/usart.c + + + + + led.c + 1 + drivers/led.c + + + + + platform + + + gpio.c + 1 + platform/gpio.c + + + + + interrupt.c + 1 + platform/interrupt.c + + + + + reset.c + 1 + platform/reset.c + + + + + rt_low_level_init.c + 1 + platform/rt_low_level_init.c + + + + + system_clock.c + 1 + platform/system_clock.c + + + + + timer0.c + 1 + platform/timer0.c + + + + + uart.c + 1 + platform/uart.c + + + + + Kernel + + + clock.c + 1 + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c + + + + + device.c + 1 + ../../src/device.c + + + + + idle.c + 1 + ../../src/idle.c + + + + + ipc.c + 1 + ../../src/ipc.c + + + + + irq.c + 1 + ../../src/irq.c + + + + + kservice.c + 1 + ../../src/kservice.c + + + + + mempool.c + 1 + ../../src/mempool.c + + + + + object.c + 1 + ../../src/object.c + + + + + scheduler.c + 1 + ../../src/scheduler.c + + + + + slab.c + 1 + ../../src/slab.c + + + + + thread.c + 1 + ../../src/thread.c + + + + + timer.c + 1 + ../../src/timer.c + + + + + ARM926 + + + cpuport.c + 1 + ../../libcpu/arm/arm926/cpuport.c + + + + + mmu.c + 1 + ../../libcpu/arm/arm926/mmu.c + + + + + stack.c + 1 + ../../libcpu/arm/arm926/stack.c + + + + + trap.c + 1 + ../../libcpu/arm/arm926/trap.c + + + + + context_rvds.S + 2 + ../../libcpu/arm/arm926/context_rvds.S + + + + + start_rvds.S + 2 + ../../libcpu/arm/arm926/start_rvds.S + + + + + backtrace.c + 1 + ../../libcpu/arm/common/backtrace.c + + + + + div0.c + 1 + ../../libcpu/arm/common/div0.c + + + + + showmem.c + 1 + ../../libcpu/arm/common/showmem.c + + + + + pthreads + + + clock_time.c + 1 + ../../components/pthreads/clock_time.c + + + + + mqueue.c + 1 + ../../components/pthreads/mqueue.c + + + + + pthread.c + 1 + ../../components/pthreads/pthread.c + + + + + pthread_attr.c + 1 + ../../components/pthreads/pthread_attr.c + + + + + pthread_barrier.c + 1 + ../../components/pthreads/pthread_barrier.c + + + + + pthread_cond.c + 1 + ../../components/pthreads/pthread_cond.c + + + + + pthread_mutex.c + 1 + ../../components/pthreads/pthread_mutex.c + + + + + pthread_rwlock.c + 1 + ../../components/pthreads/pthread_rwlock.c + + + + + pthread_spin.c + 1 + ../../components/pthreads/pthread_spin.c + + + + + pthread_tls.c + 1 + ../../components/pthreads/pthread_tls.c + + + + + sched.c + 1 + ../../components/pthreads/sched.c + + + + + semaphore.c + 1 + ../../components/pthreads/semaphore.c + + + + + libc + + + mem_std.c + 1 + ../../components/libc/armlibc/mem_std.c + + + + + stubs.c + 1 + ../../components/libc/armlibc/stubs.c + + + + + DeviceDrivers + + + serial.c + 1 + ../../components/drivers/serial/serial.c + + + + + i2c_core.c + 1 + ../../components/drivers/i2c/i2c_core.c + + + + + i2c_dev.c + 1 + ../../components/drivers/i2c/i2c_dev.c + + + + + i2c-bit-ops.c + 1 + ../../components/drivers/i2c/i2c-bit-ops.c + + + + + completion.c + 1 + ../../components/drivers/src/completion.c + + + + + dataqueue.c + 1 + ../../components/drivers/src/dataqueue.c + + + + + pipe.c + 1 + ../../components/drivers/src/pipe.c + + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + + + ringbuffer.c + 1 + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c + + + + + finsh + + + shell.c + 1 + ../../components/finsh/shell.c + + + + + symbol.c + 1 + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c + + + + + + + diff --git a/bsp/frdm-k64f/project.uvproj b/bsp/frdm-k64f/project.uvproj index dad542e65d..c9ccb80717 100644 --- a/bsp/frdm-k64f/project.uvproj +++ b/bsp/frdm-k64f/project.uvproj @@ -354,7 +354,7 @@ - .;..\..\components\drivers\include;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;applications;board;device;device\MK64F12 + board;applications;.;device;device/MK64F12;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh @@ -385,51 +385,51 @@ - --keep __fsym_* --keep __vsym_* + --keep *.o(FSymTab) --keep *.o(VSymTab) - - Applications - - - application.c - 1 - applications\application.c - - - - - startup.c - 1 - applications\startup.c - - - Board board.c 1 - board\board.c + board/board.c drv_uart.c 1 - board\drv_uart.c + board/drv_uart.c led.c 1 - board\led.c + board/led.c + + + + + Applications + + + application.c + 1 + applications/application.c + + + + + startup.c + 1 + applications/startup.c @@ -439,14 +439,14 @@ system_MK64F12.c 1 - device\MK64F12\system_MK64F12.c + device/MK64F12/system_MK64F12.c startup_MK64F12.s 2 - device\TOOLCHAIN_ARM_STD\startup_MK64F12.s + device/TOOLCHAIN_ARM_STD/startup_MK64F12.s @@ -456,84 +456,91 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c device.c 1 - ..\..\src\device.c + ../../src/device.c idle.c 1 - ..\..\src\idle.c + ../../src/idle.c ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c irq.c 1 - ..\..\src\irq.c + ../../src/irq.c kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c mem.c 1 - ..\..\src\mem.c + ../../src/mem.c mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c object.c 1 - ..\..\src\object.c + ../../src/object.c scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c thread.c 1 - ..\..\src\thread.c + ../../src/thread.c timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -543,35 +550,35 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c + ../../libcpu/arm/cortex-m4/cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S + ../../libcpu/arm/cortex-m4/context_rvds.S backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c @@ -581,42 +588,49 @@ serial.c 1 - ..\..\components\drivers\serial\serial.c + ../../components/drivers/serial/serial.c completion.c 1 - ..\..\components\drivers\src\completion.c + ../../components/drivers/src/completion.c dataqueue.c 1 - ..\..\components\drivers\src\dataqueue.c + ../../components/drivers/src/dataqueue.c pipe.c 1 - ..\..\components\drivers\src\pipe.c + ../../components/drivers/src/pipe.c portal.c 1 - ..\..\components\drivers\src\portal.c + ../../components/drivers/src/portal.c ringbuffer.c 1 - ..\..\components\drivers\src\ringbuffer.c + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c @@ -626,91 +640,91 @@ shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c cmd.c 1 - ..\..\components\finsh\cmd.c + ../../components/finsh/cmd.c finsh_compiler.c 1 - ..\..\components\finsh\finsh_compiler.c + ../../components/finsh/finsh_compiler.c finsh_error.c 1 - ..\..\components\finsh\finsh_error.c + ../../components/finsh/finsh_error.c finsh_heap.c 1 - ..\..\components\finsh\finsh_heap.c + ../../components/finsh/finsh_heap.c finsh_init.c 1 - ..\..\components\finsh\finsh_init.c + ../../components/finsh/finsh_init.c finsh_node.c 1 - ..\..\components\finsh\finsh_node.c + ../../components/finsh/finsh_node.c finsh_ops.c 1 - ..\..\components\finsh\finsh_ops.c + ../../components/finsh/finsh_ops.c finsh_parser.c 1 - ..\..\components\finsh\finsh_parser.c + ../../components/finsh/finsh_parser.c finsh_var.c 1 - ..\..\components\finsh\finsh_var.c + ../../components/finsh/finsh_var.c finsh_vm.c 1 - ..\..\components\finsh\finsh_vm.c + ../../components/finsh/finsh_vm.c finsh_token.c 1 - ..\..\components\finsh\finsh_token.c + ../../components/finsh/finsh_token.c diff --git a/bsp/lm4f232/project.uvproj b/bsp/lm4f232/project.uvproj index 32700d1ba6..db6efd334d 100644 --- a/bsp/lm4f232/project.uvproj +++ b/bsp/lm4f232/project.uvproj @@ -343,7 +343,7 @@ PART_LM4F232H5QD - .;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;Libraries;applications;drivers + Libraries;applications;.;drivers;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/finsh @@ -373,27 +373,240 @@ - --keep __fsym_* --keep __vsym_* + --keep *.o(FSymTab) --keep *.o(VSymTab) + + Libraries + + + adc.c + 1 + Libraries/driverlib/adc.c + + + + + can.c + 1 + Libraries/driverlib/can.c + + + + + comp.c + 1 + Libraries/driverlib/comp.c + + + + + cpu.c + 1 + Libraries/driverlib/cpu.c + + + + + eeprom.c + 1 + Libraries/driverlib/eeprom.c + + + + + epi.c + 1 + Libraries/driverlib/epi.c + + + + + ethernet.c + 1 + Libraries/driverlib/ethernet.c + + + + + fan.c + 1 + Libraries/driverlib/fan.c + + + + + flash.c + 1 + Libraries/driverlib/flash.c + + + + + fpu.c + 1 + Libraries/driverlib/fpu.c + + + + + gpio.c + 1 + Libraries/driverlib/gpio.c + + + + + hibernate.c + 1 + Libraries/driverlib/hibernate.c + + + + + i2c.c + 1 + Libraries/driverlib/i2c.c + + + + + i2s.c + 1 + Libraries/driverlib/i2s.c + + + + + interrupt.c + 1 + Libraries/driverlib/interrupt.c + + + + + lpc.c + 1 + Libraries/driverlib/lpc.c + + + + + mpu.c + 1 + Libraries/driverlib/mpu.c + + + + + peci.c + 1 + Libraries/driverlib/peci.c + + + + + pwm.c + 1 + Libraries/driverlib/pwm.c + + + + + qei.c + 1 + Libraries/driverlib/qei.c + + + + + ssi.c + 1 + Libraries/driverlib/ssi.c + + + + + sysctl.c + 1 + Libraries/driverlib/sysctl.c + + + + + sysexc.c + 1 + Libraries/driverlib/sysexc.c + + + + + systick.c + 1 + Libraries/driverlib/systick.c + + + + + timer.c + 1 + Libraries/driverlib/timer.c + + + + + uart.c + 1 + Libraries/driverlib/uart.c + + + + + udma.c + 1 + Libraries/driverlib/udma.c + + + + + usb.c + 1 + Libraries/driverlib/usb.c + + + + + watchdog.c + 1 + Libraries/driverlib/watchdog.c + + + + + start_rvds.S + 2 + Libraries/startup/arm/start_rvds.S + + + Applications application.c 1 - applications\application.c + applications/application.c startup.c 1 - applications\startup.c + applications/startup.c @@ -403,227 +616,14 @@ board.c 1 - drivers\board.c + drivers/board.c serial.c 1 - drivers\serial.c - - - - - Libraries - - - adc.c - 1 - Libraries\driverlib\adc.c - - - - - can.c - 1 - Libraries\driverlib\can.c - - - - - comp.c - 1 - Libraries\driverlib\comp.c - - - - - cpu.c - 1 - Libraries\driverlib\cpu.c - - - - - eeprom.c - 1 - Libraries\driverlib\eeprom.c - - - - - epi.c - 1 - Libraries\driverlib\epi.c - - - - - ethernet.c - 1 - Libraries\driverlib\ethernet.c - - - - - fan.c - 1 - Libraries\driverlib\fan.c - - - - - flash.c - 1 - Libraries\driverlib\flash.c - - - - - fpu.c - 1 - Libraries\driverlib\fpu.c - - - - - gpio.c - 1 - Libraries\driverlib\gpio.c - - - - - hibernate.c - 1 - Libraries\driverlib\hibernate.c - - - - - i2c.c - 1 - Libraries\driverlib\i2c.c - - - - - i2s.c - 1 - Libraries\driverlib\i2s.c - - - - - interrupt.c - 1 - Libraries\driverlib\interrupt.c - - - - - lpc.c - 1 - Libraries\driverlib\lpc.c - - - - - mpu.c - 1 - Libraries\driverlib\mpu.c - - - - - peci.c - 1 - Libraries\driverlib\peci.c - - - - - pwm.c - 1 - Libraries\driverlib\pwm.c - - - - - qei.c - 1 - Libraries\driverlib\qei.c - - - - - ssi.c - 1 - Libraries\driverlib\ssi.c - - - - - sysctl.c - 1 - Libraries\driverlib\sysctl.c - - - - - sysexc.c - 1 - Libraries\driverlib\sysexc.c - - - - - systick.c - 1 - Libraries\driverlib\systick.c - - - - - timer.c - 1 - Libraries\driverlib\timer.c - - - - - uart.c - 1 - Libraries\driverlib\uart.c - - - - - udma.c - 1 - Libraries\driverlib\udma.c - - - - - usb.c - 1 - Libraries\driverlib\usb.c - - - - - watchdog.c - 1 - Libraries\driverlib\watchdog.c - - - - - start_rvds.S - 2 - Libraries\startup\arm\start_rvds.S + drivers/serial.c @@ -633,91 +633,91 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c device.c 1 - ..\..\src\device.c + ../../src/device.c idle.c 1 - ..\..\src\idle.c + ../../src/idle.c ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c irq.c 1 - ..\..\src\irq.c + ../../src/irq.c kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c mem.c 1 - ..\..\src\mem.c - - - - - memheap.c - 1 - ..\..\src\memheap.c + ../../src/mem.c mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c object.c 1 - ..\..\src\object.c + ../../src/object.c scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c thread.c 1 - ..\..\src\thread.c + ../../src/thread.c src_timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -727,129 +727,129 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m4\cpuport.c + ../../libcpu/arm/cortex-m4/cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m4\context_rvds.S + ../../libcpu/arm/cortex-m4/context_rvds.S backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c finsh - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c diff --git a/bsp/lpc178x/project.uvproj b/bsp/lpc178x/project.uvproj index 8c259ccd04..d3fa95f420 100644 --- a/bsp/lpc178x/project.uvproj +++ b/bsp/lpc178x/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- RT-Thread LPC17xx @@ -15,25 +12,25 @@ LPC1788 NXP (founded by Philips) IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M3") - + "STARTUP\NXP\LPC177x_8x\startup_LPC177x_8x.s" ("NXP LPC177x_8x Startup Code") UL2CM3(-O463 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000) 5325 LPC177x_8x.H - - - - - - - - - - + + + + + + + + + + 0 - - - + + + NXP\LPC177x_8x\ NXP\LPC177x_8x\ @@ -57,31 +54,29 @@ 0 0 - - + + 0 0 - 0 - 0 0 0 - - + + 0 0 0 0 - - + + 0 0 0 - + 0 @@ -95,8 +90,8 @@ 0 0 3 - - + + SARMCM3.DLL @@ -136,23 +131,22 @@ 1 0 1 - 0 0 7 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -167,7 +161,7 @@ Segger\JL2CM3.dll "" () - + @@ -199,7 +193,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -330,7 +324,7 @@ 0x8000 - + 1 @@ -345,12 +339,11 @@ 0 0 0 - 0 - - - - .;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;CMSIS\CM3\CoreSupport;CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x;applications;drivers + + + + applications;.;drivers;CMSIS/CM3/CoreSupport;CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/finsh @@ -361,12 +354,11 @@ 0 0 0 - 0 - - - - + + + + @@ -378,12 +370,12 @@ 0 0x00000000 0x10000000 - - - - --keep __fsym_* --keep __vsym_* - - + + + + --keep *.o(FSymTab) --keep *.o(VSymTab) + + @@ -394,32 +386,14 @@ application.c 1 - applications\application.c + applications/application.c + + startup.c 1 - applications\startup.c - - - - - CMSIS - - - core_cm3.c - 1 - CMSIS\CM3\CoreSupport\core_cm3.c - - - system_LPC177x_8x.c - 1 - CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x\system_LPC177x_8x.c - - - startup_LPC177x_8x.s - 2 - CMSIS\CM3\DeviceSupport\NXP\LPC177x_8x\startup\arm\startup_LPC177x_8x.s + applications/startup.c @@ -429,47 +403,87 @@ board.c 1 - drivers\board.c + drivers/board.c + + drv_glcd.c 1 - drivers\drv_glcd.c + drivers/drv_glcd.c + + lpc177x_8x_clkpwr.c 1 - drivers\lpc177x_8x_clkpwr.c + drivers/lpc177x_8x_clkpwr.c + + lpc177x_8x_emc.c 1 - drivers\lpc177x_8x_emc.c + drivers/lpc177x_8x_emc.c + + lpc177x_8x_pinsel.c 1 - drivers\lpc177x_8x_pinsel.c + drivers/lpc177x_8x_pinsel.c + + lpc177x_8x_uart.c 1 - drivers\lpc177x_8x_uart.c + drivers/lpc177x_8x_uart.c + + lpc17xx_lcd.c 1 - drivers\lpc17xx_lcd.c + drivers/lpc17xx_lcd.c + + sdram.c 1 - drivers\sdram.c + drivers/sdram.c + + uart.c 1 - drivers\uart.c + drivers/uart.c + + + + + CMSIS + + + core_cm3.c + 1 + CMSIS/CM3/CoreSupport/core_cm3.c + + + + + system_LPC177x_8x.c + 1 + CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/system_LPC177x_8x.c + + + + + startup_LPC177x_8x.s + 2 + CMSIS/CM3/DeviceSupport/NXP/LPC177x_8x/startup/arm/startup_LPC177x_8x.s @@ -479,67 +493,98 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + device.c 1 - ..\..\src\device.c + ../../src/device.c + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + mem.c 1 - ..\..\src\mem.c + ../../src/mem.c + + memheap.c 1 - ..\..\src\memheap.c + ../../src/memheap.c + + mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -549,112 +594,133 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c + ../../libcpu/arm/cortex-m3/cpuport.c + + context_rvds.S 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S + ../../libcpu/arm/cortex-m3/context_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c finsh - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - - - msh.c - 1 - ..\..\components\finsh\msh.c - - - msh_cmd.c - 1 - ..\..\components\finsh\msh_cmd.c - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c + + symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c - diff --git a/bsp/lpc2478/project.uvproj b/bsp/lpc2478/project.uvproj index 3836907e2b..8fcdccea67 100644 --- a/bsp/lpc2478/project.uvproj +++ b/bsp/lpc2478/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- RT-Thread LPC2478 @@ -20,20 +17,21 @@ UL2ARM(-U268761108 -O7 -S0 -C0 -FO15 -FD40000000 -FC800 -FN1 -FF0LPC_IAP2_512 -FS00 -FL07E000) 4307 LPC23xx.H - - - - - - - - - - + + + + + + + + + + + 0 0 - - - + + + Philips\ Philips\ @@ -43,43 +41,45 @@ 0 1 - .\obj\ + .\build\ rtthread-lpc 1 0 0 1 1 - .\obj\ + .\build\ 1 0 0 0 0 - - + + 0 0 + 0 + 0 0 0 - - + + 0 0 0 0 - - + + 0 0 0 - + 0 @@ -93,8 +93,9 @@ 0 0 3 - - + + + 1 SARM.DLL @@ -102,7 +103,7 @@ DARMP.DLL -pLPC2478 SARM.DLL - + TARMP.DLL -pLPC2478 @@ -128,28 +129,29 @@ 1 1 - 0 + 1 1 1 1 0 1 + 0 0 7 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -162,9 +164,14 @@ 1 4096 + 1 BIN\UL2ARM.DLL "LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1) - + + + + + 0 @@ -196,7 +203,7 @@ 0 0 ARM7TDMI - + 0 0 0 @@ -327,7 +334,7 @@ 0x4000 - + 1 @@ -342,11 +349,12 @@ 0 0 0 + 0 - - - - .;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\lpc24xx;applications;drivers + + + + applications;.;drivers;../../include;../../libcpu/arm/lpc24xx;../../libcpu/arm/common;../../components/finsh @@ -357,11 +365,12 @@ 0 0 0 + 0 - - - - + + + + @@ -373,12 +382,12 @@ 0 0x00000000 0x10000000 - - - - --keep __fsym_* --keep __vsym_* - - + + + + --keep *.o(FSymTab) --keep *.o(VSymTab) + + @@ -389,12 +398,14 @@ application.c 1 - applications\application.c + applications/application.c + + startup.c 1 - applications\startup.c + applications/startup.c @@ -404,12 +415,14 @@ board.c 1 - drivers\board.c + drivers/board.c + + serial.c 1 - drivers\serial.c + drivers/serial.c @@ -419,67 +432,91 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + device.c 1 - ..\..\src\device.c + ../../src/device.c + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + mem.c 1 - ..\..\src\mem.c - - - memheap.c - 1 - ..\..\src\memheap.c + ../../src/mem.c + + mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -489,122 +526,161 @@ cpu.c 1 - ..\..\libcpu\arm\lpc24xx\cpu.c + ../../libcpu/arm/lpc24xx/cpu.c + + interrupt.c 1 - ..\..\libcpu\arm\lpc24xx\interrupt.c + ../../libcpu/arm/lpc24xx/interrupt.c + + stack.c 1 - ..\..\libcpu\arm\lpc24xx\stack.c + ../../libcpu/arm/lpc24xx/stack.c + + trap.c 1 - ..\..\libcpu\arm\lpc24xx\trap.c + ../../libcpu/arm/lpc24xx/trap.c + + context_rvds.S 2 - ..\..\libcpu\arm\lpc24xx\context_rvds.S + ../../libcpu/arm/lpc24xx/context_rvds.S + + start_rvds.S 2 - ..\..\libcpu\arm\lpc24xx\start_rvds.S + ../../libcpu/arm/lpc24xx/start_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c finsh - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c + + symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c - diff --git a/bsp/lpc408x/project.uvproj b/bsp/lpc408x/project.uvproj new file mode 100644 index 0000000000..47403d9620 --- /dev/null +++ b/bsp/lpc408x/project.uvproj @@ -0,0 +1,1031 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + RT-Thread LPC408x + 0x4 + ARM-ADS + + + LPC4088 + NXP (founded by Philips) + IRAM(0x10000000-0x1000FFFF) IRAM2(0x20000000-0x20007FFF) IROM(0-0x7FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2 + + "STARTUP\NXP\LPC407x_8x_177x_8x\startup_LPC407x_8x_177x_8x.s" ("NXP LPC407x_8x_177x_8x Startup Code") + UL2CM3(-O4303 -S0 -C0 -FO7 -FD10000000 -FC800 -FN1 -FF0LPC_IAP_512 -FS00 -FL080000) + 6493 + LPC407x_8x_177x_8x.h + + + + + + + + + + SFD\NXP\LPC407x_8x_177x_8x\LPC408x_7x.SFR + 0 + + + + NXP\LPC407x_8x_177x_8x\ + NXP\LPC407x_8x_177x_8x\ + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-lpc + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 0 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 1 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10000000 + 0x10000 + + + 0 + 0x20000000 + 0x8000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + CORE_M4, RT_USING_ARM_LIBC + + Libraries/Device/NXP/LPC407x_8x_177x_8x/Include;Libraries/CMSIS/Include;Libraries/Drivers/include;applications;.;drivers;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/pthreads;../../components/libc/armlibc;../../components/drivers/include;../../components/drivers/include;../../components/finsh + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + CMSIS + + + system_LPC407x_8x_177x_8x.c + 1 + Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/system_LPC407x_8x_177x_8x.c + + + + + startup_LPC407x_8x_177x_8x.s + 2 + Libraries/Device/NXP/LPC407x_8x_177x_8x/Source/Templates/ARM/startup_LPC407x_8x_177x_8x.s + + + + + Libraries + + + lpc_adc.c + 1 + Libraries/Drivers/source/lpc_adc.c + + + + + lpc_bod.c + 1 + Libraries/Drivers/source/lpc_bod.c + + + + + lpc_can.c + 1 + Libraries/Drivers/source/lpc_can.c + + + + + lpc_clkpwr.c + 1 + Libraries/Drivers/source/lpc_clkpwr.c + + + + + lpc_crc.c + 1 + Libraries/Drivers/source/lpc_crc.c + + + + + lpc_dac.c + 1 + Libraries/Drivers/source/lpc_dac.c + + + + + lpc_eeprom.c + 1 + Libraries/Drivers/source/lpc_eeprom.c + + + + + lpc_emc.c + 1 + Libraries/Drivers/source/lpc_emc.c + + + + + lpc_exti.c + 1 + Libraries/Drivers/source/lpc_exti.c + + + + + lpc_gpdma.c + 1 + Libraries/Drivers/source/lpc_gpdma.c + + + + + lpc_gpio.c + 1 + Libraries/Drivers/source/lpc_gpio.c + + + + + lpc_i2c.c + 1 + Libraries/Drivers/source/lpc_i2c.c + + + + + lpc_i2s.c + 1 + Libraries/Drivers/source/lpc_i2s.c + + + + + lpc_iap.c + 1 + Libraries/Drivers/source/lpc_iap.c + + + + + lpc_lcd.c + 1 + Libraries/Drivers/source/lpc_lcd.c + + + + + lpc_mcpwm.c + 1 + Libraries/Drivers/source/lpc_mcpwm.c + + + + + lpc_nvic.c + 1 + Libraries/Drivers/source/lpc_nvic.c + + + + + lpc_pinsel.c + 1 + Libraries/Drivers/source/lpc_pinsel.c + + + + + lpc_pwm.c + 1 + Libraries/Drivers/source/lpc_pwm.c + + + + + lpc_qei.c + 1 + Libraries/Drivers/source/lpc_qei.c + + + + + lpc_rtc.c + 1 + Libraries/Drivers/source/lpc_rtc.c + + + + + lpc_ssp.c + 1 + Libraries/Drivers/source/lpc_ssp.c + + + + + lpc_systick.c + 1 + Libraries/Drivers/source/lpc_systick.c + + + + + lpc_timer.c + 1 + Libraries/Drivers/source/lpc_timer.c + + + + + lpc_uart.c + 1 + Libraries/Drivers/source/lpc_uart.c + + + + + lpc_wwdt.c + 1 + Libraries/Drivers/source/lpc_wwdt.c + + + + + Applications + + + application.c + 1 + applications/application.c + + + + + board.c + 1 + applications/board.c + + + + + sram.c + 1 + applications/sram.c + + + + + startup.c + 1 + applications/startup.c + + + + + Drivers + + + drv_led.c + 1 + drivers/drv_led.c + + + + + drv_uart.c + 1 + drivers/drv_uart.c + + + + + Kernel + + + clock.c + 1 + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c + + + + + device.c + 1 + ../../src/device.c + + + + + idle.c + 1 + ../../src/idle.c + + + + + ipc.c + 1 + ../../src/ipc.c + + + + + irq.c + 1 + ../../src/irq.c + + + + + kservice.c + 1 + ../../src/kservice.c + + + + + mem.c + 1 + ../../src/mem.c + + + + + memheap.c + 1 + ../../src/memheap.c + + + + + mempool.c + 1 + ../../src/mempool.c + + + + + object.c + 1 + ../../src/object.c + + + + + scheduler.c + 1 + ../../src/scheduler.c + + + + + thread.c + 1 + ../../src/thread.c + + + + + timer.c + 1 + ../../src/timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ../../libcpu/arm/cortex-m4/cpuport.c + + + + + context_rvds.S + 2 + ../../libcpu/arm/cortex-m4/context_rvds.S + + + + + backtrace.c + 1 + ../../libcpu/arm/common/backtrace.c + + + + + div0.c + 1 + ../../libcpu/arm/common/div0.c + + + + + showmem.c + 1 + ../../libcpu/arm/common/showmem.c + + + + + pthreads + + + clock_time.c + 1 + ../../components/pthreads/clock_time.c + + + + + mqueue.c + 1 + ../../components/pthreads/mqueue.c + + + + + pthread.c + 1 + ../../components/pthreads/pthread.c + + + + + pthread_attr.c + 1 + ../../components/pthreads/pthread_attr.c + + + + + pthread_barrier.c + 1 + ../../components/pthreads/pthread_barrier.c + + + + + pthread_cond.c + 1 + ../../components/pthreads/pthread_cond.c + + + + + pthread_mutex.c + 1 + ../../components/pthreads/pthread_mutex.c + + + + + pthread_rwlock.c + 1 + ../../components/pthreads/pthread_rwlock.c + + + + + pthread_spin.c + 1 + ../../components/pthreads/pthread_spin.c + + + + + pthread_tls.c + 1 + ../../components/pthreads/pthread_tls.c + + + + + sched.c + 1 + ../../components/pthreads/sched.c + + + + + semaphore.c + 1 + ../../components/pthreads/semaphore.c + + + + + libc + + + mem_std.c + 1 + ../../components/libc/armlibc/mem_std.c + + + + + stubs.c + 1 + ../../components/libc/armlibc/stubs.c + + + + + DeviceDrivers + + + serial.c + 1 + ../../components/drivers/serial/serial.c + + + + + completion.c + 1 + ../../components/drivers/src/completion.c + + + + + dataqueue.c + 1 + ../../components/drivers/src/dataqueue.c + + + + + pipe.c + 1 + ../../components/drivers/src/pipe.c + + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + + + ringbuffer.c + 1 + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c + + + + + finsh + + + shell.c + 1 + ../../components/finsh/shell.c + + + + + symbol.c + 1 + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c + + + + + + + diff --git a/bsp/mb9bf506r/project.uvproj b/bsp/mb9bf506r/project.uvproj index e6b538f29d..6b43252f74 100644 --- a/bsp/mb9bf506r/project.uvproj +++ b/bsp/mb9bf506r/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- rtthread-fm3 @@ -15,25 +12,25 @@ MB9BF506R Fujitsu Semiconductors IRAM(0x20000000-0x20007FFF) IRAM2(0x1FFF8000-0x1FFFFFFF) IROM(0x00000000-0x0007FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") - + "Startup\Fujitsu\MB9B500\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BFx06_512 -FS00 -FL080000) 5216 MB9BF506R.h - - - - - - - - - + + + + + + + + + SFD\Fujitsu\MB9B500\MB9BF506R.SFR 0 - - - + + + Fujitsu\MB9B500\ Fujitsu\MB9B500\ @@ -57,31 +54,29 @@ 0 0 - - + + 0 0 - 0 - 0 0 0 - - + + 0 0 0 0 - - + + 0 0 0 - + 0 @@ -95,8 +90,8 @@ 0 0 3 - - + + SARMCM3.DLL @@ -130,29 +125,28 @@ 1 1 - 1 + 0 1 1 1 0 1 - 0 0 7 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -167,7 +161,7 @@ Segger\JL2CM3.dll "" () - + @@ -199,7 +193,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -330,7 +324,7 @@ 0x8000 - + 1 @@ -345,12 +339,11 @@ 0 0 0 - 0 - - - - .;..\..\components\CMSIS\Include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\init;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;applications;drivers;libraries\Device\FUJISTU\MB9BF50x\Include + + + + libraries/Device/FUJISTU/MB9BF50x/Include;../../components/CMSIS/Include;applications;.;drivers;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh @@ -361,12 +354,11 @@ 0 0 0 - 0 - - - - + + + + @@ -378,28 +370,47 @@ 0 0x08000000 0x20000000 - - - - --keep __fsym_* --keep __vsym_* - - + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + CMSIS + + + system_mb9bf50x.c + 1 + libraries/Device/FUJISTU/MB9BF50x/Source/system_mb9bf50x.c + + + + + startup_mb9bf50x.S + 2 + libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S + + + Applications application.c 1 - applications\application.c + applications/application.c + + startup.c 1 - applications\startup.c + applications/startup.c @@ -409,37 +420,28 @@ board.c 1 - drivers\board.c + drivers/board.c + + fm3_uart.c 1 - drivers\fm3_uart.c + drivers/fm3_uart.c + + led.c 1 - drivers\led.c + drivers/led.c + + nand.c 1 - drivers\nand.c - - - - - CMSIS - - - system_mb9bf50x.c - 1 - libraries\Device\FUJISTU\MB9BF50x\Source\system_mb9bf50x.c - - - startup_mb9bf50x.S - 2 - libraries\Device\FUJISTU\MB9BF50x\Source\ARM\startup_mb9bf50x.S + drivers/nand.c @@ -449,67 +451,98 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + device.c 1 - ..\..\src\device.c + ../../src/device.c + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + mem.c 1 - ..\..\src\mem.c + ../../src/mem.c + + memheap.c 1 - ..\..\src\memheap.c + ../../src/memheap.c + + mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -519,27 +552,35 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c + ../../libcpu/arm/cortex-m3/cpuport.c + + context_rvds.S 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S + ../../libcpu/arm/cortex-m3/context_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c @@ -549,112 +590,147 @@ serial.c 1 - ..\..\components\drivers\serial\serial.c + ../../components/drivers/serial/serial.c + + completion.c 1 - ..\..\components\drivers\src\completion.c + ../../components/drivers/src/completion.c + + dataqueue.c 1 - ..\..\components\drivers\src\dataqueue.c + ../../components/drivers/src/dataqueue.c + + pipe.c 1 - ..\..\components\drivers\src\pipe.c + ../../components/drivers/src/pipe.c + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + ringbuffer.c 1 - ..\..\components\drivers\src\ringbuffer.c + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c finsh - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c + + symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c - - - Components - components.c + cmd.c 1 - ..\..\components\init\components.c + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c - diff --git a/bsp/mb9bf568r/project.uvproj b/bsp/mb9bf568r/project.uvproj new file mode 100644 index 0000000000..cdffbd0c81 --- /dev/null +++ b/bsp/mb9bf568r/project.uvproj @@ -0,0 +1,682 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + rtthread-fm4 + 0x4 + ARM-ADS + + + Cortex-M4 FPU + ARM + CLOCK(12000000) CPUTYPE("Cortex-M4") ESEL ELITTLE FPU2 + + + + 5237 + + + + + + + + + + + + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template_mb9b56xx + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + + DCM.DLL + -pCM4 + SARMCM3.DLL + + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 14 + + + + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + + 1 + 0 + 0 + 0 + 1 + 4105 + + BIN\CMSIS_AGDI.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x200c0000 + 0x8000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff0000 + 0x10000 + + + 0 + 0x20038000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + applications;.;drivers;CMSIS/Include;CMSIS/DeviceSupport;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/finsh + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x00000000 + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + Applications + + + application.c + 1 + applications/application.c + + + + + demo.c + 1 + applications/demo.c + + + + + startup.c + 1 + applications/startup.c + + + + + Drivers + + + board.c + 1 + drivers/board.c + + + + + led.c + 1 + drivers/led.c + + + + + serial.c + 1 + drivers/serial.c + + + + + CMSIS + + + system_mb9abxxx.c + 1 + CMSIS/DeviceSupport/system_mb9abxxx.c + + + + + startup_mb9bf56xr.s + 2 + CMSIS/DeviceSupport/arm/startup_mb9bf56xr.s + + + + + Kernel + + + clock.c + 1 + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c + + + + + device.c + 1 + ../../src/device.c + + + + + idle.c + 1 + ../../src/idle.c + + + + + ipc.c + 1 + ../../src/ipc.c + + + + + irq.c + 1 + ../../src/irq.c + + + + + kservice.c + 1 + ../../src/kservice.c + + + + + mem.c + 1 + ../../src/mem.c + + + + + mempool.c + 1 + ../../src/mempool.c + + + + + object.c + 1 + ../../src/object.c + + + + + scheduler.c + 1 + ../../src/scheduler.c + + + + + thread.c + 1 + ../../src/thread.c + + + + + timer.c + 1 + ../../src/timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ../../libcpu/arm/cortex-m4/cpuport.c + + + + + context_rvds.S + 2 + ../../libcpu/arm/cortex-m4/context_rvds.S + + + + + backtrace.c + 1 + ../../libcpu/arm/common/backtrace.c + + + + + div0.c + 1 + ../../libcpu/arm/common/div0.c + + + + + showmem.c + 1 + ../../libcpu/arm/common/showmem.c + + + + + finsh + + + shell.c + 1 + ../../components/finsh/shell.c + + + + + symbol.c + 1 + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c + + + + + + + diff --git a/bsp/mini2440/project.Uv2 b/bsp/mini2440/project.Uv2 new file mode 100644 index 0000000000..7864fdd64e --- /dev/null +++ b/bsp/mini2440/project.Uv2 @@ -0,0 +1,431 @@ +### uVision2 Project, (C) Keil Software +### Do not modify ! + +Target (RT-Thread Mini2440), 0x0004 // Tools: 'ARM-ADS' + +Group (Startup) +Group (Kernel) +Group (S3C24X0) +Group (pthreads) +Group (libc) +Group (libz) +Group (jpeg) +Group (libpng) +Group (libdl) +Group (finsh) +Group (LwIP) +Group (Filesystem) + +File 1,1,<./application.c> +File 1,1,<./startup.c> +File 1,1,<./board.c> +File 1,1,<./console.c> +File 1,1,<./led.c> +File 1,1,<./sdcard.c> +File 1,1,<./dm9000.c> +File 1,1,<../../src/clock.c> +File 1,1,<../../src/components.c> +File 1,1,<../../src/device.c> +File 1,1,<../../src/idle.c> +File 1,1,<../../src/ipc.c> +File 1,1,<../../src/irq.c> +File 1,1,<../../src/kservice.c> +File 1,1,<../../src/mem.c> +File 1,1,<../../src/mempool.c> +File 1,1,<../../src/module.c> +File 1,1,<../../src/object.c> +File 1,1,<../../src/scheduler.c> +File 1,1,<../../src/thread.c> +File 1,1,<../../src/timer.c> +File 1,1,<../../libcpu/arm/s3c24x0/cpu.c> +File 1,1,<../../libcpu/arm/s3c24x0/interrupt.c> +File 1,1,<../../libcpu/arm/s3c24x0/mmu.c> +File 1,1,<../../libcpu/arm/s3c24x0/rtc.c> +File 1,1,<../../libcpu/arm/s3c24x0/serial.c> +File 1,1,<../../libcpu/arm/s3c24x0/stack.c> +File 1,1,<../../libcpu/arm/s3c24x0/system_clock.c> +File 1,1,<../../libcpu/arm/s3c24x0/trap.c> +File 1,2,<../../libcpu/arm/s3c24x0/context_rvds.S> +File 1,2,<../../libcpu/arm/s3c24x0/start_rvds.S> +File 1,1,<../../libcpu/arm/common/backtrace.c> +File 1,1,<../../libcpu/arm/common/div0.c> +File 1,1,<../../libcpu/arm/common/showmem.c> +File 1,1,<../../components/pthreads/clock_time.c> +File 1,1,<../../components/pthreads/mqueue.c> +File 1,1,<../../components/pthreads/pthread.c> +File 1,1,<../../components/pthreads/pthread_attr.c> +File 1,1,<../../components/pthreads/pthread_barrier.c> +File 1,1,<../../components/pthreads/pthread_cond.c> +File 1,1,<../../components/pthreads/pthread_mutex.c> +File 1,1,<../../components/pthreads/pthread_rwlock.c> +File 1,1,<../../components/pthreads/pthread_spin.c> +File 1,1,<../../components/pthreads/pthread_tls.c> +File 1,1,<../../components/pthreads/sched.c> +File 1,1,<../../components/pthreads/semaphore.c> +File 1,1,<../../components/libc/armlibc/mem_std.c> +File 1,1,<../../components/libc/armlibc/stubs.c> +File 1,1,<../../components/external/libz/adler32.c> +File 1,1,<../../components/external/libz/compress.c> +File 1,1,<../../components/external/libz/crc32.c> +File 1,1,<../../components/external/libz/deflate.c> +File 1,1,<../../components/external/libz/infback.c> +File 1,1,<../../components/external/libz/inffast.c> +File 1,1,<../../components/external/libz/inflate.c> +File 1,1,<../../components/external/libz/inftrees.c> +File 1,1,<../../components/external/libz/trees.c> +File 1,1,<../../components/external/libz/uncompr.c> +File 1,1,<../../components/external/libz/zutil.c> +File 1,1,<../../components/external/jpeg/jaricom.c> +File 1,1,<../../components/external/jpeg/jcomapi.c> +File 1,1,<../../components/external/jpeg/jutils.c> +File 1,1,<../../components/external/jpeg/jerror.c> +File 1,1,<../../components/external/jpeg/jmemmgr.c> +File 1,1,<../../components/external/jpeg/jdapimin.c> +File 1,1,<../../components/external/jpeg/jdapistd.c> +File 1,1,<../../components/external/jpeg/jdarith.c> +File 1,1,<../../components/external/jpeg/jdtrans.c> +File 1,1,<../../components/external/jpeg/jdmaster.c> +File 1,1,<../../components/external/jpeg/jdinput.c> +File 1,1,<../../components/external/jpeg/jdmarker.c> +File 1,1,<../../components/external/jpeg/jdhuff.c> +File 1,1,<../../components/external/jpeg/jdmainct.c> +File 1,1,<../../components/external/jpeg/jdcoefct.c> +File 1,1,<../../components/external/jpeg/jdpostct.c> +File 1,1,<../../components/external/jpeg/jddctmgr.c> +File 1,1,<../../components/external/jpeg/jidctfst.c> +File 1,1,<../../components/external/jpeg/jidctflt.c> +File 1,1,<../../components/external/jpeg/jidctint.c> +File 1,1,<../../components/external/jpeg/jdsample.c> +File 1,1,<../../components/external/jpeg/jdcolor.c> +File 1,1,<../../components/external/jpeg/jquant1.c> +File 1,1,<../../components/external/jpeg/jquant2.c> +File 1,1,<../../components/external/jpeg/jdmerge.c> +File 1,1,<../../components/external/jpeg/jmemnobs.c> +File 1,1,<../../components/external/libpng/png.c> +File 1,1,<../../components/external/libpng/pngerror.c> +File 1,1,<../../components/external/libpng/pnggccrd.c> +File 1,1,<../../components/external/libpng/pngget.c> +File 1,1,<../../components/external/libpng/pngmem.c> +File 1,1,<../../components/external/libpng/pngpread.c> +File 1,1,<../../components/external/libpng/pngread.c> +File 1,1,<../../components/external/libpng/pngrio.c> +File 1,1,<../../components/external/libpng/pngrtran.c> +File 1,1,<../../components/external/libpng/pngrutil.c> +File 1,1,<../../components/external/libpng/pngset.c> +File 1,1,<../../components/external/libpng/pngtrans.c> +File 1,1,<../../components/external/libpng/pngvcrd.c> +File 1,1,<../../components/external/libpng/pngwio.c> +File 1,1,<../../components/external/libpng/pngwrite.c> +File 1,1,<../../components/external/libpng/pngwtran.c> +File 1,1,<../../components/external/libpng/pngwutil.c> +File 1,1,<../../components/libdl/dlclose.c> +File 1,1,<../../components/libdl/dlerror.c> +File 1,1,<../../components/libdl/dlopen.c> +File 1,1,<../../components/libdl/dlsym.c> +File 1,1,<../../components/finsh/shell.c> +File 1,1,<../../components/finsh/symbol.c> +File 1,1,<../../components/finsh/cmd.c> +File 1,1,<../../components/finsh/finsh_compiler.c> +File 1,1,<../../components/finsh/finsh_error.c> +File 1,1,<../../components/finsh/finsh_heap.c> +File 1,1,<../../components/finsh/finsh_init.c> +File 1,1,<../../components/finsh/finsh_node.c> +File 1,1,<../../components/finsh/finsh_ops.c> +File 1,1,<../../components/finsh/finsh_parser.c> +File 1,1,<../../components/finsh/finsh_var.c> +File 1,1,<../../components/finsh/finsh_vm.c> +File 1,1,<../../components/finsh/finsh_token.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/api_lib.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/api_msg.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/err.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/netbuf.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/netdb.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/netifapi.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/sockets.c> +File 1,1,<../../components/net/lwip-1.4.1/src/api/tcpip.c> +File 1,1,<../../components/net/lwip-1.4.1/src/arch/sys_arch.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/def.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/dhcp.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/dns.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/init.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/memp.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/netif.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/pbuf.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/raw.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/stats.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/sys.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/tcp.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/tcp_in.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/tcp_out.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/timers.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/udp.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/inet.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/ip.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c> +File 1,1,<../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c> +File 1,1,<../../components/net/lwip-1.4.1/src/netif/etharp.c> +File 1,1,<../../components/net/lwip-1.4.1/src/netif/ethernetif.c> +File 1,1,<../../components/net/lwip-1.4.1/src/netif/slipif.c> +File 1,1,<../../components/dfs/src/dfs.c> +File 1,1,<../../components/dfs/src/dfs_file.c> +File 1,1,<../../components/dfs/src/dfs_fs.c> +File 1,1,<../../components/dfs/src/dfs_posix.c> +File 1,1,<../../components/dfs/filesystems/elmfat/dfs_elm.c> +File 1,1,<../../components/dfs/filesystems/elmfat/ff.c> +File 1,1,<../../components/dfs/filesystems/elmfat/option/cc936.c> +File 1,1,<../../components/dfs/filesystems/devfs/console.c> +File 1,1,<../../components/dfs/filesystems/devfs/devfs.c> +File 2,1,<../../src/clock.c> +File 2,1,<../../src/components.c> +File 2,1,<../../src/device.c> +File 2,1,<../../src/idle.c> +File 2,1,<../../src/ipc.c> +File 2,1,<../../src/irq.c> +File 2,1,<../../src/kservice.c> +File 2,1,<../../src/mem.c> +File 2,1,<../../src/mempool.c> +File 2,1,<../../src/module.c> +File 2,1,<../../src/object.c> +File 2,1,<../../src/scheduler.c> +File 2,1,<../../src/thread.c> +File 2,1,<../../src/timer.c> +File 3,1,<../../libcpu/arm/s3c24x0/cpu.c> +File 3,1,<../../libcpu/arm/s3c24x0/interrupt.c> +File 3,1,<../../libcpu/arm/s3c24x0/mmu.c> +File 3,1,<../../libcpu/arm/s3c24x0/rtc.c> +File 3,1,<../../libcpu/arm/s3c24x0/serial.c> +File 3,1,<../../libcpu/arm/s3c24x0/stack.c> +File 3,1,<../../libcpu/arm/s3c24x0/system_clock.c> +File 3,1,<../../libcpu/arm/s3c24x0/trap.c> +File 3,2,<../../libcpu/arm/s3c24x0/context_rvds.S> +File 3,2,<../../libcpu/arm/s3c24x0/start_rvds.S> +File 3,1,<../../libcpu/arm/common/backtrace.c> +File 3,1,<../../libcpu/arm/common/div0.c> +File 3,1,<../../libcpu/arm/common/showmem.c> +File 4,1,<../../components/pthreads/clock_time.c> +File 4,1,<../../components/pthreads/mqueue.c> +File 4,1,<../../components/pthreads/pthread.c> +File 4,1,<../../components/pthreads/pthread_attr.c> +File 4,1,<../../components/pthreads/pthread_barrier.c> +File 4,1,<../../components/pthreads/pthread_cond.c> +File 4,1,<../../components/pthreads/pthread_mutex.c> +File 4,1,<../../components/pthreads/pthread_rwlock.c> +File 4,1,<../../components/pthreads/pthread_spin.c> +File 4,1,<../../components/pthreads/pthread_tls.c> +File 4,1,<../../components/pthreads/sched.c> +File 4,1,<../../components/pthreads/semaphore.c> +File 5,1,<../../components/libc/armlibc/mem_std.c> +File 5,1,<../../components/libc/armlibc/stubs.c> +File 6,1,<../../components/external/libz/adler32.c> +File 6,1,<../../components/external/libz/compress.c> +File 6,1,<../../components/external/libz/crc32.c> +File 6,1,<../../components/external/libz/deflate.c> +File 6,1,<../../components/external/libz/infback.c> +File 6,1,<../../components/external/libz/inffast.c> +File 6,1,<../../components/external/libz/inflate.c> +File 6,1,<../../components/external/libz/inftrees.c> +File 6,1,<../../components/external/libz/trees.c> +File 6,1,<../../components/external/libz/uncompr.c> +File 6,1,<../../components/external/libz/zutil.c> +File 7,1,<../../components/external/jpeg/jaricom.c> +File 7,1,<../../components/external/jpeg/jcomapi.c> +File 7,1,<../../components/external/jpeg/jutils.c> +File 7,1,<../../components/external/jpeg/jerror.c> +File 7,1,<../../components/external/jpeg/jmemmgr.c> +File 7,1,<../../components/external/jpeg/jdapimin.c> +File 7,1,<../../components/external/jpeg/jdapistd.c> +File 7,1,<../../components/external/jpeg/jdarith.c> +File 7,1,<../../components/external/jpeg/jdtrans.c> +File 7,1,<../../components/external/jpeg/jdmaster.c> +File 7,1,<../../components/external/jpeg/jdinput.c> +File 7,1,<../../components/external/jpeg/jdmarker.c> +File 7,1,<../../components/external/jpeg/jdhuff.c> +File 7,1,<../../components/external/jpeg/jdmainct.c> +File 7,1,<../../components/external/jpeg/jdcoefct.c> +File 7,1,<../../components/external/jpeg/jdpostct.c> +File 7,1,<../../components/external/jpeg/jddctmgr.c> +File 7,1,<../../components/external/jpeg/jidctfst.c> +File 7,1,<../../components/external/jpeg/jidctflt.c> +File 7,1,<../../components/external/jpeg/jidctint.c> +File 7,1,<../../components/external/jpeg/jdsample.c> +File 7,1,<../../components/external/jpeg/jdcolor.c> +File 7,1,<../../components/external/jpeg/jquant1.c> +File 7,1,<../../components/external/jpeg/jquant2.c> +File 7,1,<../../components/external/jpeg/jdmerge.c> +File 7,1,<../../components/external/jpeg/jmemnobs.c> +File 8,1,<../../components/external/libpng/png.c> +File 8,1,<../../components/external/libpng/pngerror.c> +File 8,1,<../../components/external/libpng/pnggccrd.c> +File 8,1,<../../components/external/libpng/pngget.c> +File 8,1,<../../components/external/libpng/pngmem.c> +File 8,1,<../../components/external/libpng/pngpread.c> +File 8,1,<../../components/external/libpng/pngread.c> +File 8,1,<../../components/external/libpng/pngrio.c> +File 8,1,<../../components/external/libpng/pngrtran.c> +File 8,1,<../../components/external/libpng/pngrutil.c> +File 8,1,<../../components/external/libpng/pngset.c> +File 8,1,<../../components/external/libpng/pngtrans.c> +File 8,1,<../../components/external/libpng/pngvcrd.c> +File 8,1,<../../components/external/libpng/pngwio.c> +File 8,1,<../../components/external/libpng/pngwrite.c> +File 8,1,<../../components/external/libpng/pngwtran.c> +File 8,1,<../../components/external/libpng/pngwutil.c> +File 9,1,<../../components/libdl/dlclose.c> +File 9,1,<../../components/libdl/dlerror.c> +File 9,1,<../../components/libdl/dlopen.c> +File 9,1,<../../components/libdl/dlsym.c> +File 10,1,<../../components/finsh/shell.c> +File 10,1,<../../components/finsh/symbol.c> +File 10,1,<../../components/finsh/cmd.c> +File 10,1,<../../components/finsh/finsh_compiler.c> +File 10,1,<../../components/finsh/finsh_error.c> +File 10,1,<../../components/finsh/finsh_heap.c> +File 10,1,<../../components/finsh/finsh_init.c> +File 10,1,<../../components/finsh/finsh_node.c> +File 10,1,<../../components/finsh/finsh_ops.c> +File 10,1,<../../components/finsh/finsh_parser.c> +File 10,1,<../../components/finsh/finsh_var.c> +File 10,1,<../../components/finsh/finsh_vm.c> +File 10,1,<../../components/finsh/finsh_token.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/api_lib.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/api_msg.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/err.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/netbuf.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/netdb.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/netifapi.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/sockets.c> +File 11,1,<../../components/net/lwip-1.4.1/src/api/tcpip.c> +File 11,1,<../../components/net/lwip-1.4.1/src/arch/sys_arch.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/def.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/dhcp.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/dns.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/init.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/memp.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/netif.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/pbuf.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/raw.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/stats.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/sys.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/tcp.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/tcp_in.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/tcp_out.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/timers.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/udp.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/inet.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/ip.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c> +File 11,1,<../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c> +File 11,1,<../../components/net/lwip-1.4.1/src/netif/etharp.c> +File 11,1,<../../components/net/lwip-1.4.1/src/netif/ethernetif.c> +File 11,1,<../../components/net/lwip-1.4.1/src/netif/slipif.c> +File 12,1,<../../components/dfs/src/dfs.c> +File 12,1,<../../components/dfs/src/dfs_file.c> +File 12,1,<../../components/dfs/src/dfs_fs.c> +File 12,1,<../../components/dfs/src/dfs_posix.c> +File 12,1,<../../components/dfs/filesystems/elmfat/dfs_elm.c> +File 12,1,<../../components/dfs/filesystems/elmfat/ff.c> +File 12,1,<../../components/dfs/filesystems/elmfat/option/cc936.c> +File 12,1,<../../components/dfs/filesystems/devfs/console.c> +File 12,1,<../../components/dfs/filesystems/devfs/devfs.c> + + + + +Options 1,0,0 // Target 'RT-Thread Mini2440' + Device (S3C2440A) + Vendor (Samsung) + Cpu (IRAM(0x40000000-0x40000FFF) CLOCK(12000000) CPUTYPE(ARM920T)) + FlashUt () + StupF ("STARTUP\Samsung\S3C2440.s" ("Samsung S3C2440 Startup Code")) + FlashDR (UL2ARM(-UV2077N9E -O40 -S0 -C0 -N00("ARM920T Core") -D00(0032409D) -L00(4) -FO7 -FD40000000 -FC1000 -FN1 -FF0S3C2440_NAND_SP -FS030000000 -FL07FFC000)) + DevID (4277) + Rgf (S3C2440.H) + Mem () + C () + A () + RL () + OH () + DBC_IFX () + DBC_CMS () + DBC_AMS () + DBC_LMS () + UseEnv=0 + EnvBin () + EnvInc () + EnvLib () + EnvReg (Samsung\) + OrgReg (Samsung\) + TgStat=16 + OutDir (.\obj\) + OutName (rtthread-mini2440) + GenApp=1 + GenLib=0 + GenHex=0 + Debug=1 + Browse=0 + LstDir (.\obj) + HexSel=1 + MG32K=0 + TGMORE=0 + RunUsr 0 0 <> + RunUsr 1 0 <> + BrunUsr 0 0 <> + BrunUsr 1 0 <> + CrunUsr 0 0 <> + CrunUsr 1 0 <> + SVCSID <> + GLFLAGS=1790 + ADSFLGA { 242,31,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ACPUTYP (ARM920T) + RVDEV () + ADSTFLGA { 0,8,64,0,96,0,64,64,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + OCMADSIRAM { 0,0,0,0,64,0,16,0,0 } + OCMADSIROM { 0,0,0,0,0,0,0,0,0 } + OCMADSXRAM { 0,0,0,0,0,0,0,0,0 } + OCR_RVCT { 1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,64,0,16,0,0,0,0,0,0,0,0,0,0,0 } + RV_STAVEC () + ADSCCFLG { 5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSCMISC (--diag_suppress=870) + ADSCDEFN (RT_USING_ARM_LIBC) + ADSCUDEF () + ADSCINCD (../../components/libdl;../../components/external/libpng;../../libcpu/arm/s3c24x0;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/pthreads;../../components/dfs/filesystems/elmfat;../../libcpu/arm/common;../../components/dfs/filesystems/devfs;.;../../components/external/libz;../../components/net/lwip-1.4.1/src/include/netif;../../include;../../components/dfs/include;../../components/net/lwip-1.4.1/src/include;../../components/external/jpeg;../../components/libc/armlibc;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/ipv4) + ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSAMISC () + ADSADEFN () + ADSAUDEF () + ADSAINCD () + PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + IncBld=1 + AlwaysBuild=0 + GenAsm=0 + AsmAsm=0 + PublicsOnly=0 + StopCode=3 + CustArgs () + LibMods () + ADSLDFG { 16,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } + ADSLDTA (0x30000000) + ADSLDDA (0x40000000) + ADSLDSC (rtthread-mini2440.sct) + ADSLDIB () + ADSLDIC () + ADSLDMC ( --keep *.o(RTMSymTab) --keep *.o(FSymTab) --keep *.o(VSymTab) ) + ADSLDIF () + ADSLDDW () + OPTDL (SARM.DLL)()(DARMSS9.DLL)(-pS3C2440A)(SARM.DLL)()(TARMSS9.DLL)(-pS3C2440A) + OPTDBG 47614,6,()()()()()()()()()(.\Ext_RAM.ini) (Segger\JLTAgdi.dll)()()() + FLASH1 { 1,0,0,0,1,0,0,0,4,16,0,0,0,0,0,0,0,0,0,0 } + FLASH2 (Segger\JLTAgdi.dll) + FLASH3 ("" ()) + FLASH4 () +EndOpt + diff --git a/bsp/nrf51822/project.uvproj b/bsp/nrf51822/project.uvproj new file mode 100644 index 0000000000..689bd1c80c --- /dev/null +++ b/bsp/nrf51822/project.uvproj @@ -0,0 +1,646 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + + + nRF51822_xxAA + Nordic Semiconductor + NordicSemiconductor.nRF_DeviceFamilyPack.1.1.4 + http://developer.nordicsemi.com/nRF51_SDK/pieces/nRF_DeviceFamilyPack/ + IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)) + 0 + $$Device:nRF51822_xxAA$Device\Include\nrf.h + + + + + + + + + + $$Device:nRF51822_xxAA$SVD\nrf51.xml + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + template + 1 + 0 + 0 + 1 + 1 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --c99 + NRF51, USE_STDPERIPH_DRIVER + + Libraries/CMSIS/Include;Libraries/nrf51822/Include;applications;.;drivers;../../include;../../libcpu/arm/cortex-m0;../../libcpu/arm/common;../../components/drivers/include;../../components/finsh + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + --keep *.o(FSymTab) + + + + + + + + Startup Code + + + system_nrf51.c + 1 + Libraries/nrf51822/Source/templates/system_nrf51.c + + + + + arm_startup_nrf51.s + 2 + Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s + + + + + Applications + + + application.c + 1 + applications/application.c + + + + + startup.c + 1 + applications/startup.c + + + + + Drivers + + + board.c + 1 + drivers/board.c + + + + + uart.c + 1 + drivers/uart.c + + + + + Kernel + + + clock.c + 1 + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c + + + + + device.c + 1 + ../../src/device.c + + + + + idle.c + 1 + ../../src/idle.c + + + + + ipc.c + 1 + ../../src/ipc.c + + + + + irq.c + 1 + ../../src/irq.c + + + + + kservice.c + 1 + ../../src/kservice.c + + + + + object.c + 1 + ../../src/object.c + + + + + scheduler.c + 1 + ../../src/scheduler.c + + + + + thread.c + 1 + ../../src/thread.c + + + + + timer.c + 1 + ../../src/timer.c + + + + + CORTEX-M0 + + + cpuport.c + 1 + ../../libcpu/arm/cortex-m0/cpuport.c + + + + + context_rvds.S + 2 + ../../libcpu/arm/cortex-m0/context_rvds.S + + + + + backtrace.c + 1 + ../../libcpu/arm/common/backtrace.c + + + + + div0.c + 1 + ../../libcpu/arm/common/div0.c + + + + + showmem.c + 1 + ../../libcpu/arm/common/showmem.c + + + + + DeviceDrivers + + + completion.c + 1 + ../../components/drivers/src/completion.c + + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + + + ringbuffer.c + 1 + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c + + + + + finsh + + + shell.c + 1 + ../../components/finsh/shell.c + + + + + symbol.c + 1 + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + msh_cmd.c + 1 + ../../components/finsh/msh_cmd.c + + + + + msh.c + 1 + ../../components/finsh/msh.c + + + + + + + diff --git a/bsp/sam7x/project.uvproj b/bsp/sam7x/project.uvproj index c30f48ab07..29a1b42672 100644 --- a/bsp/sam7x/project.uvproj +++ b/bsp/sam7x/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- RT-Thread/AT91SAM7X256 @@ -15,25 +12,25 @@ AT91SAM7X256 Atmel IRAM(0x200000-0x20FFFF) IROM(0x100000-0x13FFFF) CLOCK(18432000) CPUTYPE(ARM7TDMI) - + "STARTUP\Atmel\SAM7.s" ("Atmel AT91SAM7 Startup Code") UL2ARM(-U56240812 -O15 -S0 -C0 -FO7 -FD200000 -FC800 -FN1 -FF0AT91SAM7_256 -FS0100000 -FL040000) 4081 AT91SAM7X256.H - - - - - - - - - - + + + + + + + + + + 0 - - - + + + Atmel\SAM7X\ Atmel\SAM7X\ @@ -57,31 +54,29 @@ 0 0 - - + + 0 0 - 0 - 0 0 0 - - + + 0 0 0 0 - - + + 0 0 0 - + 0 @@ -95,8 +90,8 @@ 0 0 3 - - + + SARM.DLL @@ -104,7 +99,7 @@ DARMATS.DLL -p91SAM7X256 SARM.DLL - + TARMATS.DLL -p91SAM7X256 @@ -140,18 +135,18 @@ 0 6 - - - - - + + + + + - - - - - + + + + + Segger\JLTAgdi.dll @@ -166,7 +161,7 @@ Segger\JLTAgdi.dll "" () - + @@ -198,7 +193,7 @@ 0 0 ARM7TDMI - + 0 0 0 @@ -329,7 +324,7 @@ 0x0 - + 1 @@ -345,10 +340,10 @@ 0 0 - - - - .;..\..\components\finsh;..\..\components\net\lwip\src;..\..\components\net\lwip\src\arch\include;..\..\components\net\lwip\src\include;..\..\components\net\lwip\src\include\ipv4;..\..\components\net\lwip\src\include\netif;..\..\include;..\..\libcpu\arm\AT91SAM7X;..\..\libcpu\arm\common;applications;drivers + + + + applications;.;drivers;../../include;../../libcpu/arm/AT91SAM7X;../../libcpu/arm/common;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif @@ -360,10 +355,10 @@ 0 0 - - - - + + + + @@ -375,12 +370,12 @@ 0 0x00100000 0x00200000 - - - - --keep __fsym_* --keep __vsym_* - - + + + + --keep *.o(FSymTab) --keep *.o(VSymTab) + + @@ -391,12 +386,14 @@ application.c 1 - applications\application.c + applications/application.c + + startup.c 1 - applications\startup.c + applications/startup.c @@ -406,17 +403,21 @@ board.c 1 - drivers\board.c + drivers/board.c + + sam7x_emac.c 1 - drivers\sam7x_emac.c + drivers/sam7x_emac.c + + serial.c 1 - drivers\serial.c + drivers/serial.c @@ -426,62 +427,91 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + device.c 1 - ..\..\src\device.c + ../../src/device.c + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + mem.c 1 - ..\..\src\mem.c + ../../src/mem.c + + mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -491,117 +521,157 @@ cpu.c 1 - ..\..\libcpu\arm\AT91SAM7X\cpu.c + ../../libcpu/arm/AT91SAM7X/cpu.c + + interrupt.c 1 - ..\..\libcpu\arm\AT91SAM7X\interrupt.c + ../../libcpu/arm/AT91SAM7X/interrupt.c + + stack.c 1 - ..\..\libcpu\arm\AT91SAM7X\stack.c + ../../libcpu/arm/AT91SAM7X/stack.c + + trap.c 1 - ..\..\libcpu\arm\AT91SAM7X\trap.c + ../../libcpu/arm/AT91SAM7X/trap.c + + context_rvds.S 2 - ..\..\libcpu\arm\AT91SAM7X\context_rvds.S + ../../libcpu/arm/AT91SAM7X/context_rvds.S + + start_rvds.S 2 - ..\..\libcpu\arm\AT91SAM7X\start_rvds.S + ../../libcpu/arm/AT91SAM7X/start_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c finsh - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c + + symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c @@ -611,182 +681,249 @@ api_lib.c 1 - ..\..\components\net\lwip\src\api\api_lib.c + ../../components/net/lwip-1.4.1/src/api/api_lib.c + + api_msg.c 1 - ..\..\components\net\lwip\src\api\api_msg.c + ../../components/net/lwip-1.4.1/src/api/api_msg.c + + err.c 1 - ..\..\components\net\lwip\src\api\err.c + ../../components/net/lwip-1.4.1/src/api/err.c + + netbuf.c 1 - ..\..\components\net\lwip\src\api\netbuf.c + ../../components/net/lwip-1.4.1/src/api/netbuf.c + + netdb.c 1 - ..\..\components\net\lwip\src\api\netdb.c + ../../components/net/lwip-1.4.1/src/api/netdb.c + + netifapi.c 1 - ..\..\components\net\lwip\src\api\netifapi.c + ../../components/net/lwip-1.4.1/src/api/netifapi.c + + sockets.c 1 - ..\..\components\net\lwip\src\api\sockets.c + ../../components/net/lwip-1.4.1/src/api/sockets.c + + tcpip.c 1 - ..\..\components\net\lwip\src\api\tcpip.c + ../../components/net/lwip-1.4.1/src/api/tcpip.c + + sys_arch.c 1 - ..\..\components\net\lwip\src\arch\sys_arch.c + ../../components/net/lwip-1.4.1/src/arch/sys_arch.c + + def.c 1 - ..\..\components\net\lwip\src\core\def.c + ../../components/net/lwip-1.4.1/src/core/def.c + + dhcp.c 1 - ..\..\components\net\lwip\src\core\dhcp.c + ../../components/net/lwip-1.4.1/src/core/dhcp.c + + dns.c 1 - ..\..\components\net\lwip\src\core\dns.c + ../../components/net/lwip-1.4.1/src/core/dns.c + + init.c 1 - ..\..\components\net\lwip\src\core\init.c + ../../components/net/lwip-1.4.1/src/core/init.c + + memp.c 1 - ..\..\components\net\lwip\src\core\memp.c + ../../components/net/lwip-1.4.1/src/core/memp.c + + netif.c 1 - ..\..\components\net\lwip\src\core\netif.c + ../../components/net/lwip-1.4.1/src/core/netif.c + + pbuf.c 1 - ..\..\components\net\lwip\src\core\pbuf.c + ../../components/net/lwip-1.4.1/src/core/pbuf.c + + raw.c 1 - ..\..\components\net\lwip\src\core\raw.c + ../../components/net/lwip-1.4.1/src/core/raw.c + + stats.c 1 - ..\..\components\net\lwip\src\core\stats.c + ../../components/net/lwip-1.4.1/src/core/stats.c + + sys.c 1 - ..\..\components\net\lwip\src\core\sys.c + ../../components/net/lwip-1.4.1/src/core/sys.c + + tcp.c 1 - ..\..\components\net\lwip\src\core\tcp.c + ../../components/net/lwip-1.4.1/src/core/tcp.c + + tcp_in.c 1 - ..\..\components\net\lwip\src\core\tcp_in.c + ../../components/net/lwip-1.4.1/src/core/tcp_in.c + + tcp_out.c 1 - ..\..\components\net\lwip\src\core\tcp_out.c + ../../components/net/lwip-1.4.1/src/core/tcp_out.c + + timers.c 1 - ..\..\components\net\lwip\src\core\timers.c + ../../components/net/lwip-1.4.1/src/core/timers.c + + udp.c 1 - ..\..\components\net\lwip\src\core\udp.c + ../../components/net/lwip-1.4.1/src/core/udp.c + + autoip.c 1 - ..\..\components\net\lwip\src\core\ipv4\autoip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c + + icmp.c 1 - ..\..\components\net\lwip\src\core\ipv4\icmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c + + igmp.c 1 - ..\..\components\net\lwip\src\core\ipv4\igmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c + + inet.c 1 - ..\..\components\net\lwip\src\core\ipv4\inet.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c + + inet_chksum.c 1 - ..\..\components\net\lwip\src\core\ipv4\inet_chksum.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c + + ip.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + + ip_addr.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip_addr.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + + ip_frag.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip_frag.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + + etharp.c 1 - ..\..\components\net\lwip\src\netif\etharp.c + ../../components/net/lwip-1.4.1/src/netif/etharp.c + + ethernetif.c 1 - ..\..\components\net\lwip\src\netif\ethernetif.c + ../../components/net/lwip-1.4.1/src/netif/ethernetif.c + + slipif.c 1 - ..\..\components\net\lwip\src\netif\slipif.c + ../../components/net/lwip-1.4.1/src/netif/slipif.c - diff --git a/bsp/stm32f0x/project.uvproj b/bsp/stm32f0x/project.uvproj index ccf96a948d..f2d0040daf 100644 --- a/bsp/stm32f0x/project.uvproj +++ b/bsp/stm32f0x/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- rt-thread @@ -15,25 +12,25 @@ STM32F051R8 STMicroelectronics IRAM(0x20000000-0x20001FFF) IROM(0x8000000-0x800FFFF) CLOCK(8000000) CPUTYPE("Cortex-M0") - + "Startup\ST\STM32F0xx\startup_stm32f0xx.s" ("STM32F0xx Startup Code") UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F05x_64 -FS08000000 -FL010000) 6188 stm32f0xx.h - - - - - - - - - + + + + + + + + + SFD\ST\STM32F0xx\STM32F051xx.sfr 0 - - - + + + ST\STM32F0xx\ ST\STM32F0xx\ @@ -57,8 +54,8 @@ 0 0 - - + + 0 0 0 @@ -67,21 +64,21 @@ 0 0 - - + + 0 0 0 0 - - + + 0 0 0 - + 0 @@ -95,16 +92,16 @@ 0 0 3 - - + + SARMCM3.DLL - + DARMCM1.DLL -pCM0 SARMCM3.DLL - + TARMCM1.DLL -pCM0 @@ -140,18 +137,18 @@ 0 13 - - - - - + + + + + - - - - - + + + + + STLink\ST-LINKIII-KEIL_SWO.dll @@ -166,7 +163,7 @@ STLink\ST-LINKIII-KEIL_SWO.dll "" () - + @@ -198,7 +195,7 @@ 0 0 "Cortex-M0" - + 0 0 0 @@ -329,7 +326,7 @@ 0x0 - + 1 @@ -345,10 +342,10 @@ 0 0 - - USE_STDPERIPH_DRIVER - - .;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;Libraries\CMSIS\Include;Libraries\CMSIS\ST\STM32F0xx\Include;Libraries\STM32F0xx_StdPeriph_Driver\inc;applications;drivers + + RT_USING_ARM_LIBC, USE_STDPERIPH_DRIVER + + Libraries/STM32F0xx_StdPeriph_Driver/inc;Libraries/CMSIS/ST/STM32F0xx/Include;Libraries/CMSIS/Include;applications;.;drivers;../../include;../../libcpu/arm/cortex-m0;../../libcpu/arm/common;../../components/libc/armlibc;../../components/drivers/include;../../components/drivers/include;../../components/finsh @@ -360,10 +357,10 @@ 0 0 - - - - + + + + @@ -375,28 +372,194 @@ 0 0x08000000 0x20000000 - - - - - - + + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + STM32_StdPeriph + + + system_stm32f0xx.c + 1 + Libraries/CMSIS/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c + + + + + stm32f0xx_adc.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c + + + + + stm32f0xx_cec.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c + + + + + stm32f0xx_comp.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c + + + + + stm32f0xx_crc.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crc.c + + + + + stm32f0xx_dac.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c + + + + + stm32f0xx_dbgmcu.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c + + + + + stm32f0xx_dma.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c + + + + + stm32f0xx_exti.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c + + + + + stm32f0xx_flash.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c + + + + + stm32f0xx_gpio.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c + + + + + stm32f0xx_i2c.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c + + + + + stm32f0xx_iwdg.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c + + + + + stm32f0xx_misc.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c + + + + + stm32f0xx_pwr.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c + + + + + stm32f0xx_rcc.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c + + + + + stm32f0xx_rtc.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c + + + + + stm32f0xx_spi.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c + + + + + stm32f0xx_syscfg.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c + + + + + stm32f0xx_tim.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c + + + + + stm32f0xx_usart.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c + + + + + stm32f0xx_wwdg.c + 1 + Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c + + + + + startup_stm32f0xx.s + 2 + Libraries/CMSIS/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s + + + Applications application.c 1 - applications\application.c + applications/application.c + + startup.c 1 - applications\startup.c + applications/startup.c @@ -406,132 +569,28 @@ board.c 1 - drivers\board.c + drivers/board.c + + + + led.c + 1 + drivers/led.c + + + stm32f0xx_it.c 1 - drivers\stm32f0xx_it.c + drivers/stm32f0xx_it.c - - - STM32_StdPeriph - system_stm32f0xx.c + usart.c 1 - Libraries\CMSIS\ST\STM32F0xx\Source\Templates\system_stm32f0xx.c - - - stm32f0xx_adc.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_adc.c - - - stm32f0xx_cec.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_cec.c - - - stm32f0xx_comp.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_comp.c - - - stm32f0xx_crc.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_crc.c - - - stm32f0xx_dac.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_dac.c - - - stm32f0xx_dbgmcu.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_dbgmcu.c - - - stm32f0xx_dma.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_dma.c - - - stm32f0xx_exti.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_exti.c - - - stm32f0xx_flash.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_flash.c - - - stm32f0xx_gpio.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_gpio.c - - - stm32f0xx_i2c.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_i2c.c - - - stm32f0xx_iwdg.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_iwdg.c - - - stm32f0xx_misc.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_misc.c - - - stm32f0xx_pwr.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_pwr.c - - - stm32f0xx_rcc.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_rcc.c - - - stm32f0xx_rtc.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_rtc.c - - - stm32f0xx_spi.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_spi.c - - - stm32f0xx_syscfg.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_syscfg.c - - - stm32f0xx_tim.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_tim.c - - - stm32f0xx_usart.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_usart.c - - - stm32f0xx_wwdg.c - 1 - Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_wwdg.c - - - startup_stm32f0xx.s - 2 - Libraries\CMSIS\ST\STM32F0xx\Source\Templates\arm\startup_stm32f0xx.s + drivers/usart.c @@ -541,47 +600,84 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + + + device.c + 1 + ../../src/device.c + + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + + + mem.c + 1 + ../../src/mem.c + + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -591,32 +687,202 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m0\cpuport.c + ../../libcpu/arm/cortex-m0/cpuport.c + + context_rvds.S 2 - ..\..\libcpu\arm\cortex-m0\context_rvds.S + ../../libcpu/arm/cortex-m0/context_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c + + + + + libc + + + mem_std.c + 1 + ../../components/libc/armlibc/mem_std.c + + + + + stubs.c + 1 + ../../components/libc/armlibc/stubs.c + + + + + DeviceDrivers + + + serial.c + 1 + ../../components/drivers/serial/serial.c + + + + + completion.c + 1 + ../../components/drivers/src/completion.c + + + + + dataqueue.c + 1 + ../../components/drivers/src/dataqueue.c + + + + + pipe.c + 1 + ../../components/drivers/src/pipe.c + + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + + + ringbuffer.c + 1 + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c + + + + + finsh + + + shell.c + 1 + ../../components/finsh/shell.c + + + + + symbol.c + 1 + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c - diff --git a/bsp/stm32f107/project.uvopt b/bsp/stm32f107/project.uvopt index 0912073847..b172f6a05b 100644 --- a/bsp/stm32f107/project.uvopt +++ b/bsp/stm32f107/project.uvopt @@ -71,7 +71,7 @@ 0 - 1 + 0 0 1 @@ -102,7 +102,7 @@ 0 1 1 - 1 + 0 1 1 1 @@ -130,65 +130,6 @@ Segger\JL2CM3.dll - - - 0 - DLGUARM - (106=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0) - - - 0 - DLGDARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) - - - 0 - DLGTARM - (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - -T0 - - - 0 - JL2CM3 - -U12345678 -O14 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight JTAG-DP") -D00(3BA00477) -L00(4) -N01("Unknown JTAG device") -D01(06418041) -L01(5) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO27 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000 - - - - - 0 - 0 - 272 - 1 -
134282140
- 0 - 0 - 0 - 0 - 1 - - - \\rtthread_stm32\init\272 - - - 1 - 0 - 274 - 1 -
134279930
- 0 - 0 - 0 - 0 - 1 - - - \\rtthread_stm32\dns\274 - - 0 0 @@ -197,7 +138,7 @@ 0 0 0 - 1 + 0 0 0 0 @@ -212,7 +153,7 @@ 0 0 0 - 0 + 3 0 @@ -220,1565 +161,4 @@ - - Startup - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 0 - 0 - 70 - 84 - 0 - .\application.c - application.c - - - 1 - 2 - 1 - 0 - 0 - 0 - 0 - 108 - 120 - 0 - .\startup.c - startup.c - - - 1 - 3 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\board.c - board.c - - - 1 - 4 - 1 - 0 - 0 - 58 - 0 - 166 - 166 - 0 - .\stm32f10x_it.c - stm32f10x_it.c - - - 1 - 5 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\usart.c - usart.c - - - 1 - 6 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - .\serial.c - serial.c - - - 1 - 7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\stm32_eth.c - stm32_eth.c - - - 1 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\msd.c - msd.c - - - - - Kernel - 0 - 0 - 0 - - 2 - 9 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\clock.c - clock.c - - - 2 - 10 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\device.c - device.c - - - 2 - 11 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\idle.c - idle.c - - - 2 - 12 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\ipc.c - ipc.c - - - 2 - 13 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\irq.c - irq.c - - - 2 - 14 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\kservice.c - kservice.c - - - 2 - 15 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\mem.c - mem.c - - - 2 - 16 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\mempool.c - mempool.c - - - 2 - 17 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\module.c - module.c - - - 2 - 18 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\object.c - object.c - - - 2 - 19 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\rtm.c - rtm.c - - - 2 - 20 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\scheduler.c - scheduler.c - - - 2 - 21 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\slab.c - slab.c - - - 2 - 22 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\thread.c - thread.c - - - 2 - 23 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\src\timer.c - timer.c - - - - - STM32 - 0 - 0 - 0 - - 3 - 26 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\common\backtrace.c - backtrace.c - - - 3 - 27 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\common\div0.c - div0.c - - - 3 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\common\showmem.c - showmem.c - - - 3 - 0 - 2 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\cortex-m3\context_rvds.S - context_rvds.S - - - 3 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\libcpu\arm\cortex-m3\cpuport.c - cpuport.c - - - - - Filesystem - 0 - 0 - 0 - - 4 - 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\dfs\src\dfs.c - dfs.c - - - 4 - 30 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\dfs\src\dfs_fs.c - dfs_fs.c - - - 4 - 31 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\dfs\src\dfs_file.c - dfs_file.c - - - 4 - 32 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\dfs\src\dfs_posix.c - dfs_posix.c - - - 4 - 33 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\dfs\filesystems\elmfat\dfs_elm.c - dfs_elm.c - - - 4 - 34 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\dfs\filesystems\elmfat\ff.c - ff.c - - - - - finsh - 0 - 0 - 0 - - 5 - 35 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\cmd.c - cmd.c - - - 5 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_compiler.c - finsh_compiler.c - - - 5 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_error.c - finsh_error.c - - - 5 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_heap.c - finsh_heap.c - - - 5 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_init.c - finsh_init.c - - - 5 - 40 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_node.c - finsh_node.c - - - 5 - 41 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_ops.c - finsh_ops.c - - - 5 - 42 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_parser.c - finsh_parser.c - - - 5 - 43 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_token.c - finsh_token.c - - - 5 - 44 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_var.c - finsh_var.c - - - 5 - 45 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\finsh_vm.c - finsh_vm.c - - - 5 - 46 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\shell.c - shell.c - - - 5 - 47 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\finsh\symbol.c - symbol.c - - - - - LwIP - 0 - 0 - 0 - - 6 - 48 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\api\api_lib.c - api_lib.c - - - 6 - 49 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\api\api_msg.c - api_msg.c - - - 6 - 50 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\api\err.c - err.c - - - 6 - 51 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\api\netbuf.c - netbuf.c - - - 6 - 52 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\api\netdb.c - netdb.c - - - 6 - 53 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\api\netifapi.c - netifapi.c - - - 6 - 54 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\api\sockets.c - sockets.c - - - 6 - 55 - 1 - 0 - 0 - 0 - 0 - 534 - 546 - 0 - ..\..\components\net\lwip\src\api\tcpip.c - tcpip.c - - - 6 - 56 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\arch\sys_arch.c - sys_arch.c - - - 6 - 57 - 1 - 0 - 0 - 0 - 0 - 25 - 36 - 0 - ..\..\components\net\lwip\src\arch\sys_arch_init.c - sys_arch_init.c - - - 6 - 58 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\dhcp.c - dhcp.c - - - 6 - 59 - 1 - 0 - 0 - 0 - 0 - 262 - 274 - 0 - ..\..\components\net\lwip\src\core\dns.c - dns.c - - - 6 - 60 - 1 - 0 - 0 - 0 - 0 - 261 - 272 - 0 - ..\..\components\net\lwip\src\core\init.c - init.c - - - 6 - 61 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\memp.c - memp.c - - - 6 - 62 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\netif.c - netif.c - - - 6 - 63 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\pbuf.c - pbuf.c - - - 6 - 64 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\raw.c - raw.c - - - 6 - 65 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\stats.c - stats.c - - - 6 - 66 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\sys.c - sys.c - - - 6 - 67 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\tcp.c - tcp.c - - - 6 - 68 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\tcp_in.c - tcp_in.c - - - 6 - 69 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\tcp_out.c - tcp_out.c - - - 6 - 70 - 1 - 0 - 0 - 18 - 0 - 578 - 590 - 0 - ..\..\components\net\lwip\src\core\udp.c - udp.c - - - 6 - 71 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\autoip.c - autoip.c - - - 6 - 72 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\icmp.c - icmp.c - - - 6 - 73 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\igmp.c - igmp.c - - - 6 - 74 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\inet.c - inet.c - - - 6 - 75 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\inet_chksum.c - inet_chksum.c - - - 6 - 76 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\ip.c - ip.c - - - 6 - 77 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\ip_addr.c - ip_addr.c - - - 6 - 78 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\core\ipv4\ip_frag.c - ip_frag.c - - - 6 - 79 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\netif\etharp.c - etharp.c - - - 6 - 80 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\netif\ethernetif.c - ethernetif.c - - - 6 - 81 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\components\net\lwip\src\netif\loopif.c - loopif.c - - - 6 - 82 - 1 - 0 - 0 - 0 - 0 - 148 - 148 - 0 - ..\..\components\net\lwip\src\netif\slipif.c - slipif.c - - - - - STM32_StdPeriph - 0 - 0 - 0 - - 7 - 83 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\CMSIS\CM3\CoreSupport\core_cm3.c - core_cm3.c - - - 7 - 84 - 1 - 0 - 0 - 0 - 0 - 257 - 269 - 0 - Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c - system_stm32f10x.c - - - 7 - 85 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c - stm32f10x_crc.c - - - 7 - 86 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c - stm32f10x_rcc.c - - - 7 - 87 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c - stm32f10x_wwdg.c - - - 7 - 88 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c - stm32f10x_pwr.c - - - 7 - 89 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c - stm32f10x_exti.c - - - 7 - 90 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c - stm32f10x_bkp.c - - - 7 - 91 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c - stm32f10x_i2c.c - - - 7 - 92 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c - stm32f10x_adc.c - - - 7 - 93 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c - stm32f10x_dac.c - - - 7 - 94 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c - stm32f10x_rtc.c - - - 7 - 95 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c - stm32f10x_fsmc.c - - - 7 - 96 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c - stm32f10x_tim.c - - - 7 - 97 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c - stm32f10x_iwdg.c - - - 7 - 98 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c - stm32f10x_spi.c - - - 7 - 99 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c - stm32f10x_flash.c - - - 7 - 100 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c - stm32f10x_sdio.c - - - 7 - 101 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c - stm32f10x_gpio.c - - - 7 - 102 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c - stm32f10x_usart.c - - - 7 - 103 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c - stm32f10x_dbgmcu.c - - - 7 - 104 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c - stm32f10x_dma.c - - - 7 - 105 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c - stm32f10x_can.c - - - 7 - 106 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c - stm32f10x_cec.c - - - 7 - 107 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Libraries\STM32F10x_StdPeriph_Driver\src\misc.c - misc.c - - - 7 - 108 - 2 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_cl.s - startup_stm32f10x_cl.s - - - diff --git a/bsp/stm32f107/project.uvproj b/bsp/stm32f107/project.uvproj index b24ef8e9c1..8477594668 100644 --- a/bsp/stm32f107/project.uvproj +++ b/bsp/stm32f107/project.uvproj @@ -1,10 +1,7 @@ - 1.1 -
### uVision Project, (C) Keil Software
- RT-Thread STM32 @@ -15,25 +12,25 @@ STM32F107VC STMicroelectronics IRAM(0x20000000-0x2000FFFF) IROM(0x8000000-0x803FFFF) CLOCK(25000000) CPUTYPE("Cortex-M3") - + "STARTUP\ST\STM32F10x.s" ("STM32 Startup Code") UL2CM3(-O14 -S0 -C0 -N00("ARM Cortex-M3") -D00(1BA00477) -L00(4) -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F10x_CL -FS08000000 -FL040000) 4889 stm32f10x_lib.h - - - - - - - - - + + + + + + + + + SFD\ST\STM32F107x\STM32F107.sfr 0 - - - + + + ST\STM32F10x\ ST\STM32F10x\ @@ -57,18 +54,16 @@ 0 0 - - + + 0 0 - 0 - 0 0 0 - - + + 0 0 @@ -76,12 +71,12 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 - + 0 @@ -95,16 +90,16 @@ 0 0 3 - - + + SARMCM3.DLL - + DARMSTM.DLL -pSTM32F107VC SARMCM3.DLL - + TARMSTM.DLL -pSTM32F107VC @@ -136,23 +131,22 @@ 1 0 1 - 0 0 7 - - - - - + + + + + - - - - - + + + + + Segger\JL2CM3.dll @@ -166,8 +160,8 @@ 4099 Segger\JL2CM3.dll - "" () - + + @@ -199,7 +193,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -330,7 +324,7 @@ 0x0 - + 1 @@ -345,12 +339,11 @@ 0 0 0 - 0 - + STM32F10X_CL, USE_STDPERIPH_DRIVER - - .;..\..\components\CMSIS\Include;..\..\components\dfs;..\..\components\dfs\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\init;..\..\components\net\lwip\src;..\..\components\net\lwip\src\arch\include;..\..\components\net\lwip\src\include;..\..\components\net\lwip\src\include\ipv4;..\..\components\net\lwip\src\include\netif;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x;Libraries\STM32F10x_StdPeriph_Driver\inc;applications;drivers + + Libraries/STM32F10x_StdPeriph_Driver/inc;Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x;../../components/CMSIS/Include;applications;.;drivers;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/drivers/spi;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif;../../components/dfs/include;../../components/dfs/filesystems/elmfat @@ -361,12 +354,11 @@ 0 0 0 - 0 - - - - + + + + @@ -378,28 +370,208 @@ 0 0x08000000 0x20000000 - - - - --keep __fsym_* --keep __vsym_* - - + + + + --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + STM32_StdPeriph + + + system_stm32f10x.c + 1 + Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c + + + + + stm32f10x_crc.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_crc.c + + + + + stm32f10x_rcc.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c + + + + + stm32f10x_wwdg.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_wwdg.c + + + + + stm32f10x_pwr.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_pwr.c + + + + + stm32f10x_exti.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_exti.c + + + + + stm32f10x_bkp.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_bkp.c + + + + + stm32f10x_i2c.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_i2c.c + + + + + stm32f10x_adc.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_adc.c + + + + + stm32f10x_dac.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dac.c + + + + + stm32f10x_rtc.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rtc.c + + + + + stm32f10x_fsmc.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_fsmc.c + + + + + stm32f10x_tim.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c + + + + + stm32f10x_iwdg.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_iwdg.c + + + + + stm32f10x_spi.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_spi.c + + + + + stm32f10x_flash.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_flash.c + + + + + stm32f10x_sdio.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_sdio.c + + + + + stm32f10x_gpio.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c + + + + + stm32f10x_usart.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_usart.c + + + + + stm32f10x_dbgmcu.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dbgmcu.c + + + + + stm32f10x_dma.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_dma.c + + + + + stm32f10x_can.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_can.c + + + + + stm32f10x_cec.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_cec.c + + + + + misc.c + 1 + Libraries/STM32F10x_StdPeriph_Driver/src/misc.c + + + + + startup_stm32f10x_cl.s + 2 + Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/startup/arm/startup_stm32f10x_cl.s + + + Applications application.c 1 - applications\application.c + applications/application.c + + startup.c 1 - applications\startup.c + applications/startup.c @@ -409,172 +581,56 @@ board.c 1 - drivers\board.c + drivers/board.c + + msd.c 1 - drivers\msd.c + drivers/msd.c + + platform.c 1 - drivers\platform.c + drivers/platform.c + + rt_stm32f10x_spi.c 1 - drivers\rt_stm32f10x_spi.c + drivers/rt_stm32f10x_spi.c + + serial.c 1 - drivers\serial.c + drivers/serial.c + + stm32_eth.c 1 - drivers\stm32_eth.c + drivers/stm32_eth.c + + stm32f10x_it.c 1 - drivers\stm32f10x_it.c + drivers/stm32f10x_it.c + + usart.c 1 - drivers\usart.c - - - - - STM32_StdPeriph - - - system_stm32f10x.c - 1 - Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\system_stm32f10x.c - - - stm32f10x_crc.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_crc.c - - - stm32f10x_rcc.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rcc.c - - - stm32f10x_wwdg.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_wwdg.c - - - stm32f10x_pwr.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_pwr.c - - - stm32f10x_exti.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_exti.c - - - stm32f10x_bkp.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_bkp.c - - - stm32f10x_i2c.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_i2c.c - - - stm32f10x_adc.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_adc.c - - - stm32f10x_dac.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dac.c - - - stm32f10x_rtc.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_rtc.c - - - stm32f10x_fsmc.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_fsmc.c - - - stm32f10x_tim.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_tim.c - - - stm32f10x_iwdg.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_iwdg.c - - - stm32f10x_spi.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_spi.c - - - stm32f10x_flash.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_flash.c - - - stm32f10x_sdio.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_sdio.c - - - stm32f10x_gpio.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_gpio.c - - - stm32f10x_usart.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_usart.c - - - stm32f10x_dbgmcu.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dbgmcu.c - - - stm32f10x_dma.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_dma.c - - - stm32f10x_can.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_can.c - - - stm32f10x_cec.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\stm32f10x_cec.c - - - misc.c - 1 - Libraries\STM32F10x_StdPeriph_Driver\src\misc.c - - - startup_stm32f10x_cl.s - 2 - Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x\startup\arm\startup_stm32f10x_cl.s + drivers/usart.c @@ -584,62 +640,91 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + components.c + 1 + ../../src/components.c + + + device.c 1 - ..\..\src\device.c + ../../src/device.c + + idle.c 1 - ..\..\src\idle.c + ../../src/idle.c + + ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c + + irq.c 1 - ..\..\src\irq.c + ../../src/irq.c + + kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c + + mem.c 1 - ..\..\src\mem.c + ../../src/mem.c + + mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c + + object.c 1 - ..\..\src\object.c + ../../src/object.c + + scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c + + thread.c 1 - ..\..\src\thread.c + ../../src/thread.c + + timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -649,62 +734,35 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c + ../../libcpu/arm/cortex-m3/cpuport.c + + context_rvds.S 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S + ../../libcpu/arm/cortex-m3/context_rvds.S + + backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c + + div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c + + showmem.c 1 - ..\..\libcpu\arm\common\showmem.c - - - - - Filesystem - - - dfs.c - 1 - ..\..\components\dfs\src\dfs.c - - - dfs_fs.c - 1 - ..\..\components\dfs\src\dfs_fs.c - - - dfs_file.c - 1 - ..\..\components\dfs\src\dfs_file.c - - - dfs_posix.c - 1 - ..\..\components\dfs\src\dfs_posix.c - - - dfs_elm.c - 1 - ..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - - ff.c - 1 - ..\..\components\dfs\filesystems\elmfat\ff.c + ../../libcpu/arm/common/showmem.c @@ -714,92 +772,108 @@ spi_core.c 1 - ..\..\components\drivers\spi\spi_core.c + ../../components/drivers/spi/spi_core.c + + spi_dev.c 1 - ..\..\components\drivers\spi\spi_dev.c + ../../components/drivers/spi/spi_dev.c finsh - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c + + symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c - - - Components - components.c + cmd.c 1 - ..\..\components\init\components.c + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c @@ -809,182 +883,294 @@ api_lib.c 1 - ..\..\components\net\lwip\src\api\api_lib.c + ../../components/net/lwip-1.4.1/src/api/api_lib.c + + api_msg.c 1 - ..\..\components\net\lwip\src\api\api_msg.c + ../../components/net/lwip-1.4.1/src/api/api_msg.c + + err.c 1 - ..\..\components\net\lwip\src\api\err.c + ../../components/net/lwip-1.4.1/src/api/err.c + + netbuf.c 1 - ..\..\components\net\lwip\src\api\netbuf.c + ../../components/net/lwip-1.4.1/src/api/netbuf.c + + netdb.c 1 - ..\..\components\net\lwip\src\api\netdb.c + ../../components/net/lwip-1.4.1/src/api/netdb.c + + netifapi.c 1 - ..\..\components\net\lwip\src\api\netifapi.c + ../../components/net/lwip-1.4.1/src/api/netifapi.c + + sockets.c 1 - ..\..\components\net\lwip\src\api\sockets.c + ../../components/net/lwip-1.4.1/src/api/sockets.c + + tcpip.c 1 - ..\..\components\net\lwip\src\api\tcpip.c + ../../components/net/lwip-1.4.1/src/api/tcpip.c + + sys_arch.c 1 - ..\..\components\net\lwip\src\arch\sys_arch.c + ../../components/net/lwip-1.4.1/src/arch/sys_arch.c + + def.c 1 - ..\..\components\net\lwip\src\core\def.c + ../../components/net/lwip-1.4.1/src/core/def.c + + dhcp.c 1 - ..\..\components\net\lwip\src\core\dhcp.c + ../../components/net/lwip-1.4.1/src/core/dhcp.c + + dns.c 1 - ..\..\components\net\lwip\src\core\dns.c + ../../components/net/lwip-1.4.1/src/core/dns.c + + init.c 1 - ..\..\components\net\lwip\src\core\init.c + ../../components/net/lwip-1.4.1/src/core/init.c + + memp.c 1 - ..\..\components\net\lwip\src\core\memp.c + ../../components/net/lwip-1.4.1/src/core/memp.c + + netif.c 1 - ..\..\components\net\lwip\src\core\netif.c + ../../components/net/lwip-1.4.1/src/core/netif.c + + pbuf.c 1 - ..\..\components\net\lwip\src\core\pbuf.c + ../../components/net/lwip-1.4.1/src/core/pbuf.c + + raw.c 1 - ..\..\components\net\lwip\src\core\raw.c + ../../components/net/lwip-1.4.1/src/core/raw.c + + stats.c 1 - ..\..\components\net\lwip\src\core\stats.c + ../../components/net/lwip-1.4.1/src/core/stats.c + + sys.c 1 - ..\..\components\net\lwip\src\core\sys.c + ../../components/net/lwip-1.4.1/src/core/sys.c + + tcp.c 1 - ..\..\components\net\lwip\src\core\tcp.c + ../../components/net/lwip-1.4.1/src/core/tcp.c + + tcp_in.c 1 - ..\..\components\net\lwip\src\core\tcp_in.c + ../../components/net/lwip-1.4.1/src/core/tcp_in.c + + tcp_out.c 1 - ..\..\components\net\lwip\src\core\tcp_out.c + ../../components/net/lwip-1.4.1/src/core/tcp_out.c + + timers.c 1 - ..\..\components\net\lwip\src\core\timers.c + ../../components/net/lwip-1.4.1/src/core/timers.c + + udp.c 1 - ..\..\components\net\lwip\src\core\udp.c + ../../components/net/lwip-1.4.1/src/core/udp.c + + autoip.c 1 - ..\..\components\net\lwip\src\core\ipv4\autoip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c + + icmp.c 1 - ..\..\components\net\lwip\src\core\ipv4\icmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c + + igmp.c 1 - ..\..\components\net\lwip\src\core\ipv4\igmp.c + ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c + + inet.c 1 - ..\..\components\net\lwip\src\core\ipv4\inet.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c + + inet_chksum.c 1 - ..\..\components\net\lwip\src\core\ipv4\inet_chksum.c + ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c + + ip.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + + ip_addr.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip_addr.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + + ip_frag.c 1 - ..\..\components\net\lwip\src\core\ipv4\ip_frag.c + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + + etharp.c 1 - ..\..\components\net\lwip\src\netif\etharp.c + ../../components/net/lwip-1.4.1/src/netif/etharp.c + + ethernetif.c 1 - ..\..\components\net\lwip\src\netif\ethernetif.c + ../../components/net/lwip-1.4.1/src/netif/ethernetif.c + + slipif.c 1 - ..\..\components\net\lwip\src\netif\slipif.c + ../../components/net/lwip-1.4.1/src/netif/slipif.c + + + + + Filesystem + + + dfs.c + 1 + ../../components/dfs/src/dfs.c + + + + + dfs_file.c + 1 + ../../components/dfs/src/dfs_file.c + + + + + dfs_fs.c + 1 + ../../components/dfs/src/dfs_fs.c + + + + + dfs_posix.c + 1 + ../../components/dfs/src/dfs_posix.c + + + + + dfs_elm.c + 1 + ../../components/dfs/filesystems/elmfat/dfs_elm.c + + + + + ff.c + 1 + ../../components/dfs/filesystems/elmfat/ff.c - diff --git a/bsp/stm32f10x/project.Uv2 b/bsp/stm32f10x/project.Uv2 index 05ab3d45a4..24b5acc90b 100644 --- a/bsp/stm32f10x/project.Uv2 +++ b/bsp/stm32f10x/project.Uv2 @@ -3,84 +3,83 @@ Target (RT-Thread STM32), 0x0004 // Tools: 'ARM-ADS' +Group (STM32_StdPeriph) Group (Applications) Group (Drivers) -Group (STM32_StdPeriph) Group (Kernel) Group (CORTEX-M3) Group (DeviceDrivers) Group (finsh) -Group (Components) -File 1,1, -File 1,1, -File 2,1, -File 2,1, -File 2,1, -File 2,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,1, -File 3,2, -File 4,1,<..\..\src\clock.c> -File 4,1,<..\..\src\device.c> -File 4,1,<..\..\src\idle.c> -File 4,1,<..\..\src\ipc.c> -File 4,1,<..\..\src\irq.c> -File 4,1,<..\..\src\kservice.c> -File 4,1,<..\..\src\mem.c> -File 4,1,<..\..\src\mempool.c> -File 4,1,<..\..\src\object.c> -File 4,1,<..\..\src\scheduler.c> -File 4,1,<..\..\src\thread.c> -File 4,1,<..\..\src\timer.c> -File 5,1,<..\..\libcpu\arm\cortex-m3\cpuport.c> -File 5,2,<..\..\libcpu\arm\cortex-m3\context_rvds.S> -File 5,1,<..\..\libcpu\arm\common\backtrace.c> -File 5,1,<..\..\libcpu\arm\common\div0.c> -File 5,1,<..\..\libcpu\arm\common\showmem.c> -File 6,1,<..\..\components\drivers\serial\serial.c> -File 6,1,<..\..\components\drivers\src\completion.c> -File 6,1,<..\..\components\drivers\src\dataqueue.c> -File 6,1,<..\..\components\drivers\src\pipe.c> -File 6,1,<..\..\components\drivers\src\ringbuffer.c> -File 7,1,<..\..\components\finsh\cmd.c> -File 7,1,<..\..\components\finsh\finsh_compiler.c> -File 7,1,<..\..\components\finsh\finsh_error.c> -File 7,1,<..\..\components\finsh\finsh_heap.c> -File 7,1,<..\..\components\finsh\finsh_init.c> -File 7,1,<..\..\components\finsh\finsh_node.c> -File 7,1,<..\..\components\finsh\finsh_ops.c> -File 7,1,<..\..\components\finsh\finsh_parser.c> -File 7,1,<..\..\components\finsh\finsh_token.c> -File 7,1,<..\..\components\finsh\finsh_var.c> -File 7,1,<..\..\components\finsh\finsh_vm.c> -File 7,1,<..\..\components\finsh\msh.c> -File 7,1,<..\..\components\finsh\msh_cmd.c> -File 7,1,<..\..\components\finsh\shell.c> -File 7,1,<..\..\components\finsh\symbol.c> -File 8,1,<..\..\components\init\components.c> +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,1, +File 1,2, +File 2,1, +File 2,1, +File 3,1, +File 3,1, +File 3,1, +File 3,1, +File 4,1,<../../src/clock.c> +File 4,1,<../../src/components.c> +File 4,1,<../../src/device.c> +File 4,1,<../../src/idle.c> +File 4,1,<../../src/ipc.c> +File 4,1,<../../src/irq.c> +File 4,1,<../../src/kservice.c> +File 4,1,<../../src/mem.c> +File 4,1,<../../src/mempool.c> +File 4,1,<../../src/object.c> +File 4,1,<../../src/scheduler.c> +File 4,1,<../../src/thread.c> +File 4,1,<../../src/timer.c> +File 5,1,<../../libcpu/arm/cortex-m3/cpuport.c> +File 5,2,<../../libcpu/arm/cortex-m3/context_rvds.S> +File 5,1,<../../libcpu/arm/common/backtrace.c> +File 5,1,<../../libcpu/arm/common/div0.c> +File 5,1,<../../libcpu/arm/common/showmem.c> +File 6,1,<../../components/drivers/serial/serial.c> +File 6,1,<../../components/drivers/src/completion.c> +File 6,1,<../../components/drivers/src/dataqueue.c> +File 6,1,<../../components/drivers/src/pipe.c> +File 6,1,<../../components/drivers/src/portal.c> +File 6,1,<../../components/drivers/src/ringbuffer.c> +File 6,1,<../../components/drivers/src/workqueue.c> +File 7,1,<../../components/finsh/shell.c> +File 7,1,<../../components/finsh/symbol.c> +File 7,1,<../../components/finsh/cmd.c> +File 7,1,<../../components/finsh/finsh_compiler.c> +File 7,1,<../../components/finsh/finsh_error.c> +File 7,1,<../../components/finsh/finsh_heap.c> +File 7,1,<../../components/finsh/finsh_init.c> +File 7,1,<../../components/finsh/finsh_node.c> +File 7,1,<../../components/finsh/finsh_ops.c> +File 7,1,<../../components/finsh/finsh_parser.c> +File 7,1,<../../components/finsh/finsh_var.c> +File 7,1,<../../components/finsh/finsh_vm.c> +File 7,1,<../../components/finsh/finsh_token.c> @@ -143,7 +142,7 @@ Options 1,0,0 // Target 'RT-Thread STM32' ADSCMISC () ADSCDEFN (STM32F10X_HD, USE_STDPERIPH_DRIVER) ADSCUDEF () - ADSCINCD (Libraries\STM32F10x_StdPeriph_Driver\inc;..\..\include;drivers;..\..\components\CMSIS\Include;.;applications;..\..\libcpu\arm\cortex-m3;..\..\components\drivers\include;..\..\libcpu\arm\common;..\..\components\init;..\..\components\finsh;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F10x) + ADSCINCD (../../libcpu/arm/cortex-m3;../../components/drivers/include;Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x;../../libcpu/arm/common;.;applications;../../include;../../components/finsh;../../components/CMSIS/Include;drivers;Libraries/STM32F10x_StdPeriph_Driver/inc) ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ADSAMISC () ADSADEFN () @@ -164,7 +163,7 @@ Options 1,0,0 // Target 'RT-Thread STM32' ADSLDSC () ADSLDIB () ADSLDIC () - ADSLDMC ( --keep __fsym_* --keep __vsym_* --keep __rt_init* ) + ADSLDMC ( --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) ) ADSLDIF () ADSLDDW () OPTDL (SARMCM3.DLL)()(DARMSTM.DLL)(-pSTM32F103ZE)(SARMCM3.DLL)()(TARMSTM.DLL)(-pSTM32F103ZE) diff --git a/bsp/stm32f20x/project.uvproj b/bsp/stm32f20x/project.uvproj index 96322bfc57..908eed33a0 100644 --- a/bsp/stm32f20x/project.uvproj +++ b/bsp/stm32f20x/project.uvproj @@ -343,7 +343,7 @@ USE_STDPERIPH_DRIVER - .;..\..\components\CMSIS\Include;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m3;Drivers;Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx;Libraries\STM32F2xx_StdPeriph_Driver\inc;applications + Libraries/STM32F2xx_StdPeriph_Driver/inc;Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx;../../components/CMSIS/Include;applications;.;Drivers;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/finsh @@ -373,27 +373,261 @@ - --keep __fsym_* --keep __vsym_* + --keep *.o(FSymTab) --keep *.o(VSymTab) + + STM32_StdPeriph + + + system_stm32f2xx.c + 1 + Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/system_stm32f2xx.c + + + + + misc.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c + + + + + stm32f2xx_adc.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c + + + + + stm32f2xx_can.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c + + + + + stm32f2xx_crc.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c + + + + + stm32f2xx_cryp.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c + + + + + stm32f2xx_cryp_aes.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c + + + + + stm32f2xx_cryp_des.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_des.c + + + + + stm32f2xx_cryp_tdes.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_tdes.c + + + + + stm32f2xx_dac.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dac.c + + + + + stm32f2xx_dbgmcu.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c + + + + + stm32f2xx_dcmi.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c + + + + + stm32f2xx_dma.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c + + + + + stm32f2xx_exti.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c + + + + + stm32f2xx_flash.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c + + + + + stm32f2xx_fsmc.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c + + + + + stm32f2xx_gpio.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c + + + + + stm32f2xx_hash.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c + + + + + stm32f2xx_hash_md5.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c + + + + + stm32f2xx_hash_sha1.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_sha1.c + + + + + stm32f2xx_i2c.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_i2c.c + + + + + stm32f2xx_iwdg.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c + + + + + stm32f2xx_pwr.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c + + + + + stm32f2xx_rcc.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c + + + + + stm32f2xx_rng.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c + + + + + stm32f2xx_rtc.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c + + + + + stm32f2xx_sdio.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c + + + + + stm32f2xx_spi.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c + + + + + stm32f2xx_syscfg.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c + + + + + stm32f2xx_tim.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c + + + + + stm32f2xx_usart.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c + + + + + stm32f2xx_wwdg.c + 1 + Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c + + + + + startup_stm32f2xx.s + 2 + Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F2xx/startup/arm/startup_stm32f2xx.s + + + Applications application.c 1 - applications\application.c + applications/application.c startup.c 1 - applications\startup.c + applications/startup.c @@ -403,290 +637,56 @@ 24LCxx.c 1 - Drivers\24LCxx.c + Drivers/24LCxx.c FM25Lx.c 1 - Drivers\FM25Lx.c + Drivers/FM25Lx.c board.c 1 - Drivers\board.c + Drivers/board.c i2c.c 1 - Drivers\i2c.c + Drivers/i2c.c rtc.c 1 - Drivers\rtc.c + Drivers/rtc.c serial.c 1 - Drivers\serial.c + Drivers/serial.c stm32f2xx_it.c 1 - Drivers\stm32f2xx_it.c + Drivers/stm32f2xx_it.c usart.c 1 - Drivers\usart.c - - - - - STM32_StdPeriph - - - system_stm32f2xx.c - 1 - Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\system_stm32f2xx.c - - - - - misc.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\misc.c - - - - - stm32f2xx_adc.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_adc.c - - - - - stm32f2xx_can.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_can.c - - - - - stm32f2xx_crc.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_crc.c - - - - - stm32f2xx_cryp.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp.c - - - - - stm32f2xx_cryp_aes.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_aes.c - - - - - stm32f2xx_cryp_des.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_des.c - - - - - stm32f2xx_cryp_tdes.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_cryp_tdes.c - - - - - stm32f2xx_dac.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dac.c - - - - - stm32f2xx_dbgmcu.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dbgmcu.c - - - - - stm32f2xx_dcmi.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dcmi.c - - - - - stm32f2xx_dma.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_dma.c - - - - - stm32f2xx_exti.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_exti.c - - - - - stm32f2xx_flash.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_flash.c - - - - - stm32f2xx_fsmc.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_fsmc.c - - - - - stm32f2xx_gpio.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_gpio.c - - - - - stm32f2xx_hash.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash.c - - - - - stm32f2xx_hash_md5.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_md5.c - - - - - stm32f2xx_hash_sha1.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_hash_sha1.c - - - - - stm32f2xx_i2c.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_i2c.c - - - - - stm32f2xx_iwdg.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_iwdg.c - - - - - stm32f2xx_pwr.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_pwr.c - - - - - stm32f2xx_rcc.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rcc.c - - - - - stm32f2xx_rng.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rng.c - - - - - stm32f2xx_rtc.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_rtc.c - - - - - stm32f2xx_sdio.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_sdio.c - - - - - stm32f2xx_spi.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_spi.c - - - - - stm32f2xx_syscfg.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_syscfg.c - - - - - stm32f2xx_tim.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_tim.c - - - - - stm32f2xx_usart.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_usart.c - - - - - stm32f2xx_wwdg.c - 1 - Libraries\STM32F2xx_StdPeriph_Driver\src\stm32f2xx_wwdg.c - - - - - startup_stm32f2xx.s - 2 - Libraries\CMSIS\CM3\DeviceSupport\ST\STM32F2xx\startup\arm\startup_stm32f2xx.s + Drivers/usart.c @@ -696,84 +696,91 @@ clock.c 1 - ..\..\src\clock.c + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c device.c 1 - ..\..\src\device.c + ../../src/device.c idle.c 1 - ..\..\src\idle.c + ../../src/idle.c ipc.c 1 - ..\..\src\ipc.c + ../../src/ipc.c irq.c 1 - ..\..\src\irq.c + ../../src/irq.c kservice.c 1 - ..\..\src\kservice.c + ../../src/kservice.c mem.c 1 - ..\..\src\mem.c + ../../src/mem.c mempool.c 1 - ..\..\src\mempool.c + ../../src/mempool.c object.c 1 - ..\..\src\object.c + ../../src/object.c scheduler.c 1 - ..\..\src\scheduler.c + ../../src/scheduler.c thread.c 1 - ..\..\src\thread.c + ../../src/thread.c timer.c 1 - ..\..\src\timer.c + ../../src/timer.c @@ -783,129 +790,129 @@ cpuport.c 1 - ..\..\libcpu\arm\cortex-m3\cpuport.c + ../../libcpu/arm/cortex-m3/cpuport.c context_rvds.S 2 - ..\..\libcpu\arm\cortex-m3\context_rvds.S + ../../libcpu/arm/cortex-m3/context_rvds.S backtrace.c 1 - ..\..\libcpu\arm\common\backtrace.c + ../../libcpu/arm/common/backtrace.c div0.c 1 - ..\..\libcpu\arm\common\div0.c + ../../libcpu/arm/common/div0.c showmem.c 1 - ..\..\libcpu\arm\common\showmem.c + ../../libcpu/arm/common/showmem.c finsh - - - cmd.c - 1 - ..\..\components\finsh\cmd.c - - - - - finsh_compiler.c - 1 - ..\..\components\finsh\finsh_compiler.c - - - - - finsh_error.c - 1 - ..\..\components\finsh\finsh_error.c - - - - - finsh_heap.c - 1 - ..\..\components\finsh\finsh_heap.c - - - - - finsh_init.c - 1 - ..\..\components\finsh\finsh_init.c - - - - - finsh_node.c - 1 - ..\..\components\finsh\finsh_node.c - - - - - finsh_ops.c - 1 - ..\..\components\finsh\finsh_ops.c - - - - - finsh_parser.c - 1 - ..\..\components\finsh\finsh_parser.c - - - - - finsh_token.c - 1 - ..\..\components\finsh\finsh_token.c - - - - - finsh_var.c - 1 - ..\..\components\finsh\finsh_var.c - - - - - finsh_vm.c - 1 - ..\..\components\finsh\finsh_vm.c - - shell.c 1 - ..\..\components\finsh\shell.c + ../../components/finsh/shell.c symbol.c 1 - ..\..\components\finsh\symbol.c + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c diff --git a/bsp/stm32f40x/project.uvproj b/bsp/stm32f40x/project.uvproj index da6c71a151..679e04d729 100644 --- a/bsp/stm32f40x/project.uvproj +++ b/bsp/stm32f40x/project.uvproj @@ -343,7 +343,7 @@ USE_STDPERIPH_DRIVER - applications;.;Libraries/STM32F4xx_StdPeriph_Driver/inc;Libraries/CMSIS/ST/STM32F4xx/Include;Libraries/CMSIS/Include;drivers;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/finsh;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include + Libraries/STM32F4xx_StdPeriph_Driver/inc;Libraries/CMSIS/ST/STM32F4xx/Include;Libraries/CMSIS/Include;applications;.;drivers;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/drivers/include;../../components/finsh @@ -373,30 +373,13 @@ - --keep __fsym_* --keep __vsym_* + --keep *.o(FSymTab) --keep *.o(VSymTab) - - Applications - - - application.c - 1 - applications/application.c - - - - - startup.c - 1 - applications/startup.c - - - STM32_StdPeriph @@ -631,6 +614,23 @@ + + Applications + + + application.c + 1 + applications/application.c + + + + + startup.c + 1 + applications/startup.c + + + Drivers @@ -640,13 +640,6 @@ drivers/board.c - - - gpio.c - 1 - drivers/gpio.c - - stm32f4xx_it.c @@ -661,6 +654,13 @@ drivers/usart.c + + + gpio.c + 1 + drivers/gpio.c + + Kernel @@ -671,6 +671,13 @@ ../../src/clock.c + + + components.c + 1 + ../../src/components.c + + device.c @@ -787,6 +794,65 @@ + + DeviceDrivers + + + pin.c + 1 + ../../components/drivers/misc/pin.c + + + + + serial.c + 1 + ../../components/drivers/serial/serial.c + + + + + completion.c + 1 + ../../components/drivers/src/completion.c + + + + + dataqueue.c + 1 + ../../components/drivers/src/dataqueue.c + + + + + pipe.c + 1 + ../../components/drivers/src/pipe.c + + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + + + ringbuffer.c + 1 + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c + + + finsh @@ -881,65 +947,6 @@ - - DeviceDrivers - - - serial.c - 1 - ../../components/drivers/serial/serial.c - - - - - pin.c - 1 - ../../components/drivers/misc/pin.c - - - - - completion.c - 1 - ../../components/drivers/src/completion.c - - - - - dataqueue.c - 1 - ../../components/drivers/src/dataqueue.c - - - - - pipe.c - 1 - ../../components/drivers/src/pipe.c - - - - - portal.c - 1 - ../../components/drivers/src/portal.c - - - - - ringbuffer.c - 1 - ../../components/drivers/src/ringbuffer.c - - - - - workqueue.c - 1 - ../../components/drivers/src/workqueue.c - - - diff --git a/bsp/tm4c129x/project.uvproj b/bsp/tm4c129x/project.uvproj new file mode 100644 index 0000000000..5a9d572475 --- /dev/null +++ b/bsp/tm4c129x/project.uvproj @@ -0,0 +1,1210 @@ + + + 1.1 +
### uVision Project, (C) Keil Software
+ + + RT-Thread TM4C129X + 0x4 + ARM-ADS + + + TM4C1294NCPDT + Texas Instruments + Keil.TM4C_DFP.1.0.0 + http://www.keil.com/pack/ + IROM(0x00000000,0x100000) IRAM(0x20000000,0x040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(120000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0TM4C129_1024 -FS00 -FL0100000 -FP0($$Device:TM4C1294NCPDT$Flash\TM4C129_1024.FLM)) + 7088 + $$Device:TM4C1294NCPDT$Device\Include\TM4C129\TM4C129.h + + + + + + + -DTM4C1294NCPDT + + + $$Device:TM4C1294NCPDT$SVD\TM4C129\TM4C1294NCPDT.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\ + rtthread-tm4c + 1 + 0 + 0 + 1 + 1 + .\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x40000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + + + PART_TM4C129XNCZAD + + libraries;libraries/inc;libraries/driverlib;applications;.;drivers;../../include;../../libcpu/arm/cortex-m4;../../libcpu/arm/common;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x00000000 + + tm4c_rom.sct + + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) + + + + + + + + Libraries + + + adc.c + 1 + libraries/driverlib/adc.c + + + + + aes.c + 1 + libraries/driverlib/aes.c + + + + + can.c + 1 + libraries/driverlib/can.c + + + + + comp.c + 1 + libraries/driverlib/comp.c + + + + + cpu.c + 1 + libraries/driverlib/cpu.c + + + + + crc.c + 1 + libraries/driverlib/crc.c + + + + + des.c + 1 + libraries/driverlib/des.c + + + + + eeprom.c + 1 + libraries/driverlib/eeprom.c + + + + + emac.c + 1 + libraries/driverlib/emac.c + + + + + epi.c + 1 + libraries/driverlib/epi.c + + + + + flash.c + 1 + libraries/driverlib/flash.c + + + + + fpu.c + 1 + libraries/driverlib/fpu.c + + + + + gpio.c + 1 + libraries/driverlib/gpio.c + + + + + hibernate.c + 1 + libraries/driverlib/hibernate.c + + + + + i2c.c + 1 + libraries/driverlib/i2c.c + + + + + interrupt.c + 1 + libraries/driverlib/interrupt.c + + + + + lcd.c + 1 + libraries/driverlib/lcd.c + + + + + mpu.c + 1 + libraries/driverlib/mpu.c + + + + + pwm.c + 1 + libraries/driverlib/pwm.c + + + + + qei.c + 1 + libraries/driverlib/qei.c + + + + + shamd5.c + 1 + libraries/driverlib/shamd5.c + + + + + ssi.c + 1 + libraries/driverlib/ssi.c + + + + + sw_crc.c + 1 + libraries/driverlib/sw_crc.c + + + + + sysctl.c + 1 + libraries/driverlib/sysctl.c + + + + + sysexc.c + 1 + libraries/driverlib/sysexc.c + + + + + systick.c + 1 + libraries/driverlib/systick.c + + + + + tiva_timer.c + 1 + libraries/driverlib/tiva_timer.c + + + + + uart.c + 1 + libraries/driverlib/uart.c + + + + + udma.c + 1 + libraries/driverlib/udma.c + + + + + usb.c + 1 + libraries/driverlib/usb.c + + + + + watchdog.c + 1 + libraries/driverlib/watchdog.c + + + + + startup_rvmdk.S + 2 + libraries/startup/startup_rvmdk.S + + + + + Applications + + + application.c + 1 + applications/application.c + + + + + board.c + 1 + applications/board.c + + + + + startup.c + 1 + applications/startup.c + + + + + Drivers + + + drv_eth.c + 1 + drivers/drv_eth.c + + + + + drv_uart.c + 1 + drivers/drv_uart.c + + + + + Kernel + + + clock.c + 1 + ../../src/clock.c + + + + + components.c + 1 + ../../src/components.c + + + + + device.c + 1 + ../../src/device.c + + + + + idle.c + 1 + ../../src/idle.c + + + + + ipc.c + 1 + ../../src/ipc.c + + + + + irq.c + 1 + ../../src/irq.c + + + + + kservice.c + 1 + ../../src/kservice.c + + + + + mem.c + 1 + ../../src/mem.c + + + + + memheap.c + 1 + ../../src/memheap.c + + + + + mempool.c + 1 + ../../src/mempool.c + + + + + object.c + 1 + ../../src/object.c + + + + + scheduler.c + 1 + ../../src/scheduler.c + + + + + thread.c + 1 + ../../src/thread.c + + + + + timer.c + 1 + ../../src/timer.c + + + + + CORTEX-M4 + + + cpuport.c + 1 + ../../libcpu/arm/cortex-m4/cpuport.c + + + + + context_rvds.S + 2 + ../../libcpu/arm/cortex-m4/context_rvds.S + + + + + backtrace.c + 1 + ../../libcpu/arm/common/backtrace.c + + + + + div0.c + 1 + ../../libcpu/arm/common/div0.c + + + + + showmem.c + 1 + ../../libcpu/arm/common/showmem.c + + + + + DeviceDrivers + + + serial.c + 1 + ../../components/drivers/serial/serial.c + + + + + completion.c + 1 + ../../components/drivers/src/completion.c + + + + + dataqueue.c + 1 + ../../components/drivers/src/dataqueue.c + + + + + pipe.c + 1 + ../../components/drivers/src/pipe.c + + + + + portal.c + 1 + ../../components/drivers/src/portal.c + + + + + ringbuffer.c + 1 + ../../components/drivers/src/ringbuffer.c + + + + + workqueue.c + 1 + ../../components/drivers/src/workqueue.c + + + + + finsh + + + shell.c + 1 + ../../components/finsh/shell.c + + + + + symbol.c + 1 + ../../components/finsh/symbol.c + + + + + cmd.c + 1 + ../../components/finsh/cmd.c + + + + + finsh_compiler.c + 1 + ../../components/finsh/finsh_compiler.c + + + + + finsh_error.c + 1 + ../../components/finsh/finsh_error.c + + + + + finsh_heap.c + 1 + ../../components/finsh/finsh_heap.c + + + + + finsh_init.c + 1 + ../../components/finsh/finsh_init.c + + + + + finsh_node.c + 1 + ../../components/finsh/finsh_node.c + + + + + finsh_ops.c + 1 + ../../components/finsh/finsh_ops.c + + + + + finsh_parser.c + 1 + ../../components/finsh/finsh_parser.c + + + + + finsh_var.c + 1 + ../../components/finsh/finsh_var.c + + + + + finsh_vm.c + 1 + ../../components/finsh/finsh_vm.c + + + + + finsh_token.c + 1 + ../../components/finsh/finsh_token.c + + + + + LwIP + + + api_lib.c + 1 + ../../components/net/lwip-1.4.1/src/api/api_lib.c + + + + + api_msg.c + 1 + ../../components/net/lwip-1.4.1/src/api/api_msg.c + + + + + err.c + 1 + ../../components/net/lwip-1.4.1/src/api/err.c + + + + + netbuf.c + 1 + ../../components/net/lwip-1.4.1/src/api/netbuf.c + + + + + netdb.c + 1 + ../../components/net/lwip-1.4.1/src/api/netdb.c + + + + + netifapi.c + 1 + ../../components/net/lwip-1.4.1/src/api/netifapi.c + + + + + sockets.c + 1 + ../../components/net/lwip-1.4.1/src/api/sockets.c + + + + + tcpip.c + 1 + ../../components/net/lwip-1.4.1/src/api/tcpip.c + + + + + sys_arch.c + 1 + ../../components/net/lwip-1.4.1/src/arch/sys_arch.c + + + + + def.c + 1 + ../../components/net/lwip-1.4.1/src/core/def.c + + + + + dhcp.c + 1 + ../../components/net/lwip-1.4.1/src/core/dhcp.c + + + + + dns.c + 1 + ../../components/net/lwip-1.4.1/src/core/dns.c + + + + + init.c + 1 + ../../components/net/lwip-1.4.1/src/core/init.c + + + + + memp.c + 1 + ../../components/net/lwip-1.4.1/src/core/memp.c + + + + + netif.c + 1 + ../../components/net/lwip-1.4.1/src/core/netif.c + + + + + pbuf.c + 1 + ../../components/net/lwip-1.4.1/src/core/pbuf.c + + + + + raw.c + 1 + ../../components/net/lwip-1.4.1/src/core/raw.c + + + + + stats.c + 1 + ../../components/net/lwip-1.4.1/src/core/stats.c + + + + + sys.c + 1 + ../../components/net/lwip-1.4.1/src/core/sys.c + + + + + tcp.c + 1 + ../../components/net/lwip-1.4.1/src/core/tcp.c + + + + + tcp_in.c + 1 + ../../components/net/lwip-1.4.1/src/core/tcp_in.c + + + + + tcp_out.c + 1 + ../../components/net/lwip-1.4.1/src/core/tcp_out.c + + + + + timers.c + 1 + ../../components/net/lwip-1.4.1/src/core/timers.c + + + + + udp.c + 1 + ../../components/net/lwip-1.4.1/src/core/udp.c + + + + + autoip.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c + + + + + icmp.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c + + + + + igmp.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c + + + + + inet.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c + + + + + inet_chksum.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c + + + + + ip.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + + + + + ip_addr.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + + + + + ip_frag.c + 1 + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + + + + + etharp.c + 1 + ../../components/net/lwip-1.4.1/src/netif/etharp.c + + + + + ethernetif.c + 1 + ../../components/net/lwip-1.4.1/src/netif/ethernetif.c + + + + + slipif.c + 1 + ../../components/net/lwip-1.4.1/src/netif/slipif.c + + + + + + + From 2313424f811c59563090e77966d906dd3eb7f127 Mon Sep 17 00:00:00 2001 From: BernardXiong Date: Mon, 11 May 2015 21:12:53 +0800 Subject: [PATCH 07/18] [tools] Add better way to generate MDK project file. --- tools/buildbot.py | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tools/buildbot.py b/tools/buildbot.py index b782dc6028..0567d84fd8 100644 --- a/tools/buildbot.py +++ b/tools/buildbot.py @@ -19,6 +19,17 @@ elif sys.argv[1] == 'clean': command = ' -c' elif sys.argv[1] == 'project': command = ' --target=mdk -s' + + projects = os.listdir(BSP_ROOT) + for item in projects: + project_dir = os.path.join(BSP_ROOT, item) + + if os.path.isfile(os.path.join(project_dir, 'template.uvproj')): + print ('prepare MDK project file on ' + project_dir) + + os.system('scons --directory=' + project_dir + command) + + sys.exit(0) else: usage() sys.exit(0) From bd592766402653b011414a3336f169c7c6756298 Mon Sep 17 00:00:00 2001 From: toasun Date: Tue, 12 May 2015 13:43:50 +0800 Subject: [PATCH 08/18] Update cmem7_eth.c --- bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c | 137 ++++++++++++++------ 1 file changed, 100 insertions(+), 37 deletions(-) diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c index c8eb45fba0..5c07abebf9 100644 --- a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c +++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_eth.c @@ -5,8 +5,8 @@ * @brief CMEM7 ethernet source file * * - * @version V1.0 - * @date 3. September 2013 + * @version V2.0 + * @date 3. September 2014 * * @note * @@ -25,7 +25,7 @@ */ #include "cmem7_eth.h" - +#include "cmem7_misc.h" typedef struct { union { @@ -49,7 +49,7 @@ typedef struct { uint32_t TCH : 1; /*!< Second Address Chained */ uint32_t : 4; uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */ - uint32_t : 2; + uint32_t : 2; uint32_t FS : 1; /*!< first segment flag */ uint32_t LS : 1; /*!< last segment flag */ uint32_t IC : 1; /*!< Interrupt on Completion */ @@ -190,8 +190,9 @@ static void mac_SetConfig(ETH_InitTypeDef *init) { ETH->CONFIG_b.IPC = init->ETH_ChecksumOffload; ETH->CONFIG_b.DM = init->ETH_Duplex; ETH->CONFIG_b.LM = FALSE; - ETH->MMC_RX_MASK = 0xFFFFFFFF; - ETH->MMC_TX_MASK = 0xFFFFFFFF; + ETH->MMCRIMR = 0xFFFFFFFF; + ETH->MMCTIMR = 0xFFFFFFFF; + ETH->MMCIRCOIM = 0xFFFFFFFF; if (init->ETH_Speed == ETH_SPEED_10M) { ETH->CONFIG_b.FES = ETH_EXACT_SPEED_10M_BPS; @@ -209,7 +210,7 @@ static void mac_SetConfig(ETH_InitTypeDef *init) { ETH->CONFIG_b.JD = TRUE; ETH->CONFIG_b.WD = TRUE; ETH->CONFIG_b.TC = FALSE; - ETH->CONFIG_b.CST = FALSE; + ETH->CONFIG_b.CST = TRUE; ETH->CONFIG_b.TWOKPE = FALSE; ETH->CONFIG_b.SARC = ETH_SOURCE_ADDR_REPLACE; } @@ -318,7 +319,7 @@ static void mac_SetFrameFilter(ETH_FrameFilter *filter) { ETH->FF_b.VTFE = FALSE; ETH->FF_b.IPFE = FALSE; ETH->FF_b.DNTU = FALSE; - ETH->FF_b.RA = TRUE; + ETH->FF_b.RA = FALSE;//TRUE // receive all if (!filter) { @@ -339,14 +340,20 @@ static void mac_SetFrameFilter(ETH_FrameFilter *filter) { // SA if (filter->ETH_SourceFilterEnable) { - ETH->FF_b.RA = FALSE; + uint32_t value; + + ETH->FF_b.RA = FALSE; ETH->FF_b.SAF = TRUE; ETH->FF_b.SAIF = filter->ETH_SourceDrop; ETH->ADDR1_HIGH_b.AE = TRUE; - ETH->ADDR1_HIGH_b.SA = TRUE; - ETH->ADDR1_HIGH_b.ADDR = + ETH->ADDR1_HIGH_b.SA = TRUE; + ETH->ADDR1_HIGH_b.ADDR = (filter->ETH_SourceMacAddr[5] << 8) | filter->ETH_SourceMacAddr[4]; - ETH->ADDR1_LOW = (filter->ETH_SourceMacAddr[3] << 24) | + + +// value = (filter->ETH_SourceMacAddr[5] << 8) | filter->ETH_SourceMacAddr[4]; +// CMEM7_BFI(&(ETH->ADDR1_HIGH), value, 0, 16); + ETH->ADDR1_LOW = (filter->ETH_SourceMacAddr[3] << 24) | (filter->ETH_SourceMacAddr[2] << 16) | (filter->ETH_SourceMacAddr[1] << 8) | filter->ETH_SourceMacAddr[0]; @@ -355,9 +362,9 @@ static void mac_SetFrameFilter(ETH_FrameFilter *filter) { static void mac_setFlowControl(void) { ETH->FC_b.FCB = FALSE; - ETH->FC_b.TFE = TRUE; - ETH->FC_b.RFE = TRUE; - ETH->FC_b.UP = TRUE; + ETH->FC_b.TFE = FALSE;//TRUE + ETH->FC_b.RFE = FALSE;//TRUE + ETH->FC_b.UP = FALSE;//TRUE } uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg) { @@ -381,27 +388,44 @@ void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data) { while (ETH->GMII_ADDR_b.BUSY) ; } - +void ETH_StructInit(ETH_InitTypeDef* init) +{ + init->ETH_Speed = ETH_SPEED_10M; + init->ETH_Duplex = ETH_DUPLEX_FULL; + init->ETH_JumboFrame = FALSE; + init->ETH_LinkUp = FALSE; + init->ETH_RxEn = TRUE; + init->ETH_TxEn = TRUE; + init->ETH_ChecksumOffload = FALSE; + init->ETH_Filter = 0; + init->ETH_MacAddr[0] = 0; + init->ETH_MacAddr[1] = 0; + init->ETH_MacAddr[2] = 0; + init->ETH_MacAddr[3] = 0; + init->ETH_MacAddr[4] = 0; + init->ETH_MacAddr[5] = 0; + +} BOOL ETH_Init(ETH_InitTypeDef *init) { - assert_param(init); - assert_param(IS_ETH_SPEED(init->ETH_Speed)); - assert_param(IS_ETH_DUPLEX(init->ETH_Duplex)); + assert_param(init); + assert_param(IS_ETH_SPEED(init->ETH_Speed)); + assert_param(IS_ETH_DUPLEX(init->ETH_Duplex)); - mac_SwReset(); - mac_SetConfig(init); - mac_SetMacAddr(init->ETH_MacAddr); + mac_SwReset(); + mac_SetConfig(init); + mac_SetMacAddr(init->ETH_MacAddr); - mac_SetBurst(ETH_BURST_MODE_MIXED, 3, 4); - mac_SetPriority(TRUE, 0); - mac_SetDescMode(TRUE, 0); - mac_SetOpertionMode(); - mac_SetFrameFilter(init->ETH_Filter); - mac_setFlowControl(); + mac_SetBurst(ETH_BURST_MODE_MIXED, 3, 4); + mac_SetPriority(TRUE, 0); + mac_SetDescMode(TRUE, 0); + mac_SetOpertionMode(); + mac_SetFrameFilter(init->ETH_Filter); + mac_setFlowControl(); - return TRUE; + return TRUE; } -void ETH_EnableInt(uint32_t Int, BOOL enable) { +void ETH_ITConfig(uint32_t Int, BOOL enable) { assert_param(IS_ETH_INT(Int)); if (enable) { @@ -426,7 +450,7 @@ void ETH_EnableInt(uint32_t Int, BOOL enable) { } } } -BOOL ETH_GetIntStatus(uint32_t Int) { +BOOL ETH_GetITStatus(uint32_t Int) { assert_param(IS_ETH_INT(Int)); Int &= ETH->INT_EN; @@ -436,8 +460,7 @@ BOOL ETH_GetIntStatus(uint32_t Int) { return FALSE; } - -void ETH_ClearInt(uint32_t Int) { +void ETH_ClearITPendingBit(uint32_t Int) { uint32_t sta; assert_param(IS_ETH_INT(Int)); @@ -450,15 +473,15 @@ void ETH_ClearInt(uint32_t Int) { if (IS_ETH_INT_NORMAL(Int)) { if (!IS_ETH_INT_NORMAL(sta)) { - // write 1 clear - ETH->STATUS_b.NIS = 1; + // write 1 clear NIS + ETH->STATUS = ETH_INT_NORMAL_SUMMARY; } } if (IS_ETH_INT_ABNORMAL(Int)) { if (!IS_ETH_INT_ABNORMAL(sta)) { - // write 1 clear - ETH->STATUS_b.AIS = 1; + // write 1 clear AIS + ETH->STATUS = ETH_INT_ABNORMAL_SUMMARY; } } } @@ -491,12 +514,25 @@ BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring) { return FALSE; } + /* If code mapping */ + ring = (ETH_TX_DESC *)GLB_ConvertToMappingFromAddr((uint32_t)ring); + buf = ring; + do { INNER_ETH_TX_DESC *desc = (INNER_ETH_TX_DESC *)buf; + uint8_t first = desc->TX_0.TX0_b.FS; + uint8_t last = desc->TX_0.TX0_b.LS; + + // clear all bits + desc->TX_0.TX0 = 0; + desc->TX_0.TX0_b.FS = first; + desc->TX_0.TX0_b.LS = last; desc->TX_0.TX0_b.TCH = TRUE; desc->TX_0.TX0_b.IC = TRUE; desc->TX_0.TX0_b.OWN = ETH_DESC_OWN_BY_SELF; + buf->bufAddr = GLB_ConvertToMappingFromAddr(buf->bufAddr); + buf->nextDescAddr = GLB_ConvertToMappingFromAddr(buf->nextDescAddr); buf = (ETH_TX_DESC *)buf->nextDescAddr; } while (buf != ring); @@ -553,6 +589,16 @@ void ETH_ReleaseTxDesc(ETH_TX_DESC *desc) { inner->TX_0.TX0_b.OWN = ETH_DESC_OWN_BY_HW; } +void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr) { + if (desc) { + desc->bufAddr = GLB_ConvertToMappingFromAddr(bufAddr);; + } +} + +uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc) { + return (desc ? GLB_ConvertToMappingToAddr(desc->bufAddr) : 0); +} + BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring) { ETH_RX_DESC *buf = ring; @@ -564,12 +610,17 @@ BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring) { return FALSE; } + /* If code mapping */ + ring = (ETH_RX_DESC *)GLB_ConvertToMappingFromAddr((uint32_t)ring); + buf = ring; do { INNER_ETH_RX_DESC *desc = (INNER_ETH_RX_DESC *)buf; desc->RX_1.RX1_b.RCH = TRUE; desc->RX_1.RX1_b.DIC = FALSE; desc->RX_0.RX0_b.OWN = ETH_DESC_OWN_BY_HW; + buf->bufAddr = GLB_ConvertToMappingFromAddr(buf->bufAddr); + buf->nextDescAddr = GLB_ConvertToMappingFromAddr(buf->nextDescAddr); buf = (ETH_RX_DESC *)buf->nextDescAddr; } while (buf != ring); @@ -627,3 +678,15 @@ void ETH_ReleaseRxDesc(ETH_RX_DESC *desc) { } +void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr) { + if (desc) { + desc->bufAddr = GLB_ConvertToMappingFromAddr(bufAddr);; + } +} + +uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc) { + return (desc ? GLB_ConvertToMappingToAddr(desc->bufAddr) : 0); +} + + + From a58078d18aa12446464e7b832bcc4c5d9e5cd34f Mon Sep 17 00:00:00 2001 From: toasun Date: Tue, 12 May 2015 15:44:57 +0800 Subject: [PATCH 09/18] --- bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h | 15959 ++++++++-------- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h | 11 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h | 799 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h | 10 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h | 11 + .../StdPeriph_Driver/inc/cmem7_includes.h | 10 + bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h | 512 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h | 178 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h | 213 +- 9 files changed, 8945 insertions(+), 8758 deletions(-) diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h index d3baf45d2f..0f2d0cf3c0 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h @@ -1,7945 +1,8014 @@ - -/****************************************************************************************************//** - * @file CMEM7.h - * - * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for - * CMEM7 from . - * - * @version V1.0 - * @date 5. June 2014 - * - * @note Generated with SVDConv V2.75 - * from CMSIS SVD File 'SVDConv_CME_M7.svd' Version 1.0, - *******************************************************************************************************/ - - - -/** @addtogroup (null) - * @{ - */ - -/** @addtogroup CMEM7 - * @{ - */ - -#ifndef CMEM7_H -#define CMEM7_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- CMEM7 Specific Interrupt Numbers ---------------------- */ - ETH_INT_IRQn = 0, /*!< 0 ETH_INT */ - USB_INT_IRQn = 1, /*!< 1 USB_INT */ - DMA_INT_IRQn = 2, /*!< 2 DMA_INT */ - CAN0_INT_IRQn = 3, /*!< 3 CAN0_INT */ - CAN1_INT_IRQn = 4, /*!< 4 CAN1_INT */ - FP0_INT_IRQn = 5, /*!< 5 FP0_INT */ - FP1_INT_IRQn = 6, /*!< 6 FP1_INT */ - FP2_INT_IRQn = 7, /*!< 7 FP2_INT */ - FP3_INT_IRQn = 8, /*!< 8 FP3_INT */ - FP4_INT_IRQn = 9, /*!< 9 FP4_INT */ - FP5_INT_IRQn = 10, /*!< 10 FP5_INT */ - FP6_INT_IRQn = 11, /*!< 11 FP6_INT */ - FP7_INT_IRQn = 12, /*!< 12 FP7_INT */ - FP8_INT_IRQn = 13, /*!< 13 FP8_INT */ - FP9_INT_IRQn = 14, /*!< 14 FP9_INT */ - FP10_INT_IRQn = 15, /*!< 15 FP10_INT */ - FP11_INT_IRQn = 16, /*!< 16 FP11_INT */ - FP12_INT_IRQn = 17, /*!< 17 FP12_INT */ - FP13_INT_IRQn = 18, /*!< 18 FP13_INT */ - FP14_INT_IRQn = 19, /*!< 19 FP14_INT */ - FP15_INT_IRQn = 20, /*!< 20 FP15_INT */ - UART0_INT_IRQn = 21, /*!< 21 UART0_INT */ - UART1_INT_IRQn = 22, /*!< 22 UART1_INT */ - ADC_INT_IRQn = 23, /*!< 23 ADC_INT */ - GPIO_INT_IRQn = 24, /*!< 24 GPIO_INT */ - SPI1_INT_IRQn = 25, /*!< 25 SPI1_INT */ - I2C1_INT_IRQn = 26, /*!< 26 I2C1_INT */ - SPI0_INT_IRQn = 27, /*!< 27 SPI0_INT */ - I2C0_INT_IRQn = 28, /*!< 28 I2C0_INT */ - RTC_1S_INT_IRQn = 29, /*!< 29 RTC_1S_INT */ - RTC_1MS_INT_IRQn = 30, /*!< 30 RTC_1MS_INT */ - WDG_INT_IRQn = 31, /*!< 31 WDG_INT */ - TIMER_INT_IRQn = 32, /*!< 32 TIMER_INT */ - DDRC_SW_PROC_IRQn = 33, /*!< 33 DDRC_SW_PROC */ - ETH_PMT_INT_IRQn = 34, /*!< 34 ETH_PMT_INT */ - PAD_INT_IRQn = 35, /*!< 35 PAD_INT */ - DDRC_LANE_SYNC_IRQn = 36, /*!< 36 DDRC_LANE_SYNC */ - UART2_INT_IRQn = 37 /*!< 37 UART2_INT */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */ -#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 0 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include /*!< Cortex-M3 processor and core peripherals */ -#include "system_cmem7.h" /*!< CMEM7 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - - -/* ================================================================================ */ -/* ================ UART0 ================ */ -/* ================================================================================ */ - - -/** - * @brief asynchronous serial controller 0 (UART0) - */ - -typedef struct { /*!< UART0 Structure */ - __IO uint16_t BAUDRATE; /*!< baudrate Register */ - __I uint16_t RESERVED0; - __IO uint16_t TX_BUF; /*!< transmit buffer Register */ - __I uint16_t RESERVED1; - __I uint16_t RX_BUF; /*!< receive buffer Register */ - __I uint16_t RESERVED2; - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t MODE : 3; /*!< asc mode control */ - __IO uint32_t STOP : 2; /*!< number of stop bits selection */ - __IO uint32_t PARITY : 1; /*!< parity selection */ - __IO uint32_t LOOPBACK : 1; /*!< loopback mode enable bit */ - uint32_t : 1; - __IO uint32_t RX_EN : 1; /*!< receive enable bit */ - uint32_t : 1; - __IO uint32_t FIFO_EN : 1; /*!< FIFO enable bit */ - __IO uint32_t CTS : 1; /*!< Clear to send, enable signal to send */ - __IO uint32_t BAUD_MODE : 1; /*!< baudrate generation mode */ - __IO uint32_t RX_THRESHOLD: 5; /*!< receive threshold */ - __IO uint32_t RX_HALF_FULL: 5; /*!< receive fifi half full level */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< interrupt mask register */ - - struct { - __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ - __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ - __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ - __IO uint32_t PE : 1; /*!< parity error interrupt */ - __IO uint32_t FE : 1; /*!< frame error interrupt */ - __IO uint32_t OE : 1; /*!< overrun error interrupt */ - __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ - } INT_MASK_b; /*!< BitSize */ - }; - - union { - __IO uint32_t STATUS; /*!< status register */ - - struct { - __IO uint32_t RNE : 1; /*!< receiver FIFO not empty */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty */ - __IO uint32_t TOE : 1; /*!< time out when the receiver FIFO is empty */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full */ - __IO uint32_t TF : 1; /*!< transmitter FIFO is full */ - } STATUS_b; /*!< BitSize */ - }; - __IO uint8_t TIMEOUT; /*!< timeout Register */ - __I uint8_t RESERVED3[3]; - - union { - __IO uint32_t TX_RESET; /*!< transmit reset Register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } TX_RESET_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RX_RESET; /*!< receive reset Register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } RX_RESET_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RUN; /*!< uart enable register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } RUN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< raw interrupt before mask register */ - - struct { - __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ - __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ - __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ - __IO uint32_t PE : 1; /*!< parity error interrupt */ - __IO uint32_t FE : 1; /*!< frame error interrupt */ - __IO uint32_t OE : 1; /*!< overrun error interrupt */ - __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ - } INT_RAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_SEEN; /*!< interrupt after mask register */ - - struct { - __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ - __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ - __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ - __IO uint32_t PE : 1; /*!< parity error interrupt */ - __IO uint32_t FE : 1; /*!< frame error interrupt */ - __IO uint32_t OE : 1; /*!< overrun error interrupt */ - __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ - } INT_SEEN_b; /*!< BitSize */ - }; -} UART0_Type; - - -/* ================================================================================ */ -/* ================ WDG ================ */ -/* ================================================================================ */ - - -/** - * @brief watchdog (WDG) - */ - -typedef struct { /*!< WDG Structure */ - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t EN : 1; /*!< flag indicates if watchdog is enabled or not */ - __IO uint32_t INT_LEN : 1; /*!< watchdog report interrupt when COUNTER is 1/4 or 1/2 of LENGTH */ - } CTRL_b; /*!< BitSize */ - }; - __IO uint32_t LEN; /*!< Ticks decrease down to 25% or 50% to trigger an interrupt */ - - union { - __IO uint32_t INT_CTRL; /*!< interrupt control */ - - struct { - __IO uint32_t MASK : 1; /*!< mask register */ - __IO uint32_t TRIGGER_MODE: 1; /*!< trigger mode */ - } INT_CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STA; /*!< interrupt status register */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_STA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw register */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_RAW_b; /*!< BitSize */ - }; - __I uint32_t CNT; /*!< counter register */ -} WDG_Type; - - -/* ================================================================================ */ -/* ================ TIMER0 ================ */ -/* ================================================================================ */ - - -/** - * @brief timer 0 (TIMER0) - */ - -typedef struct { /*!< TIMER0 Structure */ - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t EN : 1; /*!< flag indicates if timer is enabled or not */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TYPE; /*!< type Register */ - - struct { - __IO uint32_t SIGNLE_SHOT: 1; /*!< indicate timer generate only one interrupt if not reload */ - } TYPE_b; /*!< BitSize */ - }; - __IO uint32_t LEN; /*!< length */ - - union { - __IO uint32_t INT_EN; /*!< interrupt enable */ - - struct { - __IO uint32_t EN_REVERSE : 1; /*!< flag indicates if timer is disable or not */ - } INT_EN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STA; /*!< interrupt status */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_STA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw register */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_RAW_b; /*!< BitSize */ - }; - __I uint32_t CNT; /*!< counter register */ -} TIMER0_Type; - - -/* ================================================================================ */ -/* ================ SPI0 ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI 0 (SPI0) - */ - -typedef struct { /*!< SPI0 Structure */ - - union { - __I uint32_t STATUS; /*!< status Register */ - - struct { - __I uint32_t RFIFO_EMPTY: 1; /*!< receive fifo is empty */ - __I uint32_t RFIFO_FULL : 1; /*!< receive fifo is full */ - __I uint32_t RFIFO_ALMOST_EMPTY: 1; /*!< receive fifo is almost empty */ - __I uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full */ - __I uint32_t TFIFO_EMPTY: 1; /*!< transmit fifo is empty */ - __I uint32_t TFIFO_FULL : 1; /*!< transmit fifo is full */ - __I uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo is almost empty */ - __I uint32_t TFIFO_ALMOST_FULL: 1; /*!< transmit fifo almost full */ - __I uint32_t BUSY : 1; /*!< indecates if SPI is idle or busy */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t EN : 1; /*!< indicates if SPI is enabled or not */ - __IO uint32_t RX_EN : 1; /*!< indicates if SPI receiver is enabled or not */ - __IO uint32_t CLK_HIGH : 1; /*!< indicats if idle clock polarity is high level */ - __IO uint32_t NEG_EDGE : 1; /*!< 1, indicates SPI takes sample at the rise edge and transmit - data at the trailing edge. 0, conversely. */ - __IO uint32_t TX_BIT_SEQUENCE: 1; /*!< transmit bit sequence. 0 : MSB is sent first */ - __IO uint32_t RX_BIT_SEQUENCE: 1; /*!< receive bit sequence. 0: MSB is received first */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< interrupt mask Register */ - - struct { - __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ - __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ - __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ - __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ - __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ - __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ - __IO uint32_t DONE : 1; /*!< transmit done interrupt */ - } INT_MASK_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STATUS; /*!< interrupt Register */ - - struct { - __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ - __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ - __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ - __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ - __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ - __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ - __IO uint32_t DONE : 1; /*!< transmit done interrupt */ - } INT_STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw Register */ - - struct { - __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ - __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ - __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ - __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ - __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ - __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ - __IO uint32_t DONE : 1; /*!< transmit done interrupt */ - } INT_RAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t BCNT; /*!< bit length while transmitting and receiving */ - - struct { - __IO uint32_t CNT : 5; /*!< bit length while transmitting and receiving, BCNT + 1 */ - } BCNT_b; /*!< BitSize */ - }; - __IO uint8_t GAP; /*!< half cycle number between continuous data frame */ - __I uint8_t RESERVED0[3]; - __IO uint16_t DIV; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ - __I uint16_t RESERVED1; - __IO uint32_t TRANS_CNT; /*!< transmit data length, data number = TRANS_CNT + 1 */ - - union { - __O uint32_t TRANS_START; /*!< transmit startup register, write 1 to trigger transmision once */ - - struct { - __O uint32_t TX_TRIGGER : 1; /*!< write 1 to trigger transmision once */ - } TRANS_START_b; /*!< BitSize */ - }; - __IO uint32_t RW_DATA; /*!< raw data register */ -} SPI0_Type; - - -/* ================================================================================ */ -/* ================ I2C0 ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C 0 (I2C0) - */ - -typedef struct { /*!< I2C0 Structure */ - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t MODE : 1; /*!< master or slave mode */ - __IO uint32_t MASTER_ADDR_WIDTH: 1; /*!< 7- or 10-bits address as a master */ - __IO uint32_t SLAVE_ADDR_WIDTH: 1; /*!< 7- or 10-bits address width as a slave */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint16_t TAR; /*!< target address Register */ - - struct { - __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ - __IO uint16_t START_BYTE : 1; /*!< Enable start Byte for each transfer */ - } TAR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED0; - - union { - __IO uint16_t SAR; /*!< slave address Register */ - - struct { - __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ - } SAR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED1; - - union { - __IO uint32_t DATA_CMD; /*!< I2C transfer data/command entry */ - - struct { - __IO uint32_t DATA : 8; /*!< 8-bits data */ - __O uint32_t RD_CMD : 1; /*!< read command for master mode only, write 0 if slave mode */ - __O uint32_t WR_CMD : 1; /*!< write command for master mode only */ - __O uint32_t WR_RD_CMD : 1; /*!< write and read command for master mode only */ - } DATA_CMD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WRITE_READ_CNT; /*!< I2C write and read data byte counter Register */ - - struct { - __IO uint32_t RD_BYTE_CNT: 9; /*!< Decide the number of bytes read back as a master-receiver */ - uint32_t : 7; - __IO uint32_t WR_BYTE_CNT: 9; /*!< Decide the number of byte to send as a master-transmitter */ - } WRITE_READ_CNT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SCL_CNT; /*!< I2C clk pulse counter */ - - struct { - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< the SCL clock high-period count */ - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< the SCL clock low-period count */ - } SCL_CNT_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2; - - union { - __I uint32_t INT_STATUS; /*!< I2C interrupt sources */ - - struct { - __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ - __I uint32_t RX_OVER : 1; /*!< receiver overflow */ - __I uint32_t RX_FULL : 1; /*!< receiver is full */ - __I uint32_t TX_OVER : 1; /*!< transmit overflow */ - __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ - __I uint32_t RD_REQ : 1; /*!< read request */ - __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ - __I uint32_t RX_DONE : 1; /*!< receive done */ - __I uint32_t TX_DONE : 1; /*!< transmit done */ - __I uint32_t WR_REQ : 1; /*!< write request */ - } INT_STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< I2C interrupt mask register */ - - struct { - __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ - __I uint32_t RX_OVER : 1; /*!< receiver overflow */ - __I uint32_t RX_FULL : 1; /*!< receiver is full */ - __I uint32_t TX_OVER : 1; /*!< transmit overflow */ - __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ - __I uint32_t RD_REQ : 1; /*!< read request */ - __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ - __I uint32_t RX_DONE : 1; /*!< receive done */ - __I uint32_t TX_DONE : 1; /*!< transmit done */ - __I uint32_t WR_REQ : 1; /*!< write request */ - } INT_MASK_b; /*!< BitSize */ - }; - __I uint32_t RESERVED3; - - union { - __IO uint32_t RX_TL; /*!< I2C receive FIFO threshold */ - - struct { - __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ - } RX_TL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TX_TL; /*!< I2C transmit FIFO threshold */ - - struct { - __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ - } TX_TL_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_ALL_INT; /*!< I2C clear all interrupt register */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear all individual interrupts */ - } CLR_ALL_INT_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RX_UNDER; /*!< I2C clear RX_UNDER interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_UNDER interrupt (bit 19) - of the I2C_STATUS register */ - } CLR_RX_UNDER_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RX_OVER; /*!< I2C clear RX_OVER interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_OVER interrupt (bit 20) of - the I2C_STATUS register */ - } CLR_RX_OVER_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_TX_OVER; /*!< I2C clear TX_OVER interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_OVER interrupt (bit 22) of - the I2C_STATUS register */ - } CLR_TX_OVER_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RD_REQ; /*!< I2C clear RD_REQ interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RD_REQ interrupt (bit 24) of - the I2C_STATUS register */ - } CLR_RD_REQ_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_TX_ABRT; /*!< I2C clear TX_ABRT interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_ABRT interrupts (bit 25 , - bit 18, bit 17, bit 16 and bit 15) of the I2C_STATUS register. */ - } CLR_TX_ABRT_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RX_DONE; /*!< I2C clear RX_DONE interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_DONE interrupt (bit 26) of - the I2C_STATUS register */ - } CLR_RX_DONE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ENABLE; /*!< I2C enable register */ - - struct { - __IO uint32_t EN : 1; /*!< enable device */ - uint32_t : 30; - __IO uint32_t RESET : 1; /*!< TX and RX FIFO are held in an erased state( flushed) and all - interrupts deserted */ - } ENABLE_b; /*!< BitSize */ - }; - - union { - __I uint32_t STATUS; /*!< I2C status register */ - - struct { - __I uint32_t BUSY : 1; /*!< I2C busy Status */ - __I uint32_t TX_FIFO_NOT_FULL: 1; /*!< transmit FIFO is not full */ - __I uint32_t TX_FIFO_EMPTY: 1; /*!< transmit FIFO is empty */ - __I uint32_t RX_FIFO_NOT_EMPTY: 1; /*!< receive FIFO is not empty */ - __I uint32_t RX_FIFO_FULL: 1; /*!< receive FIFO is full */ - __I uint32_t EN : 1; /*!< I2C is enabled */ - __I uint32_t TX_BYTE_W_ACK: 9; /*!< Number of bytes sent to slave with acknowledge during the last - write transaction as a master-transmitter only */ - __I uint32_t ABRT_ADDR_NOACK: 1; /*!< the address sent was not acknowledged by any slave as a master */ - __I uint32_t ABRT_TX_DATA_NOACK: 1; /*!< the data sent was not acknowledged by any slave as a master */ - __I uint32_t ABRT_SLAVE_FLUSH_TX_FIFO: 1; /*!< Slave has received a read command and some data exists in the - TX FIFO so the slave issues a TX_ABRT interrupt to flush old - data in TX FIFO */ - __I uint32_t ABRT_SLAVE_RD_IN_TX: 1; /*!< When the processor side responds to a slave mode request for - data to be transmitted to a remote master and user writes a - 1 in CMD (bit 8) of I2C_DATA_CMD register */ - __I uint32_t RX_UNDER : 1; /*!< receiver is underflow */ - __I uint32_t RX_OVER : 1; /*!< receiver is overflow */ - __I uint32_t RX_FULL : 1; /*!< receiver is full */ - __I uint32_t TX_OVER : 1; /*!< transmit is overflow */ - __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ - __I uint32_t RD_REQ : 1; /*!< read request is received */ - __I uint32_t TX_ABRT : 1; /*!< transmit is abort */ - __I uint32_t RX_DONE : 1; /*!< receive is done */ - __I uint32_t TX_DONE : 1; /*!< transmit is done */ - __I uint32_t WR_REQ : 1; /*!< write request is received */ - __I uint32_t MST_RD_FLAG: 1; /*!< Master is executing read command */ - __I uint32_t MST_WR_FLAG: 1; /*!< Master is executing read command */ - __I uint32_t MST_WR_RD_FLAG: 1; /*!< Master is executing write-read command */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __I uint32_t TX_FIFO_LEVEL; /*!< I2C transmit FIFO level */ - - struct { - __I uint32_t LEVEL : 5; /*!< FIFO level */ - } TX_FIFO_LEVEL_b; /*!< BitSize */ - }; - - union { - __I uint32_t RX_FIFO_LEVEL; /*!< I2C receive FIFO level */ - - struct { - __I uint32_t LEVEL : 5; /*!< FIFO level */ - } RX_FIFO_LEVEL_b; /*!< BitSize */ - }; - __I uint32_t RESERVED4; - - union { - __O uint32_t SLAVE_NACK; /*!< I2C slave send a data NACK */ - - struct { - __O uint32_t NACK : 1; /*!< data NACK */ - } SLAVE_NACK_b; /*!< BitSize */ - }; - __I uint32_t RESERVED5; - - union { - __IO uint32_t SDA_SETUP; /*!< I2C SDA setup timer */ - - struct { - __IO uint32_t TSETUP : 10; /*!< This counter defines the max value of the following constrains:THD:STA - TSU:STO,TSETUP: T / INPUT_CLK_PERIOD */ - __IO uint32_t TSU_DAT : 8; /*!< This counter defines the constrain of TSU:DAT: 250ns (or 100ns) - / INPUT_CLK_PERIOD */ - } SDA_SETUP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TSU_STA_SETUP; /*!< I2C Tsu_sta and Tbuf_free timer */ - - struct { - __IO uint32_t TBUF : 10; /*!< This counter defines the constrain of bus free interval: Tbuf, - Tbuf : Tbus_free / INPUT_CLK_PERIOD */ - __IO uint32_t TSU_STA : 10; /*!< This counter defines the constrain of Tsu:sta, Tsu:sta : Tsu:sta - / INPUT_CLK_PERIOD */ - __IO uint32_t SDA_FILTER_CNT: 4; /*!< SDA filter count */ - __IO uint32_t SDA_FILTER_EN: 1; /*!< SDA filter enable bit */ - __IO uint32_t SCL_FILTER_CNT: 4; /*!< SCL filter count */ - __IO uint32_t SCL_FILTER_EN: 1; /*!< SCL filter enable bit */ - } TSU_STA_SETUP_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_TX_DONE; /*!< I2C clear TX_DONE interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_DONE interrupt (bit 27) of - the I2C_STATUS register */ - } CLR_TX_DONE_b; /*!< BitSize */ - }; -} I2C0_Type; - - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - - -/** - * @brief RTC (RTC) - */ - -typedef struct { /*!< RTC Structure */ - - union { - __IO uint32_t INT_STATUS; /*!< interrupt Register */ - - struct { - __IO uint32_t SECOND : 1; /*!< 1s interrupt, write 1 clear 0 */ - __IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt, write 1 clear 0 */ - } INT_STATUS_b; /*!< BitSize */ - }; - __IO uint32_t SECOND; /*!< current seconds of system time */ - - union { - __IO uint16_t MICROSECOND; /*!< current micro seconds of system time */ - - struct { - __IO uint16_t MS : 10; /*!< micro seconds */ - } MICROSECOND_b; /*!< BitSize */ - }; -} RTC_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - __I uint32_t GPIO_IN; /*!< GPIO input data */ - __IO uint32_t GPIO_OUT_UNMASK; /*!< GPIO output mask Register */ - __IO uint32_t GPIO_OUT_DATA; /*!< GPIO output data register */ - __IO uint32_t GPIO_OE; /*!< GPIO output driver enable */ - __IO uint32_t GPIO_INT_MASK; /*!< GPIO input interrupt mask */ - __IO uint32_t GPIO_INT_STATUS; /*!< GPIO input interrupt status */ - __IO uint32_t GPIO_INT_RAW; /*!< GPIO input interrupt raw */ - __IO uint32_t GPIO_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ - - union { - __IO uint32_t PWM_OUT_SEL; /*!< Select gpio output from PWM */ - - struct { - __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ - __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ - __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ - __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ - } PWM_OUT_SEL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT0_LEN; /*!< Pwm channel 0 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT0_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT1_LEN; /*!< Pwm channel 1 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT1_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT2_LEN; /*!< Pwm channel 2 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT2_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT3_LEN; /*!< Pwm channel 3 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT3_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT_EN; /*!< Pwm enable */ - - struct { - __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ - __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ - __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ - __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ - } PWM_OUT_EN_b; /*!< BitSize */ - }; - __I uint32_t GPIO_H_IN; /*!< GPIO_H input data */ - __IO uint32_t GPIO_H_OUT_UNMASK; /*!< GPIO_H output unmask Register */ - __IO uint32_t GPIO_H_OUT_DATA; /*!< GPIO_H output data register */ - __IO uint32_t GPIO_H_OE; /*!< GPIO_H output driver enable */ - __IO uint32_t GPIO_H_INT_MASK; /*!< GPIO_H interrupt mask */ - __IO uint32_t GPIO_H_INT_STATUS; /*!< GPIO_H interrupt status */ - __IO uint32_t GPIO_H_INT_RAW; /*!< GPIO_H interrupt raw */ - __IO uint32_t GPIO_H_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ - __I uint32_t GPIO_N_IN; /*!< GPIO_N input data */ - __IO uint32_t GPIO_N_OUT_UNMASK; /*!< GPIO_N output unmask Register */ - __IO uint32_t GPIO_N_OUT_DATA; /*!< GPIO_N output data register */ - __IO uint32_t GPIO_N_OE; /*!< GPIO_N output driver enable */ - __IO uint32_t GPIO_N_INT_MASK; /*!< GPIO_N interrupt mask */ - __IO uint32_t GPIO_N_INT_STATUS; /*!< GPIO_N interrupt status */ - __IO uint32_t GPIO_N_INT_RAW; /*!< GPIO_N interrupt raw */ - __IO uint32_t GPIO_N_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ -} GPIO_Type; - - -/* ================================================================================ */ -/* ================ NOR_FLASH ================ */ -/* ================================================================================ */ - - -/** - * @brief NOR_FLASH (NOR_FLASH) - */ - -typedef struct { /*!< NOR_FLASH Structure */ - - union { - __IO uint32_t CTRL0; /*!< control Register 0 */ - - struct { - __IO uint32_t DIV : 8; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ - __IO uint32_t CS_REVALID_INTERVAL: 8; /*!< interval from CS invalid to valid, number of half cycle of SCK */ - __IO uint32_t RW_BYTE_CNT: 16; /*!< RW byte count (eliminate CMD, ADDRESS, DUMMY in normal state, - contains all in transparent state. 0 is unlimited */ - } CTRL0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTRL1; /*!< control Register 1 */ - - struct { - __IO uint32_t CMD : 8; /*!< operated command */ - __IO uint32_t ADDRESS : 24; /*!< RW address */ - } CTRL1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TRIGGER; /*!< trigger register */ - - struct { - __O uint32_t OP_START : 1; /*!< operation start. */ - __IO uint32_t OP_CLEAN : 1; /*!< operation clean, stop current opration and clean FIFO */ - __IO uint32_t TRSP_RD_EN : 1; /*!< if a read operation after transparent operation */ - __IO uint32_t TRSP_EN : 1; /*!< enable transparent operation */ - } TRIGGER_b; /*!< BitSize */ - }; - - union { - __I uint32_t STATUS; /*!< status register */ - - struct { - __I uint32_t BUSY : 1; /*!< reading or writting */ - __I uint32_t RD_FIFO_ALMOST_FULL: 1; /*!< read FIFO is almost full */ - __I uint32_t RD_FIFO_EMPTY: 1; /*!< read FIFO is empty */ - __I uint32_t RD_FIFO_FULL: 1; /*!< read FIFO is full */ - __I uint32_t WR_FIFO_ALMOST_EMPTY: 1; /*!< write FIFO is almost empty */ - __I uint32_t WR_FIFO_FULL: 1; /*!< write FIFO is full */ - __I uint32_t WR_FIFO_EMPTY: 1; /*!< write FIFO is empty */ - } STATUS_b; /*!< BitSize */ - }; - __IO uint32_t DATA; /*!< data register. lower bits are significant in read and higher - bits are significant in writting */ - - union { - __IO uint32_t BYPASS; /*!< bypass Register, is used for JTAG connecting FLASH directly */ - - struct { - __IO uint32_t EN : 1; /*!< enable bypass */ - } BYPASS_b; /*!< BitSize */ - }; -} NOR_FLASH_Type; - - -/* ================================================================================ */ -/* ================ ADC ================ */ -/* ================================================================================ */ - - -/** - * @brief ADC (ADC) - */ - -typedef struct { /*!< ADC Structure */ - - union { - __IO uint32_t POWERDOWN_RESET; /*!< power down and reset Register */ - - struct { - __IO uint32_t RESET_ADC2 : 1; /*!< ADC2, reset, active high */ - __IO uint32_t RESET_ADC1 : 1; /*!< ADC1, reset, active high */ - __IO uint32_t POWERDOWN_ADC2: 1; /*!< ADC2, power down, active high */ - __IO uint32_t POWERDOWN_ADC1: 1; /*!< ADC1, power down, active high */ - } POWERDOWN_RESET_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG0; /*!< config Register */ - - struct { - __IO uint32_t VSEN : 3; /*!< ADC-1 VSEN Selection */ - __IO uint32_t PHASE_CTRL : 2; /*!< ADC-1 and ADC-2 CLK Phase Control */ - } CFG0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_ADC1; /*!< config ADC1 register */ - - struct { - __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ - __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ - __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ - __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ - } CFG_ADC1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_ADC2; /*!< config ADC1 register */ - - struct { - __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ - __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ - __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ - __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ - } CFG_ADC2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ADC1_FIFO_CLEAR; /*!< clear adc1 fifo data */ - - struct { - __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ - } ADC1_FIFO_CLEAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ADC2_FIFO_CLEAR; /*!< clear adc2 fifo data */ - - struct { - __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ - } ADC2_FIFO_CLEAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ALL_ADC_FIFO_CLEAR; /*!< clear adc1 and adc2 fifo data */ - - struct { - __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ - } ALL_ADC_FIFO_CLEAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< interrupt mask register */ - - struct { - __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ - __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ - __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ - __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ - __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ - __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ - } INT_MASK_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw register */ - - struct { - __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ - __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ - __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ - __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ - __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ - __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ - } INT_RAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STATUS; /*!< interrupt status register */ - - struct { - __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ - __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ - __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ - __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ - __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ - __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ - } INT_STATUS_b; /*!< BitSize */ - }; - __I uint32_t ADC1_OUT; /*!< ADC-1 Output data (Signed-Magnitude Format) */ - __I uint32_t ADC2_OUT; /*!< ADC-2 Output data (Signed-Magnitude Format) */ - __I uint32_t ADC1_OUT_OFFSET_CALIBRATION; /*!< ADC-1 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ - __I uint32_t ADC2_OUT_OFFSET_CALIBRATION; /*!< ADC-2 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ - __I uint32_t ADC1_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-1 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ - __I uint32_t ADC2_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-2 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ - __I uint32_t ADC1_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-1 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ - __I uint32_t ADC2_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-2 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ - - union { - __I uint32_t EOC; /*!< Conversion End Indicator */ - - struct { - __I uint32_t ADC2_EOC_GAIN: 1; /*!< ADC2 EOC_GAIN signal, conversion is done */ - __I uint32_t ADC2_EOC_OFF: 1; /*!< ADC2 EOC_OFF signal, conversion is done */ - __I uint32_t ADC2_EOC : 1; /*!< ADC2 EOC signal, conversion is done */ - __I uint32_t ADC1_EOC_GAIN: 1; /*!< ADC1 EOC_GAIN signal, conversion is done */ - __I uint32_t ADC1_EOC_OFF: 1; /*!< ADC1 EOC_OFF signal, conversion is done */ - __I uint32_t ADC1_EOC : 1; /*!< ADC1 EOC signal, conversion is done */ - } EOC_b; /*!< BitSize */ - }; - - union { - __I uint32_t BUSY; /*!< ADC is busy */ - - struct { - __I uint32_t ADC1_BUSY : 1; /*!< ADC1 is busy */ - __I uint32_t ADC2_BUSY : 1; /*!< ADC2 is busy */ - } BUSY_b; /*!< BitSize */ - }; - - union { - __O uint32_t ADC1_START; /*!< ADC1 startup enable */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC1_START_b; /*!< BitSize */ - }; - - union { - __O uint32_t ADC1_STOP; /*!< ADC1 stop enable */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC1_STOP_b; /*!< BitSize */ - }; - - union { - __O uint16_t ADC1_FIFO_READ; /*!< ADC1 FIFO read data */ - - struct { - __O uint16_t DATA : 12; /*!< data */ - __O uint16_t CHANNEL : 4; /*!< channel number */ - } ADC1_FIFO_READ_b; /*!< BitSize */ - }; - __I uint16_t RESERVED0; - - union { - __O uint32_t ADC2_START; /*!< ADC2 startup enable, only for single-conversion */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC2_START_b; /*!< BitSize */ - }; - - union { - __O uint32_t ADC2_STOP; /*!< ADC1 stop enable, only for single-conversion */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC2_STOP_b; /*!< BitSize */ - }; - - union { - __O uint16_t ADC2_FIFO_READ; /*!< ADC2 FIFO read data */ - - struct { - __O uint16_t DATA : 12; /*!< data */ - __O uint16_t CHANNEL : 4; /*!< channel number */ - } ADC2_FIFO_READ_b; /*!< BitSize */ - }; - __I uint16_t RESERVED1; - - union { - __O uint32_t ALL_ADC_START; /*!< all ADCs start */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ALL_ADC_START_b; /*!< BitSize */ - }; - - union { - __O uint32_t ALL_ADC_STOP; /*!< all ADCs stop */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ALL_ADC_STOP_b; /*!< BitSize */ - }; - - union { - __I uint32_t ALL_ADC_FIFO_READ; /*!< all ADCs FIFO read data */ - - struct { - __I uint32_t ADC1_DATA : 12; /*!< ADC1 data */ - __I uint32_t ADC1_CHANNEL: 4; /*!< ADC1 channel number */ - __I uint32_t ADC2_DATA : 12; /*!< ADC2 data */ - __I uint32_t ADC2_CHANNEL: 4; /*!< ADC2 channel number */ - } ALL_ADC_FIFO_READ_b; /*!< BitSize */ - }; - - union { - __I uint32_t STATUS; /*!< status register */ - - struct { - __I uint32_t ADC1_READ_EMPTY: 1; /*!< ADC1 read empty */ - __I uint32_t ADC2_READ_EMPTY: 1; /*!< ADC2 read empty */ - __I uint32_t ADC1_READ_ALMOST_EMPTY: 1; /*!< ADC1 read almost empty */ - __I uint32_t ADC2_READ_ALMOST_EMPTY: 1; /*!< ADC2 read almost empty */ - __I uint32_t ADC1_WRITE_FULL: 1; /*!< ADC1 write full */ - __I uint32_t ADC2_WRITE_FULL: 1; /*!< ADC2 write full */ - __I uint32_t ADC1_WRITE_ALMOST_FULL: 1; /*!< ADC1 write almost full */ - __I uint32_t ADC2_WRITE_ALMOST_FULL: 1; /*!< ADC2 write almost full */ - } STATUS_b; /*!< BitSize */ - }; -} ADC_Type; - - -/* ================================================================================ */ -/* ================ EFUSE ================ */ -/* ================================================================================ */ - - -/** - * @brief EFUSE (EFUSE) - */ - -typedef struct { /*!< EFUSE Structure */ - - union { - __IO uint32_t USER_CTRL_LOW; /*!< low user region control */ - - struct { - __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ - __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ - __I uint32_t BUSY : 1; /*!< reading or writting */ - __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ - __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ - __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ - __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ - __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ - } USER_CTRL_LOW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TIMING_0; /*!< timing 0 */ - - struct { - __IO uint32_t TPRS : 7; /*!< TPRS */ - __IO uint32_t TESR : 2; /*!< TESR */ - __IO uint32_t TRC : 4; /*!< TRC */ - __IO uint32_t TRPW : 3; /*!< TRPW */ - __IO uint32_t TRAH : 2; /*!< TRAH */ - __IO uint32_t TRAC : 3; /*!< TRAC */ - uint32_t : 6; - __IO uint32_t TPWPH : 5; /*!< TPWPH[6:2] */ - } TIMING_0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TIMING_1; /*!< timing 1 */ - - struct { - __IO uint32_t TPWPS : 7; /*!< TPWPS */ - __IO uint32_t TEPS : 4; /*!< TEPS */ - __IO uint32_t TPP : 11; /*!< TPP */ - __IO uint32_t TPIT : 8; /*!< TPIT */ - __IO uint32_t TPWPH : 2; /*!< TPWPS[1:0] */ - } TIMING_1_b; /*!< BitSize */ - }; - __IO uint32_t USER_DATA0_LOW; /*!< user data [31:0] */ - __IO uint32_t USER_DATA1_LOW; /*!< user data [63:32] */ - __IO uint32_t USER_DATA2_LOW; /*!< user data [95:64] */ - __IO uint32_t USER_DATA3_LOW; /*!< user data [127:96] */ - - union { - __IO uint32_t USER_DATA4_LOW; /*!< crc and lock bit */ - - struct { - __IO uint32_t LOCK : 1; /*!< write protection if true */ - uint32_t : 23; - __IO uint32_t CRC : 8; /*!< CRC */ - } USER_DATA4_LOW_b; /*!< BitSize */ - }; - __I uint32_t RESERVED0[3]; - - union { - __IO uint32_t USER_CTRL_HI; /*!< high user region control */ - - struct { - __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ - __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ - __I uint32_t BUSY : 1; /*!< reading or writting */ - __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ - __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ - __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ - __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ - __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ - } USER_CTRL_HI_b; /*!< BitSize */ - }; - __IO uint32_t USER_DATA0_HI; /*!< user data [159:128] */ - __IO uint32_t USER_DATA1_HI; /*!< user data [191:160] */ - __IO uint32_t USER_DATA2_HI; /*!< user data [223:192] */ - __IO uint32_t USER_DATA3_HI; /*!< user data [255:224] */ - - union { - __IO uint32_t USER_DATA4_HI; /*!< crc and lock bit */ - - struct { - __IO uint32_t LOCK : 1; /*!< write protection if true */ - uint32_t : 23; - __IO uint32_t CRC : 8; /*!< CRC */ - } USER_DATA4_HI_b; /*!< BitSize */ - }; -} EFUSE_Type; - - -/* ================================================================================ */ -/* ================ CAN0 ================ */ -/* ================================================================================ */ - - -/** - * @brief CAN 0 (CAN0) - */ - -typedef struct { /*!< CAN0 Structure */ - - union { - __IO uint8_t MODE; /*!< mode Register */ - - struct { - __IO uint8_t RM : 1; /*!< reset mode if 1 or operation mode */ - __IO uint8_t LOM : 1; /*!< Listen only mode */ - __IO uint8_t STM : 1; /*!< self test mode */ - __IO uint8_t AFM : 1; /*!< acceptance filter mode. Single filter if 1, dual filter if 0 */ - __IO uint8_t SM : 1; /*!< sleep mode */ - } MODE_b; /*!< BitSize */ - }; - __I uint8_t RESERVED0[3]; - - union { - __O uint8_t CMD; /*!< command Register */ - - struct { - __O uint8_t TR : 1; /*!< Set to 1 when a message is to be transmitted */ - __O uint8_t AT : 1; /*!< Set to 1 to cancel the next transmission request */ - __O uint8_t RRB : 1; /*!< Set to 1 to release the Receive Buffer */ - __O uint8_t CDO : 1; /*!< Set to 1 to clear the data overrun condition signaled by the - Data Overrun Status bit (SR.1). */ - __O uint8_t SSR : 1; /*!< Set to 1 when a message is to be transmitted and received simultaneously */ - } CMD_b; /*!< BitSize */ - }; - __I uint8_t RESERVED1[3]; - - union { - __I uint8_t STATUS; /*!< status Register */ - - struct { - __I uint8_t RBNE : 1; /*!< Receive Buffer not empty */ - __I uint8_t DO : 1; /*!< Data Overrun Status */ - __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ - __I uint8_t TC : 1; /*!< Transmission complete */ - __I uint8_t RXING : 1; /*!< receiving the data */ - __I uint8_t TXING : 1; /*!< transmitting the data */ - __I uint8_t ERR : 1; /*!< At least one of the error counters is more than Error Warning - Limit Register */ - __I uint8_t BUS_OFF : 1; /*!< in 'Bus Off' state */ - } STATUS_b; /*!< BitSize */ - }; - __I uint8_t RESERVED2[3]; - - union { - __I uint8_t INT; /*!< interrupt Register */ - - struct { - __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ - __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ - __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status - or Error Status bits (SR.7,SR.6) */ - __I uint8_t DO : 1; /*!< Data Overrun Status */ - __I uint8_t WAKEUP : 1; /*!< wake-up */ - __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being - in error passive state or when at least one error counter exceeds - the protocol-defined level of 127 */ - __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ - __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ - } INT_b; /*!< BitSize */ - }; - __I uint8_t RESERVED3[3]; - - union { - __IO uint8_t INT_EN; /*!< interrupt enabled Register */ - - struct { - __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ - __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ - __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status - or Error Status bits (SR.7,SR.6) */ - __I uint8_t DO : 1; /*!< Data Overrun Status */ - __I uint8_t WAKEUP : 1; /*!< wake-up */ - __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being - in error passive state or when at least one error counter exceeds - the protocol-defined level of 127 */ - __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ - __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ - } INT_EN_b; /*!< BitSize */ - }; - __I uint8_t RESERVED4[7]; - - union { - __IO uint8_t BTR0; /*!< Bus Timing 0 */ - - struct { - __IO uint8_t BRP : 6; /*!< TQ =2 x Txtal1 x (32 x BRP.5 + 16 x BRP.4 + 8 x BRP.3 + 4 x - BRP.2 + 2 x BRP.1 + BRP.0 + 1) */ - __IO uint8_t SJW : 2; /*!< the maximum number of time quanta of sync segment */ - } BTR0_b; /*!< BitSize */ - }; - __I uint8_t RESERVED5[3]; - - union { - __IO uint8_t BTR1; /*!< Bus Timing 1 */ - - struct { - __IO uint8_t TSEG1 : 4; /*!< the maximum number of time quanta of propagation and 1st phase - segment */ - __IO uint8_t TSEG2 : 3; /*!< the maximum number of time quanta of 2nd phase segment */ - __IO uint8_t SAM : 1; /*!< sample times. Sample 3 times if 1, once if 0 */ - } BTR1_b; /*!< BitSize */ - }; - __I uint8_t RESERVED6[3]; - - union { - __IO uint8_t OCR; /*!< Output Control Register */ - - struct { - __IO uint8_t MODE : 2; /*!< output control mode */ - } OCR_b; /*!< BitSize */ - }; - __I uint8_t RESERVED7[11]; - - union { - __I uint8_t ALC; /*!< Arbitration Lost Capture */ - - struct { - __I uint8_t BIT : 5; /*!< the current position of the Bit Processor when bus arbitration - lost, 1st bit (ID.28) if 0 */ - } ALC_b; /*!< BitSize */ - }; - __I uint8_t RESERVED8[3]; - - union { - __I uint8_t ECC; /*!< Error Code Capture */ - - struct { - __I uint8_t SEGMENT : 5; /*!< segment code */ - __I uint8_t DIRECTION : 1; /*!< If 1, the error occurred during reception. If 0, the error occurred - during transmission */ - __I uint8_t ERR : 2; /*!< error code */ - } ECC_b; /*!< BitSize */ - }; - __I uint8_t RESERVED9[3]; - __IO uint8_t EWLR; /*!< Error Warning Limit */ - __I uint8_t RESERVED10[3]; - __IO uint8_t RXERR; /*!< Receive Error Counter */ - __I uint8_t RESERVED11[3]; - __IO uint8_t TXERR; /*!< Transmit Error Counter */ - __I uint8_t RESERVED12[3]; - - union { - __IO uint8_t FI_OR_ACR0; /*!< Transmit Frame Information if writting or Receive Frame Information - if reading, ACR[0] if reset mode */ - - struct { - __IO uint8_t DLC : 4; /*!< byte number in the data */ - uint8_t : 2; - __IO uint8_t RTR : 1; /*!< 1 indicates a remote frame; 0 indicates a data frame */ - __IO uint8_t FF : 1; /*!< 1 selects Extended Frame Format (EFF); 0 selects Standard Frame - Format (SFF) */ - } FI_OR_ACR0_b; /*!< BitSize */ - }; - __I uint8_t RESERVED13[3]; - __IO uint8_t DI0_OR_ACR1; /*!< Transmit data Information if writting or Receive data Information - if reading, ACR[1] if reset mode */ - __I uint8_t RESERVED14[3]; - __IO uint8_t DI1_OR_ACR2; /*!< Transmit data Information if writting or Receive data Information - if reading, ACR[2] if reset mode */ - __I uint8_t RESERVED15[3]; - __IO uint8_t DI2_OR_ACR3; /*!< Transmit data Information if writting or Receive data Information - if reading, ACR[3] if reset mode */ - __I uint8_t RESERVED16[3]; - __IO uint8_t DI3_OR_AMR0; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[0] if reset mode */ - __I uint8_t RESERVED17[3]; - __IO uint8_t DI4_OR_AMR1; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[1] if reset mode */ - __I uint8_t RESERVED18[3]; - __IO uint8_t DI5_OR_AMR2; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[2] if reset mode */ - __I uint8_t RESERVED19[3]; - __IO uint8_t DI6_OR_AMR3; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[3] if reset mode */ - __I uint8_t RESERVED20[3]; - __IO uint8_t DI7; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED21[3]; - __IO uint8_t DI8; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED22[3]; - __IO uint8_t DI9; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED23[3]; - __IO uint8_t DI10; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED24[3]; - __IO uint8_t DI11; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED25[3]; - __IO uint8_t RMC; /*!< Receive Message Counter */ - __I uint8_t RESERVED26[7]; - - union { - __IO uint8_t CDR; /*!< Clock Divider Register */ - - struct { - __IO uint8_t DIVIDER : 3; /*!< divider of XTAL1 */ - __IO uint8_t OFF : 1; /*!< disable XTAL1 */ - } CDR_b; /*!< BitSize */ - }; -} CAN0_Type; - - -/* ================================================================================ */ -/* ================ DMA ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA (DMA) - */ - -typedef struct { /*!< DMA Structure */ - __IO uint32_t SAR0; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED0; - __IO uint32_t DAR0; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED1; - - union { - __IO uint32_t LLP0; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2; - - union { - __IO uint32_t CTL_LOW0; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI0; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI0_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT0; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED3; - __IO uint32_t DSTAT0; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED4; - __IO uint32_t SSTATAR0; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED5; - __IO uint32_t DSTATAR0; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED6; - - union { - __IO uint32_t CFG_LOW0; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI0; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR0; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED7; - - union { - __IO uint32_t DSR0; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED8; - __IO uint32_t SAR1; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED9; - __IO uint32_t DAR1; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED10; - - union { - __IO uint32_t LLP1; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED11; - - union { - __IO uint32_t CTL_LOW1; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI1; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI1_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT1; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED12; - __IO uint32_t DSTAT1; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED13; - __IO uint32_t SSTATAR1; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED14; - __IO uint32_t DSTATAR1; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED15; - - union { - __IO uint32_t CFG_LOW1; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI1; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR1; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED16; - - union { - __IO uint32_t DSR1; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED17; - __IO uint32_t SAR2; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED18; - __IO uint32_t DAR2; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED19; - - union { - __IO uint32_t LLP2; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED20; - - union { - __IO uint32_t CTL_LOW2; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI2; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI2_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT2; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED21; - __IO uint32_t DSTAT2; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED22; - __IO uint32_t SSTATAR2; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED23; - __IO uint32_t DSTATAR2; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED24; - - union { - __IO uint32_t CFG_LOW2; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI2; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR2; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED25; - - union { - __IO uint32_t DSR2; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED26; - __IO uint32_t SAR3; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED27; - __IO uint32_t DAR3; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED28; - - union { - __IO uint32_t LLP3; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED29; - - union { - __IO uint32_t CTL_LOW3; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI3; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI3_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT3; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED30; - __IO uint32_t DSTAT3; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED31; - __IO uint32_t SSTATAR3; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED32; - __IO uint32_t DSTATAR3; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED33; - - union { - __IO uint32_t CFG_LOW3; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI3; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR3; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED34; - - union { - __IO uint32_t DSR3; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED35; - __IO uint32_t SAR4; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED36; - __IO uint32_t DAR4; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED37; - - union { - __IO uint32_t LLP4; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED38; - - union { - __IO uint32_t CTL_LOW4; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI4; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI4_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT4; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED39; - __IO uint32_t DSTAT4; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED40; - __IO uint32_t SSTATAR4; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED41; - __IO uint32_t DSTATAR4; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED42; - - union { - __IO uint32_t CFG_LOW4; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI4; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR4; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED43; - - union { - __IO uint32_t DSR4; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED44; - __IO uint32_t SAR5; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED45; - __IO uint32_t DAR5; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED46; - - union { - __IO uint32_t LLP5; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED47; - - union { - __IO uint32_t CTL_LOW5; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI5; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI5_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT5; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED48; - __IO uint32_t DSTAT5; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED49; - __IO uint32_t SSTATAR5; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED50; - __IO uint32_t DSTATAR5; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED51; - - union { - __IO uint32_t CFG_LOW5; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI5; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR5; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED52; - - union { - __IO uint32_t DSR5; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED53; - __IO uint32_t SAR6; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED54; - __IO uint32_t DAR6; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED55; - - union { - __IO uint32_t LLP6; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED56; - - union { - __IO uint32_t CTL_LOW6; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI6; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI6_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT6; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED57; - __IO uint32_t DSTAT6; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED58; - __IO uint32_t SSTATAR6; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED59; - __IO uint32_t DSTATAR6; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED60; - - union { - __IO uint32_t CFG_LOW6; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI6; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR6; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED61; - - union { - __IO uint32_t DSR6; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED62; - __IO uint32_t SAR7; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED63; - __IO uint32_t DAR7; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED64; - - union { - __IO uint32_t LLP7; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED65; - - union { - __IO uint32_t CTL_LOW7; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI7; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI7_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT7; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED66; - __IO uint32_t DSTAT7; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED67; - __IO uint32_t SSTATAR7; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED68; - __IO uint32_t DSTATAR7; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED69; - - union { - __IO uint32_t CFG_LOW7; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI7; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR7; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED70; - - union { - __IO uint32_t DSR7; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED71[11]; - __I uint8_t INT_TFR; /*!< DMA Transfer Complete */ - __I uint8_t RESERVED72[7]; - __I uint8_t INT_BLOCK; /*!< Block Transfer Complete */ - __I uint8_t RESERVED73[7]; - __I uint8_t INT_SRC_TRAN; /*!< Source Transaction Complete */ - __I uint8_t RESERVED74[7]; - __I uint8_t INT_DST_TRAN; /*!< Destination Transaction Complete */ - __I uint8_t RESERVED75[7]; - __I uint8_t INT_ERR; /*!< Error */ - __I uint8_t RESERVED76[7]; - - union { - __IO uint16_t INT_EN_TFR; /*!< DMA Transfer Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_TFR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED77[3]; - - union { - __IO uint16_t INT_EN_BLOCK; /*!< Block Transfer Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_BLOCK_b; /*!< BitSize */ - }; - __I uint16_t RESERVED78[3]; - - union { - __IO uint16_t INT_EN_SRC_TRAN; /*!< Source Transaction Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_SRC_TRAN_b; /*!< BitSize */ - }; - __I uint16_t RESERVED79[3]; - - union { - __IO uint16_t INT_EN_DST_TRAN; /*!< Destination Transaction Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_DST_TRAN_b; /*!< BitSize */ - }; - __I uint16_t RESERVED80[3]; - - union { - __IO uint16_t INT_EN_ERR; /*!< Error */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_ERR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED81[3]; - __O uint8_t INT_CLEAR_TFR; /*!< DMA Transfer Complete */ - __I uint8_t RESERVED82[7]; - __O uint8_t INT_CLEAR_BLOCK; /*!< Block Transfer Complete */ - __I uint8_t RESERVED83[7]; - __O uint8_t INT_CLEAR_SRC_TRAN; /*!< Source Transaction Complete */ - __I uint8_t RESERVED84[7]; - __O uint8_t INT_CLEAR_DST_TRAN; /*!< Destination Transaction Complete */ - __I uint8_t RESERVED85[7]; - __O uint8_t INT_CLEAR_ERR; /*!< Error */ - __I uint8_t RESERVED86[63]; - - union { - __IO uint32_t DMA_EN; /*!< DW_ahb_dmac Configuration Register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } DMA_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED87; - - union { - __IO uint32_t CH_EN; /*!< DW_ahb_dmac Channel Enable Register */ - - struct { - __IO uint32_t EN : 8; /*!< enable */ - __IO uint32_t WE : 8; /*!< enable write enable */ - } CH_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED88[10]; - - union { - __I uint32_t DMA_COMP_PARAMS_6_HI; /*!< Component Parameters for channel 7 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_6_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_5_LOW; /*!< Component Parameters for channel 6 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_5_LOW_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_5_HI; /*!< Component Parameters for channel 5 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_5_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_4_LOW; /*!< Component Parameters for channel 4 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_4_LOW_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_4_HI; /*!< Component Parameters for channel 3 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_4_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_3_LOW; /*!< Component Parameters for channel 2 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_3_LOW_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_3_HI; /*!< Component Parameters for channel 1 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_3_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_2_LOW; /*!< Component Parameters for channel 0 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_2_LOW_b; /*!< BitSize */ - }; - __I uint32_t RESERVED89; - - union { - __I uint32_t DMA_COMP_PARAMS_1_LOW; /*!< Maximum block size for channel */ - - struct { - __I uint32_t CH0_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 0. */ - __I uint32_t CH1_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 1 */ - __I uint32_t CH2_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 2 */ - __I uint32_t CH3_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 3 */ - __I uint32_t CH4_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 4 */ - __I uint32_t CH5_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 5 */ - __I uint32_t CH6_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 6 */ - __I uint32_t CH7_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 7 */ - } DMA_COMP_PARAMS_1_LOW_b; /*!< BitSize */ - }; -} DMA_Type; - - -/* ================================================================================ */ -/* ================ ETH ================ */ -/* ================================================================================ */ - - -/** - * @brief ETH (ETH) - */ - -typedef struct { /*!< ETH Structure */ - - union { - __IO uint32_t CONFIG; /*!< MAC Configuration Register */ - - struct { - __IO uint32_t PRELEN : 2; /*!< Preamble Length for Transmit frames */ - __IO uint32_t RX_EN : 1; /*!< Receiver Enable */ - __IO uint32_t TX_EN : 1; /*!< Transmitter Enable */ - __IO uint32_t DC_EN : 1; /*!< Deferral Check Enable */ - uint32_t : 2; - __IO uint32_t ACS : 1; /*!< Automatic Pad or CRC Stripping */ - __IO uint32_t LUD : 1; /*!< Link Up or Down */ - uint32_t : 1; - __IO uint32_t IPC : 1; /*!< Checksum Offload */ - __IO uint32_t DM : 1; /*!< Duplex Mode */ - __IO uint32_t LM : 1; /*!< Loopback Mode */ - uint32_t : 1; - __IO uint32_t FES : 1; /*!< Speed in XMII interface */ - __IO uint32_t PS : 1; /*!< the Ethernet line speed */ - uint32_t : 4; - __IO uint32_t JE : 1; /*!< Jumbo enable */ - uint32_t : 1; - __IO uint32_t JD : 1; /*!< if 0, the MAC cuts off the transmitter if more than 2,048 bytes - of data (10,240 if JE is set high) */ - __IO uint32_t WD : 1; /*!< Watchdog Disable */ - __IO uint32_t TC : 1; /*!< If 1, this bit enables the transmission of duplex mode, link - speed, and link up or down information to the PHY */ - __IO uint32_t CST : 1; /*!< CRC Stripping for Type Frames */ - uint32_t : 1; - __IO uint32_t TWOKPE : 1; /*!< If 0, 1518 bytes is considered as a giant frame, 1 is 2000 bytes. */ - __IO uint32_t SARC : 3; /*!< Source Address Insertion or Replacement Control */ - } CONFIG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t FF; /*!< MAC Frame Filter */ - - struct { - __IO uint32_t PR : 1; /*!< Receive all frames in spite of source and destination address */ - __IO uint32_t HUC : 1; /*!< if 1, don't compare DA field in destination address filtering - of unicast frames with DA register */ - __IO uint32_t HMC : 1; /*!< if 1, don't compare DA field in destination address filtering - of multicast frames with DA register */ - __IO uint32_t DAIF : 1; /*!< if set, the Address Check block operates in inverse filtering - mode for the DA address comparison */ - __IO uint32_t PM : 1; /*!< Pass All Multicast */ - __IO uint32_t DBF : 1; /*!< Disable Broadcast Frames */ - __IO uint32_t PCF : 2; /*!< Pass Control Frames */ - __IO uint32_t SAIF : 1; /*!< If set, the frames whose SA matches the SA registers are marked - as failing the SA Address filter */ - __IO uint32_t SAF : 1; /*!< Source Address Filter Enable */ - __IO uint32_t HPF : 1; /*!< Hash or Perfect Filter */ - uint32_t : 5; - __IO uint32_t VTFE : 1; /*!< VLAN Tag Filter Enable */ - uint32_t : 3; - __IO uint32_t IPFE : 1; /*!< Layer 3 and Layer 4 Filter Enable */ - __IO uint32_t DNTU : 1; /*!< Drop non-TCP/UDP over IP Frames */ - uint32_t : 9; - __IO uint32_t RA : 1; /*!< Receive all */ - } FF_b; /*!< BitSize */ - }; - __IO uint32_t HTH; /*!< Hash Table High Register */ - __IO uint32_t HTL; /*!< Hash Table Low Register */ - - union { - __IO uint32_t GMII_ADDR; /*!< GMII Address Register */ - - struct { - __IO uint32_t BUSY : 1; /*!< GMII Busy */ - __IO uint32_t GW : 1; /*!< GMII write or read */ - __IO uint32_t CR : 4; /*!< CSR Clock Range */ - __IO uint32_t GR : 5; /*!< These bits select the desired GMII register in the selected - PHY device */ - __IO uint32_t PA : 5; /*!< This field indicates which of the 32 possible PHY devices are - being accessed */ - } GMII_ADDR_b; /*!< BitSize */ - }; - __IO uint32_t GMII_DATA; /*!< GMII Data Register */ - - union { - __IO uint32_t FC; /*!< Flow Control Register */ - - struct { - __IO uint32_t FCB : 1; /*!< This bit initiates a Pause frame in the full-duplex mode */ - __IO uint32_t TFE : 1; /*!< MAC enables the flow control operation to transmit Pause frames */ - __IO uint32_t RFE : 1; /*!< MAC enables the flow control operation to receive Pause frames */ - __IO uint32_t UP : 1; /*!< MAC can detect Pause frames with unicast address of the station */ - } FC_b; /*!< BitSize */ - }; - - union { - __IO uint32_t VLAN_TAG; /*!< VLAN Tag Register */ - - struct { - __IO uint32_t VL : 16; /*!< VLAN Tag Identifier for Receive Frames */ - __IO uint32_t ETV : 1; /*!< Enable 12-Bit VLAN Tag Comparison */ - __IO uint32_t VTIM : 1; /*!< If set, The frames that do not have matching VLAN Tag are marked - as matched */ - __IO uint32_t ESVL : 1; /*!< If set, consider the S-VLAN (Type = 0x88A8) frames as valid - VLAN tagged frames */ - __IO uint32_t VTHM : 1; /*!< When set, the most significant four bits of the VLAN tag's CRC - are used to index the content */ - } VLAN_TAG_b; /*!< BitSize */ - }; - __I uint32_t RESERVED0[8]; - __IO uint16_t ADDR0_HIGH; /*!< MAC Address0 High Register */ - __I uint16_t RESERVED1; - __IO uint32_t ADDR0_LOW; /*!< MAC Address0 LOW Register */ - - union { - __IO uint32_t ADDR1_HIGH; /*!< MAC Address0 High Register */ - - struct { - __IO uint32_t ADDR : 16; /*!< MAC Address1 [47:32] */ - uint32_t : 14; - __IO uint32_t SA : 1; /*!< MAC address1 is source or destination address compared with - received frame */ - __IO uint32_t AE : 1; /*!< the address filter module uses the MAC address1 for filtering */ - } ADDR1_HIGH_b; /*!< BitSize */ - }; - __IO uint32_t ADDR1_LOW; /*!< MAC Address1 LOW Register */ - __I uint32_t RESERVED2[47]; - __IO uint32_t MMC_RX_MASK; /*!< MMC Receive interrupt mask */ - __IO uint32_t MMC_TX_MASK; /*!< MMC Transmit Interrupt Mask */ - __I uint32_t RESERVED3[955]; - - union { - __IO uint32_t BUS_MODE; /*!< Flow Control Register */ - - struct { - __IO uint32_t SWR : 1; /*!< Software Reset */ - __IO uint32_t DA : 1; /*!< This bit specifies the arbitration scheme between the transmit - and receive paths of Channel */ - __IO uint32_t DSL : 5; /*!< the byte number of bus width to skip between two unchained descriptors */ - __IO uint32_t ATDS : 1; /*!< When set, the size of the alternate descriptor increases to - 32 bytes */ - __IO uint32_t PBL : 6; /*!< These bits indicate the maximum number of beats to be transferred - in one DMA transaction */ - __IO uint32_t PR : 2; /*!< The Priority Ratio is (PR + 1) : 1 */ - __IO uint32_t FB : 1; /*!< performs fixed burst transfers or not */ - __IO uint32_t RPBL : 6; /*!< This field indicates the maximum number of beats to be transferred - in one Rx DMA transaction */ - __IO uint32_t USP : 1; /*!< If set, RPBL is same as RPBL definition */ - __IO uint32_t PBLx8 : 1; /*!< If set, all PBLs multiplies 8 */ - __IO uint32_t AAL : 1; /*!< If set, all bursts aligned to the start address LS bits */ - __IO uint32_t MB : 1; /*!< When this bit is set high and the FB bit is low, the AHB master - interface starts all bursts of length more than 16 with INCR */ - __IO uint32_t TXPR : 1; /*!< When set, the transmit DMA has higher priority than the receive - DMA */ - __IO uint32_t PRWG : 2; /*!< The Priority weight is (PRWG + 1) : 1 */ - uint32_t : 1; - __IO uint32_t RIB : 1; /*!< If set, rebuilds the pending beats of any burst transfer initiated - with INCRx */ - } BUS_MODE_b; /*!< BitSize */ - }; - __IO uint32_t TPD; /*!< Transmit Poll Demand */ - __IO uint32_t RPD; /*!< Receive Poll Demand */ - __IO uint32_t RDESLA; /*!< Receive Descriptor List Address */ - __IO uint32_t TDESLA; /*!< Transmit Descriptor List Address */ - - union { - __IO uint32_t STATUS; /*!< Status Register */ - - struct { - __IO uint32_t TI : 1; /*!< This bit indicates that the frame transmission is complete */ - __IO uint32_t TPS : 1; /*!< Transmit Process Stopped */ - __IO uint32_t TU : 1; /*!< the host owns the Next Descriptor in the Transmit List and the - DMA cannot acquire it. */ - __IO uint32_t TJT : 1; /*!< Transmit Jabber Timeout */ - __IO uint32_t OVF : 1; /*!< Receive Overflow */ - __IO uint32_t UNF : 1; /*!< Transmit Underflow */ - __IO uint32_t RI : 1; /*!< the frame reception is complete */ - __IO uint32_t RU : 1; /*!< Receive Buffer Unavailable */ - __IO uint32_t RPS : 1; /*!< Receive Process Stopped */ - __IO uint32_t RWT : 1; /*!< Receive Watchdog Timeout */ - __IO uint32_t ETI : 1; /*!< the frame to be transmitted is fully transferred to the MTL - Transmit FIFO */ - uint32_t : 2; - __IO uint32_t FBI : 1; /*!< a bus error occurred, as described in EB. */ - __IO uint32_t ERI : 1; /*!< the DMA filled the first data buffer of the packet */ - __IO uint32_t AIS : 1; /*!< Abnormal Interrupt Summary, must be cleared by writting */ - __IO uint32_t NIS : 1; /*!< Normal Interrupt Summary, must be cleared by writting */ - __I uint32_t RS : 3; /*!< Receive DMA FSM state */ - __I uint32_t TS : 3; /*!< Transmit DMA FSM state */ - __I uint32_t EB : 3; /*!< Error bit */ - __I uint32_t GLI : 1; /*!< GMAC Line Interface Interrupt */ - __I uint32_t GMI : 1; /*!< GMAC MMC Interrupt */ - __I uint32_t GPI : 1; /*!< GMAC PMT Interrupt */ - __I uint32_t TTI : 1; /*!< Timestamp Trigger Interrupt */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t OPERATION; /*!< Operation Mode Register */ - - struct { - uint32_t : 1; - __IO uint32_t SR : 1; /*!< Start or Stop Receive */ - __IO uint32_t OSF : 1; /*!< Operate on Second Frame */ - __IO uint32_t RT : 2; /*!< Receive Threshold Control */ - __IO uint32_t DGF : 1; /*!< Drop Giant Frames */ - __IO uint32_t FUF : 1; /*!< Forward Undersized Good Frames */ - __IO uint32_t FEF : 1; /*!< Forward Error Frames */ - uint32_t : 5; - __IO uint32_t ST : 1; /*!< Start or Stop Transmission Command */ - __IO uint32_t TT : 3; /*!< Transmit Threshold Control */ - uint32_t : 3; - __IO uint32_t FTF : 1; /*!< Flush Transmit FIFO */ - __IO uint32_t TSF : 1; /*!< If set, transmission starts when a full frame resides in Transmit - FIFO */ - uint32_t : 2; - __IO uint32_t DFF : 1; /*!< Disable Flushing of Received Frames */ - __IO uint32_t RSF : 1; /*!< If set, the MTL reads a frame from the Rx FIFO while the complete - frame has been written to it, */ - } OPERATION_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_EN; /*!< Interrupt Enable Register */ - - struct { - __IO uint32_t TIE : 1; /*!< Transmit Interrupt Enable */ - __IO uint32_t TSE : 1; /*!< Transmit Stopped Enable */ - __IO uint32_t TUE : 1; /*!< Transmit Buffer Unavailable Enable */ - __IO uint32_t TJE : 1; /*!< Transmit Jabber Timeout Enable */ - __IO uint32_t OVE : 1; /*!< Overflow Interrupt Enable */ - __IO uint32_t UNE : 1; /*!< Underflow Interrupt Enable */ - __IO uint32_t RIE : 1; /*!< Receive Interrupt Enable */ - __IO uint32_t RUE : 1; /*!< Receive Buffer Unavailable Enable */ - __IO uint32_t RSE : 1; /*!< Receive Stopped Enable */ - __IO uint32_t RWE : 1; /*!< Receive Watchdog Timeout Enable */ - __IO uint32_t ETE : 1; /*!< Early Transmit Interrupt Enable */ - uint32_t : 2; - __IO uint32_t FBE : 1; /*!< Fatal Bus Error Enable */ - __IO uint32_t ERE : 1; /*!< Early Receive Interrupt Enable */ - __IO uint32_t AIE : 1; /*!< Abnormal Interrupt Summary Enable */ - __IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */ - } INT_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED4[3]; - - union { - __IO uint32_t AHB_STATUS; /*!< AHB Status Register */ - - struct { - __IO uint32_t BUSY : 1; /*!< If set, it indicates that the AHB master interface FSMs are - in the non-idle state */ - } AHB_STATUS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED5[6]; - __I uint32_t CURTDESAPTR; /*!< Current Host Transmit Descriptor Register */ - __I uint32_t CURRDESAPTR; /*!< Current Host Receive Descriptor Register */ - __I uint32_t CURTBUFAPTR; /*!< Current Host Transmit Buffer Address Register */ - __I uint32_t CURRBUFAPTR; /*!< Current Host Receive Buffer Address Register */ -} ETH_Type; - - -/* ================================================================================ */ -/* ================ USB ================ */ -/* ================================================================================ */ - - -/** - * @brief USB (USB) - */ - -typedef struct { /*!< USB Structure */ - - union { - __IO uint32_t GOTGCTL; /*!< Control and Status register */ - - struct { - __I uint32_t SES_REQ_SCS: 1; /*!< set when a session request initiation is successful as a device */ - __IO uint32_t SES_SEQ : 1; /*!< set to initiate a session request on the USB as a device */ - __IO uint32_t VB_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using - the GOTGCTL.VbvalidOvVal as a host */ - __IO uint32_t VB_VALID_OV_VAL: 1; /*!< set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn - is set as a host */ - __IO uint32_t A_VALID_OV_EN: 1; /*!< enable/disable the software to override the Avalid signal using - the GOTGCTL.AvalidOvVal as a host */ - __IO uint32_t A_VALID_OV_VAL: 1; /*!< set Override value for Avalid signal when GOTGCTL.AvalidOvEn - is set as a host */ - __IO uint32_t B_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using - the GOTGCTL.BvalidOvVal as a device. */ - __IO uint32_t B_VALID_OV_VAL: 1; /*!< set Override value for Bvalid signal when GOTGCTL.BvalidOvEn - is set as a device. */ - __I uint32_t HST_NEG_SCS: 1; /*!< sets when host negotiation is successful as a device. */ - __IO uint32_t HNP_REQ : 1; /*!< sets this bit to initiate an HNP request to the connected USB - host as a device */ - __IO uint32_t HST_SET_HNP_EN: 1; /*!< Host Set HNP Enable as a host */ - __IO uint32_t DEV_HNP_EN : 1; /*!< Device HNP Enabled as a device */ - uint32_t : 4; - __I uint32_t CON_ID_STS : 1; /*!< Connector ID Status */ - __I uint32_t DBNC_TIME : 1; /*!< the debounce time of a detected connection as a host */ - __I uint32_t A_SES_VLD : 1; /*!< A-Session Valid as a host */ - __I uint32_t B_SES_VLD : 1; /*!< B-Session Valid as a host */ - __IO uint32_t OTG_VER : 1; /*!< If 0, OTG Version 1.3. If 1, OTG Version 2.0. */ - } GOTGCTL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GOTGINT; /*!< OTG interrupt Register */ - - struct { - uint32_t : 2; - __IO uint32_t SES_END_DET: 1; /*!< Set when the utmiotg_bvalid signal is deasserted */ - uint32_t : 5; - __IO uint32_t SES_REQ_SUC_STS_CHNG: 1; /*!< Session Request Success Status Change */ - __IO uint32_t HST_NEG_SUC_STS_CHNG: 1; /*!< Host Negotiation Success Status Change */ - uint32_t : 7; - __IO uint32_t HST_NEG_DET: 1; /*!< if set, detects a host negotiation request on the USB */ - __IO uint32_t A_DEV_TOUT_CHG: 1; /*!< A-device has timed out while waiting for the B-device to connect */ - __IO uint32_t DBNCE_DONE : 1; /*!< debounce is completed after the device connect as a host */ - } GOTGINT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GAHBCFG; /*!< AHB Configuration Register */ - - struct { - __IO uint32_t GLBL_INTR_EN: 1; /*!< Global Interrupt Enable */ - __IO uint32_t BST_LEN : 4; /*!< Burst Length/Type */ - __IO uint32_t DMA_EN : 1; /*!< DMA enable */ - uint32_t : 15; - __IO uint32_t REMOTE_MEM_SUPP: 1; /*!< enable the functionality to wait for the system DMA Done Signal - for the DMA Write Transfers */ - __IO uint32_t NOTIFY_ALL_DMA_WRITE: 1; /*!< enable the System DMA Done functionality for all the DMA write - Transactions corresponding to the Channel/Endpoint */ - __IO uint32_t AHB_SINGLE : 1; /*!< supports Single transfers for the remaining data in a transfer */ - } GAHBCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GUSBCFG; /*!< USB Configuration Register */ - - struct { - uint32_t : 3; - __IO uint32_t PHY_IF : 1; /*!< PHY Interface */ - __IO uint32_t ULPI_UTMI_SEL: 1; /*!< 1, ULPI. 0, UTMI+ */ - __IO uint32_t FS_IF : 1; /*!< 1, 3-pin bidirectional. 0, 6-pin unidirectional */ - __IO uint32_t PHY_SEL : 1; /*!< 0, USB 2.0 High-Speed PHY. 1, USB 1.1 full-speed serial transceiver */ - __IO uint32_t DDR_SEL : 1; /*!< 0, Single Data Rate ULPI Interface, with 8-bit-wide data bus. - 1, Double Data Rate ULPI Interface, with 4-bit-wide data bus */ - __IO uint32_t SRP_CAP : 1; /*!< SRP-Capable */ - __IO uint32_t HNP_CAP : 1; /*!< HNP-Capable */ - __IO uint32_t USB_TRD_TIM: 4; /*!< Specifies the response time for a MAC request to the Packet - FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM) as - a device. */ - uint32_t : 1; - __IO uint32_t PHY_LPWR_CLK_SEL: 1; /*!< 0, 480-MHz Internal PLL clock. 1, 48-MHz External Clock */ - uint32_t : 12; - __IO uint32_t TX_END_DELAY: 1; /*!< Tx End Delay as a device */ - __IO uint32_t FORCE_HOST_MODE: 1; /*!< Force Host Mode */ - __IO uint32_t FORCE_DEVICE_MODE: 1; /*!< Force Device Mode */ - } GUSBCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GRSTCTL; /*!< Reset Register */ - - struct { - __IO uint32_t CORE_SOFT_RST: 1; /*!< Core Soft Reset */ - uint32_t : 1; - __IO uint32_t FRM_CNT_RST: 1; /*!< Host Frame Counter Reset */ - uint32_t : 1; - __IO uint32_t RX_FIFO_FLUSH: 1; /*!< RxFIFO Flush */ - __IO uint32_t TX_FIFO_FLUSH: 1; /*!< TxFIFO Flush */ - __IO uint32_t TX_FIFO_FLUSH_NUM: 4; /*!< This field indicates which of the 32 possible PHY devices are - being accessed */ - __IO uint32_t TX_FIFO_ALL: 1; /*!< TxFIFO flush all FIFOs */ - uint32_t : 19; - __I uint32_t DMA_REQ : 1; /*!< Indicates that the DMA request is in progress */ - __I uint32_t AHB_IDLE : 1; /*!< Indicates that the AHB Master State Machine is in the IDLE condition */ - } GRSTCTL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GINTSTS; /*!< Interrupt Register */ - - struct { - __I uint32_t CUR_MOD : 1; /*!< Current Mode of Operation */ - __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch Interrupt */ - __I uint32_t OTG_INT : 1; /*!< OTG Interrupt */ - __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ - __I uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ - __I uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ - __I uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ - __I uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ - uint32_t : 2; - __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ - __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ - __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ - __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ - __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a - device */ - __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ - uint32_t : 1; - __I uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ - __I uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ - __I uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ - __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ - __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous - OUT Transfer as a device */ - __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ - __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ - __I uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as - a host */ - __I uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as - a host */ - __I uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ - __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ - __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ - __IO uint32_t DD : 1; /*!< A change in connector ID status */ - __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ - __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ - } GINTSTS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GINTEN; /*!< Interrupt enable Register */ - - struct { - uint32_t : 1; - __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch */ - __IO uint32_t OTG_INT : 1; /*!< OTG */ - __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ - __IO uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ - __IO uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ - __IO uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ - __IO uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ - uint32_t : 2; - __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ - __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ - __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ - __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ - __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a - device */ - __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ - uint32_t : 1; - __IO uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ - __IO uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ - __IO uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ - __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ - __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous - OUT Transfer as a device */ - __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ - __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ - __IO uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as - a host */ - __IO uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as - a host */ - __IO uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ - __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ - __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ - __IO uint32_t DD : 1; /*!< A change in connector ID status */ - __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ - __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ - } GINTEN_b; /*!< BitSize */ - }; - - union { - __I uint32_t GRXSTSR; /*!< Returns the contents of the top of the Receive FIFO */ - - struct { - __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ - __I uint32_t BCNT : 11; /*!< byte count of the received packet */ - __I uint32_t DPID : 2; /*!< Data PID of the received packet */ - __I uint32_t PS : 4; /*!< the status of the received packet */ - __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which - the packet is received on the USB */ - } GRXSTSR_b; /*!< BitSize */ - }; - - union { - __I uint32_t GRXSTSP; /*!< Pop the contents of the top of the Receive FIFO */ - - struct { - __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ - __I uint32_t BCNT : 11; /*!< byte count of the received packet */ - __I uint32_t DPID : 2; /*!< Data PID of the received packet */ - __I uint32_t PS : 4; /*!< the status of the received packet */ - __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which - the packet is received on the USB */ - } GRXSTSP_b; /*!< BitSize */ - }; - __IO uint16_t GRXFSIZ; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 - is max */ - __I uint16_t RESERVED0; - - union { - __IO uint32_t GNPTXFSIZ; /*!< Non-Periodic Transmit FIFO Size Register */ - - struct { - __IO uint32_t NTRSA_INEF0TRSA: 16; /*!< start address for Non-periodic Transmit FIFO RAM as a host or - IN Endpoint FIFO0 Transmit RAM as a device */ - __IO uint32_t NTD_INEF0TD: 16; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 - is max. Non-periodic TxFIFO Depth as a host or IN Endpoint TxFIFO - 0 Depth as a device */ - } GNPTXFSIZ_b; /*!< BitSize */ - }; - - union { - __I uint32_t GNPTXSTS; /*!< Non-Periodic Transmit FIFO/Queue Status Register */ - - struct { - __I uint32_t NTSA : 16; /*!< the amount of free space available in the Non-periodic TxFIFO, - max is 32768. */ - __I uint32_t NTRQSA : 8; /*!< the amount of free space available in the Non-periodic Transmit - Request Queue, max is 8. */ - __I uint32_t TNTRQ_LAST : 1; /*!< last Entry in the Non-periodic Tx Request Queue that is currently - being processed by the MAC */ - __I uint32_t TNTRQ_TYPE : 2; /*!< type in the Non-periodic Tx Request Queue that is currently - being processed by the MAC */ - __I uint32_t TNTRQ_CH : 4; /*!< Channel of top of the Non-periodic Transmit Request Queue */ - } GNPTXSTS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1[5]; - - union { - __I uint32_t GHWCFG1; /*!< User HW Config1 Register */ - - struct { - __I uint32_t EP0_DIR : 2; /*!< Endpoint 0 direction, always Bidirection */ - __I uint32_t EP1_DIR : 2; /*!< Endpoint 1 direction */ - __I uint32_t EP2_DIR : 2; /*!< Endpoint 2 direction */ - __I uint32_t EP3_DIR : 2; /*!< Endpoint 3 direction */ - __I uint32_t EP4_DIR : 2; /*!< Endpoint 4 direction */ - __I uint32_t EP5_DIR : 2; /*!< Endpoint 5 direction */ - __I uint32_t EP6_DIR : 2; /*!< Endpoint 6 direction */ - __I uint32_t EP7_DIR : 2; /*!< Endpoint 7 direction */ - __I uint32_t EP8_DIR : 2; /*!< Endpoint 8 direction */ - __I uint32_t EP9_DIR : 2; /*!< Endpoint 9 direction */ - __I uint32_t EP10_DIR : 2; /*!< Endpoint 10 direction */ - __I uint32_t EP11_DIR : 2; /*!< Endpoint 11 direction */ - __I uint32_t EP12_DIR : 2; /*!< Endpoint 12 direction */ - __I uint32_t EP13_DIR : 2; /*!< Endpoint 13 direction */ - __I uint32_t EP14_DIR : 2; /*!< Endpoint 14 direction */ - __I uint32_t EP15_DIR : 2; /*!< Endpoint 15 direction */ - } GHWCFG1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2[3]; - - union { - __IO uint32_t GLPMCFG; /*!< Core LPM Configuration Register */ - - struct { - __IO uint32_t EP0_DIR : 1; /*!< LPM capability is enabled */ - } GLPMCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GPWRDN; /*!< Global Power Down Register */ - - struct { - uint32_t : 1; - __IO uint32_t PMU_ACTIVE : 1; /*!< PMU Active is enabled */ - uint32_t : 1; - __IO uint32_t PDC : 1; /*!< Power Down Clamp is enabled */ - __IO uint32_t PDR : 1; /*!< If clear, Reset DWC_otg */ - __IO uint32_t PDS : 1; /*!< If 0, DWC_otg is in ON state, or OFF state */ - __IO uint32_t DIS_VBUS : 1; /*!< Disable VBUS */ - uint32_t : 8; - __IO uint32_t SRP_DETECT_INT: 1; /*!< SRP has been detected by the PMU as a host */ - __IO uint32_t SRP_DETECT_INT_EN: 1; /*!< Enable For SRPDetect Interrupt as a host */ - __IO uint32_t STATE_CHN_INT: 1; /*!< a status change in either the IDDIG or BSessVld signal */ - __IO uint32_t STATE_CHN_INT_EN: 1; /*!< Enable For Status Change Interrupt */ - __I uint32_t LINE_STATE : 2; /*!< the current linestate on USB as seen by the PMU module */ - __I uint32_t IDDIG : 1; /*!< the status of the IDDIG signal. If 0, host mode. if 1, device - mode */ - __I uint32_t B_SESS_VLD : 1; /*!< B session valid status signal from the PHY */ - __IO uint32_t ADP_INT : 1; /*!< set whenever there is a ADP event */ - } GPWRDN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GDFIFOCFG; /*!< Global DFIFO Software Config Register */ - - struct { - __IO uint32_t GDFIFOCFG : 16; /*!< This field is for dynamic programming of the DFIFO Size. */ - __IO uint32_t EPIBA : 16; /*!< This field provides the start address of the EP info controller */ - } GDFIFOCFG_b; /*!< BitSize */ - }; - __I uint32_t RESERVED3[40]; - - union { - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Transmit FIFO Size Register */ - - struct { - __IO uint32_t HPTSA : 16; /*!< start address of the Periodic TxFIFO */ - __IO uint32_t EPIBA : 16; /*!< the size of the Periodic TxFIFO */ - } HPTXFSIZ_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF1; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF2; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF3; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF4; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF5; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF6; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF7; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF8; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF9; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF10; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF11; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF12; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF13; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF14; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF15; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED4[176]; - - union { - __IO uint32_t HCFG; /*!< Host Configuration Register */ - - struct { - __IO uint32_t FS_LS_PCS : 2; /*!< FS/LS PHY Clock Select as a host */ - __IO uint32_t FS_LS_SUPPORT: 1; /*!< If set, FS/LS-only, even If the connected device can support - HS */ - uint32_t : 4; - __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ - __IO uint32_t RVP : 8; /*!< ResValid number of clock cycles to detect a valid resume */ - uint32_t : 7; - __IO uint32_t EN_SG_DMA : 1; /*!< Enable Scatter/gather DMA in Host mode */ - __IO uint32_t FLE : 2; /*!< the number of entries in the Frame list. 8 times of FLE */ - __IO uint32_t EPS : 1; /*!< Enables periodic scheduling */ - uint32_t : 4; - __IO uint32_t MCRTE : 1; /*!< enable/disable the Host core to wait 200 PHY clock cycles at - the end of Resume to change the opmode signal to the PHY to - 00 after Suspend or LPM. */ - } HCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HFIR; /*!< Host Frame Interval Register */ - - struct { - __IO uint32_t FI : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t RC : 1; /*!< The HFIR can be dynamically reloaded during runtime if set */ - } HFIR_b; /*!< BitSize */ - }; - - union { - __I uint32_t HFNUM; /*!< Host Frame Number/Frame Time Remaining Register */ - - struct { - __I uint32_t FN : 16; /*!< This field increments when a new SOF is transmitted on the USB */ - __I uint32_t FTR : 16; /*!< amount of time remaining in the current microframe (HS) or Frame - (FS/LS), in terms of PHY clocks */ - } HFNUM_b; /*!< BitSize */ - }; - __I uint32_t RESERVED5; - - union { - __I uint32_t HPTXSTS; /*!< Host Periodic Transmit FIFO/Queue Status Register */ - - struct { - __I uint32_t PTDFSA : 16; /*!< Indicates the number of free locations available to be written - to in the Periodic TxFIFO, max is 32768 */ - __I uint32_t PTRQSA : 8; /*!< Indicates the number of free locations available to be written - in the Periodic Transmit Request Queue, max is 16 */ - __I uint32_t TPTRQ_LAST : 1; /*!< last Entry in the periodic Tx Request Queue that is currently - being processed by the MAC */ - __I uint32_t TPTRQ_TYPE : 2; /*!< type in the periodic Tx Request Queue that is currently being - processed by the MAC */ - __I uint32_t TPTRQ_CH : 4; /*!< Channel of top of the periodic Transmit Request Queue */ - __I uint32_t TPTRQ_ODD_FRAME: 1; /*!< If set, send in odd (micro)Frame */ - } HPTXSTS_b; /*!< BitSize */ - }; - - union { - __I uint32_t HAINT; /*!< Host All Channels Interrupt Register */ - - struct { - __I uint32_t INT : 16; /*!< Channel Interrupts, from 0 to 15. */ - } HAINT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HAINT_EN; /*!< Host All Channels Interrupt Enable Register */ - - struct { - __IO uint32_t EN : 16; /*!< Channel Interrupts Enable, from 0 to 15. */ - } HAINT_EN_b; /*!< BitSize */ - }; - __IO uint32_t HFLBA; /*!< The starting address of the Frame list */ - __I uint32_t RESERVED6[8]; - - union { - __IO uint32_t __HPRT; /*!< Host Port Control and Status Register */ - - struct { - __I uint32_t PCS : 1; /*!< If a device is attached to the port */ - __IO uint32_t PCD : 1; /*!< A device connection is detected */ - __IO uint32_t PE : 1; /*!< Port Enable */ - __IO uint32_t PEDC : 1; /*!< Set if when the status of the Port Enable (bit 2) of this register - changes */ - __I uint32_t POA : 1; /*!< Indicates the overcurrent condition of the port */ - __IO uint32_t POC : 1; /*!< Set if when the status of the Port Overcurrent Active bit (bit - 4) in this register changes */ - __IO uint32_t PR : 1; /*!< Application and Core all can perform resume by setting, then - clear it whatever resume is success or not */ - __IO uint32_t PS : 1; /*!< Sets this bit to put this port in Suspend mode */ - __IO uint32_t PRESET : 1; /*!< sets this bit, a reset sequence is started on this port */ - uint32_t : 1; - __IO uint32_t PLSDP : 1; /*!< Logic level of D+ */ - __IO uint32_t PLSDN : 1; /*!< Logic level of D- */ - __IO uint32_t PP : 1; /*!< this field to control power to this port. 1, power on */ - __IO uint32_t PTC : 4; /*!< The application writes a nonzero value to this field to put - the port into a Test mode */ - __I uint32_t SPEED : 2; /*!< Indicates the speed of the device attached to this port */ - } __HPRT_b; /*!< BitSize */ - }; - __I uint32_t RESERVED7[47]; - - union { - __IO uint32_t HCC0; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED8; - - union { - __IO uint32_t HCINT0; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN0; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ0; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA0; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED9; - __IO uint32_t HCDMAB0; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC1; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED10; - - union { - __IO uint32_t HCINT1; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN1; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ1; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA1; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED11; - __IO uint32_t HCDMAB1; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC2; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED12; - - union { - __IO uint32_t HCINT2; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN2; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ2; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA2; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED13; - __IO uint32_t HCDMAB2; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC3; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED14; - - union { - __IO uint32_t HCINT3; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN3; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ3; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA3; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED15; - __IO uint32_t HCDMAB3; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC4; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED16; - - union { - __IO uint32_t HCINT4; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN4; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ4; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA4; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED17; - __IO uint32_t HCDMAB4; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC5; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED18; - - union { - __IO uint32_t HCINT5; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN5; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ5; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA5; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED19; - __IO uint32_t HCDMAB5; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC6; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED20; - - union { - __IO uint32_t HCINT6; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN6; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ6; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA6; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED21; - __IO uint32_t HCDMAB6; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC7; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED22; - - union { - __IO uint32_t HCINT7; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN7; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ7; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA7; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED23; - __IO uint32_t HCDMAB7; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC8; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED24; - - union { - __IO uint32_t HCINT8; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN8; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ8; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA8; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED25; - __IO uint32_t HCDMAB8; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC9; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED26; - - union { - __IO uint32_t HCINT9; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN9; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ9; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA9; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED27; - __IO uint32_t HCDMAB9; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC10; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED28; - - union { - __IO uint32_t HCINT10; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN10; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ10; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA10; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED29; - __IO uint32_t HCDMAB10; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC11; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED30; - - union { - __IO uint32_t HCINT11; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN11; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ11; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA11; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED31; - __IO uint32_t HCDMAB11; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC12; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED32; - - union { - __IO uint32_t HCINT12; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN12; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ12; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA12; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED33; - __IO uint32_t HCDMAB12; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC13; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED34; - - union { - __IO uint32_t HCINT13; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN13; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ13; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA13; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED35; - __IO uint32_t HCDMAB13; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC14; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED36; - - union { - __IO uint32_t HCINT14; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN14; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ14; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA14; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED37; - __IO uint32_t HCDMAB14; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC15; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED38; - - union { - __IO uint32_t HCINT15; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT15_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN15; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN15_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ15; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ15_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA15; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED39; - __IO uint32_t HCDMAB15; /*!< Host Channel-n DMA Buffer Address Register */ - __I uint32_t RESERVED40[64]; - - union { - __IO uint32_t DCFG; /*!< Device Configuration Register */ - - struct { - __IO uint32_t DSPEED : 2; /*!< the maximum speed the application can support */ - __IO uint32_t NZLSOH : 1; /*!< select the handshake the core sends on receiving a non zero-length - data packet during the OUT transaction of a control transfer's - Status stage */ - __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ - __IO uint32_t DEVICE_ADDR: 7; /*!< The application must program this field after every SetAddress - control command */ - __IO uint32_t PFI : 2; /*!< Indicates the time within a (micro)frame at which the application - must be notified using the End Of Periodic Frame Interrupt */ - __IO uint32_t EDON : 1; /*!< If set the core sets NAK after Bulk OUT transfer complete */ - uint32_t : 9; - __IO uint32_t EN_SG_DMA : 1; /*!< enable the Scatter/Gather DMA operation */ - __IO uint32_t PSI : 2; /*!< Periodic Scheduling Interval */ - __IO uint32_t RVP : 6; /*!< It controls the resume period when the core resumes from suspend */ - } DCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DCTL; /*!< Device Control Register */ - - struct { - __IO uint32_t RWS : 1; /*!< If set, the core initiates remote signaling to wake the USB - hosts */ - __IO uint32_t SD : 1; /*!< If set, generates a device disconnect event to the USB host */ - __I uint32_t GNPINS : 1; /*!< A NAK handshake is sent out on all non-periodic IN endpoints, - irrespective of the data availability in the transmit FIFO. */ - __I uint32_t GONS : 1; /*!< No data is written to the RxFIFO, irrespective of space availability.. */ - __IO uint32_t TC : 3; /*!< Test Control */ - __O uint32_t SGNPIN : 1; /*!< A write to this field sets the Global Non-periodic IN NAK */ - __O uint32_t CGNPIN : 1; /*!< A write to this field clears the Global Non-periodic IN NAK */ - __O uint32_t SGON : 1; /*!< A write to this field sets the Global OUT NAK */ - __O uint32_t CGON : 1; /*!< A write to this field sets the Global OUT NAK. */ - __IO uint32_t POPD : 1; /*!< Power-On Programming Done */ - __IO uint32_t GMC : 2; /*!< GMC must be programmed only once after initialization. the number - of packets to be serviced for that end point before moving to - the next end point */ - uint32_t : 1; - __IO uint32_t IFNIE : 1; /*!< Ignore frame number for isochronous endpoints */ - __IO uint32_t NBE : 1; /*!< Set NAK automatically on babble */ - __IO uint32_t ECBNA : 1; /*!< After receiving BNA interrupt, the core disables the endpoint */ - } DCTL_b; /*!< BitSize */ - }; - - union { - __I uint32_t DSTS; /*!< Device Status Register */ - - struct { - __I uint32_t SUSPEND : 1; /*!< this bit is set as long as a Suspend condition is detected on - the USB */ - __I uint32_t SPEED : 2; /*!< Indicates the speed at which the DWC_otg core has come up after - speed detection through a chirp sequence */ - __I uint32_t EE : 1; /*!< reason of suspend state */ - uint32_t : 4; - __I uint32_t SOFFN : 14; /*!< Frame or Microframe Number of the Received SOF */ - __I uint32_t DLSDP : 1; /*!< Logic level of D+ */ - __I uint32_t DLSDN : 1; /*!< Logic level of D- */ - } DSTS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED41; - - union { - __IO uint32_t DIEPEN; /*!< Device IN Endpoint Common Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ - __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ - __IO uint32_t TIMEOUT : 1; /*!< Timeout Condition(Non-isochronous endpoints) */ - __IO uint32_t ITRWTFE : 1; /*!< IN Token Received When TxFIFO Empty */ - __IO uint32_t ITRWEPM : 1; /*!< IN Token received with EP Mismatch */ - __IO uint32_t IENE : 1; /*!< IN Endpoint NAK Effective */ - uint32_t : 1; - __IO uint32_t FU : 1; /*!< Fifo Underrun */ - __IO uint32_t BNA : 1; /*!< BNA Interrupt */ - uint32_t : 3; - __IO uint32_t NAK : 1; /*!< NAK interrupt */ - } DIEPEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DOEPEN; /*!< Device OUT Endpoint Common Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ - __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ - __IO uint32_t SPD : 1; /*!< SETUP Phase Done, Applies to control endpoints only */ - __IO uint32_t OTRWED : 1; /*!< OUT Token Received when Endpoint Disabled, Applies to control - OUT endpoints only */ - __IO uint32_t SPR : 1; /*!< Status Phase Received */ - __IO uint32_t BTBSPR : 1; /*!< Back-to-Back SETUP Packets Received, Applies to control OUT - endpoints only */ - uint32_t : 1; - __IO uint32_t OPE : 1; /*!< OUT Packet Error */ - __IO uint32_t BNA : 1; /*!< BNA Interrupt */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error interrupt */ - __IO uint32_t NAK : 1; /*!< NAK interrupt */ - __IO uint32_t NYET : 1; /*!< NYET interrupt */ - } DOEPEN_b; /*!< BitSize */ - }; - - union { - __I uint32_t DAINT; /*!< Device All Channels Interrupt Register */ - - struct { - __I uint32_t INT : 16; /*!< IN Endpoint Interrupt Bits, from 0 to 15. */ - __I uint32_t OUT_INT : 16; /*!< OUT Endpoint Interrupt Bits, from 0 to 15. */ - } DAINT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DAINT_EN; /*!< Device All Channels Interrupt Enable Register */ - - struct { - __IO uint32_t IN_EN : 16; /*!< IN EP Interrupt Enable, from 0 to 15. */ - __IO uint32_t OUT_EN : 16; /*!< OUT EP Interrupt Enable, from 0 to 15. */ - } DAINT_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED42[4]; - - union { - __IO uint32_t DTHRCTL; /*!< Device Threshold Control Register */ - - struct { - __IO uint32_t NISOINETE : 1; /*!< Non-ISO IN Endpoints Threshold Enable */ - __IO uint32_t ISOINETE : 1; /*!< ISO IN Endpoints Threshold Enable */ - __IO uint32_t TTL : 9; /*!< This field specifies Transmit thresholding size in DWORDS */ - __IO uint32_t ATR : 2; /*!< These bits define the ratio between the AHB threshold and the - MAC threshold for the transmit path only. */ - uint32_t : 3; - __IO uint32_t RTE : 1; /*!< If set, the core enables thresholding in the receive direction */ - __IO uint32_t RTL : 9; /*!< This field specifies Receive thresholding size in DWORDS */ - uint32_t : 1; - __IO uint32_t APE : 1; /*!< This bit controls internal DMA arbiter parking for IN endpoints */ - } DTHRCTL_b; /*!< BitSize */ - }; - __IO uint16_t DIEPEMPEN; /*!< Device IN Endpoint FIFO Empty Interrupt Enable Register */ - __I uint16_t RESERVED43[101]; - - union { - __IO uint32_t DIEPCTL0; /*!< Device Control IN Endpoint 0 Control Register */ - - struct { - __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, - applies to IN and OUT endpoints */ - uint32_t : 13; - __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active - in all configurations and interfaces */ - uint32_t : 1; - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ - __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a - SETUP token is received for this endpoint */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - uint32_t : 2; - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED44; - - union { - __IO uint32_t DIEPINT0; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED45; - - union { - __IO uint32_t DIEPTSIZ0; /*!< Device IN Endpoint 0 Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ - uint32_t : 12; - __IO uint32_t PACKET_CNT : 2; /*!< the total number of USB packets */ - } DIEPTSIZ0_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA0; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA0; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED46; - __I uint32_t DIEPDMAB0; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL1; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED47; - - union { - __IO uint32_t DIEPINT1; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED48; - - union { - __IO uint32_t DIEPTSIZ1; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ1_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA1; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA1; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED49; - __I uint32_t DIEPDMAB1; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL2; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED50; - - union { - __IO uint32_t DIEPINT2; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED51; - - union { - __IO uint32_t DIEPTSIZ2; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ2_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA2; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA2; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED52; - __I uint32_t DIEPDMAB2; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL3; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED53; - - union { - __IO uint32_t DIEPINT3; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED54; - - union { - __IO uint32_t DIEPTSIZ3; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ3_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA3; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA3; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED55; - __I uint32_t DIEPDMAB3; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL4; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED56; - - union { - __IO uint32_t DIEPINT4; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED57; - - union { - __IO uint32_t DIEPTSIZ4; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ4_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA4; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA4; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED58; - __I uint32_t DIEPDMAB4; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL5; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED59; - - union { - __IO uint32_t DIEPINT5; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED60; - - union { - __IO uint32_t DIEPTSIZ5; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ5_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA5; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA5; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED61; - __I uint32_t DIEPDMAB5; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL6; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED62; - - union { - __IO uint32_t DIEPINT6; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED63; - - union { - __IO uint32_t DIEPTSIZ6; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ6_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA6; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA6; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED64; - __I uint32_t DIEPDMAB6; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL7; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED65; - - union { - __IO uint32_t DIEPINT7; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED66; - - union { - __IO uint32_t DIEPTSIZ7; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ7_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA7; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA7; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED67; - __I uint32_t DIEPDMAB7; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL8; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED68; - - union { - __IO uint32_t DIEPINT8; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED69; - - union { - __IO uint32_t DIEPTSIZ8; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ8_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA8; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA8; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED70; - __I uint32_t DIEPDMAB8; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL9; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED71; - - union { - __IO uint32_t DIEPINT9; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED72; - - union { - __IO uint32_t DIEPTSIZ9; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ9_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA9; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA9; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED73; - __I uint32_t DIEPDMAB9; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL10; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED74; - - union { - __IO uint32_t DIEPINT10; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED75; - - union { - __IO uint32_t DIEPTSIZ10; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ10_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA10; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA10; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED76; - __I uint32_t DIEPDMAB10; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL11; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED77; - - union { - __IO uint32_t DIEPINT11; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED78; - - union { - __IO uint32_t DIEPTSIZ11; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ11_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA11; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA11; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED79; - __I uint32_t DIEPDMAB11; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL12; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED80; - - union { - __IO uint32_t DIEPINT12; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED81; - - union { - __IO uint32_t DIEPTSIZ12; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ12_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA12; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA12; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED82; - __I uint32_t DIEPDMAB12; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL13; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED83; - - union { - __IO uint32_t DIEPINT13; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED84; - - union { - __IO uint32_t DIEPTSIZ13; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ13_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA13; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA13; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED85; - __I uint32_t DIEPDMAB13; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL14; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED86; - - union { - __IO uint32_t DIEPINT14; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED87; - - union { - __IO uint32_t DIEPTSIZ14; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ14_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA14; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA14; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED88; - __I uint32_t DIEPDMAB14; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL15; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED89; - - union { - __IO uint32_t DIEPINT15; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED90; - - union { - __IO uint32_t DIEPTSIZ15; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ15_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA15; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA15; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED91; - __I uint32_t DIEPDMAB15; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL0; /*!< Device Control OUT Endpoint 0 Control Register */ - - struct { - __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, - applies to IN and OUT endpoints */ - uint32_t : 13; - __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active - in all configurations and interfaces */ - uint32_t : 1; - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ - __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ - __IO uint32_t SNOOP : 1; /*!< does not check if the OUT packets are correct before transferring */ - __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a - SETUP token is received for this endpoint */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - uint32_t : 2; - __I uint32_t EPD : 1; /*!< The application cannot disable control OUT endpoint 0 */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED92; - - union { - __IO uint32_t DOEPINT0; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED93; - - union { - __IO uint32_t DOEPTSIZ0; /*!< Device OUT Endpoint 0 Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ - uint32_t : 12; - __IO uint32_t PACKET_CNT : 1; /*!< This field is decremented to zero after a packet is written - into the RxFIFO */ - uint32_t : 9; - __IO uint32_t SETUP_CNT : 2; /*!< the number of back-to-back SETUP data packets the endpoint can - receive */ - } DOEPTSIZ0_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA0; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED94; - __I uint32_t DOEPDMAB0; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL1; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED95; - - union { - __IO uint32_t DOEPINT1; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED96; - - union { - __IO uint32_t DOEPTSIZ1; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ1_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA1; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED97; - __I uint32_t DOEPDMAB1; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL2; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED98; - - union { - __IO uint32_t DOEPINT2; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED99; - - union { - __IO uint32_t DOEPTSIZ2; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ2_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA2; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED100; - __I uint32_t DOEPDMAB2; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL3; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED101; - - union { - __IO uint32_t DOEPINT3; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED102; - - union { - __IO uint32_t DOEPTSIZ3; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ3_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA3; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED103; - __I uint32_t DOEPDMAB3; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL4; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED104; - - union { - __IO uint32_t DOEPINT4; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED105; - - union { - __IO uint32_t DOEPTSIZ4; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ4_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA4; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED106; - __I uint32_t DOEPDMAB4; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL5; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED107; - - union { - __IO uint32_t DOEPINT5; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED108; - - union { - __IO uint32_t DOEPTSIZ5; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ5_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA5; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED109; - __I uint32_t DOEPDMAB5; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL6; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED110; - - union { - __IO uint32_t DOEPINT6; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED111; - - union { - __IO uint32_t DOEPTSIZ6; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ6_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA6; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED112; - __I uint32_t DOEPDMAB6; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL7; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED113; - - union { - __IO uint32_t DOEPINT7; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED114; - - union { - __IO uint32_t DOEPTSIZ7; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ7_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA7; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED115; - __I uint32_t DOEPDMAB7; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL8; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED116; - - union { - __IO uint32_t DOEPINT8; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED117; - - union { - __IO uint32_t DOEPTSIZ8; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ8_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA8; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED118; - __I uint32_t DOEPDMAB8; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL9; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED119; - - union { - __IO uint32_t DOEPINT9; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED120; - - union { - __IO uint32_t DOEPTSIZ9; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ9_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA9; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED121; - __I uint32_t DOEPDMAB9; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL10; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED122; - - union { - __IO uint32_t DOEPINT10; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED123; - - union { - __IO uint32_t DOEPTSIZ10; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ10_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA10; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED124; - __I uint32_t DOEPDMAB10; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL11; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED125; - - union { - __IO uint32_t DOEPINT11; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED126; - - union { - __IO uint32_t DOEPTSIZ11; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ11_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA11; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED127; - __I uint32_t DOEPDMAB11; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL12; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED128; - - union { - __IO uint32_t DOEPINT12; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED129; - - union { - __IO uint32_t DOEPTSIZ12; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ12_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA12; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED130; - __I uint32_t DOEPDMAB12; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL13; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED131; - - union { - __IO uint32_t DOEPINT13; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED132; - - union { - __IO uint32_t DOEPTSIZ13; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ13_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA13; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED133; - __I uint32_t DOEPDMAB13; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL14; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED134; - - union { - __IO uint32_t DOEPINT14; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED135; - - union { - __IO uint32_t DOEPTSIZ14; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ14_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA14; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED136; - __I uint32_t DOEPDMAB14; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL15; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED137; - - union { - __IO uint32_t DOEPINT15; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED138; - - union { - __IO uint32_t DOEPTSIZ15; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ15_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA15; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED139; - __I uint32_t DOEPDMAB15; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ -} USB_Type; - - -/* ================================================================================ */ -/* ================ GLOBAL_CTRL ================ */ -/* ================================================================================ */ - - -/** - * @brief GLOBAL_CTRL (GLOBAL_CTRL) - */ - -typedef struct { /*!< GLOBAL_CTRL Structure */ - - union { - __I uint32_t AES_STATUS; /*!< AES status */ - - struct { - __I uint32_t RD_ALMOST_EMPTY: 1; /*!< FIFO read almost empty */ - __I uint32_t RD_EMPTY : 1; /*!< FIFO read empty */ - __I uint32_t WR_FULL_ALMOST: 1; /*!< FIFO write almost full */ - __I uint32_t WR_FULL : 1; /*!< FIFO write full */ - __I uint32_t IDLE : 1; /*!< decryption finish */ - } AES_STATUS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED0[253]; - - union { - __IO uint32_t CLK_SEL_0; /*!< clock select 0 */ - - struct { - __IO uint32_t CAN1_CLK : 2; /*!< CAN1 clock frequency dividor based on system clock, which should - be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t CAN0_CLK : 2; /*!< CAN0 clock frequency dividor based on system clock, which should - be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t I2C1_CLK : 2; /*!< I2C1 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t I2C0_CLK : 2; /*!< I2C0 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t SPI1_CLK : 2; /*!< SPI1 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t SPI0_CLK : 2; /*!< SPI0 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t UART1_CLK : 2; /*!< UART1 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t UART0_CLK : 2; /*!< UART0 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t RTC_CLK : 2; /*!< RTC clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t GPIO_CLK : 2; /*!< GPIO clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t TIMER_CLK : 2; /*!< TIMER clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t WDG_CLK : 2; /*!< watchdog clock frequency dividor based on system clock, which - should be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - uint32_t : 2; - __IO uint32_t FLASH_CLK : 2; /*!< FLASH clock frequency dividor based on system clock, which should - be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - __IO uint32_t DMA_AHB_CLK: 2; /*!< DMA AHB bus clock frequency dividor based on system clock, which - should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - __IO uint32_t USB_AHB_CLK: 2; /*!< USB AHB bus clock frequency dividor based on system clock, which - should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - } CLK_SEL_0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CLK_SEL_1; /*!< clock select 1 */ - - struct { - __IO uint32_t ETH_AHB_CLK: 2; /*!< ETH_AHB clock frequency dividor based on system clock, which - should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - __IO uint32_t DDR_CLK : 2; /*!< DDR clock frequency dividor based on system clock, which should - be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - uint32_t : 4; - __IO uint32_t ADC_CLK : 2; /*!< ADC clock frequency dividor based on system clock, which should - be 1/8, 1/16, 1/32, external from 0 to 3 */ - __IO uint32_t EFUSE_CLK : 2; /*!< EFUSE clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t SYS_CLK : 4; /*!< system clock clock frequency dividor based on system clock, - which should be oscillator(0), DLL(1), crystal(2), external(3), - JTAG(4), PS(8) */ - __IO uint32_t UART2_CLK : 2; /*!< UART2 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t UTMI_CLK : 1; /*!< UTMI clock came from on-chip usb phy(0) or off-chip usb phy(1) */ - } CLK_SEL_1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t USB_PHY_CTRL; /*!< USB Phy Control Register */ - - struct { - __IO uint32_t BITSTUFF : 1; /*!< 0: No bit stuff */ - __IO uint32_t XTLSEL : 1; /*!< 0: 12MHz */ - __IO uint32_t PLL : 1; /*!< PLL mode */ - __IO uint32_t VOLDET : 1; /*!< Voltage Detector Enable, 0: Disable */ - __IO uint32_t IDUP : 1; /*!< 0: ID is uplled up through 33k Ohm resister */ - __IO uint32_t CKISEL : 1; /*!< Clock selection, 0: Crystal, 1: Internal Clock */ - __IO uint32_t FMOD : 1; /*!< 1: Normal */ - __IO uint32_t SQUELCH : 3; /*!< Squelch Reference Voltage, 000: 27.5mV, 001: 137.5mV, 111: 220mV */ - __IO uint32_t HDISCDT : 3; /*!< Host Disconnect Detection Reference Voltage, 000: 500mV, 100: - 588mV, 111: 654mV */ - __IO uint32_t PRTSEL : 1; /*!< 0: Internal OTG PHY, 1: UTMI to External PHY */ - __IO uint32_t RSTPRT : 1; /*!< 0: The reverse of usb_rst_n will reset, 1: Reset OTG PHY */ - } USB_PHY_CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RTC_INT_EN; /*!< RTC interrupt enable Register */ - - struct { - __IO uint32_t SECOND : 1; /*!< 1s interrupt enable */ - __IO uint32_t MICROSECOND: 1; /*!< 1ms interrupt enable */ - } RTC_INT_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1; - - union { - __IO uint32_t NMI_SEL; /*!< nmi interrupt selection */ - - struct { - __IO uint32_t NMI : 7; /*!< NMI interrupt ID */ - } NMI_SEL_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2; - __IO uint32_t AES_TARGET_ADDR; /*!< AES target address, default is frame decoder address(0x41800000) */ - - union { - __IO uint32_t AES_BURST_TYPE; /*!< AES burst type */ - - struct { - __IO uint32_t TYPE : 2; /*!< burst type, fixed(0), incr(1) */ - } AES_BURST_TYPE_b; /*!< BitSize */ - }; - __I uint32_t RESERVED3[3]; - - union { - __IO uint32_t ICACHE; /*!< ICACHE Enable */ - - struct { - __IO uint32_t EN : 1; /*!< ICACHE Enable */ - } ICACHE_b; /*!< BitSize */ - }; - __IO uint32_t IBUSOFF; /*!< Code Bus Offset */ - __IO uint32_t DBUSOFF; /*!< Data Bus Offset */ - __IO uint32_t EXTADDR; /*!< Bus Ext Addr */ -} GLOBAL_CTRL_Type; - - -/* ================================================================================ */ -/* ================ AES ================ */ -/* ================================================================================ */ - - -/** - * @brief AES (AES) - */ - -typedef struct { /*!< AES Structure */ - __IO uint32_t FIFO; /*!< data FIFO to be decoded */ - - union { - __O uint32_t FIFO_CLEAR; /*!< clear data FIFO */ - - struct { - __O uint32_t CLEAR : 1; /*!< clear after write 1 and write 0 */ - } FIFO_CLEAR_b; /*!< BitSize */ - }; -} AES_Type; - - -/* ================================================================================ */ -/* ================ DDRC ================ */ -/* ================================================================================ */ - - -/** - * @brief DDR_CFG (DDRC) - */ - -typedef struct { /*!< DDRC Structure */ - __IO uint32_t CMD; /*!< DDR commands to program */ - - union { - __IO uint32_t CTRL; /*!< DDR Control */ - - struct { - __IO uint32_t TO : 1; /*!< Take over DDRC siggen */ - __IO uint32_t CLR : 1; /*!< Clear commands in FIFO */ - __O uint32_t STR : 1; /*!< Start to execute the commands in FIFO */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t MODE; /*!< DDR mode */ - - struct { - __IO uint32_t MODE : 6; /*!< DDRC Mode */ - uint32_t : 2; - __IO uint32_t LANE : 1; /*!< LANE synchronization logic bypass */ - uint32_t : 7; - __IO uint32_t B16 : 2; /*!< Active 16 bit DQ position when the unmber of DQ IO is 16 */ - uint32_t : 6; - __IO uint32_t CLKPOL : 2; /*!< DQS clkpol set by user on the PHY */ - } MODE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t QUE; /*!< DDRC queue depth */ - - struct { - __IO uint32_t DEPTH : 1; /*!< DDRC queue depth */ - } QUE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t REF; /*!< Refresh control */ - - struct { - __IO uint32_t THRD : 5; /*!< Number of refresh requests which can be postponed */ - uint32_t : 3; - __IO uint32_t TRIG : 4; /*!< Number of refresh requests every dl_refi */ - uint32_t : 4; - __IO uint32_t TIME : 16; /*!< Refresh interval time */ - } REF_b; /*!< BitSize */ - }; - - union { - __O uint32_t REF_TRIG; /*!< Refresh trigger */ - - struct { - __O uint32_t GO : 1; /*!< Write 1 to trigger one refresh request by cbus */ - } REF_TRIG_b; /*!< BitSize */ - }; - - union { - __O uint32_t ZQ_TRIG; /*!< ZQCTL trigger */ - - struct { - __O uint32_t CS : 1; /*!< Write 1 to trigger one ZQCS request by cbus */ - __O uint32_t CL : 1; /*!< Write 1 to trigger one ZQCL request by cbus */ - } ZQ_TRIG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ZQCSR; /*!< ZQCSR */ - - struct { - __IO uint32_t EN : 1; /*!< Enable ZQCS request */ - __IO uint32_t PRI : 1; /*!< 0: DMA access prior to ZQCS, 1: ZQCS prior to DMA access */ - } ZQCSR_b; /*!< BitSize */ - }; - __IO uint32_t ZQCSI; /*!< ZQCS interval time */ - - union { - __IO uint32_t RCD; /*!< t(RCD) */ - - struct { - __IO uint32_t DI : 5; /*!< t(RCD), delay from ACT command to RW command of same bank */ - } RCD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RAS; /*!< t(RAS) */ - - struct { - __IO uint32_t DI : 6; /*!< t(RAS), delay from ACT command to PRE command of same bank */ - } RAS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RP; /*!< t(RP) */ - - struct { - __IO uint32_t DI : 5; /*!< t(RP), delay from PRE command to ACT/REF/ZQ command */ - uint32_t : 3; - __IO uint32_t RPA : 1; /*!< 0: t(RP) delay for PREA command; 1: t(RP)+1 delay for PREA command */ - } RP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RC; /*!< t(RC) */ - - struct { - __IO uint32_t DI : 7; /*!< t(RC), delay from ACT command to ACT command of same bank */ - } RC_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RRD; /*!< t(RRD) */ - - struct { - __IO uint32_t DI : 4; /*!< t(RRD), delay from ACT command to ACT command */ - } RRD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CCD; /*!< t(CCD) */ - - struct { - __IO uint32_t DI : 3; /*!< t(CCD), delay from RW command to RW command */ - } CCD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RTW; /*!< t(RTW) */ - - struct { - __IO uint32_t DI : 5; /*!< t(RTW), delay from RD command to WR command */ - } RTW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WTR; /*!< t(WTR) */ - - struct { - __IO uint32_t DI : 5; /*!< t(WTR), delay from WR command to RD command */ - } WTR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RTP; /*!< t(RTP) */ - - struct { - __IO uint32_t DI : 3; /*!< t(RTP), delay from RD command to PRE command of same bank */ - } RTP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WTP; /*!< t(WTP) */ - - struct { - __IO uint32_t DI : 6; /*!< t(WTP), delay from WR command to PRE command of same bank */ - } WTP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RFC; /*!< t(RFC) */ - - struct { - __IO uint32_t DI : 8; /*!< t(WTP), delay from WR command to PRE command of same bank */ - } RFC_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ZQCL; /*!< t(ZQoper) */ - - struct { - __IO uint32_t DI : 9; /*!< t(ZQoper), delay from ZQCL command to REF/ZQ/ACT command */ - } ZQCL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ZQCS; /*!< t(ZQCS) */ - - struct { - __IO uint32_t DI : 7; /*!< t(ZQCS), delay from ZQCS command to REF/ZQ/ACT command */ - } ZQCS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t FAW; /*!< t(FAW) */ - - struct { - __IO uint32_t DI : 6; /*!< t(FAW), 4 act command window time */ - } FAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t BURST; /*!< BURST */ - - struct { - __IO uint32_t LEN : 1; /*!< 0: length 8, 1: length 4 */ - } BURST_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PHUNG; /*!< PHUNG */ - - struct { - __IO uint32_t MODE : 1; /*!< 0: normal mode, 1: prevent read hang mode */ - __IO uint32_t LPM : 1; /*!< 1: stop the IO clk */ - } PHUNG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RL; /*!< READ Latency */ - - struct { - __IO uint32_t VAL : 5; /*!< READ Latency */ - } RL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WL; /*!< WRITE Latency */ - - struct { - __IO uint32_t VAL : 5; /*!< WRITE Latency */ - } WL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TRAIN; /*!< TRAIN */ - - struct { - __IO uint32_t EN : 4; /*!< Enable lane N training mode */ - } TRAIN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN0; /*!< Delay cycles of dqsen of byte lane 0 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 0 */ - } DQSEN0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN1; /*!< Delay cycles of dqsen of byte lane 1 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 1 */ - } DQSEN1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN2; /*!< Delay cycles of dqsen of byte lane 2 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 2 */ - } DQSEN2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN3; /*!< Delay cycles of dqsen of byte lane 0 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 3 */ - } DQSEN3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ODTH; /*!< Delay from WR command to odt high transition */ - - struct { - __IO uint32_t DL : 5; /*!< Delay from WR command to odt high transition */ - } ODTH_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ODTL; /*!< Delay from WR command to odt low transition */ - - struct { - __IO uint32_t DL : 5; /*!< Delay from WR command to odt low transition */ - } ODTL_b; /*!< BitSize */ - }; - - union { - __O uint32_t ODT; /*!< Used in write leveling mode */ - - struct { - __O uint32_t TRIG : 1; /*!< 0: trigger odt low, 1: trigger odt high */ - } ODT_b; /*!< BitSize */ - }; - - union { - __O uint32_t DQS; /*!< Used in write leveling mode */ - - struct { - __O uint32_t TRIG : 1; /*!< Writing 1 to this register triggers a dqs pulse */ - } DQS_b; /*!< BitSize */ - }; - - union { - __I uint32_t STA; /*!< Commands FIFO */ - - struct { - __I uint32_t MODE : 1; /*!< DDRC in sw_proc mode */ - __I uint32_t EMPTY : 1; /*!< Sw_proc command fifo empty */ - __I uint32_t FULL : 1; /*!< Sw_proc command fifo full */ - } STA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INTCTL; /*!< Interrupt Control */ - - struct { - __IO uint32_t DONE : 1; /*!< 0: the sw_proc_done int will not be masked, 1: the sw_proc_done - int will be masked */ - __IO uint32_t ERR : 1; /*!< mask of the lane_sync_error interrupt */ - uint32_t : 14; - __IO uint32_t MODE : 1; /*!< Interrupt mode: 0: int level active, write 1 to clear; 1: int - edge active */ - } INTCTL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INTRAW; /*!< Interrupt RAW */ - - struct { - __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done before mask */ - __IO uint32_t ERR : 1; /*!< int reg of the lane sync error before masked */ - } INTRAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INTSTA; /*!< Interrupt STA */ - - struct { - __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done after mask */ - __IO uint32_t ERR : 1; /*!< int register of lane sync error after masked */ - } INTSTA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PHY; /*!< PHY */ - - struct { - __IO uint32_t RST : 1; /*!< FPGA version, reset read dq fifo. Low active */ - } PHY_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RDQ; /*!< FPGA version, read dq delay of byte lane N */ - - struct { - __IO uint32_t L3 : 6; /*!< FPGA version, read dq delay of byte lane3 */ - uint32_t : 2; - __IO uint32_t L2 : 6; /*!< FPGA version, read dq delay of byte lane2 */ - uint32_t : 2; - __IO uint32_t L1 : 6; /*!< FPGA version, read dq delay of byte lane3 */ - uint32_t : 2; - __IO uint32_t L0 : 7; /*!< FPGA version, read dq delay of byte lane0 */ - } RDQ_b; /*!< BitSize */ - }; - - union { - __I uint32_t CALIB; /*!< calibration */ - - struct { - __I uint32_t TPU : 8; /*!< calibration result values, if fail then 0x40 */ - __I uint32_t TPD : 8; /*!< calibration result values, if fail then 0x40 */ - __I uint32_t PDR : 5; /*!< calibration result values, if fail then 0x40 */ - __I uint32_t NDR : 5; /*!< calibration result values, if fail then 0x40 */ - uint32_t : 5; - __IO uint32_t EN : 1; /*!< trigger the calibration processing which is sensitive to the - positive edge */ - } CALIB_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ITMDLY; /*!< "itmdly" is the fine delay trim to the read path "dq", "itmsdly" - is to the read path of "dqs". From 000 to 111 increasingly, - each step is about 40ps */ - - struct { - __IO uint32_t I0 : 4; /*!< itmdly0 */ - __IO uint32_t IS0 : 4; /*!< itmsdly0 */ - __IO uint32_t I1 : 4; /*!< itmdly1 */ - __IO uint32_t IS1 : 4; /*!< itmsdly1 */ - __IO uint32_t I2 : 4; /*!< itmdly2 */ - __IO uint32_t IS2 : 4; /*!< itmsdly2 */ - __IO uint32_t I3 : 4; /*!< itmdly3 */ - __IO uint32_t IS3 : 4; /*!< itmsdly3 */ - } ITMDLY_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TUNE; /*!< CALIB_TUNE */ - - struct { - __IO uint32_t TPU : 4; /*!< tpu_tune, finial val = tune[3] ? val - tune : val + tune */ - __IO uint32_t TPD : 4; /*!< tpd_tune, tune[3:0] for TPD/TPU, [2:0] is the tune val */ - __IO uint32_t PDR : 4; /*!< pdr_tune, inial val = tune[2] ? val - tune : val + tune */ - __IO uint32_t NDR : 4; /*!< ndr_tune, tune[2:0] for NDR/PDR, [1:0] is the tune val */ - } TUNE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RD_SEL; /*!< RD_WINDOWS_SEL */ - - struct { - __IO uint32_t PHY_SEL : 3; /*!< To fix the phy read valid issue, this is to adjust the read - data valid window to match the phy read valid by cycle level */ - } RD_SEL_b; /*!< BitSize */ - }; -} DDRC_Type; - - -/* ================================================================================ */ -/* ================ PDLOCK ================ */ -/* ================================================================================ */ - - -/** - * @brief PLL DLL LOCK (PDLOCK) - */ - -typedef struct { /*!< PDLOCK Structure */ - - union { - __I uint32_t GCLK; /*!< GCLK */ - - struct { - __I uint32_t C1R2P : 1; /*!< gclk_c1r2_pll_lock */ - __I uint32_t C1R1P : 1; /*!< gclk_c1r1_pll_lock */ - __I uint32_t C2R1P : 1; /*!< gclk_c2r1_pll_lock */ - __I uint32_t C2R2P : 1; /*!< gclk_c2r2_pll_lock */ - __I uint32_t C1R2D : 1; /*!< gclk_c1r2_dll_lock */ - __I uint32_t C1R1D : 1; /*!< gclk_c1r1_dll_lock */ - __I uint32_t C2R1D : 1; /*!< gclk_c2r1_dll_lock */ - __I uint32_t C2R2D : 1; /*!< gclk_c2r2_dll_lock */ - } GCLK_b; /*!< BitSize */ - }; -} PDLOCK_Type; - - -/* ================================================================================ */ -/* ================ PDPROT ================ */ -/* ================================================================================ */ - - -/** - * @brief PLL DLL PROTECT (PDPROT) - */ - -typedef struct { /*!< PDPROT Structure */ - - union { - __O uint32_t LOCK; /*!< LOCK */ - - struct { - __O uint32_t EN : 1; /*!< Enable the PLL DLL Lock to Protect it */ - } LOCK_b; /*!< BitSize */ - }; -} PDPROT_Type; - - -/* ================================================================================ */ -/* ================ CFG_CTRL ================ */ -/* ================================================================================ */ - - -/** - * @brief CFG_CTRL (CFG_CTRL) - */ - -typedef struct { /*!< CFG_CTRL Structure */ - __I uint32_t RESERVED0[3]; - - union { - __IO uint32_t DONE; /*!< DONE CFG */ - - struct { - __IO uint32_t CMD : 1; /*!< Write 1 indicate all chain data write over */ - __IO uint32_t STA : 1; /*!< 1= all chain config process over, chip is in user mode */ - } DONE_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1[34]; - - union { - __IO uint32_t PDLLSTR; /*!< PLL DLL RESET */ - - struct { - __IO uint32_t C1R1P : 1; /*!< C1r1_rstpll_n, low active */ - __IO uint32_t C1R2P : 1; /*!< C1r2_rstpll_n, low active */ - __IO uint32_t C2R1P : 1; /*!< C2r1_rstpll_n, low active */ - __IO uint32_t C2R2P : 1; /*!< C2r2_rstpll_n, low active */ - __IO uint32_t C1R1D : 1; /*!< C1r1_rstdll_n, low active */ - __IO uint32_t C1R2D : 1; /*!< C1r2_rstdll_n, low active */ - __IO uint32_t C2R1D : 1; /*!< C2r1_rstdll_n, low active */ - __IO uint32_t C2R2D : 1; /*!< C2r2_rstdll_n, low active */ - } PDLLSTR_b; /*!< BitSize */ - }; -} CFG_CTRL_Type; - - -/* ================================================================================ */ -/* ================ SOFT_RESET ================ */ -/* ================================================================================ */ - - -/** - * @brief SUB SOFT RESET (SOFT_RESET) - */ - -typedef struct { /*!< SOFT_RESET Structure */ - - union { - __IO uint32_t SOFTRST; /*!< SOFTRST */ - - struct { - __IO uint32_t CAN1_n : 1; /*!< soft_rst_can1_n */ - __IO uint32_t CAN0_n : 1; /*!< soft_rst_can0_n */ - __IO uint32_t I2C1_n : 1; /*!< soft_rst_i2c1_n */ - __IO uint32_t I2C0_n : 1; /*!< soft_rst_i2c0_n */ - __IO uint32_t SPI1_n : 1; /*!< soft_rst_spi1_n */ - __IO uint32_t SPI0_n : 1; /*!< soft_rst_spi0_n */ - __IO uint32_t UART1_n : 1; /*!< soft_rst_uart1_n */ - __IO uint32_t UART0_n : 1; /*!< soft_rst_uart0_n */ - __IO uint32_t RTC_n : 1; /*!< soft_rst_rtc_n */ - __IO uint32_t GPIO_n : 1; /*!< soft_rst_gpio_n */ - __IO uint32_t TIMER_n : 1; /*!< soft_rst_timer_n */ - __IO uint32_t WDT_n : 1; /*!< soft_rst_wdt_n */ - __IO uint32_t LVDS_n : 1; /*!< soft_rst_lvds_n */ - __IO uint32_t FLS_n : 1; /*!< soft_rst_fls_n */ - __IO uint32_t DMAC_AHB_n : 1; /*!< soft_rst_dmac_ahb_n */ - __IO uint32_t USB_AHB_n : 1; /*!< soft_rst_usb_ahb_n */ - __IO uint32_t ETH_AHB_n : 1; /*!< soft_rst_eth_ahb_n */ - __IO uint32_t DDRC_n : 1; /*!< soft_rst_ddrc_n */ - __IO uint32_t ARM_HCLK_n : 1; /*!< soft_rst_arm_HCLK_n */ - __IO uint32_t _48_n : 1; /*!< soft_rst_48_n */ - __IO uint32_t UTM_n : 1; /*!< soft_rst_utmi_n */ - __IO uint32_t CACHE_n : 1; /*!< soft_rst_cache_n */ - __IO uint32_t USB_n : 1; /*!< soft_rst_cache_n */ - __IO uint32_t ETH_RX_n : 1; /*!< soft_rst_eth_rx_i_n */ - __IO uint32_t ETH_TX_n : 1; /*!< soft_rst_eth_tx_i_n */ - __IO uint32_t ADC_n : 1; /*!< soft_rst_adc_n */ - __IO uint32_t EFUSE_n : 1; /*!< soft_rst_efuse_n */ - __IO uint32_t Reserved1_n: 1; /*!< Reserved11 */ - __IO uint32_t AES_n : 1; /*!< soft_rst_aes_n */ - __IO uint32_t UART2_n : 1; /*!< soft_rst_uart2_n */ - __IO uint32_t AS_n : 1; /*!< soft_rst_as_n */ - __IO uint32_t FDCD_n : 1; /*!< soft_rst_fdcd_n */ - } SOFTRST_b; /*!< BitSize */ - }; -} SOFT_RESET_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define UART0_BASE 0x41005000UL -#define UART1_BASE 0x4100C000UL -#define UART2_BASE 0x4100E000UL -#define WDG_BASE 0x41001000UL -#define TIMER0_BASE 0x41000000UL -#define TIMER1_BASE 0x41000020UL -#define TIMER2_BASE 0x41000040UL -#define TIMER3_BASE 0x41000060UL -#define SPI0_BASE 0x41004000UL -#define SPI1_BASE 0x4100B000UL -#define I2C0_BASE 0x41003000UL -#define I2C1_BASE 0x4100A000UL -#define RTC_BASE 0x41007004UL -#define GPIO_BASE 0x41002000UL -#define NOR_FLASH_BASE 0x40800000UL -#define ADC_BASE 0x41006000UL -#define EFUSE_BASE 0x41008000UL -#define CAN0_BASE 0x41009000UL -#define CAN1_BASE 0x4100D000UL -#define DMA_BASE 0x41500000UL -#define ETH_BASE 0x41200000UL -#define USB_BASE 0x41300000UL -#define GLOBAL_CTRL_BASE 0x41007010UL -#define AES_BASE 0x41600000UL -#define DDRC_BASE 0x41400000UL -#define PDLOCK_BASE 0x41007000UL -#define PDPROT_BASE 0x41007C00UL -#define CFG_CTRL_BASE 0x41700000UL -#define SOFT_RESET_BASE 0x41007400UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define UART0 ((UART0_Type *) UART0_BASE) -#define UART1 ((UART0_Type *) UART1_BASE) -#define UART2 ((UART0_Type *) UART2_BASE) -#define WDG ((WDG_Type *) WDG_BASE) -#define TIMER0 ((TIMER0_Type *) TIMER0_BASE) -#define TIMER1 ((TIMER0_Type *) TIMER1_BASE) -#define TIMER2 ((TIMER0_Type *) TIMER2_BASE) -#define TIMER3 ((TIMER0_Type *) TIMER3_BASE) -#define SPI0 ((SPI0_Type *) SPI0_BASE) -#define SPI1 ((SPI0_Type *) SPI1_BASE) -#define I2C0 ((I2C0_Type *) I2C0_BASE) -#define I2C1 ((I2C0_Type *) I2C1_BASE) -#define RTC ((RTC_Type *) RTC_BASE) -#define GPIO ((GPIO_Type *) GPIO_BASE) -#define NOR_FLASH ((NOR_FLASH_Type *) NOR_FLASH_BASE) -#define ADC ((ADC_Type *) ADC_BASE) -#define EFUSE ((EFUSE_Type *) EFUSE_BASE) -#define CAN0 ((CAN0_Type *) CAN0_BASE) -#define CAN1 ((CAN0_Type *) CAN1_BASE) -#define DMA ((DMA_Type *) DMA_BASE) -#define ETH ((ETH_Type *) ETH_BASE) -#define USB ((USB_Type *) USB_BASE) -#define GLOBAL_CTRL ((GLOBAL_CTRL_Type *) GLOBAL_CTRL_BASE) -#define AES ((AES_Type *) AES_BASE) -#define DDRC ((DDRC_Type *) DDRC_BASE) -#define PDLOCK ((PDLOCK_Type *) PDLOCK_BASE) -#define PDPROT ((PDPROT_Type *) PDPROT_BASE) -#define CFG_CTRL ((CFG_CTRL_Type *) CFG_CTRL_BASE) -#define SOFT_RESET ((SOFT_RESET_Type *) SOFT_RESET_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group CMEM7 */ -/** @} */ /* End of group (null) */ - -#ifdef __cplusplus -} -#endif - - -#endif /* CMEM7_H */ - + +/****************************************************************************************************//** + * @file cmem7.h + * + * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for + * cmem7 from . + * + * @version V1.0 + * @date 5. January 2015 + * + * @note Generated with SVDConv V2.75 + * from CMSIS SVD File 'SVDConv_CME_M7.svd' Version 1.0, + *******************************************************************************************************/ + + + +/** @addtogroup (null) + * @{ + */ + +/** @addtogroup cmem7 + * @{ + */ + +#ifndef CMEM7_H +#define CMEM7_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ---------------------- cmem7 Specific Interrupt Numbers ---------------------- */ + ETH_INT_IRQn = 0, /*!< 0 ETH_INT */ + USB_INT_IRQn = 1, /*!< 1 USB_INT */ + DMA_INT_IRQn = 2, /*!< 2 DMA_INT */ + CAN0_INT_IRQn = 3, /*!< 3 CAN0_INT */ + CAN1_INT_IRQn = 4, /*!< 4 CAN1_INT */ + FP0_INT_IRQn = 5, /*!< 5 FP0_INT */ + FP1_INT_IRQn = 6, /*!< 6 FP1_INT */ + FP2_INT_IRQn = 7, /*!< 7 FP2_INT */ + FP3_INT_IRQn = 8, /*!< 8 FP3_INT */ + FP4_INT_IRQn = 9, /*!< 9 FP4_INT */ + FP5_INT_IRQn = 10, /*!< 10 FP5_INT */ + FP6_INT_IRQn = 11, /*!< 11 FP6_INT */ + FP7_INT_IRQn = 12, /*!< 12 FP7_INT */ + FP8_INT_IRQn = 13, /*!< 13 FP8_INT */ + FP9_INT_IRQn = 14, /*!< 14 FP9_INT */ + FP10_INT_IRQn = 15, /*!< 15 FP10_INT */ + FP11_INT_IRQn = 16, /*!< 16 FP11_INT */ + FP12_INT_IRQn = 17, /*!< 17 FP12_INT */ + FP13_INT_IRQn = 18, /*!< 18 FP13_INT */ + FP14_INT_IRQn = 19, /*!< 19 FP14_INT */ + FP15_INT_IRQn = 20, /*!< 20 FP15_INT */ + UART0_INT_IRQn = 21, /*!< 21 UART0_INT */ + UART1_INT_IRQn = 22, /*!< 22 UART1_INT */ + ADC_INT_IRQn = 23, /*!< 23 ADC_INT */ + GPIO_INT_IRQn = 24, /*!< 24 GPIO_INT */ + SPI1_INT_IRQn = 25, /*!< 25 SPI1_INT */ + I2C1_INT_IRQn = 26, /*!< 26 I2C1_INT */ + SPI0_INT_IRQn = 27, /*!< 27 SPI0_INT */ + I2C0_INT_IRQn = 28, /*!< 28 I2C0_INT */ + RTC_1S_INT_IRQn = 29, /*!< 29 RTC_1S_INT */ + RTC_1MS_INT_IRQn = 30, /*!< 30 RTC_1MS_INT */ + WDG_INT_IRQn = 31, /*!< 31 WDG_INT */ + TIMER_INT_IRQn = 32, /*!< 32 TIMER_INT */ + DDRC_SW_PROC_IRQn = 33, /*!< 33 DDRC_SW_PROC */ + ETH_PMT_INT_IRQn = 34, /*!< 34 ETH_PMT_INT */ + PAD_INT_IRQn = 35, /*!< 35 PAD_INT */ + DDRC_LANE_SYNC_IRQn = 36, /*!< 36 DDRC_LANE_SYNC */ + UART2_INT_IRQn = 37 /*!< 37 UART2_INT */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */ +#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 0 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< Cortex-M3 processor and core peripherals */ +#include "system_cmem7.h" /*!< cmem7 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ UART0 ================ */ +/* ================================================================================ */ + + +/** + * @brief asynchronous serial controller 0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + __IO uint16_t BAUDRATE; /*!< baudrate Register */ + __I uint16_t RESERVED0; + __IO uint16_t TX_BUF; /*!< transmit buffer Register */ + __I uint16_t RESERVED1; + __I uint16_t RX_BUF; /*!< receive buffer Register */ + __I uint16_t RESERVED2; + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t MODE : 3; /*!< asc mode control */ + __IO uint32_t STOP : 2; /*!< number of stop bits selection */ + __IO uint32_t PARITY : 1; /*!< parity selection */ + __IO uint32_t LOOPBACK : 1; /*!< loopback mode enable bit */ + uint32_t : 1; + __IO uint32_t RX_EN : 1; /*!< receive enable bit */ + uint32_t : 1; + __IO uint32_t FIFO_EN : 1; /*!< FIFO enable bit */ + __IO uint32_t CTS : 1; /*!< Clear to send, enable signal to send */ + __IO uint32_t BAUD_MODE : 1; /*!< baudrate generation mode */ + __IO uint32_t RX_THRESHOLD: 5; /*!< receive threshold */ + __IO uint32_t RX_HALF_FULL: 5; /*!< receive fifi half full level */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< interrupt mask register */ + + struct { + __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ + __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ + __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ + __IO uint32_t PE : 1; /*!< parity error interrupt */ + __IO uint32_t FE : 1; /*!< frame error interrupt */ + __IO uint32_t OE : 1; /*!< overrun error interrupt */ + __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ + } INT_MASK_b; /*!< BitSize */ + }; + + union { + __IO uint32_t STATUS; /*!< status register */ + + struct { + __IO uint32_t RNE : 1; /*!< receiver FIFO not empty */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty */ + __IO uint32_t TOE : 1; /*!< time out when the receiver FIFO is empty */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full */ + __IO uint32_t TF : 1; /*!< transmitter FIFO is full */ + } STATUS_b; /*!< BitSize */ + }; + __IO uint8_t TIMEOUT; /*!< timeout Register */ + __I uint8_t RESERVED3[3]; + + union { + __IO uint32_t TX_RESET; /*!< transmit reset Register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } TX_RESET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RX_RESET; /*!< receive reset Register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } RX_RESET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RUN; /*!< uart enable register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } RUN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< raw interrupt before mask register */ + + struct { + __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ + __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ + __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ + __IO uint32_t PE : 1; /*!< parity error interrupt */ + __IO uint32_t FE : 1; /*!< frame error interrupt */ + __IO uint32_t OE : 1; /*!< overrun error interrupt */ + __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ + } INT_RAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_SEEN; /*!< interrupt after mask register */ + + struct { + __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ + __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ + __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ + __IO uint32_t PE : 1; /*!< parity error interrupt */ + __IO uint32_t FE : 1; /*!< frame error interrupt */ + __IO uint32_t OE : 1; /*!< overrun error interrupt */ + __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ + } INT_SEEN_b; /*!< BitSize */ + }; +} UART0_Type; + + +/* ================================================================================ */ +/* ================ WDG ================ */ +/* ================================================================================ */ + + +/** + * @brief watchdog (WDG) + */ + +typedef struct { /*!< WDG Structure */ + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t EN : 1; /*!< flag indicates if watchdog is enabled or not */ + __IO uint32_t INT_LEN : 1; /*!< watchdog report interrupt when COUNTER is 1/4 or 1/2 of LENGTH */ + } CTRL_b; /*!< BitSize */ + }; + __IO uint32_t LEN; /*!< Ticks decrease down to 25% or 50% to trigger an interrupt */ + + union { + __IO uint32_t INT_CTRL; /*!< interrupt control */ + + struct { + __IO uint32_t MASK : 1; /*!< mask register */ + __IO uint32_t TRIGGER_MODE: 1; /*!< trigger mode */ + } INT_CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STA; /*!< interrupt status register */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_STA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw register */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_RAW_b; /*!< BitSize */ + }; + __I uint32_t CNT; /*!< counter register */ +} WDG_Type; + + +/* ================================================================================ */ +/* ================ TIMER0 ================ */ +/* ================================================================================ */ + + +/** + * @brief timer 0 (TIMER0) + */ + +typedef struct { /*!< TIMER0 Structure */ + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t EN : 1; /*!< flag indicates if timer is enabled or not */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TYPE; /*!< type Register */ + + struct { + __IO uint32_t SIGNLE_SHOT: 1; /*!< indicate timer generate only one interrupt if not reload */ + } TYPE_b; /*!< BitSize */ + }; + __IO uint32_t LEN; /*!< length */ + + union { + __IO uint32_t INT_EN; /*!< interrupt enable */ + + struct { + __IO uint32_t EN_REVERSE : 1; /*!< flag indicates if timer is disable or not */ + } INT_EN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STA; /*!< interrupt status */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_STA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw register */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_RAW_b; /*!< BitSize */ + }; + __I uint32_t CNT; /*!< counter register */ +} TIMER0_Type; + + +/* ================================================================================ */ +/* ================ SPI0 ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI 0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + + union { + __I uint32_t STATUS; /*!< status Register */ + + struct { + __I uint32_t RFIFO_EMPTY: 1; /*!< receive fifo is empty */ + __I uint32_t RFIFO_FULL : 1; /*!< receive fifo is full */ + __I uint32_t RFIFO_ALMOST_EMPTY: 1; /*!< receive fifo is almost empty */ + __I uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full */ + __I uint32_t TFIFO_EMPTY: 1; /*!< transmit fifo is empty */ + __I uint32_t TFIFO_FULL : 1; /*!< transmit fifo is full */ + __I uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo is almost empty */ + __I uint32_t TFIFO_ALMOST_FULL: 1; /*!< transmit fifo almost full */ + __I uint32_t BUSY : 1; /*!< indecates if SPI is idle or busy */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t EN : 1; /*!< indicates if SPI is enabled or not */ + __IO uint32_t RX_EN : 1; /*!< indicates if SPI receiver is enabled or not */ + __IO uint32_t CLK_HIGH : 1; /*!< indicats if idle clock polarity is high level */ + __IO uint32_t NEG_EDGE : 1; /*!< 1, indicates SPI takes sample at the rise edge and transmit + data at the trailing edge. 0, conversely. */ + __IO uint32_t TX_BIT_SEQUENCE: 1; /*!< transmit bit sequence. 0 : MSB is sent first */ + __IO uint32_t RX_BIT_SEQUENCE: 1; /*!< receive bit sequence. 0: MSB is received first */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< interrupt mask Register */ + + struct { + __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ + __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ + __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ + __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ + __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ + __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ + __IO uint32_t DONE : 1; /*!< transmit done interrupt */ + } INT_MASK_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STATUS; /*!< interrupt Register */ + + struct { + __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ + __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ + __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ + __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ + __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ + __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ + __IO uint32_t DONE : 1; /*!< transmit done interrupt */ + } INT_STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw Register */ + + struct { + __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ + __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ + __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ + __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ + __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ + __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ + __IO uint32_t DONE : 1; /*!< transmit done interrupt */ + } INT_RAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t BCNT; /*!< bit length while transmitting and receiving */ + + struct { + __IO uint32_t CNT : 5; /*!< bit length while transmitting and receiving, BCNT + 1 */ + } BCNT_b; /*!< BitSize */ + }; + __IO uint8_t GAP; /*!< half cycle number between continuous data frame */ + __I uint8_t RESERVED0[3]; + __IO uint16_t DIV; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ + __I uint16_t RESERVED1; + __IO uint32_t TRANS_CNT; /*!< transmit data length, data number = TRANS_CNT + 1 */ + + union { + __O uint32_t TRANS_START; /*!< transmit startup register, write 1 to trigger transmision once */ + + struct { + __O uint32_t TX_TRIGGER : 1; /*!< write 1 to trigger transmision once */ + } TRANS_START_b; /*!< BitSize */ + }; + __IO uint32_t RW_DATA; /*!< raw data register */ +} SPI0_Type; + + +/* ================================================================================ */ +/* ================ I2C0 ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C 0 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t MODE : 1; /*!< master or slave mode */ + __IO uint32_t MASTER_ADDR_WIDTH: 1; /*!< 7- or 10-bits address as a master */ + __IO uint32_t SLAVE_ADDR_WIDTH: 1; /*!< 7- or 10-bits address width as a slave */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint16_t TAR; /*!< target address Register */ + + struct { + __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ + __IO uint16_t START_BYTE : 1; /*!< Enable start Byte for each transfer */ + } TAR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED0; + + union { + __IO uint16_t SAR; /*!< slave address Register */ + + struct { + __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ + } SAR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED1; + + union { + __IO uint32_t DATA_CMD; /*!< I2C transfer data/command entry */ + + struct { + __IO uint32_t DATA : 8; /*!< 8-bits data */ + __O uint32_t RD_CMD : 1; /*!< read command for master mode only, write 0 if slave mode */ + __O uint32_t WR_CMD : 1; /*!< write command for master mode only */ + __O uint32_t WR_RD_CMD : 1; /*!< write and read command for master mode only */ + } DATA_CMD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WRITE_READ_CNT; /*!< I2C write and read data byte counter Register */ + + struct { + __IO uint32_t RD_BYTE_CNT: 9; /*!< Decide the number of bytes read back as a master-receiver */ + uint32_t : 7; + __IO uint32_t WR_BYTE_CNT: 9; /*!< Decide the number of byte to send as a master-transmitter */ + } WRITE_READ_CNT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SCL_CNT; /*!< I2C clk pulse counter */ + + struct { + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< the SCL clock high-period count */ + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< the SCL clock low-period count */ + } SCL_CNT_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + + union { + __I uint32_t INT_STATUS; /*!< I2C interrupt sources */ + + struct { + __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ + __I uint32_t RX_OVER : 1; /*!< receiver overflow */ + __I uint32_t RX_FULL : 1; /*!< receiver is full */ + __I uint32_t TX_OVER : 1; /*!< transmit overflow */ + __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ + __I uint32_t RD_REQ : 1; /*!< read request */ + __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ + __I uint32_t RX_DONE : 1; /*!< receive done */ + __I uint32_t TX_DONE : 1; /*!< transmit done */ + __I uint32_t WR_REQ : 1; /*!< write request */ + } INT_STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< I2C interrupt mask register */ + + struct { + __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ + __I uint32_t RX_OVER : 1; /*!< receiver overflow */ + __I uint32_t RX_FULL : 1; /*!< receiver is full */ + __I uint32_t TX_OVER : 1; /*!< transmit overflow */ + __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ + __I uint32_t RD_REQ : 1; /*!< read request */ + __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ + __I uint32_t RX_DONE : 1; /*!< receive done */ + __I uint32_t TX_DONE : 1; /*!< transmit done */ + __I uint32_t WR_REQ : 1; /*!< write request */ + } INT_MASK_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3; + + union { + __IO uint32_t RX_TL; /*!< I2C receive FIFO threshold */ + + struct { + __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ + } RX_TL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TX_TL; /*!< I2C transmit FIFO threshold */ + + struct { + __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ + } TX_TL_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_ALL_INT; /*!< I2C clear all interrupt register */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear all individual interrupts */ + } CLR_ALL_INT_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RX_UNDER; /*!< I2C clear RX_UNDER interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_UNDER interrupt (bit 19) + of the I2C_STATUS register */ + } CLR_RX_UNDER_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RX_OVER; /*!< I2C clear RX_OVER interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_OVER interrupt (bit 20) of + the I2C_STATUS register */ + } CLR_RX_OVER_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_TX_OVER; /*!< I2C clear TX_OVER interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_OVER interrupt (bit 22) of + the I2C_STATUS register */ + } CLR_TX_OVER_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RD_REQ; /*!< I2C clear RD_REQ interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RD_REQ interrupt (bit 24) of + the I2C_STATUS register */ + } CLR_RD_REQ_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_TX_ABRT; /*!< I2C clear TX_ABRT interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_ABRT interrupts (bit 25 , + bit 18, bit 17, bit 16 and bit 15) of the I2C_STATUS register. */ + } CLR_TX_ABRT_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RX_DONE; /*!< I2C clear RX_DONE interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_DONE interrupt (bit 26) of + the I2C_STATUS register */ + } CLR_RX_DONE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ENABLE; /*!< I2C enable register */ + + struct { + __IO uint32_t EN : 1; /*!< enable device */ + uint32_t : 30; + __IO uint32_t RESET : 1; /*!< TX and RX FIFO are held in an erased state( flushed) and all + interrupts deserted */ + } ENABLE_b; /*!< BitSize */ + }; + + union { + __I uint32_t STATUS; /*!< I2C status register */ + + struct { + __I uint32_t BUSY : 1; /*!< I2C busy Status */ + __I uint32_t TX_FIFO_NOT_FULL: 1; /*!< transmit FIFO is not full */ + __I uint32_t TX_FIFO_EMPTY: 1; /*!< transmit FIFO is empty */ + __I uint32_t RX_FIFO_NOT_EMPTY: 1; /*!< receive FIFO is not empty */ + __I uint32_t RX_FIFO_FULL: 1; /*!< receive FIFO is full */ + __I uint32_t EN : 1; /*!< I2C is enabled */ + __I uint32_t TX_BYTE_W_ACK: 9; /*!< Number of bytes sent to slave with acknowledge during the last + write transaction as a master-transmitter only */ + __I uint32_t ABRT_ADDR_NOACK: 1; /*!< the address sent was not acknowledged by any slave as a master */ + __I uint32_t ABRT_TX_DATA_NOACK: 1; /*!< the data sent was not acknowledged by any slave as a master */ + __I uint32_t ABRT_SLAVE_FLUSH_TX_FIFO: 1; /*!< Slave has received a read command and some data exists in the + TX FIFO so the slave issues a TX_ABRT interrupt to flush old + data in TX FIFO */ + __I uint32_t ABRT_SLAVE_RD_IN_TX: 1; /*!< When the processor side responds to a slave mode request for + data to be transmitted to a remote master and user writes a + 1 in CMD (bit 8) of I2C_DATA_CMD register */ + __I uint32_t RX_UNDER : 1; /*!< receiver is underflow */ + __I uint32_t RX_OVER : 1; /*!< receiver is overflow */ + __I uint32_t RX_FULL : 1; /*!< receiver is full */ + __I uint32_t TX_OVER : 1; /*!< transmit is overflow */ + __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ + __I uint32_t RD_REQ : 1; /*!< read request is received */ + __I uint32_t TX_ABRT : 1; /*!< transmit is abort */ + __I uint32_t RX_DONE : 1; /*!< receive is done */ + __I uint32_t TX_DONE : 1; /*!< transmit is done */ + __I uint32_t WR_REQ : 1; /*!< write request is received */ + __I uint32_t MST_RD_FLAG: 1; /*!< Master is executing read command */ + __I uint32_t MST_WR_FLAG: 1; /*!< Master is executing read command */ + __I uint32_t MST_WR_RD_FLAG: 1; /*!< Master is executing write-read command */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __I uint32_t TX_FIFO_LEVEL; /*!< I2C transmit FIFO level */ + + struct { + __I uint32_t LEVEL : 5; /*!< FIFO level */ + } TX_FIFO_LEVEL_b; /*!< BitSize */ + }; + + union { + __I uint32_t RX_FIFO_LEVEL; /*!< I2C receive FIFO level */ + + struct { + __I uint32_t LEVEL : 5; /*!< FIFO level */ + } RX_FIFO_LEVEL_b; /*!< BitSize */ + }; + __I uint32_t RESERVED4; + + union { + __O uint32_t SLAVE_NACK; /*!< I2C slave send a data NACK */ + + struct { + __O uint32_t NACK : 1; /*!< data NACK */ + } SLAVE_NACK_b; /*!< BitSize */ + }; + __I uint32_t RESERVED5; + + union { + __IO uint32_t SDA_SETUP; /*!< I2C SDA setup timer */ + + struct { + __IO uint32_t TSETUP : 10; /*!< This counter defines the max value of the following constrains:THD:STA + TSU:STO,TSETUP: T / INPUT_CLK_PERIOD */ + __IO uint32_t TSU_DAT : 8; /*!< This counter defines the constrain of TSU:DAT: 250ns (or 100ns) + / INPUT_CLK_PERIOD */ + } SDA_SETUP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TSU_STA_SETUP; /*!< I2C Tsu_sta and Tbuf_free timer */ + + struct { + __IO uint32_t TBUF : 10; /*!< This counter defines the constrain of bus free interval: Tbuf, + Tbuf : Tbus_free / INPUT_CLK_PERIOD */ + __IO uint32_t TSU_STA : 10; /*!< This counter defines the constrain of Tsu:sta, Tsu:sta : Tsu:sta + / INPUT_CLK_PERIOD */ + __IO uint32_t SDA_FILTER_CNT: 4; /*!< SDA filter count */ + __IO uint32_t SDA_FILTER_EN: 1; /*!< SDA filter enable bit */ + __IO uint32_t SCL_FILTER_CNT: 4; /*!< SCL filter count */ + __IO uint32_t SCL_FILTER_EN: 1; /*!< SCL filter enable bit */ + } TSU_STA_SETUP_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_TX_DONE; /*!< I2C clear TX_DONE interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_DONE interrupt (bit 27) of + the I2C_STATUS register */ + } CLR_TX_DONE_b; /*!< BitSize */ + }; +} I2C0_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief RTC (RTC) + */ + +typedef struct { /*!< RTC Structure */ + + union { + __IO uint32_t INT_STATUS; /*!< interrupt Register */ + + struct { + __IO uint32_t SECOND : 1; /*!< 1s interrupt, write 1 clear 0 */ + __IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt, write 1 clear 0 */ + } INT_STATUS_b; /*!< BitSize */ + }; + __IO uint32_t SECOND; /*!< current seconds of system time */ + + union { + __IO uint16_t MILLSECOND; /*!< current millseconds of system time */ + + struct { + __IO uint16_t MS : 10; /*!< micro seconds */ + } MILLSECOND_b; /*!< BitSize */ + }; +} RTC_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __I uint32_t GPIO_IN; /*!< GPIO input data */ + __IO uint32_t GPIO_OUT_UNMASK; /*!< GPIO output mask Register */ + __IO uint32_t GPIO_OUT_DATA; /*!< GPIO output data register */ + __IO uint32_t GPIO_OE; /*!< GPIO output driver enable */ + __IO uint32_t GPIO_INT_MASK; /*!< GPIO input interrupt mask */ + __IO uint32_t GPIO_INT_STATUS; /*!< GPIO input interrupt status */ + __IO uint32_t GPIO_INT_RAW; /*!< GPIO input interrupt raw */ + __IO uint32_t GPIO_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ + + union { + __IO uint32_t PWM_OUT_SEL; /*!< Select gpio output from PWM */ + + struct { + __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ + __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ + __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ + __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ + } PWM_OUT_SEL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT0_LEN; /*!< Pwm channel 0 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT0_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT1_LEN; /*!< Pwm channel 1 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT1_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT2_LEN; /*!< Pwm channel 2 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT2_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT3_LEN; /*!< Pwm channel 3 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT3_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT_EN; /*!< Pwm enable */ + + struct { + __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ + __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ + __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ + __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ + } PWM_OUT_EN_b; /*!< BitSize */ + }; + __I uint32_t GPIO_H_IN; /*!< GPIO_H input data */ + __IO uint32_t GPIO_H_OUT_UNMASK; /*!< GPIO_H output unmask Register */ + __IO uint32_t GPIO_H_OUT_DATA; /*!< GPIO_H output data register */ + __IO uint32_t GPIO_H_OE; /*!< GPIO_H output driver enable */ + __IO uint32_t GPIO_H_INT_MASK; /*!< GPIO_H interrupt mask */ + __IO uint32_t GPIO_H_INT_STATUS; /*!< GPIO_H interrupt status */ + __IO uint32_t GPIO_H_INT_RAW; /*!< GPIO_H interrupt raw */ + __IO uint32_t GPIO_H_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ + __I uint32_t GPIO_N_IN; /*!< GPIO_N input data */ + __IO uint32_t GPIO_N_OUT_UNMASK; /*!< GPIO_N output unmask Register */ + __IO uint32_t GPIO_N_OUT_DATA; /*!< GPIO_N output data register */ + __IO uint32_t GPIO_N_OE; /*!< GPIO_N output driver enable */ + __IO uint32_t GPIO_N_INT_MASK; /*!< GPIO_N interrupt mask */ + __IO uint32_t GPIO_N_INT_STATUS; /*!< GPIO_N interrupt status */ + __IO uint32_t GPIO_N_INT_RAW; /*!< GPIO_N interrupt raw */ + __IO uint32_t GPIO_N_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ +} GPIO_Type; + + +/* ================================================================================ */ +/* ================ NOR_FLASH ================ */ +/* ================================================================================ */ + + +/** + * @brief NOR_FLASH (NOR_FLASH) + */ + +typedef struct { /*!< NOR_FLASH Structure */ + + union { + __IO uint32_t CTRL0; /*!< control Register 0 */ + + struct { + __IO uint32_t DIV : 8; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ + __IO uint32_t CS_REVALID_INTERVAL: 8; /*!< interval from CS invalid to valid, number of half cycle of SCK */ + __IO uint32_t RW_BYTE_CNT: 16; /*!< RW byte count (eliminate CMD, ADDRESS, DUMMY in normal state, + contains all in transparent state. 0 is unlimited */ + } CTRL0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTRL1; /*!< control Register 1 */ + + struct { + __IO uint32_t CMD : 8; /*!< operated command */ + __IO uint32_t ADDRESS : 24; /*!< RW address */ + } CTRL1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TRIGGER; /*!< trigger register */ + + struct { + __O uint32_t OP_START : 1; /*!< operation start. */ + __IO uint32_t OP_CLEAN : 1; /*!< operation clean, stop current opration and clean FIFO */ + __IO uint32_t TRSP_RD_EN : 1; /*!< if a read operation after transparent operation */ + __IO uint32_t TRSP_EN : 1; /*!< enable transparent operation */ + } TRIGGER_b; /*!< BitSize */ + }; + + union { + __I uint32_t STATUS; /*!< status register */ + + struct { + __I uint32_t BUSY : 1; /*!< reading or writting */ + __I uint32_t RD_FIFO_ALMOST_FULL: 1; /*!< read FIFO is almost full */ + __I uint32_t RD_FIFO_EMPTY: 1; /*!< read FIFO is empty */ + __I uint32_t RD_FIFO_FULL: 1; /*!< read FIFO is full */ + __I uint32_t WR_FIFO_ALMOST_EMPTY: 1; /*!< write FIFO is almost empty */ + __I uint32_t WR_FIFO_FULL: 1; /*!< write FIFO is full */ + __I uint32_t WR_FIFO_EMPTY: 1; /*!< write FIFO is empty */ + } STATUS_b; /*!< BitSize */ + }; + __IO uint32_t DATA; /*!< data register. lower bits are significant in read and higher + bits are significant in writting */ + + union { + __IO uint32_t BYPASS; /*!< bypass Register, is used for JTAG connecting FLASH directly */ + + struct { + __IO uint32_t EN : 1; /*!< enable bypass */ + } BYPASS_b; /*!< BitSize */ + }; +} NOR_FLASH_Type; + + +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ + + +/** + * @brief ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + + union { + __IO uint32_t POWERDOWN_RESET; /*!< power down and reset Register */ + + struct { + __IO uint32_t RESET_ADC2 : 1; /*!< ADC2, reset, active high */ + __IO uint32_t RESET_ADC1 : 1; /*!< ADC1, reset, active high */ + __IO uint32_t POWERDOWN_ADC2: 1; /*!< ADC2, power down, active high */ + __IO uint32_t POWERDOWN_ADC1: 1; /*!< ADC1, power down, active high */ + } POWERDOWN_RESET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG0; /*!< config Register */ + + struct { + __IO uint32_t VSEN : 3; /*!< ADC-1 VSEN Selection */ + __IO uint32_t PHASE_CTRL : 2; /*!< ADC-1 and ADC-2 CLK Phase Control */ + } CFG0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_ADC1; /*!< config ADC1 register */ + + struct { + __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ + __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ + __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ + __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ + } CFG_ADC1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_ADC2; /*!< config ADC1 register */ + + struct { + __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ + __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ + __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ + __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ + } CFG_ADC2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ADC1_FIFO_CLEAR; /*!< clear adc1 fifo data */ + + struct { + __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ + } ADC1_FIFO_CLEAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ADC2_FIFO_CLEAR; /*!< clear adc2 fifo data */ + + struct { + __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ + } ADC2_FIFO_CLEAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ALL_ADC_FIFO_CLEAR; /*!< clear adc1 and adc2 fifo data */ + + struct { + __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ + } ALL_ADC_FIFO_CLEAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< interrupt mask register */ + + struct { + __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ + __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ + __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ + __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ + __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ + __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ + } INT_MASK_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw register */ + + struct { + __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ + __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ + __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ + __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ + __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ + __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ + } INT_RAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STATUS; /*!< interrupt status register */ + + struct { + __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ + __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ + __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ + __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ + __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ + __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ + } INT_STATUS_b; /*!< BitSize */ + }; + __I uint32_t ADC1_OUT; /*!< ADC-1 Output data (Signed-Magnitude Format) */ + __I uint32_t ADC2_OUT; /*!< ADC-2 Output data (Signed-Magnitude Format) */ + __I uint32_t ADC1_OUT_OFFSET_CALIBRATION; /*!< ADC-1 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ + __I uint32_t ADC2_OUT_OFFSET_CALIBRATION; /*!< ADC-2 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ + __I uint32_t ADC1_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-1 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ + __I uint32_t ADC2_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-2 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ + __I uint32_t ADC1_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-1 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ + __I uint32_t ADC2_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-2 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ + + union { + __I uint32_t EOC; /*!< Conversion End Indicator */ + + struct { + __I uint32_t ADC2_EOC_GAIN: 1; /*!< ADC2 EOC_GAIN signal, conversion is done */ + __I uint32_t ADC2_EOC_OFF: 1; /*!< ADC2 EOC_OFF signal, conversion is done */ + __I uint32_t ADC2_EOC : 1; /*!< ADC2 EOC signal, conversion is done */ + __I uint32_t ADC1_EOC_GAIN: 1; /*!< ADC1 EOC_GAIN signal, conversion is done */ + __I uint32_t ADC1_EOC_OFF: 1; /*!< ADC1 EOC_OFF signal, conversion is done */ + __I uint32_t ADC1_EOC : 1; /*!< ADC1 EOC signal, conversion is done */ + } EOC_b; /*!< BitSize */ + }; + + union { + __I uint32_t BUSY; /*!< ADC is busy */ + + struct { + __I uint32_t ADC1_BUSY : 1; /*!< ADC1 is busy */ + __I uint32_t ADC2_BUSY : 1; /*!< ADC2 is busy */ + } BUSY_b; /*!< BitSize */ + }; + + union { + __O uint32_t ADC1_START; /*!< ADC1 startup enable */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC1_START_b; /*!< BitSize */ + }; + + union { + __O uint32_t ADC1_STOP; /*!< ADC1 stop enable */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC1_STOP_b; /*!< BitSize */ + }; + + union { + __O uint16_t ADC1_FIFO_READ; /*!< ADC1 FIFO read data */ + + struct { + __O uint16_t DATA : 12; /*!< data */ + __O uint16_t CHANNEL : 4; /*!< channel number */ + } ADC1_FIFO_READ_b; /*!< BitSize */ + }; + __I uint16_t RESERVED0; + + union { + __O uint32_t ADC2_START; /*!< ADC2 startup enable, only for single-conversion */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC2_START_b; /*!< BitSize */ + }; + + union { + __O uint32_t ADC2_STOP; /*!< ADC1 stop enable, only for single-conversion */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC2_STOP_b; /*!< BitSize */ + }; + + union { + __O uint16_t ADC2_FIFO_READ; /*!< ADC2 FIFO read data */ + + struct { + __O uint16_t DATA : 12; /*!< data */ + __O uint16_t CHANNEL : 4; /*!< channel number */ + } ADC2_FIFO_READ_b; /*!< BitSize */ + }; + __I uint16_t RESERVED1; + + union { + __O uint32_t ALL_ADC_START; /*!< all ADCs start */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ALL_ADC_START_b; /*!< BitSize */ + }; + + union { + __O uint32_t ALL_ADC_STOP; /*!< all ADCs stop */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ALL_ADC_STOP_b; /*!< BitSize */ + }; + + union { + __I uint32_t ALL_ADC_FIFO_READ; /*!< all ADCs FIFO read data */ + + struct { + __I uint32_t ADC1_DATA : 12; /*!< ADC1 data */ + __I uint32_t ADC1_CHANNEL: 4; /*!< ADC1 channel number */ + __I uint32_t ADC2_DATA : 12; /*!< ADC2 data */ + __I uint32_t ADC2_CHANNEL: 4; /*!< ADC2 channel number */ + } ALL_ADC_FIFO_READ_b; /*!< BitSize */ + }; + + union { + __I uint32_t STATUS; /*!< status register */ + + struct { + __I uint32_t ADC1_READ_EMPTY: 1; /*!< ADC1 read empty */ + __I uint32_t ADC2_READ_EMPTY: 1; /*!< ADC2 read empty */ + __I uint32_t ADC1_READ_ALMOST_EMPTY: 1; /*!< ADC1 read almost empty */ + __I uint32_t ADC2_READ_ALMOST_EMPTY: 1; /*!< ADC2 read almost empty */ + __I uint32_t ADC1_WRITE_FULL: 1; /*!< ADC1 write full */ + __I uint32_t ADC2_WRITE_FULL: 1; /*!< ADC2 write full */ + __I uint32_t ADC1_WRITE_ALMOST_FULL: 1; /*!< ADC1 write almost full */ + __I uint32_t ADC2_WRITE_ALMOST_FULL: 1; /*!< ADC2 write almost full */ + } STATUS_b; /*!< BitSize */ + }; +} ADC_Type; + + +/* ================================================================================ */ +/* ================ EFUSE ================ */ +/* ================================================================================ */ + + +/** + * @brief EFUSE (EFUSE) + */ + +typedef struct { /*!< EFUSE Structure */ + + union { + __IO uint32_t USER_CTRL_LOW; /*!< low user region control */ + + struct { + __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ + __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ + __I uint32_t BUSY : 1; /*!< reading or writting */ + __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ + __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ + __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ + __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ + __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ + } USER_CTRL_LOW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TIMING_0; /*!< timing 0 */ + + struct { + __IO uint32_t TPRS : 7; /*!< TPRS */ + __IO uint32_t TESR : 2; /*!< TESR */ + __IO uint32_t TRC : 4; /*!< TRC */ + __IO uint32_t TRPW : 3; /*!< TRPW */ + __IO uint32_t TRAH : 2; /*!< TRAH */ + __IO uint32_t TRAC : 3; /*!< TRAC */ + uint32_t : 6; + __IO uint32_t TPWPH : 5; /*!< TPWPH[6:2] */ + } TIMING_0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TIMING_1; /*!< timing 1 */ + + struct { + __IO uint32_t TPWPS : 7; /*!< TPWPS */ + __IO uint32_t TEPS : 4; /*!< TEPS */ + __IO uint32_t TPP : 11; /*!< TPP */ + __IO uint32_t TPIT : 8; /*!< TPIT */ + __IO uint32_t TPWPH : 2; /*!< TPWPS[1:0] */ + } TIMING_1_b; /*!< BitSize */ + }; + __IO uint32_t USER_DATA0_LOW; /*!< user data [31:0] */ + __IO uint32_t USER_DATA1_LOW; /*!< user data [63:32] */ + __IO uint32_t USER_DATA2_LOW; /*!< user data [95:64] */ + __IO uint32_t USER_DATA3_LOW; /*!< user data [127:96] */ + + union { + __IO uint32_t USER_DATA4_LOW; /*!< crc and lock bit */ + + struct { + __IO uint32_t LOCK : 1; /*!< write protection if true */ + uint32_t : 23; + __IO uint32_t CRC : 8; /*!< CRC */ + } USER_DATA4_LOW_b; /*!< BitSize */ + }; + __I uint32_t RESERVED0[3]; + + union { + __IO uint32_t USER_CTRL_HI; /*!< high user region control */ + + struct { + __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ + __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ + __I uint32_t BUSY : 1; /*!< reading or writting */ + __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ + __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ + __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ + __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ + __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ + } USER_CTRL_HI_b; /*!< BitSize */ + }; + __IO uint32_t USER_DATA0_HI; /*!< user data [159:128] */ + __IO uint32_t USER_DATA1_HI; /*!< user data [191:160] */ + __IO uint32_t USER_DATA2_HI; /*!< user data [223:192] */ + __IO uint32_t USER_DATA3_HI; /*!< user data [255:224] */ + + union { + __IO uint32_t USER_DATA4_HI; /*!< crc and lock bit */ + + struct { + __IO uint32_t LOCK : 1; /*!< write protection if true */ + uint32_t : 23; + __IO uint32_t CRC : 8; /*!< CRC */ + } USER_DATA4_HI_b; /*!< BitSize */ + }; +} EFUSE_Type; + + +/* ================================================================================ */ +/* ================ CAN0 ================ */ +/* ================================================================================ */ + + +/** + * @brief CAN 0 (CAN0) + */ + +typedef struct { /*!< CAN0 Structure */ + + union { + __IO uint8_t MODE; /*!< mode Register */ + + struct { + __IO uint8_t RM : 1; /*!< reset mode if 1 or operation mode */ + __IO uint8_t LOM : 1; /*!< Listen only mode */ + __IO uint8_t STM : 1; /*!< self test mode */ + __IO uint8_t AFM : 1; /*!< acceptance filter mode. Single filter if 1, dual filter if 0 */ + __IO uint8_t SM : 1; /*!< sleep mode */ + } MODE_b; /*!< BitSize */ + }; + __I uint8_t RESERVED0[3]; + + union { + __O uint8_t CMD; /*!< command Register */ + + struct { + __O uint8_t TR : 1; /*!< Set to 1 when a message is to be transmitted */ + __O uint8_t AT : 1; /*!< Set to 1 to cancel the next transmission request */ + __O uint8_t RRB : 1; /*!< Set to 1 to release the Receive Buffer */ + __O uint8_t CDO : 1; /*!< Set to 1 to clear the data overrun condition signaled by the + Data Overrun Status bit (SR.1). */ + __O uint8_t SSR : 1; /*!< Set to 1 when a message is to be transmitted and received simultaneously */ + } CMD_b; /*!< BitSize */ + }; + __I uint8_t RESERVED1[3]; + + union { + __I uint8_t STATUS; /*!< status Register */ + + struct { + __I uint8_t RBNE : 1; /*!< Receive Buffer not empty */ + __I uint8_t DO : 1; /*!< Data Overrun Status */ + __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ + __I uint8_t TC : 1; /*!< Transmission complete */ + __I uint8_t RXING : 1; /*!< receiving the data */ + __I uint8_t TXING : 1; /*!< transmitting the data */ + __I uint8_t ERR : 1; /*!< At least one of the error counters is more than Error Warning + Limit Register */ + __I uint8_t BUS_OFF : 1; /*!< in 'Bus Off' state */ + } STATUS_b; /*!< BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __I uint8_t INT; /*!< interrupt Register */ + + struct { + __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ + __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ + __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status + or Error Status bits (SR.7,SR.6) */ + __I uint8_t DO : 1; /*!< Data Overrun Status */ + __I uint8_t WAKEUP : 1; /*!< wake-up */ + __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being + in error passive state or when at least one error counter exceeds + the protocol-defined level of 127 */ + __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ + __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ + } INT_b; /*!< BitSize */ + }; + __I uint8_t RESERVED3[3]; + + union { + __IO uint8_t INT_EN; /*!< interrupt enabled Register */ + + struct { + __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ + __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ + __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status + or Error Status bits (SR.7,SR.6) */ + __I uint8_t DO : 1; /*!< Data Overrun Status */ + __I uint8_t WAKEUP : 1; /*!< wake-up */ + __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being + in error passive state or when at least one error counter exceeds + the protocol-defined level of 127 */ + __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ + __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ + } INT_EN_b; /*!< BitSize */ + }; + __I uint8_t RESERVED4[7]; + + union { + __IO uint8_t BTR0; /*!< Bus Timing 0 */ + + struct { + __IO uint8_t BRP : 6; /*!< TQ =2 x Txtal1 x (32 x BRP.5 + 16 x BRP.4 + 8 x BRP.3 + 4 x + BRP.2 + 2 x BRP.1 + BRP.0 + 1) */ + __IO uint8_t SJW : 2; /*!< the maximum number of time quanta of sync segment */ + } BTR0_b; /*!< BitSize */ + }; + __I uint8_t RESERVED5[3]; + + union { + __IO uint8_t BTR1; /*!< Bus Timing 1 */ + + struct { + __IO uint8_t TSEG1 : 4; /*!< the maximum number of time quanta of propagation and 1st phase + segment */ + __IO uint8_t TSEG2 : 3; /*!< the maximum number of time quanta of 2nd phase segment */ + __IO uint8_t SAM : 1; /*!< sample times. Sample 3 times if 1, once if 0 */ + } BTR1_b; /*!< BitSize */ + }; + __I uint8_t RESERVED6[3]; + + union { + __IO uint8_t OCR; /*!< Output Control Register */ + + struct { + __IO uint8_t MODE : 2; /*!< output control mode */ + } OCR_b; /*!< BitSize */ + }; + __I uint8_t RESERVED7[11]; + + union { + __I uint8_t ALC; /*!< Arbitration Lost Capture */ + + struct { + __I uint8_t BIT : 5; /*!< the current position of the Bit Processor when bus arbitration + lost, 1st bit (ID.28) if 0 */ + } ALC_b; /*!< BitSize */ + }; + __I uint8_t RESERVED8[3]; + + union { + __I uint8_t ECC; /*!< Error Code Capture */ + + struct { + __I uint8_t SEGMENT : 5; /*!< segment code */ + __I uint8_t DIRECTION : 1; /*!< If 1, the error occurred during reception. If 0, the error occurred + during transmission */ + __I uint8_t ERR : 2; /*!< error code */ + } ECC_b; /*!< BitSize */ + }; + __I uint8_t RESERVED9[3]; + __IO uint8_t EWLR; /*!< Error Warning Limit */ + __I uint8_t RESERVED10[3]; + __IO uint8_t RXERR; /*!< Receive Error Counter */ + __I uint8_t RESERVED11[3]; + __IO uint8_t TXERR; /*!< Transmit Error Counter */ + __I uint8_t RESERVED12[3]; + + union { + __IO uint8_t FI_OR_ACR0; /*!< Transmit Frame Information if writting or Receive Frame Information + if reading, ACR[0] if reset mode */ + + struct { + __IO uint8_t DLC : 4; /*!< byte number in the data */ + uint8_t : 2; + __IO uint8_t RTR : 1; /*!< 1 indicates a remote frame; 0 indicates a data frame */ + __IO uint8_t FF : 1; /*!< 1 selects Extended Frame Format (EFF); 0 selects Standard Frame + Format (SFF) */ + } FI_OR_ACR0_b; /*!< BitSize */ + }; + __I uint8_t RESERVED13[3]; + __IO uint8_t DI0_OR_ACR1; /*!< Transmit data Information if writting or Receive data Information + if reading, ACR[1] if reset mode */ + __I uint8_t RESERVED14[3]; + __IO uint8_t DI1_OR_ACR2; /*!< Transmit data Information if writting or Receive data Information + if reading, ACR[2] if reset mode */ + __I uint8_t RESERVED15[3]; + __IO uint8_t DI2_OR_ACR3; /*!< Transmit data Information if writting or Receive data Information + if reading, ACR[3] if reset mode */ + __I uint8_t RESERVED16[3]; + __IO uint8_t DI3_OR_AMR0; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[0] if reset mode */ + __I uint8_t RESERVED17[3]; + __IO uint8_t DI4_OR_AMR1; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[1] if reset mode */ + __I uint8_t RESERVED18[3]; + __IO uint8_t DI5_OR_AMR2; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[2] if reset mode */ + __I uint8_t RESERVED19[3]; + __IO uint8_t DI6_OR_AMR3; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[3] if reset mode */ + __I uint8_t RESERVED20[3]; + __IO uint8_t DI7; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED21[3]; + __IO uint8_t DI8; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED22[3]; + __IO uint8_t DI9; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED23[3]; + __IO uint8_t DI10; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED24[3]; + __IO uint8_t DI11; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED25[3]; + __IO uint8_t RMC; /*!< Receive Message Counter */ + __I uint8_t RESERVED26[7]; + + union { + __IO uint8_t CDR; /*!< Clock Divider Register */ + + struct { + __IO uint8_t DIVIDER : 3; /*!< divider of XTAL1 */ + __IO uint8_t OFF : 1; /*!< disable XTAL1 */ + } CDR_b; /*!< BitSize */ + }; +} CAN0_Type; + + +/* ================================================================================ */ +/* ================ DMA ================ */ +/* ================================================================================ */ + + +/** + * @brief DMA (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IO uint32_t SAR0; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED0; + __IO uint32_t DAR0; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED1; + + union { + __IO uint32_t LLP0; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + + union { + __IO uint32_t CTL_LOW0; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI0; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI0_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT0; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED3; + __IO uint32_t DSTAT0; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED4; + __IO uint32_t SSTATAR0; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED5; + __IO uint32_t DSTATAR0; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED6; + + union { + __IO uint32_t CFG_LOW0; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI0; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR0; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED7; + + union { + __IO uint32_t DSR0; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED8; + __IO uint32_t SAR1; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED9; + __IO uint32_t DAR1; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED10; + + union { + __IO uint32_t LLP1; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED11; + + union { + __IO uint32_t CTL_LOW1; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI1; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI1_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT1; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED12; + __IO uint32_t DSTAT1; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED13; + __IO uint32_t SSTATAR1; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED14; + __IO uint32_t DSTATAR1; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED15; + + union { + __IO uint32_t CFG_LOW1; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI1; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR1; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED16; + + union { + __IO uint32_t DSR1; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED17; + __IO uint32_t SAR2; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED18; + __IO uint32_t DAR2; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED19; + + union { + __IO uint32_t LLP2; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED20; + + union { + __IO uint32_t CTL_LOW2; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI2; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI2_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT2; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED21; + __IO uint32_t DSTAT2; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED22; + __IO uint32_t SSTATAR2; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED23; + __IO uint32_t DSTATAR2; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED24; + + union { + __IO uint32_t CFG_LOW2; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI2; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR2; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED25; + + union { + __IO uint32_t DSR2; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED26; + __IO uint32_t SAR3; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED27; + __IO uint32_t DAR3; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED28; + + union { + __IO uint32_t LLP3; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED29; + + union { + __IO uint32_t CTL_LOW3; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI3; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI3_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT3; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED30; + __IO uint32_t DSTAT3; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED31; + __IO uint32_t SSTATAR3; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED32; + __IO uint32_t DSTATAR3; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED33; + + union { + __IO uint32_t CFG_LOW3; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI3; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR3; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED34; + + union { + __IO uint32_t DSR3; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED35; + __IO uint32_t SAR4; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED36; + __IO uint32_t DAR4; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED37; + + union { + __IO uint32_t LLP4; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED38; + + union { + __IO uint32_t CTL_LOW4; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI4; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI4_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT4; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED39; + __IO uint32_t DSTAT4; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED40; + __IO uint32_t SSTATAR4; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED41; + __IO uint32_t DSTATAR4; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED42; + + union { + __IO uint32_t CFG_LOW4; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI4; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR4; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED43; + + union { + __IO uint32_t DSR4; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED44; + __IO uint32_t SAR5; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED45; + __IO uint32_t DAR5; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED46; + + union { + __IO uint32_t LLP5; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED47; + + union { + __IO uint32_t CTL_LOW5; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI5; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI5_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT5; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED48; + __IO uint32_t DSTAT5; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED49; + __IO uint32_t SSTATAR5; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED50; + __IO uint32_t DSTATAR5; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED51; + + union { + __IO uint32_t CFG_LOW5; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI5; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR5; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED52; + + union { + __IO uint32_t DSR5; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED53; + __IO uint32_t SAR6; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED54; + __IO uint32_t DAR6; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED55; + + union { + __IO uint32_t LLP6; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED56; + + union { + __IO uint32_t CTL_LOW6; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI6; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI6_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT6; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED57; + __IO uint32_t DSTAT6; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED58; + __IO uint32_t SSTATAR6; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED59; + __IO uint32_t DSTATAR6; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED60; + + union { + __IO uint32_t CFG_LOW6; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI6; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR6; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED61; + + union { + __IO uint32_t DSR6; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED62; + __IO uint32_t SAR7; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED63; + __IO uint32_t DAR7; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED64; + + union { + __IO uint32_t LLP7; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED65; + + union { + __IO uint32_t CTL_LOW7; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI7; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI7_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT7; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED66; + __IO uint32_t DSTAT7; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED67; + __IO uint32_t SSTATAR7; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED68; + __IO uint32_t DSTATAR7; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED69; + + union { + __IO uint32_t CFG_LOW7; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI7; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR7; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED70; + + union { + __IO uint32_t DSR7; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED71[11]; + __I uint8_t INT_TFR; /*!< DMA Transfer Complete */ + __I uint8_t RESERVED72[7]; + __I uint8_t INT_BLOCK; /*!< Block Transfer Complete */ + __I uint8_t RESERVED73[7]; + __I uint8_t INT_SRC_TRAN; /*!< Source Transaction Complete */ + __I uint8_t RESERVED74[7]; + __I uint8_t INT_DST_TRAN; /*!< Destination Transaction Complete */ + __I uint8_t RESERVED75[7]; + __I uint8_t INT_ERR; /*!< Error */ + __I uint8_t RESERVED76[7]; + + union { + __IO uint16_t INT_EN_TFR; /*!< DMA Transfer Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_TFR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED77[3]; + + union { + __IO uint16_t INT_EN_BLOCK; /*!< Block Transfer Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_BLOCK_b; /*!< BitSize */ + }; + __I uint16_t RESERVED78[3]; + + union { + __IO uint16_t INT_EN_SRC_TRAN; /*!< Source Transaction Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_SRC_TRAN_b; /*!< BitSize */ + }; + __I uint16_t RESERVED79[3]; + + union { + __IO uint16_t INT_EN_DST_TRAN; /*!< Destination Transaction Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_DST_TRAN_b; /*!< BitSize */ + }; + __I uint16_t RESERVED80[3]; + + union { + __IO uint16_t INT_EN_ERR; /*!< Error */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_ERR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED81[3]; + __O uint8_t INT_CLEAR_TFR; /*!< DMA Transfer Complete */ + __I uint8_t RESERVED82[7]; + __O uint8_t INT_CLEAR_BLOCK; /*!< Block Transfer Complete */ + __I uint8_t RESERVED83[7]; + __O uint8_t INT_CLEAR_SRC_TRAN; /*!< Source Transaction Complete */ + __I uint8_t RESERVED84[7]; + __O uint8_t INT_CLEAR_DST_TRAN; /*!< Destination Transaction Complete */ + __I uint8_t RESERVED85[7]; + __O uint8_t INT_CLEAR_ERR; /*!< Error */ + __I uint8_t RESERVED86[63]; + + union { + __IO uint32_t DMA_EN; /*!< DW_ahb_dmac Configuration Register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } DMA_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED87; + + union { + __IO uint32_t CH_EN; /*!< DW_ahb_dmac Channel Enable Register */ + + struct { + __IO uint32_t EN : 8; /*!< enable */ + __IO uint32_t WE : 8; /*!< enable write enable */ + } CH_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED88[10]; + + union { + __I uint32_t DMA_COMP_PARAMS_6_HI; /*!< Component Parameters for channel 7 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_6_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_5_LOW; /*!< Component Parameters for channel 6 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_5_LOW_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_5_HI; /*!< Component Parameters for channel 5 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_5_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_4_LOW; /*!< Component Parameters for channel 4 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_4_LOW_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_4_HI; /*!< Component Parameters for channel 3 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_4_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_3_LOW; /*!< Component Parameters for channel 2 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_3_LOW_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_3_HI; /*!< Component Parameters for channel 1 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_3_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_2_LOW; /*!< Component Parameters for channel 0 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_2_LOW_b; /*!< BitSize */ + }; + __I uint32_t RESERVED89; + + union { + __I uint32_t DMA_COMP_PARAMS_1_LOW; /*!< Maximum block size for channel */ + + struct { + __I uint32_t CH0_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 0. */ + __I uint32_t CH1_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 1 */ + __I uint32_t CH2_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 2 */ + __I uint32_t CH3_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 3 */ + __I uint32_t CH4_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 4 */ + __I uint32_t CH5_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 5 */ + __I uint32_t CH6_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 6 */ + __I uint32_t CH7_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 7 */ + } DMA_COMP_PARAMS_1_LOW_b; /*!< BitSize */ + }; +} DMA_Type; + + +/* ================================================================================ */ +/* ================ ETH ================ */ +/* ================================================================================ */ + + +/** + * @brief ETH (ETH) + */ + +typedef struct { /*!< ETH Structure */ + + union { + __IO uint32_t CONFIG; /*!< MAC Configuration Register */ + + struct { + __IO uint32_t PRELEN : 2; /*!< Preamble Length for Transmit frames */ + __IO uint32_t RX_EN : 1; /*!< Receiver Enable */ + __IO uint32_t TX_EN : 1; /*!< Transmitter Enable */ + __IO uint32_t DC_EN : 1; /*!< Deferral Check Enable */ + uint32_t : 2; + __IO uint32_t ACS : 1; /*!< Automatic Pad or CRC Stripping */ + __IO uint32_t LUD : 1; /*!< Link Up or Down */ + uint32_t : 1; + __IO uint32_t IPC : 1; /*!< Checksum Offload */ + __IO uint32_t DM : 1; /*!< Duplex Mode */ + __IO uint32_t LM : 1; /*!< Loopback Mode */ + uint32_t : 1; + __IO uint32_t FES : 1; /*!< Speed in XMII interface */ + __IO uint32_t PS : 1; /*!< the Ethernet line speed */ + uint32_t : 4; + __IO uint32_t JE : 1; /*!< Jumbo enable */ + uint32_t : 1; + __IO uint32_t JD : 1; /*!< if 0, the MAC cuts off the transmitter if more than 2,048 bytes + of data (10,240 if JE is set high) */ + __IO uint32_t WD : 1; /*!< Watchdog Disable */ + __IO uint32_t TC : 1; /*!< If 1, this bit enables the transmission of duplex mode, link + speed, and link up or down information to the PHY */ + __IO uint32_t CST : 1; /*!< CRC Stripping for Type Frames */ + uint32_t : 1; + __IO uint32_t TWOKPE : 1; /*!< If 0, 1518 bytes is considered as a giant frame, 1 is 2000 bytes. */ + __IO uint32_t SARC : 3; /*!< Source Address Insertion or Replacement Control */ + } CONFIG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t FF; /*!< MAC Frame Filter */ + + struct { + __IO uint32_t PR : 1; /*!< Receive all frames in spite of source and destination address */ + __IO uint32_t HUC : 1; /*!< if 1, don't compare DA field in destination address filtering + of unicast frames with DA register */ + __IO uint32_t HMC : 1; /*!< if 1, don't compare DA field in destination address filtering + of multicast frames with DA register */ + __IO uint32_t DAIF : 1; /*!< if set, the Address Check block operates in inverse filtering + mode for the DA address comparison */ + __IO uint32_t PM : 1; /*!< Pass All Multicast */ + __IO uint32_t DBF : 1; /*!< Disable Broadcast Frames */ + __IO uint32_t PCF : 2; /*!< Pass Control Frames */ + __IO uint32_t SAIF : 1; /*!< If set, the frames whose SA matches the SA registers are marked + as failing the SA Address filter */ + __IO uint32_t SAF : 1; /*!< Source Address Filter Enable */ + __IO uint32_t HPF : 1; /*!< Hash or Perfect Filter */ + uint32_t : 5; + __IO uint32_t VTFE : 1; /*!< VLAN Tag Filter Enable */ + uint32_t : 3; + __IO uint32_t IPFE : 1; /*!< Layer 3 and Layer 4 Filter Enable */ + __IO uint32_t DNTU : 1; /*!< Drop non-TCP/UDP over IP Frames */ + uint32_t : 9; + __IO uint32_t RA : 1; /*!< Receive all */ + } FF_b; /*!< BitSize */ + }; + __IO uint32_t HTH; /*!< Hash Table High Register */ + __IO uint32_t HTL; /*!< Hash Table Low Register */ + + union { + __IO uint32_t GMII_ADDR; /*!< GMII Address Register */ + + struct { + __IO uint32_t BUSY : 1; /*!< GMII Busy */ + __IO uint32_t GW : 1; /*!< GMII write or read */ + __IO uint32_t CR : 4; /*!< CSR Clock Range */ + __IO uint32_t GR : 5; /*!< These bits select the desired GMII register in the selected + PHY device */ + __IO uint32_t PA : 5; /*!< This field indicates which of the 32 possible PHY devices are + being accessed */ + } GMII_ADDR_b; /*!< BitSize */ + }; + __IO uint32_t GMII_DATA; /*!< GMII Data Register */ + + union { + __IO uint32_t FC; /*!< Flow Control Register */ + + struct { + __IO uint32_t FCB : 1; /*!< This bit initiates a Pause frame in the full-duplex mode */ + __IO uint32_t TFE : 1; /*!< MAC enables the flow control operation to transmit Pause frames */ + __IO uint32_t RFE : 1; /*!< MAC enables the flow control operation to receive Pause frames */ + __IO uint32_t UP : 1; /*!< MAC can detect Pause frames with unicast address of the station */ + } FC_b; /*!< BitSize */ + }; + + union { + __IO uint32_t VLAN_TAG; /*!< VLAN Tag Register */ + + struct { + __IO uint32_t VL : 16; /*!< VLAN Tag Identifier for Receive Frames */ + __IO uint32_t ETV : 1; /*!< Enable 12-Bit VLAN Tag Comparison */ + __IO uint32_t VTIM : 1; /*!< If set, The frames that do not have matching VLAN Tag are marked + as matched */ + __IO uint32_t ESVL : 1; /*!< If set, consider the S-VLAN (Type = 0x88A8) frames as valid + VLAN tagged frames */ + __IO uint32_t VTHM : 1; /*!< When set, the most significant four bits of the VLAN tag's CRC + are used to index the content */ + } VLAN_TAG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED0[2]; + __IO uint32_t RWUFFR; /*!< Remote Wake-Up Frame Filter Register */ + + union { + __IO uint32_t PMTCSR; /*!< PMT Control and Status Register */ + + struct { + __IO uint32_t PWRDWN : 1; /*!< Power Down */ + __IO uint32_t MGKPKTEN : 1; /*!< Magic Packet Enable */ + __IO uint32_t RWKPKTEN : 1; /*!< Remote Wake-Up Frame Enable */ + uint32_t : 2; + __IO uint32_t MGKPRCVD : 1; /*!< the power management event is generated because of the reception + of a magic packet */ + __IO uint32_t RWKPRCVD : 1; /*!< When set, this bit indicates the power management event is generated + because of the reception of a remote wake-up frame */ + uint32_t : 2; + __IO uint32_t GLBLUCAST : 1; /*!< When set, enables any unicast packet filtered by the MAC (DAF)address + recognition to be a remote wake-up frame. */ + uint32_t : 14; + __IO uint32_t RWKPTR : 3; /*!< Remote Wake-up FIFO Pointer */ + uint32_t : 4; + __IO uint32_t RWKFILTRST : 1; /*!< Remote Wake-Up Frame Filter Register Pointer Reset. */ + } PMTCSR_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[2]; + __IO uint32_t MACISR; /*!< Interrupt Status Register */ + __IO uint32_t MACIMR; /*!< Interrupt Mask Register */ + __IO uint16_t ADDR0_HIGH; /*!< MAC Address0 High Register */ + __I uint16_t RESERVED2; + __IO uint32_t ADDR0_LOW; /*!< MAC Address0 LOW Register */ + + union { + __IO uint32_t ADDR1_HIGH; /*!< MAC Address0 High Register */ + + struct { + __IO uint32_t ADDR : 16; /*!< MAC Address1 [47:32] */ + uint32_t : 14; + __IO uint32_t SA : 1; /*!< MAC address1 is source or destination address compared with + received frame */ + __IO uint32_t AE : 1; /*!< the address filter module uses the MAC address1 for filtering */ + } ADDR1_HIGH_b; /*!< BitSize */ + }; + __IO uint32_t ADDR1_LOW; /*!< MAC Address1 LOW Register */ + __I uint32_t RESERVED3[44]; + + union { + __IO uint32_t MMCCR; /*!< MMC Control Register */ + + struct { + __IO uint32_t CNTRST : 1; /*!< Counters Reset */ + __IO uint32_t CNTSTOPRO : 1; /*!< Counter Stop Rollover */ + __IO uint32_t RSTONRD : 1; /*!< Reset on Read */ + __IO uint32_t CNTFREEZ : 1; /*!< MMC Counter Freeze */ + __IO uint32_t CNTPRST : 1; /*!< Counters Preset */ + __IO uint32_t CNTPRSTLVL : 1; /*!< Counters Preset */ + uint32_t : 2; + __IO uint32_t UCDBC : 1; /*!< Update MMC Counters for Dropped Broadcast Frames */ + } MMCCR_b; /*!< BitSize */ + }; + __IO uint32_t MMCRIR; /*!< MMC Receive Interrupt Register */ + __IO uint32_t MMCTIR; /*!< MMC Transmit Interrupt Register */ + __IO uint32_t MMCRIMR; /*!< MMC Receive interrupt mask */ + __IO uint32_t MMCTIMR; /*!< MMC Transmit Interrupt Mask */ + __I uint32_t RESERVED4[59]; + __IO uint32_t MMCIRCOIM; /*!< MMC IPC Receive Checksum Offload Interrupt Mask */ + __I uint32_t RESERVED5[319]; + + union { + __IO uint32_t PTPTSCR; /*!< Timestamp Control Register */ + + struct { + __IO uint32_t TSENA : 1; /*!< Timestamp Enable */ + __IO uint32_t TSCFUPDT : 1; /*!< Timestamp Fine or Coarse Update */ + __IO uint32_t TSINIT : 1; /*!< Timestamp Initialize */ + __IO uint32_t TSUPDT : 1; /*!< Timestamp Update */ + __IO uint32_t TSTRIG : 1; /*!< Timestamp Interrupt Trigger Enable */ + __IO uint32_t TSADDREG : 1; /*!< Addend Reg Update */ + } PTPTSCR_b; /*!< BitSize */ + }; + __IO uint32_t PTPSSIR; /*!< Sub-Second Increment Register */ + __IO uint32_t PTPTSHR; /*!< System Time Seconds Register */ + __IO uint32_t PTPTSLR; /*!< System Time Nanoseconds Register */ + __IO uint32_t PTPTSHUR; /*!< System Time Seconds Update Register */ + __IO uint32_t PTPTSLUR; /*!< System Time Nanoseconds Update Register */ + __IO uint32_t PTPTSAR; /*!< Timestamp Addend Register */ + __IO uint32_t PTPTTHR; /*!< Target Time Seconds Register */ + __IO uint32_t PTPTTLR; /*!< Target Time Nanoseconds Register */ + __I uint32_t RESERVED6[567]; + + union { + __IO uint32_t BUS_MODE; /*!< Flow Control Register */ + + struct { + __IO uint32_t SWR : 1; /*!< Software Reset */ + __IO uint32_t DA : 1; /*!< This bit specifies the arbitration scheme between the transmit + and receive paths of Channel */ + __IO uint32_t DSL : 5; /*!< the byte number of bus width to skip between two unchained descriptors */ + __IO uint32_t ATDS : 1; /*!< When set, the size of the alternate descriptor increases to + 32 bytes */ + __IO uint32_t PBL : 6; /*!< These bits indicate the maximum number of beats to be transferred + in one DMA transaction */ + __IO uint32_t PR : 2; /*!< The Priority Ratio is (PR + 1) : 1 */ + __IO uint32_t FB : 1; /*!< performs fixed burst transfers or not */ + __IO uint32_t RPBL : 6; /*!< This field indicates the maximum number of beats to be transferred + in one Rx DMA transaction */ + __IO uint32_t USP : 1; /*!< If set, RPBL is same as RPBL definition */ + __IO uint32_t PBLx8 : 1; /*!< If set, all PBLs multiplies 8 */ + __IO uint32_t AAL : 1; /*!< If set, all bursts aligned to the start address LS bits */ + __IO uint32_t MB : 1; /*!< When this bit is set high and the FB bit is low, the AHB master + interface starts all bursts of length more than 16 with INCR */ + __IO uint32_t TXPR : 1; /*!< When set, the transmit DMA has higher priority than the receive + DMA */ + __IO uint32_t PRWG : 2; /*!< The Priority weight is (PRWG + 1) : 1 */ + uint32_t : 1; + __IO uint32_t RIB : 1; /*!< If set, rebuilds the pending beats of any burst transfer initiated + with INCRx */ + } BUS_MODE_b; /*!< BitSize */ + }; + __IO uint32_t TPD; /*!< Transmit Poll Demand */ + __IO uint32_t RPD; /*!< Receive Poll Demand */ + __IO uint32_t RDESLA; /*!< Receive Descriptor List Address */ + __IO uint32_t TDESLA; /*!< Transmit Descriptor List Address */ + + union { + __IO uint32_t STATUS; /*!< Status Register */ + + struct { + __IO uint32_t TI : 1; /*!< This bit indicates that the frame transmission is complete */ + __IO uint32_t TPS : 1; /*!< Transmit Process Stopped */ + __IO uint32_t TU : 1; /*!< the host owns the Next Descriptor in the Transmit List and the + DMA cannot acquire it. */ + __IO uint32_t TJT : 1; /*!< Transmit Jabber Timeout */ + __IO uint32_t OVF : 1; /*!< Receive Overflow */ + __IO uint32_t UNF : 1; /*!< Transmit Underflow */ + __IO uint32_t RI : 1; /*!< the frame reception is complete */ + __IO uint32_t RU : 1; /*!< Receive Buffer Unavailable */ + __IO uint32_t RPS : 1; /*!< Receive Process Stopped */ + __IO uint32_t RWT : 1; /*!< Receive Watchdog Timeout */ + __IO uint32_t ETI : 1; /*!< the frame to be transmitted is fully transferred to the MTL + Transmit FIFO */ + uint32_t : 2; + __IO uint32_t FBI : 1; /*!< a bus error occurred, as described in EB. */ + __IO uint32_t ERI : 1; /*!< the DMA filled the first data buffer of the packet */ + __IO uint32_t AIS : 1; /*!< Abnormal Interrupt Summary, must be cleared by writting */ + __IO uint32_t NIS : 1; /*!< Normal Interrupt Summary, must be cleared by writting */ + __I uint32_t RS : 3; /*!< Receive DMA FSM state */ + __I uint32_t TS : 3; /*!< Transmit DMA FSM state */ + __I uint32_t EB : 3; /*!< Error bit */ + __I uint32_t GLI : 1; /*!< GMAC Line Interface Interrupt */ + __I uint32_t GMI : 1; /*!< GMAC MMC Interrupt */ + __I uint32_t GPI : 1; /*!< GMAC PMT Interrupt */ + __I uint32_t TTI : 1; /*!< Timestamp Trigger Interrupt */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t OPERATION; /*!< Operation Mode Register */ + + struct { + uint32_t : 1; + __IO uint32_t SR : 1; /*!< Start or Stop Receive */ + __IO uint32_t OSF : 1; /*!< Operate on Second Frame */ + __IO uint32_t RT : 2; /*!< Receive Threshold Control */ + __IO uint32_t DGF : 1; /*!< Drop Giant Frames */ + __IO uint32_t FUF : 1; /*!< Forward Undersized Good Frames */ + __IO uint32_t FEF : 1; /*!< Forward Error Frames */ + uint32_t : 5; + __IO uint32_t ST : 1; /*!< Start or Stop Transmission Command */ + __IO uint32_t TT : 3; /*!< Transmit Threshold Control */ + uint32_t : 3; + __IO uint32_t FTF : 1; /*!< Flush Transmit FIFO */ + __IO uint32_t TSF : 1; /*!< If set, transmission starts when a full frame resides in Transmit + FIFO */ + uint32_t : 2; + __IO uint32_t DFF : 1; /*!< Disable Flushing of Received Frames */ + __IO uint32_t RSF : 1; /*!< If set, the MTL reads a frame from the Rx FIFO while the complete + frame has been written to it, */ + } OPERATION_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_EN; /*!< Interrupt Enable Register */ + + struct { + __IO uint32_t TIE : 1; /*!< Transmit Interrupt Enable */ + __IO uint32_t TSE : 1; /*!< Transmit Stopped Enable */ + __IO uint32_t TUE : 1; /*!< Transmit Buffer Unavailable Enable */ + __IO uint32_t TJE : 1; /*!< Transmit Jabber Timeout Enable */ + __IO uint32_t OVE : 1; /*!< Overflow Interrupt Enable */ + __IO uint32_t UNE : 1; /*!< Underflow Interrupt Enable */ + __IO uint32_t RIE : 1; /*!< Receive Interrupt Enable */ + __IO uint32_t RUE : 1; /*!< Receive Buffer Unavailable Enable */ + __IO uint32_t RSE : 1; /*!< Receive Stopped Enable */ + __IO uint32_t RWE : 1; /*!< Receive Watchdog Timeout Enable */ + __IO uint32_t ETE : 1; /*!< Early Transmit Interrupt Enable */ + uint32_t : 2; + __IO uint32_t FBE : 1; /*!< Fatal Bus Error Enable */ + __IO uint32_t ERE : 1; /*!< Early Receive Interrupt Enable */ + __IO uint32_t AIE : 1; /*!< Abnormal Interrupt Summary Enable */ + __IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */ + } INT_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED7[3]; + + union { + __IO uint32_t AHB_STATUS; /*!< AHB Status Register */ + + struct { + __IO uint32_t BUSY : 1; /*!< If set, it indicates that the AHB master interface FSMs are + in the non-idle state */ + } AHB_STATUS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED8[6]; + __I uint32_t CURTDESAPTR; /*!< Current Host Transmit Descriptor Register */ + __I uint32_t CURRDESAPTR; /*!< Current Host Receive Descriptor Register */ + __I uint32_t CURTBUFAPTR; /*!< Current Host Transmit Buffer Address Register */ + __I uint32_t CURRBUFAPTR; /*!< Current Host Receive Buffer Address Register */ +} ETH_Type; + + +/* ================================================================================ */ +/* ================ USB ================ */ +/* ================================================================================ */ + + +/** + * @brief USB (USB) + */ + +typedef struct { /*!< USB Structure */ + + union { + __IO uint32_t GOTGCTL; /*!< Control and Status register */ + + struct { + __I uint32_t SES_REQ_SCS: 1; /*!< set when a session request initiation is successful as a device */ + __IO uint32_t SES_SEQ : 1; /*!< set to initiate a session request on the USB as a device */ + __IO uint32_t VB_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using + the GOTGCTL.VbvalidOvVal as a host */ + __IO uint32_t VB_VALID_OV_VAL: 1; /*!< set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn + is set as a host */ + __IO uint32_t A_VALID_OV_EN: 1; /*!< enable/disable the software to override the Avalid signal using + the GOTGCTL.AvalidOvVal as a host */ + __IO uint32_t A_VALID_OV_VAL: 1; /*!< set Override value for Avalid signal when GOTGCTL.AvalidOvEn + is set as a host */ + __IO uint32_t B_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using + the GOTGCTL.BvalidOvVal as a device. */ + __IO uint32_t B_VALID_OV_VAL: 1; /*!< set Override value for Bvalid signal when GOTGCTL.BvalidOvEn + is set as a device. */ + __I uint32_t HST_NEG_SCS: 1; /*!< sets when host negotiation is successful as a device. */ + __IO uint32_t HNP_REQ : 1; /*!< sets this bit to initiate an HNP request to the connected USB + host as a device */ + __IO uint32_t HST_SET_HNP_EN: 1; /*!< Host Set HNP Enable as a host */ + __IO uint32_t DEV_HNP_EN : 1; /*!< Device HNP Enabled as a device */ + uint32_t : 4; + __I uint32_t CON_ID_STS : 1; /*!< Connector ID Status */ + __I uint32_t DBNC_TIME : 1; /*!< the debounce time of a detected connection as a host */ + __I uint32_t A_SES_VLD : 1; /*!< A-Session Valid as a host */ + __I uint32_t B_SES_VLD : 1; /*!< B-Session Valid as a host */ + __IO uint32_t OTG_VER : 1; /*!< If 0, OTG Version 1.3. If 1, OTG Version 2.0. */ + } GOTGCTL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GOTGINT; /*!< OTG interrupt Register */ + + struct { + uint32_t : 2; + __IO uint32_t SES_END_DET: 1; /*!< Set when the utmiotg_bvalid signal is deasserted */ + uint32_t : 5; + __IO uint32_t SES_REQ_SUC_STS_CHNG: 1; /*!< Session Request Success Status Change */ + __IO uint32_t HST_NEG_SUC_STS_CHNG: 1; /*!< Host Negotiation Success Status Change */ + uint32_t : 7; + __IO uint32_t HST_NEG_DET: 1; /*!< if set, detects a host negotiation request on the USB */ + __IO uint32_t A_DEV_TOUT_CHG: 1; /*!< A-device has timed out while waiting for the B-device to connect */ + __IO uint32_t DBNCE_DONE : 1; /*!< debounce is completed after the device connect as a host */ + } GOTGINT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GAHBCFG; /*!< AHB Configuration Register */ + + struct { + __IO uint32_t GLBL_INTR_EN: 1; /*!< Global Interrupt Enable */ + __IO uint32_t BST_LEN : 4; /*!< Burst Length/Type */ + __IO uint32_t DMA_EN : 1; /*!< DMA enable */ + uint32_t : 15; + __IO uint32_t REMOTE_MEM_SUPP: 1; /*!< enable the functionality to wait for the system DMA Done Signal + for the DMA Write Transfers */ + __IO uint32_t NOTIFY_ALL_DMA_WRITE: 1; /*!< enable the System DMA Done functionality for all the DMA write + Transactions corresponding to the Channel/Endpoint */ + __IO uint32_t AHB_SINGLE : 1; /*!< supports Single transfers for the remaining data in a transfer */ + } GAHBCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GUSBCFG; /*!< USB Configuration Register */ + + struct { + uint32_t : 3; + __IO uint32_t PHY_IF : 1; /*!< PHY Interface */ + __IO uint32_t ULPI_UTMI_SEL: 1; /*!< 1, ULPI. 0, UTMI+ */ + __IO uint32_t FS_IF : 1; /*!< 1, 3-pin bidirectional. 0, 6-pin unidirectional */ + __IO uint32_t PHY_SEL : 1; /*!< 0, USB 2.0 High-Speed PHY. 1, USB 1.1 full-speed serial transceiver */ + __IO uint32_t DDR_SEL : 1; /*!< 0, Single Data Rate ULPI Interface, with 8-bit-wide data bus. + 1, Double Data Rate ULPI Interface, with 4-bit-wide data bus */ + __IO uint32_t SRP_CAP : 1; /*!< SRP-Capable */ + __IO uint32_t HNP_CAP : 1; /*!< HNP-Capable */ + __IO uint32_t USB_TRD_TIM: 4; /*!< Specifies the response time for a MAC request to the Packet + FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM) as + a device. */ + uint32_t : 1; + __IO uint32_t PHY_LPWR_CLK_SEL: 1; /*!< 0, 480-MHz Internal PLL clock. 1, 48-MHz External Clock */ + uint32_t : 12; + __IO uint32_t TX_END_DELAY: 1; /*!< Tx End Delay as a device */ + __IO uint32_t FORCE_HOST_MODE: 1; /*!< Force Host Mode */ + __IO uint32_t FORCE_DEVICE_MODE: 1; /*!< Force Device Mode */ + } GUSBCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GRSTCTL; /*!< Reset Register */ + + struct { + __IO uint32_t CORE_SOFT_RST: 1; /*!< Core Soft Reset */ + uint32_t : 1; + __IO uint32_t FRM_CNT_RST: 1; /*!< Host Frame Counter Reset */ + uint32_t : 1; + __IO uint32_t RX_FIFO_FLUSH: 1; /*!< RxFIFO Flush */ + __IO uint32_t TX_FIFO_FLUSH: 1; /*!< TxFIFO Flush */ + __IO uint32_t TX_FIFO_FLUSH_NUM: 4; /*!< This field indicates which of the 32 possible PHY devices are + being accessed */ + __IO uint32_t TX_FIFO_ALL: 1; /*!< TxFIFO flush all FIFOs */ + uint32_t : 19; + __I uint32_t DMA_REQ : 1; /*!< Indicates that the DMA request is in progress */ + __I uint32_t AHB_IDLE : 1; /*!< Indicates that the AHB Master State Machine is in the IDLE condition */ + } GRSTCTL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GINTSTS; /*!< Interrupt Register */ + + struct { + __I uint32_t CUR_MOD : 1; /*!< Current Mode of Operation */ + __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch Interrupt */ + __I uint32_t OTG_INT : 1; /*!< OTG Interrupt */ + __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ + __I uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ + __I uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ + __I uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ + __I uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ + uint32_t : 2; + __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ + __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ + __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ + __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ + __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a + device */ + __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ + uint32_t : 1; + __I uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ + __I uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ + __I uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ + __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ + __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous + OUT Transfer as a device */ + __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ + __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ + __I uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as + a host */ + __I uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as + a host */ + __I uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ + __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ + __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ + __IO uint32_t DD : 1; /*!< A change in connector ID status */ + __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ + __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ + } GINTSTS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GINTEN; /*!< Interrupt enable Register */ + + struct { + uint32_t : 1; + __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch */ + __IO uint32_t OTG_INT : 1; /*!< OTG */ + __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ + __IO uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ + __IO uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ + __IO uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ + __IO uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ + uint32_t : 2; + __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ + __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ + __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ + __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ + __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a + device */ + __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ + uint32_t : 1; + __IO uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ + __IO uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ + __IO uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ + __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ + __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous + OUT Transfer as a device */ + __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ + __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ + __IO uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as + a host */ + __IO uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as + a host */ + __IO uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ + __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ + __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ + __IO uint32_t DD : 1; /*!< A change in connector ID status */ + __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ + __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ + } GINTEN_b; /*!< BitSize */ + }; + + union { + __I uint32_t GRXSTSR; /*!< Returns the contents of the top of the Receive FIFO */ + + struct { + __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ + __I uint32_t BCNT : 11; /*!< byte count of the received packet */ + __I uint32_t DPID : 2; /*!< Data PID of the received packet */ + __I uint32_t PS : 4; /*!< the status of the received packet */ + __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which + the packet is received on the USB */ + } GRXSTSR_b; /*!< BitSize */ + }; + + union { + __I uint32_t GRXSTSP; /*!< Pop the contents of the top of the Receive FIFO */ + + struct { + __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ + __I uint32_t BCNT : 11; /*!< byte count of the received packet */ + __I uint32_t DPID : 2; /*!< Data PID of the received packet */ + __I uint32_t PS : 4; /*!< the status of the received packet */ + __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which + the packet is received on the USB */ + } GRXSTSP_b; /*!< BitSize */ + }; + __IO uint16_t GRXFSIZ; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 + is max */ + __I uint16_t RESERVED0; + + union { + __IO uint32_t GNPTXFSIZ; /*!< Non-Periodic Transmit FIFO Size Register */ + + struct { + __IO uint32_t NTRSA_INEF0TRSA: 16; /*!< start address for Non-periodic Transmit FIFO RAM as a host or + IN Endpoint FIFO0 Transmit RAM as a device */ + __IO uint32_t NTD_INEF0TD: 16; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 + is max. Non-periodic TxFIFO Depth as a host or IN Endpoint TxFIFO + 0 Depth as a device */ + } GNPTXFSIZ_b; /*!< BitSize */ + }; + + union { + __I uint32_t GNPTXSTS; /*!< Non-Periodic Transmit FIFO/Queue Status Register */ + + struct { + __I uint32_t NTSA : 16; /*!< the amount of free space available in the Non-periodic TxFIFO, + max is 32768. */ + __I uint32_t NTRQSA : 8; /*!< the amount of free space available in the Non-periodic Transmit + Request Queue, max is 8. */ + __I uint32_t TNTRQ_LAST : 1; /*!< last Entry in the Non-periodic Tx Request Queue that is currently + being processed by the MAC */ + __I uint32_t TNTRQ_TYPE : 2; /*!< type in the Non-periodic Tx Request Queue that is currently + being processed by the MAC */ + __I uint32_t TNTRQ_CH : 4; /*!< Channel of top of the Non-periodic Transmit Request Queue */ + } GNPTXSTS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[5]; + + union { + __I uint32_t GHWCFG1; /*!< User HW Config1 Register */ + + struct { + __I uint32_t EP0_DIR : 2; /*!< Endpoint 0 direction, always Bidirection */ + __I uint32_t EP1_DIR : 2; /*!< Endpoint 1 direction */ + __I uint32_t EP2_DIR : 2; /*!< Endpoint 2 direction */ + __I uint32_t EP3_DIR : 2; /*!< Endpoint 3 direction */ + __I uint32_t EP4_DIR : 2; /*!< Endpoint 4 direction */ + __I uint32_t EP5_DIR : 2; /*!< Endpoint 5 direction */ + __I uint32_t EP6_DIR : 2; /*!< Endpoint 6 direction */ + __I uint32_t EP7_DIR : 2; /*!< Endpoint 7 direction */ + __I uint32_t EP8_DIR : 2; /*!< Endpoint 8 direction */ + __I uint32_t EP9_DIR : 2; /*!< Endpoint 9 direction */ + __I uint32_t EP10_DIR : 2; /*!< Endpoint 10 direction */ + __I uint32_t EP11_DIR : 2; /*!< Endpoint 11 direction */ + __I uint32_t EP12_DIR : 2; /*!< Endpoint 12 direction */ + __I uint32_t EP13_DIR : 2; /*!< Endpoint 13 direction */ + __I uint32_t EP14_DIR : 2; /*!< Endpoint 14 direction */ + __I uint32_t EP15_DIR : 2; /*!< Endpoint 15 direction */ + } GHWCFG1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2[3]; + + union { + __IO uint32_t GLPMCFG; /*!< Core LPM Configuration Register */ + + struct { + __IO uint32_t EP0_DIR : 1; /*!< LPM capability is enabled */ + } GLPMCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GPWRDN; /*!< Global Power Down Register */ + + struct { + uint32_t : 1; + __IO uint32_t PMU_ACTIVE : 1; /*!< PMU Active is enabled */ + uint32_t : 1; + __IO uint32_t PDC : 1; /*!< Power Down Clamp is enabled */ + __IO uint32_t PDR : 1; /*!< If clear, Reset DWC_otg */ + __IO uint32_t PDS : 1; /*!< If 0, DWC_otg is in ON state, or OFF state */ + __IO uint32_t DIS_VBUS : 1; /*!< Disable VBUS */ + uint32_t : 8; + __IO uint32_t SRP_DETECT_INT: 1; /*!< SRP has been detected by the PMU as a host */ + __IO uint32_t SRP_DETECT_INT_EN: 1; /*!< Enable For SRPDetect Interrupt as a host */ + __IO uint32_t STATE_CHN_INT: 1; /*!< a status change in either the IDDIG or BSessVld signal */ + __IO uint32_t STATE_CHN_INT_EN: 1; /*!< Enable For Status Change Interrupt */ + __I uint32_t LINE_STATE : 2; /*!< the current linestate on USB as seen by the PMU module */ + __I uint32_t IDDIG : 1; /*!< the status of the IDDIG signal. If 0, host mode. if 1, device + mode */ + __I uint32_t B_SESS_VLD : 1; /*!< B session valid status signal from the PHY */ + __IO uint32_t ADP_INT : 1; /*!< set whenever there is a ADP event */ + } GPWRDN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GDFIFOCFG; /*!< Global DFIFO Software Config Register */ + + struct { + __IO uint32_t GDFIFOCFG : 16; /*!< This field is for dynamic programming of the DFIFO Size. */ + __IO uint32_t EPIBA : 16; /*!< This field provides the start address of the EP info controller */ + } GDFIFOCFG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[40]; + + union { + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Transmit FIFO Size Register */ + + struct { + __IO uint32_t HPTSA : 16; /*!< start address of the Periodic TxFIFO */ + __IO uint32_t EPIBA : 16; /*!< the size of the Periodic TxFIFO */ + } HPTXFSIZ_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF1; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF2; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF3; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF4; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF5; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF6; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF7; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF8; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF9; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF10; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF11; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF12; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF13; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF14; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF15; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED4[176]; + + union { + __IO uint32_t HCFG; /*!< Host Configuration Register */ + + struct { + __IO uint32_t FS_LS_PCS : 2; /*!< FS/LS PHY Clock Select as a host */ + __IO uint32_t FS_LS_SUPPORT: 1; /*!< If set, FS/LS-only, even If the connected device can support + HS */ + uint32_t : 4; + __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ + __IO uint32_t RVP : 8; /*!< ResValid number of clock cycles to detect a valid resume */ + uint32_t : 7; + __IO uint32_t EN_SG_DMA : 1; /*!< Enable Scatter/gather DMA in Host mode */ + __IO uint32_t FLE : 2; /*!< the number of entries in the Frame list. 8 times of FLE */ + __IO uint32_t EPS : 1; /*!< Enables periodic scheduling */ + uint32_t : 4; + __IO uint32_t MCRTE : 1; /*!< enable/disable the Host core to wait 200 PHY clock cycles at + the end of Resume to change the opmode signal to the PHY to + 00 after Suspend or LPM. */ + } HCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HFIR; /*!< Host Frame Interval Register */ + + struct { + __IO uint32_t FI : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t RC : 1; /*!< The HFIR can be dynamically reloaded during runtime if set */ + } HFIR_b; /*!< BitSize */ + }; + + union { + __I uint32_t HFNUM; /*!< Host Frame Number/Frame Time Remaining Register */ + + struct { + __I uint32_t FN : 16; /*!< This field increments when a new SOF is transmitted on the USB */ + __I uint32_t FTR : 16; /*!< amount of time remaining in the current microframe (HS) or Frame + (FS/LS), in terms of PHY clocks */ + } HFNUM_b; /*!< BitSize */ + }; + __I uint32_t RESERVED5; + + union { + __I uint32_t HPTXSTS; /*!< Host Periodic Transmit FIFO/Queue Status Register */ + + struct { + __I uint32_t PTDFSA : 16; /*!< Indicates the number of free locations available to be written + to in the Periodic TxFIFO, max is 32768 */ + __I uint32_t PTRQSA : 8; /*!< Indicates the number of free locations available to be written + in the Periodic Transmit Request Queue, max is 16 */ + __I uint32_t TPTRQ_LAST : 1; /*!< last Entry in the periodic Tx Request Queue that is currently + being processed by the MAC */ + __I uint32_t TPTRQ_TYPE : 2; /*!< type in the periodic Tx Request Queue that is currently being + processed by the MAC */ + __I uint32_t TPTRQ_CH : 4; /*!< Channel of top of the periodic Transmit Request Queue */ + __I uint32_t TPTRQ_ODD_FRAME: 1; /*!< If set, send in odd (micro)Frame */ + } HPTXSTS_b; /*!< BitSize */ + }; + + union { + __I uint32_t HAINT; /*!< Host All Channels Interrupt Register */ + + struct { + __I uint32_t INT : 16; /*!< Channel Interrupts, from 0 to 15. */ + } HAINT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HAINT_EN; /*!< Host All Channels Interrupt Enable Register */ + + struct { + __IO uint32_t EN : 16; /*!< Channel Interrupts Enable, from 0 to 15. */ + } HAINT_EN_b; /*!< BitSize */ + }; + __IO uint32_t HFLBA; /*!< The starting address of the Frame list */ + __I uint32_t RESERVED6[8]; + + union { + __IO uint32_t __HPRT; /*!< Host Port Control and Status Register */ + + struct { + __I uint32_t PCS : 1; /*!< If a device is attached to the port */ + __IO uint32_t PCD : 1; /*!< A device connection is detected */ + __IO uint32_t PE : 1; /*!< Port Enable */ + __IO uint32_t PEDC : 1; /*!< Set if when the status of the Port Enable (bit 2) of this register + changes */ + __I uint32_t POA : 1; /*!< Indicates the overcurrent condition of the port */ + __IO uint32_t POC : 1; /*!< Set if when the status of the Port Overcurrent Active bit (bit + 4) in this register changes */ + __IO uint32_t PR : 1; /*!< Application and Core all can perform resume by setting, then + clear it whatever resume is success or not */ + __IO uint32_t PS : 1; /*!< Sets this bit to put this port in Suspend mode */ + __IO uint32_t PRESET : 1; /*!< sets this bit, a reset sequence is started on this port */ + uint32_t : 1; + __IO uint32_t PLSDP : 1; /*!< Logic level of D+ */ + __IO uint32_t PLSDN : 1; /*!< Logic level of D- */ + __IO uint32_t PP : 1; /*!< this field to control power to this port. 1, power on */ + __IO uint32_t PTC : 4; /*!< The application writes a nonzero value to this field to put + the port into a Test mode */ + __I uint32_t SPEED : 2; /*!< Indicates the speed of the device attached to this port */ + } __HPRT_b; /*!< BitSize */ + }; + __I uint32_t RESERVED7[47]; + + union { + __IO uint32_t HCC0; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED8; + + union { + __IO uint32_t HCINT0; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN0; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ0; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA0; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED9; + __IO uint32_t HCDMAB0; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC1; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED10; + + union { + __IO uint32_t HCINT1; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN1; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ1; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA1; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED11; + __IO uint32_t HCDMAB1; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC2; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED12; + + union { + __IO uint32_t HCINT2; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN2; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ2; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA2; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED13; + __IO uint32_t HCDMAB2; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC3; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED14; + + union { + __IO uint32_t HCINT3; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN3; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ3; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA3; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED15; + __IO uint32_t HCDMAB3; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC4; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED16; + + union { + __IO uint32_t HCINT4; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN4; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ4; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA4; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED17; + __IO uint32_t HCDMAB4; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC5; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED18; + + union { + __IO uint32_t HCINT5; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN5; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ5; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA5; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED19; + __IO uint32_t HCDMAB5; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC6; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED20; + + union { + __IO uint32_t HCINT6; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN6; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ6; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA6; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED21; + __IO uint32_t HCDMAB6; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC7; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED22; + + union { + __IO uint32_t HCINT7; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN7; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ7; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA7; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED23; + __IO uint32_t HCDMAB7; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC8; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED24; + + union { + __IO uint32_t HCINT8; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN8; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ8; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA8; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED25; + __IO uint32_t HCDMAB8; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC9; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED26; + + union { + __IO uint32_t HCINT9; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN9; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ9; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA9; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED27; + __IO uint32_t HCDMAB9; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC10; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED28; + + union { + __IO uint32_t HCINT10; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN10; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ10; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA10; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED29; + __IO uint32_t HCDMAB10; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC11; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED30; + + union { + __IO uint32_t HCINT11; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN11; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ11; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA11; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED31; + __IO uint32_t HCDMAB11; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC12; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED32; + + union { + __IO uint32_t HCINT12; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN12; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ12; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA12; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED33; + __IO uint32_t HCDMAB12; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC13; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED34; + + union { + __IO uint32_t HCINT13; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN13; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ13; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA13; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED35; + __IO uint32_t HCDMAB13; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC14; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED36; + + union { + __IO uint32_t HCINT14; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN14; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ14; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA14; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED37; + __IO uint32_t HCDMAB14; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC15; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED38; + + union { + __IO uint32_t HCINT15; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT15_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN15; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN15_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ15; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ15_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA15; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED39; + __IO uint32_t HCDMAB15; /*!< Host Channel-n DMA Buffer Address Register */ + __I uint32_t RESERVED40[64]; + + union { + __IO uint32_t DCFG; /*!< Device Configuration Register */ + + struct { + __IO uint32_t DSPEED : 2; /*!< the maximum speed the application can support */ + __IO uint32_t NZLSOH : 1; /*!< select the handshake the core sends on receiving a non zero-length + data packet during the OUT transaction of a control transfer's + Status stage */ + __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ + __IO uint32_t DEVICE_ADDR: 7; /*!< The application must program this field after every SetAddress + control command */ + __IO uint32_t PFI : 2; /*!< Indicates the time within a (micro)frame at which the application + must be notified using the End Of Periodic Frame Interrupt */ + __IO uint32_t EDON : 1; /*!< If set the core sets NAK after Bulk OUT transfer complete */ + uint32_t : 9; + __IO uint32_t EN_SG_DMA : 1; /*!< enable the Scatter/Gather DMA operation */ + __IO uint32_t PSI : 2; /*!< Periodic Scheduling Interval */ + __IO uint32_t RVP : 6; /*!< It controls the resume period when the core resumes from suspend */ + } DCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DCTL; /*!< Device Control Register */ + + struct { + __IO uint32_t RWS : 1; /*!< If set, the core initiates remote signaling to wake the USB + hosts */ + __IO uint32_t SD : 1; /*!< If set, generates a device disconnect event to the USB host */ + __I uint32_t GNPINS : 1; /*!< A NAK handshake is sent out on all non-periodic IN endpoints, + irrespective of the data availability in the transmit FIFO. */ + __I uint32_t GONS : 1; /*!< No data is written to the RxFIFO, irrespective of space availability.. */ + __IO uint32_t TC : 3; /*!< Test Control */ + __O uint32_t SGNPIN : 1; /*!< A write to this field sets the Global Non-periodic IN NAK */ + __O uint32_t CGNPIN : 1; /*!< A write to this field clears the Global Non-periodic IN NAK */ + __O uint32_t SGON : 1; /*!< A write to this field sets the Global OUT NAK */ + __O uint32_t CGON : 1; /*!< A write to this field sets the Global OUT NAK. */ + __IO uint32_t POPD : 1; /*!< Power-On Programming Done */ + __IO uint32_t GMC : 2; /*!< GMC must be programmed only once after initialization. the number + of packets to be serviced for that end point before moving to + the next end point */ + uint32_t : 1; + __IO uint32_t IFNIE : 1; /*!< Ignore frame number for isochronous endpoints */ + __IO uint32_t NBE : 1; /*!< Set NAK automatically on babble */ + __IO uint32_t ECBNA : 1; /*!< After receiving BNA interrupt, the core disables the endpoint */ + } DCTL_b; /*!< BitSize */ + }; + + union { + __I uint32_t DSTS; /*!< Device Status Register */ + + struct { + __I uint32_t SUSPEND : 1; /*!< this bit is set as long as a Suspend condition is detected on + the USB */ + __I uint32_t SPEED : 2; /*!< Indicates the speed at which the DWC_otg core has come up after + speed detection through a chirp sequence */ + __I uint32_t EE : 1; /*!< reason of suspend state */ + uint32_t : 4; + __I uint32_t SOFFN : 14; /*!< Frame or Microframe Number of the Received SOF */ + __I uint32_t DLSDP : 1; /*!< Logic level of D+ */ + __I uint32_t DLSDN : 1; /*!< Logic level of D- */ + } DSTS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED41; + + union { + __IO uint32_t DIEPEN; /*!< Device IN Endpoint Common Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ + __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ + __IO uint32_t TIMEOUT : 1; /*!< Timeout Condition(Non-isochronous endpoints) */ + __IO uint32_t ITRWTFE : 1; /*!< IN Token Received When TxFIFO Empty */ + __IO uint32_t ITRWEPM : 1; /*!< IN Token received with EP Mismatch */ + __IO uint32_t IENE : 1; /*!< IN Endpoint NAK Effective */ + uint32_t : 1; + __IO uint32_t FU : 1; /*!< Fifo Underrun */ + __IO uint32_t BNA : 1; /*!< BNA Interrupt */ + uint32_t : 3; + __IO uint32_t NAK : 1; /*!< NAK interrupt */ + } DIEPEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DOEPEN; /*!< Device OUT Endpoint Common Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ + __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ + __IO uint32_t SPD : 1; /*!< SETUP Phase Done, Applies to control endpoints only */ + __IO uint32_t OTRWED : 1; /*!< OUT Token Received when Endpoint Disabled, Applies to control + OUT endpoints only */ + __IO uint32_t SPR : 1; /*!< Status Phase Received */ + __IO uint32_t BTBSPR : 1; /*!< Back-to-Back SETUP Packets Received, Applies to control OUT + endpoints only */ + uint32_t : 1; + __IO uint32_t OPE : 1; /*!< OUT Packet Error */ + __IO uint32_t BNA : 1; /*!< BNA Interrupt */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error interrupt */ + __IO uint32_t NAK : 1; /*!< NAK interrupt */ + __IO uint32_t NYET : 1; /*!< NYET interrupt */ + } DOEPEN_b; /*!< BitSize */ + }; + + union { + __I uint32_t DAINT; /*!< Device All Channels Interrupt Register */ + + struct { + __I uint32_t INT : 16; /*!< IN Endpoint Interrupt Bits, from 0 to 15. */ + __I uint32_t OUT_INT : 16; /*!< OUT Endpoint Interrupt Bits, from 0 to 15. */ + } DAINT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DAINT_EN; /*!< Device All Channels Interrupt Enable Register */ + + struct { + __IO uint32_t IN_EN : 16; /*!< IN EP Interrupt Enable, from 0 to 15. */ + __IO uint32_t OUT_EN : 16; /*!< OUT EP Interrupt Enable, from 0 to 15. */ + } DAINT_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED42[4]; + + union { + __IO uint32_t DTHRCTL; /*!< Device Threshold Control Register */ + + struct { + __IO uint32_t NISOINETE : 1; /*!< Non-ISO IN Endpoints Threshold Enable */ + __IO uint32_t ISOINETE : 1; /*!< ISO IN Endpoints Threshold Enable */ + __IO uint32_t TTL : 9; /*!< This field specifies Transmit thresholding size in DWORDS */ + __IO uint32_t ATR : 2; /*!< These bits define the ratio between the AHB threshold and the + MAC threshold for the transmit path only. */ + uint32_t : 3; + __IO uint32_t RTE : 1; /*!< If set, the core enables thresholding in the receive direction */ + __IO uint32_t RTL : 9; /*!< This field specifies Receive thresholding size in DWORDS */ + uint32_t : 1; + __IO uint32_t APE : 1; /*!< This bit controls internal DMA arbiter parking for IN endpoints */ + } DTHRCTL_b; /*!< BitSize */ + }; + __IO uint16_t DIEPEMPEN; /*!< Device IN Endpoint FIFO Empty Interrupt Enable Register */ + __I uint16_t RESERVED43[101]; + + union { + __IO uint32_t DIEPCTL0; /*!< Device Control IN Endpoint 0 Control Register */ + + struct { + __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, + applies to IN and OUT endpoints */ + uint32_t : 13; + __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active + in all configurations and interfaces */ + uint32_t : 1; + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ + __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a + SETUP token is received for this endpoint */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + uint32_t : 2; + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED44; + + union { + __IO uint32_t DIEPINT0; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED45; + + union { + __IO uint32_t DIEPTSIZ0; /*!< Device IN Endpoint 0 Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ + uint32_t : 12; + __IO uint32_t PACKET_CNT : 2; /*!< the total number of USB packets */ + } DIEPTSIZ0_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA0; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA0; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED46; + __I uint32_t DIEPDMAB0; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL1; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED47; + + union { + __IO uint32_t DIEPINT1; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED48; + + union { + __IO uint32_t DIEPTSIZ1; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ1_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA1; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA1; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED49; + __I uint32_t DIEPDMAB1; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL2; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED50; + + union { + __IO uint32_t DIEPINT2; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED51; + + union { + __IO uint32_t DIEPTSIZ2; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ2_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA2; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA2; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED52; + __I uint32_t DIEPDMAB2; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL3; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED53; + + union { + __IO uint32_t DIEPINT3; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED54; + + union { + __IO uint32_t DIEPTSIZ3; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ3_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA3; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA3; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED55; + __I uint32_t DIEPDMAB3; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL4; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED56; + + union { + __IO uint32_t DIEPINT4; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED57; + + union { + __IO uint32_t DIEPTSIZ4; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ4_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA4; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA4; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED58; + __I uint32_t DIEPDMAB4; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL5; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED59; + + union { + __IO uint32_t DIEPINT5; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED60; + + union { + __IO uint32_t DIEPTSIZ5; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ5_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA5; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA5; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED61; + __I uint32_t DIEPDMAB5; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL6; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED62; + + union { + __IO uint32_t DIEPINT6; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED63; + + union { + __IO uint32_t DIEPTSIZ6; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ6_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA6; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA6; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED64; + __I uint32_t DIEPDMAB6; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL7; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED65; + + union { + __IO uint32_t DIEPINT7; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED66; + + union { + __IO uint32_t DIEPTSIZ7; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ7_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA7; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA7; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED67; + __I uint32_t DIEPDMAB7; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL8; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED68; + + union { + __IO uint32_t DIEPINT8; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED69; + + union { + __IO uint32_t DIEPTSIZ8; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ8_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA8; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA8; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED70; + __I uint32_t DIEPDMAB8; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL9; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED71; + + union { + __IO uint32_t DIEPINT9; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED72; + + union { + __IO uint32_t DIEPTSIZ9; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ9_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA9; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA9; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED73; + __I uint32_t DIEPDMAB9; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL10; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED74; + + union { + __IO uint32_t DIEPINT10; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED75; + + union { + __IO uint32_t DIEPTSIZ10; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ10_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA10; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA10; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED76; + __I uint32_t DIEPDMAB10; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL11; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED77; + + union { + __IO uint32_t DIEPINT11; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED78; + + union { + __IO uint32_t DIEPTSIZ11; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ11_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA11; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA11; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED79; + __I uint32_t DIEPDMAB11; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL12; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED80; + + union { + __IO uint32_t DIEPINT12; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED81; + + union { + __IO uint32_t DIEPTSIZ12; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ12_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA12; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA12; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED82; + __I uint32_t DIEPDMAB12; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL13; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED83; + + union { + __IO uint32_t DIEPINT13; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED84; + + union { + __IO uint32_t DIEPTSIZ13; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ13_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA13; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA13; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED85; + __I uint32_t DIEPDMAB13; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL14; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED86; + + union { + __IO uint32_t DIEPINT14; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED87; + + union { + __IO uint32_t DIEPTSIZ14; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ14_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA14; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA14; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED88; + __I uint32_t DIEPDMAB14; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL15; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED89; + + union { + __IO uint32_t DIEPINT15; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED90; + + union { + __IO uint32_t DIEPTSIZ15; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ15_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA15; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA15; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED91; + __I uint32_t DIEPDMAB15; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL0; /*!< Device Control OUT Endpoint 0 Control Register */ + + struct { + __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, + applies to IN and OUT endpoints */ + uint32_t : 13; + __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active + in all configurations and interfaces */ + uint32_t : 1; + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ + __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ + __IO uint32_t SNOOP : 1; /*!< does not check if the OUT packets are correct before transferring */ + __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a + SETUP token is received for this endpoint */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + uint32_t : 2; + __I uint32_t EPD : 1; /*!< The application cannot disable control OUT endpoint 0 */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED92; + + union { + __IO uint32_t DOEPINT0; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED93; + + union { + __IO uint32_t DOEPTSIZ0; /*!< Device OUT Endpoint 0 Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ + uint32_t : 12; + __IO uint32_t PACKET_CNT : 1; /*!< This field is decremented to zero after a packet is written + into the RxFIFO */ + uint32_t : 9; + __IO uint32_t SETUP_CNT : 2; /*!< the number of back-to-back SETUP data packets the endpoint can + receive */ + } DOEPTSIZ0_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA0; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED94; + __I uint32_t DOEPDMAB0; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL1; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED95; + + union { + __IO uint32_t DOEPINT1; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED96; + + union { + __IO uint32_t DOEPTSIZ1; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ1_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA1; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED97; + __I uint32_t DOEPDMAB1; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL2; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED98; + + union { + __IO uint32_t DOEPINT2; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED99; + + union { + __IO uint32_t DOEPTSIZ2; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ2_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA2; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED100; + __I uint32_t DOEPDMAB2; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL3; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED101; + + union { + __IO uint32_t DOEPINT3; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED102; + + union { + __IO uint32_t DOEPTSIZ3; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ3_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA3; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED103; + __I uint32_t DOEPDMAB3; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL4; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED104; + + union { + __IO uint32_t DOEPINT4; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED105; + + union { + __IO uint32_t DOEPTSIZ4; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ4_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA4; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED106; + __I uint32_t DOEPDMAB4; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL5; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED107; + + union { + __IO uint32_t DOEPINT5; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED108; + + union { + __IO uint32_t DOEPTSIZ5; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ5_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA5; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED109; + __I uint32_t DOEPDMAB5; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL6; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED110; + + union { + __IO uint32_t DOEPINT6; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED111; + + union { + __IO uint32_t DOEPTSIZ6; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ6_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA6; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED112; + __I uint32_t DOEPDMAB6; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL7; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED113; + + union { + __IO uint32_t DOEPINT7; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED114; + + union { + __IO uint32_t DOEPTSIZ7; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ7_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA7; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED115; + __I uint32_t DOEPDMAB7; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL8; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED116; + + union { + __IO uint32_t DOEPINT8; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED117; + + union { + __IO uint32_t DOEPTSIZ8; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ8_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA8; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED118; + __I uint32_t DOEPDMAB8; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL9; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED119; + + union { + __IO uint32_t DOEPINT9; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED120; + + union { + __IO uint32_t DOEPTSIZ9; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ9_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA9; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED121; + __I uint32_t DOEPDMAB9; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL10; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED122; + + union { + __IO uint32_t DOEPINT10; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED123; + + union { + __IO uint32_t DOEPTSIZ10; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ10_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA10; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED124; + __I uint32_t DOEPDMAB10; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL11; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED125; + + union { + __IO uint32_t DOEPINT11; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED126; + + union { + __IO uint32_t DOEPTSIZ11; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ11_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA11; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED127; + __I uint32_t DOEPDMAB11; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL12; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED128; + + union { + __IO uint32_t DOEPINT12; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED129; + + union { + __IO uint32_t DOEPTSIZ12; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ12_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA12; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED130; + __I uint32_t DOEPDMAB12; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL13; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED131; + + union { + __IO uint32_t DOEPINT13; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED132; + + union { + __IO uint32_t DOEPTSIZ13; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ13_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA13; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED133; + __I uint32_t DOEPDMAB13; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL14; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED134; + + union { + __IO uint32_t DOEPINT14; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED135; + + union { + __IO uint32_t DOEPTSIZ14; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ14_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA14; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED136; + __I uint32_t DOEPDMAB14; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL15; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED137; + + union { + __IO uint32_t DOEPINT15; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED138; + + union { + __IO uint32_t DOEPTSIZ15; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ15_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA15; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED139; + __I uint32_t DOEPDMAB15; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ +} USB_Type; + + +/* ================================================================================ */ +/* ================ GLOBAL_CTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief GLOBAL_CTRL (GLOBAL_CTRL) + */ + +typedef struct { /*!< GLOBAL_CTRL Structure */ + + union { + __I uint32_t AES_STATUS; /*!< AES status */ + + struct { + __I uint32_t RD_ALMOST_EMPTY: 1; /*!< FIFO read almost empty */ + __I uint32_t RD_EMPTY : 1; /*!< FIFO read empty */ + __I uint32_t WR_FULL_ALMOST: 1; /*!< FIFO write almost full */ + __I uint32_t WR_FULL : 1; /*!< FIFO write full */ + __I uint32_t IDLE : 1; /*!< decryption finish */ + } AES_STATUS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED0[253]; + + union { + __IO uint32_t CLK_SEL_0; /*!< clock select 0 */ + + struct { + __IO uint32_t CAN1_CLK : 2; /*!< CAN1 clock frequency dividor based on system clock, which should + be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t CAN0_CLK : 2; /*!< CAN0 clock frequency dividor based on system clock, which should + be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t I2C1_CLK : 2; /*!< I2C1 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t I2C0_CLK : 2; /*!< I2C0 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t SPI1_CLK : 2; /*!< SPI1 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t SPI0_CLK : 2; /*!< SPI0 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t UART1_CLK : 2; /*!< UART1 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t UART0_CLK : 2; /*!< UART0 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t RTC_CLK : 2; /*!< RTC clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t GPIO_CLK : 2; /*!< GPIO clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t TIMER_CLK : 2; /*!< TIMER clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t WDG_CLK : 2; /*!< watchdog clock frequency dividor based on system clock, which + should be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + uint32_t : 2; + __IO uint32_t FLASH_CLK : 2; /*!< FLASH clock frequency dividor based on system clock, which should + be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + __IO uint32_t DMA_AHB_CLK: 2; /*!< DMA AHB bus clock frequency dividor based on system clock, which + should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + __IO uint32_t USB_AHB_CLK: 2; /*!< USB AHB bus clock frequency dividor based on system clock, which + should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + } CLK_SEL_0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CLK_SEL_1; /*!< clock select 1 */ + + struct { + __IO uint32_t ETH_AHB_CLK: 2; /*!< ETH_AHB clock frequency dividor based on system clock, which + should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + __IO uint32_t DDR_CLK : 2; /*!< DDR clock frequency dividor based on system clock, which should + be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + uint32_t : 4; + __IO uint32_t ADC_CLK : 2; /*!< ADC clock frequency dividor based on system clock, which should + be 1/8, 1/16, 1/32, external from 0 to 3 */ + __IO uint32_t EFUSE_CLK : 2; /*!< EFUSE clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t SYS_CLK : 4; /*!< system clock clock frequency dividor based on system clock, + which should be oscillator(0), DLL(1), crystal(2), external(3), + JTAG(4), PS(8) */ + __IO uint32_t UART2_CLK : 2; /*!< UART2 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t UTMI_CLK : 1; /*!< UTMI clock came from on-chip usb phy(0) or off-chip usb phy(1) */ + } CLK_SEL_1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t USB_PHY_CTRL; /*!< USB Phy Control Register */ + + struct { + __IO uint32_t BITSTUFF : 1; /*!< 0: No bit stuff */ + __IO uint32_t XTLSEL : 1; /*!< 0: 12MHz */ + __IO uint32_t PLL : 1; /*!< PLL mode */ + __IO uint32_t VOLDET : 1; /*!< Voltage Detector Enable, 0: Disable */ + __IO uint32_t IDUP : 1; /*!< 0: ID is uplled up through 33k Ohm resister */ + __IO uint32_t CKISEL : 1; /*!< Clock selection, 0: Crystal, 1: Internal Clock */ + __IO uint32_t FMOD : 1; /*!< 1: Normal */ + __IO uint32_t SQUELCH : 3; /*!< Squelch Reference Voltage, 000: 27.5mV, 001: 137.5mV, 111: 220mV */ + __IO uint32_t HDISCDT : 3; /*!< Host Disconnect Detection Reference Voltage, 000: 500mV, 100: + 588mV, 111: 654mV */ + __IO uint32_t PRTSEL : 1; /*!< 0: Internal OTG PHY, 1: UTMI to External PHY */ + __IO uint32_t RSTPRT : 1; /*!< 0: The reverse of usb_rst_n will reset, 1: Reset OTG PHY */ + } USB_PHY_CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RTC_INT_EN; /*!< RTC interrupt enable Register */ + + struct { + __IO uint32_t SECOND : 1; /*!< 1s interrupt enable */ + __IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt enable */ + } RTC_INT_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1; + + union { + __IO uint32_t NMI_SEL; /*!< nmi interrupt selection */ + + struct { + __IO uint32_t NMI : 7; /*!< NMI interrupt ID */ + } NMI_SEL_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + __IO uint32_t AES_TARGET_ADDR; /*!< AES target address, default is frame decoder address(0x41800000) */ + + union { + __IO uint32_t AES_BURST_TYPE; /*!< AES burst type */ + + struct { + __IO uint32_t TYPE : 2; /*!< burst type, fixed(0), incr(1) */ + } AES_BURST_TYPE_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[3]; + + union { + __IO uint32_t ICACHE; /*!< ICACHE Enable */ + + struct { + __IO uint32_t EN : 1; /*!< ICACHE Enable */ + } ICACHE_b; /*!< BitSize */ + }; + __IO uint32_t IBUSOFF; /*!< Code Bus Offset */ + __IO uint32_t DBUSOFF; /*!< Data Bus Offset */ + __IO uint32_t EXTADDR; /*!< Bus Ext Addr */ +} GLOBAL_CTRL_Type; + + +/* ================================================================================ */ +/* ================ AES ================ */ +/* ================================================================================ */ + + +/** + * @brief AES (AES) + */ + +typedef struct { /*!< AES Structure */ + __IO uint32_t FIFO; /*!< data FIFO to be decoded */ + + union { + __O uint32_t FIFO_CLEAR; /*!< clear data FIFO */ + + struct { + __O uint32_t CLEAR : 1; /*!< clear after write 1 and write 0 */ + } FIFO_CLEAR_b; /*!< BitSize */ + }; +} AES_Type; + + +/* ================================================================================ */ +/* ================ DDRC ================ */ +/* ================================================================================ */ + + +/** + * @brief DDR_CFG (DDRC) + */ + +typedef struct { /*!< DDRC Structure */ + __IO uint32_t CMD; /*!< DDR commands to program */ + + union { + __IO uint32_t CTRL; /*!< DDR Control */ + + struct { + __IO uint32_t TO : 1; /*!< Take over DDRC siggen */ + __IO uint32_t CLR : 1; /*!< Clear commands in FIFO */ + __O uint32_t STR : 1; /*!< Start to execute the commands in FIFO */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MODE; /*!< DDR mode */ + + struct { + __IO uint32_t MODE : 6; /*!< DDRC Mode */ + uint32_t : 2; + __IO uint32_t LANE : 1; /*!< LANE synchronization logic bypass */ + uint32_t : 3; + __IO uint32_t ADEC : 1; /*!< address decoder mapping */ + uint32_t : 3; + __IO uint32_t B16 : 2; /*!< Active 16 bit DQ position when the unmber of DQ IO is 16 */ + uint32_t : 6; + __IO uint32_t CLKPOL : 2; /*!< DQS clkpol set by user on the PHY */ + } MODE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QUE; /*!< DDRC queue depth */ + + struct { + __IO uint32_t DEPTH : 1; /*!< DDRC queue depth */ + } QUE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t REF; /*!< Refresh control */ + + struct { + __IO uint32_t THRD : 5; /*!< Number of refresh requests which can be postponed */ + uint32_t : 3; + __IO uint32_t TRIG : 4; /*!< Number of refresh requests every dl_refi */ + uint32_t : 4; + __IO uint32_t TIME : 16; /*!< Refresh interval time */ + } REF_b; /*!< BitSize */ + }; + + union { + __O uint32_t REF_TRIG; /*!< Refresh trigger */ + + struct { + __O uint32_t GO : 1; /*!< Write 1 to trigger one refresh request by cbus */ + } REF_TRIG_b; /*!< BitSize */ + }; + + union { + __O uint32_t ZQ_TRIG; /*!< ZQCTL trigger */ + + struct { + __O uint32_t CS : 1; /*!< Write 1 to trigger one ZQCS request by cbus */ + __O uint32_t CL : 1; /*!< Write 1 to trigger one ZQCL request by cbus */ + } ZQ_TRIG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ZQCSR; /*!< ZQCSR */ + + struct { + __IO uint32_t EN : 1; /*!< Enable ZQCS request */ + __IO uint32_t PRI : 1; /*!< 0: DMA access prior to ZQCS, 1: ZQCS prior to DMA access */ + } ZQCSR_b; /*!< BitSize */ + }; + __IO uint32_t ZQCSI; /*!< ZQCS interval time */ + + union { + __IO uint32_t RCD; /*!< t(RCD) */ + + struct { + __IO uint32_t DI : 5; /*!< t(RCD), delay from ACT command to RW command of same bank */ + } RCD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RAS; /*!< t(RAS) */ + + struct { + __IO uint32_t DI : 6; /*!< t(RAS), delay from ACT command to PRE command of same bank */ + } RAS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RP; /*!< t(RP) */ + + struct { + __IO uint32_t DI : 5; /*!< t(RP), delay from PRE command to ACT/REF/ZQ command */ + uint32_t : 3; + __IO uint32_t RPA : 1; /*!< 0: t(RP) delay for PREA command; 1: t(RP)+1 delay for PREA command */ + } RP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RC; /*!< t(RC) */ + + struct { + __IO uint32_t DI : 7; /*!< t(RC), delay from ACT command to ACT command of same bank */ + } RC_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RRD; /*!< t(RRD) */ + + struct { + __IO uint32_t DI : 4; /*!< t(RRD), delay from ACT command to ACT command */ + } RRD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CCD; /*!< t(CCD) */ + + struct { + __IO uint32_t DI : 3; /*!< t(CCD), delay from RW command to RW command */ + } CCD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RTW; /*!< t(RTW) */ + + struct { + __IO uint32_t DI : 5; /*!< t(RTW), delay from RD command to WR command */ + } RTW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WTR; /*!< t(WTR) */ + + struct { + __IO uint32_t DI : 5; /*!< t(WTR), delay from WR command to RD command */ + } WTR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RTP; /*!< t(RTP) */ + + struct { + __IO uint32_t DI : 3; /*!< t(RTP), delay from RD command to PRE command of same bank */ + } RTP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WTP; /*!< t(WTP) */ + + struct { + __IO uint32_t DI : 6; /*!< t(WTP), delay from WR command to PRE command of same bank */ + } WTP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RFC; /*!< t(RFC) */ + + struct { + __IO uint32_t DI : 8; /*!< t(WTP), delay from WR command to PRE command of same bank */ + } RFC_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ZQCL; /*!< t(ZQoper) */ + + struct { + __IO uint32_t DI : 9; /*!< t(ZQoper), delay from ZQCL command to REF/ZQ/ACT command */ + } ZQCL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ZQCS; /*!< t(ZQCS) */ + + struct { + __IO uint32_t DI : 7; /*!< t(ZQCS), delay from ZQCS command to REF/ZQ/ACT command */ + } ZQCS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t FAW; /*!< t(FAW) */ + + struct { + __IO uint32_t DI : 6; /*!< t(FAW), 4 act command window time */ + } FAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t BURST; /*!< BURST */ + + struct { + __IO uint32_t LEN : 1; /*!< 0: length 8, 1: length 4 */ + } BURST_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PHUNG; /*!< PHUNG */ + + struct { + __IO uint32_t MODE : 1; /*!< 0: normal mode, 1: prevent read hang mode */ + __IO uint32_t LPM : 1; /*!< 1: stop the IO clk */ + } PHUNG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RL; /*!< READ Latency */ + + struct { + __IO uint32_t VAL : 5; /*!< READ Latency */ + } RL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WL; /*!< WRITE Latency */ + + struct { + __IO uint32_t VAL : 5; /*!< WRITE Latency */ + } WL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TRAIN; /*!< TRAIN */ + + struct { + __IO uint32_t EN : 4; /*!< Enable lane N training mode */ + } TRAIN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN0; /*!< Delay cycles of dqsen of byte lane 0 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 0 */ + } DQSEN0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN1; /*!< Delay cycles of dqsen of byte lane 1 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 1 */ + } DQSEN1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN2; /*!< Delay cycles of dqsen of byte lane 2 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 2 */ + } DQSEN2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN3; /*!< Delay cycles of dqsen of byte lane 0 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 3 */ + } DQSEN3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ODTH; /*!< Delay from WR command to odt high transition */ + + struct { + __IO uint32_t DL : 5; /*!< Delay from WR command to odt high transition */ + } ODTH_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ODTL; /*!< Delay from WR command to odt low transition */ + + struct { + __IO uint32_t DL : 5; /*!< Delay from WR command to odt low transition */ + } ODTL_b; /*!< BitSize */ + }; + + union { + __O uint32_t ODT; /*!< Used in write leveling mode */ + + struct { + __O uint32_t TRIG : 1; /*!< 0: trigger odt low, 1: trigger odt high */ + } ODT_b; /*!< BitSize */ + }; + + union { + __O uint32_t DQS; /*!< Used in write leveling mode */ + + struct { + __O uint32_t TRIG : 1; /*!< Writing 1 to this register triggers a dqs pulse */ + } DQS_b; /*!< BitSize */ + }; + + union { + __I uint32_t STA; /*!< Commands FIFO */ + + struct { + __I uint32_t MODE : 1; /*!< DDRC in sw_proc mode */ + __I uint32_t EMPTY : 1; /*!< Sw_proc command fifo empty */ + __I uint32_t FULL : 1; /*!< Sw_proc command fifo full */ + } STA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INTCTL; /*!< Interrupt Control */ + + struct { + __IO uint32_t DONE : 1; /*!< 0: the sw_proc_done int will not be masked, 1: the sw_proc_done + int will be masked */ + __IO uint32_t ERR : 1; /*!< mask of the lane_sync_error interrupt */ + uint32_t : 14; + __IO uint32_t MODE : 1; /*!< Interrupt mode: 0: int level active, write 1 to clear; 1: int + edge active */ + } INTCTL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INTRAW; /*!< Interrupt RAW */ + + struct { + __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done before mask */ + __IO uint32_t ERR : 1; /*!< int reg of the lane sync error before masked */ + } INTRAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INTSTA; /*!< Interrupt STA */ + + struct { + __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done after mask */ + __IO uint32_t ERR : 1; /*!< int register of lane sync error after masked */ + } INTSTA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PHY; /*!< PHY */ + + struct { + __IO uint32_t RST : 1; /*!< FPGA version, reset read dq fifo. Low active */ + } PHY_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RDQ; /*!< FPGA version, read dq delay of byte lane N */ + + struct { + __IO uint32_t L3 : 6; /*!< FPGA version, read dq delay of byte lane3 */ + uint32_t : 2; + __IO uint32_t L2 : 6; /*!< FPGA version, read dq delay of byte lane2 */ + uint32_t : 2; + __IO uint32_t L1 : 6; /*!< FPGA version, read dq delay of byte lane3 */ + uint32_t : 2; + __IO uint32_t L0 : 7; /*!< FPGA version, read dq delay of byte lane0 */ + } RDQ_b; /*!< BitSize */ + }; + + union { + __I uint32_t CALIB; /*!< calibration */ + + struct { + __I uint32_t TPU : 8; /*!< calibration result values, if fail then 0x40 */ + __I uint32_t TPD : 8; /*!< calibration result values, if fail then 0x40 */ + __I uint32_t PDR : 5; /*!< calibration result values, if fail then 0x40 */ + __I uint32_t NDR : 5; /*!< calibration result values, if fail then 0x40 */ + uint32_t : 5; + __IO uint32_t EN : 1; /*!< trigger the calibration processing which is sensitive to the + positive edge */ + } CALIB_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ITMDLY; /*!< "itmdly" is the fine delay trim to the read path "dq", "itmsdly" + is to the read path of "dqs". From 000 to 111 increasingly, + each step is about 40ps */ + + struct { + __IO uint32_t I0 : 4; /*!< itmdly0 */ + __IO uint32_t IS0 : 4; /*!< itmsdly0 */ + __IO uint32_t I1 : 4; /*!< itmdly1 */ + __IO uint32_t IS1 : 4; /*!< itmsdly1 */ + __IO uint32_t I2 : 4; /*!< itmdly2 */ + __IO uint32_t IS2 : 4; /*!< itmsdly2 */ + __IO uint32_t I3 : 4; /*!< itmdly3 */ + __IO uint32_t IS3 : 4; /*!< itmsdly3 */ + } ITMDLY_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TUNE; /*!< CALIB_TUNE */ + + struct { + __IO uint32_t TPU : 4; /*!< tpu_tune, finial val = tune[3] ? val - tune : val + tune */ + __IO uint32_t TPD : 4; /*!< tpd_tune, tune[3:0] for TPD/TPU, [2:0] is the tune val */ + __IO uint32_t PDR : 4; /*!< pdr_tune, inial val = tune[2] ? val - tune : val + tune */ + __IO uint32_t NDR : 4; /*!< ndr_tune, tune[2:0] for NDR/PDR, [1:0] is the tune val */ + } TUNE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RD_SEL; /*!< RD_WINDOWS_SEL */ + + struct { + __IO uint32_t PHY_SEL : 3; /*!< To fix the phy read valid issue, this is to adjust the read + data valid window to match the phy read valid by cycle level */ + } RD_SEL_b; /*!< BitSize */ + }; +} DDRC_Type; + + +/* ================================================================================ */ +/* ================ PDLOCK ================ */ +/* ================================================================================ */ + + +/** + * @brief PLL DLL LOCK (PDLOCK) + */ + +typedef struct { /*!< PDLOCK Structure */ + + union { + __I uint32_t GCLK; /*!< GCLK */ + + struct { + __I uint32_t C1R2P : 1; /*!< gclk_c1r2_pll_lock */ + __I uint32_t C1R1P : 1; /*!< gclk_c1r1_pll_lock */ + __I uint32_t C2R1P : 1; /*!< gclk_c2r1_pll_lock */ + __I uint32_t C2R2P : 1; /*!< gclk_c2r2_pll_lock */ + __I uint32_t C1R2D : 1; /*!< gclk_c1r2_dll_lock */ + __I uint32_t C1R1D : 1; /*!< gclk_c1r1_dll_lock */ + __I uint32_t C2R1D : 1; /*!< gclk_c2r1_dll_lock */ + __I uint32_t C2R2D : 1; /*!< gclk_c2r2_dll_lock */ + } GCLK_b; /*!< BitSize */ + }; +} PDLOCK_Type; + + +/* ================================================================================ */ +/* ================ PDPROT ================ */ +/* ================================================================================ */ + + +/** + * @brief PLL DLL PROTECT (PDPROT) + */ + +typedef struct { /*!< PDPROT Structure */ + + union { + __O uint32_t LOCK; /*!< LOCK */ + + struct { + __O uint32_t EN : 1; /*!< Enable the PLL DLL Lock to Protect it */ + } LOCK_b; /*!< BitSize */ + }; +} PDPROT_Type; + + +/* ================================================================================ */ +/* ================ CFG_CTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief CFG_CTRL (CFG_CTRL) + */ + +typedef struct { /*!< CFG_CTRL Structure */ + __I uint32_t RESERVED0[3]; + + union { + __IO uint32_t DONE; /*!< DONE CFG */ + + struct { + __IO uint32_t CMD : 1; /*!< Write 1 indicate all chain data write over */ + __IO uint32_t STA : 1; /*!< 1= all chain config process over, chip is in user mode */ + } DONE_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[34]; + + union { + __IO uint32_t PDLLSTR; /*!< PLL DLL RESET */ + + struct { + __IO uint32_t C1R1P : 1; /*!< C1r1_rstpll_n, low active */ + __IO uint32_t C1R2P : 1; /*!< C1r2_rstpll_n, low active */ + __IO uint32_t C2R1P : 1; /*!< C2r1_rstpll_n, low active */ + __IO uint32_t C2R2P : 1; /*!< C2r2_rstpll_n, low active */ + __IO uint32_t C1R1D : 1; /*!< C1r1_rstdll_n, low active */ + __IO uint32_t C1R2D : 1; /*!< C1r2_rstdll_n, low active */ + __IO uint32_t C2R1D : 1; /*!< C2r1_rstdll_n, low active */ + __IO uint32_t C2R2D : 1; /*!< C2r2_rstdll_n, low active */ + } PDLLSTR_b; /*!< BitSize */ + }; +} CFG_CTRL_Type; + + +/* ================================================================================ */ +/* ================ SOFT_RESET ================ */ +/* ================================================================================ */ + + +/** + * @brief SUB SOFT RESET (SOFT_RESET) + */ + +typedef struct { /*!< SOFT_RESET Structure */ + + union { + __IO uint32_t SOFTRST; /*!< SOFTRST */ + + struct { + __IO uint32_t CAN1_n : 1; /*!< soft_rst_can1_n */ + __IO uint32_t CAN0_n : 1; /*!< soft_rst_can0_n */ + __IO uint32_t I2C1_n : 1; /*!< soft_rst_i2c1_n */ + __IO uint32_t I2C0_n : 1; /*!< soft_rst_i2c0_n */ + __IO uint32_t SPI1_n : 1; /*!< soft_rst_spi1_n */ + __IO uint32_t SPI0_n : 1; /*!< soft_rst_spi0_n */ + __IO uint32_t UART1_n : 1; /*!< soft_rst_uart1_n */ + __IO uint32_t UART0_n : 1; /*!< soft_rst_uart0_n */ + __IO uint32_t RTC_n : 1; /*!< soft_rst_rtc_n */ + __IO uint32_t GPIO_n : 1; /*!< soft_rst_gpio_n */ + __IO uint32_t TIMER_n : 1; /*!< soft_rst_timer_n */ + __IO uint32_t WDT_n : 1; /*!< soft_rst_wdt_n */ + __IO uint32_t LVDS_n : 1; /*!< soft_rst_lvds_n */ + __IO uint32_t FLS_n : 1; /*!< soft_rst_fls_n */ + __IO uint32_t DMAC_AHB_n : 1; /*!< soft_rst_dmac_ahb_n */ + __IO uint32_t USB_AHB_n : 1; /*!< soft_rst_usb_ahb_n */ + __IO uint32_t ETH_AHB_n : 1; /*!< soft_rst_eth_ahb_n */ + __IO uint32_t DDRC_n : 1; /*!< soft_rst_ddrc_n */ + __IO uint32_t ARM_HCLK_n : 1; /*!< soft_rst_arm_HCLK_n */ + __IO uint32_t _48_n : 1; /*!< soft_rst_48_n */ + __IO uint32_t UTM_n : 1; /*!< soft_rst_utmi_n */ + __IO uint32_t CACHE_n : 1; /*!< soft_rst_cache_n */ + __IO uint32_t USB_n : 1; /*!< soft_rst_cache_n */ + __IO uint32_t ETH_RX_n : 1; /*!< soft_rst_eth_rx_i_n */ + __IO uint32_t ETH_TX_n : 1; /*!< soft_rst_eth_tx_i_n */ + __IO uint32_t ADC_n : 1; /*!< soft_rst_adc_n */ + __IO uint32_t EFUSE_n : 1; /*!< soft_rst_efuse_n */ + __IO uint32_t Reserved1_n: 1; /*!< Reserved11 */ + __IO uint32_t AES_n : 1; /*!< soft_rst_aes_n */ + __IO uint32_t UART2_n : 1; /*!< soft_rst_uart2_n */ + __IO uint32_t AS_n : 1; /*!< soft_rst_as_n */ + __IO uint32_t FDCD_n : 1; /*!< soft_rst_fdcd_n */ + } SOFTRST_b; /*!< BitSize */ + }; +} SOFT_RESET_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define UART0_BASE 0x41005000UL +#define UART1_BASE 0x4100C000UL +#define UART2_BASE 0x4100E000UL +#define WDG_BASE 0x41001000UL +#define TIMER0_BASE 0x41000000UL +#define TIMER1_BASE 0x41000020UL +#define TIMER2_BASE 0x41000040UL +#define TIMER3_BASE 0x41000060UL +#define SPI0_BASE 0x41004000UL +#define SPI1_BASE 0x4100B000UL +#define I2C0_BASE 0x41003000UL +#define I2C1_BASE 0x4100A000UL +#define RTC_BASE 0x41007004UL +#define GPIO_BASE 0x41002000UL +#define NOR_FLASH_BASE 0x40800000UL +#define ADC_BASE 0x41006000UL +#define EFUSE_BASE 0x41008000UL +#define CAN0_BASE 0x41009000UL +#define CAN1_BASE 0x4100D000UL +#define DMA_BASE 0x41500000UL +#define ETH_BASE 0x41200000UL +#define USB_BASE 0x41300000UL +#define GLOBAL_CTRL_BASE 0x41007010UL +#define AES_BASE 0x41600000UL +#define DDRC_BASE 0x41400000UL +#define PDLOCK_BASE 0x41007000UL +#define PDPROT_BASE 0x41007C00UL +#define CFG_CTRL_BASE 0x41700000UL +#define SOFT_RESET_BASE 0x41007400UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define UART0 ((UART0_Type *) UART0_BASE) +#define UART1 ((UART0_Type *) UART1_BASE) +#define UART2 ((UART0_Type *) UART2_BASE) +#define WDG ((WDG_Type *) WDG_BASE) +#define TIMER0 ((TIMER0_Type *) TIMER0_BASE) +#define TIMER1 ((TIMER0_Type *) TIMER1_BASE) +#define TIMER2 ((TIMER0_Type *) TIMER2_BASE) +#define TIMER3 ((TIMER0_Type *) TIMER3_BASE) +#define SPI0 ((SPI0_Type *) SPI0_BASE) +#define SPI1 ((SPI0_Type *) SPI1_BASE) +#define I2C0 ((I2C0_Type *) I2C0_BASE) +#define I2C1 ((I2C0_Type *) I2C1_BASE) +#define RTC ((RTC_Type *) RTC_BASE) +#define GPIO ((GPIO_Type *) GPIO_BASE) +#define NOR_FLASH ((NOR_FLASH_Type *) NOR_FLASH_BASE) +#define ADC ((ADC_Type *) ADC_BASE) +#define EFUSE ((EFUSE_Type *) EFUSE_BASE) +#define CAN0 ((CAN0_Type *) CAN0_BASE) +#define CAN1 ((CAN0_Type *) CAN1_BASE) +#define DMA ((DMA_Type *) DMA_BASE) +#define ETH ((ETH_Type *) ETH_BASE) +#define USB ((USB_Type *) USB_BASE) +#define GLOBAL_CTRL ((GLOBAL_CTRL_Type *) GLOBAL_CTRL_BASE) +#define AES ((AES_Type *) AES_BASE) +#define DDRC ((DDRC_Type *) DDRC_BASE) +#define PDLOCK ((PDLOCK_Type *) PDLOCK_BASE) +#define PDPROT ((PDPROT_Type *) PDPROT_BASE) +#define CFG_CTRL ((CFG_CTRL_Type *) CFG_CTRL_BASE) +#define SOFT_RESET ((SOFT_RESET_Type *) SOFT_RESET_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group cmem7 */ +/** @} */ /* End of group (null) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* cmem7_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h index db3b45c0a2..28088028b2 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h @@ -43,7 +43,12 @@ #define _TIM #define _UART #define _USB -#define _WDG +#define _WDG + +//#define _MARVELL +//#define _IP1826D +#define _M7NORFLASH +#define _ME_6095_F #define USE_FULL_ASSERT 1 @@ -71,7 +76,9 @@ typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL; /** * System clock frequency, unit is Hz. */ -#define SYSTEM_CLOCK_FREQ 200000000 +#define SYSTEM_CLOCK_FREQ 300000000 +//250000000 +//300000000 /** * @brief usecond delay diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h index 4d8a46527a..a5663ea869 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h @@ -1,382 +1,417 @@ -/** - ***************************************************************************** - * @file cmem7_eth.h - * - * @brief CMEM7 ethernet header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_ETH_H -#define __CMEM7_ETH_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** @defgroup ETH_SPEED - * @{ - */ -#define ETH_SPEED_10M 0x0 -#define ETH_SPEED_100M 0x1 -#define ETH_SPEED_1000M 0x2 - -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M) || \ - ((SPEED) == ETH_SPEED_1000M)) -/** - * @} - */ - -/** @defgroup ETH_DUPLEX - * @{ - */ -#define ETH_DUPLEX_HALF 0x0 -#define ETH_DUPLEX_FULL 0x1 - -#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \ - ((DUPLEX) == ETH_DUPLEX_FULL)) -/** - * @} - */ - -/** @defgroup ETH_INT - * @{ - */ -#define ETH_INT_TX_COMPLETE_FRAME 0x0001 -#define ETH_INT_TX_STOP 0x0002 -#define ETH_INT_TX_BUF_UNAVAI 0x0004 -#define ETH_INT_RX_OVERFLOW 0x0010 -#define ETH_INT_TX_UNDERFLOW 0x0020 -#define ETH_INT_RX_COMPLETE_FRAME 0x0040 -#define ETH_INT_RX_BUF_UNAVAI 0x0080 -#define ETH_INT_RX_STOP 0x0100 -#define ETH_INT_BUS_FATAL_ERROR 0x2000 -#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \ - ETH_INT_TX_STOP | \ - ETH_INT_TX_BUF_UNAVAI | \ - ETH_INT_RX_OVERFLOW | \ - ETH_INT_TX_UNDERFLOW | \ - ETH_INT_RX_COMPLETE_FRAME | \ - ETH_INT_RX_BUF_UNAVAI | \ - ETH_INT_RX_STOP | \ - ETH_INT_BUS_FATAL_ERROR) - -#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0)) -/** - * @} - */ - -/** - * @brief EFUSE receive filter structure - */ -typedef struct -{ - BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */ - BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */ - BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */ - BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */ - BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */ - uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */ -} ETH_FrameFilter; - -/** - * @brief Ethernet initialization structure - */ -typedef struct -{ - BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */ - uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */ - uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */ - BOOL ETH_RxEn; /*!< Rx enable */ - BOOL ETH_TxEn; /*!< Tx enable */ - BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */ - BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */ - uint8_t ETH_MacAddr[6]; /*!< MAC address */ - ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */ -} ETH_InitTypeDef; - -/** - * @brief Ethernet Tx descriptor structure - */ -typedef struct { - union { - uint32_t TX0; - - struct { - uint32_t : 1; - uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */ - uint32_t : 1; - uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */ - uint32_t : 1; - uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */ - uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */ - uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */ - uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */ - uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */ - uint32_t : 2; - uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */ - uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */ - uint32_t : 8; - uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */ - uint32_t : 2; - uint32_t FS : 1; /*!< first segment flag */ - uint32_t LS : 1; /*!< last segment flag */ - uint32_t : 2; - } TX0_b; - } TX_0; - - union { - uint32_t TX1; - - struct { - uint32_t SIZE : 13; /*!< buffer size */ - uint32_t : 19; - } TX1_b; - } TX_1; - - uint32_t bufAddr; /*!< address of buffer */ - uint32_t nextDescAddr; /*!< address of next descriptor */ - uint64_t reserved; - uint64_t timeStamp; /*!< time stamp while last segment */ -} ETH_TX_DESC; - -/** - * @brief Ethernet Rx descriptor structure - */ -typedef struct { - union { - uint32_t RX0; - - struct { - uint32_t : 1; - uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */ - uint32_t : 5; - uint32_t TTSE : 1; /*!< timestamp available while last segment */ - uint32_t LS : 1; /*!< last segment flag */ - uint32_t FS : 1; /*!< first segment flag */ - uint32_t : 1; - uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */ - uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */ - uint32_t : 2; - uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */ - uint32_t FL : 14; /*!< frame length while last segment */ - uint32_t : 2; - } RX0_b; - } RX_0; - - union { - uint32_t RX1; - - struct { - uint32_t SIZE : 13; /*!< buffer size */ - uint32_t : 19; - } RX1_b; - } RX_1; - - uint32_t bufAddr; /*!< buffer address */ - uint32_t nextDescAddr; /*!< address of next descriptor */ - uint64_t reserved; - uint64_t timeStamp; /*!< time stamp while the last segment */ -} ETH_RX_DESC; - -/** - * @brief Read data from phy chip - * @param[in] phyAddr Address of phy chip - * @param[in] phyReg Address of phy's register to be read - * @retval uint32_t value of phy's register - */ -uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg); - -/** - * @brief Write data to phy chip - * @param[in] phyAddr Address of phy chip - * @param[in] phyReg Address of phy's register to be written - * @param[in] data Data to be written - * @retval None - */ -void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data); - -/** - * @brief Ethernet initialization - * @note This function should be called at first before any other interfaces. - * @param[in] init A pointer to structure ETH_InitTypeDef - * @retval BOOL The bit indicates if ethernet is initialized successfully - */ -BOOL ETH_Init(ETH_InitTypeDef *init); - -/** - * @brief Enable or disable ethernet interrupt. - * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT - * @param[in] Enable The bit indicates if specific interrupts are enable or not - * @retval None - */ -void ETH_EnableInt(uint32_t Int, BOOL enable); - -/** - * @brief Check specific interrupts are set or not - * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT - * @retval BOOL The bit indicates if specific interrupts are set or not - */ -BOOL ETH_GetIntStatus(uint32_t Int); - -/** - * @brief Clear specific interrupts - * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT - * @retval None - */ -void ETH_ClearInt(uint32_t Int); - -/** - * @brief Get ethernte MAC address - * @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes. - * @retval None - */ -void ETH_GetMacAddr(uint8_t *mac); - -/** - * @brief Set ethernet transmission descriptor ring - * @note Make sure that memory occupied by descriptors should be in physical - * memory and keep valid before ethernet transmission is finished. - * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node - * has a 'nextDescAddr' pointed to first node. - * @retval BOOL The bit indicates if valid ring is set - */ -BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring); - -/** - * @brief Start ethernet transmission - * @param None - * @retval None - */ -void ETH_StartTx(void); - -/** - * @brief Stop ethernet transmission - * @param None - * @retval None - */ -void ETH_StopTx(void); - -/** - * @brief Resume ethernet transmission\n - * While ethernet doesn't have enough buffer to transmit data, it will - * pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users - * must call this function to start ethernet again after new buffer - * prepared. - * @param None - * @retval None - */ -void ETH_ResumeTx(void); - -/** - * @brief Get free transmission descriptor\n - * @param None - * @retval ETH_TX_DESC* A pointer of free transmission descriptor, - * NULL if no free descriptor - */ -ETH_TX_DESC *ETH_AcquireFreeTxDesc(void); - -/** - * @brief Check if a transmission descriptor is free or not - * @param desc A pointer of a transmission descriptor - * @retval BOOL True if the transmission descriptor is free, or flase. - */ -BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc); - -/** - * @brief Release a transmission descriptor to ethernet\n - * After users prepared data in the buffer of a free descriptor, - * They must call this function to change ownership of the - * descriptor to hardware. - * @param desc A pointer of a transmission descriptor - * @retval None - */ -void ETH_ReleaseTxDesc(ETH_TX_DESC *desc); - -/** - * @brief Set ethernet receive descriptor ring - * @note Make sure that memory occupied by descriptors should be in physical - * memory and keep valid before ethernet receive is finished. - * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node - * has a 'nextDescAddr' pointed to first node. - * @retval BOOL The bit indicates if valid ring is set - */ -BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring); - -/** - * @brief Start ethernet receive - * @param None - * @retval None - */ -void ETH_StartRx(void); - -/** - * @brief Stop ethernet receive - * @param None - * @retval None - */ -void ETH_StopRx(void); - -/** - * @brief Resume ethernet receive\n - * While ethernet doesn't have enough buffer to receive data, it will - * pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users - * must call this function to start ethernet again after new buffer - * prepared. - * @param None - * @retval None - */ -void ETH_ResumeRx(void); - -/** - * @brief Get the free descriptor which contains received data\n - * @param None - * @retval ETH_RX_DESC* A pointer of free receive descriptor, - * NULL if no free descriptor - */ -ETH_RX_DESC *ETH_AcquireFreeRxDesc(void); - -/** - * @brief Check if a receive descriptor is free or not - * @param desc A pointer of a receive descriptor - * @retval BOOL True if the receive descriptor is free, or flase. - */ -BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc); - -/** - * @brief Release a receive descriptor to ethernet\n - * After users handled data in the buffer of a free descriptor, - * They must call this function to change ownership of the - * descriptor to hardware. - * @param desc A pointer of a transmission descriptor - * @retval None - */ -void ETH_ReleaseRxDesc(ETH_RX_DESC *desc); - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_ETH_H */ - +/** + ***************************************************************************** + * @file cmem7_eth.h + * + * @brief CMEM7 ethernet header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_ETH_H +#define __CMEM7_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** @defgroup ETH_SPEED + * @{ + */ +#define ETH_SPEED_10M 0x0 +#define ETH_SPEED_100M 0x1 +#define ETH_SPEED_1000M 0x2 + +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ + ((SPEED) == ETH_SPEED_100M) || \ + ((SPEED) == ETH_SPEED_1000M)) +/** + * @} + */ + +/** @defgroup ETH_DUPLEX + * @{ + */ +#define ETH_DUPLEX_HALF 0x0 +#define ETH_DUPLEX_FULL 0x1 + +#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \ + ((DUPLEX) == ETH_DUPLEX_FULL)) +/** + * @} + */ + +/** @defgroup ETH_INT + * @{ + */ +#define ETH_INT_TX_COMPLETE_FRAME 0x0001 +#define ETH_INT_TX_STOP 0x0002 +#define ETH_INT_TX_BUF_UNAVAI 0x0004 +#define ETH_INT_RX_OVERFLOW 0x0010 +#define ETH_INT_TX_UNDERFLOW 0x0020 +#define ETH_INT_RX_COMPLETE_FRAME 0x0040 +#define ETH_INT_RX_BUF_UNAVAI 0x0080 +#define ETH_INT_RX_STOP 0x0100 +#define ETH_INT_BUS_FATAL_ERROR 0x2000 +#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \ + ETH_INT_TX_STOP | \ + ETH_INT_TX_BUF_UNAVAI | \ + ETH_INT_RX_OVERFLOW | \ + ETH_INT_TX_UNDERFLOW | \ + ETH_INT_RX_COMPLETE_FRAME | \ + ETH_INT_RX_BUF_UNAVAI | \ + ETH_INT_RX_STOP | \ + ETH_INT_BUS_FATAL_ERROR) + +#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0)) +/** + * @} + */ +/** + * @brief EFUSE receive filter structure + */ +typedef struct +{ + BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */ + BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */ + BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */ + BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */ + BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */ + uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */ +} ETH_FrameFilter; + +/** + * @brief Ethernet initialization structure + */ +typedef struct +{ + BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */ + uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */ + uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */ + BOOL ETH_RxEn; /*!< Rx enable */ + BOOL ETH_TxEn; /*!< Tx enable */ + BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */ + BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */ + uint8_t ETH_MacAddr[6]; /*!< MAC address */ + ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */ +} ETH_InitTypeDef; + +/** + * @brief Ethernet Tx descriptor structure + */ +typedef struct { + union { + uint32_t TX0; + + struct { + uint32_t : 1; + uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */ + uint32_t : 1; + uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */ + uint32_t : 1; + uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */ + uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */ + uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */ + uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */ + uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */ + uint32_t : 2; + uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */ + uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */ + uint32_t : 8; + uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */ + uint32_t : 2; + uint32_t FS : 1; /*!< first segment flag */ + uint32_t LS : 1; /*!< last segment flag */ + uint32_t : 2; + } TX0_b; + } TX_0; + + union { + uint32_t TX1; + + struct { + uint32_t SIZE : 13; /*!< buffer size */ + uint32_t : 19; + } TX1_b; + } TX_1; + + uint32_t bufAddr; /*!< address of buffer */ + uint32_t nextDescAddr; /*!< address of next descriptor */ + uint64_t reserved; + uint64_t timeStamp; /*!< time stamp while last segment */ +} ETH_TX_DESC; + +/** + * @brief Ethernet Rx descriptor structure + */ +typedef struct { + union { + uint32_t RX0; + + struct { + uint32_t : 1; + uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */ + uint32_t : 5; + uint32_t TTSE : 1; /*!< timestamp available while last segment */ + uint32_t LS : 1; /*!< [OUT] last segment flag */ + uint32_t FS : 1; /*!< [OUT] first segment flag */ + uint32_t : 1; + uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */ + uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */ + uint32_t : 2; + uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */ + uint32_t FL : 14; /*!< [OUT] frame length while last segment */ + uint32_t : 2; + } RX0_b; + } RX_0; + + union { + uint32_t RX1; + + struct { + uint32_t SIZE : 13; /*!< buffer size */ + uint32_t : 19; + } RX1_b; + } RX_1; + + uint32_t bufAddr; /*!< buffer address */ + uint32_t nextDescAddr; /*!< address of next descriptor */ + uint64_t reserved; + uint64_t timeStamp; /*!< time stamp while the last segment */ +} ETH_RX_DESC; + +/** + * @brief Read data from phy chip + * @param[in] phyAddr Address of phy chip + * @param[in] phyReg Address of phy's register to be read + * @retval uint32_t value of phy's register + */ +uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg); + +/** + * @brief Write data to phy chip + * @param[in] phyAddr Address of phy chip + * @param[in] phyReg Address of phy's register to be written + * @param[in] data Data to be written + * @retval None + */ +void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data); +/** + * @brief Fills each ETH_InitStruct member with its default value. + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void ETH_StructInit(ETH_InitTypeDef* init); +/** + * @brief Ethernet initialization + * @note This function should be called at first before any other interfaces. + * @param[in] init A pointer to structure ETH_InitTypeDef + * @retval BOOL The bit indicates if ethernet is initialized successfully + */ +BOOL ETH_Init(ETH_InitTypeDef *init); + +/** + * @brief Enable or disable ethernet interrupt. + * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT + * @param[in] Enable The bit indicates if specific interrupts are enable or not + * @retval None + */ +void ETH_ITConfig(uint32_t Int, BOOL enable); + +/** + * @brief Check specific interrupts are set or not + * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT + * @retval BOOL The bit indicates if specific interrupts are set or not + */ +BOOL ETH_GetITStatus(uint32_t Int); + +/** + * @brief Clear specific interrupts + * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT + * @retval None + */ +void ETH_ClearITPendingBit(uint32_t Int); + +/** + * @brief Get ethernte MAC address + * @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes. + * @retval None + */ +void ETH_GetMacAddr(uint8_t *mac); + +/** + * @brief Set ethernet transmission descriptor ring + * @note Make sure that memory occupied by descriptors should be in physical + * memory and keep valid before ethernet transmission is finished. + * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node + * has a 'nextDescAddr' pointed to first node. + * @retval BOOL The bit indicates if valid ring is set + */ +BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring); + +/** + * @brief Start ethernet transmission + * @param None + * @retval None + */ +void ETH_StartTx(void); + +/** + * @brief Stop ethernet transmission + * @param None + * @retval None + */ +void ETH_StopTx(void); + +/** + * @brief Resume ethernet transmission\n + * While ethernet doesn't have enough buffer to transmit data, it will + * pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users + * must call this function to start ethernet again after new buffer + * prepared. + * @param None + * @retval None + */ +void ETH_ResumeTx(void); + +/** + * @brief Get free transmission descriptor\n + * @param None + * @retval ETH_TX_DESC* A pointer of free transmission descriptor, + * NULL if no free descriptor + */ +ETH_TX_DESC *ETH_AcquireFreeTxDesc(void); + +/** + * @brief Check if a transmission descriptor is free or not + * @param[in] desc A pointer of a transmission descriptor + * @retval BOOL True if the transmission descriptor is free, or flase. + */ +BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc); + +/** + * @brief Release a transmission descriptor to ethernet\n + * After users prepared data in the buffer of a free descriptor, + * They must call this function to change ownership of the + * descriptor to hardware. + * @param[in] desc A pointer of a transmission descriptor + * @retval None + */ +void ETH_ReleaseTxDesc(ETH_TX_DESC *desc); + +/** + * @brief Set buffer address of the specific TX descriptor + * @param[in] desc A pointer of a transmission descriptor + * @param[in] bufAddr buffer address to be sent + * @retval None + */ +void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr); + +/** + * @brief Get buffer address of the specific TX descriptor + * @param[in] desc A pointer of a transmission descriptor + * @retval uint32_t buffer address to be gotten + */ +uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc); + +/** + * @brief Set ethernet receive descriptor ring + * @note Make sure that memory occupied by descriptors should be in physical + * memory and keep valid before ethernet receive is finished. + * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node + * has a 'nextDescAddr' pointed to first node. + * @retval BOOL The bit indicates if valid ring is set + */ +BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring); + +/** + * @brief Start ethernet receive + * @param None + * @retval None + */ +void ETH_StartRx(void); + +/** + * @brief Stop ethernet receive + * @param None + * @retval None + */ +void ETH_StopRx(void); + +/** + * @brief Resume ethernet receive\n + * While ethernet doesn't have enough buffer to receive data, it will + * pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users + * must call this function to start ethernet again after new buffer + * prepared. + * @param None + * @retval None + */ +void ETH_ResumeRx(void); + +/** + * @brief Get the free descriptor which contains received data\n + * @param None + * @retval ETH_RX_DESC* A pointer of free receive descriptor, + * NULL if no free descriptor + */ +ETH_RX_DESC *ETH_AcquireFreeRxDesc(void); + +/** + * @brief Check if a receive descriptor is free or not + * @param[in] desc A pointer of a receive descriptor + * @retval BOOL True if the receive descriptor is free, or flase. + */ +BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc); + +/** + * @brief Release a receive descriptor to ethernet\n + * After users handled data in the buffer of a free descriptor, + * They must call this function to change ownership of the + * descriptor to hardware. + * @param[in] desc A pointer of a transmission descriptor + * @retval None + */ +void ETH_ReleaseRxDesc(ETH_RX_DESC *desc); + +/** + * @brief Set buffer address of the specific RX descriptor + * @param[in] desc A pointer of a receive descriptor + * @param[in] bufAddr buffer address to be received + * @retval None + */ +void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr); + +/** + * @brief Get buffer address of the specific RX descriptor + * @param[in] desc A pointer of a receive descriptor + * @retval uint32_t buffer address to be gotten + */ +uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc); + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_ETH_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h index 477cc59212..b2ef305965 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h @@ -200,7 +200,15 @@ void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data); * @param[out] data A pointer to the data to be written * @retval None */ -void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data); +void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data); + + +void flash_WaitInWritting(void) ; + +void flash_WaitReadFifoNotEmpty(void); + +uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ; + #ifdef __cplusplus } diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h index 836bc2f7b6..e76d9d42d2 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h @@ -139,6 +139,17 @@ void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLev * @retval None */ void GPIO_EnablePwm(uint8_t Channel, BOOL Enable); + + + +/** + xjf 20150324 + +**/ +void GPIO_SetBits(uint32_t mask); +void GPIO_clrBits(uint32_t mask); +uint32_t GPIO_getBits(uint32_t mask); + #ifdef __cplusplus } diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h index a7e6cc2cc4..54d608dc41 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h @@ -101,6 +101,16 @@ #ifdef _WDG #include "cmem7_wdg.h" #endif + + +#ifdef _MARVELL + #include + #include +#endif + +#ifdef _IP1826D + #include +#endif #ifdef __cplusplus } diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h index d0b980aa72..43744c2625 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h @@ -1,236 +1,276 @@ -/** - ***************************************************************************** - * @file cmem7_misc.h - * - * @brief CMEM7 miscellaneous header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_MISC_H -#define __CMEM7_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** - * @brief NVIC initialization structure - */ -/** -@code - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endcode - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete Capital-micro Devices IRQ Channels list, please - refer to cmem7.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - - -/** @defgroup NVIC_VectTab - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup NVIC_LP - * @{ - */ -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup NVIC_PriorityGroup - * @{ - */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) -/** - * @} - */ - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values, ref as @ref NVIC_VectTab: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple - * of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values, ref as @ref NVIC_LP: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState); - -/** - * @brief Memory map from address 'from' to 'address 'to' and open icache or not - * @param[in] from address to be mapped from - * @param[in] to address to be mapped to - * @param[in] isIcacheOn icache is on or off - * @retval None - */ -void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn); - -/** - * @brief Set NMI irq number, it should be one of @ref IRQn_Type. - * @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI - * interrupt routine if the specific 'irq' occurs. By default, NMI irq number - * is 0, same as ETH_INT_IRQn - * @param[in] irq irq number - * @retval None - */ -void GLB_SetNmiIrqNum(uint32_t irq); - -/** @defgroup SYS_CLK_SEL - * @{ - */ -#define SYS_CLK_SEL_OSC 0x0 -#define SYS_CLK_SEL_DLL 0x1 -#define SYS_CLK_SEL_CRYSTAL 0x2 -#define SYS_CLK_SEL_EXTERNAL 0x3 -/** - * @} - */ - -/** - * @brief Select system clock source, it should be one of @ref SYS_CLK_SEL. - * @Note You MUST make sure externel clock has been stabled if clock - * source is external before call this function. - * Default value is SYS_CLK_SEL_OSC - * @param[in] irq irq number - * @retval None - */ -void GLB_SelectSysClkSource(uint8_t source); - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_MISC_H */ - +/** + ***************************************************************************** + * @file cmem7_misc.h + * + * @brief CMEM7 miscellaneous header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_MISC_H +#define __CMEM7_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** + * @brief NVIC initialization structure + */ +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete Capital-micro Devices IRQ Channels list, please + refer to cmem7.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + + +/** @defgroup NVIC_VectTab + * @{ + */ + +#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000) +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \ + ((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup NVIC_LP + * @{ + */ +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup NVIC_PriorityGroup + * @{ + */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) +/** + * @} + */ + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values, ref as @ref NVIC_VectTab: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple + * of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values, ref as @ref NVIC_LP: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState); + +/** + * @brief Memory map from address 'from' to 'address 'to' and open icache or not + * @param[in] from address to be mapped from + * @param[in] to address to be mapped to + * @param[in] isIcacheOn icache is on or off + * @retval None + */ +void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn); + +/** + * @brief Convert the mapping destination address to source address + * @param[in] to address to be mapped to + * @retval uint32_t address to be mapped from + */ +uint32_t GLB_ConvertToMappingFromAddr(uint32_t to); + +/** + * @brief Convert the mapping source address to destination address + * @param[in] from address to be mapped from + * @retval uint32_t address to be mapped to + */ +uint32_t GLB_ConvertToMappingToAddr(uint32_t from); + +/** + * @brief Set NMI irq number, it should be one of @ref IRQn_Type. + * @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI + * interrupt routine if the specific 'irq' occurs. By default, NMI irq number + * is 0, same as ETH_INT_IRQn + * @param[in] irq irq number + * @retval None + */ +void GLB_SetNmiIrqNum(uint32_t irq); + +/** @defgroup SYS_CLK_SEL + * @{ + */ +#define SYS_CLK_SEL_OSC 0x0 +#define SYS_CLK_SEL_DLL 0x1 +#define SYS_CLK_SEL_CRYSTAL 0x2 +#define SYS_CLK_SEL_EXTERNAL 0x3 +/** + * @} + */ + +/** + * @brief Select system clock source, it should be one of @ref SYS_CLK_SEL. + * @Note You MUST make sure externel clock has been stabled if clock + * source is external before call this function. + * Default value is SYS_CLK_SEL_OSC + * @param[in] irq irq number + * @retval None + */ +void GLB_SelectSysClkSource(uint8_t source); + +/** + * @brief Simulate instruction 'STRB' or 'STRH' with 'BFI' + * @Note In M7, you have to write a register in 32-bit alignment, + * not in 8-bit or 16-bit. + * @param[in] addr register address to be written + * @param[in] value value to be written + * @param[in] lsb LSB in register to be written + * @param[in] len bit length to be written + * @retval None + */ + + +//#define aaaa(len) __asm("LDR len, 11") + +#define CMEM7_BFI(addr, value, lsb, len) \ + do { \ + unsigned long tmp; \ + unsigned long tmp1 = (unsigned long)addr; \ + \ + __asm("LDR tmp, [tmp1]\n" \ + "BFI tmp, "#value", "#lsb", "#len" \n" \ + "STR tmp, [tmp1]\n"); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_MISC_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h index bb04de5d83..00d5d74520 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h @@ -1,89 +1,89 @@ -/** - ***************************************************************************** - * @file cmem7_rtc.h - * - * @brief CMEM7 RTC header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_RTC_H -#define __CMEM7_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** @defgroup RTC_Int - * @{ - */ -#define RTC_Int_Second ((uint32_t)0x00000001) -#define RTC_Int_Microsecond ((uint32_t)0x00000002) -#define RTC_Int_All ((uint32_t)0x00000003) -#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0)) -/** - * @} - */ - -/** - * @brief Enable or disable RTC interrupt. - * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int - * @param[in] Enable The bit indicates if specific interrupts are enable or not - * @retval None - */ -void RTC_EnableInt(uint32_t Int, BOOL Enable); - -/** - * @brief Check specific interrupts are set or not - * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int - * @retval BOOL The bit indicates if specific interrupts are set or not - */ -BOOL RTC_GetIntStatus(uint32_t Int); - -/** - * @brief Clear specific interrupts - * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int - * @retval None - */ -void RTC_ClearInt(uint32_t Int); - -/** - * @brief Get seconds since power up - * @param None - * @retval uint32_t Seconds since power up - */ -uint32_t RTC_GetSecond(void); - -/** - * @brief Get current micro-seconds - * @param None - * @retval uint32_t Current micro-seconds - */ -uint16_t RTC_GetMicroSecond(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_RTC_H */ - +/** + ***************************************************************************** + * @file cmem7_rtc.h + * + * @brief CMEM7 RTC header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_RTC_H +#define __CMEM7_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** @defgroup RTC_Int + * @{ + */ +#define RTC_Int_Second ((uint32_t)0x00000001) +#define RTC_Int_Millsecond ((uint32_t)0x00000002) +#define RTC_Int_All ((uint32_t)0x00000003) +#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0)) +/** + * @} + */ + +/** + * @brief Enable or disable RTC interrupt. + * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int + * @param[in] Enable The bit indicates if specific interrupts are enable or not + * @retval None + */ +void RTC_ITConfig(uint32_t Int, BOOL Enable); + +/** + * @brief Check specific interrupts are set or not + * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int + * @retval BOOL The bit indicates if specific interrupts are set or not + */ +BOOL RTC_GetITStatus(uint32_t Int); + +/** + * @brief Clear specific interrupts + * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t Int); + +/** + * @brief Get seconds since power up + * @param None + * @retval uint32_t Seconds since power up + */ +uint32_t RTC_GetSecond(void); + +/** + * @brief Get current millseconds + * @param None + * @retval uint32_t Current millseconds + */ +uint16_t RTC_GetMillSecond(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_RTC_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h index 86fecbe8fa..5abf7ba0d8 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h @@ -1,103 +1,110 @@ -/** - ***************************************************************************** - * @file cmem7_wdg.h - * - * @brief CMEM7 watchdog header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_WDG_H -#define __CMEM7_WDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** @defgroup WDG_INT - * @{ - */ -#define WDG_INT_QUARTER 0 -#define WDG_INT_HALF 1 -#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \ - ((INT) == WDG_INT_HALF)) -/** - * @} - */ - -/** @defgroup WDG_TRIGGER_MODE - * @{ - */ -#define WDG_TRIGGER_MODE_EDGE 0 -#define WDG_TRIGGER_MODE_LEVEL 1 -#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \ - ((TRI) == WDG_TRIGGER_MODE_LEVEL)) -/** - * @} - */ - -/** - * @brief Watchdog initialization - * @note This function should be called at first before any other interfaces. - * @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE - * @param[in] ResetMicroSecond MicroSeconds lasts before global reset - * @retval None - */ -void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond); - -/** - * @brief Enable or disable watchdog interrupt. - * @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT - * @param[in] Enable The bit indicates if the specific interrupt are enable or not - * @retval None - */ -void WDG_EnableInt(uint8_t Int, BOOL Enable); - -/** - * @brief Check the specific interrupt are set or not - * @param None - * @retval BOOL The bit indicates if the specific interrupt are set or not - */ -BOOL WDG_GetIntStatus(void); - -/** - * @brief Clear the specific interrupt - * @param None - * @retval None - */ -void WDG_ClearInt(void); - -/** - * @brief Enable or disable watchdog. - * @param[in] Enable The bit indicates if watchdog is enable or not - * @retval None - */ -void WDG_Enable(BOOL Enable); - - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_WDG_H */ - +/** + ***************************************************************************** + * @file cmem7_wdg.h + * + * @brief CMEM7 watchdog header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_WDG_H +#define __CMEM7_WDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** @defgroup WDG_INT + * @{ + */ +#define WDG_INT_QUARTER 0 +#define WDG_INT_HALF 1 +#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \ + ((INT) == WDG_INT_HALF)) +/** + * @} + */ + +/** @defgroup WDG_TRIGGER_MODE + * @{ + */ +#define WDG_TRIGGER_MODE_EDGE 0 +#define WDG_TRIGGER_MODE_LEVEL 1 +#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \ + ((TRI) == WDG_TRIGGER_MODE_LEVEL)) +/** + * @} + */ + +/** + * @brief Deinitializes the Watchdog peripheral registers to their default reset values. + * @param[in] None + * @retval None + */ +void WDG_DeInit(void); + +/** + * @brief Watchdog initialization + * @note This function should be called at first before any other interfaces. + * @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE + * @param[in] ResetMillSecond MillSeconds lasts before global reset + * @retval None + */ +void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond); + +/** + * @brief Enable or disable watchdog interrupt. + * @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT + * @param[in] Enable The bit indicates if the specific interrupt are enable or not + * @retval None + */ +void WDG_ITConfig(uint8_t Int, BOOL Enable); + +/** + * @brief Check the specific interrupt are set or not + * @param None + * @retval BOOL The bit indicates if the specific interrupt are set or not + */ +BOOL WDG_GetITStatus(void); + +/** + * @brief Clear the specific interrupt + * @param None + * @retval None + */ +void WDG_ClearITPendingBit(void); + +/** + * @brief Enable or disable watchdog. + * @param[in] Enable The bit indicates if watchdog is enable or not + * @retval None + */ +void WDG_Cmd(BOOL Enable); + + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_WDG_H */ + From b25e602afb4cb01974e19edd95ab701c55b3ca53 Mon Sep 17 00:00:00 2001 From: Alex Date: Wed, 13 May 2015 08:50:14 +0800 Subject: [PATCH 10/18] fix a eth driver bug to avoid crush fix a eth driver bug to avoid crush --- bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h | 16028 ++++++++-------- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h | 14 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h | 834 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h | 16 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h | 22 +- .../StdPeriph_Driver/inc/cmem7_includes.h | 20 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h | 552 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h | 178 +- bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h | 220 +- bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c | 9 +- bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c | 75 + bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c | 46 +- bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c | 10 +- bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c | 17 +- bsp/CME_M7/drivers/emac.c | 34 +- bsp/CME_M7/project.uvopt | 1527 +- bsp/CME_M7/project.uvproj | 309 +- 17 files changed, 10672 insertions(+), 9239 deletions(-) diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h index 0f2d0cf3c0..83d7476753 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7.h @@ -1,8014 +1,8014 @@ - -/****************************************************************************************************//** - * @file cmem7.h - * - * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for - * cmem7 from . - * - * @version V1.0 - * @date 5. January 2015 - * - * @note Generated with SVDConv V2.75 - * from CMSIS SVD File 'SVDConv_CME_M7.svd' Version 1.0, - *******************************************************************************************************/ - - - -/** @addtogroup (null) - * @{ - */ - -/** @addtogroup cmem7 - * @{ - */ - -#ifndef CMEM7_H -#define CMEM7_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- cmem7 Specific Interrupt Numbers ---------------------- */ - ETH_INT_IRQn = 0, /*!< 0 ETH_INT */ - USB_INT_IRQn = 1, /*!< 1 USB_INT */ - DMA_INT_IRQn = 2, /*!< 2 DMA_INT */ - CAN0_INT_IRQn = 3, /*!< 3 CAN0_INT */ - CAN1_INT_IRQn = 4, /*!< 4 CAN1_INT */ - FP0_INT_IRQn = 5, /*!< 5 FP0_INT */ - FP1_INT_IRQn = 6, /*!< 6 FP1_INT */ - FP2_INT_IRQn = 7, /*!< 7 FP2_INT */ - FP3_INT_IRQn = 8, /*!< 8 FP3_INT */ - FP4_INT_IRQn = 9, /*!< 9 FP4_INT */ - FP5_INT_IRQn = 10, /*!< 10 FP5_INT */ - FP6_INT_IRQn = 11, /*!< 11 FP6_INT */ - FP7_INT_IRQn = 12, /*!< 12 FP7_INT */ - FP8_INT_IRQn = 13, /*!< 13 FP8_INT */ - FP9_INT_IRQn = 14, /*!< 14 FP9_INT */ - FP10_INT_IRQn = 15, /*!< 15 FP10_INT */ - FP11_INT_IRQn = 16, /*!< 16 FP11_INT */ - FP12_INT_IRQn = 17, /*!< 17 FP12_INT */ - FP13_INT_IRQn = 18, /*!< 18 FP13_INT */ - FP14_INT_IRQn = 19, /*!< 19 FP14_INT */ - FP15_INT_IRQn = 20, /*!< 20 FP15_INT */ - UART0_INT_IRQn = 21, /*!< 21 UART0_INT */ - UART1_INT_IRQn = 22, /*!< 22 UART1_INT */ - ADC_INT_IRQn = 23, /*!< 23 ADC_INT */ - GPIO_INT_IRQn = 24, /*!< 24 GPIO_INT */ - SPI1_INT_IRQn = 25, /*!< 25 SPI1_INT */ - I2C1_INT_IRQn = 26, /*!< 26 I2C1_INT */ - SPI0_INT_IRQn = 27, /*!< 27 SPI0_INT */ - I2C0_INT_IRQn = 28, /*!< 28 I2C0_INT */ - RTC_1S_INT_IRQn = 29, /*!< 29 RTC_1S_INT */ - RTC_1MS_INT_IRQn = 30, /*!< 30 RTC_1MS_INT */ - WDG_INT_IRQn = 31, /*!< 31 WDG_INT */ - TIMER_INT_IRQn = 32, /*!< 32 TIMER_INT */ - DDRC_SW_PROC_IRQn = 33, /*!< 33 DDRC_SW_PROC */ - ETH_PMT_INT_IRQn = 34, /*!< 34 ETH_PMT_INT */ - PAD_INT_IRQn = 35, /*!< 35 PAD_INT */ - DDRC_LANE_SYNC_IRQn = 36, /*!< 36 DDRC_LANE_SYNC */ - UART2_INT_IRQn = 37 /*!< 37 UART2_INT */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */ -#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 0 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include /*!< Cortex-M3 processor and core peripherals */ -#include "system_cmem7.h" /*!< cmem7 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - - -/* ================================================================================ */ -/* ================ UART0 ================ */ -/* ================================================================================ */ - - -/** - * @brief asynchronous serial controller 0 (UART0) - */ - -typedef struct { /*!< UART0 Structure */ - __IO uint16_t BAUDRATE; /*!< baudrate Register */ - __I uint16_t RESERVED0; - __IO uint16_t TX_BUF; /*!< transmit buffer Register */ - __I uint16_t RESERVED1; - __I uint16_t RX_BUF; /*!< receive buffer Register */ - __I uint16_t RESERVED2; - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t MODE : 3; /*!< asc mode control */ - __IO uint32_t STOP : 2; /*!< number of stop bits selection */ - __IO uint32_t PARITY : 1; /*!< parity selection */ - __IO uint32_t LOOPBACK : 1; /*!< loopback mode enable bit */ - uint32_t : 1; - __IO uint32_t RX_EN : 1; /*!< receive enable bit */ - uint32_t : 1; - __IO uint32_t FIFO_EN : 1; /*!< FIFO enable bit */ - __IO uint32_t CTS : 1; /*!< Clear to send, enable signal to send */ - __IO uint32_t BAUD_MODE : 1; /*!< baudrate generation mode */ - __IO uint32_t RX_THRESHOLD: 5; /*!< receive threshold */ - __IO uint32_t RX_HALF_FULL: 5; /*!< receive fifi half full level */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< interrupt mask register */ - - struct { - __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ - __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ - __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ - __IO uint32_t PE : 1; /*!< parity error interrupt */ - __IO uint32_t FE : 1; /*!< frame error interrupt */ - __IO uint32_t OE : 1; /*!< overrun error interrupt */ - __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ - } INT_MASK_b; /*!< BitSize */ - }; - - union { - __IO uint32_t STATUS; /*!< status register */ - - struct { - __IO uint32_t RNE : 1; /*!< receiver FIFO not empty */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty */ - __IO uint32_t TOE : 1; /*!< time out when the receiver FIFO is empty */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full */ - __IO uint32_t TF : 1; /*!< transmitter FIFO is full */ - } STATUS_b; /*!< BitSize */ - }; - __IO uint8_t TIMEOUT; /*!< timeout Register */ - __I uint8_t RESERVED3[3]; - - union { - __IO uint32_t TX_RESET; /*!< transmit reset Register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } TX_RESET_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RX_RESET; /*!< receive reset Register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } RX_RESET_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RUN; /*!< uart enable register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } RUN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< raw interrupt before mask register */ - - struct { - __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ - __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ - __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ - __IO uint32_t PE : 1; /*!< parity error interrupt */ - __IO uint32_t FE : 1; /*!< frame error interrupt */ - __IO uint32_t OE : 1; /*!< overrun error interrupt */ - __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ - } INT_RAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_SEEN; /*!< interrupt after mask register */ - - struct { - __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ - __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ - __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ - __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ - __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ - __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ - __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ - __IO uint32_t PE : 1; /*!< parity error interrupt */ - __IO uint32_t FE : 1; /*!< frame error interrupt */ - __IO uint32_t OE : 1; /*!< overrun error interrupt */ - __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ - } INT_SEEN_b; /*!< BitSize */ - }; -} UART0_Type; - - -/* ================================================================================ */ -/* ================ WDG ================ */ -/* ================================================================================ */ - - -/** - * @brief watchdog (WDG) - */ - -typedef struct { /*!< WDG Structure */ - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t EN : 1; /*!< flag indicates if watchdog is enabled or not */ - __IO uint32_t INT_LEN : 1; /*!< watchdog report interrupt when COUNTER is 1/4 or 1/2 of LENGTH */ - } CTRL_b; /*!< BitSize */ - }; - __IO uint32_t LEN; /*!< Ticks decrease down to 25% or 50% to trigger an interrupt */ - - union { - __IO uint32_t INT_CTRL; /*!< interrupt control */ - - struct { - __IO uint32_t MASK : 1; /*!< mask register */ - __IO uint32_t TRIGGER_MODE: 1; /*!< trigger mode */ - } INT_CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STA; /*!< interrupt status register */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_STA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw register */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_RAW_b; /*!< BitSize */ - }; - __I uint32_t CNT; /*!< counter register */ -} WDG_Type; - - -/* ================================================================================ */ -/* ================ TIMER0 ================ */ -/* ================================================================================ */ - - -/** - * @brief timer 0 (TIMER0) - */ - -typedef struct { /*!< TIMER0 Structure */ - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t EN : 1; /*!< flag indicates if timer is enabled or not */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TYPE; /*!< type Register */ - - struct { - __IO uint32_t SIGNLE_SHOT: 1; /*!< indicate timer generate only one interrupt if not reload */ - } TYPE_b; /*!< BitSize */ - }; - __IO uint32_t LEN; /*!< length */ - - union { - __IO uint32_t INT_EN; /*!< interrupt enable */ - - struct { - __IO uint32_t EN_REVERSE : 1; /*!< flag indicates if timer is disable or not */ - } INT_EN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STA; /*!< interrupt status */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_STA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw register */ - - struct { - __IO uint32_t STA : 1; /*!< interrupt status */ - } INT_RAW_b; /*!< BitSize */ - }; - __I uint32_t CNT; /*!< counter register */ -} TIMER0_Type; - - -/* ================================================================================ */ -/* ================ SPI0 ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI 0 (SPI0) - */ - -typedef struct { /*!< SPI0 Structure */ - - union { - __I uint32_t STATUS; /*!< status Register */ - - struct { - __I uint32_t RFIFO_EMPTY: 1; /*!< receive fifo is empty */ - __I uint32_t RFIFO_FULL : 1; /*!< receive fifo is full */ - __I uint32_t RFIFO_ALMOST_EMPTY: 1; /*!< receive fifo is almost empty */ - __I uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full */ - __I uint32_t TFIFO_EMPTY: 1; /*!< transmit fifo is empty */ - __I uint32_t TFIFO_FULL : 1; /*!< transmit fifo is full */ - __I uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo is almost empty */ - __I uint32_t TFIFO_ALMOST_FULL: 1; /*!< transmit fifo almost full */ - __I uint32_t BUSY : 1; /*!< indecates if SPI is idle or busy */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t EN : 1; /*!< indicates if SPI is enabled or not */ - __IO uint32_t RX_EN : 1; /*!< indicates if SPI receiver is enabled or not */ - __IO uint32_t CLK_HIGH : 1; /*!< indicats if idle clock polarity is high level */ - __IO uint32_t NEG_EDGE : 1; /*!< 1, indicates SPI takes sample at the rise edge and transmit - data at the trailing edge. 0, conversely. */ - __IO uint32_t TX_BIT_SEQUENCE: 1; /*!< transmit bit sequence. 0 : MSB is sent first */ - __IO uint32_t RX_BIT_SEQUENCE: 1; /*!< receive bit sequence. 0: MSB is received first */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< interrupt mask Register */ - - struct { - __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ - __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ - __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ - __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ - __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ - __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ - __IO uint32_t DONE : 1; /*!< transmit done interrupt */ - } INT_MASK_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STATUS; /*!< interrupt Register */ - - struct { - __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ - __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ - __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ - __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ - __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ - __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ - __IO uint32_t DONE : 1; /*!< transmit done interrupt */ - } INT_STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw Register */ - - struct { - __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ - __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ - __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ - __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ - __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ - __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ - __IO uint32_t DONE : 1; /*!< transmit done interrupt */ - } INT_RAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t BCNT; /*!< bit length while transmitting and receiving */ - - struct { - __IO uint32_t CNT : 5; /*!< bit length while transmitting and receiving, BCNT + 1 */ - } BCNT_b; /*!< BitSize */ - }; - __IO uint8_t GAP; /*!< half cycle number between continuous data frame */ - __I uint8_t RESERVED0[3]; - __IO uint16_t DIV; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ - __I uint16_t RESERVED1; - __IO uint32_t TRANS_CNT; /*!< transmit data length, data number = TRANS_CNT + 1 */ - - union { - __O uint32_t TRANS_START; /*!< transmit startup register, write 1 to trigger transmision once */ - - struct { - __O uint32_t TX_TRIGGER : 1; /*!< write 1 to trigger transmision once */ - } TRANS_START_b; /*!< BitSize */ - }; - __IO uint32_t RW_DATA; /*!< raw data register */ -} SPI0_Type; - - -/* ================================================================================ */ -/* ================ I2C0 ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C 0 (I2C0) - */ - -typedef struct { /*!< I2C0 Structure */ - - union { - __IO uint32_t CTRL; /*!< control Register */ - - struct { - __IO uint32_t MODE : 1; /*!< master or slave mode */ - __IO uint32_t MASTER_ADDR_WIDTH: 1; /*!< 7- or 10-bits address as a master */ - __IO uint32_t SLAVE_ADDR_WIDTH: 1; /*!< 7- or 10-bits address width as a slave */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint16_t TAR; /*!< target address Register */ - - struct { - __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ - __IO uint16_t START_BYTE : 1; /*!< Enable start Byte for each transfer */ - } TAR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED0; - - union { - __IO uint16_t SAR; /*!< slave address Register */ - - struct { - __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ - } SAR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED1; - - union { - __IO uint32_t DATA_CMD; /*!< I2C transfer data/command entry */ - - struct { - __IO uint32_t DATA : 8; /*!< 8-bits data */ - __O uint32_t RD_CMD : 1; /*!< read command for master mode only, write 0 if slave mode */ - __O uint32_t WR_CMD : 1; /*!< write command for master mode only */ - __O uint32_t WR_RD_CMD : 1; /*!< write and read command for master mode only */ - } DATA_CMD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WRITE_READ_CNT; /*!< I2C write and read data byte counter Register */ - - struct { - __IO uint32_t RD_BYTE_CNT: 9; /*!< Decide the number of bytes read back as a master-receiver */ - uint32_t : 7; - __IO uint32_t WR_BYTE_CNT: 9; /*!< Decide the number of byte to send as a master-transmitter */ - } WRITE_READ_CNT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SCL_CNT; /*!< I2C clk pulse counter */ - - struct { - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< the SCL clock high-period count */ - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< the SCL clock low-period count */ - } SCL_CNT_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2; - - union { - __I uint32_t INT_STATUS; /*!< I2C interrupt sources */ - - struct { - __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ - __I uint32_t RX_OVER : 1; /*!< receiver overflow */ - __I uint32_t RX_FULL : 1; /*!< receiver is full */ - __I uint32_t TX_OVER : 1; /*!< transmit overflow */ - __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ - __I uint32_t RD_REQ : 1; /*!< read request */ - __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ - __I uint32_t RX_DONE : 1; /*!< receive done */ - __I uint32_t TX_DONE : 1; /*!< transmit done */ - __I uint32_t WR_REQ : 1; /*!< write request */ - } INT_STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< I2C interrupt mask register */ - - struct { - __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ - __I uint32_t RX_OVER : 1; /*!< receiver overflow */ - __I uint32_t RX_FULL : 1; /*!< receiver is full */ - __I uint32_t TX_OVER : 1; /*!< transmit overflow */ - __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ - __I uint32_t RD_REQ : 1; /*!< read request */ - __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ - __I uint32_t RX_DONE : 1; /*!< receive done */ - __I uint32_t TX_DONE : 1; /*!< transmit done */ - __I uint32_t WR_REQ : 1; /*!< write request */ - } INT_MASK_b; /*!< BitSize */ - }; - __I uint32_t RESERVED3; - - union { - __IO uint32_t RX_TL; /*!< I2C receive FIFO threshold */ - - struct { - __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ - } RX_TL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TX_TL; /*!< I2C transmit FIFO threshold */ - - struct { - __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ - } TX_TL_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_ALL_INT; /*!< I2C clear all interrupt register */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear all individual interrupts */ - } CLR_ALL_INT_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RX_UNDER; /*!< I2C clear RX_UNDER interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_UNDER interrupt (bit 19) - of the I2C_STATUS register */ - } CLR_RX_UNDER_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RX_OVER; /*!< I2C clear RX_OVER interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_OVER interrupt (bit 20) of - the I2C_STATUS register */ - } CLR_RX_OVER_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_TX_OVER; /*!< I2C clear TX_OVER interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_OVER interrupt (bit 22) of - the I2C_STATUS register */ - } CLR_TX_OVER_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RD_REQ; /*!< I2C clear RD_REQ interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RD_REQ interrupt (bit 24) of - the I2C_STATUS register */ - } CLR_RD_REQ_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_TX_ABRT; /*!< I2C clear TX_ABRT interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_ABRT interrupts (bit 25 , - bit 18, bit 17, bit 16 and bit 15) of the I2C_STATUS register. */ - } CLR_TX_ABRT_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_RX_DONE; /*!< I2C clear RX_DONE interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_DONE interrupt (bit 26) of - the I2C_STATUS register */ - } CLR_RX_DONE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ENABLE; /*!< I2C enable register */ - - struct { - __IO uint32_t EN : 1; /*!< enable device */ - uint32_t : 30; - __IO uint32_t RESET : 1; /*!< TX and RX FIFO are held in an erased state( flushed) and all - interrupts deserted */ - } ENABLE_b; /*!< BitSize */ - }; - - union { - __I uint32_t STATUS; /*!< I2C status register */ - - struct { - __I uint32_t BUSY : 1; /*!< I2C busy Status */ - __I uint32_t TX_FIFO_NOT_FULL: 1; /*!< transmit FIFO is not full */ - __I uint32_t TX_FIFO_EMPTY: 1; /*!< transmit FIFO is empty */ - __I uint32_t RX_FIFO_NOT_EMPTY: 1; /*!< receive FIFO is not empty */ - __I uint32_t RX_FIFO_FULL: 1; /*!< receive FIFO is full */ - __I uint32_t EN : 1; /*!< I2C is enabled */ - __I uint32_t TX_BYTE_W_ACK: 9; /*!< Number of bytes sent to slave with acknowledge during the last - write transaction as a master-transmitter only */ - __I uint32_t ABRT_ADDR_NOACK: 1; /*!< the address sent was not acknowledged by any slave as a master */ - __I uint32_t ABRT_TX_DATA_NOACK: 1; /*!< the data sent was not acknowledged by any slave as a master */ - __I uint32_t ABRT_SLAVE_FLUSH_TX_FIFO: 1; /*!< Slave has received a read command and some data exists in the - TX FIFO so the slave issues a TX_ABRT interrupt to flush old - data in TX FIFO */ - __I uint32_t ABRT_SLAVE_RD_IN_TX: 1; /*!< When the processor side responds to a slave mode request for - data to be transmitted to a remote master and user writes a - 1 in CMD (bit 8) of I2C_DATA_CMD register */ - __I uint32_t RX_UNDER : 1; /*!< receiver is underflow */ - __I uint32_t RX_OVER : 1; /*!< receiver is overflow */ - __I uint32_t RX_FULL : 1; /*!< receiver is full */ - __I uint32_t TX_OVER : 1; /*!< transmit is overflow */ - __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ - __I uint32_t RD_REQ : 1; /*!< read request is received */ - __I uint32_t TX_ABRT : 1; /*!< transmit is abort */ - __I uint32_t RX_DONE : 1; /*!< receive is done */ - __I uint32_t TX_DONE : 1; /*!< transmit is done */ - __I uint32_t WR_REQ : 1; /*!< write request is received */ - __I uint32_t MST_RD_FLAG: 1; /*!< Master is executing read command */ - __I uint32_t MST_WR_FLAG: 1; /*!< Master is executing read command */ - __I uint32_t MST_WR_RD_FLAG: 1; /*!< Master is executing write-read command */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __I uint32_t TX_FIFO_LEVEL; /*!< I2C transmit FIFO level */ - - struct { - __I uint32_t LEVEL : 5; /*!< FIFO level */ - } TX_FIFO_LEVEL_b; /*!< BitSize */ - }; - - union { - __I uint32_t RX_FIFO_LEVEL; /*!< I2C receive FIFO level */ - - struct { - __I uint32_t LEVEL : 5; /*!< FIFO level */ - } RX_FIFO_LEVEL_b; /*!< BitSize */ - }; - __I uint32_t RESERVED4; - - union { - __O uint32_t SLAVE_NACK; /*!< I2C slave send a data NACK */ - - struct { - __O uint32_t NACK : 1; /*!< data NACK */ - } SLAVE_NACK_b; /*!< BitSize */ - }; - __I uint32_t RESERVED5; - - union { - __IO uint32_t SDA_SETUP; /*!< I2C SDA setup timer */ - - struct { - __IO uint32_t TSETUP : 10; /*!< This counter defines the max value of the following constrains:THD:STA - TSU:STO,TSETUP: T / INPUT_CLK_PERIOD */ - __IO uint32_t TSU_DAT : 8; /*!< This counter defines the constrain of TSU:DAT: 250ns (or 100ns) - / INPUT_CLK_PERIOD */ - } SDA_SETUP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TSU_STA_SETUP; /*!< I2C Tsu_sta and Tbuf_free timer */ - - struct { - __IO uint32_t TBUF : 10; /*!< This counter defines the constrain of bus free interval: Tbuf, - Tbuf : Tbus_free / INPUT_CLK_PERIOD */ - __IO uint32_t TSU_STA : 10; /*!< This counter defines the constrain of Tsu:sta, Tsu:sta : Tsu:sta - / INPUT_CLK_PERIOD */ - __IO uint32_t SDA_FILTER_CNT: 4; /*!< SDA filter count */ - __IO uint32_t SDA_FILTER_EN: 1; /*!< SDA filter enable bit */ - __IO uint32_t SCL_FILTER_CNT: 4; /*!< SCL filter count */ - __IO uint32_t SCL_FILTER_EN: 1; /*!< SCL filter enable bit */ - } TSU_STA_SETUP_b; /*!< BitSize */ - }; - - union { - __I uint32_t CLR_TX_DONE; /*!< I2C clear TX_DONE interrupt */ - - struct { - __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_DONE interrupt (bit 27) of - the I2C_STATUS register */ - } CLR_TX_DONE_b; /*!< BitSize */ - }; -} I2C0_Type; - - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - - -/** - * @brief RTC (RTC) - */ - -typedef struct { /*!< RTC Structure */ - - union { - __IO uint32_t INT_STATUS; /*!< interrupt Register */ - - struct { - __IO uint32_t SECOND : 1; /*!< 1s interrupt, write 1 clear 0 */ - __IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt, write 1 clear 0 */ - } INT_STATUS_b; /*!< BitSize */ - }; - __IO uint32_t SECOND; /*!< current seconds of system time */ - - union { - __IO uint16_t MILLSECOND; /*!< current millseconds of system time */ - - struct { - __IO uint16_t MS : 10; /*!< micro seconds */ - } MILLSECOND_b; /*!< BitSize */ - }; -} RTC_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - __I uint32_t GPIO_IN; /*!< GPIO input data */ - __IO uint32_t GPIO_OUT_UNMASK; /*!< GPIO output mask Register */ - __IO uint32_t GPIO_OUT_DATA; /*!< GPIO output data register */ - __IO uint32_t GPIO_OE; /*!< GPIO output driver enable */ - __IO uint32_t GPIO_INT_MASK; /*!< GPIO input interrupt mask */ - __IO uint32_t GPIO_INT_STATUS; /*!< GPIO input interrupt status */ - __IO uint32_t GPIO_INT_RAW; /*!< GPIO input interrupt raw */ - __IO uint32_t GPIO_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ - - union { - __IO uint32_t PWM_OUT_SEL; /*!< Select gpio output from PWM */ - - struct { - __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ - __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ - __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ - __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ - } PWM_OUT_SEL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT0_LEN; /*!< Pwm channel 0 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT0_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT1_LEN; /*!< Pwm channel 1 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT1_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT2_LEN; /*!< Pwm channel 2 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT2_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT3_LEN; /*!< Pwm channel 3 paramters */ - - struct { - __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ - __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ - } PWM_OUT3_LEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PWM_OUT_EN; /*!< Pwm enable */ - - struct { - __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ - __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ - __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ - __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ - } PWM_OUT_EN_b; /*!< BitSize */ - }; - __I uint32_t GPIO_H_IN; /*!< GPIO_H input data */ - __IO uint32_t GPIO_H_OUT_UNMASK; /*!< GPIO_H output unmask Register */ - __IO uint32_t GPIO_H_OUT_DATA; /*!< GPIO_H output data register */ - __IO uint32_t GPIO_H_OE; /*!< GPIO_H output driver enable */ - __IO uint32_t GPIO_H_INT_MASK; /*!< GPIO_H interrupt mask */ - __IO uint32_t GPIO_H_INT_STATUS; /*!< GPIO_H interrupt status */ - __IO uint32_t GPIO_H_INT_RAW; /*!< GPIO_H interrupt raw */ - __IO uint32_t GPIO_H_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ - __I uint32_t GPIO_N_IN; /*!< GPIO_N input data */ - __IO uint32_t GPIO_N_OUT_UNMASK; /*!< GPIO_N output unmask Register */ - __IO uint32_t GPIO_N_OUT_DATA; /*!< GPIO_N output data register */ - __IO uint32_t GPIO_N_OE; /*!< GPIO_N output driver enable */ - __IO uint32_t GPIO_N_INT_MASK; /*!< GPIO_N interrupt mask */ - __IO uint32_t GPIO_N_INT_STATUS; /*!< GPIO_N interrupt status */ - __IO uint32_t GPIO_N_INT_RAW; /*!< GPIO_N interrupt raw */ - __IO uint32_t GPIO_N_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ -} GPIO_Type; - - -/* ================================================================================ */ -/* ================ NOR_FLASH ================ */ -/* ================================================================================ */ - - -/** - * @brief NOR_FLASH (NOR_FLASH) - */ - -typedef struct { /*!< NOR_FLASH Structure */ - - union { - __IO uint32_t CTRL0; /*!< control Register 0 */ - - struct { - __IO uint32_t DIV : 8; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ - __IO uint32_t CS_REVALID_INTERVAL: 8; /*!< interval from CS invalid to valid, number of half cycle of SCK */ - __IO uint32_t RW_BYTE_CNT: 16; /*!< RW byte count (eliminate CMD, ADDRESS, DUMMY in normal state, - contains all in transparent state. 0 is unlimited */ - } CTRL0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTRL1; /*!< control Register 1 */ - - struct { - __IO uint32_t CMD : 8; /*!< operated command */ - __IO uint32_t ADDRESS : 24; /*!< RW address */ - } CTRL1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TRIGGER; /*!< trigger register */ - - struct { - __O uint32_t OP_START : 1; /*!< operation start. */ - __IO uint32_t OP_CLEAN : 1; /*!< operation clean, stop current opration and clean FIFO */ - __IO uint32_t TRSP_RD_EN : 1; /*!< if a read operation after transparent operation */ - __IO uint32_t TRSP_EN : 1; /*!< enable transparent operation */ - } TRIGGER_b; /*!< BitSize */ - }; - - union { - __I uint32_t STATUS; /*!< status register */ - - struct { - __I uint32_t BUSY : 1; /*!< reading or writting */ - __I uint32_t RD_FIFO_ALMOST_FULL: 1; /*!< read FIFO is almost full */ - __I uint32_t RD_FIFO_EMPTY: 1; /*!< read FIFO is empty */ - __I uint32_t RD_FIFO_FULL: 1; /*!< read FIFO is full */ - __I uint32_t WR_FIFO_ALMOST_EMPTY: 1; /*!< write FIFO is almost empty */ - __I uint32_t WR_FIFO_FULL: 1; /*!< write FIFO is full */ - __I uint32_t WR_FIFO_EMPTY: 1; /*!< write FIFO is empty */ - } STATUS_b; /*!< BitSize */ - }; - __IO uint32_t DATA; /*!< data register. lower bits are significant in read and higher - bits are significant in writting */ - - union { - __IO uint32_t BYPASS; /*!< bypass Register, is used for JTAG connecting FLASH directly */ - - struct { - __IO uint32_t EN : 1; /*!< enable bypass */ - } BYPASS_b; /*!< BitSize */ - }; -} NOR_FLASH_Type; - - -/* ================================================================================ */ -/* ================ ADC ================ */ -/* ================================================================================ */ - - -/** - * @brief ADC (ADC) - */ - -typedef struct { /*!< ADC Structure */ - - union { - __IO uint32_t POWERDOWN_RESET; /*!< power down and reset Register */ - - struct { - __IO uint32_t RESET_ADC2 : 1; /*!< ADC2, reset, active high */ - __IO uint32_t RESET_ADC1 : 1; /*!< ADC1, reset, active high */ - __IO uint32_t POWERDOWN_ADC2: 1; /*!< ADC2, power down, active high */ - __IO uint32_t POWERDOWN_ADC1: 1; /*!< ADC1, power down, active high */ - } POWERDOWN_RESET_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG0; /*!< config Register */ - - struct { - __IO uint32_t VSEN : 3; /*!< ADC-1 VSEN Selection */ - __IO uint32_t PHASE_CTRL : 2; /*!< ADC-1 and ADC-2 CLK Phase Control */ - } CFG0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_ADC1; /*!< config ADC1 register */ - - struct { - __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ - __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ - __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ - __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ - } CFG_ADC1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_ADC2; /*!< config ADC1 register */ - - struct { - __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ - __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ - __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ - __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ - } CFG_ADC2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ADC1_FIFO_CLEAR; /*!< clear adc1 fifo data */ - - struct { - __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ - } ADC1_FIFO_CLEAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ADC2_FIFO_CLEAR; /*!< clear adc2 fifo data */ - - struct { - __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ - } ADC2_FIFO_CLEAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ALL_ADC_FIFO_CLEAR; /*!< clear adc1 and adc2 fifo data */ - - struct { - __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ - } ALL_ADC_FIFO_CLEAR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_MASK; /*!< interrupt mask register */ - - struct { - __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ - __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ - __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ - __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ - __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ - __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ - } INT_MASK_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_RAW; /*!< interrupt raw register */ - - struct { - __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ - __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ - __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ - __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ - __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ - __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ - } INT_RAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_STATUS; /*!< interrupt status register */ - - struct { - __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ - __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ - __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ - __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ - __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ - __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ - } INT_STATUS_b; /*!< BitSize */ - }; - __I uint32_t ADC1_OUT; /*!< ADC-1 Output data (Signed-Magnitude Format) */ - __I uint32_t ADC2_OUT; /*!< ADC-2 Output data (Signed-Magnitude Format) */ - __I uint32_t ADC1_OUT_OFFSET_CALIBRATION; /*!< ADC-1 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ - __I uint32_t ADC2_OUT_OFFSET_CALIBRATION; /*!< ADC-2 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ - __I uint32_t ADC1_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-1 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ - __I uint32_t ADC2_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-2 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ - __I uint32_t ADC1_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-1 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ - __I uint32_t ADC2_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-2 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ - - union { - __I uint32_t EOC; /*!< Conversion End Indicator */ - - struct { - __I uint32_t ADC2_EOC_GAIN: 1; /*!< ADC2 EOC_GAIN signal, conversion is done */ - __I uint32_t ADC2_EOC_OFF: 1; /*!< ADC2 EOC_OFF signal, conversion is done */ - __I uint32_t ADC2_EOC : 1; /*!< ADC2 EOC signal, conversion is done */ - __I uint32_t ADC1_EOC_GAIN: 1; /*!< ADC1 EOC_GAIN signal, conversion is done */ - __I uint32_t ADC1_EOC_OFF: 1; /*!< ADC1 EOC_OFF signal, conversion is done */ - __I uint32_t ADC1_EOC : 1; /*!< ADC1 EOC signal, conversion is done */ - } EOC_b; /*!< BitSize */ - }; - - union { - __I uint32_t BUSY; /*!< ADC is busy */ - - struct { - __I uint32_t ADC1_BUSY : 1; /*!< ADC1 is busy */ - __I uint32_t ADC2_BUSY : 1; /*!< ADC2 is busy */ - } BUSY_b; /*!< BitSize */ - }; - - union { - __O uint32_t ADC1_START; /*!< ADC1 startup enable */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC1_START_b; /*!< BitSize */ - }; - - union { - __O uint32_t ADC1_STOP; /*!< ADC1 stop enable */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC1_STOP_b; /*!< BitSize */ - }; - - union { - __O uint16_t ADC1_FIFO_READ; /*!< ADC1 FIFO read data */ - - struct { - __O uint16_t DATA : 12; /*!< data */ - __O uint16_t CHANNEL : 4; /*!< channel number */ - } ADC1_FIFO_READ_b; /*!< BitSize */ - }; - __I uint16_t RESERVED0; - - union { - __O uint32_t ADC2_START; /*!< ADC2 startup enable, only for single-conversion */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC2_START_b; /*!< BitSize */ - }; - - union { - __O uint32_t ADC2_STOP; /*!< ADC1 stop enable, only for single-conversion */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ADC2_STOP_b; /*!< BitSize */ - }; - - union { - __O uint16_t ADC2_FIFO_READ; /*!< ADC2 FIFO read data */ - - struct { - __O uint16_t DATA : 12; /*!< data */ - __O uint16_t CHANNEL : 4; /*!< channel number */ - } ADC2_FIFO_READ_b; /*!< BitSize */ - }; - __I uint16_t RESERVED1; - - union { - __O uint32_t ALL_ADC_START; /*!< all ADCs start */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ALL_ADC_START_b; /*!< BitSize */ - }; - - union { - __O uint32_t ALL_ADC_STOP; /*!< all ADCs stop */ - - struct { - __O uint32_t EN : 1; /*!< start */ - } ALL_ADC_STOP_b; /*!< BitSize */ - }; - - union { - __I uint32_t ALL_ADC_FIFO_READ; /*!< all ADCs FIFO read data */ - - struct { - __I uint32_t ADC1_DATA : 12; /*!< ADC1 data */ - __I uint32_t ADC1_CHANNEL: 4; /*!< ADC1 channel number */ - __I uint32_t ADC2_DATA : 12; /*!< ADC2 data */ - __I uint32_t ADC2_CHANNEL: 4; /*!< ADC2 channel number */ - } ALL_ADC_FIFO_READ_b; /*!< BitSize */ - }; - - union { - __I uint32_t STATUS; /*!< status register */ - - struct { - __I uint32_t ADC1_READ_EMPTY: 1; /*!< ADC1 read empty */ - __I uint32_t ADC2_READ_EMPTY: 1; /*!< ADC2 read empty */ - __I uint32_t ADC1_READ_ALMOST_EMPTY: 1; /*!< ADC1 read almost empty */ - __I uint32_t ADC2_READ_ALMOST_EMPTY: 1; /*!< ADC2 read almost empty */ - __I uint32_t ADC1_WRITE_FULL: 1; /*!< ADC1 write full */ - __I uint32_t ADC2_WRITE_FULL: 1; /*!< ADC2 write full */ - __I uint32_t ADC1_WRITE_ALMOST_FULL: 1; /*!< ADC1 write almost full */ - __I uint32_t ADC2_WRITE_ALMOST_FULL: 1; /*!< ADC2 write almost full */ - } STATUS_b; /*!< BitSize */ - }; -} ADC_Type; - - -/* ================================================================================ */ -/* ================ EFUSE ================ */ -/* ================================================================================ */ - - -/** - * @brief EFUSE (EFUSE) - */ - -typedef struct { /*!< EFUSE Structure */ - - union { - __IO uint32_t USER_CTRL_LOW; /*!< low user region control */ - - struct { - __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ - __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ - __I uint32_t BUSY : 1; /*!< reading or writting */ - __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ - __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ - __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ - __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ - __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ - } USER_CTRL_LOW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TIMING_0; /*!< timing 0 */ - - struct { - __IO uint32_t TPRS : 7; /*!< TPRS */ - __IO uint32_t TESR : 2; /*!< TESR */ - __IO uint32_t TRC : 4; /*!< TRC */ - __IO uint32_t TRPW : 3; /*!< TRPW */ - __IO uint32_t TRAH : 2; /*!< TRAH */ - __IO uint32_t TRAC : 3; /*!< TRAC */ - uint32_t : 6; - __IO uint32_t TPWPH : 5; /*!< TPWPH[6:2] */ - } TIMING_0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TIMING_1; /*!< timing 1 */ - - struct { - __IO uint32_t TPWPS : 7; /*!< TPWPS */ - __IO uint32_t TEPS : 4; /*!< TEPS */ - __IO uint32_t TPP : 11; /*!< TPP */ - __IO uint32_t TPIT : 8; /*!< TPIT */ - __IO uint32_t TPWPH : 2; /*!< TPWPS[1:0] */ - } TIMING_1_b; /*!< BitSize */ - }; - __IO uint32_t USER_DATA0_LOW; /*!< user data [31:0] */ - __IO uint32_t USER_DATA1_LOW; /*!< user data [63:32] */ - __IO uint32_t USER_DATA2_LOW; /*!< user data [95:64] */ - __IO uint32_t USER_DATA3_LOW; /*!< user data [127:96] */ - - union { - __IO uint32_t USER_DATA4_LOW; /*!< crc and lock bit */ - - struct { - __IO uint32_t LOCK : 1; /*!< write protection if true */ - uint32_t : 23; - __IO uint32_t CRC : 8; /*!< CRC */ - } USER_DATA4_LOW_b; /*!< BitSize */ - }; - __I uint32_t RESERVED0[3]; - - union { - __IO uint32_t USER_CTRL_HI; /*!< high user region control */ - - struct { - __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ - __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ - __I uint32_t BUSY : 1; /*!< reading or writting */ - __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ - __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ - __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ - __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ - __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ - } USER_CTRL_HI_b; /*!< BitSize */ - }; - __IO uint32_t USER_DATA0_HI; /*!< user data [159:128] */ - __IO uint32_t USER_DATA1_HI; /*!< user data [191:160] */ - __IO uint32_t USER_DATA2_HI; /*!< user data [223:192] */ - __IO uint32_t USER_DATA3_HI; /*!< user data [255:224] */ - - union { - __IO uint32_t USER_DATA4_HI; /*!< crc and lock bit */ - - struct { - __IO uint32_t LOCK : 1; /*!< write protection if true */ - uint32_t : 23; - __IO uint32_t CRC : 8; /*!< CRC */ - } USER_DATA4_HI_b; /*!< BitSize */ - }; -} EFUSE_Type; - - -/* ================================================================================ */ -/* ================ CAN0 ================ */ -/* ================================================================================ */ - - -/** - * @brief CAN 0 (CAN0) - */ - -typedef struct { /*!< CAN0 Structure */ - - union { - __IO uint8_t MODE; /*!< mode Register */ - - struct { - __IO uint8_t RM : 1; /*!< reset mode if 1 or operation mode */ - __IO uint8_t LOM : 1; /*!< Listen only mode */ - __IO uint8_t STM : 1; /*!< self test mode */ - __IO uint8_t AFM : 1; /*!< acceptance filter mode. Single filter if 1, dual filter if 0 */ - __IO uint8_t SM : 1; /*!< sleep mode */ - } MODE_b; /*!< BitSize */ - }; - __I uint8_t RESERVED0[3]; - - union { - __O uint8_t CMD; /*!< command Register */ - - struct { - __O uint8_t TR : 1; /*!< Set to 1 when a message is to be transmitted */ - __O uint8_t AT : 1; /*!< Set to 1 to cancel the next transmission request */ - __O uint8_t RRB : 1; /*!< Set to 1 to release the Receive Buffer */ - __O uint8_t CDO : 1; /*!< Set to 1 to clear the data overrun condition signaled by the - Data Overrun Status bit (SR.1). */ - __O uint8_t SSR : 1; /*!< Set to 1 when a message is to be transmitted and received simultaneously */ - } CMD_b; /*!< BitSize */ - }; - __I uint8_t RESERVED1[3]; - - union { - __I uint8_t STATUS; /*!< status Register */ - - struct { - __I uint8_t RBNE : 1; /*!< Receive Buffer not empty */ - __I uint8_t DO : 1; /*!< Data Overrun Status */ - __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ - __I uint8_t TC : 1; /*!< Transmission complete */ - __I uint8_t RXING : 1; /*!< receiving the data */ - __I uint8_t TXING : 1; /*!< transmitting the data */ - __I uint8_t ERR : 1; /*!< At least one of the error counters is more than Error Warning - Limit Register */ - __I uint8_t BUS_OFF : 1; /*!< in 'Bus Off' state */ - } STATUS_b; /*!< BitSize */ - }; - __I uint8_t RESERVED2[3]; - - union { - __I uint8_t INT; /*!< interrupt Register */ - - struct { - __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ - __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ - __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status - or Error Status bits (SR.7,SR.6) */ - __I uint8_t DO : 1; /*!< Data Overrun Status */ - __I uint8_t WAKEUP : 1; /*!< wake-up */ - __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being - in error passive state or when at least one error counter exceeds - the protocol-defined level of 127 */ - __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ - __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ - } INT_b; /*!< BitSize */ - }; - __I uint8_t RESERVED3[3]; - - union { - __IO uint8_t INT_EN; /*!< interrupt enabled Register */ - - struct { - __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ - __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ - __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status - or Error Status bits (SR.7,SR.6) */ - __I uint8_t DO : 1; /*!< Data Overrun Status */ - __I uint8_t WAKEUP : 1; /*!< wake-up */ - __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being - in error passive state or when at least one error counter exceeds - the protocol-defined level of 127 */ - __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ - __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ - } INT_EN_b; /*!< BitSize */ - }; - __I uint8_t RESERVED4[7]; - - union { - __IO uint8_t BTR0; /*!< Bus Timing 0 */ - - struct { - __IO uint8_t BRP : 6; /*!< TQ =2 x Txtal1 x (32 x BRP.5 + 16 x BRP.4 + 8 x BRP.3 + 4 x - BRP.2 + 2 x BRP.1 + BRP.0 + 1) */ - __IO uint8_t SJW : 2; /*!< the maximum number of time quanta of sync segment */ - } BTR0_b; /*!< BitSize */ - }; - __I uint8_t RESERVED5[3]; - - union { - __IO uint8_t BTR1; /*!< Bus Timing 1 */ - - struct { - __IO uint8_t TSEG1 : 4; /*!< the maximum number of time quanta of propagation and 1st phase - segment */ - __IO uint8_t TSEG2 : 3; /*!< the maximum number of time quanta of 2nd phase segment */ - __IO uint8_t SAM : 1; /*!< sample times. Sample 3 times if 1, once if 0 */ - } BTR1_b; /*!< BitSize */ - }; - __I uint8_t RESERVED6[3]; - - union { - __IO uint8_t OCR; /*!< Output Control Register */ - - struct { - __IO uint8_t MODE : 2; /*!< output control mode */ - } OCR_b; /*!< BitSize */ - }; - __I uint8_t RESERVED7[11]; - - union { - __I uint8_t ALC; /*!< Arbitration Lost Capture */ - - struct { - __I uint8_t BIT : 5; /*!< the current position of the Bit Processor when bus arbitration - lost, 1st bit (ID.28) if 0 */ - } ALC_b; /*!< BitSize */ - }; - __I uint8_t RESERVED8[3]; - - union { - __I uint8_t ECC; /*!< Error Code Capture */ - - struct { - __I uint8_t SEGMENT : 5; /*!< segment code */ - __I uint8_t DIRECTION : 1; /*!< If 1, the error occurred during reception. If 0, the error occurred - during transmission */ - __I uint8_t ERR : 2; /*!< error code */ - } ECC_b; /*!< BitSize */ - }; - __I uint8_t RESERVED9[3]; - __IO uint8_t EWLR; /*!< Error Warning Limit */ - __I uint8_t RESERVED10[3]; - __IO uint8_t RXERR; /*!< Receive Error Counter */ - __I uint8_t RESERVED11[3]; - __IO uint8_t TXERR; /*!< Transmit Error Counter */ - __I uint8_t RESERVED12[3]; - - union { - __IO uint8_t FI_OR_ACR0; /*!< Transmit Frame Information if writting or Receive Frame Information - if reading, ACR[0] if reset mode */ - - struct { - __IO uint8_t DLC : 4; /*!< byte number in the data */ - uint8_t : 2; - __IO uint8_t RTR : 1; /*!< 1 indicates a remote frame; 0 indicates a data frame */ - __IO uint8_t FF : 1; /*!< 1 selects Extended Frame Format (EFF); 0 selects Standard Frame - Format (SFF) */ - } FI_OR_ACR0_b; /*!< BitSize */ - }; - __I uint8_t RESERVED13[3]; - __IO uint8_t DI0_OR_ACR1; /*!< Transmit data Information if writting or Receive data Information - if reading, ACR[1] if reset mode */ - __I uint8_t RESERVED14[3]; - __IO uint8_t DI1_OR_ACR2; /*!< Transmit data Information if writting or Receive data Information - if reading, ACR[2] if reset mode */ - __I uint8_t RESERVED15[3]; - __IO uint8_t DI2_OR_ACR3; /*!< Transmit data Information if writting or Receive data Information - if reading, ACR[3] if reset mode */ - __I uint8_t RESERVED16[3]; - __IO uint8_t DI3_OR_AMR0; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[0] if reset mode */ - __I uint8_t RESERVED17[3]; - __IO uint8_t DI4_OR_AMR1; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[1] if reset mode */ - __I uint8_t RESERVED18[3]; - __IO uint8_t DI5_OR_AMR2; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[2] if reset mode */ - __I uint8_t RESERVED19[3]; - __IO uint8_t DI6_OR_AMR3; /*!< Transmit data Information if writting or Receive data Information - if reading, AMR[3] if reset mode */ - __I uint8_t RESERVED20[3]; - __IO uint8_t DI7; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED21[3]; - __IO uint8_t DI8; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED22[3]; - __IO uint8_t DI9; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED23[3]; - __IO uint8_t DI10; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED24[3]; - __IO uint8_t DI11; /*!< Transmit data Information if writting or Receive data Information - if reading */ - __I uint8_t RESERVED25[3]; - __IO uint8_t RMC; /*!< Receive Message Counter */ - __I uint8_t RESERVED26[7]; - - union { - __IO uint8_t CDR; /*!< Clock Divider Register */ - - struct { - __IO uint8_t DIVIDER : 3; /*!< divider of XTAL1 */ - __IO uint8_t OFF : 1; /*!< disable XTAL1 */ - } CDR_b; /*!< BitSize */ - }; -} CAN0_Type; - - -/* ================================================================================ */ -/* ================ DMA ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA (DMA) - */ - -typedef struct { /*!< DMA Structure */ - __IO uint32_t SAR0; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED0; - __IO uint32_t DAR0; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED1; - - union { - __IO uint32_t LLP0; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2; - - union { - __IO uint32_t CTL_LOW0; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI0; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI0_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT0; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED3; - __IO uint32_t DSTAT0; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED4; - __IO uint32_t SSTATAR0; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED5; - __IO uint32_t DSTATAR0; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED6; - - union { - __IO uint32_t CFG_LOW0; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI0; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR0; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED7; - - union { - __IO uint32_t DSR0; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED8; - __IO uint32_t SAR1; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED9; - __IO uint32_t DAR1; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED10; - - union { - __IO uint32_t LLP1; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED11; - - union { - __IO uint32_t CTL_LOW1; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI1; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI1_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT1; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED12; - __IO uint32_t DSTAT1; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED13; - __IO uint32_t SSTATAR1; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED14; - __IO uint32_t DSTATAR1; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED15; - - union { - __IO uint32_t CFG_LOW1; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI1; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR1; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED16; - - union { - __IO uint32_t DSR1; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED17; - __IO uint32_t SAR2; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED18; - __IO uint32_t DAR2; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED19; - - union { - __IO uint32_t LLP2; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED20; - - union { - __IO uint32_t CTL_LOW2; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI2; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI2_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT2; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED21; - __IO uint32_t DSTAT2; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED22; - __IO uint32_t SSTATAR2; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED23; - __IO uint32_t DSTATAR2; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED24; - - union { - __IO uint32_t CFG_LOW2; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI2; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR2; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED25; - - union { - __IO uint32_t DSR2; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED26; - __IO uint32_t SAR3; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED27; - __IO uint32_t DAR3; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED28; - - union { - __IO uint32_t LLP3; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED29; - - union { - __IO uint32_t CTL_LOW3; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI3; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI3_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT3; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED30; - __IO uint32_t DSTAT3; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED31; - __IO uint32_t SSTATAR3; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED32; - __IO uint32_t DSTATAR3; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED33; - - union { - __IO uint32_t CFG_LOW3; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI3; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR3; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED34; - - union { - __IO uint32_t DSR3; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED35; - __IO uint32_t SAR4; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED36; - __IO uint32_t DAR4; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED37; - - union { - __IO uint32_t LLP4; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED38; - - union { - __IO uint32_t CTL_LOW4; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI4; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI4_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT4; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED39; - __IO uint32_t DSTAT4; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED40; - __IO uint32_t SSTATAR4; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED41; - __IO uint32_t DSTATAR4; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED42; - - union { - __IO uint32_t CFG_LOW4; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI4; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR4; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED43; - - union { - __IO uint32_t DSR4; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED44; - __IO uint32_t SAR5; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED45; - __IO uint32_t DAR5; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED46; - - union { - __IO uint32_t LLP5; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED47; - - union { - __IO uint32_t CTL_LOW5; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI5; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI5_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT5; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED48; - __IO uint32_t DSTAT5; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED49; - __IO uint32_t SSTATAR5; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED50; - __IO uint32_t DSTATAR5; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED51; - - union { - __IO uint32_t CFG_LOW5; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI5; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR5; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED52; - - union { - __IO uint32_t DSR5; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED53; - __IO uint32_t SAR6; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED54; - __IO uint32_t DAR6; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED55; - - union { - __IO uint32_t LLP6; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED56; - - union { - __IO uint32_t CTL_LOW6; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI6; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI6_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT6; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED57; - __IO uint32_t DSTAT6; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED58; - __IO uint32_t SSTATAR6; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED59; - __IO uint32_t DSTATAR6; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED60; - - union { - __IO uint32_t CFG_LOW6; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI6; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR6; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED61; - - union { - __IO uint32_t DSR6; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED62; - __IO uint32_t SAR7; /*!< Current Source Address of DMA transfer */ - __I uint32_t RESERVED63; - __IO uint32_t DAR7; /*!< Current Destination Address of DMA transfer */ - __I uint32_t RESERVED64; - - union { - __IO uint32_t LLP7; /*!< Linked List Pointer Register for Channel */ - - struct { - __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that - stores the next linked list item resides. */ - __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is - enabled */ - } LLP7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED65; - - union { - __IO uint32_t CTL_LOW7; /*!< Lower 32-bits Control Register for Channel */ - - struct { - __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ - __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ - __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ - __IO uint32_t DINC : 2; /*!< Destination Address Increment */ - __IO uint32_t SINC : 2; /*!< Source Address Increment */ - __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ - __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ - __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ - __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ - uint32_t : 1; - __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ - __IO uint32_t DMS : 2; /*!< Destination Master Select */ - __IO uint32_t SMS : 2; /*!< Source Master Select */ - __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ - __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ - } CTL_LOW7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CTL_HI7; /*!< Higher 32-bits Control Register for Channel */ - - struct { - __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform - for every block transfer */ - __IO uint32_t DONE : 1; /*!< a block transfer is complete */ - } CTL_HI7_b; /*!< BitSize */ - }; - __IO uint32_t SSTAT7; /*!< Source Status Register for Channel */ - __I uint32_t RESERVED66; - __IO uint32_t DSTAT7; /*!< Destination Status Register for Channel */ - __I uint32_t RESERVED67; - __IO uint32_t SSTATAR7; /*!< Source Status Address Register for Channel */ - __I uint32_t RESERVED68; - __IO uint32_t DSTATAR7; /*!< Destination Status Address Register for Channel */ - __I uint32_t RESERVED69; - - union { - __IO uint32_t CFG_LOW7; /*!< Lower 32-bit Configuration Register for Channel */ - - struct { - uint32_t : 5; - __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ - __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit - is cleared. */ - __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ - __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ - __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ - __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ - __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ - __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ - __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ - __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ - __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ - __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ - __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ - __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ - } CFG_LOW7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CFG_HI7; /*!< Higher 32-bit Configuration Register for Channel */ - - struct { - __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination - Peripheral is the flow controller. */ - __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before - a burst transaction request is serviced. */ - __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the - HPROT[3:1] master interface signals */ - __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ - } CFG_HI7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t SGR7; /*!< Source Gather Register for Channel */ - - struct { - __IO uint32_t SGI : 20; /*!< Source gather interval */ - __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ - } SGR7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED70; - - union { - __IO uint32_t DSR7; /*!< Destination Scatter Register for Channel */ - - struct { - __IO uint32_t DSI : 20; /*!< Destination scatter interval */ - __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of - CTLx.DST_TR_WIDTH */ - } DSR7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED71[11]; - __I uint8_t INT_TFR; /*!< DMA Transfer Complete */ - __I uint8_t RESERVED72[7]; - __I uint8_t INT_BLOCK; /*!< Block Transfer Complete */ - __I uint8_t RESERVED73[7]; - __I uint8_t INT_SRC_TRAN; /*!< Source Transaction Complete */ - __I uint8_t RESERVED74[7]; - __I uint8_t INT_DST_TRAN; /*!< Destination Transaction Complete */ - __I uint8_t RESERVED75[7]; - __I uint8_t INT_ERR; /*!< Error */ - __I uint8_t RESERVED76[7]; - - union { - __IO uint16_t INT_EN_TFR; /*!< DMA Transfer Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_TFR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED77[3]; - - union { - __IO uint16_t INT_EN_BLOCK; /*!< Block Transfer Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_BLOCK_b; /*!< BitSize */ - }; - __I uint16_t RESERVED78[3]; - - union { - __IO uint16_t INT_EN_SRC_TRAN; /*!< Source Transaction Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_SRC_TRAN_b; /*!< BitSize */ - }; - __I uint16_t RESERVED79[3]; - - union { - __IO uint16_t INT_EN_DST_TRAN; /*!< Destination Transaction Complete */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_DST_TRAN_b; /*!< BitSize */ - }; - __I uint16_t RESERVED80[3]; - - union { - __IO uint16_t INT_EN_ERR; /*!< Error */ - - struct { - __IO uint16_t EN : 8; /*!< interrupt enable */ - __IO uint16_t WE : 8; /*!< interrupt enable write enable */ - } INT_EN_ERR_b; /*!< BitSize */ - }; - __I uint16_t RESERVED81[3]; - __O uint8_t INT_CLEAR_TFR; /*!< DMA Transfer Complete */ - __I uint8_t RESERVED82[7]; - __O uint8_t INT_CLEAR_BLOCK; /*!< Block Transfer Complete */ - __I uint8_t RESERVED83[7]; - __O uint8_t INT_CLEAR_SRC_TRAN; /*!< Source Transaction Complete */ - __I uint8_t RESERVED84[7]; - __O uint8_t INT_CLEAR_DST_TRAN; /*!< Destination Transaction Complete */ - __I uint8_t RESERVED85[7]; - __O uint8_t INT_CLEAR_ERR; /*!< Error */ - __I uint8_t RESERVED86[63]; - - union { - __IO uint32_t DMA_EN; /*!< DW_ahb_dmac Configuration Register */ - - struct { - __IO uint32_t EN : 1; /*!< enable */ - } DMA_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED87; - - union { - __IO uint32_t CH_EN; /*!< DW_ahb_dmac Channel Enable Register */ - - struct { - __IO uint32_t EN : 8; /*!< enable */ - __IO uint32_t WE : 8; /*!< enable write enable */ - } CH_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED88[10]; - - union { - __I uint32_t DMA_COMP_PARAMS_6_HI; /*!< Component Parameters for channel 7 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_6_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_5_LOW; /*!< Component Parameters for channel 6 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_5_LOW_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_5_HI; /*!< Component Parameters for channel 5 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_5_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_4_LOW; /*!< Component Parameters for channel 4 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_4_LOW_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_4_HI; /*!< Component Parameters for channel 3 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_4_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_3_LOW; /*!< Component Parameters for channel 2 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_3_LOW_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_3_HI; /*!< Component Parameters for channel 1 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_3_HI_b; /*!< BitSize */ - }; - - union { - __I uint32_t DMA_COMP_PARAMS_2_LOW; /*!< Component Parameters for channel 0 */ - - struct { - __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination - transfer width. */ - __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source - transfer width. */ - __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ - __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ - __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ - __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ - __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ - __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ - __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is - on */ - __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ - uint32_t : 2; - __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ - __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ - __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ - __I uint32_t SMS : 3; /*!< source AHB dma interface */ - __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ - } DMA_COMP_PARAMS_2_LOW_b; /*!< BitSize */ - }; - __I uint32_t RESERVED89; - - union { - __I uint32_t DMA_COMP_PARAMS_1_LOW; /*!< Maximum block size for channel */ - - struct { - __I uint32_t CH0_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 0. */ - __I uint32_t CH1_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 1 */ - __I uint32_t CH2_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 2 */ - __I uint32_t CH3_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 3 */ - __I uint32_t CH4_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 4 */ - __I uint32_t CH5_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 5 */ - __I uint32_t CH6_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 6 */ - __I uint32_t CH7_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 7 */ - } DMA_COMP_PARAMS_1_LOW_b; /*!< BitSize */ - }; -} DMA_Type; - - -/* ================================================================================ */ -/* ================ ETH ================ */ -/* ================================================================================ */ - - -/** - * @brief ETH (ETH) - */ - -typedef struct { /*!< ETH Structure */ - - union { - __IO uint32_t CONFIG; /*!< MAC Configuration Register */ - - struct { - __IO uint32_t PRELEN : 2; /*!< Preamble Length for Transmit frames */ - __IO uint32_t RX_EN : 1; /*!< Receiver Enable */ - __IO uint32_t TX_EN : 1; /*!< Transmitter Enable */ - __IO uint32_t DC_EN : 1; /*!< Deferral Check Enable */ - uint32_t : 2; - __IO uint32_t ACS : 1; /*!< Automatic Pad or CRC Stripping */ - __IO uint32_t LUD : 1; /*!< Link Up or Down */ - uint32_t : 1; - __IO uint32_t IPC : 1; /*!< Checksum Offload */ - __IO uint32_t DM : 1; /*!< Duplex Mode */ - __IO uint32_t LM : 1; /*!< Loopback Mode */ - uint32_t : 1; - __IO uint32_t FES : 1; /*!< Speed in XMII interface */ - __IO uint32_t PS : 1; /*!< the Ethernet line speed */ - uint32_t : 4; - __IO uint32_t JE : 1; /*!< Jumbo enable */ - uint32_t : 1; - __IO uint32_t JD : 1; /*!< if 0, the MAC cuts off the transmitter if more than 2,048 bytes - of data (10,240 if JE is set high) */ - __IO uint32_t WD : 1; /*!< Watchdog Disable */ - __IO uint32_t TC : 1; /*!< If 1, this bit enables the transmission of duplex mode, link - speed, and link up or down information to the PHY */ - __IO uint32_t CST : 1; /*!< CRC Stripping for Type Frames */ - uint32_t : 1; - __IO uint32_t TWOKPE : 1; /*!< If 0, 1518 bytes is considered as a giant frame, 1 is 2000 bytes. */ - __IO uint32_t SARC : 3; /*!< Source Address Insertion or Replacement Control */ - } CONFIG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t FF; /*!< MAC Frame Filter */ - - struct { - __IO uint32_t PR : 1; /*!< Receive all frames in spite of source and destination address */ - __IO uint32_t HUC : 1; /*!< if 1, don't compare DA field in destination address filtering - of unicast frames with DA register */ - __IO uint32_t HMC : 1; /*!< if 1, don't compare DA field in destination address filtering - of multicast frames with DA register */ - __IO uint32_t DAIF : 1; /*!< if set, the Address Check block operates in inverse filtering - mode for the DA address comparison */ - __IO uint32_t PM : 1; /*!< Pass All Multicast */ - __IO uint32_t DBF : 1; /*!< Disable Broadcast Frames */ - __IO uint32_t PCF : 2; /*!< Pass Control Frames */ - __IO uint32_t SAIF : 1; /*!< If set, the frames whose SA matches the SA registers are marked - as failing the SA Address filter */ - __IO uint32_t SAF : 1; /*!< Source Address Filter Enable */ - __IO uint32_t HPF : 1; /*!< Hash or Perfect Filter */ - uint32_t : 5; - __IO uint32_t VTFE : 1; /*!< VLAN Tag Filter Enable */ - uint32_t : 3; - __IO uint32_t IPFE : 1; /*!< Layer 3 and Layer 4 Filter Enable */ - __IO uint32_t DNTU : 1; /*!< Drop non-TCP/UDP over IP Frames */ - uint32_t : 9; - __IO uint32_t RA : 1; /*!< Receive all */ - } FF_b; /*!< BitSize */ - }; - __IO uint32_t HTH; /*!< Hash Table High Register */ - __IO uint32_t HTL; /*!< Hash Table Low Register */ - - union { - __IO uint32_t GMII_ADDR; /*!< GMII Address Register */ - - struct { - __IO uint32_t BUSY : 1; /*!< GMII Busy */ - __IO uint32_t GW : 1; /*!< GMII write or read */ - __IO uint32_t CR : 4; /*!< CSR Clock Range */ - __IO uint32_t GR : 5; /*!< These bits select the desired GMII register in the selected - PHY device */ - __IO uint32_t PA : 5; /*!< This field indicates which of the 32 possible PHY devices are - being accessed */ - } GMII_ADDR_b; /*!< BitSize */ - }; - __IO uint32_t GMII_DATA; /*!< GMII Data Register */ - - union { - __IO uint32_t FC; /*!< Flow Control Register */ - - struct { - __IO uint32_t FCB : 1; /*!< This bit initiates a Pause frame in the full-duplex mode */ - __IO uint32_t TFE : 1; /*!< MAC enables the flow control operation to transmit Pause frames */ - __IO uint32_t RFE : 1; /*!< MAC enables the flow control operation to receive Pause frames */ - __IO uint32_t UP : 1; /*!< MAC can detect Pause frames with unicast address of the station */ - } FC_b; /*!< BitSize */ - }; - - union { - __IO uint32_t VLAN_TAG; /*!< VLAN Tag Register */ - - struct { - __IO uint32_t VL : 16; /*!< VLAN Tag Identifier for Receive Frames */ - __IO uint32_t ETV : 1; /*!< Enable 12-Bit VLAN Tag Comparison */ - __IO uint32_t VTIM : 1; /*!< If set, The frames that do not have matching VLAN Tag are marked - as matched */ - __IO uint32_t ESVL : 1; /*!< If set, consider the S-VLAN (Type = 0x88A8) frames as valid - VLAN tagged frames */ - __IO uint32_t VTHM : 1; /*!< When set, the most significant four bits of the VLAN tag's CRC - are used to index the content */ - } VLAN_TAG_b; /*!< BitSize */ - }; - __I uint32_t RESERVED0[2]; - __IO uint32_t RWUFFR; /*!< Remote Wake-Up Frame Filter Register */ - - union { - __IO uint32_t PMTCSR; /*!< PMT Control and Status Register */ - - struct { - __IO uint32_t PWRDWN : 1; /*!< Power Down */ - __IO uint32_t MGKPKTEN : 1; /*!< Magic Packet Enable */ - __IO uint32_t RWKPKTEN : 1; /*!< Remote Wake-Up Frame Enable */ - uint32_t : 2; - __IO uint32_t MGKPRCVD : 1; /*!< the power management event is generated because of the reception - of a magic packet */ - __IO uint32_t RWKPRCVD : 1; /*!< When set, this bit indicates the power management event is generated - because of the reception of a remote wake-up frame */ - uint32_t : 2; - __IO uint32_t GLBLUCAST : 1; /*!< When set, enables any unicast packet filtered by the MAC (DAF)address - recognition to be a remote wake-up frame. */ - uint32_t : 14; - __IO uint32_t RWKPTR : 3; /*!< Remote Wake-up FIFO Pointer */ - uint32_t : 4; - __IO uint32_t RWKFILTRST : 1; /*!< Remote Wake-Up Frame Filter Register Pointer Reset. */ - } PMTCSR_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1[2]; - __IO uint32_t MACISR; /*!< Interrupt Status Register */ - __IO uint32_t MACIMR; /*!< Interrupt Mask Register */ - __IO uint16_t ADDR0_HIGH; /*!< MAC Address0 High Register */ - __I uint16_t RESERVED2; - __IO uint32_t ADDR0_LOW; /*!< MAC Address0 LOW Register */ - - union { - __IO uint32_t ADDR1_HIGH; /*!< MAC Address0 High Register */ - - struct { - __IO uint32_t ADDR : 16; /*!< MAC Address1 [47:32] */ - uint32_t : 14; - __IO uint32_t SA : 1; /*!< MAC address1 is source or destination address compared with - received frame */ - __IO uint32_t AE : 1; /*!< the address filter module uses the MAC address1 for filtering */ - } ADDR1_HIGH_b; /*!< BitSize */ - }; - __IO uint32_t ADDR1_LOW; /*!< MAC Address1 LOW Register */ - __I uint32_t RESERVED3[44]; - - union { - __IO uint32_t MMCCR; /*!< MMC Control Register */ - - struct { - __IO uint32_t CNTRST : 1; /*!< Counters Reset */ - __IO uint32_t CNTSTOPRO : 1; /*!< Counter Stop Rollover */ - __IO uint32_t RSTONRD : 1; /*!< Reset on Read */ - __IO uint32_t CNTFREEZ : 1; /*!< MMC Counter Freeze */ - __IO uint32_t CNTPRST : 1; /*!< Counters Preset */ - __IO uint32_t CNTPRSTLVL : 1; /*!< Counters Preset */ - uint32_t : 2; - __IO uint32_t UCDBC : 1; /*!< Update MMC Counters for Dropped Broadcast Frames */ - } MMCCR_b; /*!< BitSize */ - }; - __IO uint32_t MMCRIR; /*!< MMC Receive Interrupt Register */ - __IO uint32_t MMCTIR; /*!< MMC Transmit Interrupt Register */ - __IO uint32_t MMCRIMR; /*!< MMC Receive interrupt mask */ - __IO uint32_t MMCTIMR; /*!< MMC Transmit Interrupt Mask */ - __I uint32_t RESERVED4[59]; - __IO uint32_t MMCIRCOIM; /*!< MMC IPC Receive Checksum Offload Interrupt Mask */ - __I uint32_t RESERVED5[319]; - - union { - __IO uint32_t PTPTSCR; /*!< Timestamp Control Register */ - - struct { - __IO uint32_t TSENA : 1; /*!< Timestamp Enable */ - __IO uint32_t TSCFUPDT : 1; /*!< Timestamp Fine or Coarse Update */ - __IO uint32_t TSINIT : 1; /*!< Timestamp Initialize */ - __IO uint32_t TSUPDT : 1; /*!< Timestamp Update */ - __IO uint32_t TSTRIG : 1; /*!< Timestamp Interrupt Trigger Enable */ - __IO uint32_t TSADDREG : 1; /*!< Addend Reg Update */ - } PTPTSCR_b; /*!< BitSize */ - }; - __IO uint32_t PTPSSIR; /*!< Sub-Second Increment Register */ - __IO uint32_t PTPTSHR; /*!< System Time Seconds Register */ - __IO uint32_t PTPTSLR; /*!< System Time Nanoseconds Register */ - __IO uint32_t PTPTSHUR; /*!< System Time Seconds Update Register */ - __IO uint32_t PTPTSLUR; /*!< System Time Nanoseconds Update Register */ - __IO uint32_t PTPTSAR; /*!< Timestamp Addend Register */ - __IO uint32_t PTPTTHR; /*!< Target Time Seconds Register */ - __IO uint32_t PTPTTLR; /*!< Target Time Nanoseconds Register */ - __I uint32_t RESERVED6[567]; - - union { - __IO uint32_t BUS_MODE; /*!< Flow Control Register */ - - struct { - __IO uint32_t SWR : 1; /*!< Software Reset */ - __IO uint32_t DA : 1; /*!< This bit specifies the arbitration scheme between the transmit - and receive paths of Channel */ - __IO uint32_t DSL : 5; /*!< the byte number of bus width to skip between two unchained descriptors */ - __IO uint32_t ATDS : 1; /*!< When set, the size of the alternate descriptor increases to - 32 bytes */ - __IO uint32_t PBL : 6; /*!< These bits indicate the maximum number of beats to be transferred - in one DMA transaction */ - __IO uint32_t PR : 2; /*!< The Priority Ratio is (PR + 1) : 1 */ - __IO uint32_t FB : 1; /*!< performs fixed burst transfers or not */ - __IO uint32_t RPBL : 6; /*!< This field indicates the maximum number of beats to be transferred - in one Rx DMA transaction */ - __IO uint32_t USP : 1; /*!< If set, RPBL is same as RPBL definition */ - __IO uint32_t PBLx8 : 1; /*!< If set, all PBLs multiplies 8 */ - __IO uint32_t AAL : 1; /*!< If set, all bursts aligned to the start address LS bits */ - __IO uint32_t MB : 1; /*!< When this bit is set high and the FB bit is low, the AHB master - interface starts all bursts of length more than 16 with INCR */ - __IO uint32_t TXPR : 1; /*!< When set, the transmit DMA has higher priority than the receive - DMA */ - __IO uint32_t PRWG : 2; /*!< The Priority weight is (PRWG + 1) : 1 */ - uint32_t : 1; - __IO uint32_t RIB : 1; /*!< If set, rebuilds the pending beats of any burst transfer initiated - with INCRx */ - } BUS_MODE_b; /*!< BitSize */ - }; - __IO uint32_t TPD; /*!< Transmit Poll Demand */ - __IO uint32_t RPD; /*!< Receive Poll Demand */ - __IO uint32_t RDESLA; /*!< Receive Descriptor List Address */ - __IO uint32_t TDESLA; /*!< Transmit Descriptor List Address */ - - union { - __IO uint32_t STATUS; /*!< Status Register */ - - struct { - __IO uint32_t TI : 1; /*!< This bit indicates that the frame transmission is complete */ - __IO uint32_t TPS : 1; /*!< Transmit Process Stopped */ - __IO uint32_t TU : 1; /*!< the host owns the Next Descriptor in the Transmit List and the - DMA cannot acquire it. */ - __IO uint32_t TJT : 1; /*!< Transmit Jabber Timeout */ - __IO uint32_t OVF : 1; /*!< Receive Overflow */ - __IO uint32_t UNF : 1; /*!< Transmit Underflow */ - __IO uint32_t RI : 1; /*!< the frame reception is complete */ - __IO uint32_t RU : 1; /*!< Receive Buffer Unavailable */ - __IO uint32_t RPS : 1; /*!< Receive Process Stopped */ - __IO uint32_t RWT : 1; /*!< Receive Watchdog Timeout */ - __IO uint32_t ETI : 1; /*!< the frame to be transmitted is fully transferred to the MTL - Transmit FIFO */ - uint32_t : 2; - __IO uint32_t FBI : 1; /*!< a bus error occurred, as described in EB. */ - __IO uint32_t ERI : 1; /*!< the DMA filled the first data buffer of the packet */ - __IO uint32_t AIS : 1; /*!< Abnormal Interrupt Summary, must be cleared by writting */ - __IO uint32_t NIS : 1; /*!< Normal Interrupt Summary, must be cleared by writting */ - __I uint32_t RS : 3; /*!< Receive DMA FSM state */ - __I uint32_t TS : 3; /*!< Transmit DMA FSM state */ - __I uint32_t EB : 3; /*!< Error bit */ - __I uint32_t GLI : 1; /*!< GMAC Line Interface Interrupt */ - __I uint32_t GMI : 1; /*!< GMAC MMC Interrupt */ - __I uint32_t GPI : 1; /*!< GMAC PMT Interrupt */ - __I uint32_t TTI : 1; /*!< Timestamp Trigger Interrupt */ - } STATUS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t OPERATION; /*!< Operation Mode Register */ - - struct { - uint32_t : 1; - __IO uint32_t SR : 1; /*!< Start or Stop Receive */ - __IO uint32_t OSF : 1; /*!< Operate on Second Frame */ - __IO uint32_t RT : 2; /*!< Receive Threshold Control */ - __IO uint32_t DGF : 1; /*!< Drop Giant Frames */ - __IO uint32_t FUF : 1; /*!< Forward Undersized Good Frames */ - __IO uint32_t FEF : 1; /*!< Forward Error Frames */ - uint32_t : 5; - __IO uint32_t ST : 1; /*!< Start or Stop Transmission Command */ - __IO uint32_t TT : 3; /*!< Transmit Threshold Control */ - uint32_t : 3; - __IO uint32_t FTF : 1; /*!< Flush Transmit FIFO */ - __IO uint32_t TSF : 1; /*!< If set, transmission starts when a full frame resides in Transmit - FIFO */ - uint32_t : 2; - __IO uint32_t DFF : 1; /*!< Disable Flushing of Received Frames */ - __IO uint32_t RSF : 1; /*!< If set, the MTL reads a frame from the Rx FIFO while the complete - frame has been written to it, */ - } OPERATION_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INT_EN; /*!< Interrupt Enable Register */ - - struct { - __IO uint32_t TIE : 1; /*!< Transmit Interrupt Enable */ - __IO uint32_t TSE : 1; /*!< Transmit Stopped Enable */ - __IO uint32_t TUE : 1; /*!< Transmit Buffer Unavailable Enable */ - __IO uint32_t TJE : 1; /*!< Transmit Jabber Timeout Enable */ - __IO uint32_t OVE : 1; /*!< Overflow Interrupt Enable */ - __IO uint32_t UNE : 1; /*!< Underflow Interrupt Enable */ - __IO uint32_t RIE : 1; /*!< Receive Interrupt Enable */ - __IO uint32_t RUE : 1; /*!< Receive Buffer Unavailable Enable */ - __IO uint32_t RSE : 1; /*!< Receive Stopped Enable */ - __IO uint32_t RWE : 1; /*!< Receive Watchdog Timeout Enable */ - __IO uint32_t ETE : 1; /*!< Early Transmit Interrupt Enable */ - uint32_t : 2; - __IO uint32_t FBE : 1; /*!< Fatal Bus Error Enable */ - __IO uint32_t ERE : 1; /*!< Early Receive Interrupt Enable */ - __IO uint32_t AIE : 1; /*!< Abnormal Interrupt Summary Enable */ - __IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */ - } INT_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED7[3]; - - union { - __IO uint32_t AHB_STATUS; /*!< AHB Status Register */ - - struct { - __IO uint32_t BUSY : 1; /*!< If set, it indicates that the AHB master interface FSMs are - in the non-idle state */ - } AHB_STATUS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED8[6]; - __I uint32_t CURTDESAPTR; /*!< Current Host Transmit Descriptor Register */ - __I uint32_t CURRDESAPTR; /*!< Current Host Receive Descriptor Register */ - __I uint32_t CURTBUFAPTR; /*!< Current Host Transmit Buffer Address Register */ - __I uint32_t CURRBUFAPTR; /*!< Current Host Receive Buffer Address Register */ -} ETH_Type; - - -/* ================================================================================ */ -/* ================ USB ================ */ -/* ================================================================================ */ - - -/** - * @brief USB (USB) - */ - -typedef struct { /*!< USB Structure */ - - union { - __IO uint32_t GOTGCTL; /*!< Control and Status register */ - - struct { - __I uint32_t SES_REQ_SCS: 1; /*!< set when a session request initiation is successful as a device */ - __IO uint32_t SES_SEQ : 1; /*!< set to initiate a session request on the USB as a device */ - __IO uint32_t VB_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using - the GOTGCTL.VbvalidOvVal as a host */ - __IO uint32_t VB_VALID_OV_VAL: 1; /*!< set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn - is set as a host */ - __IO uint32_t A_VALID_OV_EN: 1; /*!< enable/disable the software to override the Avalid signal using - the GOTGCTL.AvalidOvVal as a host */ - __IO uint32_t A_VALID_OV_VAL: 1; /*!< set Override value for Avalid signal when GOTGCTL.AvalidOvEn - is set as a host */ - __IO uint32_t B_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using - the GOTGCTL.BvalidOvVal as a device. */ - __IO uint32_t B_VALID_OV_VAL: 1; /*!< set Override value for Bvalid signal when GOTGCTL.BvalidOvEn - is set as a device. */ - __I uint32_t HST_NEG_SCS: 1; /*!< sets when host negotiation is successful as a device. */ - __IO uint32_t HNP_REQ : 1; /*!< sets this bit to initiate an HNP request to the connected USB - host as a device */ - __IO uint32_t HST_SET_HNP_EN: 1; /*!< Host Set HNP Enable as a host */ - __IO uint32_t DEV_HNP_EN : 1; /*!< Device HNP Enabled as a device */ - uint32_t : 4; - __I uint32_t CON_ID_STS : 1; /*!< Connector ID Status */ - __I uint32_t DBNC_TIME : 1; /*!< the debounce time of a detected connection as a host */ - __I uint32_t A_SES_VLD : 1; /*!< A-Session Valid as a host */ - __I uint32_t B_SES_VLD : 1; /*!< B-Session Valid as a host */ - __IO uint32_t OTG_VER : 1; /*!< If 0, OTG Version 1.3. If 1, OTG Version 2.0. */ - } GOTGCTL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GOTGINT; /*!< OTG interrupt Register */ - - struct { - uint32_t : 2; - __IO uint32_t SES_END_DET: 1; /*!< Set when the utmiotg_bvalid signal is deasserted */ - uint32_t : 5; - __IO uint32_t SES_REQ_SUC_STS_CHNG: 1; /*!< Session Request Success Status Change */ - __IO uint32_t HST_NEG_SUC_STS_CHNG: 1; /*!< Host Negotiation Success Status Change */ - uint32_t : 7; - __IO uint32_t HST_NEG_DET: 1; /*!< if set, detects a host negotiation request on the USB */ - __IO uint32_t A_DEV_TOUT_CHG: 1; /*!< A-device has timed out while waiting for the B-device to connect */ - __IO uint32_t DBNCE_DONE : 1; /*!< debounce is completed after the device connect as a host */ - } GOTGINT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GAHBCFG; /*!< AHB Configuration Register */ - - struct { - __IO uint32_t GLBL_INTR_EN: 1; /*!< Global Interrupt Enable */ - __IO uint32_t BST_LEN : 4; /*!< Burst Length/Type */ - __IO uint32_t DMA_EN : 1; /*!< DMA enable */ - uint32_t : 15; - __IO uint32_t REMOTE_MEM_SUPP: 1; /*!< enable the functionality to wait for the system DMA Done Signal - for the DMA Write Transfers */ - __IO uint32_t NOTIFY_ALL_DMA_WRITE: 1; /*!< enable the System DMA Done functionality for all the DMA write - Transactions corresponding to the Channel/Endpoint */ - __IO uint32_t AHB_SINGLE : 1; /*!< supports Single transfers for the remaining data in a transfer */ - } GAHBCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GUSBCFG; /*!< USB Configuration Register */ - - struct { - uint32_t : 3; - __IO uint32_t PHY_IF : 1; /*!< PHY Interface */ - __IO uint32_t ULPI_UTMI_SEL: 1; /*!< 1, ULPI. 0, UTMI+ */ - __IO uint32_t FS_IF : 1; /*!< 1, 3-pin bidirectional. 0, 6-pin unidirectional */ - __IO uint32_t PHY_SEL : 1; /*!< 0, USB 2.0 High-Speed PHY. 1, USB 1.1 full-speed serial transceiver */ - __IO uint32_t DDR_SEL : 1; /*!< 0, Single Data Rate ULPI Interface, with 8-bit-wide data bus. - 1, Double Data Rate ULPI Interface, with 4-bit-wide data bus */ - __IO uint32_t SRP_CAP : 1; /*!< SRP-Capable */ - __IO uint32_t HNP_CAP : 1; /*!< HNP-Capable */ - __IO uint32_t USB_TRD_TIM: 4; /*!< Specifies the response time for a MAC request to the Packet - FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM) as - a device. */ - uint32_t : 1; - __IO uint32_t PHY_LPWR_CLK_SEL: 1; /*!< 0, 480-MHz Internal PLL clock. 1, 48-MHz External Clock */ - uint32_t : 12; - __IO uint32_t TX_END_DELAY: 1; /*!< Tx End Delay as a device */ - __IO uint32_t FORCE_HOST_MODE: 1; /*!< Force Host Mode */ - __IO uint32_t FORCE_DEVICE_MODE: 1; /*!< Force Device Mode */ - } GUSBCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GRSTCTL; /*!< Reset Register */ - - struct { - __IO uint32_t CORE_SOFT_RST: 1; /*!< Core Soft Reset */ - uint32_t : 1; - __IO uint32_t FRM_CNT_RST: 1; /*!< Host Frame Counter Reset */ - uint32_t : 1; - __IO uint32_t RX_FIFO_FLUSH: 1; /*!< RxFIFO Flush */ - __IO uint32_t TX_FIFO_FLUSH: 1; /*!< TxFIFO Flush */ - __IO uint32_t TX_FIFO_FLUSH_NUM: 4; /*!< This field indicates which of the 32 possible PHY devices are - being accessed */ - __IO uint32_t TX_FIFO_ALL: 1; /*!< TxFIFO flush all FIFOs */ - uint32_t : 19; - __I uint32_t DMA_REQ : 1; /*!< Indicates that the DMA request is in progress */ - __I uint32_t AHB_IDLE : 1; /*!< Indicates that the AHB Master State Machine is in the IDLE condition */ - } GRSTCTL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GINTSTS; /*!< Interrupt Register */ - - struct { - __I uint32_t CUR_MOD : 1; /*!< Current Mode of Operation */ - __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch Interrupt */ - __I uint32_t OTG_INT : 1; /*!< OTG Interrupt */ - __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ - __I uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ - __I uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ - __I uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ - __I uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ - uint32_t : 2; - __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ - __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ - __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ - __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ - __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a - device */ - __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ - uint32_t : 1; - __I uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ - __I uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ - __I uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ - __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ - __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous - OUT Transfer as a device */ - __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ - __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ - __I uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as - a host */ - __I uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as - a host */ - __I uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ - __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ - __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ - __IO uint32_t DD : 1; /*!< A change in connector ID status */ - __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ - __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ - } GINTSTS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GINTEN; /*!< Interrupt enable Register */ - - struct { - uint32_t : 1; - __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch */ - __IO uint32_t OTG_INT : 1; /*!< OTG */ - __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ - __IO uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ - __IO uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ - __IO uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ - __IO uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ - uint32_t : 2; - __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ - __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ - __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ - __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ - __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a - device */ - __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ - uint32_t : 1; - __IO uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ - __IO uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ - __IO uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ - __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ - __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous - OUT Transfer as a device */ - __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ - __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ - __IO uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as - a host */ - __IO uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as - a host */ - __IO uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ - __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ - __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ - __IO uint32_t DD : 1; /*!< A change in connector ID status */ - __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ - __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ - } GINTEN_b; /*!< BitSize */ - }; - - union { - __I uint32_t GRXSTSR; /*!< Returns the contents of the top of the Receive FIFO */ - - struct { - __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ - __I uint32_t BCNT : 11; /*!< byte count of the received packet */ - __I uint32_t DPID : 2; /*!< Data PID of the received packet */ - __I uint32_t PS : 4; /*!< the status of the received packet */ - __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which - the packet is received on the USB */ - } GRXSTSR_b; /*!< BitSize */ - }; - - union { - __I uint32_t GRXSTSP; /*!< Pop the contents of the top of the Receive FIFO */ - - struct { - __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ - __I uint32_t BCNT : 11; /*!< byte count of the received packet */ - __I uint32_t DPID : 2; /*!< Data PID of the received packet */ - __I uint32_t PS : 4; /*!< the status of the received packet */ - __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which - the packet is received on the USB */ - } GRXSTSP_b; /*!< BitSize */ - }; - __IO uint16_t GRXFSIZ; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 - is max */ - __I uint16_t RESERVED0; - - union { - __IO uint32_t GNPTXFSIZ; /*!< Non-Periodic Transmit FIFO Size Register */ - - struct { - __IO uint32_t NTRSA_INEF0TRSA: 16; /*!< start address for Non-periodic Transmit FIFO RAM as a host or - IN Endpoint FIFO0 Transmit RAM as a device */ - __IO uint32_t NTD_INEF0TD: 16; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 - is max. Non-periodic TxFIFO Depth as a host or IN Endpoint TxFIFO - 0 Depth as a device */ - } GNPTXFSIZ_b; /*!< BitSize */ - }; - - union { - __I uint32_t GNPTXSTS; /*!< Non-Periodic Transmit FIFO/Queue Status Register */ - - struct { - __I uint32_t NTSA : 16; /*!< the amount of free space available in the Non-periodic TxFIFO, - max is 32768. */ - __I uint32_t NTRQSA : 8; /*!< the amount of free space available in the Non-periodic Transmit - Request Queue, max is 8. */ - __I uint32_t TNTRQ_LAST : 1; /*!< last Entry in the Non-periodic Tx Request Queue that is currently - being processed by the MAC */ - __I uint32_t TNTRQ_TYPE : 2; /*!< type in the Non-periodic Tx Request Queue that is currently - being processed by the MAC */ - __I uint32_t TNTRQ_CH : 4; /*!< Channel of top of the Non-periodic Transmit Request Queue */ - } GNPTXSTS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1[5]; - - union { - __I uint32_t GHWCFG1; /*!< User HW Config1 Register */ - - struct { - __I uint32_t EP0_DIR : 2; /*!< Endpoint 0 direction, always Bidirection */ - __I uint32_t EP1_DIR : 2; /*!< Endpoint 1 direction */ - __I uint32_t EP2_DIR : 2; /*!< Endpoint 2 direction */ - __I uint32_t EP3_DIR : 2; /*!< Endpoint 3 direction */ - __I uint32_t EP4_DIR : 2; /*!< Endpoint 4 direction */ - __I uint32_t EP5_DIR : 2; /*!< Endpoint 5 direction */ - __I uint32_t EP6_DIR : 2; /*!< Endpoint 6 direction */ - __I uint32_t EP7_DIR : 2; /*!< Endpoint 7 direction */ - __I uint32_t EP8_DIR : 2; /*!< Endpoint 8 direction */ - __I uint32_t EP9_DIR : 2; /*!< Endpoint 9 direction */ - __I uint32_t EP10_DIR : 2; /*!< Endpoint 10 direction */ - __I uint32_t EP11_DIR : 2; /*!< Endpoint 11 direction */ - __I uint32_t EP12_DIR : 2; /*!< Endpoint 12 direction */ - __I uint32_t EP13_DIR : 2; /*!< Endpoint 13 direction */ - __I uint32_t EP14_DIR : 2; /*!< Endpoint 14 direction */ - __I uint32_t EP15_DIR : 2; /*!< Endpoint 15 direction */ - } GHWCFG1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2[3]; - - union { - __IO uint32_t GLPMCFG; /*!< Core LPM Configuration Register */ - - struct { - __IO uint32_t EP0_DIR : 1; /*!< LPM capability is enabled */ - } GLPMCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GPWRDN; /*!< Global Power Down Register */ - - struct { - uint32_t : 1; - __IO uint32_t PMU_ACTIVE : 1; /*!< PMU Active is enabled */ - uint32_t : 1; - __IO uint32_t PDC : 1; /*!< Power Down Clamp is enabled */ - __IO uint32_t PDR : 1; /*!< If clear, Reset DWC_otg */ - __IO uint32_t PDS : 1; /*!< If 0, DWC_otg is in ON state, or OFF state */ - __IO uint32_t DIS_VBUS : 1; /*!< Disable VBUS */ - uint32_t : 8; - __IO uint32_t SRP_DETECT_INT: 1; /*!< SRP has been detected by the PMU as a host */ - __IO uint32_t SRP_DETECT_INT_EN: 1; /*!< Enable For SRPDetect Interrupt as a host */ - __IO uint32_t STATE_CHN_INT: 1; /*!< a status change in either the IDDIG or BSessVld signal */ - __IO uint32_t STATE_CHN_INT_EN: 1; /*!< Enable For Status Change Interrupt */ - __I uint32_t LINE_STATE : 2; /*!< the current linestate on USB as seen by the PMU module */ - __I uint32_t IDDIG : 1; /*!< the status of the IDDIG signal. If 0, host mode. if 1, device - mode */ - __I uint32_t B_SESS_VLD : 1; /*!< B session valid status signal from the PHY */ - __IO uint32_t ADP_INT : 1; /*!< set whenever there is a ADP event */ - } GPWRDN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t GDFIFOCFG; /*!< Global DFIFO Software Config Register */ - - struct { - __IO uint32_t GDFIFOCFG : 16; /*!< This field is for dynamic programming of the DFIFO Size. */ - __IO uint32_t EPIBA : 16; /*!< This field provides the start address of the EP info controller */ - } GDFIFOCFG_b; /*!< BitSize */ - }; - __I uint32_t RESERVED3[40]; - - union { - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Transmit FIFO Size Register */ - - struct { - __IO uint32_t HPTSA : 16; /*!< start address of the Periodic TxFIFO */ - __IO uint32_t EPIBA : 16; /*!< the size of the Periodic TxFIFO */ - } HPTXFSIZ_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF1; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF2; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF3; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF4; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF5; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF6; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF7; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF8; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF9; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF10; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF11; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF12; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF13; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF14; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DIEPTXF15; /*!< Device In Endpoint Transmit FIFO Size Register */ - - struct { - __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ - } DIEPTXF15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED4[176]; - - union { - __IO uint32_t HCFG; /*!< Host Configuration Register */ - - struct { - __IO uint32_t FS_LS_PCS : 2; /*!< FS/LS PHY Clock Select as a host */ - __IO uint32_t FS_LS_SUPPORT: 1; /*!< If set, FS/LS-only, even If the connected device can support - HS */ - uint32_t : 4; - __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ - __IO uint32_t RVP : 8; /*!< ResValid number of clock cycles to detect a valid resume */ - uint32_t : 7; - __IO uint32_t EN_SG_DMA : 1; /*!< Enable Scatter/gather DMA in Host mode */ - __IO uint32_t FLE : 2; /*!< the number of entries in the Frame list. 8 times of FLE */ - __IO uint32_t EPS : 1; /*!< Enables periodic scheduling */ - uint32_t : 4; - __IO uint32_t MCRTE : 1; /*!< enable/disable the Host core to wait 200 PHY clock cycles at - the end of Resume to change the opmode signal to the PHY to - 00 after Suspend or LPM. */ - } HCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HFIR; /*!< Host Frame Interval Register */ - - struct { - __IO uint32_t FI : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ - __IO uint32_t RC : 1; /*!< The HFIR can be dynamically reloaded during runtime if set */ - } HFIR_b; /*!< BitSize */ - }; - - union { - __I uint32_t HFNUM; /*!< Host Frame Number/Frame Time Remaining Register */ - - struct { - __I uint32_t FN : 16; /*!< This field increments when a new SOF is transmitted on the USB */ - __I uint32_t FTR : 16; /*!< amount of time remaining in the current microframe (HS) or Frame - (FS/LS), in terms of PHY clocks */ - } HFNUM_b; /*!< BitSize */ - }; - __I uint32_t RESERVED5; - - union { - __I uint32_t HPTXSTS; /*!< Host Periodic Transmit FIFO/Queue Status Register */ - - struct { - __I uint32_t PTDFSA : 16; /*!< Indicates the number of free locations available to be written - to in the Periodic TxFIFO, max is 32768 */ - __I uint32_t PTRQSA : 8; /*!< Indicates the number of free locations available to be written - in the Periodic Transmit Request Queue, max is 16 */ - __I uint32_t TPTRQ_LAST : 1; /*!< last Entry in the periodic Tx Request Queue that is currently - being processed by the MAC */ - __I uint32_t TPTRQ_TYPE : 2; /*!< type in the periodic Tx Request Queue that is currently being - processed by the MAC */ - __I uint32_t TPTRQ_CH : 4; /*!< Channel of top of the periodic Transmit Request Queue */ - __I uint32_t TPTRQ_ODD_FRAME: 1; /*!< If set, send in odd (micro)Frame */ - } HPTXSTS_b; /*!< BitSize */ - }; - - union { - __I uint32_t HAINT; /*!< Host All Channels Interrupt Register */ - - struct { - __I uint32_t INT : 16; /*!< Channel Interrupts, from 0 to 15. */ - } HAINT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HAINT_EN; /*!< Host All Channels Interrupt Enable Register */ - - struct { - __IO uint32_t EN : 16; /*!< Channel Interrupts Enable, from 0 to 15. */ - } HAINT_EN_b; /*!< BitSize */ - }; - __IO uint32_t HFLBA; /*!< The starting address of the Frame list */ - __I uint32_t RESERVED6[8]; - - union { - __IO uint32_t __HPRT; /*!< Host Port Control and Status Register */ - - struct { - __I uint32_t PCS : 1; /*!< If a device is attached to the port */ - __IO uint32_t PCD : 1; /*!< A device connection is detected */ - __IO uint32_t PE : 1; /*!< Port Enable */ - __IO uint32_t PEDC : 1; /*!< Set if when the status of the Port Enable (bit 2) of this register - changes */ - __I uint32_t POA : 1; /*!< Indicates the overcurrent condition of the port */ - __IO uint32_t POC : 1; /*!< Set if when the status of the Port Overcurrent Active bit (bit - 4) in this register changes */ - __IO uint32_t PR : 1; /*!< Application and Core all can perform resume by setting, then - clear it whatever resume is success or not */ - __IO uint32_t PS : 1; /*!< Sets this bit to put this port in Suspend mode */ - __IO uint32_t PRESET : 1; /*!< sets this bit, a reset sequence is started on this port */ - uint32_t : 1; - __IO uint32_t PLSDP : 1; /*!< Logic level of D+ */ - __IO uint32_t PLSDN : 1; /*!< Logic level of D- */ - __IO uint32_t PP : 1; /*!< this field to control power to this port. 1, power on */ - __IO uint32_t PTC : 4; /*!< The application writes a nonzero value to this field to put - the port into a Test mode */ - __I uint32_t SPEED : 2; /*!< Indicates the speed of the device attached to this port */ - } __HPRT_b; /*!< BitSize */ - }; - __I uint32_t RESERVED7[47]; - - union { - __IO uint32_t HCC0; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED8; - - union { - __IO uint32_t HCINT0; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN0; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ0; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA0; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED9; - __IO uint32_t HCDMAB0; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC1; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED10; - - union { - __IO uint32_t HCINT1; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN1; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ1; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA1; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED11; - __IO uint32_t HCDMAB1; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC2; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED12; - - union { - __IO uint32_t HCINT2; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN2; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ2; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA2; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED13; - __IO uint32_t HCDMAB2; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC3; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED14; - - union { - __IO uint32_t HCINT3; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN3; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ3; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA3; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED15; - __IO uint32_t HCDMAB3; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC4; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED16; - - union { - __IO uint32_t HCINT4; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN4; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ4; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ4_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA4; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED17; - __IO uint32_t HCDMAB4; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC5; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED18; - - union { - __IO uint32_t HCINT5; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN5; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ5; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ5_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA5; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED19; - __IO uint32_t HCDMAB5; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC6; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED20; - - union { - __IO uint32_t HCINT6; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN6; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ6; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ6_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA6; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED21; - __IO uint32_t HCDMAB6; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC7; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED22; - - union { - __IO uint32_t HCINT7; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN7; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ7; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ7_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA7; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED23; - __IO uint32_t HCDMAB7; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC8; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED24; - - union { - __IO uint32_t HCINT8; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN8; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ8; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ8_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA8; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED25; - __IO uint32_t HCDMAB8; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC9; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED26; - - union { - __IO uint32_t HCINT9; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN9; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ9; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ9_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA9; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED27; - __IO uint32_t HCDMAB9; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC10; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED28; - - union { - __IO uint32_t HCINT10; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN10; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ10; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ10_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA10; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED29; - __IO uint32_t HCDMAB10; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC11; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED30; - - union { - __IO uint32_t HCINT11; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN11; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ11; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ11_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA11; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED31; - __IO uint32_t HCDMAB11; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC12; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED32; - - union { - __IO uint32_t HCINT12; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN12; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ12; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ12_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA12; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED33; - __IO uint32_t HCDMAB12; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC13; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED34; - - union { - __IO uint32_t HCINT13; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN13; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ13; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ13_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA13; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED35; - __IO uint32_t HCDMAB13; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC14; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED36; - - union { - __IO uint32_t HCINT14; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN14; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ14; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ14_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA14; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED37; - __IO uint32_t HCDMAB14; /*!< Host Channel-n DMA Buffer Address Register */ - - union { - __IO uint32_t HCC15; /*!< Host Channel Characteristics Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ - uint32_t : 1; - __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ - __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source - or sink. */ - __IO uint32_t OF : 1; /*!< The frame is odd or even. */ - __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ - __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not - yet. */ - } HCC15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED38; - - union { - __IO uint32_t HCINT15; /*!< Host Channel Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT15_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCINT_EN15; /*!< Host Channel Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data - source or sink. */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - uint32_t : 8; - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ - __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ - } HCINT_EN15_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCTSIZ15; /*!< Host Channel Transfer Size Register */ - - struct { - __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that - microframe.Bit N indicates scheduling for Nth microframe scheduling - for 8th microframe in that frame. */ - __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ - uint32_t : 13; - __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ - __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ - } HCTSIZ15_b; /*!< BitSize */ - }; - - union { - __IO uint32_t HCDMA15; /*!< Host Channel-n DMA Address Register */ - - struct { - uint32_t : 3; - __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ - __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ - } HCDMA15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED39; - __IO uint32_t HCDMAB15; /*!< Host Channel-n DMA Buffer Address Register */ - __I uint32_t RESERVED40[64]; - - union { - __IO uint32_t DCFG; /*!< Device Configuration Register */ - - struct { - __IO uint32_t DSPEED : 2; /*!< the maximum speed the application can support */ - __IO uint32_t NZLSOH : 1; /*!< select the handshake the core sends on receiving a non zero-length - data packet during the OUT transaction of a control transfer's - Status stage */ - __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ - __IO uint32_t DEVICE_ADDR: 7; /*!< The application must program this field after every SetAddress - control command */ - __IO uint32_t PFI : 2; /*!< Indicates the time within a (micro)frame at which the application - must be notified using the End Of Periodic Frame Interrupt */ - __IO uint32_t EDON : 1; /*!< If set the core sets NAK after Bulk OUT transfer complete */ - uint32_t : 9; - __IO uint32_t EN_SG_DMA : 1; /*!< enable the Scatter/Gather DMA operation */ - __IO uint32_t PSI : 2; /*!< Periodic Scheduling Interval */ - __IO uint32_t RVP : 6; /*!< It controls the resume period when the core resumes from suspend */ - } DCFG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DCTL; /*!< Device Control Register */ - - struct { - __IO uint32_t RWS : 1; /*!< If set, the core initiates remote signaling to wake the USB - hosts */ - __IO uint32_t SD : 1; /*!< If set, generates a device disconnect event to the USB host */ - __I uint32_t GNPINS : 1; /*!< A NAK handshake is sent out on all non-periodic IN endpoints, - irrespective of the data availability in the transmit FIFO. */ - __I uint32_t GONS : 1; /*!< No data is written to the RxFIFO, irrespective of space availability.. */ - __IO uint32_t TC : 3; /*!< Test Control */ - __O uint32_t SGNPIN : 1; /*!< A write to this field sets the Global Non-periodic IN NAK */ - __O uint32_t CGNPIN : 1; /*!< A write to this field clears the Global Non-periodic IN NAK */ - __O uint32_t SGON : 1; /*!< A write to this field sets the Global OUT NAK */ - __O uint32_t CGON : 1; /*!< A write to this field sets the Global OUT NAK. */ - __IO uint32_t POPD : 1; /*!< Power-On Programming Done */ - __IO uint32_t GMC : 2; /*!< GMC must be programmed only once after initialization. the number - of packets to be serviced for that end point before moving to - the next end point */ - uint32_t : 1; - __IO uint32_t IFNIE : 1; /*!< Ignore frame number for isochronous endpoints */ - __IO uint32_t NBE : 1; /*!< Set NAK automatically on babble */ - __IO uint32_t ECBNA : 1; /*!< After receiving BNA interrupt, the core disables the endpoint */ - } DCTL_b; /*!< BitSize */ - }; - - union { - __I uint32_t DSTS; /*!< Device Status Register */ - - struct { - __I uint32_t SUSPEND : 1; /*!< this bit is set as long as a Suspend condition is detected on - the USB */ - __I uint32_t SPEED : 2; /*!< Indicates the speed at which the DWC_otg core has come up after - speed detection through a chirp sequence */ - __I uint32_t EE : 1; /*!< reason of suspend state */ - uint32_t : 4; - __I uint32_t SOFFN : 14; /*!< Frame or Microframe Number of the Received SOF */ - __I uint32_t DLSDP : 1; /*!< Logic level of D+ */ - __I uint32_t DLSDN : 1; /*!< Logic level of D- */ - } DSTS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED41; - - union { - __IO uint32_t DIEPEN; /*!< Device IN Endpoint Common Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ - __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ - __IO uint32_t TIMEOUT : 1; /*!< Timeout Condition(Non-isochronous endpoints) */ - __IO uint32_t ITRWTFE : 1; /*!< IN Token Received When TxFIFO Empty */ - __IO uint32_t ITRWEPM : 1; /*!< IN Token received with EP Mismatch */ - __IO uint32_t IENE : 1; /*!< IN Endpoint NAK Effective */ - uint32_t : 1; - __IO uint32_t FU : 1; /*!< Fifo Underrun */ - __IO uint32_t BNA : 1; /*!< BNA Interrupt */ - uint32_t : 3; - __IO uint32_t NAK : 1; /*!< NAK interrupt */ - } DIEPEN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DOEPEN; /*!< Device OUT Endpoint Common Interrupt Enable Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ - __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ - __IO uint32_t SPD : 1; /*!< SETUP Phase Done, Applies to control endpoints only */ - __IO uint32_t OTRWED : 1; /*!< OUT Token Received when Endpoint Disabled, Applies to control - OUT endpoints only */ - __IO uint32_t SPR : 1; /*!< Status Phase Received */ - __IO uint32_t BTBSPR : 1; /*!< Back-to-Back SETUP Packets Received, Applies to control OUT - endpoints only */ - uint32_t : 1; - __IO uint32_t OPE : 1; /*!< OUT Packet Error */ - __IO uint32_t BNA : 1; /*!< BNA Interrupt */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error interrupt */ - __IO uint32_t NAK : 1; /*!< NAK interrupt */ - __IO uint32_t NYET : 1; /*!< NYET interrupt */ - } DOEPEN_b; /*!< BitSize */ - }; - - union { - __I uint32_t DAINT; /*!< Device All Channels Interrupt Register */ - - struct { - __I uint32_t INT : 16; /*!< IN Endpoint Interrupt Bits, from 0 to 15. */ - __I uint32_t OUT_INT : 16; /*!< OUT Endpoint Interrupt Bits, from 0 to 15. */ - } DAINT_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DAINT_EN; /*!< Device All Channels Interrupt Enable Register */ - - struct { - __IO uint32_t IN_EN : 16; /*!< IN EP Interrupt Enable, from 0 to 15. */ - __IO uint32_t OUT_EN : 16; /*!< OUT EP Interrupt Enable, from 0 to 15. */ - } DAINT_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED42[4]; - - union { - __IO uint32_t DTHRCTL; /*!< Device Threshold Control Register */ - - struct { - __IO uint32_t NISOINETE : 1; /*!< Non-ISO IN Endpoints Threshold Enable */ - __IO uint32_t ISOINETE : 1; /*!< ISO IN Endpoints Threshold Enable */ - __IO uint32_t TTL : 9; /*!< This field specifies Transmit thresholding size in DWORDS */ - __IO uint32_t ATR : 2; /*!< These bits define the ratio between the AHB threshold and the - MAC threshold for the transmit path only. */ - uint32_t : 3; - __IO uint32_t RTE : 1; /*!< If set, the core enables thresholding in the receive direction */ - __IO uint32_t RTL : 9; /*!< This field specifies Receive thresholding size in DWORDS */ - uint32_t : 1; - __IO uint32_t APE : 1; /*!< This bit controls internal DMA arbiter parking for IN endpoints */ - } DTHRCTL_b; /*!< BitSize */ - }; - __IO uint16_t DIEPEMPEN; /*!< Device IN Endpoint FIFO Empty Interrupt Enable Register */ - __I uint16_t RESERVED43[101]; - - union { - __IO uint32_t DIEPCTL0; /*!< Device Control IN Endpoint 0 Control Register */ - - struct { - __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, - applies to IN and OUT endpoints */ - uint32_t : 13; - __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active - in all configurations and interfaces */ - uint32_t : 1; - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ - __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a - SETUP token is received for this endpoint */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - uint32_t : 2; - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED44; - - union { - __IO uint32_t DIEPINT0; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED45; - - union { - __IO uint32_t DIEPTSIZ0; /*!< Device IN Endpoint 0 Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ - uint32_t : 12; - __IO uint32_t PACKET_CNT : 2; /*!< the total number of USB packets */ - } DIEPTSIZ0_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA0; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA0; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED46; - __I uint32_t DIEPDMAB0; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL1; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED47; - - union { - __IO uint32_t DIEPINT1; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED48; - - union { - __IO uint32_t DIEPTSIZ1; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ1_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA1; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA1; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED49; - __I uint32_t DIEPDMAB1; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL2; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED50; - - union { - __IO uint32_t DIEPINT2; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED51; - - union { - __IO uint32_t DIEPTSIZ2; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ2_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA2; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA2; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED52; - __I uint32_t DIEPDMAB2; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL3; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED53; - - union { - __IO uint32_t DIEPINT3; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED54; - - union { - __IO uint32_t DIEPTSIZ3; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ3_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA3; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA3; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED55; - __I uint32_t DIEPDMAB3; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL4; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED56; - - union { - __IO uint32_t DIEPINT4; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED57; - - union { - __IO uint32_t DIEPTSIZ4; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ4_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA4; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA4; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED58; - __I uint32_t DIEPDMAB4; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL5; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED59; - - union { - __IO uint32_t DIEPINT5; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED60; - - union { - __IO uint32_t DIEPTSIZ5; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ5_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA5; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA5; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED61; - __I uint32_t DIEPDMAB5; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL6; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED62; - - union { - __IO uint32_t DIEPINT6; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED63; - - union { - __IO uint32_t DIEPTSIZ6; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ6_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA6; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA6; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED64; - __I uint32_t DIEPDMAB6; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL7; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED65; - - union { - __IO uint32_t DIEPINT7; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED66; - - union { - __IO uint32_t DIEPTSIZ7; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ7_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA7; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA7; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED67; - __I uint32_t DIEPDMAB7; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL8; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED68; - - union { - __IO uint32_t DIEPINT8; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED69; - - union { - __IO uint32_t DIEPTSIZ8; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ8_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA8; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA8; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED70; - __I uint32_t DIEPDMAB8; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL9; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED71; - - union { - __IO uint32_t DIEPINT9; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED72; - - union { - __IO uint32_t DIEPTSIZ9; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ9_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA9; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA9; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED73; - __I uint32_t DIEPDMAB9; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL10; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED74; - - union { - __IO uint32_t DIEPINT10; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED75; - - union { - __IO uint32_t DIEPTSIZ10; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ10_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA10; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA10; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED76; - __I uint32_t DIEPDMAB10; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL11; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED77; - - union { - __IO uint32_t DIEPINT11; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED78; - - union { - __IO uint32_t DIEPTSIZ11; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ11_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA11; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA11; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED79; - __I uint32_t DIEPDMAB11; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL12; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED80; - - union { - __IO uint32_t DIEPINT12; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED81; - - union { - __IO uint32_t DIEPTSIZ12; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ12_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA12; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA12; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED82; - __I uint32_t DIEPDMAB12; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL13; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED83; - - union { - __IO uint32_t DIEPINT13; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED84; - - union { - __IO uint32_t DIEPTSIZ13; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ13_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA13; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA13; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED85; - __I uint32_t DIEPDMAB13; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL14; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED86; - - union { - __IO uint32_t DIEPINT14; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED87; - - union { - __IO uint32_t DIEPTSIZ14; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ14_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA14; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA14; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED88; - __I uint32_t DIEPDMAB14; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DIEPCTL15; /*!< Device IN Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - uint32_t : 1; - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. - To control endpoints, response an ACK */ - __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an - endpoint even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - transmit is setup */ - } DIEPCTL15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED89; - - union { - __IO uint32_t DIEPINT15; /*!< Device IN Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this - endpoint */ - __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ - __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ - __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DIEPINT15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED90; - - union { - __IO uint32_t DIEPTSIZ15; /*!< Device IN Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. - The number of packets must be fetched per non-periodic IN endpoints */ - } DIEPTSIZ15_b; /*!< BitSize */ - }; - __IO uint32_t DIEPDMA15; /*!< Device IN Endpoint-n DMA Address Register */ - __IO uint16_t DTXFSA15; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ - __I uint16_t RESERVED91; - __I uint32_t DIEPDMAB15; /*!< Device IN Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL0; /*!< Device Control OUT Endpoint 0 Control Register */ - - struct { - __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, - applies to IN and OUT endpoints */ - uint32_t : 13; - __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active - in all configurations and interfaces */ - uint32_t : 1; - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ - __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ - __IO uint32_t SNOOP : 1; /*!< does not check if the OUT packets are correct before transferring */ - __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a - SETUP token is received for this endpoint */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - uint32_t : 2; - __I uint32_t EPD : 1; /*!< The application cannot disable control OUT endpoint 0 */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED92; - - union { - __IO uint32_t DOEPINT0; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT0_b; /*!< BitSize */ - }; - __I uint32_t RESERVED93; - - union { - __IO uint32_t DOEPTSIZ0; /*!< Device OUT Endpoint 0 Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ - uint32_t : 12; - __IO uint32_t PACKET_CNT : 1; /*!< This field is decremented to zero after a packet is written - into the RxFIFO */ - uint32_t : 9; - __IO uint32_t SETUP_CNT : 2; /*!< the number of back-to-back SETUP data packets the endpoint can - receive */ - } DOEPTSIZ0_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA0; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED94; - __I uint32_t DOEPDMAB0; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL1; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED95; - - union { - __IO uint32_t DOEPINT1; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT1_b; /*!< BitSize */ - }; - __I uint32_t RESERVED96; - - union { - __IO uint32_t DOEPTSIZ1; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ1_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA1; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED97; - __I uint32_t DOEPDMAB1; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL2; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED98; - - union { - __IO uint32_t DOEPINT2; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT2_b; /*!< BitSize */ - }; - __I uint32_t RESERVED99; - - union { - __IO uint32_t DOEPTSIZ2; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ2_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA2; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED100; - __I uint32_t DOEPDMAB2; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL3; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED101; - - union { - __IO uint32_t DOEPINT3; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT3_b; /*!< BitSize */ - }; - __I uint32_t RESERVED102; - - union { - __IO uint32_t DOEPTSIZ3; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ3_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA3; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED103; - __I uint32_t DOEPDMAB3; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL4; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED104; - - union { - __IO uint32_t DOEPINT4; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT4_b; /*!< BitSize */ - }; - __I uint32_t RESERVED105; - - union { - __IO uint32_t DOEPTSIZ4; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ4_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA4; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED106; - __I uint32_t DOEPDMAB4; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL5; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED107; - - union { - __IO uint32_t DOEPINT5; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT5_b; /*!< BitSize */ - }; - __I uint32_t RESERVED108; - - union { - __IO uint32_t DOEPTSIZ5; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ5_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA5; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED109; - __I uint32_t DOEPDMAB5; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL6; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED110; - - union { - __IO uint32_t DOEPINT6; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT6_b; /*!< BitSize */ - }; - __I uint32_t RESERVED111; - - union { - __IO uint32_t DOEPTSIZ6; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ6_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA6; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED112; - __I uint32_t DOEPDMAB6; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL7; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED113; - - union { - __IO uint32_t DOEPINT7; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT7_b; /*!< BitSize */ - }; - __I uint32_t RESERVED114; - - union { - __IO uint32_t DOEPTSIZ7; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ7_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA7; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED115; - __I uint32_t DOEPDMAB7; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL8; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED116; - - union { - __IO uint32_t DOEPINT8; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT8_b; /*!< BitSize */ - }; - __I uint32_t RESERVED117; - - union { - __IO uint32_t DOEPTSIZ8; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ8_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA8; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED118; - __I uint32_t DOEPDMAB8; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL9; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED119; - - union { - __IO uint32_t DOEPINT9; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT9_b; /*!< BitSize */ - }; - __I uint32_t RESERVED120; - - union { - __IO uint32_t DOEPTSIZ9; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ9_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA9; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED121; - __I uint32_t DOEPDMAB9; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL10; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED122; - - union { - __IO uint32_t DOEPINT10; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT10_b; /*!< BitSize */ - }; - __I uint32_t RESERVED123; - - union { - __IO uint32_t DOEPTSIZ10; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ10_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA10; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED124; - __I uint32_t DOEPDMAB10; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL11; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED125; - - union { - __IO uint32_t DOEPINT11; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT11_b; /*!< BitSize */ - }; - __I uint32_t RESERVED126; - - union { - __IO uint32_t DOEPTSIZ11; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ11_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA11; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED127; - __I uint32_t DOEPDMAB11; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL12; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED128; - - union { - __IO uint32_t DOEPINT12; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT12_b; /*!< BitSize */ - }; - __I uint32_t RESERVED129; - - union { - __IO uint32_t DOEPTSIZ12; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ12_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA12; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED130; - __I uint32_t DOEPDMAB12; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL13; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED131; - - union { - __IO uint32_t DOEPINT13; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT13_b; /*!< BitSize */ - }; - __I uint32_t RESERVED132; - - union { - __IO uint32_t DOEPTSIZ13; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ13_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA13; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED133; - __I uint32_t DOEPDMAB13; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL14; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED134; - - union { - __IO uint32_t DOEPINT14; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT14_b; /*!< BitSize */ - }; - __I uint32_t RESERVED135; - - union { - __IO uint32_t DOEPTSIZ14; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ14_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA14; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED136; - __I uint32_t DOEPDMAB14; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ - - union { - __IO uint32_t DOEPCTL15; /*!< Device OUT Endpoint N Control Register */ - - struct { - __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ - uint32_t : 4; - __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ - __I uint32_t DPID : 1; /*!< Endpoint Data PID */ - __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if - set */ - __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ - __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ - __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. - To control endpoints, response an ACK */ - uint32_t : 4; - __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ - __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ - __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ - __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ - __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint - even before the transfer for that endpoint is complete */ - __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to - receive data is setup */ - } DOEPCTL15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED137; - - union { - __IO uint32_t DOEPINT15; /*!< Device OUT Endpoint-n Interrupt Register */ - - struct { - __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ - __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ - __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ - __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control - endpoint is complete */ - __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ - __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data - phase to the status phase of a Control Write transfer */ - __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back - SETUP packets for this particular endpoint */ - __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ - __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ - __IO uint32_t BNA : 1; /*!< Buffer Not Available */ - uint32_t : 2; - __IO uint32_t BE : 1; /*!< Babble Error */ - __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ - __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ - } DOEPINT15_b; /*!< BitSize */ - }; - __I uint32_t RESERVED138; - - union { - __IO uint32_t DOEPTSIZ15; /*!< Device OUT Endpoint-n Transfer Size Register */ - - struct { - __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ - __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ - __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. - To isochronous OUT endpoints, data PID received in the last - packet */ - } DOEPTSIZ15_b; /*!< BitSize */ - }; - __IO uint32_t DOEPDMA15; /*!< Device OUT Endpoint-n DMA Address Register */ - __I uint32_t RESERVED139; - __I uint32_t DOEPDMAB15; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ -} USB_Type; - - -/* ================================================================================ */ -/* ================ GLOBAL_CTRL ================ */ -/* ================================================================================ */ - - -/** - * @brief GLOBAL_CTRL (GLOBAL_CTRL) - */ - -typedef struct { /*!< GLOBAL_CTRL Structure */ - - union { - __I uint32_t AES_STATUS; /*!< AES status */ - - struct { - __I uint32_t RD_ALMOST_EMPTY: 1; /*!< FIFO read almost empty */ - __I uint32_t RD_EMPTY : 1; /*!< FIFO read empty */ - __I uint32_t WR_FULL_ALMOST: 1; /*!< FIFO write almost full */ - __I uint32_t WR_FULL : 1; /*!< FIFO write full */ - __I uint32_t IDLE : 1; /*!< decryption finish */ - } AES_STATUS_b; /*!< BitSize */ - }; - __I uint32_t RESERVED0[253]; - - union { - __IO uint32_t CLK_SEL_0; /*!< clock select 0 */ - - struct { - __IO uint32_t CAN1_CLK : 2; /*!< CAN1 clock frequency dividor based on system clock, which should - be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t CAN0_CLK : 2; /*!< CAN0 clock frequency dividor based on system clock, which should - be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t I2C1_CLK : 2; /*!< I2C1 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t I2C0_CLK : 2; /*!< I2C0 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t SPI1_CLK : 2; /*!< SPI1 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t SPI0_CLK : 2; /*!< SPI0 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t UART1_CLK : 2; /*!< UART1 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t UART0_CLK : 2; /*!< UART0 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t RTC_CLK : 2; /*!< RTC clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t GPIO_CLK : 2; /*!< GPIO clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t TIMER_CLK : 2; /*!< TIMER clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t WDG_CLK : 2; /*!< watchdog clock frequency dividor based on system clock, which - should be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - uint32_t : 2; - __IO uint32_t FLASH_CLK : 2; /*!< FLASH clock frequency dividor based on system clock, which should - be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - __IO uint32_t DMA_AHB_CLK: 2; /*!< DMA AHB bus clock frequency dividor based on system clock, which - should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - __IO uint32_t USB_AHB_CLK: 2; /*!< USB AHB bus clock frequency dividor based on system clock, which - should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - } CLK_SEL_0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CLK_SEL_1; /*!< clock select 1 */ - - struct { - __IO uint32_t ETH_AHB_CLK: 2; /*!< ETH_AHB clock frequency dividor based on system clock, which - should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - __IO uint32_t DDR_CLK : 2; /*!< DDR clock frequency dividor based on system clock, which should - be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ - uint32_t : 4; - __IO uint32_t ADC_CLK : 2; /*!< ADC clock frequency dividor based on system clock, which should - be 1/8, 1/16, 1/32, external from 0 to 3 */ - __IO uint32_t EFUSE_CLK : 2; /*!< EFUSE clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t SYS_CLK : 4; /*!< system clock clock frequency dividor based on system clock, - which should be oscillator(0), DLL(1), crystal(2), external(3), - JTAG(4), PS(8) */ - __IO uint32_t UART2_CLK : 2; /*!< UART2 clock frequency dividor based on system clock, which should - be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ - __IO uint32_t UTMI_CLK : 1; /*!< UTMI clock came from on-chip usb phy(0) or off-chip usb phy(1) */ - } CLK_SEL_1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t USB_PHY_CTRL; /*!< USB Phy Control Register */ - - struct { - __IO uint32_t BITSTUFF : 1; /*!< 0: No bit stuff */ - __IO uint32_t XTLSEL : 1; /*!< 0: 12MHz */ - __IO uint32_t PLL : 1; /*!< PLL mode */ - __IO uint32_t VOLDET : 1; /*!< Voltage Detector Enable, 0: Disable */ - __IO uint32_t IDUP : 1; /*!< 0: ID is uplled up through 33k Ohm resister */ - __IO uint32_t CKISEL : 1; /*!< Clock selection, 0: Crystal, 1: Internal Clock */ - __IO uint32_t FMOD : 1; /*!< 1: Normal */ - __IO uint32_t SQUELCH : 3; /*!< Squelch Reference Voltage, 000: 27.5mV, 001: 137.5mV, 111: 220mV */ - __IO uint32_t HDISCDT : 3; /*!< Host Disconnect Detection Reference Voltage, 000: 500mV, 100: - 588mV, 111: 654mV */ - __IO uint32_t PRTSEL : 1; /*!< 0: Internal OTG PHY, 1: UTMI to External PHY */ - __IO uint32_t RSTPRT : 1; /*!< 0: The reverse of usb_rst_n will reset, 1: Reset OTG PHY */ - } USB_PHY_CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RTC_INT_EN; /*!< RTC interrupt enable Register */ - - struct { - __IO uint32_t SECOND : 1; /*!< 1s interrupt enable */ - __IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt enable */ - } RTC_INT_EN_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1; - - union { - __IO uint32_t NMI_SEL; /*!< nmi interrupt selection */ - - struct { - __IO uint32_t NMI : 7; /*!< NMI interrupt ID */ - } NMI_SEL_b; /*!< BitSize */ - }; - __I uint32_t RESERVED2; - __IO uint32_t AES_TARGET_ADDR; /*!< AES target address, default is frame decoder address(0x41800000) */ - - union { - __IO uint32_t AES_BURST_TYPE; /*!< AES burst type */ - - struct { - __IO uint32_t TYPE : 2; /*!< burst type, fixed(0), incr(1) */ - } AES_BURST_TYPE_b; /*!< BitSize */ - }; - __I uint32_t RESERVED3[3]; - - union { - __IO uint32_t ICACHE; /*!< ICACHE Enable */ - - struct { - __IO uint32_t EN : 1; /*!< ICACHE Enable */ - } ICACHE_b; /*!< BitSize */ - }; - __IO uint32_t IBUSOFF; /*!< Code Bus Offset */ - __IO uint32_t DBUSOFF; /*!< Data Bus Offset */ - __IO uint32_t EXTADDR; /*!< Bus Ext Addr */ -} GLOBAL_CTRL_Type; - - -/* ================================================================================ */ -/* ================ AES ================ */ -/* ================================================================================ */ - - -/** - * @brief AES (AES) - */ - -typedef struct { /*!< AES Structure */ - __IO uint32_t FIFO; /*!< data FIFO to be decoded */ - - union { - __O uint32_t FIFO_CLEAR; /*!< clear data FIFO */ - - struct { - __O uint32_t CLEAR : 1; /*!< clear after write 1 and write 0 */ - } FIFO_CLEAR_b; /*!< BitSize */ - }; -} AES_Type; - - -/* ================================================================================ */ -/* ================ DDRC ================ */ -/* ================================================================================ */ - - -/** - * @brief DDR_CFG (DDRC) - */ - -typedef struct { /*!< DDRC Structure */ - __IO uint32_t CMD; /*!< DDR commands to program */ - - union { - __IO uint32_t CTRL; /*!< DDR Control */ - - struct { - __IO uint32_t TO : 1; /*!< Take over DDRC siggen */ - __IO uint32_t CLR : 1; /*!< Clear commands in FIFO */ - __O uint32_t STR : 1; /*!< Start to execute the commands in FIFO */ - } CTRL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t MODE; /*!< DDR mode */ - - struct { - __IO uint32_t MODE : 6; /*!< DDRC Mode */ - uint32_t : 2; - __IO uint32_t LANE : 1; /*!< LANE synchronization logic bypass */ - uint32_t : 3; - __IO uint32_t ADEC : 1; /*!< address decoder mapping */ - uint32_t : 3; - __IO uint32_t B16 : 2; /*!< Active 16 bit DQ position when the unmber of DQ IO is 16 */ - uint32_t : 6; - __IO uint32_t CLKPOL : 2; /*!< DQS clkpol set by user on the PHY */ - } MODE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t QUE; /*!< DDRC queue depth */ - - struct { - __IO uint32_t DEPTH : 1; /*!< DDRC queue depth */ - } QUE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t REF; /*!< Refresh control */ - - struct { - __IO uint32_t THRD : 5; /*!< Number of refresh requests which can be postponed */ - uint32_t : 3; - __IO uint32_t TRIG : 4; /*!< Number of refresh requests every dl_refi */ - uint32_t : 4; - __IO uint32_t TIME : 16; /*!< Refresh interval time */ - } REF_b; /*!< BitSize */ - }; - - union { - __O uint32_t REF_TRIG; /*!< Refresh trigger */ - - struct { - __O uint32_t GO : 1; /*!< Write 1 to trigger one refresh request by cbus */ - } REF_TRIG_b; /*!< BitSize */ - }; - - union { - __O uint32_t ZQ_TRIG; /*!< ZQCTL trigger */ - - struct { - __O uint32_t CS : 1; /*!< Write 1 to trigger one ZQCS request by cbus */ - __O uint32_t CL : 1; /*!< Write 1 to trigger one ZQCL request by cbus */ - } ZQ_TRIG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ZQCSR; /*!< ZQCSR */ - - struct { - __IO uint32_t EN : 1; /*!< Enable ZQCS request */ - __IO uint32_t PRI : 1; /*!< 0: DMA access prior to ZQCS, 1: ZQCS prior to DMA access */ - } ZQCSR_b; /*!< BitSize */ - }; - __IO uint32_t ZQCSI; /*!< ZQCS interval time */ - - union { - __IO uint32_t RCD; /*!< t(RCD) */ - - struct { - __IO uint32_t DI : 5; /*!< t(RCD), delay from ACT command to RW command of same bank */ - } RCD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RAS; /*!< t(RAS) */ - - struct { - __IO uint32_t DI : 6; /*!< t(RAS), delay from ACT command to PRE command of same bank */ - } RAS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RP; /*!< t(RP) */ - - struct { - __IO uint32_t DI : 5; /*!< t(RP), delay from PRE command to ACT/REF/ZQ command */ - uint32_t : 3; - __IO uint32_t RPA : 1; /*!< 0: t(RP) delay for PREA command; 1: t(RP)+1 delay for PREA command */ - } RP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RC; /*!< t(RC) */ - - struct { - __IO uint32_t DI : 7; /*!< t(RC), delay from ACT command to ACT command of same bank */ - } RC_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RRD; /*!< t(RRD) */ - - struct { - __IO uint32_t DI : 4; /*!< t(RRD), delay from ACT command to ACT command */ - } RRD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t CCD; /*!< t(CCD) */ - - struct { - __IO uint32_t DI : 3; /*!< t(CCD), delay from RW command to RW command */ - } CCD_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RTW; /*!< t(RTW) */ - - struct { - __IO uint32_t DI : 5; /*!< t(RTW), delay from RD command to WR command */ - } RTW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WTR; /*!< t(WTR) */ - - struct { - __IO uint32_t DI : 5; /*!< t(WTR), delay from WR command to RD command */ - } WTR_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RTP; /*!< t(RTP) */ - - struct { - __IO uint32_t DI : 3; /*!< t(RTP), delay from RD command to PRE command of same bank */ - } RTP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WTP; /*!< t(WTP) */ - - struct { - __IO uint32_t DI : 6; /*!< t(WTP), delay from WR command to PRE command of same bank */ - } WTP_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RFC; /*!< t(RFC) */ - - struct { - __IO uint32_t DI : 8; /*!< t(WTP), delay from WR command to PRE command of same bank */ - } RFC_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ZQCL; /*!< t(ZQoper) */ - - struct { - __IO uint32_t DI : 9; /*!< t(ZQoper), delay from ZQCL command to REF/ZQ/ACT command */ - } ZQCL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ZQCS; /*!< t(ZQCS) */ - - struct { - __IO uint32_t DI : 7; /*!< t(ZQCS), delay from ZQCS command to REF/ZQ/ACT command */ - } ZQCS_b; /*!< BitSize */ - }; - - union { - __IO uint32_t FAW; /*!< t(FAW) */ - - struct { - __IO uint32_t DI : 6; /*!< t(FAW), 4 act command window time */ - } FAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t BURST; /*!< BURST */ - - struct { - __IO uint32_t LEN : 1; /*!< 0: length 8, 1: length 4 */ - } BURST_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PHUNG; /*!< PHUNG */ - - struct { - __IO uint32_t MODE : 1; /*!< 0: normal mode, 1: prevent read hang mode */ - __IO uint32_t LPM : 1; /*!< 1: stop the IO clk */ - } PHUNG_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RL; /*!< READ Latency */ - - struct { - __IO uint32_t VAL : 5; /*!< READ Latency */ - } RL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t WL; /*!< WRITE Latency */ - - struct { - __IO uint32_t VAL : 5; /*!< WRITE Latency */ - } WL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TRAIN; /*!< TRAIN */ - - struct { - __IO uint32_t EN : 4; /*!< Enable lane N training mode */ - } TRAIN_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN0; /*!< Delay cycles of dqsen of byte lane 0 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 0 */ - } DQSEN0_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN1; /*!< Delay cycles of dqsen of byte lane 1 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 1 */ - } DQSEN1_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN2; /*!< Delay cycles of dqsen of byte lane 2 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 2 */ - } DQSEN2_b; /*!< BitSize */ - }; - - union { - __IO uint32_t DQSEN3; /*!< Delay cycles of dqsen of byte lane 0 */ - - struct { - __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 3 */ - } DQSEN3_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ODTH; /*!< Delay from WR command to odt high transition */ - - struct { - __IO uint32_t DL : 5; /*!< Delay from WR command to odt high transition */ - } ODTH_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ODTL; /*!< Delay from WR command to odt low transition */ - - struct { - __IO uint32_t DL : 5; /*!< Delay from WR command to odt low transition */ - } ODTL_b; /*!< BitSize */ - }; - - union { - __O uint32_t ODT; /*!< Used in write leveling mode */ - - struct { - __O uint32_t TRIG : 1; /*!< 0: trigger odt low, 1: trigger odt high */ - } ODT_b; /*!< BitSize */ - }; - - union { - __O uint32_t DQS; /*!< Used in write leveling mode */ - - struct { - __O uint32_t TRIG : 1; /*!< Writing 1 to this register triggers a dqs pulse */ - } DQS_b; /*!< BitSize */ - }; - - union { - __I uint32_t STA; /*!< Commands FIFO */ - - struct { - __I uint32_t MODE : 1; /*!< DDRC in sw_proc mode */ - __I uint32_t EMPTY : 1; /*!< Sw_proc command fifo empty */ - __I uint32_t FULL : 1; /*!< Sw_proc command fifo full */ - } STA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INTCTL; /*!< Interrupt Control */ - - struct { - __IO uint32_t DONE : 1; /*!< 0: the sw_proc_done int will not be masked, 1: the sw_proc_done - int will be masked */ - __IO uint32_t ERR : 1; /*!< mask of the lane_sync_error interrupt */ - uint32_t : 14; - __IO uint32_t MODE : 1; /*!< Interrupt mode: 0: int level active, write 1 to clear; 1: int - edge active */ - } INTCTL_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INTRAW; /*!< Interrupt RAW */ - - struct { - __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done before mask */ - __IO uint32_t ERR : 1; /*!< int reg of the lane sync error before masked */ - } INTRAW_b; /*!< BitSize */ - }; - - union { - __IO uint32_t INTSTA; /*!< Interrupt STA */ - - struct { - __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done after mask */ - __IO uint32_t ERR : 1; /*!< int register of lane sync error after masked */ - } INTSTA_b; /*!< BitSize */ - }; - - union { - __IO uint32_t PHY; /*!< PHY */ - - struct { - __IO uint32_t RST : 1; /*!< FPGA version, reset read dq fifo. Low active */ - } PHY_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RDQ; /*!< FPGA version, read dq delay of byte lane N */ - - struct { - __IO uint32_t L3 : 6; /*!< FPGA version, read dq delay of byte lane3 */ - uint32_t : 2; - __IO uint32_t L2 : 6; /*!< FPGA version, read dq delay of byte lane2 */ - uint32_t : 2; - __IO uint32_t L1 : 6; /*!< FPGA version, read dq delay of byte lane3 */ - uint32_t : 2; - __IO uint32_t L0 : 7; /*!< FPGA version, read dq delay of byte lane0 */ - } RDQ_b; /*!< BitSize */ - }; - - union { - __I uint32_t CALIB; /*!< calibration */ - - struct { - __I uint32_t TPU : 8; /*!< calibration result values, if fail then 0x40 */ - __I uint32_t TPD : 8; /*!< calibration result values, if fail then 0x40 */ - __I uint32_t PDR : 5; /*!< calibration result values, if fail then 0x40 */ - __I uint32_t NDR : 5; /*!< calibration result values, if fail then 0x40 */ - uint32_t : 5; - __IO uint32_t EN : 1; /*!< trigger the calibration processing which is sensitive to the - positive edge */ - } CALIB_b; /*!< BitSize */ - }; - - union { - __IO uint32_t ITMDLY; /*!< "itmdly" is the fine delay trim to the read path "dq", "itmsdly" - is to the read path of "dqs". From 000 to 111 increasingly, - each step is about 40ps */ - - struct { - __IO uint32_t I0 : 4; /*!< itmdly0 */ - __IO uint32_t IS0 : 4; /*!< itmsdly0 */ - __IO uint32_t I1 : 4; /*!< itmdly1 */ - __IO uint32_t IS1 : 4; /*!< itmsdly1 */ - __IO uint32_t I2 : 4; /*!< itmdly2 */ - __IO uint32_t IS2 : 4; /*!< itmsdly2 */ - __IO uint32_t I3 : 4; /*!< itmdly3 */ - __IO uint32_t IS3 : 4; /*!< itmsdly3 */ - } ITMDLY_b; /*!< BitSize */ - }; - - union { - __IO uint32_t TUNE; /*!< CALIB_TUNE */ - - struct { - __IO uint32_t TPU : 4; /*!< tpu_tune, finial val = tune[3] ? val - tune : val + tune */ - __IO uint32_t TPD : 4; /*!< tpd_tune, tune[3:0] for TPD/TPU, [2:0] is the tune val */ - __IO uint32_t PDR : 4; /*!< pdr_tune, inial val = tune[2] ? val - tune : val + tune */ - __IO uint32_t NDR : 4; /*!< ndr_tune, tune[2:0] for NDR/PDR, [1:0] is the tune val */ - } TUNE_b; /*!< BitSize */ - }; - - union { - __IO uint32_t RD_SEL; /*!< RD_WINDOWS_SEL */ - - struct { - __IO uint32_t PHY_SEL : 3; /*!< To fix the phy read valid issue, this is to adjust the read - data valid window to match the phy read valid by cycle level */ - } RD_SEL_b; /*!< BitSize */ - }; -} DDRC_Type; - - -/* ================================================================================ */ -/* ================ PDLOCK ================ */ -/* ================================================================================ */ - - -/** - * @brief PLL DLL LOCK (PDLOCK) - */ - -typedef struct { /*!< PDLOCK Structure */ - - union { - __I uint32_t GCLK; /*!< GCLK */ - - struct { - __I uint32_t C1R2P : 1; /*!< gclk_c1r2_pll_lock */ - __I uint32_t C1R1P : 1; /*!< gclk_c1r1_pll_lock */ - __I uint32_t C2R1P : 1; /*!< gclk_c2r1_pll_lock */ - __I uint32_t C2R2P : 1; /*!< gclk_c2r2_pll_lock */ - __I uint32_t C1R2D : 1; /*!< gclk_c1r2_dll_lock */ - __I uint32_t C1R1D : 1; /*!< gclk_c1r1_dll_lock */ - __I uint32_t C2R1D : 1; /*!< gclk_c2r1_dll_lock */ - __I uint32_t C2R2D : 1; /*!< gclk_c2r2_dll_lock */ - } GCLK_b; /*!< BitSize */ - }; -} PDLOCK_Type; - - -/* ================================================================================ */ -/* ================ PDPROT ================ */ -/* ================================================================================ */ - - -/** - * @brief PLL DLL PROTECT (PDPROT) - */ - -typedef struct { /*!< PDPROT Structure */ - - union { - __O uint32_t LOCK; /*!< LOCK */ - - struct { - __O uint32_t EN : 1; /*!< Enable the PLL DLL Lock to Protect it */ - } LOCK_b; /*!< BitSize */ - }; -} PDPROT_Type; - - -/* ================================================================================ */ -/* ================ CFG_CTRL ================ */ -/* ================================================================================ */ - - -/** - * @brief CFG_CTRL (CFG_CTRL) - */ - -typedef struct { /*!< CFG_CTRL Structure */ - __I uint32_t RESERVED0[3]; - - union { - __IO uint32_t DONE; /*!< DONE CFG */ - - struct { - __IO uint32_t CMD : 1; /*!< Write 1 indicate all chain data write over */ - __IO uint32_t STA : 1; /*!< 1= all chain config process over, chip is in user mode */ - } DONE_b; /*!< BitSize */ - }; - __I uint32_t RESERVED1[34]; - - union { - __IO uint32_t PDLLSTR; /*!< PLL DLL RESET */ - - struct { - __IO uint32_t C1R1P : 1; /*!< C1r1_rstpll_n, low active */ - __IO uint32_t C1R2P : 1; /*!< C1r2_rstpll_n, low active */ - __IO uint32_t C2R1P : 1; /*!< C2r1_rstpll_n, low active */ - __IO uint32_t C2R2P : 1; /*!< C2r2_rstpll_n, low active */ - __IO uint32_t C1R1D : 1; /*!< C1r1_rstdll_n, low active */ - __IO uint32_t C1R2D : 1; /*!< C1r2_rstdll_n, low active */ - __IO uint32_t C2R1D : 1; /*!< C2r1_rstdll_n, low active */ - __IO uint32_t C2R2D : 1; /*!< C2r2_rstdll_n, low active */ - } PDLLSTR_b; /*!< BitSize */ - }; -} CFG_CTRL_Type; - - -/* ================================================================================ */ -/* ================ SOFT_RESET ================ */ -/* ================================================================================ */ - - -/** - * @brief SUB SOFT RESET (SOFT_RESET) - */ - -typedef struct { /*!< SOFT_RESET Structure */ - - union { - __IO uint32_t SOFTRST; /*!< SOFTRST */ - - struct { - __IO uint32_t CAN1_n : 1; /*!< soft_rst_can1_n */ - __IO uint32_t CAN0_n : 1; /*!< soft_rst_can0_n */ - __IO uint32_t I2C1_n : 1; /*!< soft_rst_i2c1_n */ - __IO uint32_t I2C0_n : 1; /*!< soft_rst_i2c0_n */ - __IO uint32_t SPI1_n : 1; /*!< soft_rst_spi1_n */ - __IO uint32_t SPI0_n : 1; /*!< soft_rst_spi0_n */ - __IO uint32_t UART1_n : 1; /*!< soft_rst_uart1_n */ - __IO uint32_t UART0_n : 1; /*!< soft_rst_uart0_n */ - __IO uint32_t RTC_n : 1; /*!< soft_rst_rtc_n */ - __IO uint32_t GPIO_n : 1; /*!< soft_rst_gpio_n */ - __IO uint32_t TIMER_n : 1; /*!< soft_rst_timer_n */ - __IO uint32_t WDT_n : 1; /*!< soft_rst_wdt_n */ - __IO uint32_t LVDS_n : 1; /*!< soft_rst_lvds_n */ - __IO uint32_t FLS_n : 1; /*!< soft_rst_fls_n */ - __IO uint32_t DMAC_AHB_n : 1; /*!< soft_rst_dmac_ahb_n */ - __IO uint32_t USB_AHB_n : 1; /*!< soft_rst_usb_ahb_n */ - __IO uint32_t ETH_AHB_n : 1; /*!< soft_rst_eth_ahb_n */ - __IO uint32_t DDRC_n : 1; /*!< soft_rst_ddrc_n */ - __IO uint32_t ARM_HCLK_n : 1; /*!< soft_rst_arm_HCLK_n */ - __IO uint32_t _48_n : 1; /*!< soft_rst_48_n */ - __IO uint32_t UTM_n : 1; /*!< soft_rst_utmi_n */ - __IO uint32_t CACHE_n : 1; /*!< soft_rst_cache_n */ - __IO uint32_t USB_n : 1; /*!< soft_rst_cache_n */ - __IO uint32_t ETH_RX_n : 1; /*!< soft_rst_eth_rx_i_n */ - __IO uint32_t ETH_TX_n : 1; /*!< soft_rst_eth_tx_i_n */ - __IO uint32_t ADC_n : 1; /*!< soft_rst_adc_n */ - __IO uint32_t EFUSE_n : 1; /*!< soft_rst_efuse_n */ - __IO uint32_t Reserved1_n: 1; /*!< Reserved11 */ - __IO uint32_t AES_n : 1; /*!< soft_rst_aes_n */ - __IO uint32_t UART2_n : 1; /*!< soft_rst_uart2_n */ - __IO uint32_t AS_n : 1; /*!< soft_rst_as_n */ - __IO uint32_t FDCD_n : 1; /*!< soft_rst_fdcd_n */ - } SOFTRST_b; /*!< BitSize */ - }; -} SOFT_RESET_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define UART0_BASE 0x41005000UL -#define UART1_BASE 0x4100C000UL -#define UART2_BASE 0x4100E000UL -#define WDG_BASE 0x41001000UL -#define TIMER0_BASE 0x41000000UL -#define TIMER1_BASE 0x41000020UL -#define TIMER2_BASE 0x41000040UL -#define TIMER3_BASE 0x41000060UL -#define SPI0_BASE 0x41004000UL -#define SPI1_BASE 0x4100B000UL -#define I2C0_BASE 0x41003000UL -#define I2C1_BASE 0x4100A000UL -#define RTC_BASE 0x41007004UL -#define GPIO_BASE 0x41002000UL -#define NOR_FLASH_BASE 0x40800000UL -#define ADC_BASE 0x41006000UL -#define EFUSE_BASE 0x41008000UL -#define CAN0_BASE 0x41009000UL -#define CAN1_BASE 0x4100D000UL -#define DMA_BASE 0x41500000UL -#define ETH_BASE 0x41200000UL -#define USB_BASE 0x41300000UL -#define GLOBAL_CTRL_BASE 0x41007010UL -#define AES_BASE 0x41600000UL -#define DDRC_BASE 0x41400000UL -#define PDLOCK_BASE 0x41007000UL -#define PDPROT_BASE 0x41007C00UL -#define CFG_CTRL_BASE 0x41700000UL -#define SOFT_RESET_BASE 0x41007400UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define UART0 ((UART0_Type *) UART0_BASE) -#define UART1 ((UART0_Type *) UART1_BASE) -#define UART2 ((UART0_Type *) UART2_BASE) -#define WDG ((WDG_Type *) WDG_BASE) -#define TIMER0 ((TIMER0_Type *) TIMER0_BASE) -#define TIMER1 ((TIMER0_Type *) TIMER1_BASE) -#define TIMER2 ((TIMER0_Type *) TIMER2_BASE) -#define TIMER3 ((TIMER0_Type *) TIMER3_BASE) -#define SPI0 ((SPI0_Type *) SPI0_BASE) -#define SPI1 ((SPI0_Type *) SPI1_BASE) -#define I2C0 ((I2C0_Type *) I2C0_BASE) -#define I2C1 ((I2C0_Type *) I2C1_BASE) -#define RTC ((RTC_Type *) RTC_BASE) -#define GPIO ((GPIO_Type *) GPIO_BASE) -#define NOR_FLASH ((NOR_FLASH_Type *) NOR_FLASH_BASE) -#define ADC ((ADC_Type *) ADC_BASE) -#define EFUSE ((EFUSE_Type *) EFUSE_BASE) -#define CAN0 ((CAN0_Type *) CAN0_BASE) -#define CAN1 ((CAN0_Type *) CAN1_BASE) -#define DMA ((DMA_Type *) DMA_BASE) -#define ETH ((ETH_Type *) ETH_BASE) -#define USB ((USB_Type *) USB_BASE) -#define GLOBAL_CTRL ((GLOBAL_CTRL_Type *) GLOBAL_CTRL_BASE) -#define AES ((AES_Type *) AES_BASE) -#define DDRC ((DDRC_Type *) DDRC_BASE) -#define PDLOCK ((PDLOCK_Type *) PDLOCK_BASE) -#define PDPROT ((PDPROT_Type *) PDPROT_BASE) -#define CFG_CTRL ((CFG_CTRL_Type *) CFG_CTRL_BASE) -#define SOFT_RESET ((SOFT_RESET_Type *) SOFT_RESET_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group cmem7 */ -/** @} */ /* End of group (null) */ - -#ifdef __cplusplus -} -#endif - - -#endif /* cmem7_H */ - + +/****************************************************************************************************//** + * @file cmem7.h + * + * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for + * cmem7 from . + * + * @version V1.0 + * @date 5. January 2015 + * + * @note Generated with SVDConv V2.75 + * from CMSIS SVD File 'SVDConv_CME_M7.svd' Version 1.0, + *******************************************************************************************************/ + + + +/** @addtogroup (null) + * @{ + */ + +/** @addtogroup cmem7 + * @{ + */ + +#ifndef CMEM7_H +#define CMEM7_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum { +/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ + PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ + SysTick_IRQn = -1, /*!< 15 System Tick Timer */ +/* ---------------------- cmem7 Specific Interrupt Numbers ---------------------- */ + ETH_INT_IRQn = 0, /*!< 0 ETH_INT */ + USB_INT_IRQn = 1, /*!< 1 USB_INT */ + DMA_INT_IRQn = 2, /*!< 2 DMA_INT */ + CAN0_INT_IRQn = 3, /*!< 3 CAN0_INT */ + CAN1_INT_IRQn = 4, /*!< 4 CAN1_INT */ + FP0_INT_IRQn = 5, /*!< 5 FP0_INT */ + FP1_INT_IRQn = 6, /*!< 6 FP1_INT */ + FP2_INT_IRQn = 7, /*!< 7 FP2_INT */ + FP3_INT_IRQn = 8, /*!< 8 FP3_INT */ + FP4_INT_IRQn = 9, /*!< 9 FP4_INT */ + FP5_INT_IRQn = 10, /*!< 10 FP5_INT */ + FP6_INT_IRQn = 11, /*!< 11 FP6_INT */ + FP7_INT_IRQn = 12, /*!< 12 FP7_INT */ + FP8_INT_IRQn = 13, /*!< 13 FP8_INT */ + FP9_INT_IRQn = 14, /*!< 14 FP9_INT */ + FP10_INT_IRQn = 15, /*!< 15 FP10_INT */ + FP11_INT_IRQn = 16, /*!< 16 FP11_INT */ + FP12_INT_IRQn = 17, /*!< 17 FP12_INT */ + FP13_INT_IRQn = 18, /*!< 18 FP13_INT */ + FP14_INT_IRQn = 19, /*!< 19 FP14_INT */ + FP15_INT_IRQn = 20, /*!< 20 FP15_INT */ + UART0_INT_IRQn = 21, /*!< 21 UART0_INT */ + UART1_INT_IRQn = 22, /*!< 22 UART1_INT */ + ADC_INT_IRQn = 23, /*!< 23 ADC_INT */ + GPIO_INT_IRQn = 24, /*!< 24 GPIO_INT */ + SPI1_INT_IRQn = 25, /*!< 25 SPI1_INT */ + I2C1_INT_IRQn = 26, /*!< 26 I2C1_INT */ + SPI0_INT_IRQn = 27, /*!< 27 SPI0_INT */ + I2C0_INT_IRQn = 28, /*!< 28 I2C0_INT */ + RTC_1S_INT_IRQn = 29, /*!< 29 RTC_1S_INT */ + RTC_1MS_INT_IRQn = 30, /*!< 30 RTC_1MS_INT */ + WDG_INT_IRQn = 31, /*!< 31 WDG_INT */ + TIMER_INT_IRQn = 32, /*!< 32 TIMER_INT */ + DDRC_SW_PROC_IRQn = 33, /*!< 33 DDRC_SW_PROC */ + ETH_PMT_INT_IRQn = 34, /*!< 34 ETH_PMT_INT */ + PAD_INT_IRQn = 35, /*!< 35 PAD_INT */ + DDRC_LANE_SYNC_IRQn = 36, /*!< 36 DDRC_LANE_SYNC */ + UART2_INT_IRQn = 37 /*!< 37 UART2_INT */ +} IRQn_Type; + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */ +#define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 0 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< Cortex-M3 processor and core peripherals */ +#include "system_cmem7.h" /*!< cmem7 System */ + + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + + +/** @addtogroup Device_Peripheral_Registers + * @{ + */ + + +/* ------------------- Start of section using anonymous unions ------------------ */ +#if defined(__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined(__ICCARM__) + #pragma language=extended +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) +/* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning 586 +#else + #warning Not supported compiler type +#endif + + + +/* ================================================================================ */ +/* ================ UART0 ================ */ +/* ================================================================================ */ + + +/** + * @brief asynchronous serial controller 0 (UART0) + */ + +typedef struct { /*!< UART0 Structure */ + __IO uint16_t BAUDRATE; /*!< baudrate Register */ + __I uint16_t RESERVED0; + __IO uint16_t TX_BUF; /*!< transmit buffer Register */ + __I uint16_t RESERVED1; + __I uint16_t RX_BUF; /*!< receive buffer Register */ + __I uint16_t RESERVED2; + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t MODE : 3; /*!< asc mode control */ + __IO uint32_t STOP : 2; /*!< number of stop bits selection */ + __IO uint32_t PARITY : 1; /*!< parity selection */ + __IO uint32_t LOOPBACK : 1; /*!< loopback mode enable bit */ + uint32_t : 1; + __IO uint32_t RX_EN : 1; /*!< receive enable bit */ + uint32_t : 1; + __IO uint32_t FIFO_EN : 1; /*!< FIFO enable bit */ + __IO uint32_t CTS : 1; /*!< Clear to send, enable signal to send */ + __IO uint32_t BAUD_MODE : 1; /*!< baudrate generation mode */ + __IO uint32_t RX_THRESHOLD: 5; /*!< receive threshold */ + __IO uint32_t RX_HALF_FULL: 5; /*!< receive fifi half full level */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< interrupt mask register */ + + struct { + __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ + __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ + __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ + __IO uint32_t PE : 1; /*!< parity error interrupt */ + __IO uint32_t FE : 1; /*!< frame error interrupt */ + __IO uint32_t OE : 1; /*!< overrun error interrupt */ + __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ + } INT_MASK_b; /*!< BitSize */ + }; + + union { + __IO uint32_t STATUS; /*!< status register */ + + struct { + __IO uint32_t RNE : 1; /*!< receiver FIFO not empty */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty */ + __IO uint32_t TOE : 1; /*!< time out when the receiver FIFO is empty */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full */ + __IO uint32_t TF : 1; /*!< transmitter FIFO is full */ + } STATUS_b; /*!< BitSize */ + }; + __IO uint8_t TIMEOUT; /*!< timeout Register */ + __I uint8_t RESERVED3[3]; + + union { + __IO uint32_t TX_RESET; /*!< transmit reset Register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } TX_RESET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RX_RESET; /*!< receive reset Register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } RX_RESET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RUN; /*!< uart enable register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } RUN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< raw interrupt before mask register */ + + struct { + __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ + __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ + __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ + __IO uint32_t PE : 1; /*!< parity error interrupt */ + __IO uint32_t FE : 1; /*!< frame error interrupt */ + __IO uint32_t OE : 1; /*!< overrun error interrupt */ + __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ + } INT_RAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_SEEN; /*!< interrupt after mask register */ + + struct { + __IO uint32_t RNE : 1; /*!< Receive FIFO not empty interrupt */ + __IO uint32_t TE : 1; /*!< Transmitter FIFO empty interrupt */ + __IO uint32_t THE : 1; /*!< Transmitter FIFO at least half empty flag */ + __IO uint32_t TONE : 1; /*!< timeout when the receiver FIFO is not empty interrupt */ + __IO uint32_t TOE : 1; /*!< timeout when the receiver FIFO is empty interrupt */ + __IO uint32_t RHF : 1; /*!< receiver FIFO is half full interrupt */ + __IO uint32_t TF : 1; /*!< transmitter FIFO full interrupt */ + __IO uint32_t PE : 1; /*!< parity error interrupt */ + __IO uint32_t FE : 1; /*!< frame error interrupt */ + __IO uint32_t OE : 1; /*!< overrun error interrupt */ + __IO uint32_t RX_THRE_REACH: 1; /*!< Receive threshold reach interrupt */ + } INT_SEEN_b; /*!< BitSize */ + }; +} UART0_Type; + + +/* ================================================================================ */ +/* ================ WDG ================ */ +/* ================================================================================ */ + + +/** + * @brief watchdog (WDG) + */ + +typedef struct { /*!< WDG Structure */ + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t EN : 1; /*!< flag indicates if watchdog is enabled or not */ + __IO uint32_t INT_LEN : 1; /*!< watchdog report interrupt when COUNTER is 1/4 or 1/2 of LENGTH */ + } CTRL_b; /*!< BitSize */ + }; + __IO uint32_t LEN; /*!< Ticks decrease down to 25% or 50% to trigger an interrupt */ + + union { + __IO uint32_t INT_CTRL; /*!< interrupt control */ + + struct { + __IO uint32_t MASK : 1; /*!< mask register */ + __IO uint32_t TRIGGER_MODE: 1; /*!< trigger mode */ + } INT_CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STA; /*!< interrupt status register */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_STA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw register */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_RAW_b; /*!< BitSize */ + }; + __I uint32_t CNT; /*!< counter register */ +} WDG_Type; + + +/* ================================================================================ */ +/* ================ TIMER0 ================ */ +/* ================================================================================ */ + + +/** + * @brief timer 0 (TIMER0) + */ + +typedef struct { /*!< TIMER0 Structure */ + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t EN : 1; /*!< flag indicates if timer is enabled or not */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TYPE; /*!< type Register */ + + struct { + __IO uint32_t SIGNLE_SHOT: 1; /*!< indicate timer generate only one interrupt if not reload */ + } TYPE_b; /*!< BitSize */ + }; + __IO uint32_t LEN; /*!< length */ + + union { + __IO uint32_t INT_EN; /*!< interrupt enable */ + + struct { + __IO uint32_t EN_REVERSE : 1; /*!< flag indicates if timer is disable or not */ + } INT_EN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STA; /*!< interrupt status */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_STA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw register */ + + struct { + __IO uint32_t STA : 1; /*!< interrupt status */ + } INT_RAW_b; /*!< BitSize */ + }; + __I uint32_t CNT; /*!< counter register */ +} TIMER0_Type; + + +/* ================================================================================ */ +/* ================ SPI0 ================ */ +/* ================================================================================ */ + + +/** + * @brief SPI 0 (SPI0) + */ + +typedef struct { /*!< SPI0 Structure */ + + union { + __I uint32_t STATUS; /*!< status Register */ + + struct { + __I uint32_t RFIFO_EMPTY: 1; /*!< receive fifo is empty */ + __I uint32_t RFIFO_FULL : 1; /*!< receive fifo is full */ + __I uint32_t RFIFO_ALMOST_EMPTY: 1; /*!< receive fifo is almost empty */ + __I uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full */ + __I uint32_t TFIFO_EMPTY: 1; /*!< transmit fifo is empty */ + __I uint32_t TFIFO_FULL : 1; /*!< transmit fifo is full */ + __I uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo is almost empty */ + __I uint32_t TFIFO_ALMOST_FULL: 1; /*!< transmit fifo almost full */ + __I uint32_t BUSY : 1; /*!< indecates if SPI is idle or busy */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t EN : 1; /*!< indicates if SPI is enabled or not */ + __IO uint32_t RX_EN : 1; /*!< indicates if SPI receiver is enabled or not */ + __IO uint32_t CLK_HIGH : 1; /*!< indicats if idle clock polarity is high level */ + __IO uint32_t NEG_EDGE : 1; /*!< 1, indicates SPI takes sample at the rise edge and transmit + data at the trailing edge. 0, conversely. */ + __IO uint32_t TX_BIT_SEQUENCE: 1; /*!< transmit bit sequence. 0 : MSB is sent first */ + __IO uint32_t RX_BIT_SEQUENCE: 1; /*!< receive bit sequence. 0: MSB is received first */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< interrupt mask Register */ + + struct { + __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ + __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ + __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ + __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ + __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ + __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ + __IO uint32_t DONE : 1; /*!< transmit done interrupt */ + } INT_MASK_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STATUS; /*!< interrupt Register */ + + struct { + __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ + __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ + __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ + __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ + __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ + __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ + __IO uint32_t DONE : 1; /*!< transmit done interrupt */ + } INT_STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw Register */ + + struct { + __IO uint32_t RFIFO_UNDERFLOW: 1; /*!< receive fifo underflow interrupt */ + __IO uint32_t RFIFO_OVERFLOW: 1; /*!< receive fifo overflow interrupt */ + __IO uint32_t RFIFO_ALMOST_FULL: 1; /*!< receive fifo almost full interrupt */ + __IO uint32_t TFIFO_UNDERFLOW: 1; /*!< transmit fifo underflow interrupt */ + __IO uint32_t TFIFO_OVERFLOW: 1; /*!< transmit fifo overflow interrupt */ + __IO uint32_t TFIFO_ALMOST_EMPTY: 1; /*!< transmit fifo almost empty interrupt */ + __IO uint32_t DONE : 1; /*!< transmit done interrupt */ + } INT_RAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t BCNT; /*!< bit length while transmitting and receiving */ + + struct { + __IO uint32_t CNT : 5; /*!< bit length while transmitting and receiving, BCNT + 1 */ + } BCNT_b; /*!< BitSize */ + }; + __IO uint8_t GAP; /*!< half cycle number between continuous data frame */ + __I uint8_t RESERVED0[3]; + __IO uint16_t DIV; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ + __I uint16_t RESERVED1; + __IO uint32_t TRANS_CNT; /*!< transmit data length, data number = TRANS_CNT + 1 */ + + union { + __O uint32_t TRANS_START; /*!< transmit startup register, write 1 to trigger transmision once */ + + struct { + __O uint32_t TX_TRIGGER : 1; /*!< write 1 to trigger transmision once */ + } TRANS_START_b; /*!< BitSize */ + }; + __IO uint32_t RW_DATA; /*!< raw data register */ +} SPI0_Type; + + +/* ================================================================================ */ +/* ================ I2C0 ================ */ +/* ================================================================================ */ + + +/** + * @brief I2C 0 (I2C0) + */ + +typedef struct { /*!< I2C0 Structure */ + + union { + __IO uint32_t CTRL; /*!< control Register */ + + struct { + __IO uint32_t MODE : 1; /*!< master or slave mode */ + __IO uint32_t MASTER_ADDR_WIDTH: 1; /*!< 7- or 10-bits address as a master */ + __IO uint32_t SLAVE_ADDR_WIDTH: 1; /*!< 7- or 10-bits address width as a slave */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint16_t TAR; /*!< target address Register */ + + struct { + __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ + __IO uint16_t START_BYTE : 1; /*!< Enable start Byte for each transfer */ + } TAR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED0; + + union { + __IO uint16_t SAR; /*!< slave address Register */ + + struct { + __IO uint16_t ADDR10 : 10; /*!< 7- or 10-bits address */ + } SAR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED1; + + union { + __IO uint32_t DATA_CMD; /*!< I2C transfer data/command entry */ + + struct { + __IO uint32_t DATA : 8; /*!< 8-bits data */ + __O uint32_t RD_CMD : 1; /*!< read command for master mode only, write 0 if slave mode */ + __O uint32_t WR_CMD : 1; /*!< write command for master mode only */ + __O uint32_t WR_RD_CMD : 1; /*!< write and read command for master mode only */ + } DATA_CMD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WRITE_READ_CNT; /*!< I2C write and read data byte counter Register */ + + struct { + __IO uint32_t RD_BYTE_CNT: 9; /*!< Decide the number of bytes read back as a master-receiver */ + uint32_t : 7; + __IO uint32_t WR_BYTE_CNT: 9; /*!< Decide the number of byte to send as a master-transmitter */ + } WRITE_READ_CNT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SCL_CNT; /*!< I2C clk pulse counter */ + + struct { + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< the SCL clock high-period count */ + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< the SCL clock low-period count */ + } SCL_CNT_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + + union { + __I uint32_t INT_STATUS; /*!< I2C interrupt sources */ + + struct { + __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ + __I uint32_t RX_OVER : 1; /*!< receiver overflow */ + __I uint32_t RX_FULL : 1; /*!< receiver is full */ + __I uint32_t TX_OVER : 1; /*!< transmit overflow */ + __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ + __I uint32_t RD_REQ : 1; /*!< read request */ + __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ + __I uint32_t RX_DONE : 1; /*!< receive done */ + __I uint32_t TX_DONE : 1; /*!< transmit done */ + __I uint32_t WR_REQ : 1; /*!< write request */ + } INT_STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< I2C interrupt mask register */ + + struct { + __I uint32_t RX_UNDER : 1; /*!< receiver underflow */ + __I uint32_t RX_OVER : 1; /*!< receiver overflow */ + __I uint32_t RX_FULL : 1; /*!< receiver is full */ + __I uint32_t TX_OVER : 1; /*!< transmit overflow */ + __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ + __I uint32_t RD_REQ : 1; /*!< read request */ + __I uint32_t TX_ABRT : 1; /*!< transmit abortion */ + __I uint32_t RX_DONE : 1; /*!< receive done */ + __I uint32_t TX_DONE : 1; /*!< transmit done */ + __I uint32_t WR_REQ : 1; /*!< write request */ + } INT_MASK_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3; + + union { + __IO uint32_t RX_TL; /*!< I2C receive FIFO threshold */ + + struct { + __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ + } RX_TL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TX_TL; /*!< I2C transmit FIFO threshold */ + + struct { + __IO uint32_t THRESHOLD : 5; /*!< FIFO threashold */ + } TX_TL_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_ALL_INT; /*!< I2C clear all interrupt register */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear all individual interrupts */ + } CLR_ALL_INT_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RX_UNDER; /*!< I2C clear RX_UNDER interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_UNDER interrupt (bit 19) + of the I2C_STATUS register */ + } CLR_RX_UNDER_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RX_OVER; /*!< I2C clear RX_OVER interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_OVER interrupt (bit 20) of + the I2C_STATUS register */ + } CLR_RX_OVER_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_TX_OVER; /*!< I2C clear TX_OVER interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_OVER interrupt (bit 22) of + the I2C_STATUS register */ + } CLR_TX_OVER_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RD_REQ; /*!< I2C clear RD_REQ interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RD_REQ interrupt (bit 24) of + the I2C_STATUS register */ + } CLR_RD_REQ_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_TX_ABRT; /*!< I2C clear TX_ABRT interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_ABRT interrupts (bit 25 , + bit 18, bit 17, bit 16 and bit 15) of the I2C_STATUS register. */ + } CLR_TX_ABRT_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_RX_DONE; /*!< I2C clear RX_DONE interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the RX_DONE interrupt (bit 26) of + the I2C_STATUS register */ + } CLR_RX_DONE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ENABLE; /*!< I2C enable register */ + + struct { + __IO uint32_t EN : 1; /*!< enable device */ + uint32_t : 30; + __IO uint32_t RESET : 1; /*!< TX and RX FIFO are held in an erased state( flushed) and all + interrupts deserted */ + } ENABLE_b; /*!< BitSize */ + }; + + union { + __I uint32_t STATUS; /*!< I2C status register */ + + struct { + __I uint32_t BUSY : 1; /*!< I2C busy Status */ + __I uint32_t TX_FIFO_NOT_FULL: 1; /*!< transmit FIFO is not full */ + __I uint32_t TX_FIFO_EMPTY: 1; /*!< transmit FIFO is empty */ + __I uint32_t RX_FIFO_NOT_EMPTY: 1; /*!< receive FIFO is not empty */ + __I uint32_t RX_FIFO_FULL: 1; /*!< receive FIFO is full */ + __I uint32_t EN : 1; /*!< I2C is enabled */ + __I uint32_t TX_BYTE_W_ACK: 9; /*!< Number of bytes sent to slave with acknowledge during the last + write transaction as a master-transmitter only */ + __I uint32_t ABRT_ADDR_NOACK: 1; /*!< the address sent was not acknowledged by any slave as a master */ + __I uint32_t ABRT_TX_DATA_NOACK: 1; /*!< the data sent was not acknowledged by any slave as a master */ + __I uint32_t ABRT_SLAVE_FLUSH_TX_FIFO: 1; /*!< Slave has received a read command and some data exists in the + TX FIFO so the slave issues a TX_ABRT interrupt to flush old + data in TX FIFO */ + __I uint32_t ABRT_SLAVE_RD_IN_TX: 1; /*!< When the processor side responds to a slave mode request for + data to be transmitted to a remote master and user writes a + 1 in CMD (bit 8) of I2C_DATA_CMD register */ + __I uint32_t RX_UNDER : 1; /*!< receiver is underflow */ + __I uint32_t RX_OVER : 1; /*!< receiver is overflow */ + __I uint32_t RX_FULL : 1; /*!< receiver is full */ + __I uint32_t TX_OVER : 1; /*!< transmit is overflow */ + __I uint32_t TX_EMPTY : 1; /*!< transmit is empty */ + __I uint32_t RD_REQ : 1; /*!< read request is received */ + __I uint32_t TX_ABRT : 1; /*!< transmit is abort */ + __I uint32_t RX_DONE : 1; /*!< receive is done */ + __I uint32_t TX_DONE : 1; /*!< transmit is done */ + __I uint32_t WR_REQ : 1; /*!< write request is received */ + __I uint32_t MST_RD_FLAG: 1; /*!< Master is executing read command */ + __I uint32_t MST_WR_FLAG: 1; /*!< Master is executing read command */ + __I uint32_t MST_WR_RD_FLAG: 1; /*!< Master is executing write-read command */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __I uint32_t TX_FIFO_LEVEL; /*!< I2C transmit FIFO level */ + + struct { + __I uint32_t LEVEL : 5; /*!< FIFO level */ + } TX_FIFO_LEVEL_b; /*!< BitSize */ + }; + + union { + __I uint32_t RX_FIFO_LEVEL; /*!< I2C receive FIFO level */ + + struct { + __I uint32_t LEVEL : 5; /*!< FIFO level */ + } RX_FIFO_LEVEL_b; /*!< BitSize */ + }; + __I uint32_t RESERVED4; + + union { + __O uint32_t SLAVE_NACK; /*!< I2C slave send a data NACK */ + + struct { + __O uint32_t NACK : 1; /*!< data NACK */ + } SLAVE_NACK_b; /*!< BitSize */ + }; + __I uint32_t RESERVED5; + + union { + __IO uint32_t SDA_SETUP; /*!< I2C SDA setup timer */ + + struct { + __IO uint32_t TSETUP : 10; /*!< This counter defines the max value of the following constrains:THD:STA + TSU:STO,TSETUP: T / INPUT_CLK_PERIOD */ + __IO uint32_t TSU_DAT : 8; /*!< This counter defines the constrain of TSU:DAT: 250ns (or 100ns) + / INPUT_CLK_PERIOD */ + } SDA_SETUP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TSU_STA_SETUP; /*!< I2C Tsu_sta and Tbuf_free timer */ + + struct { + __IO uint32_t TBUF : 10; /*!< This counter defines the constrain of bus free interval: Tbuf, + Tbuf : Tbus_free / INPUT_CLK_PERIOD */ + __IO uint32_t TSU_STA : 10; /*!< This counter defines the constrain of Tsu:sta, Tsu:sta : Tsu:sta + / INPUT_CLK_PERIOD */ + __IO uint32_t SDA_FILTER_CNT: 4; /*!< SDA filter count */ + __IO uint32_t SDA_FILTER_EN: 1; /*!< SDA filter enable bit */ + __IO uint32_t SCL_FILTER_CNT: 4; /*!< SCL filter count */ + __IO uint32_t SCL_FILTER_EN: 1; /*!< SCL filter enable bit */ + } TSU_STA_SETUP_b; /*!< BitSize */ + }; + + union { + __I uint32_t CLR_TX_DONE; /*!< I2C clear TX_DONE interrupt */ + + struct { + __I uint32_t CLEAR : 1; /*!< Read this register to clear the TX_DONE interrupt (bit 27) of + the I2C_STATUS register */ + } CLR_TX_DONE_b; /*!< BitSize */ + }; +} I2C0_Type; + + +/* ================================================================================ */ +/* ================ RTC ================ */ +/* ================================================================================ */ + + +/** + * @brief RTC (RTC) + */ + +typedef struct { /*!< RTC Structure */ + + union { + __IO uint32_t INT_STATUS; /*!< interrupt Register */ + + struct { + __IO uint32_t SECOND : 1; /*!< 1s interrupt, write 1 clear 0 */ + __IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt, write 1 clear 0 */ + } INT_STATUS_b; /*!< BitSize */ + }; + __IO uint32_t SECOND; /*!< current seconds of system time */ + + union { + __IO uint16_t MILLSECOND; /*!< current millseconds of system time */ + + struct { + __IO uint16_t MS : 10; /*!< micro seconds */ + } MILLSECOND_b; /*!< BitSize */ + }; +} RTC_Type; + + +/* ================================================================================ */ +/* ================ GPIO ================ */ +/* ================================================================================ */ + + +/** + * @brief GPIO (GPIO) + */ + +typedef struct { /*!< GPIO Structure */ + __I uint32_t GPIO_IN; /*!< GPIO input data */ + __IO uint32_t GPIO_OUT_UNMASK; /*!< GPIO output mask Register */ + __IO uint32_t GPIO_OUT_DATA; /*!< GPIO output data register */ + __IO uint32_t GPIO_OE; /*!< GPIO output driver enable */ + __IO uint32_t GPIO_INT_MASK; /*!< GPIO input interrupt mask */ + __IO uint32_t GPIO_INT_STATUS; /*!< GPIO input interrupt status */ + __IO uint32_t GPIO_INT_RAW; /*!< GPIO input interrupt raw */ + __IO uint32_t GPIO_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ + + union { + __IO uint32_t PWM_OUT_SEL; /*!< Select gpio output from PWM */ + + struct { + __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ + __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ + __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ + __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ + } PWM_OUT_SEL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT0_LEN; /*!< Pwm channel 0 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT0_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT1_LEN; /*!< Pwm channel 1 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT1_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT2_LEN; /*!< Pwm channel 2 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT2_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT3_LEN; /*!< Pwm channel 3 paramters */ + + struct { + __IO uint32_t LOW_LEVEL_TICK: 16; /*!< low level width = ticks + 1 */ + __IO uint32_t HIGH_LEVEL_TICK: 16; /*!< high level width = ticks + 1 */ + } PWM_OUT3_LEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PWM_OUT_EN; /*!< Pwm enable */ + + struct { + __IO uint32_t GPIO_31 : 1; /*!< GPIO[31] is selected to output PWM */ + __IO uint32_t GPIO_H_9 : 1; /*!< GPIO_H[9] is selected to output PWM */ + __IO uint32_t GPIO_H_19 : 1; /*!< GPIO_H[19] is selected to output PWM */ + __IO uint32_t GPIO_H_20 : 1; /*!< GPIO_H[20] is selected to output PWM */ + } PWM_OUT_EN_b; /*!< BitSize */ + }; + __I uint32_t GPIO_H_IN; /*!< GPIO_H input data */ + __IO uint32_t GPIO_H_OUT_UNMASK; /*!< GPIO_H output unmask Register */ + __IO uint32_t GPIO_H_OUT_DATA; /*!< GPIO_H output data register */ + __IO uint32_t GPIO_H_OE; /*!< GPIO_H output driver enable */ + __IO uint32_t GPIO_H_INT_MASK; /*!< GPIO_H interrupt mask */ + __IO uint32_t GPIO_H_INT_STATUS; /*!< GPIO_H interrupt status */ + __IO uint32_t GPIO_H_INT_RAW; /*!< GPIO_H interrupt raw */ + __IO uint32_t GPIO_H_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ + __I uint32_t GPIO_N_IN; /*!< GPIO_N input data */ + __IO uint32_t GPIO_N_OUT_UNMASK; /*!< GPIO_N output unmask Register */ + __IO uint32_t GPIO_N_OUT_DATA; /*!< GPIO_N output data register */ + __IO uint32_t GPIO_N_OE; /*!< GPIO_N output driver enable */ + __IO uint32_t GPIO_N_INT_MASK; /*!< GPIO_N interrupt mask */ + __IO uint32_t GPIO_N_INT_STATUS; /*!< GPIO_N interrupt status */ + __IO uint32_t GPIO_N_INT_RAW; /*!< GPIO_N interrupt raw */ + __IO uint32_t GPIO_N_POSITIVE_EDGE_INT_TRIGGER; /*!< triggers an interrupt while a positive edge, else negitive edge */ +} GPIO_Type; + + +/* ================================================================================ */ +/* ================ NOR_FLASH ================ */ +/* ================================================================================ */ + + +/** + * @brief NOR_FLASH (NOR_FLASH) + */ + +typedef struct { /*!< NOR_FLASH Structure */ + + union { + __IO uint32_t CTRL0; /*!< control Register 0 */ + + struct { + __IO uint32_t DIV : 8; /*!< frequency division register, fsck = fclk_io / (DIV + 1) / 2 */ + __IO uint32_t CS_REVALID_INTERVAL: 8; /*!< interval from CS invalid to valid, number of half cycle of SCK */ + __IO uint32_t RW_BYTE_CNT: 16; /*!< RW byte count (eliminate CMD, ADDRESS, DUMMY in normal state, + contains all in transparent state. 0 is unlimited */ + } CTRL0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTRL1; /*!< control Register 1 */ + + struct { + __IO uint32_t CMD : 8; /*!< operated command */ + __IO uint32_t ADDRESS : 24; /*!< RW address */ + } CTRL1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TRIGGER; /*!< trigger register */ + + struct { + __O uint32_t OP_START : 1; /*!< operation start. */ + __IO uint32_t OP_CLEAN : 1; /*!< operation clean, stop current opration and clean FIFO */ + __IO uint32_t TRSP_RD_EN : 1; /*!< if a read operation after transparent operation */ + __IO uint32_t TRSP_EN : 1; /*!< enable transparent operation */ + } TRIGGER_b; /*!< BitSize */ + }; + + union { + __I uint32_t STATUS; /*!< status register */ + + struct { + __I uint32_t BUSY : 1; /*!< reading or writting */ + __I uint32_t RD_FIFO_ALMOST_FULL: 1; /*!< read FIFO is almost full */ + __I uint32_t RD_FIFO_EMPTY: 1; /*!< read FIFO is empty */ + __I uint32_t RD_FIFO_FULL: 1; /*!< read FIFO is full */ + __I uint32_t WR_FIFO_ALMOST_EMPTY: 1; /*!< write FIFO is almost empty */ + __I uint32_t WR_FIFO_FULL: 1; /*!< write FIFO is full */ + __I uint32_t WR_FIFO_EMPTY: 1; /*!< write FIFO is empty */ + } STATUS_b; /*!< BitSize */ + }; + __IO uint32_t DATA; /*!< data register. lower bits are significant in read and higher + bits are significant in writting */ + + union { + __IO uint32_t BYPASS; /*!< bypass Register, is used for JTAG connecting FLASH directly */ + + struct { + __IO uint32_t EN : 1; /*!< enable bypass */ + } BYPASS_b; /*!< BitSize */ + }; +} NOR_FLASH_Type; + + +/* ================================================================================ */ +/* ================ ADC ================ */ +/* ================================================================================ */ + + +/** + * @brief ADC (ADC) + */ + +typedef struct { /*!< ADC Structure */ + + union { + __IO uint32_t POWERDOWN_RESET; /*!< power down and reset Register */ + + struct { + __IO uint32_t RESET_ADC2 : 1; /*!< ADC2, reset, active high */ + __IO uint32_t RESET_ADC1 : 1; /*!< ADC1, reset, active high */ + __IO uint32_t POWERDOWN_ADC2: 1; /*!< ADC2, power down, active high */ + __IO uint32_t POWERDOWN_ADC1: 1; /*!< ADC1, power down, active high */ + } POWERDOWN_RESET_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG0; /*!< config Register */ + + struct { + __IO uint32_t VSEN : 3; /*!< ADC-1 VSEN Selection */ + __IO uint32_t PHASE_CTRL : 2; /*!< ADC-1 and ADC-2 CLK Phase Control */ + } CFG0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_ADC1; /*!< config ADC1 register */ + + struct { + __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ + __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ + __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ + __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ + } CFG_ADC1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_ADC2; /*!< config ADC1 register */ + + struct { + __IO uint32_t SYSTEM_MODE: 3; /*!< system mode selection */ + __IO uint32_t CHANNEL_SEL: 4; /*!< channel selection */ + __IO uint32_t MULTI_CHANNEL_CONTINUE_SCAN: 1;/*!< If continue to scan multiply channel, else single scan */ + __IO uint32_t MULTI_CHANNEL_BIT: 8; /*!< each bit represents each channel */ + } CFG_ADC2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ADC1_FIFO_CLEAR; /*!< clear adc1 fifo data */ + + struct { + __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ + } ADC1_FIFO_CLEAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ADC2_FIFO_CLEAR; /*!< clear adc2 fifo data */ + + struct { + __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ + } ADC2_FIFO_CLEAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ALL_ADC_FIFO_CLEAR; /*!< clear adc1 and adc2 fifo data */ + + struct { + __IO uint32_t CLEAR : 1; /*!< clear fifo data, active high */ + } ALL_ADC_FIFO_CLEAR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_MASK; /*!< interrupt mask register */ + + struct { + __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ + __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ + __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ + __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ + __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ + __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ + } INT_MASK_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_RAW; /*!< interrupt raw register */ + + struct { + __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ + __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ + __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ + __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ + __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ + __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ + } INT_RAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_STATUS; /*!< interrupt status register */ + + struct { + __IO uint32_t ADC1_ALMOST_FULL: 1; /*!< ADC 1 almost full */ + __IO uint32_t ADC1_OVERFLOW: 1; /*!< ADC 1 is overflow */ + __IO uint32_t ADC1_EMPTY_ERR: 1; /*!< ADC 1 read empty error */ + __IO uint32_t ADC2_ALMOST_FULL: 1; /*!< ADC 2 almost full */ + __IO uint32_t ADC2_OVERFLOW: 1; /*!< ADC 2 is overflow */ + __IO uint32_t ADC2_EMPTY_ERR: 1; /*!< ADC 2 read empty error */ + } INT_STATUS_b; /*!< BitSize */ + }; + __I uint32_t ADC1_OUT; /*!< ADC-1 Output data (Signed-Magnitude Format) */ + __I uint32_t ADC2_OUT; /*!< ADC-2 Output data (Signed-Magnitude Format) */ + __I uint32_t ADC1_OUT_OFFSET_CALIBRATION; /*!< ADC-1 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ + __I uint32_t ADC2_OUT_OFFSET_CALIBRATION; /*!< ADC-2 Output in offset calibration when Input=0, Ideally DAO[11:0]=000h */ + __I uint32_t ADC1_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-1 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ + __I uint32_t ADC2_OUT_NEGTIVE_GAIN_CALIBRATION; /*!< ADC-2 Output in gain calibration when Input=-FS, Ideally DAO[11:0]=801h */ + __I uint32_t ADC1_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-1 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ + __I uint32_t ADC2_OUT_POSITIVE_GAIN_CALIBRATION;/*!< ADC-2 Output in gain calibration when Input=FS, Ideally DAO[11:0]=7FFh */ + + union { + __I uint32_t EOC; /*!< Conversion End Indicator */ + + struct { + __I uint32_t ADC2_EOC_GAIN: 1; /*!< ADC2 EOC_GAIN signal, conversion is done */ + __I uint32_t ADC2_EOC_OFF: 1; /*!< ADC2 EOC_OFF signal, conversion is done */ + __I uint32_t ADC2_EOC : 1; /*!< ADC2 EOC signal, conversion is done */ + __I uint32_t ADC1_EOC_GAIN: 1; /*!< ADC1 EOC_GAIN signal, conversion is done */ + __I uint32_t ADC1_EOC_OFF: 1; /*!< ADC1 EOC_OFF signal, conversion is done */ + __I uint32_t ADC1_EOC : 1; /*!< ADC1 EOC signal, conversion is done */ + } EOC_b; /*!< BitSize */ + }; + + union { + __I uint32_t BUSY; /*!< ADC is busy */ + + struct { + __I uint32_t ADC1_BUSY : 1; /*!< ADC1 is busy */ + __I uint32_t ADC2_BUSY : 1; /*!< ADC2 is busy */ + } BUSY_b; /*!< BitSize */ + }; + + union { + __O uint32_t ADC1_START; /*!< ADC1 startup enable */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC1_START_b; /*!< BitSize */ + }; + + union { + __O uint32_t ADC1_STOP; /*!< ADC1 stop enable */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC1_STOP_b; /*!< BitSize */ + }; + + union { + __O uint16_t ADC1_FIFO_READ; /*!< ADC1 FIFO read data */ + + struct { + __O uint16_t DATA : 12; /*!< data */ + __O uint16_t CHANNEL : 4; /*!< channel number */ + } ADC1_FIFO_READ_b; /*!< BitSize */ + }; + __I uint16_t RESERVED0; + + union { + __O uint32_t ADC2_START; /*!< ADC2 startup enable, only for single-conversion */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC2_START_b; /*!< BitSize */ + }; + + union { + __O uint32_t ADC2_STOP; /*!< ADC1 stop enable, only for single-conversion */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ADC2_STOP_b; /*!< BitSize */ + }; + + union { + __O uint16_t ADC2_FIFO_READ; /*!< ADC2 FIFO read data */ + + struct { + __O uint16_t DATA : 12; /*!< data */ + __O uint16_t CHANNEL : 4; /*!< channel number */ + } ADC2_FIFO_READ_b; /*!< BitSize */ + }; + __I uint16_t RESERVED1; + + union { + __O uint32_t ALL_ADC_START; /*!< all ADCs start */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ALL_ADC_START_b; /*!< BitSize */ + }; + + union { + __O uint32_t ALL_ADC_STOP; /*!< all ADCs stop */ + + struct { + __O uint32_t EN : 1; /*!< start */ + } ALL_ADC_STOP_b; /*!< BitSize */ + }; + + union { + __I uint32_t ALL_ADC_FIFO_READ; /*!< all ADCs FIFO read data */ + + struct { + __I uint32_t ADC1_DATA : 12; /*!< ADC1 data */ + __I uint32_t ADC1_CHANNEL: 4; /*!< ADC1 channel number */ + __I uint32_t ADC2_DATA : 12; /*!< ADC2 data */ + __I uint32_t ADC2_CHANNEL: 4; /*!< ADC2 channel number */ + } ALL_ADC_FIFO_READ_b; /*!< BitSize */ + }; + + union { + __I uint32_t STATUS; /*!< status register */ + + struct { + __I uint32_t ADC1_READ_EMPTY: 1; /*!< ADC1 read empty */ + __I uint32_t ADC2_READ_EMPTY: 1; /*!< ADC2 read empty */ + __I uint32_t ADC1_READ_ALMOST_EMPTY: 1; /*!< ADC1 read almost empty */ + __I uint32_t ADC2_READ_ALMOST_EMPTY: 1; /*!< ADC2 read almost empty */ + __I uint32_t ADC1_WRITE_FULL: 1; /*!< ADC1 write full */ + __I uint32_t ADC2_WRITE_FULL: 1; /*!< ADC2 write full */ + __I uint32_t ADC1_WRITE_ALMOST_FULL: 1; /*!< ADC1 write almost full */ + __I uint32_t ADC2_WRITE_ALMOST_FULL: 1; /*!< ADC2 write almost full */ + } STATUS_b; /*!< BitSize */ + }; +} ADC_Type; + + +/* ================================================================================ */ +/* ================ EFUSE ================ */ +/* ================================================================================ */ + + +/** + * @brief EFUSE (EFUSE) + */ + +typedef struct { /*!< EFUSE Structure */ + + union { + __IO uint32_t USER_CTRL_LOW; /*!< low user region control */ + + struct { + __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ + __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ + __I uint32_t BUSY : 1; /*!< reading or writting */ + __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ + __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ + __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ + __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ + __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ + } USER_CTRL_LOW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TIMING_0; /*!< timing 0 */ + + struct { + __IO uint32_t TPRS : 7; /*!< TPRS */ + __IO uint32_t TESR : 2; /*!< TESR */ + __IO uint32_t TRC : 4; /*!< TRC */ + __IO uint32_t TRPW : 3; /*!< TRPW */ + __IO uint32_t TRAH : 2; /*!< TRAH */ + __IO uint32_t TRAC : 3; /*!< TRAC */ + uint32_t : 6; + __IO uint32_t TPWPH : 5; /*!< TPWPH[6:2] */ + } TIMING_0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TIMING_1; /*!< timing 1 */ + + struct { + __IO uint32_t TPWPS : 7; /*!< TPWPS */ + __IO uint32_t TEPS : 4; /*!< TEPS */ + __IO uint32_t TPP : 11; /*!< TPP */ + __IO uint32_t TPIT : 8; /*!< TPIT */ + __IO uint32_t TPWPH : 2; /*!< TPWPS[1:0] */ + } TIMING_1_b; /*!< BitSize */ + }; + __IO uint32_t USER_DATA0_LOW; /*!< user data [31:0] */ + __IO uint32_t USER_DATA1_LOW; /*!< user data [63:32] */ + __IO uint32_t USER_DATA2_LOW; /*!< user data [95:64] */ + __IO uint32_t USER_DATA3_LOW; /*!< user data [127:96] */ + + union { + __IO uint32_t USER_DATA4_LOW; /*!< crc and lock bit */ + + struct { + __IO uint32_t LOCK : 1; /*!< write protection if true */ + uint32_t : 23; + __IO uint32_t CRC : 8; /*!< CRC */ + } USER_DATA4_LOW_b; /*!< BitSize */ + }; + __I uint32_t RESERVED0[3]; + + union { + __IO uint32_t USER_CTRL_HI; /*!< high user region control */ + + struct { + __IO uint32_t WR_EN : 1; /*!< write enable. 1 : write data into EFUSE. clear 0 after read */ + __IO uint32_t RD_EN : 1; /*!< read enable. 1 : write data into EFUSE. clear 0 after read */ + __I uint32_t BUSY : 1; /*!< reading or writting */ + __IO uint32_t COMPARE_FAIL: 1; /*!< data read isn't consist with EFUSE */ + __I uint32_t RD_CRC_ERR : 1; /*!< CRC error in reading */ + __I uint32_t WR_CRC_ERR : 1; /*!< CRC error in writting */ + __I uint32_t LOCK : 1; /*!< user region in EFUSE is locked, EFUSE can't be burn */ + __IO uint32_t TMRF : 2; /*!< Reference resistor select, 1200ohm is recommended */ + } USER_CTRL_HI_b; /*!< BitSize */ + }; + __IO uint32_t USER_DATA0_HI; /*!< user data [159:128] */ + __IO uint32_t USER_DATA1_HI; /*!< user data [191:160] */ + __IO uint32_t USER_DATA2_HI; /*!< user data [223:192] */ + __IO uint32_t USER_DATA3_HI; /*!< user data [255:224] */ + + union { + __IO uint32_t USER_DATA4_HI; /*!< crc and lock bit */ + + struct { + __IO uint32_t LOCK : 1; /*!< write protection if true */ + uint32_t : 23; + __IO uint32_t CRC : 8; /*!< CRC */ + } USER_DATA4_HI_b; /*!< BitSize */ + }; +} EFUSE_Type; + + +/* ================================================================================ */ +/* ================ CAN0 ================ */ +/* ================================================================================ */ + + +/** + * @brief CAN 0 (CAN0) + */ + +typedef struct { /*!< CAN0 Structure */ + + union { + __IO uint8_t MODE; /*!< mode Register */ + + struct { + __IO uint8_t RM : 1; /*!< reset mode if 1 or operation mode */ + __IO uint8_t LOM : 1; /*!< Listen only mode */ + __IO uint8_t STM : 1; /*!< self test mode */ + __IO uint8_t AFM : 1; /*!< acceptance filter mode. Single filter if 1, dual filter if 0 */ + __IO uint8_t SM : 1; /*!< sleep mode */ + } MODE_b; /*!< BitSize */ + }; + __I uint8_t RESERVED0[3]; + + union { + __O uint8_t CMD; /*!< command Register */ + + struct { + __O uint8_t TR : 1; /*!< Set to 1 when a message is to be transmitted */ + __O uint8_t AT : 1; /*!< Set to 1 to cancel the next transmission request */ + __O uint8_t RRB : 1; /*!< Set to 1 to release the Receive Buffer */ + __O uint8_t CDO : 1; /*!< Set to 1 to clear the data overrun condition signaled by the + Data Overrun Status bit (SR.1). */ + __O uint8_t SSR : 1; /*!< Set to 1 when a message is to be transmitted and received simultaneously */ + } CMD_b; /*!< BitSize */ + }; + __I uint8_t RESERVED1[3]; + + union { + __I uint8_t STATUS; /*!< status Register */ + + struct { + __I uint8_t RBNE : 1; /*!< Receive Buffer not empty */ + __I uint8_t DO : 1; /*!< Data Overrun Status */ + __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ + __I uint8_t TC : 1; /*!< Transmission complete */ + __I uint8_t RXING : 1; /*!< receiving the data */ + __I uint8_t TXING : 1; /*!< transmitting the data */ + __I uint8_t ERR : 1; /*!< At least one of the error counters is more than Error Warning + Limit Register */ + __I uint8_t BUS_OFF : 1; /*!< in 'Bus Off' state */ + } STATUS_b; /*!< BitSize */ + }; + __I uint8_t RESERVED2[3]; + + union { + __I uint8_t INT; /*!< interrupt Register */ + + struct { + __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ + __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ + __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status + or Error Status bits (SR.7,SR.6) */ + __I uint8_t DO : 1; /*!< Data Overrun Status */ + __I uint8_t WAKEUP : 1; /*!< wake-up */ + __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being + in error passive state or when at least one error counter exceeds + the protocol-defined level of 127 */ + __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ + __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ + } INT_b; /*!< BitSize */ + }; + __I uint8_t RESERVED3[3]; + + union { + __IO uint8_t INT_EN; /*!< interrupt enabled Register */ + + struct { + __I uint8_t RBNF : 1; /*!< Receive Buffer not empty */ + __I uint8_t TB_UNLOCK : 1; /*!< Transmit Buffer is unlocked and not in transmitting */ + __I uint8_t ERR : 1; /*!< Set on every change (set or clear) of either the Bus Status + or Error Status bits (SR.7,SR.6) */ + __I uint8_t DO : 1; /*!< Data Overrun Status */ + __I uint8_t WAKEUP : 1; /*!< wake-up */ + __I uint8_t EP : 1; /*!< Set when the MCAN2 re-enters error active state after being + in error passive state or when at least one error counter exceeds + the protocol-defined level of 127 */ + __I uint8_t AL : 1; /*!< Set when the MCAN2 loses arbitration and becomes a receiver */ + __I uint8_t BUS_ERR : 1; /*!< Set when the MCAN2 detects an error on the CAN-bus */ + } INT_EN_b; /*!< BitSize */ + }; + __I uint8_t RESERVED4[7]; + + union { + __IO uint8_t BTR0; /*!< Bus Timing 0 */ + + struct { + __IO uint8_t BRP : 6; /*!< TQ =2 x Txtal1 x (32 x BRP.5 + 16 x BRP.4 + 8 x BRP.3 + 4 x + BRP.2 + 2 x BRP.1 + BRP.0 + 1) */ + __IO uint8_t SJW : 2; /*!< the maximum number of time quanta of sync segment */ + } BTR0_b; /*!< BitSize */ + }; + __I uint8_t RESERVED5[3]; + + union { + __IO uint8_t BTR1; /*!< Bus Timing 1 */ + + struct { + __IO uint8_t TSEG1 : 4; /*!< the maximum number of time quanta of propagation and 1st phase + segment */ + __IO uint8_t TSEG2 : 3; /*!< the maximum number of time quanta of 2nd phase segment */ + __IO uint8_t SAM : 1; /*!< sample times. Sample 3 times if 1, once if 0 */ + } BTR1_b; /*!< BitSize */ + }; + __I uint8_t RESERVED6[3]; + + union { + __IO uint8_t OCR; /*!< Output Control Register */ + + struct { + __IO uint8_t MODE : 2; /*!< output control mode */ + } OCR_b; /*!< BitSize */ + }; + __I uint8_t RESERVED7[11]; + + union { + __I uint8_t ALC; /*!< Arbitration Lost Capture */ + + struct { + __I uint8_t BIT : 5; /*!< the current position of the Bit Processor when bus arbitration + lost, 1st bit (ID.28) if 0 */ + } ALC_b; /*!< BitSize */ + }; + __I uint8_t RESERVED8[3]; + + union { + __I uint8_t ECC; /*!< Error Code Capture */ + + struct { + __I uint8_t SEGMENT : 5; /*!< segment code */ + __I uint8_t DIRECTION : 1; /*!< If 1, the error occurred during reception. If 0, the error occurred + during transmission */ + __I uint8_t ERR : 2; /*!< error code */ + } ECC_b; /*!< BitSize */ + }; + __I uint8_t RESERVED9[3]; + __IO uint8_t EWLR; /*!< Error Warning Limit */ + __I uint8_t RESERVED10[3]; + __IO uint8_t RXERR; /*!< Receive Error Counter */ + __I uint8_t RESERVED11[3]; + __IO uint8_t TXERR; /*!< Transmit Error Counter */ + __I uint8_t RESERVED12[3]; + + union { + __IO uint8_t FI_OR_ACR0; /*!< Transmit Frame Information if writting or Receive Frame Information + if reading, ACR[0] if reset mode */ + + struct { + __IO uint8_t DLC : 4; /*!< byte number in the data */ + uint8_t : 2; + __IO uint8_t RTR : 1; /*!< 1 indicates a remote frame; 0 indicates a data frame */ + __IO uint8_t FF : 1; /*!< 1 selects Extended Frame Format (EFF); 0 selects Standard Frame + Format (SFF) */ + } FI_OR_ACR0_b; /*!< BitSize */ + }; + __I uint8_t RESERVED13[3]; + __IO uint8_t DI0_OR_ACR1; /*!< Transmit data Information if writting or Receive data Information + if reading, ACR[1] if reset mode */ + __I uint8_t RESERVED14[3]; + __IO uint8_t DI1_OR_ACR2; /*!< Transmit data Information if writting or Receive data Information + if reading, ACR[2] if reset mode */ + __I uint8_t RESERVED15[3]; + __IO uint8_t DI2_OR_ACR3; /*!< Transmit data Information if writting or Receive data Information + if reading, ACR[3] if reset mode */ + __I uint8_t RESERVED16[3]; + __IO uint8_t DI3_OR_AMR0; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[0] if reset mode */ + __I uint8_t RESERVED17[3]; + __IO uint8_t DI4_OR_AMR1; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[1] if reset mode */ + __I uint8_t RESERVED18[3]; + __IO uint8_t DI5_OR_AMR2; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[2] if reset mode */ + __I uint8_t RESERVED19[3]; + __IO uint8_t DI6_OR_AMR3; /*!< Transmit data Information if writting or Receive data Information + if reading, AMR[3] if reset mode */ + __I uint8_t RESERVED20[3]; + __IO uint8_t DI7; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED21[3]; + __IO uint8_t DI8; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED22[3]; + __IO uint8_t DI9; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED23[3]; + __IO uint8_t DI10; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED24[3]; + __IO uint8_t DI11; /*!< Transmit data Information if writting or Receive data Information + if reading */ + __I uint8_t RESERVED25[3]; + __IO uint8_t RMC; /*!< Receive Message Counter */ + __I uint8_t RESERVED26[7]; + + union { + __IO uint8_t CDR; /*!< Clock Divider Register */ + + struct { + __IO uint8_t DIVIDER : 3; /*!< divider of XTAL1 */ + __IO uint8_t OFF : 1; /*!< disable XTAL1 */ + } CDR_b; /*!< BitSize */ + }; +} CAN0_Type; + + +/* ================================================================================ */ +/* ================ DMA ================ */ +/* ================================================================================ */ + + +/** + * @brief DMA (DMA) + */ + +typedef struct { /*!< DMA Structure */ + __IO uint32_t SAR0; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED0; + __IO uint32_t DAR0; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED1; + + union { + __IO uint32_t LLP0; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + + union { + __IO uint32_t CTL_LOW0; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI0; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI0_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT0; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED3; + __IO uint32_t DSTAT0; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED4; + __IO uint32_t SSTATAR0; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED5; + __IO uint32_t DSTATAR0; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED6; + + union { + __IO uint32_t CFG_LOW0; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI0; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR0; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED7; + + union { + __IO uint32_t DSR0; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED8; + __IO uint32_t SAR1; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED9; + __IO uint32_t DAR1; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED10; + + union { + __IO uint32_t LLP1; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED11; + + union { + __IO uint32_t CTL_LOW1; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI1; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI1_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT1; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED12; + __IO uint32_t DSTAT1; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED13; + __IO uint32_t SSTATAR1; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED14; + __IO uint32_t DSTATAR1; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED15; + + union { + __IO uint32_t CFG_LOW1; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI1; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR1; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED16; + + union { + __IO uint32_t DSR1; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED17; + __IO uint32_t SAR2; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED18; + __IO uint32_t DAR2; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED19; + + union { + __IO uint32_t LLP2; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED20; + + union { + __IO uint32_t CTL_LOW2; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI2; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI2_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT2; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED21; + __IO uint32_t DSTAT2; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED22; + __IO uint32_t SSTATAR2; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED23; + __IO uint32_t DSTATAR2; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED24; + + union { + __IO uint32_t CFG_LOW2; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI2; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR2; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED25; + + union { + __IO uint32_t DSR2; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED26; + __IO uint32_t SAR3; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED27; + __IO uint32_t DAR3; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED28; + + union { + __IO uint32_t LLP3; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED29; + + union { + __IO uint32_t CTL_LOW3; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI3; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI3_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT3; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED30; + __IO uint32_t DSTAT3; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED31; + __IO uint32_t SSTATAR3; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED32; + __IO uint32_t DSTATAR3; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED33; + + union { + __IO uint32_t CFG_LOW3; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI3; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR3; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED34; + + union { + __IO uint32_t DSR3; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED35; + __IO uint32_t SAR4; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED36; + __IO uint32_t DAR4; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED37; + + union { + __IO uint32_t LLP4; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED38; + + union { + __IO uint32_t CTL_LOW4; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI4; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI4_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT4; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED39; + __IO uint32_t DSTAT4; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED40; + __IO uint32_t SSTATAR4; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED41; + __IO uint32_t DSTATAR4; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED42; + + union { + __IO uint32_t CFG_LOW4; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI4; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR4; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED43; + + union { + __IO uint32_t DSR4; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED44; + __IO uint32_t SAR5; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED45; + __IO uint32_t DAR5; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED46; + + union { + __IO uint32_t LLP5; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED47; + + union { + __IO uint32_t CTL_LOW5; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI5; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI5_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT5; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED48; + __IO uint32_t DSTAT5; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED49; + __IO uint32_t SSTATAR5; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED50; + __IO uint32_t DSTATAR5; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED51; + + union { + __IO uint32_t CFG_LOW5; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI5; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR5; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED52; + + union { + __IO uint32_t DSR5; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED53; + __IO uint32_t SAR6; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED54; + __IO uint32_t DAR6; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED55; + + union { + __IO uint32_t LLP6; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED56; + + union { + __IO uint32_t CTL_LOW6; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI6; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI6_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT6; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED57; + __IO uint32_t DSTAT6; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED58; + __IO uint32_t SSTATAR6; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED59; + __IO uint32_t DSTATAR6; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED60; + + union { + __IO uint32_t CFG_LOW6; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI6; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR6; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED61; + + union { + __IO uint32_t DSR6; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED62; + __IO uint32_t SAR7; /*!< Current Source Address of DMA transfer */ + __I uint32_t RESERVED63; + __IO uint32_t DAR7; /*!< Current Destination Address of DMA transfer */ + __I uint32_t RESERVED64; + + union { + __IO uint32_t LLP7; /*!< Linked List Pointer Register for Channel */ + + struct { + __IO uint32_t LMS : 2; /*!< Identifies the AHB layer/interface where the memory device that + stores the next linked list item resides. */ + __IO uint32_t LOC : 30; /*!< Starting Address In Memory of next LLI if block chaining is + enabled */ + } LLP7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED65; + + union { + __IO uint32_t CTL_LOW7; /*!< Lower 32-bits Control Register for Channel */ + + struct { + __IO uint32_t INT_EN : 1; /*!< Interrupt Enable Bit */ + __IO uint32_t DST_TR_WIDTH: 3; /*!< Destination Transfer Width */ + __IO uint32_t SRC_TR_WIDTH: 3; /*!< Source Transfer Width */ + __IO uint32_t DINC : 2; /*!< Destination Address Increment */ + __IO uint32_t SINC : 2; /*!< Source Address Increment */ + __IO uint32_t DEST_MSIZE : 3; /*!< Destination Burst Transaction Length */ + __IO uint32_t SRC_MSIZE : 3; /*!< Source Burst Transaction Length */ + __IO uint32_t SRC_GATHER_EN: 1; /*!< Source gather enable bit */ + __IO uint32_t DST_SCATTER_EN: 1; /*!< Destination scatter enable bit */ + uint32_t : 1; + __IO uint32_t TT_FC : 3; /*!< Transfer Type and Flow Control */ + __IO uint32_t DMS : 2; /*!< Destination Master Select */ + __IO uint32_t SMS : 2; /*!< Source Master Select */ + __IO uint32_t LLP_DST_EN : 1; /*!< Block chaining is enabled on the destination side */ + __IO uint32_t LLP_SRC_EN : 1; /*!< Block chaining is enabled on the source side */ + } CTL_LOW7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CTL_HI7; /*!< Higher 32-bits Control Register for Channel */ + + struct { + __IO uint32_t BLOCK_TS : 12; /*!< indicates the total number of single transactions to perform + for every block transfer */ + __IO uint32_t DONE : 1; /*!< a block transfer is complete */ + } CTL_HI7_b; /*!< BitSize */ + }; + __IO uint32_t SSTAT7; /*!< Source Status Register for Channel */ + __I uint32_t RESERVED66; + __IO uint32_t DSTAT7; /*!< Destination Status Register for Channel */ + __I uint32_t RESERVED67; + __IO uint32_t SSTATAR7; /*!< Source Status Address Register for Channel */ + __I uint32_t RESERVED68; + __IO uint32_t DSTATAR7; /*!< Destination Status Address Register for Channel */ + __I uint32_t RESERVED69; + + union { + __IO uint32_t CFG_LOW7; /*!< Lower 32-bit Configuration Register for Channel */ + + struct { + uint32_t : 5; + __IO uint32_t CH_PRIOR : 3; /*!< Channel priority. A priority of 7 is the highest priority */ + __IO uint32_t CH_SUSP : 1; /*!< Suspends all DMA data transfers from the source until this bit + is cleared. */ + __I uint32_t FIFO_EMPTY : 1; /*!< Indicates if there is data left in the channel FIFO */ + __IO uint32_t HS_SEL_DST : 1; /*!< If Destination Software handshaking interface */ + __IO uint32_t HS_SEL_SRC : 1; /*!< If Source Software handshaking interface */ + __IO uint32_t LOCK_CH_L : 2; /*!< Indicates the duration over which CFGx.LOCK_CH bit applies. */ + __IO uint32_t LOCK_B_L : 2; /*!< Indicates the duration over which CFGx.LOCK_B bit applies. */ + __IO uint32_t LOCK_CH : 1; /*!< Channel Lock Bit */ + __IO uint32_t LOCK_B : 1; /*!< Bus Lock Bit */ + __IO uint32_t DST_HS_POL : 1; /*!< Destination Handshaking Interface Polarity. 0: active high */ + __IO uint32_t SRC_HS_POL : 1; /*!< Source Handshaking Interface Polarity. 0: active high */ + __IO uint32_t MAX_ABRST : 10; /*!< Maximum AMBA Burst Length */ + __IO uint32_t RELOAD_SRC : 1; /*!< Automatic Source Reload */ + __IO uint32_t RELOAD_DST : 1; /*!< Automatic Destination Reload */ + } CFG_LOW7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CFG_HI7; /*!< Higher 32-bit Configuration Register for Channel */ + + struct { + __IO uint32_t FCMODE : 1; /*!< if source transaction requests aren't serviced when the Destination + Peripheral is the flow controller. */ + __IO uint32_t FIFO_MODE : 1; /*!< Determines space or data needs to be available in the FIFO before + a burst transaction request is serviced. */ + __IO uint32_t PROTCTL : 3; /*!< There is a one-to-one mapping of these register bits to the + HPROT[3:1] master interface signals */ + __IO uint32_t DS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + __IO uint32_t SS_UPD_EN : 1; /*!< STATx is only updated from STATARx */ + } CFG_HI7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t SGR7; /*!< Source Gather Register for Channel */ + + struct { + __IO uint32_t SGI : 20; /*!< Source gather interval */ + __IO uint32_t SGC : 12; /*!< Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH */ + } SGR7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED70; + + union { + __IO uint32_t DSR7; /*!< Destination Scatter Register for Channel */ + + struct { + __IO uint32_t DSI : 20; /*!< Destination scatter interval */ + __IO uint32_t DSC : 12; /*!< Specifies the number of contiguous destination transfers of + CTLx.DST_TR_WIDTH */ + } DSR7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED71[11]; + __I uint8_t INT_TFR; /*!< DMA Transfer Complete */ + __I uint8_t RESERVED72[7]; + __I uint8_t INT_BLOCK; /*!< Block Transfer Complete */ + __I uint8_t RESERVED73[7]; + __I uint8_t INT_SRC_TRAN; /*!< Source Transaction Complete */ + __I uint8_t RESERVED74[7]; + __I uint8_t INT_DST_TRAN; /*!< Destination Transaction Complete */ + __I uint8_t RESERVED75[7]; + __I uint8_t INT_ERR; /*!< Error */ + __I uint8_t RESERVED76[7]; + + union { + __IO uint16_t INT_EN_TFR; /*!< DMA Transfer Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_TFR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED77[3]; + + union { + __IO uint16_t INT_EN_BLOCK; /*!< Block Transfer Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_BLOCK_b; /*!< BitSize */ + }; + __I uint16_t RESERVED78[3]; + + union { + __IO uint16_t INT_EN_SRC_TRAN; /*!< Source Transaction Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_SRC_TRAN_b; /*!< BitSize */ + }; + __I uint16_t RESERVED79[3]; + + union { + __IO uint16_t INT_EN_DST_TRAN; /*!< Destination Transaction Complete */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_DST_TRAN_b; /*!< BitSize */ + }; + __I uint16_t RESERVED80[3]; + + union { + __IO uint16_t INT_EN_ERR; /*!< Error */ + + struct { + __IO uint16_t EN : 8; /*!< interrupt enable */ + __IO uint16_t WE : 8; /*!< interrupt enable write enable */ + } INT_EN_ERR_b; /*!< BitSize */ + }; + __I uint16_t RESERVED81[3]; + __O uint8_t INT_CLEAR_TFR; /*!< DMA Transfer Complete */ + __I uint8_t RESERVED82[7]; + __O uint8_t INT_CLEAR_BLOCK; /*!< Block Transfer Complete */ + __I uint8_t RESERVED83[7]; + __O uint8_t INT_CLEAR_SRC_TRAN; /*!< Source Transaction Complete */ + __I uint8_t RESERVED84[7]; + __O uint8_t INT_CLEAR_DST_TRAN; /*!< Destination Transaction Complete */ + __I uint8_t RESERVED85[7]; + __O uint8_t INT_CLEAR_ERR; /*!< Error */ + __I uint8_t RESERVED86[63]; + + union { + __IO uint32_t DMA_EN; /*!< DW_ahb_dmac Configuration Register */ + + struct { + __IO uint32_t EN : 1; /*!< enable */ + } DMA_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED87; + + union { + __IO uint32_t CH_EN; /*!< DW_ahb_dmac Channel Enable Register */ + + struct { + __IO uint32_t EN : 8; /*!< enable */ + __IO uint32_t WE : 8; /*!< enable write enable */ + } CH_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED88[10]; + + union { + __I uint32_t DMA_COMP_PARAMS_6_HI; /*!< Component Parameters for channel 7 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_6_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_5_LOW; /*!< Component Parameters for channel 6 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_5_LOW_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_5_HI; /*!< Component Parameters for channel 5 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_5_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_4_LOW; /*!< Component Parameters for channel 4 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_4_LOW_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_4_HI; /*!< Component Parameters for channel 3 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_4_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_3_LOW; /*!< Component Parameters for channel 2 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_3_LOW_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_3_HI; /*!< Component Parameters for channel 1 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_3_HI_b; /*!< BitSize */ + }; + + union { + __I uint32_t DMA_COMP_PARAMS_2_LOW; /*!< Component Parameters for channel 0 */ + + struct { + __I uint32_t DTW : 3; /*!< If this is not hardcoded, then software can program the destination + transfer width. */ + __I uint32_t STW : 3; /*!< If this is not hardcoded, then software can program the source + transfer width. */ + __I uint32_t STAT_DST : 1; /*!< If destination status load feature is on */ + __I uint32_t STAT_SRC : 1; /*!< If source status load feature is on */ + __I uint32_t DST_SCA_EN : 1; /*!< If destination scatter feature is on */ + __I uint32_t SRC_GAT_EN : 1; /*!< If source gather feature is on */ + __I uint32_t LOCK_EN : 1; /*!< If channel lock feature is on */ + __I uint32_t MULTI_BLK_EN: 1; /*!< If multi blocks transfer feature is on */ + __I uint32_t CTL_WB_EN : 1; /*!< If write back initial values to relative registers feature is + on */ + __I uint32_t HC_LLP : 1; /*!< If disable LLP feature is on */ + uint32_t : 2; + __I uint32_t MAX_MULT_SIZE: 3; /*!< Maximum value of burst transaction size (SRC_MSIZE and DEST_MSIZE). */ + __I uint32_t DMS : 3; /*!< Destination AHB dma interface */ + __I uint32_t LMS : 3; /*!< Linked list AHB dma interface */ + __I uint32_t SMS : 3; /*!< source AHB dma interface */ + __I uint32_t FIFO_DEPTH : 3; /*!< FIFO depth in bytes */ + } DMA_COMP_PARAMS_2_LOW_b; /*!< BitSize */ + }; + __I uint32_t RESERVED89; + + union { + __I uint32_t DMA_COMP_PARAMS_1_LOW; /*!< Maximum block size for channel */ + + struct { + __I uint32_t CH0_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 0. */ + __I uint32_t CH1_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 1 */ + __I uint32_t CH2_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 2 */ + __I uint32_t CH3_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 3 */ + __I uint32_t CH4_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 4 */ + __I uint32_t CH5_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 5 */ + __I uint32_t CH6_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 6 */ + __I uint32_t CH7_MAX_BLK_SIZE: 4; /*!< Maximum block size for channel 7 */ + } DMA_COMP_PARAMS_1_LOW_b; /*!< BitSize */ + }; +} DMA_Type; + + +/* ================================================================================ */ +/* ================ ETH ================ */ +/* ================================================================================ */ + + +/** + * @brief ETH (ETH) + */ + +typedef struct { /*!< ETH Structure */ + + union { + __IO uint32_t CONFIG; /*!< MAC Configuration Register */ + + struct { + __IO uint32_t PRELEN : 2; /*!< Preamble Length for Transmit frames */ + __IO uint32_t RX_EN : 1; /*!< Receiver Enable */ + __IO uint32_t TX_EN : 1; /*!< Transmitter Enable */ + __IO uint32_t DC_EN : 1; /*!< Deferral Check Enable */ + uint32_t : 2; + __IO uint32_t ACS : 1; /*!< Automatic Pad or CRC Stripping */ + __IO uint32_t LUD : 1; /*!< Link Up or Down */ + uint32_t : 1; + __IO uint32_t IPC : 1; /*!< Checksum Offload */ + __IO uint32_t DM : 1; /*!< Duplex Mode */ + __IO uint32_t LM : 1; /*!< Loopback Mode */ + uint32_t : 1; + __IO uint32_t FES : 1; /*!< Speed in XMII interface */ + __IO uint32_t PS : 1; /*!< the Ethernet line speed */ + uint32_t : 4; + __IO uint32_t JE : 1; /*!< Jumbo enable */ + uint32_t : 1; + __IO uint32_t JD : 1; /*!< if 0, the MAC cuts off the transmitter if more than 2,048 bytes + of data (10,240 if JE is set high) */ + __IO uint32_t WD : 1; /*!< Watchdog Disable */ + __IO uint32_t TC : 1; /*!< If 1, this bit enables the transmission of duplex mode, link + speed, and link up or down information to the PHY */ + __IO uint32_t CST : 1; /*!< CRC Stripping for Type Frames */ + uint32_t : 1; + __IO uint32_t TWOKPE : 1; /*!< If 0, 1518 bytes is considered as a giant frame, 1 is 2000 bytes. */ + __IO uint32_t SARC : 3; /*!< Source Address Insertion or Replacement Control */ + } CONFIG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t FF; /*!< MAC Frame Filter */ + + struct { + __IO uint32_t PR : 1; /*!< Receive all frames in spite of source and destination address */ + __IO uint32_t HUC : 1; /*!< if 1, don't compare DA field in destination address filtering + of unicast frames with DA register */ + __IO uint32_t HMC : 1; /*!< if 1, don't compare DA field in destination address filtering + of multicast frames with DA register */ + __IO uint32_t DAIF : 1; /*!< if set, the Address Check block operates in inverse filtering + mode for the DA address comparison */ + __IO uint32_t PM : 1; /*!< Pass All Multicast */ + __IO uint32_t DBF : 1; /*!< Disable Broadcast Frames */ + __IO uint32_t PCF : 2; /*!< Pass Control Frames */ + __IO uint32_t SAIF : 1; /*!< If set, the frames whose SA matches the SA registers are marked + as failing the SA Address filter */ + __IO uint32_t SAF : 1; /*!< Source Address Filter Enable */ + __IO uint32_t HPF : 1; /*!< Hash or Perfect Filter */ + uint32_t : 5; + __IO uint32_t VTFE : 1; /*!< VLAN Tag Filter Enable */ + uint32_t : 3; + __IO uint32_t IPFE : 1; /*!< Layer 3 and Layer 4 Filter Enable */ + __IO uint32_t DNTU : 1; /*!< Drop non-TCP/UDP over IP Frames */ + uint32_t : 9; + __IO uint32_t RA : 1; /*!< Receive all */ + } FF_b; /*!< BitSize */ + }; + __IO uint32_t HTH; /*!< Hash Table High Register */ + __IO uint32_t HTL; /*!< Hash Table Low Register */ + + union { + __IO uint32_t GMII_ADDR; /*!< GMII Address Register */ + + struct { + __IO uint32_t BUSY : 1; /*!< GMII Busy */ + __IO uint32_t GW : 1; /*!< GMII write or read */ + __IO uint32_t CR : 4; /*!< CSR Clock Range */ + __IO uint32_t GR : 5; /*!< These bits select the desired GMII register in the selected + PHY device */ + __IO uint32_t PA : 5; /*!< This field indicates which of the 32 possible PHY devices are + being accessed */ + } GMII_ADDR_b; /*!< BitSize */ + }; + __IO uint32_t GMII_DATA; /*!< GMII Data Register */ + + union { + __IO uint32_t FC; /*!< Flow Control Register */ + + struct { + __IO uint32_t FCB : 1; /*!< This bit initiates a Pause frame in the full-duplex mode */ + __IO uint32_t TFE : 1; /*!< MAC enables the flow control operation to transmit Pause frames */ + __IO uint32_t RFE : 1; /*!< MAC enables the flow control operation to receive Pause frames */ + __IO uint32_t UP : 1; /*!< MAC can detect Pause frames with unicast address of the station */ + } FC_b; /*!< BitSize */ + }; + + union { + __IO uint32_t VLAN_TAG; /*!< VLAN Tag Register */ + + struct { + __IO uint32_t VL : 16; /*!< VLAN Tag Identifier for Receive Frames */ + __IO uint32_t ETV : 1; /*!< Enable 12-Bit VLAN Tag Comparison */ + __IO uint32_t VTIM : 1; /*!< If set, The frames that do not have matching VLAN Tag are marked + as matched */ + __IO uint32_t ESVL : 1; /*!< If set, consider the S-VLAN (Type = 0x88A8) frames as valid + VLAN tagged frames */ + __IO uint32_t VTHM : 1; /*!< When set, the most significant four bits of the VLAN tag's CRC + are used to index the content */ + } VLAN_TAG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED0[2]; + __IO uint32_t RWUFFR; /*!< Remote Wake-Up Frame Filter Register */ + + union { + __IO uint32_t PMTCSR; /*!< PMT Control and Status Register */ + + struct { + __IO uint32_t PWRDWN : 1; /*!< Power Down */ + __IO uint32_t MGKPKTEN : 1; /*!< Magic Packet Enable */ + __IO uint32_t RWKPKTEN : 1; /*!< Remote Wake-Up Frame Enable */ + uint32_t : 2; + __IO uint32_t MGKPRCVD : 1; /*!< the power management event is generated because of the reception + of a magic packet */ + __IO uint32_t RWKPRCVD : 1; /*!< When set, this bit indicates the power management event is generated + because of the reception of a remote wake-up frame */ + uint32_t : 2; + __IO uint32_t GLBLUCAST : 1; /*!< When set, enables any unicast packet filtered by the MAC (DAF)address + recognition to be a remote wake-up frame. */ + uint32_t : 14; + __IO uint32_t RWKPTR : 3; /*!< Remote Wake-up FIFO Pointer */ + uint32_t : 4; + __IO uint32_t RWKFILTRST : 1; /*!< Remote Wake-Up Frame Filter Register Pointer Reset. */ + } PMTCSR_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[2]; + __IO uint32_t MACISR; /*!< Interrupt Status Register */ + __IO uint32_t MACIMR; /*!< Interrupt Mask Register */ + __IO uint16_t ADDR0_HIGH; /*!< MAC Address0 High Register */ + __I uint16_t RESERVED2; + __IO uint32_t ADDR0_LOW; /*!< MAC Address0 LOW Register */ + + union { + __IO uint32_t ADDR1_HIGH; /*!< MAC Address0 High Register */ + + struct { + __IO uint32_t ADDR : 16; /*!< MAC Address1 [47:32] */ + uint32_t : 14; + __IO uint32_t SA : 1; /*!< MAC address1 is source or destination address compared with + received frame */ + __IO uint32_t AE : 1; /*!< the address filter module uses the MAC address1 for filtering */ + } ADDR1_HIGH_b; /*!< BitSize */ + }; + __IO uint32_t ADDR1_LOW; /*!< MAC Address1 LOW Register */ + __I uint32_t RESERVED3[44]; + + union { + __IO uint32_t MMCCR; /*!< MMC Control Register */ + + struct { + __IO uint32_t CNTRST : 1; /*!< Counters Reset */ + __IO uint32_t CNTSTOPRO : 1; /*!< Counter Stop Rollover */ + __IO uint32_t RSTONRD : 1; /*!< Reset on Read */ + __IO uint32_t CNTFREEZ : 1; /*!< MMC Counter Freeze */ + __IO uint32_t CNTPRST : 1; /*!< Counters Preset */ + __IO uint32_t CNTPRSTLVL : 1; /*!< Counters Preset */ + uint32_t : 2; + __IO uint32_t UCDBC : 1; /*!< Update MMC Counters for Dropped Broadcast Frames */ + } MMCCR_b; /*!< BitSize */ + }; + __IO uint32_t MMCRIR; /*!< MMC Receive Interrupt Register */ + __IO uint32_t MMCTIR; /*!< MMC Transmit Interrupt Register */ + __IO uint32_t MMCRIMR; /*!< MMC Receive interrupt mask */ + __IO uint32_t MMCTIMR; /*!< MMC Transmit Interrupt Mask */ + __I uint32_t RESERVED4[59]; + __IO uint32_t MMCIRCOIM; /*!< MMC IPC Receive Checksum Offload Interrupt Mask */ + __I uint32_t RESERVED5[319]; + + union { + __IO uint32_t PTPTSCR; /*!< Timestamp Control Register */ + + struct { + __IO uint32_t TSENA : 1; /*!< Timestamp Enable */ + __IO uint32_t TSCFUPDT : 1; /*!< Timestamp Fine or Coarse Update */ + __IO uint32_t TSINIT : 1; /*!< Timestamp Initialize */ + __IO uint32_t TSUPDT : 1; /*!< Timestamp Update */ + __IO uint32_t TSTRIG : 1; /*!< Timestamp Interrupt Trigger Enable */ + __IO uint32_t TSADDREG : 1; /*!< Addend Reg Update */ + } PTPTSCR_b; /*!< BitSize */ + }; + __IO uint32_t PTPSSIR; /*!< Sub-Second Increment Register */ + __IO uint32_t PTPTSHR; /*!< System Time Seconds Register */ + __IO uint32_t PTPTSLR; /*!< System Time Nanoseconds Register */ + __IO uint32_t PTPTSHUR; /*!< System Time Seconds Update Register */ + __IO uint32_t PTPTSLUR; /*!< System Time Nanoseconds Update Register */ + __IO uint32_t PTPTSAR; /*!< Timestamp Addend Register */ + __IO uint32_t PTPTTHR; /*!< Target Time Seconds Register */ + __IO uint32_t PTPTTLR; /*!< Target Time Nanoseconds Register */ + __I uint32_t RESERVED6[567]; + + union { + __IO uint32_t BUS_MODE; /*!< Flow Control Register */ + + struct { + __IO uint32_t SWR : 1; /*!< Software Reset */ + __IO uint32_t DA : 1; /*!< This bit specifies the arbitration scheme between the transmit + and receive paths of Channel */ + __IO uint32_t DSL : 5; /*!< the byte number of bus width to skip between two unchained descriptors */ + __IO uint32_t ATDS : 1; /*!< When set, the size of the alternate descriptor increases to + 32 bytes */ + __IO uint32_t PBL : 6; /*!< These bits indicate the maximum number of beats to be transferred + in one DMA transaction */ + __IO uint32_t PR : 2; /*!< The Priority Ratio is (PR + 1) : 1 */ + __IO uint32_t FB : 1; /*!< performs fixed burst transfers or not */ + __IO uint32_t RPBL : 6; /*!< This field indicates the maximum number of beats to be transferred + in one Rx DMA transaction */ + __IO uint32_t USP : 1; /*!< If set, RPBL is same as RPBL definition */ + __IO uint32_t PBLx8 : 1; /*!< If set, all PBLs multiplies 8 */ + __IO uint32_t AAL : 1; /*!< If set, all bursts aligned to the start address LS bits */ + __IO uint32_t MB : 1; /*!< When this bit is set high and the FB bit is low, the AHB master + interface starts all bursts of length more than 16 with INCR */ + __IO uint32_t TXPR : 1; /*!< When set, the transmit DMA has higher priority than the receive + DMA */ + __IO uint32_t PRWG : 2; /*!< The Priority weight is (PRWG + 1) : 1 */ + uint32_t : 1; + __IO uint32_t RIB : 1; /*!< If set, rebuilds the pending beats of any burst transfer initiated + with INCRx */ + } BUS_MODE_b; /*!< BitSize */ + }; + __IO uint32_t TPD; /*!< Transmit Poll Demand */ + __IO uint32_t RPD; /*!< Receive Poll Demand */ + __IO uint32_t RDESLA; /*!< Receive Descriptor List Address */ + __IO uint32_t TDESLA; /*!< Transmit Descriptor List Address */ + + union { + __IO uint32_t STATUS; /*!< Status Register */ + + struct { + __IO uint32_t TI : 1; /*!< This bit indicates that the frame transmission is complete */ + __IO uint32_t TPS : 1; /*!< Transmit Process Stopped */ + __IO uint32_t TU : 1; /*!< the host owns the Next Descriptor in the Transmit List and the + DMA cannot acquire it. */ + __IO uint32_t TJT : 1; /*!< Transmit Jabber Timeout */ + __IO uint32_t OVF : 1; /*!< Receive Overflow */ + __IO uint32_t UNF : 1; /*!< Transmit Underflow */ + __IO uint32_t RI : 1; /*!< the frame reception is complete */ + __IO uint32_t RU : 1; /*!< Receive Buffer Unavailable */ + __IO uint32_t RPS : 1; /*!< Receive Process Stopped */ + __IO uint32_t RWT : 1; /*!< Receive Watchdog Timeout */ + __IO uint32_t ETI : 1; /*!< the frame to be transmitted is fully transferred to the MTL + Transmit FIFO */ + uint32_t : 2; + __IO uint32_t FBI : 1; /*!< a bus error occurred, as described in EB. */ + __IO uint32_t ERI : 1; /*!< the DMA filled the first data buffer of the packet */ + __IO uint32_t AIS : 1; /*!< Abnormal Interrupt Summary, must be cleared by writting */ + __IO uint32_t NIS : 1; /*!< Normal Interrupt Summary, must be cleared by writting */ + __I uint32_t RS : 3; /*!< Receive DMA FSM state */ + __I uint32_t TS : 3; /*!< Transmit DMA FSM state */ + __I uint32_t EB : 3; /*!< Error bit */ + __I uint32_t GLI : 1; /*!< GMAC Line Interface Interrupt */ + __I uint32_t GMI : 1; /*!< GMAC MMC Interrupt */ + __I uint32_t GPI : 1; /*!< GMAC PMT Interrupt */ + __I uint32_t TTI : 1; /*!< Timestamp Trigger Interrupt */ + } STATUS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t OPERATION; /*!< Operation Mode Register */ + + struct { + uint32_t : 1; + __IO uint32_t SR : 1; /*!< Start or Stop Receive */ + __IO uint32_t OSF : 1; /*!< Operate on Second Frame */ + __IO uint32_t RT : 2; /*!< Receive Threshold Control */ + __IO uint32_t DGF : 1; /*!< Drop Giant Frames */ + __IO uint32_t FUF : 1; /*!< Forward Undersized Good Frames */ + __IO uint32_t FEF : 1; /*!< Forward Error Frames */ + uint32_t : 5; + __IO uint32_t ST : 1; /*!< Start or Stop Transmission Command */ + __IO uint32_t TT : 3; /*!< Transmit Threshold Control */ + uint32_t : 3; + __IO uint32_t FTF : 1; /*!< Flush Transmit FIFO */ + __IO uint32_t TSF : 1; /*!< If set, transmission starts when a full frame resides in Transmit + FIFO */ + uint32_t : 2; + __IO uint32_t DFF : 1; /*!< Disable Flushing of Received Frames */ + __IO uint32_t RSF : 1; /*!< If set, the MTL reads a frame from the Rx FIFO while the complete + frame has been written to it, */ + } OPERATION_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INT_EN; /*!< Interrupt Enable Register */ + + struct { + __IO uint32_t TIE : 1; /*!< Transmit Interrupt Enable */ + __IO uint32_t TSE : 1; /*!< Transmit Stopped Enable */ + __IO uint32_t TUE : 1; /*!< Transmit Buffer Unavailable Enable */ + __IO uint32_t TJE : 1; /*!< Transmit Jabber Timeout Enable */ + __IO uint32_t OVE : 1; /*!< Overflow Interrupt Enable */ + __IO uint32_t UNE : 1; /*!< Underflow Interrupt Enable */ + __IO uint32_t RIE : 1; /*!< Receive Interrupt Enable */ + __IO uint32_t RUE : 1; /*!< Receive Buffer Unavailable Enable */ + __IO uint32_t RSE : 1; /*!< Receive Stopped Enable */ + __IO uint32_t RWE : 1; /*!< Receive Watchdog Timeout Enable */ + __IO uint32_t ETE : 1; /*!< Early Transmit Interrupt Enable */ + uint32_t : 2; + __IO uint32_t FBE : 1; /*!< Fatal Bus Error Enable */ + __IO uint32_t ERE : 1; /*!< Early Receive Interrupt Enable */ + __IO uint32_t AIE : 1; /*!< Abnormal Interrupt Summary Enable */ + __IO uint32_t NIE : 1; /*!< Normal Interrupt Summary Enable */ + } INT_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED7[3]; + + union { + __IO uint32_t AHB_STATUS; /*!< AHB Status Register */ + + struct { + __IO uint32_t BUSY : 1; /*!< If set, it indicates that the AHB master interface FSMs are + in the non-idle state */ + } AHB_STATUS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED8[6]; + __I uint32_t CURTDESAPTR; /*!< Current Host Transmit Descriptor Register */ + __I uint32_t CURRDESAPTR; /*!< Current Host Receive Descriptor Register */ + __I uint32_t CURTBUFAPTR; /*!< Current Host Transmit Buffer Address Register */ + __I uint32_t CURRBUFAPTR; /*!< Current Host Receive Buffer Address Register */ +} ETH_Type; + + +/* ================================================================================ */ +/* ================ USB ================ */ +/* ================================================================================ */ + + +/** + * @brief USB (USB) + */ + +typedef struct { /*!< USB Structure */ + + union { + __IO uint32_t GOTGCTL; /*!< Control and Status register */ + + struct { + __I uint32_t SES_REQ_SCS: 1; /*!< set when a session request initiation is successful as a device */ + __IO uint32_t SES_SEQ : 1; /*!< set to initiate a session request on the USB as a device */ + __IO uint32_t VB_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using + the GOTGCTL.VbvalidOvVal as a host */ + __IO uint32_t VB_VALID_OV_VAL: 1; /*!< set Override value for vbusvalid signal when GOTGCTL.VbvalidOvEn + is set as a host */ + __IO uint32_t A_VALID_OV_EN: 1; /*!< enable/disable the software to override the Avalid signal using + the GOTGCTL.AvalidOvVal as a host */ + __IO uint32_t A_VALID_OV_VAL: 1; /*!< set Override value for Avalid signal when GOTGCTL.AvalidOvEn + is set as a host */ + __IO uint32_t B_VALID_OV_EN: 1; /*!< enable/disable the software to override the Bvalid signal using + the GOTGCTL.BvalidOvVal as a device. */ + __IO uint32_t B_VALID_OV_VAL: 1; /*!< set Override value for Bvalid signal when GOTGCTL.BvalidOvEn + is set as a device. */ + __I uint32_t HST_NEG_SCS: 1; /*!< sets when host negotiation is successful as a device. */ + __IO uint32_t HNP_REQ : 1; /*!< sets this bit to initiate an HNP request to the connected USB + host as a device */ + __IO uint32_t HST_SET_HNP_EN: 1; /*!< Host Set HNP Enable as a host */ + __IO uint32_t DEV_HNP_EN : 1; /*!< Device HNP Enabled as a device */ + uint32_t : 4; + __I uint32_t CON_ID_STS : 1; /*!< Connector ID Status */ + __I uint32_t DBNC_TIME : 1; /*!< the debounce time of a detected connection as a host */ + __I uint32_t A_SES_VLD : 1; /*!< A-Session Valid as a host */ + __I uint32_t B_SES_VLD : 1; /*!< B-Session Valid as a host */ + __IO uint32_t OTG_VER : 1; /*!< If 0, OTG Version 1.3. If 1, OTG Version 2.0. */ + } GOTGCTL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GOTGINT; /*!< OTG interrupt Register */ + + struct { + uint32_t : 2; + __IO uint32_t SES_END_DET: 1; /*!< Set when the utmiotg_bvalid signal is deasserted */ + uint32_t : 5; + __IO uint32_t SES_REQ_SUC_STS_CHNG: 1; /*!< Session Request Success Status Change */ + __IO uint32_t HST_NEG_SUC_STS_CHNG: 1; /*!< Host Negotiation Success Status Change */ + uint32_t : 7; + __IO uint32_t HST_NEG_DET: 1; /*!< if set, detects a host negotiation request on the USB */ + __IO uint32_t A_DEV_TOUT_CHG: 1; /*!< A-device has timed out while waiting for the B-device to connect */ + __IO uint32_t DBNCE_DONE : 1; /*!< debounce is completed after the device connect as a host */ + } GOTGINT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GAHBCFG; /*!< AHB Configuration Register */ + + struct { + __IO uint32_t GLBL_INTR_EN: 1; /*!< Global Interrupt Enable */ + __IO uint32_t BST_LEN : 4; /*!< Burst Length/Type */ + __IO uint32_t DMA_EN : 1; /*!< DMA enable */ + uint32_t : 15; + __IO uint32_t REMOTE_MEM_SUPP: 1; /*!< enable the functionality to wait for the system DMA Done Signal + for the DMA Write Transfers */ + __IO uint32_t NOTIFY_ALL_DMA_WRITE: 1; /*!< enable the System DMA Done functionality for all the DMA write + Transactions corresponding to the Channel/Endpoint */ + __IO uint32_t AHB_SINGLE : 1; /*!< supports Single transfers for the remaining data in a transfer */ + } GAHBCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GUSBCFG; /*!< USB Configuration Register */ + + struct { + uint32_t : 3; + __IO uint32_t PHY_IF : 1; /*!< PHY Interface */ + __IO uint32_t ULPI_UTMI_SEL: 1; /*!< 1, ULPI. 0, UTMI+ */ + __IO uint32_t FS_IF : 1; /*!< 1, 3-pin bidirectional. 0, 6-pin unidirectional */ + __IO uint32_t PHY_SEL : 1; /*!< 0, USB 2.0 High-Speed PHY. 1, USB 1.1 full-speed serial transceiver */ + __IO uint32_t DDR_SEL : 1; /*!< 0, Single Data Rate ULPI Interface, with 8-bit-wide data bus. + 1, Double Data Rate ULPI Interface, with 4-bit-wide data bus */ + __IO uint32_t SRP_CAP : 1; /*!< SRP-Capable */ + __IO uint32_t HNP_CAP : 1; /*!< HNP-Capable */ + __IO uint32_t USB_TRD_TIM: 4; /*!< Specifies the response time for a MAC request to the Packet + FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM) as + a device. */ + uint32_t : 1; + __IO uint32_t PHY_LPWR_CLK_SEL: 1; /*!< 0, 480-MHz Internal PLL clock. 1, 48-MHz External Clock */ + uint32_t : 12; + __IO uint32_t TX_END_DELAY: 1; /*!< Tx End Delay as a device */ + __IO uint32_t FORCE_HOST_MODE: 1; /*!< Force Host Mode */ + __IO uint32_t FORCE_DEVICE_MODE: 1; /*!< Force Device Mode */ + } GUSBCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GRSTCTL; /*!< Reset Register */ + + struct { + __IO uint32_t CORE_SOFT_RST: 1; /*!< Core Soft Reset */ + uint32_t : 1; + __IO uint32_t FRM_CNT_RST: 1; /*!< Host Frame Counter Reset */ + uint32_t : 1; + __IO uint32_t RX_FIFO_FLUSH: 1; /*!< RxFIFO Flush */ + __IO uint32_t TX_FIFO_FLUSH: 1; /*!< TxFIFO Flush */ + __IO uint32_t TX_FIFO_FLUSH_NUM: 4; /*!< This field indicates which of the 32 possible PHY devices are + being accessed */ + __IO uint32_t TX_FIFO_ALL: 1; /*!< TxFIFO flush all FIFOs */ + uint32_t : 19; + __I uint32_t DMA_REQ : 1; /*!< Indicates that the DMA request is in progress */ + __I uint32_t AHB_IDLE : 1; /*!< Indicates that the AHB Master State Machine is in the IDLE condition */ + } GRSTCTL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GINTSTS; /*!< Interrupt Register */ + + struct { + __I uint32_t CUR_MOD : 1; /*!< Current Mode of Operation */ + __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch Interrupt */ + __I uint32_t OTG_INT : 1; /*!< OTG Interrupt */ + __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ + __I uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ + __I uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ + __I uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ + __I uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ + uint32_t : 2; + __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ + __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ + __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ + __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ + __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a + device */ + __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ + uint32_t : 1; + __I uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ + __I uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ + __I uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ + __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ + __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous + OUT Transfer as a device */ + __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ + __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ + __I uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as + a host */ + __I uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as + a host */ + __I uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ + __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ + __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ + __IO uint32_t DD : 1; /*!< A change in connector ID status */ + __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ + __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ + } GINTSTS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GINTEN; /*!< Interrupt enable Register */ + + struct { + uint32_t : 1; + __IO uint32_t MODE_MIS : 1; /*!< Mode Mismatch */ + __IO uint32_t OTG_INT : 1; /*!< OTG */ + __IO uint32_t SOF : 1; /*!< Start of (micro)Frame */ + __IO uint32_t RFNE : 1; /*!< RxFIFO Non-Empty */ + __IO uint32_t NPTFE : 1; /*!< Non-periodic TxFIFO Empty */ + __IO uint32_t GIN_NAK_EFF: 1; /*!< Global IN Non-periodic NAK Effective as a device */ + __IO uint32_t GOUT_NAK_EFF: 1; /*!< Global OUT NAK Effective as a device */ + uint32_t : 2; + __IO uint32_t EARLY_SUS : 1; /*!< an Idle state has been detected on the USB For 3 ms as a device */ + __IO uint32_t USB_SUS : 1; /*!< A suspend was detected on the USB as a device */ + __IO uint32_t USB_RST : 1; /*!< A reset is detected on the USB as a device */ + __IO uint32_t ENUM_DONE : 1; /*!< speed enumeration is complete as a device */ + __IO uint32_t ISO_OUT_DROP: 1; /*!< Drop an isochronous OUT packet while no space in RXFIFO as a + device */ + __IO uint32_t EOPF : 1; /*!< End of Periodic Frame Interrupt as a device */ + uint32_t : 1; + __IO uint32_t EP_MIS : 1; /*!< Endpoint Mismatch Interrupt as a device */ + __IO uint32_t IEP_INT : 1; /*!< IN Endpoints Interrupt as a device */ + __IO uint32_t OEP_INT : 1; /*!< OUT Endpoints Interrupt as a device */ + __IO uint32_t INCOMP_ISO_IN: 1; /*!< Incomplete Isochronous IN Transfer as a device */ + __IO uint32_t IPT_IIOT : 1; /*!< OUT Incomplete Periodic Transfer as a host or Incomplete Isochronous + OUT Transfer as a device */ + __IO uint32_t DFS : 1; /*!< Data Fetch Suspended as a device */ + __IO uint32_t RST_DET : 1; /*!< reset detect as a device */ + __IO uint32_t HP : 1; /*!< a change in port status of one of the DWC_otg core ports as + a host */ + __IO uint32_t HC : 1; /*!< an interrupt is pending on one of the channels of the core as + a host */ + __IO uint32_t PTFE : 1; /*!< Periodic TxFIFO Empty as a host */ + __IO uint32_t LPM : 1; /*!< LPM Transaction Received Interrupt */ + __IO uint32_t CIDSC : 1; /*!< A change in connector ID status */ + __IO uint32_t DD : 1; /*!< A change in connector ID status */ + __IO uint32_t SR : 1; /*!< Session Request/New Session Detected Interrupt */ + __IO uint32_t WAKEUP : 1; /*!< Resume/Remote Wakeup Detected Interrupt */ + } GINTEN_b; /*!< BitSize */ + }; + + union { + __I uint32_t GRXSTSR; /*!< Returns the contents of the top of the Receive FIFO */ + + struct { + __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ + __I uint32_t BCNT : 11; /*!< byte count of the received packet */ + __I uint32_t DPID : 2; /*!< Data PID of the received packet */ + __I uint32_t PS : 4; /*!< the status of the received packet */ + __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which + the packet is received on the USB */ + } GRXSTSR_b; /*!< BitSize */ + }; + + union { + __I uint32_t GRXSTSP; /*!< Pop the contents of the top of the Receive FIFO */ + + struct { + __I uint32_t CH_EP_NUM : 4; /*!< channel number as a host or EP number as a device */ + __I uint32_t BCNT : 11; /*!< byte count of the received packet */ + __I uint32_t DPID : 2; /*!< Data PID of the received packet */ + __I uint32_t PS : 4; /*!< the status of the received packet */ + __I uint32_t FN : 4; /*!< the least significant 4 bits of the (micro)frame number in which + the packet is received on the USB */ + } GRXSTSP_b; /*!< BitSize */ + }; + __IO uint16_t GRXFSIZ; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 + is max */ + __I uint16_t RESERVED0; + + union { + __IO uint32_t GNPTXFSIZ; /*!< Non-Periodic Transmit FIFO Size Register */ + + struct { + __IO uint32_t NTRSA_INEF0TRSA: 16; /*!< start address for Non-periodic Transmit FIFO RAM as a host or + IN Endpoint FIFO0 Transmit RAM as a device */ + __IO uint32_t NTD_INEF0TD: 16; /*!< This value is in terms of 32-bit words, 16 is minimize and 32768 + is max. Non-periodic TxFIFO Depth as a host or IN Endpoint TxFIFO + 0 Depth as a device */ + } GNPTXFSIZ_b; /*!< BitSize */ + }; + + union { + __I uint32_t GNPTXSTS; /*!< Non-Periodic Transmit FIFO/Queue Status Register */ + + struct { + __I uint32_t NTSA : 16; /*!< the amount of free space available in the Non-periodic TxFIFO, + max is 32768. */ + __I uint32_t NTRQSA : 8; /*!< the amount of free space available in the Non-periodic Transmit + Request Queue, max is 8. */ + __I uint32_t TNTRQ_LAST : 1; /*!< last Entry in the Non-periodic Tx Request Queue that is currently + being processed by the MAC */ + __I uint32_t TNTRQ_TYPE : 2; /*!< type in the Non-periodic Tx Request Queue that is currently + being processed by the MAC */ + __I uint32_t TNTRQ_CH : 4; /*!< Channel of top of the Non-periodic Transmit Request Queue */ + } GNPTXSTS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[5]; + + union { + __I uint32_t GHWCFG1; /*!< User HW Config1 Register */ + + struct { + __I uint32_t EP0_DIR : 2; /*!< Endpoint 0 direction, always Bidirection */ + __I uint32_t EP1_DIR : 2; /*!< Endpoint 1 direction */ + __I uint32_t EP2_DIR : 2; /*!< Endpoint 2 direction */ + __I uint32_t EP3_DIR : 2; /*!< Endpoint 3 direction */ + __I uint32_t EP4_DIR : 2; /*!< Endpoint 4 direction */ + __I uint32_t EP5_DIR : 2; /*!< Endpoint 5 direction */ + __I uint32_t EP6_DIR : 2; /*!< Endpoint 6 direction */ + __I uint32_t EP7_DIR : 2; /*!< Endpoint 7 direction */ + __I uint32_t EP8_DIR : 2; /*!< Endpoint 8 direction */ + __I uint32_t EP9_DIR : 2; /*!< Endpoint 9 direction */ + __I uint32_t EP10_DIR : 2; /*!< Endpoint 10 direction */ + __I uint32_t EP11_DIR : 2; /*!< Endpoint 11 direction */ + __I uint32_t EP12_DIR : 2; /*!< Endpoint 12 direction */ + __I uint32_t EP13_DIR : 2; /*!< Endpoint 13 direction */ + __I uint32_t EP14_DIR : 2; /*!< Endpoint 14 direction */ + __I uint32_t EP15_DIR : 2; /*!< Endpoint 15 direction */ + } GHWCFG1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2[3]; + + union { + __IO uint32_t GLPMCFG; /*!< Core LPM Configuration Register */ + + struct { + __IO uint32_t EP0_DIR : 1; /*!< LPM capability is enabled */ + } GLPMCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GPWRDN; /*!< Global Power Down Register */ + + struct { + uint32_t : 1; + __IO uint32_t PMU_ACTIVE : 1; /*!< PMU Active is enabled */ + uint32_t : 1; + __IO uint32_t PDC : 1; /*!< Power Down Clamp is enabled */ + __IO uint32_t PDR : 1; /*!< If clear, Reset DWC_otg */ + __IO uint32_t PDS : 1; /*!< If 0, DWC_otg is in ON state, or OFF state */ + __IO uint32_t DIS_VBUS : 1; /*!< Disable VBUS */ + uint32_t : 8; + __IO uint32_t SRP_DETECT_INT: 1; /*!< SRP has been detected by the PMU as a host */ + __IO uint32_t SRP_DETECT_INT_EN: 1; /*!< Enable For SRPDetect Interrupt as a host */ + __IO uint32_t STATE_CHN_INT: 1; /*!< a status change in either the IDDIG or BSessVld signal */ + __IO uint32_t STATE_CHN_INT_EN: 1; /*!< Enable For Status Change Interrupt */ + __I uint32_t LINE_STATE : 2; /*!< the current linestate on USB as seen by the PMU module */ + __I uint32_t IDDIG : 1; /*!< the status of the IDDIG signal. If 0, host mode. if 1, device + mode */ + __I uint32_t B_SESS_VLD : 1; /*!< B session valid status signal from the PHY */ + __IO uint32_t ADP_INT : 1; /*!< set whenever there is a ADP event */ + } GPWRDN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t GDFIFOCFG; /*!< Global DFIFO Software Config Register */ + + struct { + __IO uint32_t GDFIFOCFG : 16; /*!< This field is for dynamic programming of the DFIFO Size. */ + __IO uint32_t EPIBA : 16; /*!< This field provides the start address of the EP info controller */ + } GDFIFOCFG_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[40]; + + union { + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Transmit FIFO Size Register */ + + struct { + __IO uint32_t HPTSA : 16; /*!< start address of the Periodic TxFIFO */ + __IO uint32_t EPIBA : 16; /*!< the size of the Periodic TxFIFO */ + } HPTXFSIZ_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF1; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF2; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF3; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF4; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF5; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF6; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF7; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF8; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF9; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF10; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF11; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF12; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF13; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF14; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DIEPTXF15; /*!< Device In Endpoint Transmit FIFO Size Register */ + + struct { + __IO uint32_t INEFTRSA : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t INETFD : 16; /*!< IN Endpoint TxFIFO Depth */ + } DIEPTXF15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED4[176]; + + union { + __IO uint32_t HCFG; /*!< Host Configuration Register */ + + struct { + __IO uint32_t FS_LS_PCS : 2; /*!< FS/LS PHY Clock Select as a host */ + __IO uint32_t FS_LS_SUPPORT: 1; /*!< If set, FS/LS-only, even If the connected device can support + HS */ + uint32_t : 4; + __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ + __IO uint32_t RVP : 8; /*!< ResValid number of clock cycles to detect a valid resume */ + uint32_t : 7; + __IO uint32_t EN_SG_DMA : 1; /*!< Enable Scatter/gather DMA in Host mode */ + __IO uint32_t FLE : 2; /*!< the number of entries in the Frame list. 8 times of FLE */ + __IO uint32_t EPS : 1; /*!< Enables periodic scheduling */ + uint32_t : 4; + __IO uint32_t MCRTE : 1; /*!< enable/disable the Host core to wait 200 PHY clock cycles at + the end of Resume to change the opmode signal to the PHY to + 00 after Suspend or LPM. */ + } HCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HFIR; /*!< Host Frame Interval Register */ + + struct { + __IO uint32_t FI : 16; /*!< IN Endpoint FIFOn Transmit RAM Start Address */ + __IO uint32_t RC : 1; /*!< The HFIR can be dynamically reloaded during runtime if set */ + } HFIR_b; /*!< BitSize */ + }; + + union { + __I uint32_t HFNUM; /*!< Host Frame Number/Frame Time Remaining Register */ + + struct { + __I uint32_t FN : 16; /*!< This field increments when a new SOF is transmitted on the USB */ + __I uint32_t FTR : 16; /*!< amount of time remaining in the current microframe (HS) or Frame + (FS/LS), in terms of PHY clocks */ + } HFNUM_b; /*!< BitSize */ + }; + __I uint32_t RESERVED5; + + union { + __I uint32_t HPTXSTS; /*!< Host Periodic Transmit FIFO/Queue Status Register */ + + struct { + __I uint32_t PTDFSA : 16; /*!< Indicates the number of free locations available to be written + to in the Periodic TxFIFO, max is 32768 */ + __I uint32_t PTRQSA : 8; /*!< Indicates the number of free locations available to be written + in the Periodic Transmit Request Queue, max is 16 */ + __I uint32_t TPTRQ_LAST : 1; /*!< last Entry in the periodic Tx Request Queue that is currently + being processed by the MAC */ + __I uint32_t TPTRQ_TYPE : 2; /*!< type in the periodic Tx Request Queue that is currently being + processed by the MAC */ + __I uint32_t TPTRQ_CH : 4; /*!< Channel of top of the periodic Transmit Request Queue */ + __I uint32_t TPTRQ_ODD_FRAME: 1; /*!< If set, send in odd (micro)Frame */ + } HPTXSTS_b; /*!< BitSize */ + }; + + union { + __I uint32_t HAINT; /*!< Host All Channels Interrupt Register */ + + struct { + __I uint32_t INT : 16; /*!< Channel Interrupts, from 0 to 15. */ + } HAINT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HAINT_EN; /*!< Host All Channels Interrupt Enable Register */ + + struct { + __IO uint32_t EN : 16; /*!< Channel Interrupts Enable, from 0 to 15. */ + } HAINT_EN_b; /*!< BitSize */ + }; + __IO uint32_t HFLBA; /*!< The starting address of the Frame list */ + __I uint32_t RESERVED6[8]; + + union { + __IO uint32_t __HPRT; /*!< Host Port Control and Status Register */ + + struct { + __I uint32_t PCS : 1; /*!< If a device is attached to the port */ + __IO uint32_t PCD : 1; /*!< A device connection is detected */ + __IO uint32_t PE : 1; /*!< Port Enable */ + __IO uint32_t PEDC : 1; /*!< Set if when the status of the Port Enable (bit 2) of this register + changes */ + __I uint32_t POA : 1; /*!< Indicates the overcurrent condition of the port */ + __IO uint32_t POC : 1; /*!< Set if when the status of the Port Overcurrent Active bit (bit + 4) in this register changes */ + __IO uint32_t PR : 1; /*!< Application and Core all can perform resume by setting, then + clear it whatever resume is success or not */ + __IO uint32_t PS : 1; /*!< Sets this bit to put this port in Suspend mode */ + __IO uint32_t PRESET : 1; /*!< sets this bit, a reset sequence is started on this port */ + uint32_t : 1; + __IO uint32_t PLSDP : 1; /*!< Logic level of D+ */ + __IO uint32_t PLSDN : 1; /*!< Logic level of D- */ + __IO uint32_t PP : 1; /*!< this field to control power to this port. 1, power on */ + __IO uint32_t PTC : 4; /*!< The application writes a nonzero value to this field to put + the port into a Test mode */ + __I uint32_t SPEED : 2; /*!< Indicates the speed of the device attached to this port */ + } __HPRT_b; /*!< BitSize */ + }; + __I uint32_t RESERVED7[47]; + + union { + __IO uint32_t HCC0; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED8; + + union { + __IO uint32_t HCINT0; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN0; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ0; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA0; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED9; + __IO uint32_t HCDMAB0; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC1; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED10; + + union { + __IO uint32_t HCINT1; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN1; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ1; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA1; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED11; + __IO uint32_t HCDMAB1; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC2; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED12; + + union { + __IO uint32_t HCINT2; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN2; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ2; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA2; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED13; + __IO uint32_t HCDMAB2; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC3; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED14; + + union { + __IO uint32_t HCINT3; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN3; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ3; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA3; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED15; + __IO uint32_t HCDMAB3; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC4; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED16; + + union { + __IO uint32_t HCINT4; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN4; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ4; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ4_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA4; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED17; + __IO uint32_t HCDMAB4; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC5; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED18; + + union { + __IO uint32_t HCINT5; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN5; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ5; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ5_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA5; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED19; + __IO uint32_t HCDMAB5; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC6; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED20; + + union { + __IO uint32_t HCINT6; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN6; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ6; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ6_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA6; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED21; + __IO uint32_t HCDMAB6; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC7; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED22; + + union { + __IO uint32_t HCINT7; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN7; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ7; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ7_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA7; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED23; + __IO uint32_t HCDMAB7; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC8; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED24; + + union { + __IO uint32_t HCINT8; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN8; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ8; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ8_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA8; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED25; + __IO uint32_t HCDMAB8; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC9; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED26; + + union { + __IO uint32_t HCINT9; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN9; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ9; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ9_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA9; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED27; + __IO uint32_t HCDMAB9; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC10; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED28; + + union { + __IO uint32_t HCINT10; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN10; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ10; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ10_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA10; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED29; + __IO uint32_t HCDMAB10; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC11; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED30; + + union { + __IO uint32_t HCINT11; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN11; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ11; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ11_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA11; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED31; + __IO uint32_t HCDMAB11; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC12; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED32; + + union { + __IO uint32_t HCINT12; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN12; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ12; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ12_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA12; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED33; + __IO uint32_t HCDMAB12; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC13; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED34; + + union { + __IO uint32_t HCINT13; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN13; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ13; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ13_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA13; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED35; + __IO uint32_t HCDMAB13; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC14; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED36; + + union { + __IO uint32_t HCINT14; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN14; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ14; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ14_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA14; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED37; + __IO uint32_t HCDMAB14; /*!< Host Channel-n DMA Buffer Address Register */ + + union { + __IO uint32_t HCC15; /*!< Host Channel Characteristics Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + __IO uint32_t EP_NUM : 4; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t EP_DIR : 1; /*!< Indicates whether the transaction is IN or OUT. 0, OUT. 1, IN */ + uint32_t : 1; + __IO uint32_t LSD : 1; /*!< indicate that this channel is communicating to a low-speed device. */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 2; /*!< Multi Count (MC) / Error Count (EC). */ + __IO uint32_t DA : 7; /*!< This field selects the specific device serving as the data source + or sink. */ + __IO uint32_t OF : 1; /*!< The frame is odd or even. */ + __IO uint32_t CD : 1; /*!< sets this bit to stop transmitting/receiving data on a channel. */ + __IO uint32_t CE : 1; /*!< If the descriptor structure and data buffer are ready or not + yet. */ + } HCC15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED38; + + union { + __IO uint32_t HCINT15; /*!< Host Channel Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT15_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCINT_EN15; /*!< Host Channel Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t CH_HALT : 1; /*!< Indicates the endpoint number on the device serving as the data + source or sink. */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + uint32_t : 8; + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + __IO uint32_t ETE : 1; /*!< 3 consecutive transaction errors occurred on the USB bus */ + __IO uint32_t DR : 1; /*!< the corresponding channel's descriptor list rolls over */ + } HCINT_EN15_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCTSIZ15; /*!< Host Channel Transfer Size Register */ + + struct { + __IO uint32_t SCHED_INFO : 8; /*!< Every bit in this 8 bit register indicates scheduling for that + microframe.Bit N indicates scheduling for Nth microframe scheduling + for 8th microframe in that frame. */ + __IO uint32_t NTD : 8; /*!< Number of Transfer Descriptors. */ + uint32_t : 13; + __IO uint32_t PID : 2; /*!< the type of PID to use for the initial transaction */ + __IO uint32_t PING : 1; /*!< Setting this field to 1 directs the host to do PING protocol */ + } HCTSIZ15_b; /*!< BitSize */ + }; + + union { + __IO uint32_t HCDMA15; /*!< Host Channel-n DMA Address Register */ + + struct { + uint32_t : 3; + __IO uint32_t CTD : 6; /*!< Number of Transfer Descriptors for Non-Isochronous */ + __IO uint32_t ADDR : 23; /*!< he start address of 512 bytes page for Non-Isochronous */ + } HCDMA15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED39; + __IO uint32_t HCDMAB15; /*!< Host Channel-n DMA Buffer Address Register */ + __I uint32_t RESERVED40[64]; + + union { + __IO uint32_t DCFG; /*!< Device Configuration Register */ + + struct { + __IO uint32_t DSPEED : 2; /*!< the maximum speed the application can support */ + __IO uint32_t NZLSOH : 1; /*!< select the handshake the core sends on receiving a non zero-length + data packet during the OUT transaction of a control transfer's + Status stage */ + __IO uint32_t EN_32K_SUS : 1; /*!< Enable 32 KHz Suspend mode */ + __IO uint32_t DEVICE_ADDR: 7; /*!< The application must program this field after every SetAddress + control command */ + __IO uint32_t PFI : 2; /*!< Indicates the time within a (micro)frame at which the application + must be notified using the End Of Periodic Frame Interrupt */ + __IO uint32_t EDON : 1; /*!< If set the core sets NAK after Bulk OUT transfer complete */ + uint32_t : 9; + __IO uint32_t EN_SG_DMA : 1; /*!< enable the Scatter/Gather DMA operation */ + __IO uint32_t PSI : 2; /*!< Periodic Scheduling Interval */ + __IO uint32_t RVP : 6; /*!< It controls the resume period when the core resumes from suspend */ + } DCFG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DCTL; /*!< Device Control Register */ + + struct { + __IO uint32_t RWS : 1; /*!< If set, the core initiates remote signaling to wake the USB + hosts */ + __IO uint32_t SD : 1; /*!< If set, generates a device disconnect event to the USB host */ + __I uint32_t GNPINS : 1; /*!< A NAK handshake is sent out on all non-periodic IN endpoints, + irrespective of the data availability in the transmit FIFO. */ + __I uint32_t GONS : 1; /*!< No data is written to the RxFIFO, irrespective of space availability.. */ + __IO uint32_t TC : 3; /*!< Test Control */ + __O uint32_t SGNPIN : 1; /*!< A write to this field sets the Global Non-periodic IN NAK */ + __O uint32_t CGNPIN : 1; /*!< A write to this field clears the Global Non-periodic IN NAK */ + __O uint32_t SGON : 1; /*!< A write to this field sets the Global OUT NAK */ + __O uint32_t CGON : 1; /*!< A write to this field sets the Global OUT NAK. */ + __IO uint32_t POPD : 1; /*!< Power-On Programming Done */ + __IO uint32_t GMC : 2; /*!< GMC must be programmed only once after initialization. the number + of packets to be serviced for that end point before moving to + the next end point */ + uint32_t : 1; + __IO uint32_t IFNIE : 1; /*!< Ignore frame number for isochronous endpoints */ + __IO uint32_t NBE : 1; /*!< Set NAK automatically on babble */ + __IO uint32_t ECBNA : 1; /*!< After receiving BNA interrupt, the core disables the endpoint */ + } DCTL_b; /*!< BitSize */ + }; + + union { + __I uint32_t DSTS; /*!< Device Status Register */ + + struct { + __I uint32_t SUSPEND : 1; /*!< this bit is set as long as a Suspend condition is detected on + the USB */ + __I uint32_t SPEED : 2; /*!< Indicates the speed at which the DWC_otg core has come up after + speed detection through a chirp sequence */ + __I uint32_t EE : 1; /*!< reason of suspend state */ + uint32_t : 4; + __I uint32_t SOFFN : 14; /*!< Frame or Microframe Number of the Received SOF */ + __I uint32_t DLSDP : 1; /*!< Logic level of D+ */ + __I uint32_t DLSDN : 1; /*!< Logic level of D- */ + } DSTS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED41; + + union { + __IO uint32_t DIEPEN; /*!< Device IN Endpoint Common Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ + __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ + __IO uint32_t TIMEOUT : 1; /*!< Timeout Condition(Non-isochronous endpoints) */ + __IO uint32_t ITRWTFE : 1; /*!< IN Token Received When TxFIFO Empty */ + __IO uint32_t ITRWEPM : 1; /*!< IN Token received with EP Mismatch */ + __IO uint32_t IENE : 1; /*!< IN Endpoint NAK Effective */ + uint32_t : 1; + __IO uint32_t FU : 1; /*!< Fifo Underrun */ + __IO uint32_t BNA : 1; /*!< BNA Interrupt */ + uint32_t : 3; + __IO uint32_t NAK : 1; /*!< NAK interrupt */ + } DIEPEN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DOEPEN; /*!< Device OUT Endpoint Common Interrupt Enable Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer Completed Interrupt */ + __IO uint32_t ED : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< AHB Error Interrupt */ + __IO uint32_t SPD : 1; /*!< SETUP Phase Done, Applies to control endpoints only */ + __IO uint32_t OTRWED : 1; /*!< OUT Token Received when Endpoint Disabled, Applies to control + OUT endpoints only */ + __IO uint32_t SPR : 1; /*!< Status Phase Received */ + __IO uint32_t BTBSPR : 1; /*!< Back-to-Back SETUP Packets Received, Applies to control OUT + endpoints only */ + uint32_t : 1; + __IO uint32_t OPE : 1; /*!< OUT Packet Error */ + __IO uint32_t BNA : 1; /*!< BNA Interrupt */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error interrupt */ + __IO uint32_t NAK : 1; /*!< NAK interrupt */ + __IO uint32_t NYET : 1; /*!< NYET interrupt */ + } DOEPEN_b; /*!< BitSize */ + }; + + union { + __I uint32_t DAINT; /*!< Device All Channels Interrupt Register */ + + struct { + __I uint32_t INT : 16; /*!< IN Endpoint Interrupt Bits, from 0 to 15. */ + __I uint32_t OUT_INT : 16; /*!< OUT Endpoint Interrupt Bits, from 0 to 15. */ + } DAINT_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DAINT_EN; /*!< Device All Channels Interrupt Enable Register */ + + struct { + __IO uint32_t IN_EN : 16; /*!< IN EP Interrupt Enable, from 0 to 15. */ + __IO uint32_t OUT_EN : 16; /*!< OUT EP Interrupt Enable, from 0 to 15. */ + } DAINT_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED42[4]; + + union { + __IO uint32_t DTHRCTL; /*!< Device Threshold Control Register */ + + struct { + __IO uint32_t NISOINETE : 1; /*!< Non-ISO IN Endpoints Threshold Enable */ + __IO uint32_t ISOINETE : 1; /*!< ISO IN Endpoints Threshold Enable */ + __IO uint32_t TTL : 9; /*!< This field specifies Transmit thresholding size in DWORDS */ + __IO uint32_t ATR : 2; /*!< These bits define the ratio between the AHB threshold and the + MAC threshold for the transmit path only. */ + uint32_t : 3; + __IO uint32_t RTE : 1; /*!< If set, the core enables thresholding in the receive direction */ + __IO uint32_t RTL : 9; /*!< This field specifies Receive thresholding size in DWORDS */ + uint32_t : 1; + __IO uint32_t APE : 1; /*!< This bit controls internal DMA arbiter parking for IN endpoints */ + } DTHRCTL_b; /*!< BitSize */ + }; + __IO uint16_t DIEPEMPEN; /*!< Device IN Endpoint FIFO Empty Interrupt Enable Register */ + __I uint16_t RESERVED43[101]; + + union { + __IO uint32_t DIEPCTL0; /*!< Device Control IN Endpoint 0 Control Register */ + + struct { + __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, + applies to IN and OUT endpoints */ + uint32_t : 13; + __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active + in all configurations and interfaces */ + uint32_t : 1; + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ + __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a + SETUP token is received for this endpoint */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + uint32_t : 2; + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED44; + + union { + __IO uint32_t DIEPINT0; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED45; + + union { + __IO uint32_t DIEPTSIZ0; /*!< Device IN Endpoint 0 Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ + uint32_t : 12; + __IO uint32_t PACKET_CNT : 2; /*!< the total number of USB packets */ + } DIEPTSIZ0_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA0; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA0; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED46; + __I uint32_t DIEPDMAB0; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL1; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED47; + + union { + __IO uint32_t DIEPINT1; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED48; + + union { + __IO uint32_t DIEPTSIZ1; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ1_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA1; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA1; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED49; + __I uint32_t DIEPDMAB1; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL2; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED50; + + union { + __IO uint32_t DIEPINT2; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED51; + + union { + __IO uint32_t DIEPTSIZ2; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ2_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA2; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA2; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED52; + __I uint32_t DIEPDMAB2; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL3; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED53; + + union { + __IO uint32_t DIEPINT3; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED54; + + union { + __IO uint32_t DIEPTSIZ3; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ3_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA3; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA3; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED55; + __I uint32_t DIEPDMAB3; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL4; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED56; + + union { + __IO uint32_t DIEPINT4; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED57; + + union { + __IO uint32_t DIEPTSIZ4; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ4_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA4; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA4; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED58; + __I uint32_t DIEPDMAB4; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL5; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED59; + + union { + __IO uint32_t DIEPINT5; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED60; + + union { + __IO uint32_t DIEPTSIZ5; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ5_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA5; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA5; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED61; + __I uint32_t DIEPDMAB5; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL6; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED62; + + union { + __IO uint32_t DIEPINT6; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED63; + + union { + __IO uint32_t DIEPTSIZ6; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ6_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA6; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA6; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED64; + __I uint32_t DIEPDMAB6; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL7; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED65; + + union { + __IO uint32_t DIEPINT7; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED66; + + union { + __IO uint32_t DIEPTSIZ7; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ7_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA7; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA7; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED67; + __I uint32_t DIEPDMAB7; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL8; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED68; + + union { + __IO uint32_t DIEPINT8; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED69; + + union { + __IO uint32_t DIEPTSIZ8; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ8_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA8; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA8; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED70; + __I uint32_t DIEPDMAB8; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL9; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED71; + + union { + __IO uint32_t DIEPINT9; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED72; + + union { + __IO uint32_t DIEPTSIZ9; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ9_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA9; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA9; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED73; + __I uint32_t DIEPDMAB9; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL10; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED74; + + union { + __IO uint32_t DIEPINT10; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED75; + + union { + __IO uint32_t DIEPTSIZ10; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ10_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA10; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA10; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED76; + __I uint32_t DIEPDMAB10; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL11; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED77; + + union { + __IO uint32_t DIEPINT11; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED78; + + union { + __IO uint32_t DIEPTSIZ11; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ11_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA11; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA11; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED79; + __I uint32_t DIEPDMAB11; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL12; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED80; + + union { + __IO uint32_t DIEPINT12; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED81; + + union { + __IO uint32_t DIEPTSIZ12; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ12_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA12; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA12; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED82; + __I uint32_t DIEPDMAB12; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL13; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED83; + + union { + __IO uint32_t DIEPINT13; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED84; + + union { + __IO uint32_t DIEPTSIZ13; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ13_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA13; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA13; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED85; + __I uint32_t DIEPDMAB13; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL14; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED86; + + union { + __IO uint32_t DIEPINT14; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED87; + + union { + __IO uint32_t DIEPTSIZ14; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ14_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA14; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA14; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED88; + __I uint32_t DIEPDMAB14; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DIEPCTL15; /*!< Device IN Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + uint32_t : 1; + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous IN endpoints, stall all tokens. + To control endpoints, response an ACK */ + __IO uint32_t TX_FIFO_NUM: 4; /*!< TxFIFO Number */ + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop transmitting data on an + endpoint even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + transmit is setup */ + } DIEPCTL15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED89; + + union { + __IO uint32_t DIEPINT15; /*!< Device IN Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t TIMEOUT : 1; /*!< a timeout condition on the USB for the last IN token on this + endpoint */ + __IO uint32_t INTRWTFE : 1; /*!< IN Token Received When TxFIFO is Empty */ + __IO uint32_t INTRWEPM : 1; /*!< IN Token Received with EP Mismatch */ + __IO uint32_t INEPNE : 1; /*!< IN Endpoint NAK Effective */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t TFU : 1; /*!< Transmit FIFO Underrun */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DIEPINT15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED90; + + union { + __IO uint32_t DIEPTSIZ15; /*!< Device IN Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t MC : 2; /*!< the number of packets per microframe to periodic IN endpoints. + The number of packets must be fetched per non-periodic IN endpoints */ + } DIEPTSIZ15_b; /*!< BitSize */ + }; + __IO uint32_t DIEPDMA15; /*!< Device IN Endpoint-n DMA Address Register */ + __IO uint16_t DTXFSA15; /*!< Device IN Endpoint-n Transmit FIFO Space Avail Register */ + __I uint16_t RESERVED91; + __I uint32_t DIEPDMAB15; /*!< Device IN Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL0; /*!< Device Control OUT Endpoint 0 Control Register */ + + struct { + __IO uint32_t MPS : 2; /*!< Indicates the maximum packet size of the associated endpoint, + applies to IN and OUT endpoints */ + uint32_t : 13; + __I uint32_t USBAE : 1; /*!< Always 1, indicating that control endpoint 0 is always active + in all configurations and interfaces */ + uint32_t : 1; + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint */ + __I uint32_t EP_TYPE : 2; /*!< Hardcoded to 00 for control */ + __IO uint32_t SNOOP : 1; /*!< does not check if the OUT packets are correct before transferring */ + __IO uint32_t STALL : 1; /*!< The application sets this bit, and the core clears it when a + SETUP token is received for this endpoint */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + uint32_t : 2; + __I uint32_t EPD : 1; /*!< The application cannot disable control OUT endpoint 0 */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED92; + + union { + __IO uint32_t DOEPINT0; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT0_b; /*!< BitSize */ + }; + __I uint32_t RESERVED93; + + union { + __IO uint32_t DOEPTSIZ0; /*!< Device OUT Endpoint 0 Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 7; /*!< Indicates the transfer size in bytes for endpoint 0 */ + uint32_t : 12; + __IO uint32_t PACKET_CNT : 1; /*!< This field is decremented to zero after a packet is written + into the RxFIFO */ + uint32_t : 9; + __IO uint32_t SETUP_CNT : 2; /*!< the number of back-to-back SETUP data packets the endpoint can + receive */ + } DOEPTSIZ0_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA0; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED94; + __I uint32_t DOEPDMAB0; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL1; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED95; + + union { + __IO uint32_t DOEPINT1; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT1_b; /*!< BitSize */ + }; + __I uint32_t RESERVED96; + + union { + __IO uint32_t DOEPTSIZ1; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ1_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA1; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED97; + __I uint32_t DOEPDMAB1; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL2; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED98; + + union { + __IO uint32_t DOEPINT2; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT2_b; /*!< BitSize */ + }; + __I uint32_t RESERVED99; + + union { + __IO uint32_t DOEPTSIZ2; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ2_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA2; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED100; + __I uint32_t DOEPDMAB2; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL3; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED101; + + union { + __IO uint32_t DOEPINT3; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT3_b; /*!< BitSize */ + }; + __I uint32_t RESERVED102; + + union { + __IO uint32_t DOEPTSIZ3; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ3_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA3; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED103; + __I uint32_t DOEPDMAB3; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL4; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED104; + + union { + __IO uint32_t DOEPINT4; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT4_b; /*!< BitSize */ + }; + __I uint32_t RESERVED105; + + union { + __IO uint32_t DOEPTSIZ4; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ4_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA4; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED106; + __I uint32_t DOEPDMAB4; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL5; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED107; + + union { + __IO uint32_t DOEPINT5; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT5_b; /*!< BitSize */ + }; + __I uint32_t RESERVED108; + + union { + __IO uint32_t DOEPTSIZ5; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ5_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA5; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED109; + __I uint32_t DOEPDMAB5; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL6; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED110; + + union { + __IO uint32_t DOEPINT6; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT6_b; /*!< BitSize */ + }; + __I uint32_t RESERVED111; + + union { + __IO uint32_t DOEPTSIZ6; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ6_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA6; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED112; + __I uint32_t DOEPDMAB6; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL7; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED113; + + union { + __IO uint32_t DOEPINT7; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT7_b; /*!< BitSize */ + }; + __I uint32_t RESERVED114; + + union { + __IO uint32_t DOEPTSIZ7; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ7_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA7; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED115; + __I uint32_t DOEPDMAB7; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL8; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED116; + + union { + __IO uint32_t DOEPINT8; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT8_b; /*!< BitSize */ + }; + __I uint32_t RESERVED117; + + union { + __IO uint32_t DOEPTSIZ8; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ8_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA8; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED118; + __I uint32_t DOEPDMAB8; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL9; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED119; + + union { + __IO uint32_t DOEPINT9; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT9_b; /*!< BitSize */ + }; + __I uint32_t RESERVED120; + + union { + __IO uint32_t DOEPTSIZ9; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ9_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA9; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED121; + __I uint32_t DOEPDMAB9; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL10; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED122; + + union { + __IO uint32_t DOEPINT10; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT10_b; /*!< BitSize */ + }; + __I uint32_t RESERVED123; + + union { + __IO uint32_t DOEPTSIZ10; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ10_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA10; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED124; + __I uint32_t DOEPDMAB10; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL11; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED125; + + union { + __IO uint32_t DOEPINT11; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT11_b; /*!< BitSize */ + }; + __I uint32_t RESERVED126; + + union { + __IO uint32_t DOEPTSIZ11; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ11_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA11; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED127; + __I uint32_t DOEPDMAB11; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL12; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED128; + + union { + __IO uint32_t DOEPINT12; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT12_b; /*!< BitSize */ + }; + __I uint32_t RESERVED129; + + union { + __IO uint32_t DOEPTSIZ12; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ12_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA12; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED130; + __I uint32_t DOEPDMAB12; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL13; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED131; + + union { + __IO uint32_t DOEPINT13; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT13_b; /*!< BitSize */ + }; + __I uint32_t RESERVED132; + + union { + __IO uint32_t DOEPTSIZ13; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ13_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA13; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED133; + __I uint32_t DOEPDMAB13; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL14; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED134; + + union { + __IO uint32_t DOEPINT14; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT14_b; /*!< BitSize */ + }; + __I uint32_t RESERVED135; + + union { + __IO uint32_t DOEPTSIZ14; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ14_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA14; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED136; + __I uint32_t DOEPDMAB14; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ + + union { + __IO uint32_t DOEPCTL15; /*!< Device OUT Endpoint N Control Register */ + + struct { + __IO uint32_t MPS : 11; /*!< Indicates the maximum packet size of the associated endpoint */ + uint32_t : 4; + __IO uint32_t UAE : 1; /*!< Indicates whether this endpoint is active */ + __I uint32_t DPID : 1; /*!< Endpoint Data PID */ + __I uint32_t NAK : 1; /*!< The core is transmitting NAK handshakes on this endpoint if + set */ + __IO uint32_t EP_TYPE : 2; /*!< Indicates the transfer type selected. */ + __IO uint32_t EC : 1; /*!< Doesn't check the correctness of OUT packets before transferring */ + __IO uint32_t STALL : 1; /*!< To non-control, non-isochronous OUT endpoints, stall all tokens. + To control endpoints, response an ACK */ + uint32_t : 4; + __O uint32_t CNAK : 1; /*!< A write to this bit clears the NAK bit for the endpoint */ + __O uint32_t SNAK : 1; /*!< A write to this bit sets the NAK bit for the endpoint */ + __O uint32_t SET_D0_PID : 1; /*!< Set DATA0 PID */ + __O uint32_t SET_D1_PID : 1; /*!< Set DATA1 PID */ + __IO uint32_t EPD : 1; /*!< The application sets this bit to stop receiving data on an endpoint + even before the transfer for that endpoint is complete */ + __IO uint32_t EPE : 1; /*!< the descriptor structure and data buffer with data ready to + receive data is setup */ + } DOEPCTL15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED137; + + union { + __IO uint32_t DOEPINT15; /*!< Device OUT Endpoint-n Interrupt Register */ + + struct { + __IO uint32_t TC : 1; /*!< Transfer completed normally without any errors */ + __IO uint32_t EPD : 1; /*!< Endpoint Disabled Interrupt */ + __IO uint32_t AHB_ERR : 1; /*!< there is an AHB error during AHB read/write */ + __IO uint32_t SETUP : 1; /*!< Only for Control OUT endpoints, the SETUP phase for the control + endpoint is complete */ + __IO uint32_t OUTTRWEPD : 1; /*!< OUT Token Received When Endpoint Disabled */ + __IO uint32_t SPRFCW : 1; /*!< Only for Control OUT endpoints, the host has switched from data + phase to the status phase of a Control Write transfer */ + __IO uint32_t B2BSETUPPR : 1; /*!< to Control OUT endpoints only, received more than three back-to-back + SETUP packets for this particular endpoint */ + __I uint32_t TFE : 1; /*!< either half or completely empty depending on GAHBCFG.NPTxFEmpLvl */ + __IO uint32_t OUTPE : 1; /*!< an overflow or a CRC error for an OUT packet */ + __IO uint32_t BNA : 1; /*!< Buffer Not Available */ + uint32_t : 2; + __IO uint32_t BE : 1; /*!< Babble Error */ + __IO uint32_t NAK : 1; /*!< a NAK is transmitted */ + __IO uint32_t NYET : 1; /*!< a NYET response is transmitted */ + } DOEPINT15_b; /*!< BitSize */ + }; + __I uint32_t RESERVED138; + + union { + __IO uint32_t DOEPTSIZ15; /*!< Device OUT Endpoint-n Transfer Size Register */ + + struct { + __IO uint32_t SIZE : 19; /*!< Indicates the transfer size in bytes for endpoint 0 */ + __IO uint32_t PACKET_CNT : 10; /*!< the total number of USB packets */ + __IO uint32_t SETUPCNT_PID: 2; /*!< To control OUT Endpoints only, back-to-back SETUP data packets. + To isochronous OUT endpoints, data PID received in the last + packet */ + } DOEPTSIZ15_b; /*!< BitSize */ + }; + __IO uint32_t DOEPDMA15; /*!< Device OUT Endpoint-n DMA Address Register */ + __I uint32_t RESERVED139; + __I uint32_t DOEPDMAB15; /*!< Device OUT Endpoint-n DMA Buffer Address Register */ +} USB_Type; + + +/* ================================================================================ */ +/* ================ GLOBAL_CTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief GLOBAL_CTRL (GLOBAL_CTRL) + */ + +typedef struct { /*!< GLOBAL_CTRL Structure */ + + union { + __I uint32_t AES_STATUS; /*!< AES status */ + + struct { + __I uint32_t RD_ALMOST_EMPTY: 1; /*!< FIFO read almost empty */ + __I uint32_t RD_EMPTY : 1; /*!< FIFO read empty */ + __I uint32_t WR_FULL_ALMOST: 1; /*!< FIFO write almost full */ + __I uint32_t WR_FULL : 1; /*!< FIFO write full */ + __I uint32_t IDLE : 1; /*!< decryption finish */ + } AES_STATUS_b; /*!< BitSize */ + }; + __I uint32_t RESERVED0[253]; + + union { + __IO uint32_t CLK_SEL_0; /*!< clock select 0 */ + + struct { + __IO uint32_t CAN1_CLK : 2; /*!< CAN1 clock frequency dividor based on system clock, which should + be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t CAN0_CLK : 2; /*!< CAN0 clock frequency dividor based on system clock, which should + be 1/32, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t I2C1_CLK : 2; /*!< I2C1 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t I2C0_CLK : 2; /*!< I2C0 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t SPI1_CLK : 2; /*!< SPI1 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t SPI0_CLK : 2; /*!< SPI0 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t UART1_CLK : 2; /*!< UART1 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t UART0_CLK : 2; /*!< UART0 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t RTC_CLK : 2; /*!< RTC clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t GPIO_CLK : 2; /*!< GPIO clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t TIMER_CLK : 2; /*!< TIMER clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t WDG_CLK : 2; /*!< watchdog clock frequency dividor based on system clock, which + should be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + uint32_t : 2; + __IO uint32_t FLASH_CLK : 2; /*!< FLASH clock frequency dividor based on system clock, which should + be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + __IO uint32_t DMA_AHB_CLK: 2; /*!< DMA AHB bus clock frequency dividor based on system clock, which + should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + __IO uint32_t USB_AHB_CLK: 2; /*!< USB AHB bus clock frequency dividor based on system clock, which + should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + } CLK_SEL_0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CLK_SEL_1; /*!< clock select 1 */ + + struct { + __IO uint32_t ETH_AHB_CLK: 2; /*!< ETH_AHB clock frequency dividor based on system clock, which + should be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + __IO uint32_t DDR_CLK : 2; /*!< DDR clock frequency dividor based on system clock, which should + be 1/1, 1/2, 1/4, 1/8 from 0 to 3 */ + uint32_t : 4; + __IO uint32_t ADC_CLK : 2; /*!< ADC clock frequency dividor based on system clock, which should + be 1/8, 1/16, 1/32, external from 0 to 3 */ + __IO uint32_t EFUSE_CLK : 2; /*!< EFUSE clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t SYS_CLK : 4; /*!< system clock clock frequency dividor based on system clock, + which should be oscillator(0), DLL(1), crystal(2), external(3), + JTAG(4), PS(8) */ + __IO uint32_t UART2_CLK : 2; /*!< UART2 clock frequency dividor based on system clock, which should + be 1/2, 1/4, 1/8, 1/16 from 0 to 3 */ + __IO uint32_t UTMI_CLK : 1; /*!< UTMI clock came from on-chip usb phy(0) or off-chip usb phy(1) */ + } CLK_SEL_1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t USB_PHY_CTRL; /*!< USB Phy Control Register */ + + struct { + __IO uint32_t BITSTUFF : 1; /*!< 0: No bit stuff */ + __IO uint32_t XTLSEL : 1; /*!< 0: 12MHz */ + __IO uint32_t PLL : 1; /*!< PLL mode */ + __IO uint32_t VOLDET : 1; /*!< Voltage Detector Enable, 0: Disable */ + __IO uint32_t IDUP : 1; /*!< 0: ID is uplled up through 33k Ohm resister */ + __IO uint32_t CKISEL : 1; /*!< Clock selection, 0: Crystal, 1: Internal Clock */ + __IO uint32_t FMOD : 1; /*!< 1: Normal */ + __IO uint32_t SQUELCH : 3; /*!< Squelch Reference Voltage, 000: 27.5mV, 001: 137.5mV, 111: 220mV */ + __IO uint32_t HDISCDT : 3; /*!< Host Disconnect Detection Reference Voltage, 000: 500mV, 100: + 588mV, 111: 654mV */ + __IO uint32_t PRTSEL : 1; /*!< 0: Internal OTG PHY, 1: UTMI to External PHY */ + __IO uint32_t RSTPRT : 1; /*!< 0: The reverse of usb_rst_n will reset, 1: Reset OTG PHY */ + } USB_PHY_CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RTC_INT_EN; /*!< RTC interrupt enable Register */ + + struct { + __IO uint32_t SECOND : 1; /*!< 1s interrupt enable */ + __IO uint32_t MILLSECOND : 1; /*!< 1ms interrupt enable */ + } RTC_INT_EN_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1; + + union { + __IO uint32_t NMI_SEL; /*!< nmi interrupt selection */ + + struct { + __IO uint32_t NMI : 7; /*!< NMI interrupt ID */ + } NMI_SEL_b; /*!< BitSize */ + }; + __I uint32_t RESERVED2; + __IO uint32_t AES_TARGET_ADDR; /*!< AES target address, default is frame decoder address(0x41800000) */ + + union { + __IO uint32_t AES_BURST_TYPE; /*!< AES burst type */ + + struct { + __IO uint32_t TYPE : 2; /*!< burst type, fixed(0), incr(1) */ + } AES_BURST_TYPE_b; /*!< BitSize */ + }; + __I uint32_t RESERVED3[3]; + + union { + __IO uint32_t ICACHE; /*!< ICACHE Enable */ + + struct { + __IO uint32_t EN : 1; /*!< ICACHE Enable */ + } ICACHE_b; /*!< BitSize */ + }; + __IO uint32_t IBUSOFF; /*!< Code Bus Offset */ + __IO uint32_t DBUSOFF; /*!< Data Bus Offset */ + __IO uint32_t EXTADDR; /*!< Bus Ext Addr */ +} GLOBAL_CTRL_Type; + + +/* ================================================================================ */ +/* ================ AES ================ */ +/* ================================================================================ */ + + +/** + * @brief AES (AES) + */ + +typedef struct { /*!< AES Structure */ + __IO uint32_t FIFO; /*!< data FIFO to be decoded */ + + union { + __O uint32_t FIFO_CLEAR; /*!< clear data FIFO */ + + struct { + __O uint32_t CLEAR : 1; /*!< clear after write 1 and write 0 */ + } FIFO_CLEAR_b; /*!< BitSize */ + }; +} AES_Type; + + +/* ================================================================================ */ +/* ================ DDRC ================ */ +/* ================================================================================ */ + + +/** + * @brief DDR_CFG (DDRC) + */ + +typedef struct { /*!< DDRC Structure */ + __IO uint32_t CMD; /*!< DDR commands to program */ + + union { + __IO uint32_t CTRL; /*!< DDR Control */ + + struct { + __IO uint32_t TO : 1; /*!< Take over DDRC siggen */ + __IO uint32_t CLR : 1; /*!< Clear commands in FIFO */ + __O uint32_t STR : 1; /*!< Start to execute the commands in FIFO */ + } CTRL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t MODE; /*!< DDR mode */ + + struct { + __IO uint32_t MODE : 6; /*!< DDRC Mode */ + uint32_t : 2; + __IO uint32_t LANE : 1; /*!< LANE synchronization logic bypass */ + uint32_t : 3; + __IO uint32_t ADEC : 1; /*!< address decoder mapping */ + uint32_t : 3; + __IO uint32_t B16 : 2; /*!< Active 16 bit DQ position when the unmber of DQ IO is 16 */ + uint32_t : 6; + __IO uint32_t CLKPOL : 2; /*!< DQS clkpol set by user on the PHY */ + } MODE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t QUE; /*!< DDRC queue depth */ + + struct { + __IO uint32_t DEPTH : 1; /*!< DDRC queue depth */ + } QUE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t REF; /*!< Refresh control */ + + struct { + __IO uint32_t THRD : 5; /*!< Number of refresh requests which can be postponed */ + uint32_t : 3; + __IO uint32_t TRIG : 4; /*!< Number of refresh requests every dl_refi */ + uint32_t : 4; + __IO uint32_t TIME : 16; /*!< Refresh interval time */ + } REF_b; /*!< BitSize */ + }; + + union { + __O uint32_t REF_TRIG; /*!< Refresh trigger */ + + struct { + __O uint32_t GO : 1; /*!< Write 1 to trigger one refresh request by cbus */ + } REF_TRIG_b; /*!< BitSize */ + }; + + union { + __O uint32_t ZQ_TRIG; /*!< ZQCTL trigger */ + + struct { + __O uint32_t CS : 1; /*!< Write 1 to trigger one ZQCS request by cbus */ + __O uint32_t CL : 1; /*!< Write 1 to trigger one ZQCL request by cbus */ + } ZQ_TRIG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ZQCSR; /*!< ZQCSR */ + + struct { + __IO uint32_t EN : 1; /*!< Enable ZQCS request */ + __IO uint32_t PRI : 1; /*!< 0: DMA access prior to ZQCS, 1: ZQCS prior to DMA access */ + } ZQCSR_b; /*!< BitSize */ + }; + __IO uint32_t ZQCSI; /*!< ZQCS interval time */ + + union { + __IO uint32_t RCD; /*!< t(RCD) */ + + struct { + __IO uint32_t DI : 5; /*!< t(RCD), delay from ACT command to RW command of same bank */ + } RCD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RAS; /*!< t(RAS) */ + + struct { + __IO uint32_t DI : 6; /*!< t(RAS), delay from ACT command to PRE command of same bank */ + } RAS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RP; /*!< t(RP) */ + + struct { + __IO uint32_t DI : 5; /*!< t(RP), delay from PRE command to ACT/REF/ZQ command */ + uint32_t : 3; + __IO uint32_t RPA : 1; /*!< 0: t(RP) delay for PREA command; 1: t(RP)+1 delay for PREA command */ + } RP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RC; /*!< t(RC) */ + + struct { + __IO uint32_t DI : 7; /*!< t(RC), delay from ACT command to ACT command of same bank */ + } RC_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RRD; /*!< t(RRD) */ + + struct { + __IO uint32_t DI : 4; /*!< t(RRD), delay from ACT command to ACT command */ + } RRD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t CCD; /*!< t(CCD) */ + + struct { + __IO uint32_t DI : 3; /*!< t(CCD), delay from RW command to RW command */ + } CCD_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RTW; /*!< t(RTW) */ + + struct { + __IO uint32_t DI : 5; /*!< t(RTW), delay from RD command to WR command */ + } RTW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WTR; /*!< t(WTR) */ + + struct { + __IO uint32_t DI : 5; /*!< t(WTR), delay from WR command to RD command */ + } WTR_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RTP; /*!< t(RTP) */ + + struct { + __IO uint32_t DI : 3; /*!< t(RTP), delay from RD command to PRE command of same bank */ + } RTP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WTP; /*!< t(WTP) */ + + struct { + __IO uint32_t DI : 6; /*!< t(WTP), delay from WR command to PRE command of same bank */ + } WTP_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RFC; /*!< t(RFC) */ + + struct { + __IO uint32_t DI : 8; /*!< t(WTP), delay from WR command to PRE command of same bank */ + } RFC_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ZQCL; /*!< t(ZQoper) */ + + struct { + __IO uint32_t DI : 9; /*!< t(ZQoper), delay from ZQCL command to REF/ZQ/ACT command */ + } ZQCL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ZQCS; /*!< t(ZQCS) */ + + struct { + __IO uint32_t DI : 7; /*!< t(ZQCS), delay from ZQCS command to REF/ZQ/ACT command */ + } ZQCS_b; /*!< BitSize */ + }; + + union { + __IO uint32_t FAW; /*!< t(FAW) */ + + struct { + __IO uint32_t DI : 6; /*!< t(FAW), 4 act command window time */ + } FAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t BURST; /*!< BURST */ + + struct { + __IO uint32_t LEN : 1; /*!< 0: length 8, 1: length 4 */ + } BURST_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PHUNG; /*!< PHUNG */ + + struct { + __IO uint32_t MODE : 1; /*!< 0: normal mode, 1: prevent read hang mode */ + __IO uint32_t LPM : 1; /*!< 1: stop the IO clk */ + } PHUNG_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RL; /*!< READ Latency */ + + struct { + __IO uint32_t VAL : 5; /*!< READ Latency */ + } RL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t WL; /*!< WRITE Latency */ + + struct { + __IO uint32_t VAL : 5; /*!< WRITE Latency */ + } WL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TRAIN; /*!< TRAIN */ + + struct { + __IO uint32_t EN : 4; /*!< Enable lane N training mode */ + } TRAIN_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN0; /*!< Delay cycles of dqsen of byte lane 0 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 0 */ + } DQSEN0_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN1; /*!< Delay cycles of dqsen of byte lane 1 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 1 */ + } DQSEN1_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN2; /*!< Delay cycles of dqsen of byte lane 2 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 2 */ + } DQSEN2_b; /*!< BitSize */ + }; + + union { + __IO uint32_t DQSEN3; /*!< Delay cycles of dqsen of byte lane 0 */ + + struct { + __IO uint32_t DL : 3; /*!< Delay cycles of dqsen of byte lane 3 */ + } DQSEN3_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ODTH; /*!< Delay from WR command to odt high transition */ + + struct { + __IO uint32_t DL : 5; /*!< Delay from WR command to odt high transition */ + } ODTH_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ODTL; /*!< Delay from WR command to odt low transition */ + + struct { + __IO uint32_t DL : 5; /*!< Delay from WR command to odt low transition */ + } ODTL_b; /*!< BitSize */ + }; + + union { + __O uint32_t ODT; /*!< Used in write leveling mode */ + + struct { + __O uint32_t TRIG : 1; /*!< 0: trigger odt low, 1: trigger odt high */ + } ODT_b; /*!< BitSize */ + }; + + union { + __O uint32_t DQS; /*!< Used in write leveling mode */ + + struct { + __O uint32_t TRIG : 1; /*!< Writing 1 to this register triggers a dqs pulse */ + } DQS_b; /*!< BitSize */ + }; + + union { + __I uint32_t STA; /*!< Commands FIFO */ + + struct { + __I uint32_t MODE : 1; /*!< DDRC in sw_proc mode */ + __I uint32_t EMPTY : 1; /*!< Sw_proc command fifo empty */ + __I uint32_t FULL : 1; /*!< Sw_proc command fifo full */ + } STA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INTCTL; /*!< Interrupt Control */ + + struct { + __IO uint32_t DONE : 1; /*!< 0: the sw_proc_done int will not be masked, 1: the sw_proc_done + int will be masked */ + __IO uint32_t ERR : 1; /*!< mask of the lane_sync_error interrupt */ + uint32_t : 14; + __IO uint32_t MODE : 1; /*!< Interrupt mode: 0: int level active, write 1 to clear; 1: int + edge active */ + } INTCTL_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INTRAW; /*!< Interrupt RAW */ + + struct { + __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done before mask */ + __IO uint32_t ERR : 1; /*!< int reg of the lane sync error before masked */ + } INTRAW_b; /*!< BitSize */ + }; + + union { + __IO uint32_t INTSTA; /*!< Interrupt STA */ + + struct { + __IO uint32_t DONE : 1; /*!< Int register of sw_proc_done after mask */ + __IO uint32_t ERR : 1; /*!< int register of lane sync error after masked */ + } INTSTA_b; /*!< BitSize */ + }; + + union { + __IO uint32_t PHY; /*!< PHY */ + + struct { + __IO uint32_t RST : 1; /*!< FPGA version, reset read dq fifo. Low active */ + } PHY_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RDQ; /*!< FPGA version, read dq delay of byte lane N */ + + struct { + __IO uint32_t L3 : 6; /*!< FPGA version, read dq delay of byte lane3 */ + uint32_t : 2; + __IO uint32_t L2 : 6; /*!< FPGA version, read dq delay of byte lane2 */ + uint32_t : 2; + __IO uint32_t L1 : 6; /*!< FPGA version, read dq delay of byte lane3 */ + uint32_t : 2; + __IO uint32_t L0 : 7; /*!< FPGA version, read dq delay of byte lane0 */ + } RDQ_b; /*!< BitSize */ + }; + + union { + __I uint32_t CALIB; /*!< calibration */ + + struct { + __I uint32_t TPU : 8; /*!< calibration result values, if fail then 0x40 */ + __I uint32_t TPD : 8; /*!< calibration result values, if fail then 0x40 */ + __I uint32_t PDR : 5; /*!< calibration result values, if fail then 0x40 */ + __I uint32_t NDR : 5; /*!< calibration result values, if fail then 0x40 */ + uint32_t : 5; + __IO uint32_t EN : 1; /*!< trigger the calibration processing which is sensitive to the + positive edge */ + } CALIB_b; /*!< BitSize */ + }; + + union { + __IO uint32_t ITMDLY; /*!< "itmdly" is the fine delay trim to the read path "dq", "itmsdly" + is to the read path of "dqs". From 000 to 111 increasingly, + each step is about 40ps */ + + struct { + __IO uint32_t I0 : 4; /*!< itmdly0 */ + __IO uint32_t IS0 : 4; /*!< itmsdly0 */ + __IO uint32_t I1 : 4; /*!< itmdly1 */ + __IO uint32_t IS1 : 4; /*!< itmsdly1 */ + __IO uint32_t I2 : 4; /*!< itmdly2 */ + __IO uint32_t IS2 : 4; /*!< itmsdly2 */ + __IO uint32_t I3 : 4; /*!< itmdly3 */ + __IO uint32_t IS3 : 4; /*!< itmsdly3 */ + } ITMDLY_b; /*!< BitSize */ + }; + + union { + __IO uint32_t TUNE; /*!< CALIB_TUNE */ + + struct { + __IO uint32_t TPU : 4; /*!< tpu_tune, finial val = tune[3] ? val - tune : val + tune */ + __IO uint32_t TPD : 4; /*!< tpd_tune, tune[3:0] for TPD/TPU, [2:0] is the tune val */ + __IO uint32_t PDR : 4; /*!< pdr_tune, inial val = tune[2] ? val - tune : val + tune */ + __IO uint32_t NDR : 4; /*!< ndr_tune, tune[2:0] for NDR/PDR, [1:0] is the tune val */ + } TUNE_b; /*!< BitSize */ + }; + + union { + __IO uint32_t RD_SEL; /*!< RD_WINDOWS_SEL */ + + struct { + __IO uint32_t PHY_SEL : 3; /*!< To fix the phy read valid issue, this is to adjust the read + data valid window to match the phy read valid by cycle level */ + } RD_SEL_b; /*!< BitSize */ + }; +} DDRC_Type; + + +/* ================================================================================ */ +/* ================ PDLOCK ================ */ +/* ================================================================================ */ + + +/** + * @brief PLL DLL LOCK (PDLOCK) + */ + +typedef struct { /*!< PDLOCK Structure */ + + union { + __I uint32_t GCLK; /*!< GCLK */ + + struct { + __I uint32_t C1R2P : 1; /*!< gclk_c1r2_pll_lock */ + __I uint32_t C1R1P : 1; /*!< gclk_c1r1_pll_lock */ + __I uint32_t C2R1P : 1; /*!< gclk_c2r1_pll_lock */ + __I uint32_t C2R2P : 1; /*!< gclk_c2r2_pll_lock */ + __I uint32_t C1R2D : 1; /*!< gclk_c1r2_dll_lock */ + __I uint32_t C1R1D : 1; /*!< gclk_c1r1_dll_lock */ + __I uint32_t C2R1D : 1; /*!< gclk_c2r1_dll_lock */ + __I uint32_t C2R2D : 1; /*!< gclk_c2r2_dll_lock */ + } GCLK_b; /*!< BitSize */ + }; +} PDLOCK_Type; + + +/* ================================================================================ */ +/* ================ PDPROT ================ */ +/* ================================================================================ */ + + +/** + * @brief PLL DLL PROTECT (PDPROT) + */ + +typedef struct { /*!< PDPROT Structure */ + + union { + __O uint32_t LOCK; /*!< LOCK */ + + struct { + __O uint32_t EN : 1; /*!< Enable the PLL DLL Lock to Protect it */ + } LOCK_b; /*!< BitSize */ + }; +} PDPROT_Type; + + +/* ================================================================================ */ +/* ================ CFG_CTRL ================ */ +/* ================================================================================ */ + + +/** + * @brief CFG_CTRL (CFG_CTRL) + */ + +typedef struct { /*!< CFG_CTRL Structure */ + __I uint32_t RESERVED0[3]; + + union { + __IO uint32_t DONE; /*!< DONE CFG */ + + struct { + __IO uint32_t CMD : 1; /*!< Write 1 indicate all chain data write over */ + __IO uint32_t STA : 1; /*!< 1= all chain config process over, chip is in user mode */ + } DONE_b; /*!< BitSize */ + }; + __I uint32_t RESERVED1[34]; + + union { + __IO uint32_t PDLLSTR; /*!< PLL DLL RESET */ + + struct { + __IO uint32_t C1R1P : 1; /*!< C1r1_rstpll_n, low active */ + __IO uint32_t C1R2P : 1; /*!< C1r2_rstpll_n, low active */ + __IO uint32_t C2R1P : 1; /*!< C2r1_rstpll_n, low active */ + __IO uint32_t C2R2P : 1; /*!< C2r2_rstpll_n, low active */ + __IO uint32_t C1R1D : 1; /*!< C1r1_rstdll_n, low active */ + __IO uint32_t C1R2D : 1; /*!< C1r2_rstdll_n, low active */ + __IO uint32_t C2R1D : 1; /*!< C2r1_rstdll_n, low active */ + __IO uint32_t C2R2D : 1; /*!< C2r2_rstdll_n, low active */ + } PDLLSTR_b; /*!< BitSize */ + }; +} CFG_CTRL_Type; + + +/* ================================================================================ */ +/* ================ SOFT_RESET ================ */ +/* ================================================================================ */ + + +/** + * @brief SUB SOFT RESET (SOFT_RESET) + */ + +typedef struct { /*!< SOFT_RESET Structure */ + + union { + __IO uint32_t SOFTRST; /*!< SOFTRST */ + + struct { + __IO uint32_t CAN1_n : 1; /*!< soft_rst_can1_n */ + __IO uint32_t CAN0_n : 1; /*!< soft_rst_can0_n */ + __IO uint32_t I2C1_n : 1; /*!< soft_rst_i2c1_n */ + __IO uint32_t I2C0_n : 1; /*!< soft_rst_i2c0_n */ + __IO uint32_t SPI1_n : 1; /*!< soft_rst_spi1_n */ + __IO uint32_t SPI0_n : 1; /*!< soft_rst_spi0_n */ + __IO uint32_t UART1_n : 1; /*!< soft_rst_uart1_n */ + __IO uint32_t UART0_n : 1; /*!< soft_rst_uart0_n */ + __IO uint32_t RTC_n : 1; /*!< soft_rst_rtc_n */ + __IO uint32_t GPIO_n : 1; /*!< soft_rst_gpio_n */ + __IO uint32_t TIMER_n : 1; /*!< soft_rst_timer_n */ + __IO uint32_t WDT_n : 1; /*!< soft_rst_wdt_n */ + __IO uint32_t LVDS_n : 1; /*!< soft_rst_lvds_n */ + __IO uint32_t FLS_n : 1; /*!< soft_rst_fls_n */ + __IO uint32_t DMAC_AHB_n : 1; /*!< soft_rst_dmac_ahb_n */ + __IO uint32_t USB_AHB_n : 1; /*!< soft_rst_usb_ahb_n */ + __IO uint32_t ETH_AHB_n : 1; /*!< soft_rst_eth_ahb_n */ + __IO uint32_t DDRC_n : 1; /*!< soft_rst_ddrc_n */ + __IO uint32_t ARM_HCLK_n : 1; /*!< soft_rst_arm_HCLK_n */ + __IO uint32_t _48_n : 1; /*!< soft_rst_48_n */ + __IO uint32_t UTM_n : 1; /*!< soft_rst_utmi_n */ + __IO uint32_t CACHE_n : 1; /*!< soft_rst_cache_n */ + __IO uint32_t USB_n : 1; /*!< soft_rst_cache_n */ + __IO uint32_t ETH_RX_n : 1; /*!< soft_rst_eth_rx_i_n */ + __IO uint32_t ETH_TX_n : 1; /*!< soft_rst_eth_tx_i_n */ + __IO uint32_t ADC_n : 1; /*!< soft_rst_adc_n */ + __IO uint32_t EFUSE_n : 1; /*!< soft_rst_efuse_n */ + __IO uint32_t Reserved1_n: 1; /*!< Reserved11 */ + __IO uint32_t AES_n : 1; /*!< soft_rst_aes_n */ + __IO uint32_t UART2_n : 1; /*!< soft_rst_uart2_n */ + __IO uint32_t AS_n : 1; /*!< soft_rst_as_n */ + __IO uint32_t FDCD_n : 1; /*!< soft_rst_fdcd_n */ + } SOFTRST_b; /*!< BitSize */ + }; +} SOFT_RESET_Type; + + +/* -------------------- End of section using anonymous unions ------------------- */ +#if defined(__CC_ARM) + #pragma pop +#elif defined(__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined(__TASKING__) + #pragma warning restore +#else + #warning Not supported compiler type +#endif + + + + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define UART0_BASE 0x41005000UL +#define UART1_BASE 0x4100C000UL +#define UART2_BASE 0x4100E000UL +#define WDG_BASE 0x41001000UL +#define TIMER0_BASE 0x41000000UL +#define TIMER1_BASE 0x41000020UL +#define TIMER2_BASE 0x41000040UL +#define TIMER3_BASE 0x41000060UL +#define SPI0_BASE 0x41004000UL +#define SPI1_BASE 0x4100B000UL +#define I2C0_BASE 0x41003000UL +#define I2C1_BASE 0x4100A000UL +#define RTC_BASE 0x41007004UL +#define GPIO_BASE 0x41002000UL +#define NOR_FLASH_BASE 0x40800000UL +#define ADC_BASE 0x41006000UL +#define EFUSE_BASE 0x41008000UL +#define CAN0_BASE 0x41009000UL +#define CAN1_BASE 0x4100D000UL +#define DMA_BASE 0x41500000UL +#define ETH_BASE 0x41200000UL +#define USB_BASE 0x41300000UL +#define GLOBAL_CTRL_BASE 0x41007010UL +#define AES_BASE 0x41600000UL +#define DDRC_BASE 0x41400000UL +#define PDLOCK_BASE 0x41007000UL +#define PDPROT_BASE 0x41007C00UL +#define CFG_CTRL_BASE 0x41700000UL +#define SOFT_RESET_BASE 0x41007400UL + + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define UART0 ((UART0_Type *) UART0_BASE) +#define UART1 ((UART0_Type *) UART1_BASE) +#define UART2 ((UART0_Type *) UART2_BASE) +#define WDG ((WDG_Type *) WDG_BASE) +#define TIMER0 ((TIMER0_Type *) TIMER0_BASE) +#define TIMER1 ((TIMER0_Type *) TIMER1_BASE) +#define TIMER2 ((TIMER0_Type *) TIMER2_BASE) +#define TIMER3 ((TIMER0_Type *) TIMER3_BASE) +#define SPI0 ((SPI0_Type *) SPI0_BASE) +#define SPI1 ((SPI0_Type *) SPI1_BASE) +#define I2C0 ((I2C0_Type *) I2C0_BASE) +#define I2C1 ((I2C0_Type *) I2C1_BASE) +#define RTC ((RTC_Type *) RTC_BASE) +#define GPIO ((GPIO_Type *) GPIO_BASE) +#define NOR_FLASH ((NOR_FLASH_Type *) NOR_FLASH_BASE) +#define ADC ((ADC_Type *) ADC_BASE) +#define EFUSE ((EFUSE_Type *) EFUSE_BASE) +#define CAN0 ((CAN0_Type *) CAN0_BASE) +#define CAN1 ((CAN0_Type *) CAN1_BASE) +#define DMA ((DMA_Type *) DMA_BASE) +#define ETH ((ETH_Type *) ETH_BASE) +#define USB ((USB_Type *) USB_BASE) +#define GLOBAL_CTRL ((GLOBAL_CTRL_Type *) GLOBAL_CTRL_BASE) +#define AES ((AES_Type *) AES_BASE) +#define DDRC ((DDRC_Type *) DDRC_BASE) +#define PDLOCK ((PDLOCK_Type *) PDLOCK_BASE) +#define PDPROT ((PDPROT_Type *) PDPROT_BASE) +#define CFG_CTRL ((CFG_CTRL_Type *) CFG_CTRL_BASE) +#define SOFT_RESET ((SOFT_RESET_Type *) SOFT_RESET_BASE) + + +/** @} */ /* End of group Device_Peripheral_Registers */ +/** @} */ /* End of group cmem7 */ +/** @} */ /* End of group (null) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* cmem7_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h index 28088028b2..f6a2757476 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_conf.h @@ -43,12 +43,12 @@ #define _TIM #define _UART #define _USB -#define _WDG +#define _WDG -//#define _MARVELL -//#define _IP1826D -#define _M7NORFLASH -#define _ME_6095_F +//#define _MARVELL +//#define _IP1826D +#define _M7NORFLASH +#define _ME_6095_F #define USE_FULL_ASSERT 1 @@ -76,8 +76,8 @@ typedef enum _BOOL {FALSE = 0, TRUE = 1} BOOL; /** * System clock frequency, unit is Hz. */ -#define SYSTEM_CLOCK_FREQ 300000000 -//250000000 +#define SYSTEM_CLOCK_FREQ 300000000 +//250000000 //300000000 /** diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h index a5663ea869..4edeca9205 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_eth.h @@ -1,417 +1,417 @@ -/** - ***************************************************************************** - * @file cmem7_eth.h - * - * @brief CMEM7 ethernet header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_ETH_H -#define __CMEM7_ETH_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** @defgroup ETH_SPEED - * @{ - */ -#define ETH_SPEED_10M 0x0 -#define ETH_SPEED_100M 0x1 -#define ETH_SPEED_1000M 0x2 - -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M) || \ - ((SPEED) == ETH_SPEED_1000M)) -/** - * @} - */ - -/** @defgroup ETH_DUPLEX - * @{ - */ -#define ETH_DUPLEX_HALF 0x0 -#define ETH_DUPLEX_FULL 0x1 - -#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \ - ((DUPLEX) == ETH_DUPLEX_FULL)) -/** - * @} - */ - -/** @defgroup ETH_INT - * @{ - */ -#define ETH_INT_TX_COMPLETE_FRAME 0x0001 -#define ETH_INT_TX_STOP 0x0002 -#define ETH_INT_TX_BUF_UNAVAI 0x0004 -#define ETH_INT_RX_OVERFLOW 0x0010 -#define ETH_INT_TX_UNDERFLOW 0x0020 -#define ETH_INT_RX_COMPLETE_FRAME 0x0040 -#define ETH_INT_RX_BUF_UNAVAI 0x0080 -#define ETH_INT_RX_STOP 0x0100 -#define ETH_INT_BUS_FATAL_ERROR 0x2000 -#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \ - ETH_INT_TX_STOP | \ - ETH_INT_TX_BUF_UNAVAI | \ - ETH_INT_RX_OVERFLOW | \ - ETH_INT_TX_UNDERFLOW | \ - ETH_INT_RX_COMPLETE_FRAME | \ - ETH_INT_RX_BUF_UNAVAI | \ - ETH_INT_RX_STOP | \ - ETH_INT_BUS_FATAL_ERROR) - -#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0)) -/** - * @} - */ -/** - * @brief EFUSE receive filter structure - */ -typedef struct -{ - BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */ - BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */ - BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */ - BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */ - BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */ - uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */ -} ETH_FrameFilter; - -/** - * @brief Ethernet initialization structure - */ -typedef struct -{ - BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */ - uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */ - uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */ - BOOL ETH_RxEn; /*!< Rx enable */ - BOOL ETH_TxEn; /*!< Tx enable */ - BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */ - BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */ - uint8_t ETH_MacAddr[6]; /*!< MAC address */ - ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */ -} ETH_InitTypeDef; - -/** - * @brief Ethernet Tx descriptor structure - */ -typedef struct { - union { - uint32_t TX0; - - struct { - uint32_t : 1; - uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */ - uint32_t : 1; - uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */ - uint32_t : 1; - uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */ - uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */ - uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */ - uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */ - uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */ - uint32_t : 2; - uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */ - uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */ - uint32_t : 8; - uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */ - uint32_t : 2; - uint32_t FS : 1; /*!< first segment flag */ - uint32_t LS : 1; /*!< last segment flag */ - uint32_t : 2; - } TX0_b; - } TX_0; - - union { - uint32_t TX1; - - struct { - uint32_t SIZE : 13; /*!< buffer size */ - uint32_t : 19; - } TX1_b; - } TX_1; - - uint32_t bufAddr; /*!< address of buffer */ - uint32_t nextDescAddr; /*!< address of next descriptor */ - uint64_t reserved; - uint64_t timeStamp; /*!< time stamp while last segment */ -} ETH_TX_DESC; - -/** - * @brief Ethernet Rx descriptor structure - */ -typedef struct { - union { - uint32_t RX0; - - struct { - uint32_t : 1; - uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */ - uint32_t : 5; - uint32_t TTSE : 1; /*!< timestamp available while last segment */ - uint32_t LS : 1; /*!< [OUT] last segment flag */ - uint32_t FS : 1; /*!< [OUT] first segment flag */ - uint32_t : 1; - uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */ - uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */ - uint32_t : 2; - uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */ - uint32_t FL : 14; /*!< [OUT] frame length while last segment */ - uint32_t : 2; - } RX0_b; - } RX_0; - - union { - uint32_t RX1; - - struct { - uint32_t SIZE : 13; /*!< buffer size */ - uint32_t : 19; - } RX1_b; - } RX_1; - - uint32_t bufAddr; /*!< buffer address */ - uint32_t nextDescAddr; /*!< address of next descriptor */ - uint64_t reserved; - uint64_t timeStamp; /*!< time stamp while the last segment */ -} ETH_RX_DESC; - -/** - * @brief Read data from phy chip - * @param[in] phyAddr Address of phy chip - * @param[in] phyReg Address of phy's register to be read - * @retval uint32_t value of phy's register - */ -uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg); - -/** - * @brief Write data to phy chip - * @param[in] phyAddr Address of phy chip - * @param[in] phyReg Address of phy's register to be written - * @param[in] data Data to be written - * @retval None - */ -void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data); -/** - * @brief Fills each ETH_InitStruct member with its default value. - * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure - * which will be initialized. - * @retval : None - */ -void ETH_StructInit(ETH_InitTypeDef* init); -/** - * @brief Ethernet initialization - * @note This function should be called at first before any other interfaces. - * @param[in] init A pointer to structure ETH_InitTypeDef - * @retval BOOL The bit indicates if ethernet is initialized successfully - */ -BOOL ETH_Init(ETH_InitTypeDef *init); - -/** - * @brief Enable or disable ethernet interrupt. - * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT - * @param[in] Enable The bit indicates if specific interrupts are enable or not - * @retval None - */ -void ETH_ITConfig(uint32_t Int, BOOL enable); - -/** - * @brief Check specific interrupts are set or not - * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT - * @retval BOOL The bit indicates if specific interrupts are set or not - */ -BOOL ETH_GetITStatus(uint32_t Int); - -/** - * @brief Clear specific interrupts - * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT - * @retval None - */ -void ETH_ClearITPendingBit(uint32_t Int); - -/** - * @brief Get ethernte MAC address - * @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes. - * @retval None - */ -void ETH_GetMacAddr(uint8_t *mac); - -/** - * @brief Set ethernet transmission descriptor ring - * @note Make sure that memory occupied by descriptors should be in physical - * memory and keep valid before ethernet transmission is finished. - * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node - * has a 'nextDescAddr' pointed to first node. - * @retval BOOL The bit indicates if valid ring is set - */ -BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring); - -/** - * @brief Start ethernet transmission - * @param None - * @retval None - */ -void ETH_StartTx(void); - -/** - * @brief Stop ethernet transmission - * @param None - * @retval None - */ -void ETH_StopTx(void); - -/** - * @brief Resume ethernet transmission\n - * While ethernet doesn't have enough buffer to transmit data, it will - * pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users - * must call this function to start ethernet again after new buffer - * prepared. - * @param None - * @retval None - */ -void ETH_ResumeTx(void); - -/** - * @brief Get free transmission descriptor\n - * @param None - * @retval ETH_TX_DESC* A pointer of free transmission descriptor, - * NULL if no free descriptor - */ -ETH_TX_DESC *ETH_AcquireFreeTxDesc(void); - -/** - * @brief Check if a transmission descriptor is free or not - * @param[in] desc A pointer of a transmission descriptor - * @retval BOOL True if the transmission descriptor is free, or flase. - */ -BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc); - -/** - * @brief Release a transmission descriptor to ethernet\n - * After users prepared data in the buffer of a free descriptor, - * They must call this function to change ownership of the - * descriptor to hardware. - * @param[in] desc A pointer of a transmission descriptor - * @retval None - */ -void ETH_ReleaseTxDesc(ETH_TX_DESC *desc); - -/** - * @brief Set buffer address of the specific TX descriptor - * @param[in] desc A pointer of a transmission descriptor - * @param[in] bufAddr buffer address to be sent - * @retval None - */ -void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr); - -/** - * @brief Get buffer address of the specific TX descriptor - * @param[in] desc A pointer of a transmission descriptor - * @retval uint32_t buffer address to be gotten - */ -uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc); - -/** - * @brief Set ethernet receive descriptor ring - * @note Make sure that memory occupied by descriptors should be in physical - * memory and keep valid before ethernet receive is finished. - * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node - * has a 'nextDescAddr' pointed to first node. - * @retval BOOL The bit indicates if valid ring is set - */ -BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring); - -/** - * @brief Start ethernet receive - * @param None - * @retval None - */ -void ETH_StartRx(void); - -/** - * @brief Stop ethernet receive - * @param None - * @retval None - */ -void ETH_StopRx(void); - -/** - * @brief Resume ethernet receive\n - * While ethernet doesn't have enough buffer to receive data, it will - * pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users - * must call this function to start ethernet again after new buffer - * prepared. - * @param None - * @retval None - */ -void ETH_ResumeRx(void); - -/** - * @brief Get the free descriptor which contains received data\n - * @param None - * @retval ETH_RX_DESC* A pointer of free receive descriptor, - * NULL if no free descriptor - */ -ETH_RX_DESC *ETH_AcquireFreeRxDesc(void); - -/** - * @brief Check if a receive descriptor is free or not - * @param[in] desc A pointer of a receive descriptor - * @retval BOOL True if the receive descriptor is free, or flase. - */ -BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc); - -/** - * @brief Release a receive descriptor to ethernet\n - * After users handled data in the buffer of a free descriptor, - * They must call this function to change ownership of the - * descriptor to hardware. - * @param[in] desc A pointer of a transmission descriptor - * @retval None - */ -void ETH_ReleaseRxDesc(ETH_RX_DESC *desc); - -/** - * @brief Set buffer address of the specific RX descriptor - * @param[in] desc A pointer of a receive descriptor - * @param[in] bufAddr buffer address to be received - * @retval None - */ -void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr); - -/** - * @brief Get buffer address of the specific RX descriptor - * @param[in] desc A pointer of a receive descriptor - * @retval uint32_t buffer address to be gotten - */ -uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc); - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_ETH_H */ - +/** + ***************************************************************************** + * @file cmem7_eth.h + * + * @brief CMEM7 ethernet header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_ETH_H +#define __CMEM7_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** @defgroup ETH_SPEED + * @{ + */ +#define ETH_SPEED_10M 0x0 +#define ETH_SPEED_100M 0x1 +#define ETH_SPEED_1000M 0x2 + +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ + ((SPEED) == ETH_SPEED_100M) || \ + ((SPEED) == ETH_SPEED_1000M)) +/** + * @} + */ + +/** @defgroup ETH_DUPLEX + * @{ + */ +#define ETH_DUPLEX_HALF 0x0 +#define ETH_DUPLEX_FULL 0x1 + +#define IS_ETH_DUPLEX(DUPLEX) (((DUPLEX) == ETH_DUPLEX_HALF) || \ + ((DUPLEX) == ETH_DUPLEX_FULL)) +/** + * @} + */ + +/** @defgroup ETH_INT + * @{ + */ +#define ETH_INT_TX_COMPLETE_FRAME 0x0001 +#define ETH_INT_TX_STOP 0x0002 +#define ETH_INT_TX_BUF_UNAVAI 0x0004 +#define ETH_INT_RX_OVERFLOW 0x0010 +#define ETH_INT_TX_UNDERFLOW 0x0020 +#define ETH_INT_RX_COMPLETE_FRAME 0x0040 +#define ETH_INT_RX_BUF_UNAVAI 0x0080 +#define ETH_INT_RX_STOP 0x0100 +#define ETH_INT_BUS_FATAL_ERROR 0x2000 +#define ETH_INT_ALL (ETH_INT_TX_COMPLETE_FRAME | \ + ETH_INT_TX_STOP | \ + ETH_INT_TX_BUF_UNAVAI | \ + ETH_INT_RX_OVERFLOW | \ + ETH_INT_TX_UNDERFLOW | \ + ETH_INT_RX_COMPLETE_FRAME | \ + ETH_INT_RX_BUF_UNAVAI | \ + ETH_INT_RX_STOP | \ + ETH_INT_BUS_FATAL_ERROR) + +#define IS_ETH_INT(INT) (((INT) != 0) && (((INT) & ~ETH_INT_ALL) == 0)) +/** + * @} + */ +/** + * @brief EFUSE receive filter structure + */ +typedef struct +{ + BOOL ETH_BroadcastFilterEnable; /*!< Broadcast is dropped or passed */ + BOOL ETH_OwnFilterEnable; /*!< source address filter is on or off */ + BOOL ETH_SelfDrop; /*!< Only own address is dropped or passed */ + BOOL ETH_SourceFilterEnable; /*!< source address filter is on or off */ + BOOL ETH_SourceDrop; /*!< Only specific source address is dropped or passed */ + uint8_t ETH_SourceMacAddr[6]; /*!< Source MAC address */ +} ETH_FrameFilter; + +/** + * @brief Ethernet initialization structure + */ +typedef struct +{ + BOOL ETH_LinkUp; /*!< If ETH is linked up and it can be retrieved from PHY */ + uint8_t ETH_Speed; /*!< speed of ETH, refer as @ref ETH_SPEED */ + uint8_t ETH_Duplex; /*!< duplex mode of ETH, refer as @ref ETH_DUPLEX */ + BOOL ETH_RxEn; /*!< Rx enable */ + BOOL ETH_TxEn; /*!< Tx enable */ + BOOL ETH_ChecksumOffload; /*!< Checksum offload enable */ + BOOL ETH_JumboFrame; /*!< Jumbo Frame Enable */ + uint8_t ETH_MacAddr[6]; /*!< MAC address */ + ETH_FrameFilter *ETH_Filter; /*!< Received frame address filter, receive all if null */ +} ETH_InitTypeDef; + +/** + * @brief Ethernet Tx descriptor structure + */ +typedef struct { + union { + uint32_t TX0; + + struct { + uint32_t : 1; + uint32_t UNDERFLOW_ERR : 1; /*!< [OUT] Underflow error */ + uint32_t : 1; + uint32_t COLLISION_CNT : 4; /*!< [OUT] Collision count */ + uint32_t : 1; + uint32_t EX_COLLISION : 1; /*!< [OUT] Excessive collision error */ + uint32_t LATE_COLLISION : 1; /*!< [OUT] Late collision error */ + uint32_t NO_CARRIER : 1; /*!< [OUT] No carrier error */ + uint32_t LOSS_CARRIER : 1; /*!< [OUT] loss of carrier error */ + uint32_t PAYLOAD_ERR : 1; /*!< [OUT] IP payload error */ + uint32_t : 2; + uint32_t ERR_SUM : 1; /*!< [OUT] Error summary */ + uint32_t HEADER_ERR : 1; /*!< [OUT] IP header error */ + uint32_t : 8; + uint32_t TTSE : 1; /*!< enables IEEE1588 hardware timestamping in first segment */ + uint32_t : 2; + uint32_t FS : 1; /*!< first segment flag */ + uint32_t LS : 1; /*!< last segment flag */ + uint32_t : 2; + } TX0_b; + } TX_0; + + union { + uint32_t TX1; + + struct { + uint32_t SIZE : 13; /*!< buffer size */ + uint32_t : 19; + } TX1_b; + } TX_1; + + uint32_t bufAddr; /*!< address of buffer */ + uint32_t nextDescAddr; /*!< address of next descriptor */ + uint64_t reserved; + uint64_t timeStamp; /*!< time stamp while last segment */ +} ETH_TX_DESC; + +/** + * @brief Ethernet Rx descriptor structure + */ +typedef struct { + union { + uint32_t RX0; + + struct { + uint32_t : 1; + uint32_t CRC_ERR : 1; /*!< [OUT] CRC error while last segment */ + uint32_t : 5; + uint32_t TTSE : 1; /*!< timestamp available while last segment */ + uint32_t LS : 1; /*!< [OUT] last segment flag */ + uint32_t FS : 1; /*!< [OUT] first segment flag */ + uint32_t : 1; + uint32_t OVERFLOW_ERR : 1; /*!< [OUT] FIFO overflow while last segment */ + uint32_t LENGTH_ERR : 1; /*!< [OUT] length error while last segment */ + uint32_t : 2; + uint32_t ERR_SUM : 1; /*!< [OUT] Error summary while last segment */ + uint32_t FL : 14; /*!< [OUT] frame length while last segment */ + uint32_t : 2; + } RX0_b; + } RX_0; + + union { + uint32_t RX1; + + struct { + uint32_t SIZE : 13; /*!< buffer size */ + uint32_t : 19; + } RX1_b; + } RX_1; + + uint32_t bufAddr; /*!< buffer address */ + uint32_t nextDescAddr; /*!< address of next descriptor */ + uint64_t reserved; + uint64_t timeStamp; /*!< time stamp while the last segment */ +} ETH_RX_DESC; + +/** + * @brief Read data from phy chip + * @param[in] phyAddr Address of phy chip + * @param[in] phyReg Address of phy's register to be read + * @retval uint32_t value of phy's register + */ +uint32_t ETH_PhyRead(uint32_t phyAddr, uint32_t phyReg); + +/** + * @brief Write data to phy chip + * @param[in] phyAddr Address of phy chip + * @param[in] phyReg Address of phy's register to be written + * @param[in] data Data to be written + * @retval None + */ +void ETH_PhyWrite(uint32_t phyAddr, uint32_t phyReg, uint32_t data); +/** + * @brief Fills each ETH_InitStruct member with its default value. + * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure + * which will be initialized. + * @retval : None + */ +void ETH_StructInit(ETH_InitTypeDef* init); +/** + * @brief Ethernet initialization + * @note This function should be called at first before any other interfaces. + * @param[in] init A pointer to structure ETH_InitTypeDef + * @retval BOOL The bit indicates if ethernet is initialized successfully + */ +BOOL ETH_Init(ETH_InitTypeDef *init); + +/** + * @brief Enable or disable ethernet interrupt. + * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT + * @param[in] Enable The bit indicates if specific interrupts are enable or not + * @retval None + */ +void ETH_ITConfig(uint32_t Int, BOOL enable); + +/** + * @brief Check specific interrupts are set or not + * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT + * @retval BOOL The bit indicates if specific interrupts are set or not + */ +BOOL ETH_GetITStatus(uint32_t Int); + +/** + * @brief Clear specific interrupts + * @param[in] Int interrupt mask bits, which can be the combination of @ref ETH_INT + * @retval None + */ +void ETH_ClearITPendingBit(uint32_t Int); + +/** + * @brief Get ethernte MAC address + * @param[in] mac A user-allocated buffer to fetch MAC to be read, 6 bytes. + * @retval None + */ +void ETH_GetMacAddr(uint8_t *mac); + +/** + * @brief Set ethernet transmission descriptor ring + * @note Make sure that memory occupied by descriptors should be in physical + * memory and keep valid before ethernet transmission is finished. + * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node + * has a 'nextDescAddr' pointed to first node. + * @retval BOOL The bit indicates if valid ring is set + */ +BOOL ETH_SetTxDescRing(ETH_TX_DESC *ring); + +/** + * @brief Start ethernet transmission + * @param None + * @retval None + */ +void ETH_StartTx(void); + +/** + * @brief Stop ethernet transmission + * @param None + * @retval None + */ +void ETH_StopTx(void); + +/** + * @brief Resume ethernet transmission\n + * While ethernet doesn't have enough buffer to transmit data, it will + * pause and inform users by interrupt 'ETH_INT_TX_BUF_UNAVAI'. Users + * must call this function to start ethernet again after new buffer + * prepared. + * @param None + * @retval None + */ +void ETH_ResumeTx(void); + +/** + * @brief Get free transmission descriptor\n + * @param None + * @retval ETH_TX_DESC* A pointer of free transmission descriptor, + * NULL if no free descriptor + */ +ETH_TX_DESC *ETH_AcquireFreeTxDesc(void); + +/** + * @brief Check if a transmission descriptor is free or not + * @param[in] desc A pointer of a transmission descriptor + * @retval BOOL True if the transmission descriptor is free, or flase. + */ +BOOL ETH_IsFreeTxDesc(ETH_TX_DESC *desc); + +/** + * @brief Release a transmission descriptor to ethernet\n + * After users prepared data in the buffer of a free descriptor, + * They must call this function to change ownership of the + * descriptor to hardware. + * @param[in] desc A pointer of a transmission descriptor + * @retval None + */ +void ETH_ReleaseTxDesc(ETH_TX_DESC *desc); + +/** + * @brief Set buffer address of the specific TX descriptor + * @param[in] desc A pointer of a transmission descriptor + * @param[in] bufAddr buffer address to be sent + * @retval None + */ +void ETH_SetTxDescBufAddr(ETH_TX_DESC *desc, uint32_t bufAddr); + +/** + * @brief Get buffer address of the specific TX descriptor + * @param[in] desc A pointer of a transmission descriptor + * @retval uint32_t buffer address to be gotten + */ +uint32_t ETH_GetTxDescBufAddr(ETH_TX_DESC *desc); + +/** + * @brief Set ethernet receive descriptor ring + * @note Make sure that memory occupied by descriptors should be in physical + * memory and keep valid before ethernet receive is finished. + * @param[in] ring A pointer to header of ETH_TX_DESC ring, whose last node + * has a 'nextDescAddr' pointed to first node. + * @retval BOOL The bit indicates if valid ring is set + */ +BOOL ETH_SetRxDescRing(ETH_RX_DESC *ring); + +/** + * @brief Start ethernet receive + * @param None + * @retval None + */ +void ETH_StartRx(void); + +/** + * @brief Stop ethernet receive + * @param None + * @retval None + */ +void ETH_StopRx(void); + +/** + * @brief Resume ethernet receive\n + * While ethernet doesn't have enough buffer to receive data, it will + * pause and inform users by interrupt 'ETH_INT_RX_BUF_UNAVAI'. Users + * must call this function to start ethernet again after new buffer + * prepared. + * @param None + * @retval None + */ +void ETH_ResumeRx(void); + +/** + * @brief Get the free descriptor which contains received data\n + * @param None + * @retval ETH_RX_DESC* A pointer of free receive descriptor, + * NULL if no free descriptor + */ +ETH_RX_DESC *ETH_AcquireFreeRxDesc(void); + +/** + * @brief Check if a receive descriptor is free or not + * @param[in] desc A pointer of a receive descriptor + * @retval BOOL True if the receive descriptor is free, or flase. + */ +BOOL ETH_IsFreeRxDesc(ETH_RX_DESC *desc); + +/** + * @brief Release a receive descriptor to ethernet\n + * After users handled data in the buffer of a free descriptor, + * They must call this function to change ownership of the + * descriptor to hardware. + * @param[in] desc A pointer of a transmission descriptor + * @retval None + */ +void ETH_ReleaseRxDesc(ETH_RX_DESC *desc); + +/** + * @brief Set buffer address of the specific RX descriptor + * @param[in] desc A pointer of a receive descriptor + * @param[in] bufAddr buffer address to be received + * @retval None + */ +void ETH_SetRxDescBufAddr(ETH_RX_DESC *desc, uint32_t bufAddr); + +/** + * @brief Get buffer address of the specific RX descriptor + * @param[in] desc A pointer of a receive descriptor + * @retval uint32_t buffer address to be gotten + */ +uint32_t ETH_GetRxDescBufAddr(ETH_RX_DESC *desc); + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_ETH_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h index b2ef305965..c0737b5295 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_flash.h @@ -200,14 +200,14 @@ void FLASH_Read(uint8_t ReadMode, uint32_t addr, uint16_t size, uint8_t* data); * @param[out] data A pointer to the data to be written * @retval None */ -void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data); - - -void flash_WaitInWritting(void) ; - -void flash_WaitReadFifoNotEmpty(void); - -uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ; +void FLASH_Write(uint32_t addr, uint16_t size, uint8_t* data); + + +void flash_WaitInWritting(void) ; + +void flash_WaitReadFifoNotEmpty(void); + +uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) ; #ifdef __cplusplus diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h index e76d9d42d2..1652a8a5d2 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_gpio.h @@ -139,17 +139,17 @@ void GPIO_InitPwm(uint8_t Channel, uint32_t HighLevelNanoSecond, uint32_t LowLev * @retval None */ void GPIO_EnablePwm(uint8_t Channel, BOOL Enable); - - - -/** - xjf 20150324 - -**/ -void GPIO_SetBits(uint32_t mask); -void GPIO_clrBits(uint32_t mask); -uint32_t GPIO_getBits(uint32_t mask); - + + + +/** + xjf 20150324 + +**/ +void GPIO_SetBits(uint32_t mask); +void GPIO_clrBits(uint32_t mask); +uint32_t GPIO_getBits(uint32_t mask); + #ifdef __cplusplus } diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h index 54d608dc41..bb2adcd2a9 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_includes.h @@ -101,16 +101,16 @@ #ifdef _WDG #include "cmem7_wdg.h" #endif - - -#ifdef _MARVELL - #include - #include -#endif - -#ifdef _IP1826D - #include -#endif + + +#ifdef _MARVELL + #include + #include +#endif + +#ifdef _IP1826D + #include +#endif #ifdef __cplusplus } diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h index 43744c2625..820a8ea59f 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_misc.h @@ -1,276 +1,276 @@ -/** - ***************************************************************************** - * @file cmem7_misc.h - * - * @brief CMEM7 miscellaneous header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_MISC_H -#define __CMEM7_MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** - * @brief NVIC initialization structure - */ -/** -@code - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - ============================================================================================================================ - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ============================================================================================================================ - NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - ---------------------------------------------------------------------------------------------------------------------------- - NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ============================================================================================================================ -@endcode - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be a value of @ref IRQn_Type - (For the complete Capital-micro Devices IRQ Channels list, please - refer to cmem7.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref NVIC_Priority_Table */ - - BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - - -/** @defgroup NVIC_VectTab - * @{ - */ - -#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000) -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \ - ((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup NVIC_LP - * @{ - */ -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup NVIC_PriorityGroup - * @{ - */ -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) -/** - * @} - */ - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values, ref as @ref NVIC_VectTab: - * @arg NVIC_VectTab_RAM - * @arg NVIC_VectTab_FLASH - * @param Offset: Vector Table base offset field. This value must be a multiple - * of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values, ref as @ref NVIC_LP: - * @arg NVIC_LP_SEVONPEND - * @arg NVIC_LP_SLEEPDEEP - * @arg NVIC_LP_SLEEPONEXIT - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState); - -/** - * @brief Memory map from address 'from' to 'address 'to' and open icache or not - * @param[in] from address to be mapped from - * @param[in] to address to be mapped to - * @param[in] isIcacheOn icache is on or off - * @retval None - */ -void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn); - -/** - * @brief Convert the mapping destination address to source address - * @param[in] to address to be mapped to - * @retval uint32_t address to be mapped from - */ -uint32_t GLB_ConvertToMappingFromAddr(uint32_t to); - -/** - * @brief Convert the mapping source address to destination address - * @param[in] from address to be mapped from - * @retval uint32_t address to be mapped to - */ -uint32_t GLB_ConvertToMappingToAddr(uint32_t from); - -/** - * @brief Set NMI irq number, it should be one of @ref IRQn_Type. - * @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI - * interrupt routine if the specific 'irq' occurs. By default, NMI irq number - * is 0, same as ETH_INT_IRQn - * @param[in] irq irq number - * @retval None - */ -void GLB_SetNmiIrqNum(uint32_t irq); - -/** @defgroup SYS_CLK_SEL - * @{ - */ -#define SYS_CLK_SEL_OSC 0x0 -#define SYS_CLK_SEL_DLL 0x1 -#define SYS_CLK_SEL_CRYSTAL 0x2 -#define SYS_CLK_SEL_EXTERNAL 0x3 -/** - * @} - */ - -/** - * @brief Select system clock source, it should be one of @ref SYS_CLK_SEL. - * @Note You MUST make sure externel clock has been stabled if clock - * source is external before call this function. - * Default value is SYS_CLK_SEL_OSC - * @param[in] irq irq number - * @retval None - */ -void GLB_SelectSysClkSource(uint8_t source); - -/** - * @brief Simulate instruction 'STRB' or 'STRH' with 'BFI' - * @Note In M7, you have to write a register in 32-bit alignment, - * not in 8-bit or 16-bit. - * @param[in] addr register address to be written - * @param[in] value value to be written - * @param[in] lsb LSB in register to be written - * @param[in] len bit length to be written - * @retval None - */ - - -//#define aaaa(len) __asm("LDR len, 11") - -#define CMEM7_BFI(addr, value, lsb, len) \ - do { \ - unsigned long tmp; \ - unsigned long tmp1 = (unsigned long)addr; \ - \ - __asm("LDR tmp, [tmp1]\n" \ - "BFI tmp, "#value", "#lsb", "#len" \n" \ - "STR tmp, [tmp1]\n"); \ - } while (0) - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_MISC_H */ - +/** + ***************************************************************************** + * @file cmem7_misc.h + * + * @brief CMEM7 miscellaneous header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_MISC_H +#define __CMEM7_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** + * @brief NVIC initialization structure + */ +/** +@code + The table below gives the allowed values of the pre-emption priority and subpriority according + to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function + ============================================================================================================================ + NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description + ============================================================================================================================ + NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority + | | | 4 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority + | | | 3 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority + | | | 2 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority + | | | 1 bits for subpriority + ---------------------------------------------------------------------------------------------------------------------------- + NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority + | | | 0 bits for subpriority + ============================================================================================================================ +@endcode + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete Capital-micro Devices IRQ Channels list, please + refer to cmem7.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref NVIC_Priority_Table */ + + BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + + +/** @defgroup NVIC_VectTab + * @{ + */ + +#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000) +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \ + ((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup NVIC_LP + * @{ + */ +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup NVIC_PriorityGroup + * @{ + */ +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) +/** + * @} + */ + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values, ref as @ref NVIC_VectTab: + * @arg NVIC_VectTab_RAM + * @arg NVIC_VectTab_FLASH + * @param Offset: Vector Table base offset field. This value must be a multiple + * of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values, ref as @ref NVIC_LP: + * @arg NVIC_LP_SEVONPEND + * @arg NVIC_LP_SLEEPDEEP + * @arg NVIC_LP_SLEEPONEXIT + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState); + +/** + * @brief Memory map from address 'from' to 'address 'to' and open icache or not + * @param[in] from address to be mapped from + * @param[in] to address to be mapped to + * @param[in] isIcacheOn icache is on or off + * @retval None + */ +void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn); + +/** + * @brief Convert the mapping destination address to source address + * @param[in] to address to be mapped to + * @retval uint32_t address to be mapped from + */ +uint32_t GLB_ConvertToMappingFromAddr(uint32_t to); + +/** + * @brief Convert the mapping source address to destination address + * @param[in] from address to be mapped from + * @retval uint32_t address to be mapped to + */ +uint32_t GLB_ConvertToMappingToAddr(uint32_t from); + +/** + * @brief Set NMI irq number, it should be one of @ref IRQn_Type. + * @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI + * interrupt routine if the specific 'irq' occurs. By default, NMI irq number + * is 0, same as ETH_INT_IRQn + * @param[in] irq irq number + * @retval None + */ +void GLB_SetNmiIrqNum(uint32_t irq); + +/** @defgroup SYS_CLK_SEL + * @{ + */ +#define SYS_CLK_SEL_OSC 0x0 +#define SYS_CLK_SEL_DLL 0x1 +#define SYS_CLK_SEL_CRYSTAL 0x2 +#define SYS_CLK_SEL_EXTERNAL 0x3 +/** + * @} + */ + +/** + * @brief Select system clock source, it should be one of @ref SYS_CLK_SEL. + * @Note You MUST make sure externel clock has been stabled if clock + * source is external before call this function. + * Default value is SYS_CLK_SEL_OSC + * @param[in] irq irq number + * @retval None + */ +void GLB_SelectSysClkSource(uint8_t source); + +/** + * @brief Simulate instruction 'STRB' or 'STRH' with 'BFI' + * @Note In M7, you have to write a register in 32-bit alignment, + * not in 8-bit or 16-bit. + * @param[in] addr register address to be written + * @param[in] value value to be written + * @param[in] lsb LSB in register to be written + * @param[in] len bit length to be written + * @retval None + */ + + +//#define aaaa(len) __asm("LDR len, 11") + +#define CMEM7_BFI(addr, value, lsb, len) \ + do { \ + unsigned long tmp; \ + unsigned long tmp1 = (unsigned long)addr; \ + \ + __asm("LDR tmp, [tmp1]\n" \ + "BFI tmp, "#value", "#lsb", "#len" \n" \ + "STR tmp, [tmp1]\n"); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_MISC_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h index 00d5d74520..885d704ceb 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_rtc.h @@ -1,89 +1,89 @@ -/** - ***************************************************************************** - * @file cmem7_rtc.h - * - * @brief CMEM7 RTC header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_RTC_H -#define __CMEM7_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** @defgroup RTC_Int - * @{ - */ -#define RTC_Int_Second ((uint32_t)0x00000001) -#define RTC_Int_Millsecond ((uint32_t)0x00000002) -#define RTC_Int_All ((uint32_t)0x00000003) -#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0)) -/** - * @} - */ - -/** - * @brief Enable or disable RTC interrupt. - * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int - * @param[in] Enable The bit indicates if specific interrupts are enable or not - * @retval None - */ -void RTC_ITConfig(uint32_t Int, BOOL Enable); - -/** - * @brief Check specific interrupts are set or not - * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int - * @retval BOOL The bit indicates if specific interrupts are set or not - */ -BOOL RTC_GetITStatus(uint32_t Int); - -/** - * @brief Clear specific interrupts - * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t Int); - -/** - * @brief Get seconds since power up - * @param None - * @retval uint32_t Seconds since power up - */ -uint32_t RTC_GetSecond(void); - -/** - * @brief Get current millseconds - * @param None - * @retval uint32_t Current millseconds - */ -uint16_t RTC_GetMillSecond(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_RTC_H */ - +/** + ***************************************************************************** + * @file cmem7_rtc.h + * + * @brief CMEM7 RTC header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_RTC_H +#define __CMEM7_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** @defgroup RTC_Int + * @{ + */ +#define RTC_Int_Second ((uint32_t)0x00000001) +#define RTC_Int_Millsecond ((uint32_t)0x00000002) +#define RTC_Int_All ((uint32_t)0x00000003) +#define IS_RTC_INT(INT) (((INT) != 0) && (((INT) & ~RTC_Int_All) == 0)) +/** + * @} + */ + +/** + * @brief Enable or disable RTC interrupt. + * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int + * @param[in] Enable The bit indicates if specific interrupts are enable or not + * @retval None + */ +void RTC_ITConfig(uint32_t Int, BOOL Enable); + +/** + * @brief Check specific interrupts are set or not + * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int + * @retval BOOL The bit indicates if specific interrupts are set or not + */ +BOOL RTC_GetITStatus(uint32_t Int); + +/** + * @brief Clear specific interrupts + * @param[in] Int interrupt mask bits, which can be the combination of @ref RTC_Int + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t Int); + +/** + * @brief Get seconds since power up + * @param None + * @retval uint32_t Seconds since power up + */ +uint32_t RTC_GetSecond(void); + +/** + * @brief Get current millseconds + * @param None + * @retval uint32_t Current millseconds + */ +uint16_t RTC_GetMillSecond(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_RTC_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h index 5abf7ba0d8..78c444c53b 100644 --- a/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h +++ b/bsp/CME_M7/StdPeriph_Driver/inc/cmem7_wdg.h @@ -1,110 +1,110 @@ -/** - ***************************************************************************** - * @file cmem7_wdg.h - * - * @brief CMEM7 watchdog header file - * - * - * @version V1.0 - * @date 3. September 2013 - * - * @note - * - ***************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, - * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2013 Capital-micro

- ***************************************************************************** - */ - -#ifndef __CMEM7_WDG_H -#define __CMEM7_WDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -#include "cmem7.h" -#include "cmem7_conf.h" - -/** @defgroup WDG_INT - * @{ - */ -#define WDG_INT_QUARTER 0 -#define WDG_INT_HALF 1 -#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \ - ((INT) == WDG_INT_HALF)) -/** - * @} - */ - -/** @defgroup WDG_TRIGGER_MODE - * @{ - */ -#define WDG_TRIGGER_MODE_EDGE 0 -#define WDG_TRIGGER_MODE_LEVEL 1 -#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \ - ((TRI) == WDG_TRIGGER_MODE_LEVEL)) -/** - * @} - */ - -/** - * @brief Deinitializes the Watchdog peripheral registers to their default reset values. - * @param[in] None - * @retval None - */ -void WDG_DeInit(void); - -/** - * @brief Watchdog initialization - * @note This function should be called at first before any other interfaces. - * @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE - * @param[in] ResetMillSecond MillSeconds lasts before global reset - * @retval None - */ -void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond); - -/** - * @brief Enable or disable watchdog interrupt. - * @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT - * @param[in] Enable The bit indicates if the specific interrupt are enable or not - * @retval None - */ -void WDG_ITConfig(uint8_t Int, BOOL Enable); - -/** - * @brief Check the specific interrupt are set or not - * @param None - * @retval BOOL The bit indicates if the specific interrupt are set or not - */ -BOOL WDG_GetITStatus(void); - -/** - * @brief Clear the specific interrupt - * @param None - * @retval None - */ -void WDG_ClearITPendingBit(void); - -/** - * @brief Enable or disable watchdog. - * @param[in] Enable The bit indicates if watchdog is enable or not - * @retval None - */ -void WDG_Cmd(BOOL Enable); - - -#ifdef __cplusplus -} -#endif - -#endif /* __CMEM7_WDG_H */ - +/** + ***************************************************************************** + * @file cmem7_wdg.h + * + * @brief CMEM7 watchdog header file + * + * + * @version V1.0 + * @date 3. September 2013 + * + * @note + * + ***************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2013 Capital-micro

+ ***************************************************************************** + */ + +#ifndef __CMEM7_WDG_H +#define __CMEM7_WDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "cmem7.h" +#include "cmem7_conf.h" + +/** @defgroup WDG_INT + * @{ + */ +#define WDG_INT_QUARTER 0 +#define WDG_INT_HALF 1 +#define IS_WDG_INT(INT) (((INT) == WDG_INT_QUARTER) || \ + ((INT) == WDG_INT_HALF)) +/** + * @} + */ + +/** @defgroup WDG_TRIGGER_MODE + * @{ + */ +#define WDG_TRIGGER_MODE_EDGE 0 +#define WDG_TRIGGER_MODE_LEVEL 1 +#define IS_WDG_TRIGGER_MODE(TRI) (((TRI) == WDG_TRIGGER_MODE_EDGE) || \ + ((TRI) == WDG_TRIGGER_MODE_LEVEL)) +/** + * @} + */ + +/** + * @brief Deinitializes the Watchdog peripheral registers to their default reset values. + * @param[in] None + * @retval None + */ +void WDG_DeInit(void); + +/** + * @brief Watchdog initialization + * @note This function should be called at first before any other interfaces. + * @param[in] trigger Watchdog interrupt trigger mode, which is a value of @ref WDG_TRIGGER_MODE + * @param[in] ResetMillSecond MillSeconds lasts before global reset + * @retval None + */ +void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond); + +/** + * @brief Enable or disable watchdog interrupt. + * @param[in] Int interrupt mask bits, which is a value of @ref WDG_INT + * @param[in] Enable The bit indicates if the specific interrupt are enable or not + * @retval None + */ +void WDG_ITConfig(uint8_t Int, BOOL Enable); + +/** + * @brief Check the specific interrupt are set or not + * @param None + * @retval BOOL The bit indicates if the specific interrupt are set or not + */ +BOOL WDG_GetITStatus(void); + +/** + * @brief Clear the specific interrupt + * @param None + * @retval None + */ +void WDG_ClearITPendingBit(void); + +/** + * @brief Enable or disable watchdog. + * @param[in] Enable The bit indicates if watchdog is enable or not + * @retval None + */ +void WDG_Cmd(BOOL Enable); + + +#ifdef __cplusplus +} +#endif + +#endif /* __CMEM7_WDG_H */ + diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c index db9adf0763..8fc764abf6 100644 --- a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c +++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_flash.c @@ -108,7 +108,8 @@ static uint8_t flash_ReadInnerStatusHigh() { return (uint8_t)NOR_FLASH->DATA; } -static void flash_WaitInWritting() { +//static void flash_WaitInWritting() { +void flash_WaitInWritting(void) { FLASH_INNER_STATUS s; while (NOR_FLASH->STATUS_b.BUSY); @@ -173,7 +174,8 @@ static void flash_RwReq(uint8_t cmd, uint32_t addr, uint16_t size) { NOR_FLASH->TRIGGER_b.OP_START = TRUE; } -static void flash_WaitReadFifoNotEmpty() { +//static void flash_WaitReadFifoNotEmpty() { +void flash_WaitReadFifoNotEmpty(void) { while (NOR_FLASH->STATUS_b.RD_FIFO_EMPTY) { if (wait) { (*wait)(); @@ -181,7 +183,8 @@ static void flash_WaitReadFifoNotEmpty() { } } -static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) { +//static uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) { +uint16_t flash_ReadFifo(uint16_t size, uint8_t* data) { uint16_t count = 0; while (!NOR_FLASH->STATUS_b.RD_FIFO_EMPTY && size != 0) { diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c index f49e727862..785c8a0767 100644 --- a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c +++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_gpio.c @@ -179,3 +179,78 @@ void GPIO_EnablePwm(uint8_t Channel, BOOL Enable) { } } +/** + xjf 20150324 + +**/ +void GPIO_SetBits(uint32_t mask) +{ + static uint32_t g_GPIO_OUT_UNMASK; + static uint32_t g_GPIO_OUT_DATA; + static uint32_t g_GPIO_OE; + + g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ; + g_GPIO_OUT_DATA = GPIO->GPIO_OUT_DATA ; + g_GPIO_OE = GPIO->GPIO_OE ; + g_GPIO_OUT_UNMASK |=mask; + g_GPIO_OE |=mask; + g_GPIO_OUT_DATA |=mask; + + GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ; + GPIO->GPIO_OUT_DATA =g_GPIO_OUT_DATA ; + GPIO->GPIO_OE =g_GPIO_OE ; +} + +void GPIO_clrBits(uint32_t mask) +{ + static uint32_t g_GPIO_OUT_UNMASK; + static uint32_t g_GPIO_OUT_DATA; + static uint32_t g_GPIO_OE; + + g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ; + g_GPIO_OUT_DATA = GPIO->GPIO_OUT_DATA ; + g_GPIO_OE = GPIO->GPIO_OE ; + g_GPIO_OUT_UNMASK |=mask; + g_GPIO_OE |=mask; + g_GPIO_OUT_DATA &=(~ mask); + + GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ; + GPIO->GPIO_OUT_DATA =g_GPIO_OUT_DATA ; + GPIO->GPIO_OE =g_GPIO_OE ; +} + +uint32_t GPIO_getBits(uint32_t mask) +{ + static uint32_t g_GPIO_OUT_UNMASK; + //static uint32_t g_GPIO_OUT_DATA; + static uint32_t g_GPIO_OE; + + uint32_t get_delay = 0; + uint32_t saved_mask; + + saved_mask=mask; + + g_GPIO_OUT_UNMASK = GPIO->GPIO_OUT_UNMASK ; + g_GPIO_OE = GPIO->GPIO_OE ; + g_GPIO_OUT_UNMASK &=(~mask); + g_GPIO_OE &=(~mask); + GPIO->GPIO_OUT_UNMASK =g_GPIO_OUT_UNMASK ; + GPIO->GPIO_OE =g_GPIO_OE ; + for(get_delay=0;get_delay<100;get_delay++) + { + } + //get_delay=(GPIO->GPIO_IN)&saved_mask; + if(((GPIO->GPIO_IN)&saved_mask)==saved_mask) + { + return(1); + } + else + { + return(0); + } + +} +/** + xjf 20150324 + +**/ diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c index fd88e6769c..9f4151fa85 100644 --- a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c +++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_misc.c @@ -92,8 +92,20 @@ void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState) } } +#define DEF_IBUS_OFFSET 0x1FFE0000 +#define DEF_EXT_ADDR 0x08020000 +static BOOL isMappingOn() { + /* If default values aren't changed */ + if ((GLOBAL_CTRL->IBUSOFF == DEF_IBUS_OFFSET) && + (GLOBAL_CTRL->EXTADDR == DEF_EXT_ADDR)) { + return FALSE; + } + + return TRUE; +} + void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) { - int n; + volatile int n; GLOBAL_CTRL->IBUSOFF = GLOBAL_CTRL->DBUSOFF = (from - to); GLOBAL_CTRL->EXTADDR = to; @@ -104,6 +116,38 @@ void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn) { for (n = 0; n < 100; n++); } +/* + * ------------------------------------------------------------------ + * | 0 - 0x20000 | --> 0x20000000 | -> 0x40000000 | -> 0xFFFFFFFF | + * | code SRAM | map to region | data SRAM | map from region | + * ------------------------------------------------------------------ + */ +#define MAPPING_FROM_REGION_START 0x40000000 +#define MAPPING_TO_REGION_END 0x20000000 +uint32_t GLB_ConvertToMappingFromAddr(uint32_t to) { + if (!isMappingOn()) { + return to; + } + + if ((to > MAPPING_TO_REGION_END) || (to < GLOBAL_CTRL->EXTADDR)) { + return to; + } + + return (to + GLOBAL_CTRL->IBUSOFF); +} + +uint32_t GLB_ConvertToMappingToAddr(uint32_t from) { + if (!isMappingOn()) { + return from; + } + + if (from < MAPPING_FROM_REGION_START) { + return from; + } + + return (from - GLOBAL_CTRL->IBUSOFF); +} + void GLB_SetNmiIrqNum(uint32_t irq) { GLOBAL_CTRL->NMI_SEL_b.NMI = irq; } diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c index d107e0cb8d..aec1580ad9 100644 --- a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c +++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_rtc.c @@ -28,7 +28,7 @@ #define SECONDS_IN_A_DAY (86400) -void RTC_EnableInt(uint32_t Int, BOOL Enable) { +void RTC_ITConfig(uint32_t Int, BOOL Enable) { assert_param(IS_RTC_INT(Int)); if (Enable) { @@ -38,7 +38,7 @@ void RTC_EnableInt(uint32_t Int, BOOL Enable) { } } -BOOL RTC_GetIntStatus(uint32_t Int) { +BOOL RTC_GetITStatus(uint32_t Int) { assert_param(IS_RTC_INT(Int)); if (0 != (RTC->INT_STATUS & Int)) { @@ -48,7 +48,7 @@ BOOL RTC_GetIntStatus(uint32_t Int) { return FALSE; } -void RTC_ClearInt(uint32_t Int) { +void RTC_ClearITPendingBit(uint32_t Int) { assert_param(IS_RTC_INT(Int)); RTC->INT_STATUS = Int; @@ -58,6 +58,6 @@ uint32_t RTC_GetSecond() { return RTC->SECOND; } -uint16_t RTC_GetMicroSecond() { - return RTC->MICROSECOND_b.MS; +uint16_t RTC_GetMillSecond() { + return RTC->MILLSECOND_b.MS; } diff --git a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c index 6518d81225..8ac809caf9 100644 --- a/bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c +++ b/bsp/CME_M7/StdPeriph_Driver/src/cmem7_wdg.c @@ -30,29 +30,34 @@ static uint32_t wdg_GetClock() { return SYSTEM_CLOCK_FREQ / (1 << (GLOBAL_CTRL->CLK_SEL_0_b.WDG_CLK + 1)); } -void WDG_Init(uint8_t trigger, uint16_t ResetMicroSecond) { +void WDG_DeInit(void){ + SOFT_RESET->SOFTRST_b.WDT_n = 0; + SOFT_RESET->SOFTRST_b.WDT_n = 1; +} + +void WDG_Init(uint8_t trigger, uint16_t ResetMillSecond) { assert_param(IS_WDG_TRIGGER_MODE(trigger)); WDG->INT_CTRL_b.TRIGGER_MODE = trigger; - WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMicroSecond / 1000; + WDG->LEN = ((uint64_t)wdg_GetClock()) * ResetMillSecond / 1000; } -void WDG_EnableInt(uint8_t Int, BOOL Enable) { +void WDG_ITConfig(uint8_t Int, BOOL Enable) { assert_param(IS_WDG_INT(Int)); WDG->CTRL_b.INT_LEN = Int; WDG->INT_CTRL_b.MASK = !Enable; } -BOOL WDG_GetIntStatus() { +BOOL WDG_GetITStatus() { return (WDG->INT_STA_b.STA == 1) ? TRUE : FALSE; } -void WDG_ClearInt() { +void WDG_ClearITPendingBit() { WDG->INT_STA_b.STA = 1; } -void WDG_Enable(BOOL Enable) { +void WDG_Cmd(BOOL Enable) { WDG->CTRL_b.EN = Enable; } diff --git a/bsp/CME_M7/drivers/emac.c b/bsp/CME_M7/drivers/emac.c index 3de53142b9..a8837d44ce 100644 --- a/bsp/CME_M7/drivers/emac.c +++ b/bsp/CME_M7/drivers/emac.c @@ -205,14 +205,14 @@ static rt_err_t rt_cme_eth_init(rt_device_t dev) RxDescChainInit(); TxDescChainInit(); - ETH_EnableInt(ETH_INT_BUS_FATAL_ERROR, TRUE); + ETH_ITConfig(ETH_INT_BUS_FATAL_ERROR, TRUE); - ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE); - ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE); - ETH_EnableInt(ETH_INT_RX_STOP, TRUE); + ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE); + ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE); + ETH_ITConfig(ETH_INT_RX_STOP, TRUE); ETH_StartRx(); - ETH_EnableInt(ETH_INT_TX_COMPLETE_FRAME, TRUE); + ETH_ITConfig(ETH_INT_TX_COMPLETE_FRAME, TRUE); ETH_StartTx(); return RT_EOK; @@ -318,8 +318,8 @@ struct pbuf *rt_cme_eth_rx(rt_device_t dev) desc = ETH_AcquireFreeRxDesc(); if(desc == RT_NULL) { - ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, TRUE); - ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, TRUE); + ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, TRUE); + ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, TRUE); ETH_ResumeRx(); goto _exit; } @@ -414,28 +414,28 @@ void ETH_IRQHandler(void) /* enter interrupt */ rt_interrupt_enter(); - if (ETH_GetIntStatus(ETH_INT_TX_COMPLETE_FRAME)) + if (ETH_GetITStatus(ETH_INT_TX_COMPLETE_FRAME)) { rt_sem_release(&cme_eth_device.tx_buf_free); - ETH_ClearInt(ETH_INT_TX_COMPLETE_FRAME); + ETH_ClearITPendingBit(ETH_INT_TX_COMPLETE_FRAME); } - if (ETH_GetIntStatus(ETH_INT_RX_STOP)) + if (ETH_GetITStatus(ETH_INT_RX_STOP)) { CME_ETH_PRINTF("ETH_INT_RX_STOP\n"); - ETH_ClearInt(ETH_INT_RX_STOP); + ETH_ClearITPendingBit(ETH_INT_RX_STOP); } - if ((ETH_GetIntStatus(ETH_INT_RX_BUF_UNAVAI)) || - (ETH_GetIntStatus(ETH_INT_RX_COMPLETE_FRAME))) + if ((ETH_GetITStatus(ETH_INT_RX_BUF_UNAVAI)) || + (ETH_GetITStatus(ETH_INT_RX_COMPLETE_FRAME))) { /* a frame has been received */ eth_device_ready(&(cme_eth_device.parent)); - ETH_EnableInt(ETH_INT_RX_COMPLETE_FRAME, FALSE); - ETH_EnableInt(ETH_INT_RX_BUF_UNAVAI, FALSE); - ETH_ClearInt(ETH_INT_RX_BUF_UNAVAI); - ETH_ClearInt(ETH_INT_RX_COMPLETE_FRAME); + ETH_ITConfig(ETH_INT_RX_COMPLETE_FRAME, FALSE); + ETH_ITConfig(ETH_INT_RX_BUF_UNAVAI, FALSE); + ETH_ClearITPendingBit(ETH_INT_RX_BUF_UNAVAI); + ETH_ClearITPendingBit(ETH_INT_RX_COMPLETE_FRAME); } /* leave interrupt */ diff --git a/bsp/CME_M7/project.uvopt b/bsp/CME_M7/project.uvopt index 21805b8fa9..b1d469cb6d 100644 --- a/bsp/CME_M7/project.uvopt +++ b/bsp/CME_M7/project.uvopt @@ -76,6 +76,16 @@ 1 0 + + SARMCM3.DLL + + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + 0 1 @@ -93,13 +103,9 @@ 1 0 1 - 1 - 1 - 1 - 1 0 0 - 17 + 15 @@ -125,9 +131,6 @@ - - 0 - 0 1 @@ -160,11 +163,1515 @@ - Source Group 1 + StdPeriph_Driver 0 0 0 - 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_adc.c + cmem7_adc.c + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_aes.c + cmem7_aes.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_can.c + cmem7_can.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_ddr.c + cmem7_ddr.c + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_dma.c + cmem7_dma.c + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_efuse.c + cmem7_efuse.c + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_eth.c + cmem7_eth.c + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_flash.c + cmem7_flash.c + + + 1 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_gpio.c + cmem7_gpio.c + + + 1 + 10 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_i2c.c + cmem7_i2c.c + + + 1 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_misc.c + cmem7_misc.c + + + 1 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_rtc.c + cmem7_rtc.c + + + 1 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_spi.c + cmem7_spi.c + + + 1 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_tim.c + cmem7_tim.c + + + 1 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_uart.c + cmem7_uart.c + + + 1 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_usb.c + cmem7_usb.c + + + 1 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + StdPeriph_Driver/src/cmem7_wdg.c + cmem7_wdg.c + + + + + Applications + 0 + 0 + 0 + + 2 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + applications/application.c + application.c + + + 2 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + applications/led.c + led.c + + + 2 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + applications/startup.c + startup.c + + + + + Drivers + 0 + 0 + 0 + + 3 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + drivers/board.c + board.c + + + 3 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + drivers/uart.c + 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../../src/mem.c + mem.c + + + 5 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../src/mempool.c + mempool.c + + + 5 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../src/object.c + object.c + + + 5 + 37 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../src/scheduler.c + scheduler.c + + + 5 + 38 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../src/thread.c + thread.c + + + 5 + 39 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../src/timer.c + timer.c + + + + + CORTEX-M3 + 0 + 0 + 0 + + 6 + 40 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../libcpu/arm/cortex-m3/cpuport.c + cpuport.c + + + 6 + 41 + 2 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../libcpu/arm/cortex-m3/context_rvds.S + context_rvds.S + + + 6 + 42 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../libcpu/arm/common/backtrace.c + backtrace.c + + + 6 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../libcpu/arm/common/div0.c + div0.c + + + 6 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../libcpu/arm/common/showmem.c + showmem.c + + + + + libc + 0 + 0 + 0 + + 7 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/libc/armlibc/mem_std.c + mem_std.c + + + 7 + 46 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/libc/armlibc/stubs.c + stubs.c + + + + + DeviceDrivers + 0 + 0 + 0 + + 8 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/drivers/serial/serial.c + serial.c + + + 8 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/drivers/src/completion.c + completion.c + + + 8 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/drivers/src/dataqueue.c + dataqueue.c + + + 8 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/drivers/src/pipe.c + pipe.c + + + 8 + 51 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/drivers/src/portal.c + portal.c + + + 8 + 52 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/drivers/src/ringbuffer.c + ringbuffer.c + + + 8 + 53 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/drivers/src/workqueue.c + workqueue.c + + + + + finsh + 0 + 0 + 0 + + 9 + 54 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/shell.c + shell.c + + + 9 + 55 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/symbol.c + symbol.c + + + 9 + 56 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/cmd.c + cmd.c + + + 9 + 57 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/msh_cmd.c + msh_cmd.c + + + 9 + 58 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/msh.c + msh.c + + + 9 + 59 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_compiler.c + finsh_compiler.c + + + 9 + 60 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_error.c + finsh_error.c + + + 9 + 61 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_heap.c + finsh_heap.c + + + 9 + 62 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_init.c + finsh_init.c + + + 9 + 63 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_node.c + finsh_node.c + + + 9 + 64 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_ops.c + finsh_ops.c + + + 9 + 65 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_parser.c + finsh_parser.c + + + 9 + 66 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_var.c + finsh_var.c + + + 9 + 67 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_vm.c + finsh_vm.c + + + 9 + 68 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/finsh/finsh_token.c + finsh_token.c + + + + + LwIP + 0 + 0 + 0 + + 10 + 69 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/api_lib.c + api_lib.c + + + 10 + 70 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/api_msg.c + api_msg.c + + + 10 + 71 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/err.c + err.c + + + 10 + 72 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/netbuf.c + netbuf.c + + + 10 + 73 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/netdb.c + netdb.c + + + 10 + 74 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/netifapi.c + netifapi.c + + + 10 + 75 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/sockets.c + sockets.c + + + 10 + 76 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/api/tcpip.c + tcpip.c + + + 10 + 77 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/arch/sys_arch.c + sys_arch.c + + + 10 + 78 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/def.c + def.c + + + 10 + 79 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/dhcp.c + dhcp.c + + + 10 + 80 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/dns.c + dns.c + + + 10 + 81 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/init.c + init.c + + + 10 + 82 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/memp.c + memp.c + + + 10 + 83 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/netif.c + netif.c + + + 10 + 84 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/pbuf.c + pbuf.c + + + 10 + 85 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/raw.c + raw.c + + + 10 + 86 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/stats.c + stats.c + + + 10 + 87 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/sys.c + sys.c + + + 10 + 88 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/tcp.c + tcp.c + + + 10 + 89 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/tcp_in.c + tcp_in.c + + + 10 + 90 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/tcp_out.c + tcp_out.c + + + 10 + 91 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/timers.c + timers.c + + + 10 + 92 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/udp.c + udp.c + + + 10 + 93 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c + autoip.c + + + 10 + 94 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c + icmp.c + + + 10 + 95 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c + igmp.c + + + 10 + 96 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c + inet.c + + + 10 + 97 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c + inet_chksum.c + + + 10 + 98 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c + ip.c + + + 10 + 99 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c + ip_addr.c + + + 10 + 100 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c + ip_frag.c + + + 10 + 101 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/netif/etharp.c + etharp.c + + + 10 + 102 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/netif/ethernetif.c + ethernetif.c + + + 10 + 103 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ../../components/net/lwip-1.4.1/src/netif/slipif.c + slipif.c + diff --git a/bsp/CME_M7/project.uvproj b/bsp/CME_M7/project.uvproj index 9a1283bdcc..44f7d87d47 100644 --- a/bsp/CME_M7/project.uvproj +++ b/bsp/CME_M7/project.uvproj @@ -1,7 +1,10 @@ + 1.1 +
### uVision Project, (C) Keil Software
+ rtthread @@ -11,31 +14,28 @@ ARMCM3 ARM - ARM.CMSIS.4.1.0 - http://www.keil.com/pack/ CPUTYPE("Cortex-M3") CLOCK(10000000) ESEL ELITTLE - - - + + + 0 $$Device:ARMCM3$Device\ARM\ARMCM3\Include\ARMCM3.h - - - - - - - - - + + + + + + + + + $$Device:ARMCM3$Device\ARM\SVD\ARMCM3.svd - 0 0 - - - - - + + + + + 0 0 @@ -57,8 +57,8 @@ 0 0 - - + + 0 0 0 @@ -67,23 +67,21 @@ 0 0 - - + + 0 0 - 0 - 0 0 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 - + 0 @@ -97,9 +95,8 @@ 0 0 3 - - - 1 + + SARMCM3.DLL @@ -107,7 +104,7 @@ DCM.DLL -pCM3 SARMCM3.DLL - + TCM.DLL -pCM3 @@ -129,7 +126,6 @@ 1 1 0 - 1 1 @@ -140,25 +136,22 @@ 1 0 1 - 1 - 1 - 1 0 - 17 + 15 - - - - - + + + + + - - - - - + + + + + CapitalMicro\BIN\cmagdi.dll @@ -171,14 +164,9 @@ 1 4097 - 0 BIN\UL2CM3.DLL "" () - - - - - 0 + @@ -210,7 +198,7 @@ 0 0 "Cortex-M3" - + 0 0 0 @@ -341,7 +329,7 @@ 0x0 - + 1 @@ -357,12 +345,10 @@ 2 0 0 - 0 - 0 - + RT_USING_ARM_LIBC - + StdPeriph_Driver/inc;applications;.;drivers;CMSIS/CME_M7;../../components/CMSIS/Include;../../include;../../libcpu/arm/cortex-m3;../../libcpu/arm/common;../../components/libc/armlibc;../../components/drivers/include;../../components/drivers/include;../../components/finsh;../../components/net/lwip-1.4.1/src;../../components/net/lwip-1.4.1/src/include;../../components/net/lwip-1.4.1/src/include/ipv4;../../components/net/lwip-1.4.1/src/arch/include;../../components/net/lwip-1.4.1/src/include/netif @@ -375,12 +361,11 @@ 0 0 0 - 0 - - - - + + + + @@ -392,13 +377,12 @@ 0 0x00000000 0x00000000 - CME_M7.sct - - + + --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - + + @@ -411,113 +395,81 @@ 1 StdPeriph_Driver/src/cmem7_adc.c - - cmem7_aes.c 1 StdPeriph_Driver/src/cmem7_aes.c - - cmem7_can.c 1 StdPeriph_Driver/src/cmem7_can.c - - cmem7_ddr.c 1 StdPeriph_Driver/src/cmem7_ddr.c - - cmem7_dma.c 1 StdPeriph_Driver/src/cmem7_dma.c - - cmem7_efuse.c 1 StdPeriph_Driver/src/cmem7_efuse.c - - cmem7_eth.c 1 StdPeriph_Driver/src/cmem7_eth.c - - cmem7_flash.c 1 StdPeriph_Driver/src/cmem7_flash.c - - cmem7_gpio.c 1 StdPeriph_Driver/src/cmem7_gpio.c - - cmem7_i2c.c 1 StdPeriph_Driver/src/cmem7_i2c.c - - cmem7_misc.c 1 StdPeriph_Driver/src/cmem7_misc.c - - cmem7_rtc.c 1 StdPeriph_Driver/src/cmem7_rtc.c - - cmem7_spi.c 1 StdPeriph_Driver/src/cmem7_spi.c - - cmem7_tim.c 1 StdPeriph_Driver/src/cmem7_tim.c - - cmem7_uart.c 1 StdPeriph_Driver/src/cmem7_uart.c - - cmem7_usb.c 1 StdPeriph_Driver/src/cmem7_usb.c - - cmem7_wdg.c 1 @@ -533,15 +485,11 @@ 1 applications/application.c - - led.c 1 applications/led.c - - startup.c 1 @@ -557,22 +505,16 @@ 1 drivers/board.c - - uart.c 1 drivers/uart.c - - emac.c 1 drivers/emac.c - - app_phy.c 1 @@ -588,8 +530,6 @@ 1 CMSIS/CME_M7/system_cmem7.c - - startup_cmem7.s 2 @@ -605,85 +545,61 @@ 1 ../../src/clock.c - - components.c 1 ../../src/components.c - - device.c 1 ../../src/device.c - - idle.c 1 ../../src/idle.c - - ipc.c 1 ../../src/ipc.c - - irq.c 1 ../../src/irq.c - - kservice.c 1 ../../src/kservice.c - - mem.c 1 ../../src/mem.c - - mempool.c 1 ../../src/mempool.c - - object.c 1 ../../src/object.c - - scheduler.c 1 ../../src/scheduler.c - - thread.c 1 ../../src/thread.c - - timer.c 1 @@ -699,29 +615,21 @@ 1 ../../libcpu/arm/cortex-m3/cpuport.c - - context_rvds.S 2 ../../libcpu/arm/cortex-m3/context_rvds.S - - backtrace.c 1 ../../libcpu/arm/common/backtrace.c - - div0.c 1 ../../libcpu/arm/common/div0.c - - showmem.c 1 @@ -737,8 +645,6 @@ 1 ../../components/libc/armlibc/mem_std.c - - stubs.c 1 @@ -754,43 +660,31 @@ 1 ../../components/drivers/serial/serial.c - - completion.c 1 ../../components/drivers/src/completion.c - - dataqueue.c 1 ../../components/drivers/src/dataqueue.c - - pipe.c 1 ../../components/drivers/src/pipe.c - - portal.c 1 ../../components/drivers/src/portal.c - - ringbuffer.c 1 ../../components/drivers/src/ringbuffer.c - - workqueue.c 1 @@ -806,99 +700,71 @@ 1 ../../components/finsh/shell.c - - symbol.c 1 ../../components/finsh/symbol.c - - cmd.c 1 ../../components/finsh/cmd.c - - msh_cmd.c 1 ../../components/finsh/msh_cmd.c - - msh.c 1 ../../components/finsh/msh.c - - finsh_compiler.c 1 ../../components/finsh/finsh_compiler.c - - finsh_error.c 1 ../../components/finsh/finsh_error.c - - finsh_heap.c 1 ../../components/finsh/finsh_heap.c - - finsh_init.c 1 ../../components/finsh/finsh_init.c - - finsh_node.c 1 ../../components/finsh/finsh_node.c - - finsh_ops.c 1 ../../components/finsh/finsh_ops.c - - finsh_parser.c 1 ../../components/finsh/finsh_parser.c - - finsh_var.c 1 ../../components/finsh/finsh_var.c - - finsh_vm.c 1 ../../components/finsh/finsh_vm.c - - finsh_token.c 1 @@ -914,239 +780,171 @@ 1 ../../components/net/lwip-1.4.1/src/api/api_lib.c - - api_msg.c 1 ../../components/net/lwip-1.4.1/src/api/api_msg.c - - err.c 1 ../../components/net/lwip-1.4.1/src/api/err.c - - netbuf.c 1 ../../components/net/lwip-1.4.1/src/api/netbuf.c - - netdb.c 1 ../../components/net/lwip-1.4.1/src/api/netdb.c - - netifapi.c 1 ../../components/net/lwip-1.4.1/src/api/netifapi.c - - sockets.c 1 ../../components/net/lwip-1.4.1/src/api/sockets.c - - tcpip.c 1 ../../components/net/lwip-1.4.1/src/api/tcpip.c - - sys_arch.c 1 ../../components/net/lwip-1.4.1/src/arch/sys_arch.c - - def.c 1 ../../components/net/lwip-1.4.1/src/core/def.c - - dhcp.c 1 ../../components/net/lwip-1.4.1/src/core/dhcp.c - - dns.c 1 ../../components/net/lwip-1.4.1/src/core/dns.c - - init.c 1 ../../components/net/lwip-1.4.1/src/core/init.c - - memp.c 1 ../../components/net/lwip-1.4.1/src/core/memp.c - - netif.c 1 ../../components/net/lwip-1.4.1/src/core/netif.c - - pbuf.c 1 ../../components/net/lwip-1.4.1/src/core/pbuf.c - - raw.c 1 ../../components/net/lwip-1.4.1/src/core/raw.c - - stats.c 1 ../../components/net/lwip-1.4.1/src/core/stats.c - - sys.c 1 ../../components/net/lwip-1.4.1/src/core/sys.c - - tcp.c 1 ../../components/net/lwip-1.4.1/src/core/tcp.c - - tcp_in.c 1 ../../components/net/lwip-1.4.1/src/core/tcp_in.c - - tcp_out.c 1 ../../components/net/lwip-1.4.1/src/core/tcp_out.c - - timers.c 1 ../../components/net/lwip-1.4.1/src/core/timers.c - - udp.c 1 ../../components/net/lwip-1.4.1/src/core/udp.c - - autoip.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/autoip.c - - icmp.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/icmp.c - - igmp.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/igmp.c - - inet.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/inet.c - - inet_chksum.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/inet_chksum.c - - ip.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/ip.c - - ip_addr.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/ip_addr.c - - ip_frag.c 1 ../../components/net/lwip-1.4.1/src/core/ipv4/ip_frag.c - - etharp.c 1 ../../components/net/lwip-1.4.1/src/netif/etharp.c - - ethernetif.c 1 ../../components/net/lwip-1.4.1/src/netif/ethernetif.c - - slipif.c 1 @@ -1157,4 +955,5 @@ + From 73df162d3f9de24158eec9cc66f2662ecd9ec269 Mon Sep 17 00:00:00 2001 From: aozima Date: Wed, 13 May 2015 11:54:10 +0800 Subject: [PATCH 11/18] fixed assembly warnings. --- libcpu/arm/cortex-m0/context_rvds.S | 4 ++-- libcpu/arm/cortex-m3/context_rvds.S | 6 +++--- libcpu/arm/cortex-m4/context_rvds.S | 3 ++- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S index 89ac029282..bf68592e63 100644 --- a/libcpu/arm/cortex-m0/context_rvds.S +++ b/libcpu/arm/cortex-m0/context_rvds.S @@ -183,13 +183,11 @@ rt_hw_context_switch_to PROC LDR r0, =NVIC_INT_CTRL LDR r1, =NVIC_PENDSVSET STR r1, [r0] - NOP ; restore MSP LDR r0, =SCB_VTOR LDR r0, [r0] LDR r0, [r0] - NOP MSR msp, r0 ; enable interrupts at processor level @@ -216,4 +214,6 @@ HardFault_Handler PROC POP {pc} ENDP + ALIGN 4 + END diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S index 33fcd124d9..ebfd5c8da8 100644 --- a/libcpu/arm/cortex-m3/context_rvds.S +++ b/libcpu/arm/cortex-m3/context_rvds.S @@ -177,7 +177,6 @@ rt_hw_context_switch_to PROC rt_hw_interrupt_thread_switch PROC EXPORT rt_hw_interrupt_thread_switch BX lr - NOP ENDP IMPORT rt_hw_hard_fault_exception @@ -203,5 +202,6 @@ HardFault_Handler PROC BX lr ENDP - NOP - END \ No newline at end of file + ALIGN 4 + + END diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S index af7461fd49..d7cb34d5c3 100644 --- a/libcpu/arm/cortex-m4/context_rvds.S +++ b/libcpu/arm/cortex-m4/context_rvds.S @@ -218,7 +218,6 @@ rt_hw_context_switch_to PROC rt_hw_interrupt_thread_switch PROC EXPORT rt_hw_interrupt_thread_switch BX lr - NOP ENDP IMPORT rt_hw_hard_fault_exception @@ -235,4 +234,6 @@ HardFault_Handler PROC BX lr ENDP + ALIGN 4 + END From 8257a629905b28e8616b1e9b7f9f6cfd60f0c4dd Mon Sep 17 00:00:00 2001 From: heyuanjie87 Date: Wed, 13 May 2015 21:07:31 +0800 Subject: [PATCH 12/18] =?UTF-8?q?[stm32f4]=E6=9B=B4=E6=96=B0mdk5=E5=B7=A5?= =?UTF-8?q?=E7=A8=8B=E6=96=87=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32f40x/project.uvprojx | 64 +++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 7 deletions(-) diff --git a/bsp/stm32f40x/project.uvprojx b/bsp/stm32f40x/project.uvprojx index 50bd41f02b..9061692cce 100644 --- a/bsp/stm32f40x/project.uvprojx +++ b/bsp/stm32f40x/project.uvprojx @@ -365,7 +365,7 @@ USE_STDPERIPH_DRIVER - .;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;Libraries\CMSIS\Include;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\STM32F4xx_StdPeriph_Driver\inc;applications;drivers + .;..\..\components\drivers\include;..\..\components\finsh;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;Libraries\CMSIS\Include;Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\STM32F4xx_StdPeriph_Driver\inc;applications;drivers @@ -398,7 +398,7 @@ - --keep __fsym_* --keep __vsym_* + --keep *.o(FSymTab) --keep *.o(VSymTab) @@ -428,11 +428,6 @@ 1 drivers\board.c - - serial.c - 1 - drivers\serial.c - stm32f4xx_it.c 1 @@ -443,6 +438,11 @@ 1 drivers\usart.c + + gpio.c + 1 + drivers\gpio.c + @@ -623,6 +623,11 @@ 1 ..\..\src\clock.c + + components.c + 1 + ..\..\src\components.c + device.c 1 @@ -710,6 +715,51 @@ + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + portal.c + 1 + ..\..\components\drivers\src\portal.c + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + finsh From 2f5c5b676ddd1db13d2b850e39b6fbfb000f907e Mon Sep 17 00:00:00 2001 From: BernardXiong Date: Wed, 13 May 2015 21:28:02 +0800 Subject: [PATCH 13/18] [DeviceDrivers] Add GD25Q flash id in w25qxx.c --- components/drivers/spi/spi_flash_w25qxx.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/components/drivers/spi/spi_flash_w25qxx.c b/components/drivers/spi/spi_flash_w25qxx.c index bdcdbd83c1..6e002c38c8 100644 --- a/components/drivers/spi/spi_flash_w25qxx.c +++ b/components/drivers/spi/spi_flash_w25qxx.c @@ -13,6 +13,7 @@ * 2012-05-06 aozima can page write. * 2012-08-23 aozima add flash lock. * 2012-08-24 aozima fixed write status register BUG. + * 2015-05-13 bernard add GD25Q flash ID. */ #include @@ -28,8 +29,10 @@ #define PAGE_SIZE 4096 -/* JEDEC Manufacturers ID */ +/* JEDEC Manufacturer��s ID */ #define MF_ID (0xEF) +#define GD_ID (0xC8) + /* JEDEC Device ID: Memory type and Capacity */ #define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */ #define MTC_W25Q16_DW (0x6015) /* W25Q16DW */ @@ -297,7 +300,7 @@ rt_err_t w25qxx_init(const char * flash_device_name, const char * spi_device_nam flash_unlock(&spi_flash_device); - if(id_recv[0] != MF_ID) + if(id_recv[0] != MF_ID && id_recv[0] != GD_ID) { FLASH_TRACE("Manufacturers ID error!\r\n"); FLASH_TRACE("JEDEC Read-ID Data : %02X %02X %02X\r\n", id_recv[0], id_recv[1], id_recv[2]); From eb56b832ef2528c9b9dd48c8df98c5311ac42daa Mon Sep 17 00:00:00 2001 From: "Aubr.Cool" Date: Thu, 14 May 2015 15:44:06 +0800 Subject: [PATCH 14/18] Add Can Drv --- bsp/stm32f10x/applications/canapp.c | 141 +++ bsp/stm32f10x/drivers/bxcan.c | 1411 ++++++++++++++++++++++ bsp/stm32f10x/drivers/bxcan.h | 16 + components/drivers/can/can.c | 906 ++++++++++++++ components/drivers/include/drivers/can.h | 292 +++++ components/drivers/include/rtdevice.h | 4 + 6 files changed, 2770 insertions(+) create mode 100644 bsp/stm32f10x/applications/canapp.c create mode 100644 bsp/stm32f10x/drivers/bxcan.c create mode 100644 bsp/stm32f10x/drivers/bxcan.h create mode 100644 components/drivers/can/can.c create mode 100644 components/drivers/include/drivers/can.h diff --git a/bsp/stm32f10x/applications/canapp.c b/bsp/stm32f10x/applications/canapp.c new file mode 100644 index 0000000000..7a77df4265 --- /dev/null +++ b/bsp/stm32f10x/applications/canapp.c @@ -0,0 +1,141 @@ +/* + * File : canapp.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ +#include +#include +#include +struct can_app_struct +{ + const char* name; + struct rt_event event; + struct rt_can_filter_config * filter; + rt_uint8_t eventopt; +}; +static struct can_app_struct can_data[2]; +static rt_err_t can1ind(rt_device_t dev, void* args, rt_int32_t hdr, rt_size_t size) +{ + rt_event_t pevent = (rt_event_t)args; + rt_event_send(pevent, 1 << (hdr)); + return RT_EOK; +} +static rt_err_t can2ind(rt_device_t dev, void* args, rt_int32_t hdr, rt_size_t size) +{ + rt_event_t pevent = (rt_event_t)args; + rt_event_send(pevent, 1 << (hdr)); + return RT_EOK; +} +struct rt_can_filter_item filter1item[4] = +{ + RT_CAN_FILTER_STD_INIT(1,can1ind,&can_data[0].event), + RT_CAN_FILTER_STD_INIT(2,can1ind,&can_data[0].event), + RT_CAN_STD_RMT_FILTER_INIT(3,can1ind,&can_data[0].event), + RT_CAN_STD_RMT_DATA_FILTER_INIT(4,can1ind,&can_data[0].event), +}; +struct rt_can_filter_item filter2item[4] = +{ + RT_CAN_FILTER_STD_INIT(1,can2ind,&can_data[1].event), + RT_CAN_FILTER_STD_INIT(2,can2ind,&can_data[1].event), + RT_CAN_STD_RMT_FILTER_INIT(3,can2ind,&can_data[1].event), + RT_CAN_STD_RMT_DATA_FILTER_INIT(4,can2ind,&can_data[1].event), +}; +struct rt_can_filter_config filter1 = +{ + .count = 4, + .actived = 1, + .items = filter1item, +}; +struct rt_can_filter_config filter2 = +{ + .count = 4, + .actived = 1, + .items = filter2item, +}; +static struct can_app_struct can_data[2] = { + { + .name = "bxcan1", + .filter = &filter1, + .eventopt = RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR, + }, + { + .name = "bxcan2", + .filter = &filter2, + .eventopt = RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, + }, +}; +void rt_can_thread_entry(void* parameter) +{ + struct rt_can_msg msg; + struct can_app_struct* canpara = (struct can_app_struct*) parameter; + rt_device_t candev; + rt_uint32_t e; + + candev = rt_device_find(canpara->name); + RT_ASSERT(candev); + rt_event_init(&canpara->event, canpara->name, RT_IPC_FLAG_FIFO); + rt_device_open(candev, (RT_DEVICE_OFLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX)); + rt_device_control(candev,RT_CAN_CMD_SET_FILTER,canpara->filter); + while(1) { + if ( + rt_event_recv(&canpara->event, + ((1 << canpara->filter->items[0].hdr) | + (1 << canpara->filter->items[1].hdr) | + (1 << canpara->filter->items[2].hdr) | + (1 << canpara->filter->items[3].hdr)), + canpara->eventopt, + RT_WAITING_FOREVER, &e) != RT_EOK + ) { + continue; + } + if(e & (1 << canpara->filter->items[0].hdr)) { + msg.hdr = canpara->filter->items[0].hdr; + while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) { + rt_device_write(candev, 0, &msg, sizeof(msg)); + } + } + if(e & (1 << canpara->filter->items[1].hdr)) { + msg.hdr = canpara->filter->items[1].hdr; + while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) { + rt_device_write(candev, 0, &msg, sizeof(msg)); + } + } + if(e & (1 << canpara->filter->items[2].hdr)) { + msg.hdr = canpara->filter->items[2].hdr; + while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) { + rt_device_write(candev, 0, &msg, sizeof(msg)); + } + } + if(e & (1 << canpara->filter->items[3].hdr)) { + msg.hdr = canpara->filter->items[3].hdr; + while (rt_device_read(candev, 0, &msg, sizeof(msg)) == sizeof(msg)) { + rt_device_write(candev, 0, &msg, sizeof(msg)); + } + } + } +} +int rt_can_app_init(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("canapp1", + rt_can_thread_entry, &can_data[0], + 512, RT_THREAD_PRIORITY_MAX /3 - 1, 20); + if (tid != RT_NULL) rt_thread_startup(tid); + + tid = rt_thread_create("canapp2", + rt_can_thread_entry, &can_data[1], + 512, RT_THREAD_PRIORITY_MAX /3 - 1, 20); + if (tid != RT_NULL) rt_thread_startup(tid); + + return 0; +} + +INIT_APP_EXPORT(rt_can_app_init); diff --git a/bsp/stm32f10x/drivers/bxcan.c b/bsp/stm32f10x/drivers/bxcan.c new file mode 100644 index 0000000000..0454991708 --- /dev/null +++ b/bsp/stm32f10x/drivers/bxcan.c @@ -0,0 +1,1411 @@ +/* + * File : bxcan.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ +#include +#include +#include +#include +#ifdef RT_USING_COMPONENTS_INIT +#include +#endif +#ifdef RT_USING_CAN + +#ifndef STM32F10X_CL +#define BX_CAN_FMRNUMBER 14 +#define BX_CAN2_FMRSTART 7 +#else +#define BX_CAN_FMRNUMBER 28 +#define BX_CAN2_FMRSTART 14 +#endif + +#define BX_CAN_MAX_FILTERS (BX_CAN_FMRNUMBER * 4) +#define BX_CAN_MAX_FILTER_MASKS BX_CAN_MAX_FILTERS +#define BX_CAN_FILTER_MAX_ARRAY_SIZE ((BX_CAN_MAX_FILTERS + 32 - 1) / 32) + +struct stm_bxcanfiltermap { + rt_uint32_t id32mask_cnt; + rt_uint32_t id32bit_cnt; + rt_uint32_t id16mask_cnt; + rt_uint32_t id16bit_cnt; +}; +struct stm_bxcanfilter_masks { + rt_uint32_t id32maskm[BX_CAN_FILTER_MAX_ARRAY_SIZE]; + rt_uint32_t id32bitm[BX_CAN_FILTER_MAX_ARRAY_SIZE]; + rt_uint32_t id16maskm[BX_CAN_FILTER_MAX_ARRAY_SIZE]; + rt_uint32_t id16bitm[BX_CAN_FILTER_MAX_ARRAY_SIZE]; + rt_uint32_t id32maskshift[2]; + rt_uint32_t id32bitshift[2]; + rt_uint32_t id16maskshift[2]; + rt_uint32_t id16bitshift[2]; +}; +struct stm_bxcan +{ + CAN_TypeDef* reg; + void* mfrbase; + IRQn_Type sndirq; + IRQn_Type rcvirq0; + IRQn_Type rcvirq1; + IRQn_Type errirq; + struct stm_bxcanfilter_masks filtermask; + rt_uint32_t alocmask[BX_CAN_FILTER_MAX_ARRAY_SIZE]; + const rt_uint32_t filtercnt; + const rt_uint32_t fifo1filteroff; + const struct stm_bxcanfiltermap filtermap[2]; +}; +static void calcfiltermasks(struct stm_bxcan *pbxcan); +static void bxcan1_filter_init(struct rt_can_device *can) +{ + rt_uint32_t i; + rt_uint32_t mask; + struct stm_bxcan *pbxcan = (struct stm_bxcan *) can->parent.user_data; + for(i = 0; i < BX_CAN2_FMRSTART; i++) { + CAN1->FMR |= FMR_FINIT; + mask = 0x01 << (i + 0); + if(i < pbxcan->fifo1filteroff) { + if(pbxcan->filtermap[0].id32mask_cnt && i < pbxcan->filtermap[0].id32mask_cnt) { + CAN1->FS1R |= mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R &= ~mask; + } else if(pbxcan->filtermap[0].id32bit_cnt && + i < pbxcan->filtermap[0].id32mask_cnt + pbxcan->filtermap[0].id32bit_cnt /2) { + CAN1->FS1R |= mask; + CAN1->FM1R |= mask; + CAN1->FFA1R &= ~mask; + } else if(pbxcan->filtermap[0].id16mask_cnt && + i < pbxcan->filtermap[0].id32mask_cnt + pbxcan->filtermap[0].id32bit_cnt /2 + + pbxcan->filtermap[0].id16mask_cnt /2) { + CAN1->FS1R &= ~mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R &= ~mask; + } else if(pbxcan->filtermap[0].id16bit_cnt && + i < pbxcan->filtermap[0].id32mask_cnt + pbxcan->filtermap[0].id32bit_cnt /2 + + pbxcan->filtermap[0].id16mask_cnt /2 + pbxcan->filtermap[0].id16bit_cnt / 4 + ) { + CAN1->FS1R &= ~mask; + CAN1->FM1R |= mask; + CAN1->FFA1R &= ~mask; + } + } else { + if(pbxcan->filtermap[1].id32mask_cnt && + i < pbxcan->filtermap[1].id32mask_cnt + pbxcan->fifo1filteroff) { + CAN1->FS1R |= mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R |= mask; + } else if(pbxcan->filtermap[1].id32bit_cnt && + i < pbxcan->filtermap[1].id32mask_cnt + pbxcan->filtermap[1].id32bit_cnt /2 + + pbxcan->fifo1filteroff) { + CAN1->FS1R |= mask; + CAN1->FM1R |= mask; + CAN1->FFA1R |= mask; + } else if(pbxcan->filtermap[1].id16mask_cnt && + i < pbxcan->filtermap[1].id32mask_cnt + pbxcan->filtermap[1].id32bit_cnt /2 + + pbxcan->filtermap[1].id16mask_cnt / 2 + pbxcan->fifo1filteroff) { + CAN1->FS1R &= ~mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R |= mask; + } else if(pbxcan->filtermap[1].id16bit_cnt && + i < pbxcan->filtermap[1].id32mask_cnt + pbxcan->filtermap[1].id32bit_cnt /2 + + pbxcan->filtermap[1].id16mask_cnt /2 + pbxcan->filtermap[1].id16bit_cnt / 4 + + pbxcan->fifo1filteroff) { + CAN1->FS1R &= ~mask; + CAN1->FM1R |= mask; + CAN1->FFA1R |= mask; + } + } + CAN1->sFilterRegister[i].FR1 = 0xFFFFFFFF; + CAN1->sFilterRegister[i].FR2 = 0xFFFFFFFF; + CAN1->FMR &= ~FMR_FINIT; + } + calcfiltermasks(pbxcan); +} +static void bxcan2_filter_init(struct rt_can_device *can) +{ + rt_uint32_t i; + rt_uint32_t off; + rt_uint32_t mask; + CAN_SlaveStartBank(BX_CAN2_FMRSTART); + struct stm_bxcan *pbxcan = (struct stm_bxcan *) can->parent.user_data; + for(i = BX_CAN2_FMRSTART; i < BX_CAN_FMRNUMBER; i++) { + CAN1->FMR |= FMR_FINIT; + mask = 0x01 << (i + 0); + off = i - BX_CAN2_FMRSTART; + if(i < pbxcan->fifo1filteroff) { + if(pbxcan->filtermap[0].id32mask_cnt && off < pbxcan->filtermap[0].id32mask_cnt) { + CAN1->FS1R |= mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R &= ~mask; + } else if(pbxcan->filtermap[0].id32bit_cnt && + off < pbxcan->filtermap[0].id32mask_cnt + pbxcan->filtermap[0].id32bit_cnt /2) { + CAN1->FS1R |= mask; + CAN1->FM1R |= mask; + CAN1->FFA1R &= ~mask; + } else if(pbxcan->filtermap[0].id16mask_cnt && + off < pbxcan->filtermap[0].id32mask_cnt + pbxcan->filtermap[0].id32bit_cnt /2 + + pbxcan->filtermap[0].id16mask_cnt /2) { + CAN1->FS1R &= ~mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R &= ~mask; + } else if(pbxcan->filtermap[0].id16bit_cnt && + off < pbxcan->filtermap[0].id32mask_cnt + pbxcan->filtermap[0].id32bit_cnt /2 + + pbxcan->filtermap[0].id16mask_cnt /2 + pbxcan->filtermap[0].id16bit_cnt / 4 + ) { + CAN1->FS1R &= ~mask; + CAN1->FM1R |= mask; + CAN1->FFA1R &= ~mask; + } + } else { + if(pbxcan->filtermap[1].id32mask_cnt && + off < pbxcan->filtermap[1].id32mask_cnt + pbxcan->fifo1filteroff) { + CAN1->FS1R |= mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R |= mask; + } else if(pbxcan->filtermap[1].id32bit_cnt && + off < pbxcan->filtermap[1].id32mask_cnt + pbxcan->filtermap[1].id32bit_cnt /2 + + pbxcan->fifo1filteroff) { + CAN1->FS1R |= mask; + CAN1->FM1R |= mask; + CAN1->FFA1R |= mask; + } else if(pbxcan->filtermap[1].id16mask_cnt && + off < pbxcan->filtermap[1].id32mask_cnt + pbxcan->filtermap[1].id32bit_cnt /2 + + pbxcan->filtermap[1].id16mask_cnt / 2 + pbxcan->fifo1filteroff) { + CAN1->FS1R &= ~mask; + CAN1->FM1R &= ~mask; + CAN1->FFA1R |= mask; + } else if(pbxcan->filtermap[1].id16bit_cnt && + off < pbxcan->filtermap[1].id32mask_cnt + pbxcan->filtermap[1].id32bit_cnt /2 + + pbxcan->filtermap[1].id16mask_cnt /2 + pbxcan->filtermap[1].id16bit_cnt / 4 + + pbxcan->fifo1filteroff) { + CAN1->FS1R &= ~mask; + CAN1->FM1R |= mask; + CAN1->FFA1R |= mask; + } + } + CAN1->sFilterRegister[i].FR1 = 0xFFFFFFFF; + CAN1->sFilterRegister[i].FR2 = 0xFFFFFFFF; + CAN1->FMR &= ~FMR_FINIT; + } + calcfiltermasks(pbxcan); +} +#define BS1SHIFT 16 +#define BS2SHIFT 20 +#define RRESCLSHIFT 0 +#define SJWSHIFT 24 +#define BS1MASK ( (0x0F) << BS1SHIFT ) +#define BS2MASK ( (0x07) << BS2SHIFT ) +#define RRESCLMASK ( 0x3FF << RRESCLSHIFT ) +#define SJWMASK ( 0x3 << SJWSHIFT ) + +#define MK_BKCAN_BAUD(SJW,BS1,BS2,PRES) \ + ((SJW << SJWSHIFT) | (BS1 << BS1SHIFT) | (BS2 << BS2SHIFT) | (PRES << RRESCLSHIFT)) + +static const rt_uint32_t bxcan_baud_rate_tab[] = +{ + // 48 M + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_12tq,CAN_BS2_3tq,3), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_6tq,CAN_BS2_3tq,6), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_12tq,CAN_BS2_3tq,5), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_12tq,CAN_BS2_3tq,11), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_12tq,CAN_BS2_3tq,23), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_12tq,CAN_BS2_3tq,29), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_12tq,CAN_BS2_3tq,59), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_14tq,CAN_BS2_3tq,149), + MK_BKCAN_BAUD(CAN_SJW_2tq,CAN_BS1_16tq,CAN_BS2_8tq,199), +}; + +#define BAUD_DATA(TYPE,NO) \ + ((bxcan_baud_rate_tab[NO] & TYPE##MASK) >> TYPE##SHIFT) + +static void bxcan_init(CAN_TypeDef* pcan, rt_uint32_t baud, rt_uint32_t mode) +{ + CAN_InitTypeDef CAN_InitStructure; + + CAN_InitStructure.CAN_TTCM = DISABLE; + CAN_InitStructure.CAN_ABOM = ENABLE; + CAN_InitStructure.CAN_AWUM = DISABLE; + CAN_InitStructure.CAN_NART = DISABLE; + CAN_InitStructure.CAN_RFLM = DISABLE; + CAN_InitStructure.CAN_TXFP = ENABLE; + switch(mode) + { + case RT_CAN_MODE_NORMAL: + CAN_InitStructure.CAN_Mode = CAN_Mode_Normal; + break; + case RT_CAN_MODE_LISEN: + CAN_InitStructure.CAN_Mode = CAN_Mode_Silent; + break; + case RT_CAN_MODE_LOOPBACK: + CAN_InitStructure.CAN_Mode = CAN_Mode_LoopBack; + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + CAN_InitStructure.CAN_Mode = CAN_Mode_Silent_LoopBack; + break; + } + CAN_InitStructure.CAN_SJW = BAUD_DATA(SJW,baud); + CAN_InitStructure.CAN_BS1 = BAUD_DATA(BS1,baud); + CAN_InitStructure.CAN_BS2 = BAUD_DATA(BS2,baud); + CAN_InitStructure.CAN_Prescaler =BAUD_DATA(RRESCL,baud); + + CAN_Init(pcan, &CAN_InitStructure); +} +static void bxcan1_hw_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1 , ENABLE); + + CAN_DeInit(CAN1); + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX0_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0; + NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = CAN1_RX1_IRQn; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = CAN1_TX_IRQn; + NVIC_Init(&NVIC_InitStructure); +} +static void bxcan2_hw_init(void) +{ + GPIO_InitTypeDef GPIO_InitStructure; + NVIC_InitTypeDef NVIC_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); + + CAN_DeInit(CAN2); + + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX0_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0; + NVIC_InitStructure.NVIC_IRQChannelCmd = DISABLE; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = CAN2_RX1_IRQn; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = CAN2_TX_IRQn; + NVIC_Init(&NVIC_InitStructure); +} +static inline rt_err_t bxcan_enter_init(CAN_TypeDef* pcan) +{ + uint32_t wait_ack = 0x00000000; + + pcan->MCR |= CAN_MCR_INRQ ; + + while (((pcan->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + if ((pcan->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + return RT_ERROR; + } + return RT_EOK; +} +static inline rt_err_t bxcan_exit_init(CAN_TypeDef* pcan) +{ + uint32_t wait_ack = 0x00000000; + + pcan->MCR &= ~(uint32_t)CAN_MCR_INRQ; + + while (((pcan->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + if ((pcan->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) + { + return RT_ERROR; + } + return RT_EOK; +} +static rt_err_t bxcan_set_mode(CAN_TypeDef* pcan, rt_uint32_t mode) +{ + if(bxcan_enter_init(pcan) != RT_EOK) + { + return RT_ERROR; + } + pcan->BTR &= ~(uint32_t)((uint32_t)0x03 << 30); + switch(mode) + { + case RT_CAN_MODE_NORMAL: + mode = CAN_Mode_Normal; + break; + case RT_CAN_MODE_LISEN: + mode = CAN_Mode_Silent; + break; + case RT_CAN_MODE_LOOPBACK: + mode = CAN_Mode_LoopBack; + break; + case RT_CAN_MODE_LOOPBACKANLISEN: + mode = CAN_Mode_Silent_LoopBack; + break; + } + pcan->BTR |= ~(uint32_t)(mode << 30); + if(bxcan_exit_init(pcan) != RT_EOK) + { + return RT_ERROR; + } + return RT_EOK; +} +static rt_err_t bxcan_set_privmode(CAN_TypeDef* pcan, rt_uint32_t mode) +{ + if(bxcan_enter_init(pcan) != RT_EOK) + { + return RT_ERROR; + } + if (mode == ENABLE) + { + pcan->MCR |= CAN_MCR_TXFP; + } + else + { + pcan->MCR &= ~(uint32_t)CAN_MCR_TXFP; + } + if(bxcan_exit_init(pcan) != RT_EOK) + { + return RT_ERROR; + } + return RT_EOK; +} +static rt_err_t bxcan_set_baud_rate(CAN_TypeDef* pcan, rt_uint32_t baud) +{ + rt_uint32_t mode; + if(bxcan_enter_init(pcan) != RT_EOK) + { + return RT_ERROR; + } + pcan->BTR = 0; + mode = pcan->BTR & ((rt_uint32_t)0x03 << 30); + pcan->BTR = (mode | \ + ((BAUD_DATA(SJW,baud)) << 24) | \ + ((BAUD_DATA(BS1,baud)) << 16) | \ + ((BAUD_DATA(BS2,baud)) << 20) | \ + (BAUD_DATA(RRESCL,baud))); + if(bxcan_exit_init(pcan) != RT_EOK) + { + return RT_ERROR; + } + return RT_EOK; +} +static rt_err_t bxcancalcbaseoff(struct stm_bxcan *pbxcan, rt_int32_t hdr, + rt_int32_t * pbase, rt_int32_t * poff) +{ + rt_uint32_t fifo0start,fifo0end; + rt_uint32_t fifo1start,fifo1end; + rt_uint32_t ptr; + fifo0start = 0; + fifo0end = pbxcan->filtermap[0].id32mask_cnt + + pbxcan->filtermap[0].id32bit_cnt + + pbxcan->filtermap[0].id16mask_cnt + + pbxcan->filtermap[0].id16bit_cnt ; + fifo1start = pbxcan->fifo1filteroff * 4; + fifo1end = pbxcan->filtermap[1].id32mask_cnt + + pbxcan->filtermap[1].id32bit_cnt + + pbxcan->filtermap[1].id16mask_cnt + + pbxcan->filtermap[1].id16bit_cnt ; + if(hdr >= fifo0start && hdr < fifo0end) { + *pbase = 0; + ptr = 0; + } else if(hdr >= fifo1start && hdr < fifo1end) { + *pbase = pbxcan->fifo1filteroff; + ptr = 1; + } else { + return RT_ERROR; + } + ptr = 0; + if(hdr > pbxcan->filtermap[ptr].id32mask_cnt) { + hdr -= pbxcan->filtermap[ptr].id32mask_cnt; + *pbase += pbxcan->filtermap[ptr].id32mask_cnt; + } else { + *pbase += hdr; + *poff = 0; + return RT_EOK; + } + if(hdr > pbxcan->filtermap[ptr].id32bit_cnt) { + hdr -= pbxcan->filtermap[ptr].id32bit_cnt; + *pbase += pbxcan->filtermap[ptr].id32bit_cnt / 2; + } else { + *pbase += hdr / 2; + *poff = hdr % 2; + return RT_EOK; + } + if(hdr > pbxcan->filtermap[ptr].id16mask_cnt) { + hdr -= pbxcan->filtermap[ptr].id16mask_cnt; + *pbase += pbxcan->filtermap[ptr].id16mask_cnt / 2; + } else { + *pbase += hdr / 2; + *poff = hdr % 2; + return RT_EOK; + } + if(hdr > pbxcan->filtermap[ptr].id16bit_cnt) { + return RT_ERROR; + } else { + *pbase += hdr / 4; + *poff = hdr % 4; + return RT_EOK; + } +} +static void calcandormask(rt_uint32_t* pmask,rt_uint32_t shift,rt_int32_t count) +{ + rt_uint32_t tmpmask; + rt_uint32_t tmpmaskarray[BX_CAN_FILTER_MAX_ARRAY_SIZE] = {0,}; + rt_int32_t i; + i = 0; + while(count > 0) { + if(i >= 32) { + tmpmaskarray[i] = 0xFFFFFFFF; + } else { + tmpmaskarray[i] = (0x01 << count) - 1; + } + count -= 32; + i++; + }; + count = i; + for(i = 0; i < count && i < BX_CAN_FILTER_MAX_ARRAY_SIZE; i++) { + tmpmask = tmpmaskarray[i]; + pmask[i] |= (rt_uint32_t)(tmpmask << shift); + if(i < BX_CAN_FILTER_MAX_ARRAY_SIZE - 1) { + pmask[i + 1] |= (rt_uint32_t)(tmpmask >> (32 - shift)); + } + } +} +static void calcfiltermasks(struct stm_bxcan *pbxcan) +{ + rt_memset(&pbxcan->filtermask,0,sizeof(pbxcan->filtermask)); + pbxcan->filtermask.id32maskshift[0] = 0; + if(pbxcan->filtermap[0].id32mask_cnt) { + calcandormask(pbxcan->filtermask.id32maskm,pbxcan->filtermask.id32maskshift[0], + pbxcan->filtermap[0].id32mask_cnt); + } + pbxcan->filtermask.id32maskshift[1] = pbxcan->fifo1filteroff * 4; + if(pbxcan->filtermap[1].id32mask_cnt) { + calcandormask(pbxcan->filtermask.id32maskm,pbxcan->filtermask.id32maskshift[1], + pbxcan->filtermap[1].id32mask_cnt); + } + pbxcan->filtermask.id32bitshift[0] = pbxcan->filtermask.id32maskshift[0] + + pbxcan->filtermap[0].id32mask_cnt; + if(pbxcan->filtermap[0].id32bit_cnt) { + calcandormask(pbxcan->filtermask.id32bitm,pbxcan->filtermask.id32bitshift[0], + pbxcan->filtermap[0].id32bit_cnt); + } + pbxcan->filtermask.id32bitshift[1] = pbxcan->filtermask.id32maskshift[1] + + pbxcan->filtermap[1].id32mask_cnt; + if(pbxcan->filtermap[1].id32bit_cnt) { + calcandormask(pbxcan->filtermask.id32bitm,pbxcan->filtermask.id32bitshift[1], + pbxcan->filtermap[1].id32bit_cnt); + } + pbxcan->filtermask.id16maskshift[0] = pbxcan->filtermask.id32bitshift[0] + + pbxcan->filtermap[0].id32bit_cnt; + if(pbxcan->filtermap[0].id16mask_cnt) { + calcandormask(pbxcan->filtermask.id16maskm,pbxcan->filtermask.id16maskshift[0], + pbxcan->filtermap[0].id16mask_cnt); + } + pbxcan->filtermask.id16maskshift[1] = pbxcan->filtermask.id32bitshift[1] + + pbxcan->filtermap[1].id32bit_cnt; + if(pbxcan->filtermap[1].id16mask_cnt) { + calcandormask(pbxcan->filtermask.id16maskm,pbxcan->filtermask.id16maskshift[1], + pbxcan->filtermap[1].id16mask_cnt); + } + pbxcan->filtermask.id16bitshift[0] = pbxcan->filtermask.id16maskshift[0] + + pbxcan->filtermap[0].id16mask_cnt; + if(pbxcan->filtermap[0].id16bit_cnt) { + calcandormask(pbxcan->filtermask.id16bitm,pbxcan->filtermask.id16bitshift[0], + pbxcan->filtermap[0].id16bit_cnt); + } + pbxcan->filtermask.id16bitshift[1] = pbxcan->filtermask.id16maskshift[1] + + pbxcan->filtermap[1].id16mask_cnt; + if(pbxcan->filtermap[1].id16bit_cnt) { + calcandormask(pbxcan->filtermask.id16bitm,pbxcan->filtermask.id16bitshift[1], + pbxcan->filtermap[1].id16bit_cnt); + } +} +static rt_int32_t bxcanfindfilter(struct stm_bxcan *pbxcan,struct rt_can_filter_item* pitem, + rt_int32_t type,rt_int32_t* base,rt_int32_t* off) +{ + rt_int32_t i; + rt_uint32_t bits,thisid,thismask,shift,found; + CAN_FilterRegister_TypeDef * pfilterreg; + found = 0; + switch(type) { + case 3: + shift = 3; + for(i = 0; i < BX_CAN_MAX_FILTERS; i++) { + bits = 0x01 << (i & 0x1F); + if(bits & (pbxcan->filtermask.id32maskm[i >> 5] & pbxcan->alocmask[i >> 5])) { + bxcancalcbaseoff(pbxcan,i,base,off); + pfilterreg = &((CAN_FilterRegister_TypeDef *)pbxcan->mfrbase)[*base]; + thisid = (rt_uint32_t)pitem->id<mask<ide) { + thisid |= CAN_ID_EXT; + thismask |= CAN_ID_EXT; + } + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE; + thismask |= CAN_RTR_REMOTE; + } + if(pfilterreg->FR1 == thisid && pfilterreg->FR2 == thismask) { + found = 1; + break; + } + } + } + break; + case 2: + shift = 3; + for(i = 0; i < BX_CAN_MAX_FILTERS; i++) { + bits = 0x01 << (i % 32); + if(bits & (pbxcan->filtermask.id32bitm[i >> 5] & pbxcan->alocmask[i >> 5])) { + bxcancalcbaseoff(pbxcan,i,base,off); + pfilterreg = &((CAN_FilterRegister_TypeDef *)pbxcan->mfrbase)[*base]; + thisid = (rt_uint32_t)pitem->id<ide) { + thisid |= CAN_ID_EXT; + } + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE; + } + if((off == 0 && pfilterreg->FR1 == thisid) || + (*off == 1 && pfilterreg->FR2 == thisid) + ) { + found = 1; + break; + } + } + } + break; + case 1: + shift = 5; + for(i = 0; i < BX_CAN_MAX_FILTERS; i++) { + bits = 0x01 << (i % 32); + if(bits & (pbxcan->filtermask.id16maskm[i >> 5] & pbxcan->alocmask[i >> 5])) { + bxcancalcbaseoff(pbxcan,i,base,off); + pfilterreg = &((CAN_FilterRegister_TypeDef *)pbxcan->mfrbase)[*base]; + thisid = pitem->id << shift; + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE << (shift - 2); + } + thismask = pitem->mask << shift; + if(pitem->rtr) { + thismask |= CAN_RTR_REMOTE << (shift - 2); + } + if(*off == 0 && pfilterreg->FR1 == ((thisid & 0x0000FFFF) | ((thismask & 0x0000FFFF) << 16)) || + *off == 1 && pfilterreg->FR2 == ((thisid & 0x0000FFFF) | ((thismask & 0x0000FFFF) << 16)) + ){ + found = 1; + break; + } + } + } + break; + case 0: + shift = 5; + for(i = 0; i < BX_CAN_MAX_FILTERS; i++) { + bits = 0x01 << (i % 32); + if(bits & (pbxcan->filtermask.id16bitm[i >> 5] & pbxcan->alocmask[i >> 5])) { + bxcancalcbaseoff(pbxcan,i,base,off); + pfilterreg = &((CAN_FilterRegister_TypeDef *)pbxcan->mfrbase)[*base]; + thisid = pitem->id << shift; + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE << (shift - 2); + } + if(*off < 2 && ((rt_uint16_t*)&pfilterreg->FR1)[*off & 0x01] == thisid || + *off >= 2 && ((rt_uint16_t*)&pfilterreg->FR2)[*off & 0x01] == thisid) { + found = 1; + break; + } + } + } + break; + } + if(found) { + return i; + } + return -1; +} +extern int __rt_ffs(int value); +static rt_err_t bxcanallocfilter(rt_uint32_t * pmask, rt_uint32_t * palocmask, + rt_uint32_t count, rt_int32_t* hdr) +{ + rt_int32_t i; + for(i = 0; i < count; i++) { + rt_enter_critical(); + if((pmask[i] & ~palocmask[i]) != 0) { + *hdr = __rt_ffs(pmask[i] & ~palocmask[i]) - 1 + i * 32; + palocmask[i] |= 0x01 <<(*hdr % 0x1F); + rt_exit_critical(); + return RT_EOK; + } + rt_exit_critical(); + } + if(i >= count) { + return RT_ENOMEM; + } + return RT_EOK; +} +static rt_err_t bxcanallocnewfilter(struct stm_bxcan *pbxcan, rt_int32_t actived, + rt_int32_t type, rt_int32_t* hdr, rt_int32_t* base, rt_int32_t* off) +{ + rt_err_t res; + *hdr = -1; + switch(type) { + case 0x03: + res = bxcanallocfilter(pbxcan->filtermask.id32maskm,pbxcan->alocmask, + BX_CAN_FILTER_MAX_ARRAY_SIZE,hdr); + break; + case 0x02: + res = bxcanallocfilter(pbxcan->filtermask.id32bitm,pbxcan->alocmask, + BX_CAN_FILTER_MAX_ARRAY_SIZE,hdr); + break; + case 0x01: + res = bxcanallocfilter(pbxcan->filtermask.id16maskm,pbxcan->alocmask, + BX_CAN_FILTER_MAX_ARRAY_SIZE,hdr); + break; + case 0x00: + res = bxcanallocfilter(pbxcan->filtermask.id16bitm,pbxcan->alocmask, + BX_CAN_FILTER_MAX_ARRAY_SIZE,hdr); + break; + } + if(res != RT_EOK || *hdr < 0) { + return RT_ENOMEM; + } + bxcancalcbaseoff(pbxcan,*hdr,base,off); + return RT_EOK; +} +static rt_err_t bxmodifyfilter(struct stm_bxcan *pbxcan, struct rt_can_filter_item* pitem, rt_uint32_t actived) +{ + rt_int32_t fcase; + rt_err_t res; + rt_int32_t hdr,fbase,foff; + + fcase = (pitem->mode | (pitem->ide << 1)); + hdr = bxcanfindfilter(pbxcan,pitem,fcase,&fbase,&foff); + if(hdr < 0) { + if(!actived) { + return RT_EOK; + } else if(pitem->hdr == -1) { + res = bxcanallocnewfilter(pbxcan,actived,fcase,&hdr,&fbase,&foff); + if(res != RT_EOK) { + return res; + } + } else if(pitem->hdr >= 0) { + rt_enter_critical(); + res = bxcancalcbaseoff(pbxcan,pitem->hdr,&fbase,&foff); + if(res != RT_EOK) { + return res; + } + hdr = pitem->hdr; + if(actived) { + pbxcan->alocmask[hdr >> 5] |= 0x01 <<(hdr % 0x1F); + } + rt_exit_critical(); + } + } else { + if(!actived) { + pitem->hdr = hdr; + } else if(hdr >= 0 && (pitem->hdr >= 0 || pitem->hdr == -1)) { + pitem->hdr = hdr; + return RT_EBUSY; + } + } + rt_uint32_t ID[2]; + rt_uint32_t shift; + rt_uint32_t thisid; + rt_uint32_t thismask; + CAN_FilterInitTypeDef CAN_FilterInitStructure; + + pitem->hdr = hdr; + CAN_FilterRegister_TypeDef * pfilterreg = &((CAN_FilterRegister_TypeDef *)pbxcan->mfrbase)[fbase]; + ID[0] = pfilterreg->FR1; + ID[1] = pfilterreg->FR2; + CAN_FilterInitStructure.CAN_FilterNumber = (pfilterreg - &CAN1->sFilterRegister[0]); + if(pitem->mode) { + CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdMask; + } else { + CAN_FilterInitStructure.CAN_FilterMode=CAN_FilterMode_IdList; + } + if(pitem->ide) { + CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_32bit; + } else { + CAN_FilterInitStructure.CAN_FilterScale=CAN_FilterScale_16bit; + } + switch(fcase) { + case 0x03: + if(actived) { + shift = 3; + thisid = (rt_uint32_t)pitem->id<mask<ide) { + thisid |= CAN_ID_EXT; + thismask |= CAN_ID_EXT; + } + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE; + thismask |= CAN_RTR_REMOTE; + } + ID[0] = thisid; + ID[1] = thismask; + } else { + ID[0] = 0xFFFFFFFF; + ID[1] = 0xFFFFFFFF; + } + break; + case 0x02: + if(actived) { + shift = 3; + thisid = (rt_uint32_t)pitem->id<ide) { + thisid |= CAN_ID_EXT; + } + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE; + } + ID[foff] = thisid; + } else { + ID[foff] = 0xFFFFFFFF; + } + break; + case 0x01: + if(actived) { + shift = 5; + thisid = pitem->id << shift; + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE << (shift - 2); + } + thismask = pitem->mask << shift; + if(pitem->rtr) { + thismask |= CAN_RTR_REMOTE << (shift - 2); + } + ID[foff] = (thisid & 0x0000FFFF) | ((thismask & 0x0000FFFF) << 16); + } else { + ID[foff] = 0xFFFFFFFF; + } + break; + case 0x00: + if(actived) { + shift = 5; + thisid = pitem->id << shift; + if(pitem->rtr) { + thisid |= CAN_RTR_REMOTE << (shift - 2); + } + ((rt_uint16_t*) ID)[foff] = thisid; + } else { + ((rt_uint16_t*) ID)[foff] = 0xFFFF; + } + break; + } + CAN_FilterInitStructure.CAN_FilterIdHigh = ((ID[1]) & 0x0000FFFF); + CAN_FilterInitStructure.CAN_FilterIdLow = ID[0] & 0x0000FFFF; + CAN_FilterInitStructure.CAN_FilterMaskIdHigh = (ID[1] & 0xFFFF0000) >> 16; + CAN_FilterInitStructure.CAN_FilterMaskIdLow = (ID[0] & 0xFFFF0000) >> 16; + if(fbase >= pbxcan->fifo1filteroff) { + CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 1; + } else { + CAN_FilterInitStructure.CAN_FilterFIFOAssignment = 0; + } + if(ID[0] != 0xFFFFFFFF || ID[1] != 0xFFFFFFFF) { + CAN_FilterInitStructure.CAN_FilterActivation=ENABLE; + } else { + CAN_FilterInitStructure.CAN_FilterActivation=DISABLE; + } + if(!actived) { + rt_enter_critical(); + pbxcan->alocmask[hdr >> 5] &= ~(0x01 <<(hdr % 0x1F)); + rt_exit_critical(); + } + CAN_FilterInit(&CAN_FilterInitStructure); + return RT_EOK; +} +static rt_err_t setfilter(struct stm_bxcan *pbxcan,struct rt_can_filter_config *pconfig) +{ + struct rt_can_filter_item* pitem = pconfig->items; + rt_uint32_t count = pconfig->count; + rt_err_t res; + while(count) { + res = bxmodifyfilter(pbxcan,pitem,pconfig->actived); + if(res != RT_EOK) { + return res; + } + pitem++; + count--; + } + return RT_EOK; +} +static rt_err_t configure(struct rt_can_device *can, struct can_configure *cfg) +{ + CAN_TypeDef* pbxcan; + + pbxcan = ((struct stm_bxcan *) can->parent.user_data)->reg; + assert_param(IS_CAN_ALL_PERIPH(pbxcan)); + if(pbxcan == CAN1) + { + bxcan1_hw_init(); + bxcan_init(pbxcan,cfg->baud_rate,can->config.mode); + bxcan1_filter_init(can); + } else { + bxcan2_hw_init(); + bxcan_init(pbxcan,cfg->baud_rate,can->config.mode); + bxcan2_filter_init(can); + } + return RT_EOK; +} +static rt_err_t control(struct rt_can_device *can, int cmd, void *arg) +{ + struct stm_bxcan* pbxcan; + rt_uint32_t argval; + NVIC_InitTypeDef NVIC_InitStructure; + + pbxcan= (struct stm_bxcan *) can->parent.user_data; + assert_param(pbxcan != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_CLR_INT: + argval = (rt_uint32_t) arg; + if(argval == RT_DEVICE_FLAG_INT_RX) + { + NVIC_DisableIRQ(pbxcan->rcvirq0); + NVIC_DisableIRQ(pbxcan->rcvirq1); + CAN_ITConfig(pbxcan->reg,CAN_IT_FMP0 ,DISABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FF0 ,DISABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FOV0 ,DISABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FMP1 ,DISABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FF1 ,DISABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FOV1 ,DISABLE); + } else if(argval == RT_DEVICE_FLAG_INT_TX) + { + NVIC_DisableIRQ(pbxcan->sndirq); + CAN_ITConfig(pbxcan->reg,CAN_IT_TME,DISABLE); + } else if(argval == RT_DEVICE_CAN_INT_ERR) { + CAN_ITConfig(pbxcan->reg,CAN_IT_BOF ,DISABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_LEC ,DISABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_ERR ,DISABLE); + NVIC_DisableIRQ(pbxcan->errirq); + } + break; + case RT_DEVICE_CTRL_SET_INT: + argval = (rt_uint32_t) arg; + if(argval == RT_DEVICE_FLAG_INT_RX) + { + CAN_ITConfig(pbxcan->reg,CAN_IT_FMP0 ,ENABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FF0 ,ENABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FOV0 ,ENABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FMP1 ,ENABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FF1 ,ENABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_FOV1 ,ENABLE); + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_InitStructure.NVIC_IRQChannel = pbxcan->rcvirq0; + NVIC_Init(&NVIC_InitStructure); + NVIC_InitStructure.NVIC_IRQChannel = pbxcan->rcvirq1; + NVIC_Init(&NVIC_InitStructure); + } else if(argval == RT_DEVICE_FLAG_INT_TX) + { + CAN_ITConfig(pbxcan->reg,CAN_IT_TME,ENABLE); + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_InitStructure.NVIC_IRQChannel = pbxcan->sndirq; + NVIC_Init(&NVIC_InitStructure); + } else if(argval == RT_DEVICE_CAN_INT_ERR) { + CAN_ITConfig(pbxcan->reg,CAN_IT_BOF ,ENABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_LEC ,ENABLE); + CAN_ITConfig(pbxcan->reg,CAN_IT_ERR ,ENABLE); + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0x1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0x0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_InitStructure.NVIC_IRQChannel = pbxcan->errirq; + NVIC_Init(&NVIC_InitStructure); + } + break; + case RT_CAN_CMD_SET_FILTER: + return setfilter(pbxcan, (struct rt_can_filter_config*) arg); + break; + case RT_CAN_CMD_SET_MODE: + argval = (rt_uint32_t) arg; + if(argval != RT_CAN_MODE_NORMAL || + argval != RT_CAN_MODE_LISEN || + argval != RT_CAN_MODE_LOOPBACK || + argval != RT_CAN_MODE_LOOPBACKANLISEN ) { + return RT_ERROR; + } + if(argval != can->config.mode) + { + can->config.mode = argval; + return bxcan_set_mode(pbxcan->reg, argval); + } + break; + case RT_CAN_CMD_SET_BAUD: + argval = (rt_uint32_t) arg; + if(argval != CAN1MBaud || + argval != CAN800kBaud || + argval != CAN500kBaud || + argval != CAN250kBaud || + argval != CAN125kBaud || + argval != CAN100kBaud || + argval != CAN50kBaud || + argval != CAN20kBaud || + argval != CAN10kBaud ) { + return RT_ERROR; + } + if(argval != can->config.baud_rate) + { + can->config.baud_rate = argval; + return bxcan_set_baud_rate(pbxcan->reg, argval); + } + break; + case RT_CAN_CMD_SET_PRIV: + argval = (rt_uint32_t) arg; + if(argval != RT_CAN_MODE_PRIV || + argval != RT_CAN_MODE_NOPRIV) { + return RT_ERROR; + } + if(argval != can->config.privmode) + { + can->config.privmode = argval; + return bxcan_set_privmode(pbxcan->reg, argval); + } + break; + case RT_CAN_CMD_GET_STATUS: + { + rt_uint32_t errtype; + errtype = pbxcan->reg->ESR; + can->status.rcverrcnt = errtype >> 24; + can->status.snderrcnt = (errtype >> 16 & 0xFF); + can->status.errcode = errtype & 0x07; + if(arg != &can->status) { + rt_memcpy(arg,&can->status,sizeof(can->status)); + } + } + break; + } + + return RT_EOK; +} +static int sendmsg(struct rt_can_device *can, const void* buf, rt_uint32_t boxno) +{ + CAN_TypeDef* pbxcan; + struct rt_can_msg* pmsg = (struct rt_can_msg*) buf; + + pbxcan= ((struct stm_bxcan *) can->parent.user_data)->reg; + assert_param(IS_CAN_ALL_PERIPH(pbxcan)); + + pbxcan->sTxMailBox[boxno].TIR &= TMIDxR_TXRQ; + if (pmsg->ide == RT_CAN_STDID) + { + assert_param(IS_CAN_STDID(pmsg->id)); + pbxcan->sTxMailBox[boxno].TIR |= ((pmsg->id << 21) | \ + pmsg->rtr); + } + else + { + assert_param(IS_CAN_EXTID(pmsg->id)); + pbxcan->sTxMailBox[boxno].TIR |= ((pmsg->id << 3) | \ + pmsg->ide <<2 | \ + pmsg->rtr); + } + + pmsg->len &= (uint8_t)0x0000000F; + pbxcan->sTxMailBox[boxno].TDTR &= (uint32_t)0xFFFFFFF0; + pbxcan->sTxMailBox[boxno].TDTR |= pmsg->len; + + pbxcan->sTxMailBox[boxno].TDLR = (((uint32_t)pmsg->data[3] << 24) | + ((uint32_t)pmsg->data[2] << 16) | + ((uint32_t)pmsg->data[1] << 8) | + ((uint32_t)pmsg->data[0])); + if(pmsg->len > 4) { + pbxcan->sTxMailBox[boxno].TDHR = (((uint32_t)pmsg->data[7] << 24) | + ((uint32_t)pmsg->data[6] << 16) | + ((uint32_t)pmsg->data[5] << 8) | + ((uint32_t)pmsg->data[4])); + } + pbxcan->sTxMailBox[boxno].TIR |= TMIDxR_TXRQ; + + return RT_EOK; +} +static int recvmsg(struct rt_can_device *can, void* buf, rt_uint32_t boxno) +{ + CAN_TypeDef* pbxcan; + struct rt_can_msg* pmsg = (struct rt_can_msg*) buf; + + pbxcan= ((struct stm_bxcan *) can->parent.user_data)->reg; + assert_param(IS_CAN_ALL_PERIPH(pbxcan)); + assert_param(IS_CAN_FIFO(boxno)); + pmsg->ide = ((uint8_t)0x04 & pbxcan->sFIFOMailBox[boxno].RIR)>>2; + if (pmsg->ide == CAN_Id_Standard) + { + pmsg->id = (uint32_t)0x000007FF & (pbxcan->sFIFOMailBox[boxno].RIR >> 21); + } + else + { + pmsg->id = (uint32_t)0x1FFFFFFF & (pbxcan->sFIFOMailBox[boxno].RIR >> 3); + } + + pmsg->rtr = (uint8_t)0x02 & pbxcan->sFIFOMailBox[boxno].RIR; + pmsg->len = (uint8_t)0x0F & pbxcan->sFIFOMailBox[boxno].RDTR; + pmsg->data[0] = (uint8_t)0xFF & pbxcan->sFIFOMailBox[boxno].RDLR; + pmsg->data[1] = (uint8_t)0xFF & (pbxcan->sFIFOMailBox[boxno].RDLR >> 8); + pmsg->data[2] = (uint8_t)0xFF & (pbxcan->sFIFOMailBox[boxno].RDLR >> 16); + pmsg->data[3] = (uint8_t)0xFF & (pbxcan->sFIFOMailBox[boxno].RDLR >> 24); + if(pmsg->len > 4) { + pmsg->data[4] = (uint8_t)0xFF & pbxcan->sFIFOMailBox[boxno].RDHR; + pmsg->data[5] = (uint8_t)0xFF & (pbxcan->sFIFOMailBox[boxno].RDHR >> 8); + pmsg->data[6] = (uint8_t)0xFF & (pbxcan->sFIFOMailBox[boxno].RDHR >> 16); + pmsg->data[7] = (uint8_t)0xFF & (pbxcan->sFIFOMailBox[boxno].RDHR >> 24); + } + pmsg->hdr = (uint8_t)0xFF & (pbxcan->sFIFOMailBox[boxno].RDTR >> 8); + if(boxno) pmsg->hdr += ((struct stm_bxcan *) can->parent.user_data)->fifo1filteroff * 4; + return RT_EOK; +} + +static const struct rt_can_ops canops = +{ + configure, + control, + sendmsg, + recvmsg, +}; +#ifdef USING_BXCAN1 +#ifdef RT_CAN_USING_LED +static struct rt_can_led can1rcvled = +{ + CANRT1,PIN_MODE_OUTPUT_OD,1, +}; +static struct rt_can_led can1errled = +{ + CANERR1,PIN_MODE_OUTPUT_OD,1, +}; +#endif +static struct stm_bxcan bxcan1data = +{ + .reg = CAN1, + .mfrbase = (void*)&CAN1->sFilterRegister[0], + .sndirq = CAN1_TX_IRQn, + .rcvirq0 = CAN1_RX0_IRQn, + .rcvirq1 = CAN1_RX1_IRQn, + .errirq = CAN1_SCE_IRQn, + .alocmask = {0,0}, + .filtercnt = BX_CAN2_FMRSTART, + .fifo1filteroff = 7, + .filtermap = { + [0] = { + .id32mask_cnt = 0, + .id32bit_cnt = 0, + .id16mask_cnt = 2, + .id16bit_cnt =24, + }, + [1] = { + .id32mask_cnt = 0, + .id32bit_cnt = 0, + .id16mask_cnt = 2, + .id16bit_cnt =24, + }, + }, +}; +struct rt_can_device bxcan1; +void CAN1_RX0_IRQHandler(void) +{ + while(CAN1->RF0R & 0x11) + { + if ((CAN1->RF0R & CAN_RF0R_FOVR0) != 0) + { + CAN1->RF0R = CAN_RF0R_FOVR0; + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_RXOF_IND | 0<<8); + } else { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_RX_IND | 0<<8); + } + CAN1->RF0R |= CAN_RF0R_RFOM0; + } +} +void CAN1_RX1_IRQHandler(void) +{ + while(CAN1->RF1R & 0x11) + { + if ((CAN1->RF1R & CAN_RF1R_FOVR1) != 0) + { + CAN1->RF1R = CAN_RF1R_FOVR1; + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_RXOF_IND | 1<<8); + } else { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_RX_IND | 1<<8); + } + CAN1->RF1R |= CAN_RF1R_RFOM1; + } +} +void CAN1_TX_IRQHandler(void) +{ + rt_uint32_t state; + if(CAN1->TSR & (CAN_TSR_RQCP0)) + { + state = CAN1->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + CAN1->TSR |= CAN_TSR_RQCP0; + if(state == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) + { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_TX_DONE | 0<<8); + } else { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_TX_FAIL | 0<<8); + } + } + if(CAN1->TSR & (CAN_TSR_RQCP1)) { + state = CAN1->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + CAN1->TSR |= CAN_TSR_RQCP1; + if(state == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) + { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_TX_DONE | 1<<8); + } else { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_TX_FAIL | 1<<8); + } + } + if(CAN1->TSR & (CAN_TSR_RQCP2)) { + state = CAN1->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + CAN1->TSR |= CAN_TSR_RQCP2; + if(state == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) + { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_TX_DONE | 2<<8); + } else { + rt_hw_can_isr(&bxcan1,RT_CAN_EVENT_TX_FAIL | 2<<8); + } + } +} +void CAN1_SCE_IRQHandler(void) +{ + rt_uint32_t errtype; + errtype = CAN1->ESR; + if(errtype & 0x70 && bxcan1.status.lasterrtype == (errtype & 0x70)) { + switch((errtype & 0x70)>>4) { + case RT_CAN_BUS_BIT_PAD_ERR: + bxcan1.status.bitpaderrcnt++; + break; + case RT_CAN_BUS_FORMAT_ERR: + bxcan1.status.formaterrcnt++; + break; + case RT_CAN_BUS_ACK_ERR: + bxcan1.status.ackerrcnt++; + break; + case RT_CAN_BUS_IMPLICIT_BIT_ERR: + case RT_CAN_BUS_EXPLICIT_BIT_ERR: + bxcan1.status.biterrcnt++; + break; + case RT_CAN_BUS_CRC_ERR: + bxcan1.status.crcerrcnt++; + break; + } + bxcan1.status.lasterrtype = errtype & 0x70; + CAN1->ESR &= ~0x70; + } + bxcan1.status.rcverrcnt = errtype >> 24; + bxcan1.status.snderrcnt = (errtype >> 16 & 0xFF); + bxcan1.status.errcode = errtype & 0x07; + CAN1->MSR |= CAN_MSR_ERRI; +} +#endif /*USING_BXCAN1*/ + +#ifdef USING_BXCAN2 +#ifdef RT_CAN_USING_LED +static struct rt_can_led can2rcvled = +{ + CANRT2,PIN_MODE_OUTPUT_OD,1, +}; +static struct rt_can_led can2errled = +{ + CANERR2,PIN_MODE_OUTPUT_OD,1, +}; +#endif +static struct stm_bxcan bxcan2data = +{ + .reg = CAN2, + .mfrbase = (void*)&CAN1->sFilterRegister[BX_CAN2_FMRSTART], + .sndirq = CAN2_TX_IRQn, + .rcvirq0 = CAN2_RX0_IRQn, + .rcvirq1 = CAN2_RX1_IRQn, + .errirq = CAN2_SCE_IRQn, + .alocmask = {0,0}, + .filtercnt = BX_CAN_FMRNUMBER - BX_CAN2_FMRSTART, + .fifo1filteroff = 7, + .filtermap = { + [0] = { + .id32mask_cnt = 0, + .id32bit_cnt = 0, + .id16mask_cnt = 2, + .id16bit_cnt =24, + }, + [1] = { + .id32mask_cnt = 0, + .id32bit_cnt = 0, + .id16mask_cnt = 2, + .id16bit_cnt =24, + }, + }, +}; + +struct rt_can_device bxcan2; +void CAN2_RX0_IRQHandler(void) +{ + while(CAN2->RF0R & 0x11) + { + if ((CAN2->RF0R & CAN_RF0R_FOVR0) != 0) + { + CAN2->RF0R = CAN_RF0R_FOVR0; + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_RXOF_IND | 0<<8); + } else { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_RX_IND | 0<<8); + } + CAN2->RF0R |= CAN_RF0R_RFOM0; + } +} +void CAN2_RX1_IRQHandler(void) +{ + while(CAN2->RF1R & 0x11) + { + if ((CAN2->RF1R & CAN_RF1R_FOVR1) != 0) + { + CAN2->RF1R = CAN_RF1R_FOVR1; + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_RXOF_IND | 1<<8); + } else { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_RX_IND | 1<<8); + } + CAN2->RF1R |= CAN_RF1R_RFOM1; + } +} +void CAN2_TX_IRQHandler(void) +{ + rt_uint32_t state; + if(CAN2->TSR & (CAN_TSR_RQCP0)) + { + state = CAN2->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); + CAN2->TSR |= CAN_TSR_RQCP0; + if(state == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) + { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_TX_DONE | 0<<8); + } else { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_TX_FAIL | 0<<8); + } + } + if(CAN2->TSR & (CAN_TSR_RQCP1)) { + state = CAN2->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); + CAN2->TSR |= CAN_TSR_RQCP1; + if(state == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) + { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_TX_DONE | 1<<8); + } else { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_TX_FAIL | 1<<8); + } + } + if(CAN2->TSR & (CAN_TSR_RQCP2)) { + state = CAN2->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); + CAN2->TSR |= CAN_TSR_RQCP2; + if(state == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) + { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_TX_DONE | 2<<8); + } else { + rt_hw_can_isr(&bxcan2,RT_CAN_EVENT_TX_FAIL | 2<<8); + } + } +} +void CAN2_SCE_IRQHandler(void) +{ + rt_uint32_t errtype; + errtype = CAN2->ESR; + if(errtype & 0x70 && bxcan2.status.lasterrtype == (errtype & 0x70)) { + switch((errtype & 0x70)>>4) { + case RT_CAN_BUS_BIT_PAD_ERR: + bxcan2.status.bitpaderrcnt++; + break; + case RT_CAN_BUS_FORMAT_ERR: + bxcan2.status.formaterrcnt++; + break; + case RT_CAN_BUS_ACK_ERR: + bxcan2.status.ackerrcnt++; + break; + case RT_CAN_BUS_IMPLICIT_BIT_ERR: + case RT_CAN_BUS_EXPLICIT_BIT_ERR: + bxcan2.status.biterrcnt++; + break; + case RT_CAN_BUS_CRC_ERR: + bxcan2.status.crcerrcnt++; + break; + } + bxcan2.status.lasterrtype = errtype & 0x70; + CAN2->ESR &= ~0x70; + } + bxcan2.status.rcverrcnt = errtype >> 24; + bxcan2.status.snderrcnt = (errtype >> 16 & 0xFF); + bxcan2.status.errcode = errtype & 0x07; + CAN2->MSR |= CAN_MSR_ERRI; +} +#endif /*USING_BXCAN2*/ + +int stm32_bxcan_init(void) +{ + +#ifdef USING_BXCAN1 + bxcan1.config.baud_rate=CAN1MBaud; + bxcan1.config.msgboxsz=16; + bxcan1.config.sndboxnumber=3; + bxcan1.config.mode=RT_CAN_MODE_NORMAL; + bxcan1.config.privmode=0; + #ifdef RT_CAN_USING_LED + bxcan1.config.rcvled = &can1rcvled; + bxcan1.config.sndled = RT_NULL; + bxcan1.config.errled = &can1errled; + #endif + bxcan1.config.ticks = 50; +#ifdef RT_CAN_USING_HDR + bxcan1.config.maxhdr = BX_CAN2_FMRSTART * 4; +#endif + rt_hw_can_register(&bxcan1, "bxcan1", &canops, &bxcan1data); +#endif + +#ifdef USING_BXCAN2 + bxcan2.config.baud_rate=CAN1MBaud; + bxcan2.config.msgboxsz=16; + bxcan2.config.sndboxnumber=3; + bxcan2.config.mode=RT_CAN_MODE_NORMAL; + bxcan2.config.privmode=0; + #ifdef RT_CAN_USING_LED + bxcan2.config.rcvled = &can2rcvled; + bxcan2.config.sndled = RT_NULL; + bxcan2.config.errled = &can2errled; + #endif + bxcan2.config.ticks = 50; +#ifdef RT_CAN_USING_HDR + bxcan2.config.maxhdr = (BX_CAN_FMRNUMBER - BX_CAN2_FMRSTART) * 4; +#endif + rt_hw_can_register(&bxcan2, "bxcan2", &canops, &bxcan2data); +#endif + return RT_EOK; +} +INIT_BOARD_EXPORT(stm32_bxcan_init); + +#endif /*RT_USING_CAN2*/ diff --git a/bsp/stm32f10x/drivers/bxcan.h b/bsp/stm32f10x/drivers/bxcan.h new file mode 100644 index 0000000000..60ee996a3c --- /dev/null +++ b/bsp/stm32f10x/drivers/bxcan.h @@ -0,0 +1,16 @@ +/* + * File : bxcan.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ + +#ifndef BXCAN_H_ +#define BXCAN_H_ +#endif /*BXCAN_H_*/ diff --git a/components/drivers/can/can.c b/components/drivers/can/can.c new file mode 100644 index 0000000000..3d31409756 --- /dev/null +++ b/components/drivers/can/can.c @@ -0,0 +1,906 @@ +/* + * File : can.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ +#include +#include +#include + +static rt_err_t rt_can_init(struct rt_device *dev) +{ + rt_err_t result = RT_EOK; + struct rt_can_device *can; + + RT_ASSERT(dev != RT_NULL); + can = (struct rt_can_device *)dev; + + /* initialize rx/tx */ + can->can_rx = RT_NULL; + can->can_tx = RT_NULL; + + /* apply configuration */ + if (can->ops->configure) + result = can->ops->configure(can, &can->config); + + return result; +} +/* + * can interrupt routines + */ +rt_inline int _can_int_rx(struct rt_can_device *can, struct rt_can_msg *data, int msgs) +{ + int size; + struct rt_can_rx_fifo* rx_fifo; + + RT_ASSERT(can != RT_NULL); + size = msgs; + + rx_fifo = (struct rt_can_rx_fifo*) can->can_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + /* read from software FIFO */ + while (msgs) + { + rt_base_t level; + struct rt_can_msg_list *listmsg=RT_NULL; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); +#ifdef RT_CAN_USING_HDR + rt_int32_t hdr = data->hdr; + if (hdr >=0 && can->hdr && hdr < can->config.maxhdr && !rt_list_isempty(&can->hdr[hdr].list)) + { + listmsg=rt_list_entry(can->hdr[hdr].list.next, struct rt_can_msg_list, hdrlist); + rt_list_remove(&listmsg->list); + rt_list_remove(&listmsg->hdrlist); + if(can->hdr[hdr].msgs) { + can->hdr[hdr].msgs--; + } + listmsg->owner = RT_NULL; + } else +#endif /*RT_CAN_USING_HDR*/ + if (!rt_list_isempty(&rx_fifo->uselist)) + { + listmsg=rt_list_entry(rx_fifo->uselist.next, struct rt_can_msg_list, list); + rt_list_remove(&listmsg->list); +#ifdef RT_CAN_USING_HDR + rt_list_remove(&listmsg->hdrlist); + if(listmsg->owner != RT_NULL && listmsg->owner->msgs) { + listmsg->owner->msgs--; + } + listmsg->owner = RT_NULL; +#endif + } + else + { + /* no data, enable interrupt and break out */ + rt_hw_interrupt_enable(level); + break; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + if(listmsg!=RT_NULL) + { + rt_memcpy(data,&listmsg->data,sizeof(struct rt_can_msg)); + level = rt_hw_interrupt_disable(); + rt_list_insert_before(&rx_fifo->freelist,&listmsg->list); + rx_fifo->freenumbers++; + RT_ASSERT(rx_fifo->freenumbers <= can->config.msgboxsz); + rt_hw_interrupt_enable(level); + listmsg = RT_NULL; + } + data ++; msgs -= sizeof(struct rt_can_msg); + } + + return (size - msgs); +} + +rt_inline int _can_int_tx(struct rt_can_device *can, const struct rt_can_msg *data, int msgs) +{ + int size; + struct rt_can_tx_fifo *tx_fifo; + + RT_ASSERT(can != RT_NULL); + + size = msgs; + tx_fifo = (struct rt_can_tx_fifo*) can->can_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + while (msgs) + { + rt_base_t level; + rt_uint32_t no; + struct rt_can_sndbxinx_list* tx_tosnd = RT_NULL; + level = rt_hw_interrupt_disable(); + if(!rt_list_isempty(&tx_fifo->freelist)) + { + tx_tosnd = rt_list_entry(tx_fifo->freelist.next, struct rt_can_sndbxinx_list, list); + RT_ASSERT(tx_tosnd != RT_NULL); + rt_list_remove(&tx_tosnd->list); + } else { + rt_hw_interrupt_enable(level); + rt_completion_wait(&(tx_fifo->completion), RT_WAITING_FOREVER); + continue; + } + rt_hw_interrupt_enable(level); + no=((rt_uint32_t)tx_tosnd-(rt_uint32_t)tx_fifo->buffer)/sizeof(struct rt_can_sndbxinx_list); + tx_tosnd->result = RT_CAN__SND_RESUTL_WAIT; + if (can->ops->sendmsg(can, data ,no)) + { + level = rt_hw_interrupt_disable(); + rt_list_insert_after(&tx_fifo->freelist,&tx_tosnd->list); + rt_hw_interrupt_enable(level); + continue; + } + can->status.sndchange = 1; + rt_completion_wait(&(tx_tosnd->completion), RT_WAITING_FOREVER); + level = rt_hw_interrupt_disable(); + rt_uint32_t result = tx_tosnd->result; + if(!rt_list_isempty(&tx_tosnd->list)) { + rt_list_remove(&tx_tosnd->list); + } + rt_list_insert_before(&tx_fifo->freelist,&tx_tosnd->list); + rt_hw_interrupt_enable(level); + + if(result == RT_CAN__SND_RESUTL_OK) + { + level = rt_hw_interrupt_disable(); + can->status.sndpkg++; + rt_hw_interrupt_enable(level); + data ++; msgs -= sizeof(struct rt_can_msg); + if(!msgs) break; + } + else + { + level = rt_hw_interrupt_disable(); + can->status.dropedsndpkg++; + rt_hw_interrupt_enable(level); + break; + } + + level = rt_hw_interrupt_disable(); + if(rt_list_isempty(&tx_fifo->freelist)) + { + rt_hw_interrupt_enable(level); + rt_completion_done(&(tx_fifo->completion)); + } + else + { + rt_hw_interrupt_enable(level); + } + } + + return (size - msgs); +} +rt_inline int _can_int_tx_priv(struct rt_can_device *can, const struct rt_can_msg *data, int msgs) +{ + int size; + struct rt_can_tx_fifo *tx_fifo; + + RT_ASSERT(can != RT_NULL); + + size = msgs; + tx_fifo = (struct rt_can_tx_fifo*) can->can_tx; + RT_ASSERT(tx_fifo != RT_NULL); + + rt_base_t level; + rt_uint32_t no; + rt_uint32_t result; + while (msgs) + { + no = data->priv; + if(no >= can->config.sndboxnumber) { + break; + } + level = rt_hw_interrupt_disable(); + if((tx_fifo->buffer[no].result != RT_CAN__SND_RESUTL_OK)) { + rt_hw_interrupt_enable(level); + rt_completion_wait(&(tx_fifo->buffer[no].completion), RT_WAITING_FOREVER); + continue; + } + tx_fifo->buffer[no].result = RT_CAN__SND_RESUTL_WAIT; + rt_hw_interrupt_enable(level); + if (can->ops->sendmsg(can, data ,no) != RT_EOK) + { + continue; + } + can->status.sndchange = 1; + rt_completion_wait(&(tx_fifo->buffer[no].completion), RT_WAITING_FOREVER); + result = tx_fifo->buffer[no].result; + if(result == RT_CAN__SND_RESUTL_OK) + { + level = rt_hw_interrupt_disable(); + can->status.sndpkg++; + rt_hw_interrupt_enable(level); + data ++; msgs -= sizeof(struct rt_can_msg); + if(!msgs) break; + } + else + { + level = rt_hw_interrupt_disable(); + can->status.dropedsndpkg++; + rt_hw_interrupt_enable(level); + break; + } + } + + return (size - msgs); +} +static rt_err_t rt_can_open(struct rt_device *dev, rt_uint16_t oflag) +{ + struct rt_can_device *can; + + RT_ASSERT(dev != RT_NULL); + can = (struct rt_can_device *)dev; + + /* get open flags */ + dev->open_flag = oflag & 0xff; + rt_enter_critical(); + if (can->can_rx == RT_NULL) + { + if (oflag & RT_DEVICE_FLAG_INT_RX) + { + struct rt_can_rx_fifo* rx_fifo; + + rx_fifo = (struct rt_can_rx_fifo*) rt_malloc (sizeof(struct rt_can_rx_fifo) + + can->config.msgboxsz * sizeof(struct rt_can_msg_list)); + RT_ASSERT(rx_fifo != RT_NULL); + rx_fifo->buffer = (struct rt_can_msg_list*) (rx_fifo + 1); + rt_memset(rx_fifo->buffer, 0, can->config.msgboxsz * sizeof(struct rt_can_msg_list)); + rt_list_init(&rx_fifo->freelist); + rt_list_init(&rx_fifo->uselist); + rx_fifo->freenumbers=can->config.msgboxsz; + int i = 0; + for(i = 0; i< can->config.msgboxsz; i++) + { + rt_list_insert_before(&rx_fifo->freelist,&rx_fifo->buffer[i].list); +#ifdef RT_CAN_USING_HDR + rt_list_init(&rx_fifo->buffer[i].hdrlist); + rx_fifo->buffer[i].owner = RT_NULL; +#endif + } + can->can_rx = rx_fifo; + rt_exit_critical(); + dev->open_flag |= RT_DEVICE_FLAG_INT_RX; + /* configure low level device */ + can->ops->control(can, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX); + } + else + { + can->can_rx = RT_NULL; + rt_exit_critical(); + } + } else { + rt_exit_critical(); + } + rt_enter_critical(); + if (can->can_tx == RT_NULL) + { + if (oflag & RT_DEVICE_FLAG_INT_TX) + { + struct rt_can_tx_fifo *tx_fifo; + + tx_fifo = (struct rt_can_tx_fifo*) rt_malloc(sizeof(struct rt_can_tx_fifo)+ + can->config.sndboxnumber*sizeof(struct rt_can_sndbxinx_list)); + RT_ASSERT(tx_fifo != RT_NULL); + tx_fifo->buffer = (struct rt_can_sndbxinx_list *) (tx_fifo + 1); + rt_memset(tx_fifo->buffer, 0, + can->config.sndboxnumber*sizeof(struct rt_can_sndbxinx_list)); + rt_list_init(&tx_fifo->freelist); + int i = 0; + for(i = 0; i< can->config.sndboxnumber; i++) + { + rt_list_insert_before(&tx_fifo->freelist,&tx_fifo->buffer[i].list); + rt_completion_init(&(tx_fifo->buffer[i].completion)); + tx_fifo->buffer[i].result = RT_CAN__SND_RESUTL_OK; + } + rt_completion_init(&(tx_fifo->completion)); + can->can_tx = tx_fifo; + rt_exit_critical(); + dev->open_flag |= RT_DEVICE_FLAG_INT_TX; + /* configure low level device */ + can->ops->control(can, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_TX); + } + else + { + can->can_tx = RT_NULL; + rt_exit_critical(); + } + } else { + rt_exit_critical(); + } + can->ops->control(can, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_CAN_INT_ERR); +#ifdef RT_CAN_USING_HDR + rt_enter_critical(); + if(can->hdr == RT_NULL) { + struct rt_can_hdr * phdr; + phdr = (struct rt_can_hdr *) rt_malloc(can->config.maxhdr*sizeof(struct rt_can_hdr)); + RT_ASSERT(phdr != RT_NULL); + rt_memset(phdr, 0,can->config.maxhdr*sizeof(struct rt_can_hdr)); + int i = 0; + for(i = 0; i< can->config.maxhdr; i++) + { + rt_list_init(&phdr[i].list); + } + can->hdr = phdr; + rt_exit_critical(); + } else { + rt_exit_critical(); + } +#endif + rt_enter_critical(); + if(!can->timerinitflag) { + can->timerinitflag = 1; + rt_exit_critical(); + #ifdef RT_CAN_USING_LED + if(can->config.rcvled != RT_NULL) { + rt_pin_mode(can->config.rcvled->pin,can->config.rcvled->mode); + rt_pin_write(can->config.rcvled->pin,can->config.rcvled->init); + } + if(can->config.sndled != RT_NULL) { + rt_pin_mode(can->config.sndled->pin,can->config.sndled->mode); + rt_pin_write(can->config.sndled->pin,can->config.sndled->init); + } + if(can->config.errled != RT_NULL) { + rt_pin_mode(can->config.errled->pin,can->config.errled->mode); + rt_pin_write(can->config.errled->pin,can->config.errled->init); + } + #endif + rt_timer_start(&can->timer); + } else { + rt_exit_critical(); + } + return RT_EOK; +} + +static rt_err_t rt_can_close(struct rt_device *dev) +{ + struct rt_can_device *can; + + RT_ASSERT(dev != RT_NULL); + can = (struct rt_can_device *)dev; + + /* this device has more reference count */ + if (dev->ref_count > 1) return RT_EOK; + rt_enter_critical(); + if(can->timerinitflag) { + can->timerinitflag = 0; + rt_exit_critical(); + rt_timer_stop(&can->timer); + #ifdef RT_CAN_USING_LED + rt_pin_write(can->config.rcvled->pin,can->config.rcvled->init); + rt_pin_write(can->config.rcvled->pin,can->config.sndled->init); + rt_pin_write(can->config.rcvled->pin,can->config.errled->init); + #endif + } else { + rt_exit_critical(); + } + rt_enter_critical(); + can->status_indicate.ind = RT_NULL; + can->status_indicate.args = RT_NULL; + rt_exit_critical(); +#ifdef RT_CAN_USING_HDR + rt_enter_critical(); + if(can->hdr != RT_NULL) { + rt_free(can->hdr); + can->hdr = RT_NULL; + rt_exit_critical(); + } else { + rt_exit_critical(); + } +#endif + if (dev->open_flag & RT_DEVICE_FLAG_INT_RX) + { + struct rt_can_rx_fifo* rx_fifo; + + rx_fifo = (struct rt_can_rx_fifo*)can->can_rx; + RT_ASSERT(rx_fifo != RT_NULL); + + rt_free(rx_fifo); + dev->open_flag &= ~RT_DEVICE_FLAG_INT_RX; + /* configure low level device */ + can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void*)RT_DEVICE_FLAG_INT_TX); + } + if (dev->open_flag & RT_DEVICE_FLAG_INT_TX) + { + struct rt_can_tx_fifo* tx_fifo; + + tx_fifo = (struct rt_can_tx_fifo*)can->can_rx; + RT_ASSERT(tx_fifo != RT_NULL); + + rt_free(tx_fifo); + dev->open_flag &= ~RT_DEVICE_FLAG_INT_TX; + /* configure low level device */ + can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void*)RT_DEVICE_FLAG_INT_TX); + } + can->ops->control(can, RT_DEVICE_CTRL_CLR_INT, (void *)RT_DEVICE_CAN_INT_ERR); + return RT_EOK; +} + +static rt_size_t rt_can_read(struct rt_device *dev, + rt_off_t pos, + void *buffer, + rt_size_t size) +{ + struct rt_can_device *can; + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + can = (struct rt_can_device *)dev; + + if (dev->open_flag & RT_DEVICE_FLAG_INT_RX) + { + return _can_int_rx(can, buffer, size); + } + return 0; +} + +static rt_size_t rt_can_write(struct rt_device *dev, + rt_off_t pos, + const void *buffer, + rt_size_t size) +{ + struct rt_can_device *can; + + RT_ASSERT(dev != RT_NULL); + if (size == 0) return 0; + + can = (struct rt_can_device *)dev; + + if (dev->open_flag & RT_DEVICE_FLAG_INT_TX) + { + if(can->config.privmode) { + return _can_int_tx_priv(can, buffer, size); + } else { + return _can_int_tx(can, buffer, size); + } + } + return 0; +} + +static rt_err_t rt_can_control(struct rt_device *dev, + rt_uint8_t cmd, + void *args) +{ + struct rt_can_device *can; + rt_err_t res; + + RT_ASSERT(dev != RT_NULL); + can = (struct rt_can_device *)dev; + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_CONFIG: + /* configure device */ + can->ops->configure(can, (struct can_configure *)args); + break; + case RT_CAN_CMD_SET_PRIV: + /* configure device */ + if((rt_uint32_t)args != can->config.privmode) { + if(res = can->ops->control(can, cmd, args) != RT_EOK) { + return res; + } + struct rt_can_tx_fifo* tx_fifo; + tx_fifo = (struct rt_can_tx_fifo*) can->can_tx; + int i; + rt_base_t level; + if(can->config.privmode) { + rt_completion_done(&(tx_fifo->completion)); + level = rt_hw_interrupt_disable(); + for(i = 0; i< can->config.sndboxnumber; i++) + { + rt_list_remove(&tx_fifo->buffer[i].list); + } + rt_hw_interrupt_enable(level); + } else { + for(i = 0; i< can->config.sndboxnumber; i++) + { + rt_base_t level; + level = rt_hw_interrupt_disable(); + if(tx_fifo->buffer[i].result == RT_CAN__SND_RESUTL_OK) { + rt_list_insert_before(&tx_fifo->freelist,&tx_fifo->buffer[i].list); + } + rt_hw_interrupt_enable(level); + } + } + return RT_EOK; + } + break; + case RT_CAN_CMD_SET_STATUS_IND: + can->status_indicate.ind = ((rt_can_status_ind_type_t)args)->ind; + can->status_indicate.args = ((rt_can_status_ind_type_t)args)->args; + break; +#ifdef RT_CAN_USING_HDR + case RT_CAN_CMD_SET_FILTER: + res = can->ops->control(can, cmd, args); + if(res != RT_EOK || can->hdr == RT_NULL) { + return res; + } + { + struct rt_can_filter_config* pfilter; + struct rt_can_filter_item* pitem; + rt_uint32_t count; + rt_base_t level; + pfilter = (struct rt_can_filter_config*)args; + count = pfilter->count; + pitem = pfilter->items; + if(pfilter->actived) { + while(count) { + if(pitem->hdr >= can->config.maxhdr || pitem->hdr < 0) { + count--; + pitem++; + continue; + } + level = rt_hw_interrupt_disable(); + if(!can->hdr[pitem->hdr].connected) { + rt_memcpy(&can->hdr[pitem->hdr].filter,pitem, + sizeof(struct rt_can_filter_item)); + can->hdr[pitem->hdr].connected = 1; + can->hdr[pitem->hdr].msgs = 0; + rt_list_init(&can->hdr[pitem->hdr].list); + } + rt_hw_interrupt_enable(level); + count--; + pitem++; + } + } else { + while(count) { + if(pitem->hdr >= can->config.maxhdr || pitem->hdr < 0) { + count--; + pitem++; + continue; + } + level = rt_hw_interrupt_disable(); + if(can->hdr[pitem->hdr].connected) { + rt_memset(&can->hdr[pitem->hdr].filter,0, + sizeof(struct rt_can_filter_item)); + can->hdr[pitem->hdr].connected = 0; + can->hdr[pitem->hdr].msgs = 0; + if(!rt_list_isempty(&can->hdr[pitem->hdr].list)) + { + rt_list_remove(can->hdr[pitem->hdr].list.next); + } + } + rt_hw_interrupt_enable(level); + count--; + pitem++; + } + } + } + break; +#endif /*RT_CAN_USING_HDR*/ + default : + /* control device */ + if(can->ops->control != RT_NULL) + { + can->ops->control(can, cmd, args); + } + break; + } + + return RT_EOK; +} +/* + * can timer + */ +static void cantimeout(void* arg) +{ + rt_uint32_t ledonflag = 0; + rt_can_t can = (rt_can_t)arg; + rt_device_control((rt_device_t)can,RT_CAN_CMD_GET_STATUS,(void* )&can->status); + if(can->timerinitflag == 1) { + ledonflag = 1; + can->timerinitflag = 0xFF; + } + #ifdef RT_CAN_USING_LED + if(can->config.rcvled != RT_NULL && can->config.sndled == RT_NULL) { + if(ledonflag == 1) { + rt_pin_write(can->config.rcvled->pin,can->config.rcvled->init?0:1); + } else { + if(can->status.rcvchange == 1 || can->status.sndchange == 1) + { + can->status.rcvchange = 0; + can->status.sndchange = 0; + rt_pin_write(can->config.rcvled->pin,rt_pin_read(can->config.rcvled->pin)?0:1); + } else { + rt_pin_write(can->config.rcvled->pin,can->config.rcvled->init); + } + } + } else if(can->config.rcvled != RT_NULL && can->config.sndled != RT_NULL) { + if(ledonflag == 1) { + rt_pin_write(can->config.rcvled->pin,can->config.rcvled->init?0:1); + rt_pin_write(can->config.sndled->pin,can->config.sndled->init?0:1); + } else { + if(can->status.rcvchange == 1) + { + can->status.rcvchange = 0; + rt_pin_write(can->config.rcvled->pin,rt_pin_read(can->config.rcvled->pin)?0:1); + } else { + rt_pin_write(can->config.rcvled->pin,can->config.rcvled->init); + } + if(can->status.sndchange == 1) + { + can->status.sndchange = 0; + rt_pin_write(can->config.sndled->pin,rt_pin_read(can->config.sndled->pin)?0:1); + } else { + rt_pin_write(can->config.sndled->pin,can->config.sndled->init); + } + } + } else if(can->config.rcvled == RT_NULL && can->config.sndled != RT_NULL) { + if(ledonflag == 1) { + rt_pin_write(can->config.sndled->pin,can->config.sndled->init?0:1); + } else { + if(can->status.rcvchange == 1 || can->status.sndchange == 1) + { + can->status.rcvchange = 0; + can->status.sndchange = 0; + rt_pin_write(can->config.sndled->pin,rt_pin_read(can->config.sndled->pin)?0:1); + } else { + rt_pin_write(can->config.sndled->pin,can->config.sndled->init); + } + } + } + if(ledonflag == 1) { + rt_pin_write(can->config.errled->pin,can->config.errled->init?0:1); + } else { + if(can->status.errcode) { + rt_pin_write(can->config.errled->pin,can->config.errled->init?0:1); + } else { + rt_pin_write(can->config.errled->pin,can->config.errled->init); + } + } + #endif + if(can->status_indicate.ind != RT_NULL) + { + can->status_indicate.ind(can,can->status_indicate.args); + } +} + +/* + * can register + */ +rt_err_t rt_hw_can_register(struct rt_can_device *can, + const char *name, + const struct rt_can_ops *ops, + void *data) +{ + struct rt_device *device; + RT_ASSERT(can != RT_NULL); + + device = &(can->parent); + + device->type = RT_Device_Class_CAN; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; +#ifdef RT_CAN_USING_HDR + can->hdr = RT_NULL; +#endif + can->can_rx = RT_NULL; + can->can_tx = RT_NULL; + device->init = rt_can_init; + device->open = rt_can_open; + device->close = rt_can_close; + device->read = rt_can_read; + device->write = rt_can_write; + device->control = rt_can_control; + can->ops = ops; + + can->status_indicate.ind = RT_NULL; + can->status_indicate.args = RT_NULL; + rt_memset(&can->status,0,sizeof(can->status)); + + device->user_data = data; + can->timerinitflag = 0; + if(can->config.rcvled != RT_NULL || + can->config.sndled != RT_NULL || + can->config.errled != RT_NULL) + { + rt_timer_init(&can->timer, + name, + cantimeout, + (void*)can, + can->config.ticks, + RT_TIMER_FLAG_PERIODIC); + } + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR); +} + +/* ISR for can interrupt */ +void rt_hw_can_isr(struct rt_can_device *can, int event) +{ + switch (event & 0xff) + { + case RT_CAN_EVENT_RXOF_IND: + { + rt_base_t level; + level = rt_hw_interrupt_disable(); + can->status.dropedrcvpkg++; + rt_hw_interrupt_enable(level); + } + case RT_CAN_EVENT_RX_IND: + { + struct rt_can_msg tmpmsg; + struct rt_can_rx_fifo* rx_fifo; + struct rt_can_msg_list* listmsg=RT_NULL; +#ifdef RT_CAN_USING_HDR + rt_int32_t hdr; +#endif + int ch = -1; + rt_base_t level; + rx_fifo = (struct rt_can_rx_fifo*)can->can_rx; + RT_ASSERT(rx_fifo != RT_NULL); + /* interrupt mode receive */ + RT_ASSERT(can->parent.open_flag & RT_DEVICE_FLAG_INT_RX); + + rt_uint32_t no; + no = event >> 8; + ch = can->ops->recvmsg(can,&tmpmsg,no); + if (ch == -1) break; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + can->status.rcvpkg++; + can->status.rcvchange = 1; + if(!rt_list_isempty(&rx_fifo->freelist)) + { + listmsg = rt_list_entry(rx_fifo->freelist.next, struct rt_can_msg_list, list); + rt_list_remove(&listmsg->list); +#ifdef RT_CAN_USING_HDR + rt_list_remove(&listmsg->hdrlist); + if(listmsg->owner != RT_NULL && listmsg->owner->msgs) { + listmsg->owner->msgs--; + } + listmsg->owner = RT_NULL; +#endif /*RT_CAN_USING_HDR*/ + RT_ASSERT(rx_fifo->freenumbers >0); + rx_fifo->freenumbers--; + } else if(!rt_list_isempty(&rx_fifo->uselist)) { + listmsg = rt_list_entry(rx_fifo->uselist.next, struct rt_can_msg_list, list); + can->status.dropedrcvpkg++; + rt_list_remove(&listmsg->list); +#ifdef RT_CAN_USING_HDR + rt_list_remove(&listmsg->hdrlist); + if(listmsg->owner != RT_NULL && listmsg->owner->msgs) { + listmsg->owner->msgs--; + } + listmsg->owner = RT_NULL; +#endif + } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + if(listmsg != RT_NULL) { + rt_memcpy(&listmsg->data,&tmpmsg,sizeof(struct rt_can_msg)); + level = rt_hw_interrupt_disable(); + rt_list_insert_before(&rx_fifo->uselist,&listmsg->list); +#ifdef RT_CAN_USING_HDR + hdr = tmpmsg.hdr; + if(can->hdr != RT_NULL) { + RT_ASSERT(hdr < can->config.maxhdr && hdr >= 0); + if(can->hdr[hdr].connected) { + rt_list_insert_before(&can->hdr[hdr].list,&listmsg->hdrlist); + listmsg->owner = &can->hdr[hdr]; + can->hdr[hdr].msgs++; + } + + } +#endif + rt_hw_interrupt_enable(level); + } + + /* invoke callback */ +#ifdef RT_CAN_USING_HDR + if(can->hdr != RT_NULL && can->hdr[hdr].connected && can->hdr[hdr].filter.ind) { + RT_ASSERT(hdr < can->config.maxhdr && hdr >= 0); + rt_size_t rx_length; + level = rt_hw_interrupt_disable(); + rx_length = can->hdr[hdr].msgs * sizeof(struct rt_can_msg); + rt_hw_interrupt_enable(level); + can->hdr[hdr].filter.ind(&can->parent, can->hdr[hdr].filter.args, hdr, rx_length); + + } else +#endif + if (can->parent.rx_indicate != RT_NULL) { + rt_size_t rx_length; + /* get rx length */ + level = rt_hw_interrupt_disable(); + rx_length = rx_fifo->freenumbers*sizeof(struct rt_can_msg); + rt_hw_interrupt_enable(level); + + can->parent.rx_indicate(&can->parent, rx_length); + } + break; + } + case RT_CAN_EVENT_TX_DONE: + case RT_CAN_EVENT_TX_FAIL: + { + struct rt_can_tx_fifo* tx_fifo; + rt_uint32_t no; + no = event >> 8; + tx_fifo = (struct rt_can_tx_fifo*) can->can_tx; + RT_ASSERT(tx_fifo != RT_NULL); + if((event & 0xff) == RT_CAN_EVENT_TX_DONE) { + tx_fifo->buffer[no].result = RT_CAN__SND_RESUTL_OK; + } else { + tx_fifo->buffer[no].result = RT_CAN__SND_RESUTL_ERR; + } + rt_completion_done(&(tx_fifo->buffer[no].completion)); + break; + } + } +} +#ifdef RT_USING_FINSH +#include +int cmd_canstat(int argc,void** argv) +{ + static const char* ErrCode[] = { + "No Error!", + "Warning !", + "Passive !", + "Bus Off !" + }; + if(argc >= 2) { + rt_device_t candev = rt_device_find(argv[1]); + if(!candev) { + rt_kprintf(" Can't find can device %s\n",argv[1]); + return -1; + } + rt_kprintf(" Finded can device: %s...",argv[1]); + struct rt_can_status status; + rt_device_control(candev,RT_CAN_CMD_GET_STATUS,&status); + rt_kprintf("\n Receive...error..count: %010ld. Send.....error....count: %010ld.", + status.rcverrcnt,status.snderrcnt); + rt_kprintf("\n Bit..pad..error..count: %010ld. Format...error....count: %010ld", + status.bitpaderrcnt,status.formaterrcnt); + rt_kprintf("\n Ack.......error..count: %010ld. Bit......error....count: %010ld.", + status.ackerrcnt,status.biterrcnt); + rt_kprintf("\n CRC.......error..count: %010ld. Error.code.[%010ld]: ", + status.crcerrcnt,status.errcode); + switch(status.errcode) { + case 0: + rt_kprintf("%s.",ErrCode[0]); + break; + case 1: + rt_kprintf("%s.",ErrCode[1]); + break; + case 2: + case 3: + rt_kprintf("%s.",ErrCode[2]); + break; + case 4: + case 5: + case 6: + case 7: + rt_kprintf("%s.",ErrCode[3]); + break; + } + rt_kprintf("\n Total.receive.packages: %010ld. Droped.receive.packages: %010ld.", + status.rcvpkg,status.dropedrcvpkg); + rt_kprintf("\n Total..send...packages: %010ld. Droped...send..packages: %010ld.\n", + status.sndpkg + status.dropedsndpkg,status.dropedsndpkg); + } else { + rt_kprintf(" Invalid Call %s\n",argv[0]); + rt_kprintf(" Please using %s cannamex .Here canname is driver name and x is candrive number.\n",argv[0]); + } + return 0; +} +FINSH_FUNCTION_EXPORT_ALIAS(cmd_canstat, __cmd_canstat, Stat Can Device Status.); +#endif diff --git a/components/drivers/include/drivers/can.h b/components/drivers/include/drivers/can.h new file mode 100644 index 0000000000..0bd4106ee0 --- /dev/null +++ b/components/drivers/include/drivers/can.h @@ -0,0 +1,292 @@ +/* + * File : can.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2015, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + */ +#ifndef CAN_H_ +#define CAN_H_ + +#ifndef RT_CANMSG_BOX_SZ +#define RT_CANMSG_BOX_SZ 16 +#endif +#ifndef RT_CANSND_BOX_NUM +#define RT_CANSND_BOX_NUM 1 +#endif + +enum CANBAUD +{ + CAN1MBaud=0, // 1 MBit/sec + CAN800kBaud, // 800 kBit/sec + CAN500kBaud, // 500 kBit/sec + CAN250kBaud, // 250 kBit/sec + CAN125kBaud, // 125 kBit/sec + CAN100kBaud, // 100 kBit/sec + CAN50kBaud, // 50 kBit/sec + CAN20kBaud, // 20 kBit/sec + CAN10kBaud // 10 kBit/sec +}; +#define RT_CAN_MODE_NORMAL 0 +#define RT_CAN_MODE_LISEN 1 +#define RT_CAN_MODE_LOOPBACK 2 +#define RT_CAN_MODE_LOOPBACKANLISEN 3 + +#define RT_CAN_MODE_PRIV 0x01 +#define RT_CAN_MODE_NOPRIV 0x00 + +#ifdef RT_CAN_USING_LED +struct rt_can_led +{ + rt_uint32_t pin,mode,init; + struct rt_timer* timer; + const char* timer_name; +}; +#endif /*RT_CAN_USING_LED*/ + +struct rt_can_filter_item +{ + rt_uint32_t id :29; + rt_uint32_t ide :1; + rt_uint32_t rtr :1; + rt_uint32_t mode :1; + rt_uint32_t mask; + rt_int32_t hdr; + rt_err_t (*ind)(rt_device_t dev, void* args ,rt_int32_t hdr, rt_size_t size); + void* args; +}; +#ifdef RT_CAN_USING_HDR +#define RT_CAN_FILTER_ITEM_INIT(id,ide,rtr,mode,mask,ind,args) \ + {\ + id,\ + ide,\ + rtr,\ + mode,\ + mask,\ + -1,\ + ind,\ + args,\ + } +#define RT_CAN_FILTER_STD_INIT(id,ind,args) \ + RT_CAN_FILTER_ITEM_INIT(id,0,0,0,0xFFFFFFFF,ind,args) +#define RT_CAN_FILTER_EXT_INIT(id,ind,args) \ + RT_CAN_FILTER_ITEM_INIT(id,1,0,0,0xFFFFFFFF,ind,args) +#define RT_CAN_STD_RMT_FILTER_INIT(id,ind,args) \ + RT_CAN_FILTER_ITEM_INIT(id,0,1,0,0xFFFFFFFF,ind,args) +#define RT_CAN_EXT_RMT_FILTER_INIT(id,ind,args) \ + RT_CAN_FILTER_ITEM_INIT(id,1,1,0,0xFFFFFFFF,ind,args) +#define RT_CAN_STD_RMT_DATA_FILTER_INIT(id,ind,args) \ + RT_CAN_FILTER_ITEM_INIT(id,0,0,1,0xFFFFFFFF,ind,args) +#define RT_CAN_EXT_RMT_DATA_FILTER_INIT(id,ind,args) \ + RT_CAN_FILTER_ITEM_INIT(id,1,0,1,0xFFFFFFFF,ind,args) +#else +#define RT_CAN_FILTER_ITEM_INIT(id,ide,rtr,mode,mask,args) \ + {\ + id,\ + ide,\ + rtr,\ + mode,\ + mask,\ + -1,\ + args,\ + } +#define RT_CAN_FILTER_STD_INIT(id,args) \ + RT_CAN_FILTER_ITEM_INIT(id,0,0,0,0xFFFFFFFF,args) +#define RT_CAN_FILTER_EXT_INIT(id,args) \ + RT_CAN_FILTER_ITEM_INIT(id,1,0,0,0xFFFFFFFF,args) +#define RT_CAN_STD_RMT_FILTER_INIT(id,args) \ + RT_CAN_FILTER_ITEM_INIT(id,0,1,0,0xFFFFFFFF,args) +#define RT_CAN_EXT_RMT_FILTER_INIT(id,args) \ + RT_CAN_FILTER_ITEM_INIT(id,1,1,0,0xFFFFFFFF,args) +#define RT_CAN_STD_RMT_DATA_FILTER_INIT(id,args) \ + RT_CAN_FILTER_ITEM_INIT(id,0,0,1,0xFFFFFFFF,args) +#define RT_CAN_EXT_RMT_DATA_FILTER_INIT(id,args) \ + RT_CAN_FILTER_ITEM_INIT(id,1,0,1,0xFFFFFFFF,args) +#endif + +struct rt_can_filter_config +{ + rt_uint32_t count; + rt_uint32_t actived; + struct rt_can_filter_item* items; +}; +struct can_configure +{ + rt_uint32_t baud_rate; + rt_uint32_t msgboxsz; + rt_uint32_t sndboxnumber; + rt_uint32_t mode :8; + rt_uint32_t privmode :8; + rt_uint32_t reserved :16; + #ifdef RT_CAN_USING_LED + const struct rt_can_led* rcvled; + const struct rt_can_led* sndled; + const struct rt_can_led* errled; + #endif /*RT_CAN_USING_LED*/ + rt_uint32_t ticks; +#ifdef RT_CAN_USING_HDR + rt_uint32_t maxhdr; +#endif +}; + +#define CANDEFAULTCONFIG \ +{\ + CAN1MBaud,\ + RT_CANMSG_BOX_SZ,\ + RT_CANSND_BOX_NUM,\ + RT_CAN_MODE_NORMAL,\ +}; + +struct rt_can_ops; +#define RT_CAN_CMD_SET_FILTER 0x13 +#define RT_CAN_CMD_SET_BAUD 0x14 +#define RT_CAN_CMD_SET_MODE 0x15 +#define RT_CAN_CMD_SET_PRIV 0x16 +#define RT_CAN_CMD_GET_STATUS 0x17 +#define RT_CAN_CMD_SET_STATUS_IND 0x18 + +#define RT_DEVICE_CAN_INT_ERR 0x1000 + +enum RT_CAN_STATUS_MODE +{ + NORMAL = 0, + ERRWARNING = 1, + ERRPASSIVE = 2, + BUSOFF = 4, +}; +enum RT_CAN_BUS_ERR +{ + RT_CAN_BUS_NO_ERR = 0, + RT_CAN_BUS_BIT_PAD_ERR = 1, + RT_CAN_BUS_FORMAT_ERR = 2, + RT_CAN_BUS_ACK_ERR = 3, + RT_CAN_BUS_IMPLICIT_BIT_ERR = 4, + RT_CAN_BUS_EXPLICIT_BIT_ERR = 5, + RT_CAN_BUS_CRC_ERR = 6, +}; +struct rt_can_status +{ + rt_uint32_t rcverrcnt; + rt_uint32_t snderrcnt; + rt_uint32_t errcode; + rt_uint32_t rcvpkg; + rt_uint32_t dropedrcvpkg; + rt_uint32_t sndpkg; + rt_uint32_t dropedsndpkg; + rt_uint32_t bitpaderrcnt; + rt_uint32_t formaterrcnt; + rt_uint32_t ackerrcnt; + rt_uint32_t biterrcnt; + rt_uint32_t crcerrcnt; + rt_uint32_t rcvchange; + rt_uint32_t sndchange; + rt_uint32_t lasterrtype; +}; +#ifdef RT_CAN_USING_HDR +struct rt_can_hdr { + rt_uint32_t connected; + rt_uint32_t msgs; + struct rt_can_filter_item filter; + struct rt_list_node list; +}; +#endif +struct rt_can_device; +typedef rt_err_t (*rt_canstatus_ind)(struct rt_can_device*, void*); +typedef struct rt_can_status_ind_type +{ + rt_canstatus_ind ind; + void* args; +} *rt_can_status_ind_type_t; +struct rt_can_device +{ + struct rt_device parent; + + const struct rt_can_ops *ops; + struct can_configure config; + struct rt_can_status status; + rt_uint32_t timerinitflag; + struct rt_timer timer; + struct rt_can_status_ind_type status_indicate; +#ifdef RT_CAN_USING_HDR + struct rt_can_hdr* hdr; +#endif + void *can_rx; + void *can_tx; +}; +typedef struct rt_can_device *rt_can_t; + +#define RT_CAN_STDID 0 +#define RT_CAN_EXTID 1 +#define RT_CAN_DTR 0 +#define RT_CAN_RTR 1 + +typedef struct rt_can_status * rt_can_status_t; +struct rt_can_msg +{ + rt_uint32_t id :29; + rt_uint32_t ide :1; + rt_uint32_t rtr :1; + rt_uint32_t rsv :1; + rt_uint32_t len :8; + rt_uint32_t priv :8; + rt_uint32_t hdr :8; + rt_uint32_t reserved :8; + rt_uint8_t data[8]; +}; +typedef struct rt_can_msg* rt_can_msg_t; +struct rt_can_msg_list { + struct rt_list_node list; +#ifdef RT_CAN_USING_HDR + struct rt_list_node hdrlist; + struct rt_can_hdr* owner; +#endif + struct rt_can_msg data; +}; +struct rt_can_rx_fifo +{ + /* software fifo */ + struct rt_can_msg_list *buffer; + rt_uint32_t freenumbers; + struct rt_list_node freelist; + struct rt_list_node uselist; +}; + +#define RT_CAN__SND_RESUTL_OK 0 +#define RT_CAN__SND_RESUTL_ERR 1 +#define RT_CAN__SND_RESUTL_WAIT 2 + +#define RT_CAN_EVENT_RX_IND 0x01 /* Rx indication */ +#define RT_CAN_EVENT_TX_DONE 0x02 /* Tx complete */ +#define RT_CAN_EVENT_TX_FAIL 0x03 /* Tx complete */ +#define RT_CAN_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */ +#define RT_CAN_EVENT_RXOF_IND 0x06 /* Rx overflow */ + +struct rt_can_sndbxinx_list { + struct rt_list_node list; + struct rt_completion completion; + rt_uint32_t result; +}; +struct rt_can_tx_fifo +{ + struct rt_can_sndbxinx_list *buffer; + struct rt_completion completion; + struct rt_list_node freelist; +}; +struct rt_can_ops +{ + rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg); + rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg); + int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno); + int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno); +}; +rt_err_t rt_hw_can_register(struct rt_can_device *can, + const char *name, + const struct rt_can_ops *ops, + void *data); +void rt_hw_can_isr(struct rt_can_device *can, int event); +#endif /*_CAN_H*/ diff --git a/components/drivers/include/rtdevice.h b/components/drivers/include/rtdevice.h index 5d74ed6199..f4d967831c 100644 --- a/components/drivers/include/rtdevice.h +++ b/components/drivers/include/rtdevice.h @@ -366,6 +366,10 @@ rt_inline void rt_work_init(struct rt_work* work, void (*work_func)(struct rt_wo #include "drivers/pin.h" #endif +#ifdef RT_USING_CAN +#include "drivers/can.h" +#endif + #ifdef __cplusplus } #endif From 707a6577446594653a3a8cec77dce4e4604ec108 Mon Sep 17 00:00:00 2001 From: weety Date: Thu, 14 May 2015 22:41:31 +0800 Subject: [PATCH 15/18] [FTP server] 1.Fixed PASV mode issue; 2.Implement RNFR and RNTO command; 3.Change some command code according RFC959; 4.Add command for msh shell; 5.Implement "noop" command. --- components/net/lwip/apps/ftpd.c | 264 +++++++++++++++++++++++++++----- 1 file changed, 229 insertions(+), 35 deletions(-) diff --git a/components/net/lwip/apps/ftpd.c b/components/net/lwip/apps/ftpd.c index af48237e42..df1609fe1d 100644 --- a/components/net/lwip/apps/ftpd.c +++ b/components/net/lwip/apps/ftpd.c @@ -11,17 +11,24 @@ #define FTP_MAX_CONNECTION 2 #define FTP_USER "rtt" #define FTP_PASSWORD "demo" -#define FTP_WELCOME_MSG "220-= welcome on RT-Thread FTP server =-\r\n220 \r\n" +#define FTP_WELCOME_MSG "220 welcome on RT-Thread FTP server.\r\n" #define FTP_BUFFER_SIZE 1024 +#define INET_ADDRSTRLEN 16 + + struct ftp_session { rt_bool_t is_anonymous; int sockfd; struct sockaddr_in remote; + struct sockaddr_in server; + + char serveraddr[INET_ADDRSTRLEN]; /* pasv data */ + int pasv_listen_sockfd; char pasv_active; int pasv_sockfd; @@ -43,6 +50,7 @@ struct ftp_session* ftp_new_session() struct ftp_session* session; session = (struct ftp_session*)rt_malloc(sizeof(struct ftp_session)); + rt_memset((void *)session, 0, sizeof(struct ftp_session)); session->next = session_list; session_list = session; @@ -71,6 +79,83 @@ void ftp_close_session(struct ftp_session* session) rt_free(session); } +static int open_data_connection(struct ftp_session* session) +{ + socklen_t len = sizeof(struct sockaddr); + struct sockaddr_in sin; +#if 0 + /* Previous PORT command from client */ + if (ctrl->data_address[0]) { + ctrl->data_sd = socket(AF_INET, SOCK_STREAM, 0); + if (-1 == ctrl->data_sd) { + printf("Failed creating data socket"); + return -1; + } + + memset(&sin, 0, sizeof(sin)); + sin.sin_family = AF_INET; + sin.sin_port = htons(ctrl->data_port); + inet_aton(ctrl->data_address, &(sin.sin_addr)); + + if (connect(ctrl->data_sd, (struct sockaddr *)&sin, len) == -1) { + printf("Failed connecting data socket to client"); + close(ctrl->data_sd); + ctrl->data_sd = -1; + + return -1; + } + + DBG("Connected successfully to client's previously requested address:PORT %s:%d", ctrl->data_address, ctrl->data_port); + return 0; + } +#endif + /* Previous PASV command, accept connect from client */ + if (session->pasv_listen_sockfd > 0) { + char client_ip[100]; + + session->pasv_sockfd = accept(session->pasv_listen_sockfd, (struct sockaddr *)&sin, &len); + if (-1 == session->pasv_sockfd) { + printf("Failed accepting connection from client"); + return -1; + } + + len = sizeof(struct sockaddr); + if (-1 == getpeername(session->pasv_sockfd, (struct sockaddr *)&sin, &len)) { + printf("Cannot determine client address"); + closesocket(session->pasv_sockfd); + session->pasv_sockfd = -1; + return -1; + } + + printf("Client PASV data connection from %s\n", inet_ntoa(sin.sin_addr)); + } + + return 0; +} + +static void close_data_connection(struct ftp_session* session) +{ + /* PASV server listening socket */ + if (session->pasv_listen_sockfd > 0) { + closesocket(session->pasv_listen_sockfd); + session->pasv_listen_sockfd = -1; + } + + /* PASV client socket */ + if (session->pasv_sockfd > 0) { + closesocket(session->pasv_sockfd); + session->pasv_sockfd = -1; + } +#if 0 + /* PORT */ + if (ctrl->data_address[0]) { + ctrl->data_address[0] = 0; + ctrl->data_port = 0; + } +#endif +} + + int ftp_get_filesize(char * filename) { int pos; @@ -179,6 +264,10 @@ void ftpd_thread_entry(void* parameter) session = ftp_new_session(); if (session != NULL) { + if (-1 == getsockname(com_socket, (struct sockaddr *)&session->server, &addr_len)) { + printf("Cannot determine our address, need it if client should connect to us\n"); + } + ipaddr_ntoa_r(&(session->server.sin_addr), session->serveraddr, sizeof(session->serveraddr)); strcpy(session->currentdir, FTP_SRV_ROOT); session->sockfd = com_socket; session->remote = remote; @@ -201,6 +290,7 @@ void ftpd_thread_entry(void* parameter) rt_kprintf("Client %s disconnected\n", inet_ntoa(session->remote.sin_addr)); FD_CLR(session->sockfd, &readfds); closesocket(session->sockfd); + session->sockfd = -1; ftp_close_session(session); } else @@ -210,6 +300,7 @@ void ftpd_thread_entry(void* parameter) { rt_kprintf("Client %s disconnected\r\n", inet_ntoa(session->remote.sin_addr)); closesocket(session->sockfd); + session->sockfd = -1; ftp_close_session(session); } } @@ -359,7 +450,7 @@ int ftp_process_request(struct ftp_session* session, char *buf) } else if (strcmp(parameter_ptr, FTP_USER) == 0) { - session->is_anonymous = RT_FALSE; + session->is_anonymous = RT_FALSE; rt_sprintf(sbuf, "331 Password required for %s\r\n", parameter_ptr); send(session->sockfd, sbuf, strlen(sbuf), 0); } @@ -380,25 +471,26 @@ int ftp_process_request(struct ftp_session* session, char *buf) session->is_anonymous == RT_TRUE) { // password correct - rt_sprintf(sbuf, "230 User logged in\r\n"); + rt_sprintf(sbuf, "230 User logged in.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); + rt_free(sbuf); return 0; } // incorrect password rt_sprintf(sbuf, "530 Login or Password incorrect. Bye!\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); + rt_free(sbuf); return -1; } else if(str_begin_with(buf, "LIST")==0 ) { memset(sbuf,0,FTP_BUFFER_SIZE); + open_data_connection(session); rt_sprintf(sbuf, "150 Opening Binary mode connection for file list.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); do_list(session->currentdir, session->pasv_sockfd); - closesocket(session->pasv_sockfd); + close_data_connection(session); session->pasv_active = 0; rt_sprintf(sbuf, "226 Transfert Complete.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); @@ -408,8 +500,9 @@ int ftp_process_request(struct ftp_session* session, char *buf) memset(sbuf, 0, FTP_BUFFER_SIZE); rt_sprintf(sbuf, "150 Opening Binary mode connection for file list.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); + open_data_connection(session); do_simple_list(session->currentdir, session->pasv_sockfd); - closesocket(session->pasv_sockfd); + close_data_connection(session); session->pasv_active = 0; rt_sprintf(sbuf, "226 Transfert Complete.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); @@ -436,8 +529,20 @@ int ftp_process_request(struct ftp_session* session, char *buf) else if(str_begin_with(buf, "PASV")==0) { int dig1, dig2; - int sockfd; - char optval='1'; + //int sockfd; + int optval=1; + int port; + struct sockaddr_in data; + socklen_t len = sizeof(struct sockaddr); + char *msg, *p; + + if (session->pasv_sockfd > 0) { + closesocket(session->pasv_sockfd); + session->pasv_sockfd = -1; + } + + if (session->pasv_listen_sockfd > 0) + closesocket(session->pasv_listen_sockfd); session->pasv_port = 10000; session->pasv_active = 1; @@ -448,40 +553,63 @@ int ftp_process_request(struct ftp_session* session, char *buf) dig2 = session->pasv_port % 256; FD_ZERO(&readfds); - if((sockfd=socket(PF_INET, SOCK_STREAM, 0))==-1) + if((session->pasv_listen_sockfd=socket(PF_INET, SOCK_STREAM, 0))==-1) { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); + rt_sprintf(sbuf, "425 Can't open data connection0.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); goto err1; } - if(setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &optval, sizeof(optval))==-1) + if(setsockopt(session->pasv_listen_sockfd, SOL_SOCKET, SO_REUSEADDR, &optval, sizeof(optval))==-1) { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); + rt_sprintf(sbuf, "425 Can't open data connection1.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); goto err1; } - if(bind(sockfd, (struct sockaddr *)&local, addr_len)==-1) + if(bind(session->pasv_listen_sockfd, (struct sockaddr *)&local, addr_len)==-1) { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); + rt_sprintf(sbuf, "425 Can't open data connection2.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); goto err1; } - if(listen(sockfd, 1)==-1) + if(listen(session->pasv_listen_sockfd, 1)==-1) { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); + rt_sprintf(sbuf, "425 Can't open data connection3.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); goto err1; } + if (-1 == getsockname(session->pasv_listen_sockfd, (struct sockaddr *)&data, &len)) { + rt_kprintf("Cannot determine our address, need it if client should connect to us\n"); + goto err1; + } + + port = ntohs(data.sin_port); + rt_kprintf("Port %d\n", port); + + /* Convert server IP address and port to comma separated list */ + msg = strdup(session->serveraddr); + if (!msg) { + rt_sprintf(sbuf, "426 Internal server error.\r\n"); + send(session->sockfd, sbuf, strlen(sbuf), 0); + goto err1; + } + p = msg; + while ((p = strchr(p, '.'))) + *p++ = ','; + rt_kprintf("Listening %d seconds @ port %d\n", tv.tv_sec, session->pasv_port); - rt_sprintf(sbuf, "227 Entering passive mode (%d,%d,%d,%d,%d,%d)\r\n", 127, 0, 0, 1, dig1, dig2); + rt_sprintf(sbuf, "227 Entering passive mode (%s,%d,%d)\r\n", msg, port / 256, port % 256); send(session->sockfd, sbuf, strlen(sbuf), 0); + rt_free(sbuf); + rt_free(msg); + return 0; + #if 0 FD_SET(sockfd, &readfds); select(0, &readfds, 0, 0, &tv); if(FD_ISSET(sockfd, &readfds)) { if((session->pasv_sockfd = accept(sockfd, (struct sockaddr*)&pasvremote, &addr_len))==-1) { - rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); + rt_sprintf(sbuf, "425 Can't open data connection4.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); goto err1; } @@ -500,11 +628,21 @@ err1: rt_free(sbuf); return 0; } + #endif +err1: + close_data_connection(session); + session->pasv_active = 0; + rt_free(sbuf); + rt_free(msg); + return 0; + } else if (str_begin_with(buf, "RETR")==0) { int file_size; + open_data_connection(session); + strcpy(filename, buf + 5); build_full_path(session, parameter_ptr, filename, 256); @@ -514,13 +652,15 @@ err1: rt_sprintf(sbuf, "550 \"%s\" : not a regular file\r\n", filename); send(session->sockfd, sbuf, strlen(sbuf), 0); session->offset=0; - rt_free(sbuf); + close_data_connection(session); + rt_free(sbuf); return 0; } fd = open(filename, O_RDONLY, 0); if (fd < 0) { + close_data_connection(session); rt_free(sbuf); return 0; } @@ -543,14 +683,16 @@ err1: rt_sprintf(sbuf, "226 Finished.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); close(fd); - closesocket(session->pasv_sockfd); + close_data_connection(session); } else if (str_begin_with(buf, "STOR")==0) { + open_data_connection(session); if(session->is_anonymous == RT_TRUE) { rt_sprintf(sbuf, "550 Permission denied.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); + close_data_connection(session); rt_free(sbuf); return 0; } @@ -562,6 +704,7 @@ err1: { rt_sprintf(sbuf, "550 Cannot open \"%s\" for writing.\r\n", filename); send(session->sockfd, sbuf, strlen(sbuf), 0); + close_data_connection(session); rt_free(sbuf); return 0; } @@ -579,7 +722,7 @@ err1: else if(numbytes==0) { close(fd); - closesocket(session->pasv_sockfd); + close_data_connection(session); rt_sprintf(sbuf, "226 Finished.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); break; @@ -587,12 +730,12 @@ err1: else if(numbytes==-1) { close(fd); - closesocket(session->pasv_sockfd); + close_data_connection(session); rt_free(sbuf); return -1; } } - closesocket(session->pasv_sockfd); + close_data_connection(session); } else if(str_begin_with(buf, "SIZE")==0) { @@ -659,7 +802,7 @@ err1: send(session->sockfd, sbuf, strlen(sbuf), 0); closesocket(session->pasv_sockfd); session->pasv_active = 0; - rt_free(sbuf); + rt_free(sbuf); return 0; } pasvremote.sin_addr.s_addr=inet_addr(tmpip); @@ -674,7 +817,7 @@ err1: rt_sprintf(sbuf, "425 Can't open data connection.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); closesocket(session->pasv_sockfd); - rt_free(sbuf); + rt_free(sbuf); return 0; } } @@ -697,9 +840,9 @@ err1: { if (session->is_anonymous == RT_TRUE) { - rt_sprintf(sbuf, "550 Permission denied.\r\n"); + rt_sprintf(sbuf, "530 Permission denied.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); + rt_free(sbuf); return 0; } @@ -720,7 +863,7 @@ err1: { if (session->is_anonymous == RT_TRUE) { - rt_sprintf(sbuf, "550 Permission denied.\r\n"); + rt_sprintf(sbuf, "530 Permission denied.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); rt_free(sbuf); return 0; @@ -740,9 +883,9 @@ err1: { if (session->is_anonymous == RT_TRUE) { - rt_sprintf(sbuf, "550 Permission denied.\r\n"); + rt_sprintf(sbuf, "530 Permission denied.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); + rt_free(sbuf); return 0; } build_full_path(session, parameter_ptr, filename, 256); @@ -758,12 +901,53 @@ err1: send(session->sockfd, sbuf, strlen(sbuf), 0); } } - + else if(str_begin_with(buf, "RNFR")==0) + { + if (session->is_anonymous == RT_TRUE) + { + rt_sprintf(sbuf, "530 Permission denied.\r\n"); + send(session->sockfd, sbuf, strlen(sbuf), 0); + rt_free(sbuf); + return 0; + } + build_full_path(session, parameter_ptr, filename, 256); + + rt_sprintf(sbuf, "350 Successfully rececive old file \"%s\".\r\n", filename); + send(session->sockfd, sbuf, strlen(sbuf), 0); + } + else if(str_begin_with(buf, "RNTO")==0) + { + char new_filename[256]; + if (session->is_anonymous == RT_TRUE) + { + rt_sprintf(sbuf, "530 Permission denied.\r\n"); + send(session->sockfd, sbuf, strlen(sbuf), 0); + rt_free(sbuf); + return 0; + } + build_full_path(session, parameter_ptr, new_filename, 256); + + if(rename(filename, new_filename) == -1) + { + rt_sprintf(sbuf, "553 rename file \"%s\" error.\r\n", filename); + send(session->sockfd, sbuf, strlen(sbuf), 0); + } + else + { + rt_sprintf(sbuf, "250 Successfully rename to new file \"%s\".\r\n", filename); + send(session->sockfd, sbuf, strlen(sbuf), 0); + } + } + else if((str_begin_with(buf, "NOOP")==0) || str_begin_with(buf, "noop")==0) + { + rt_sprintf(sbuf, "200 noop!\r\n"); + send(session->sockfd, sbuf, strlen(sbuf), 0); + } else if(str_begin_with(buf, "QUIT")==0) { rt_sprintf(sbuf, "221 Bye!\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); - rt_free(sbuf); + rt_free(sbuf); return -1; } else @@ -771,7 +955,7 @@ err1: rt_sprintf(sbuf, "502 Not Implemented.\r\n"); send(session->sockfd, sbuf, strlen(sbuf), 0); } - rt_free(sbuf); + rt_free(sbuf); return 0; } @@ -787,5 +971,15 @@ void ftpd_start() #ifdef RT_USING_FINSH #include -FINSH_FUNCTION_EXPORT(ftpd_start, start ftp server) +FINSH_FUNCTION_EXPORT(ftpd_start, start ftp server); + +#ifdef FINSH_USING_MSH +int cmd_ftpd_start(int argc, char** argv) +{ + ftpd_start(); + return 0; +} +FINSH_FUNCTION_EXPORT_ALIAS(cmd_ftpd_start, __cmd_ftpd_start, start ftp server.); +#endif + #endif From 8e29e3d98be63acae431fab47662db3aca9eeeba Mon Sep 17 00:00:00 2001 From: "Aubr.Cool" Date: Thu, 14 May 2015 16:51:47 +0800 Subject: [PATCH 16/18] add author information --- bsp/stm32f10x/applications/canapp.c | 6 +++++- bsp/stm32f10x/drivers/bxcan.c | 3 ++- bsp/stm32f10x/drivers/bxcan.h | 1 + components/drivers/can/can.c | 3 ++- components/drivers/include/drivers/can.h | 3 ++- 5 files changed, 12 insertions(+), 4 deletions(-) diff --git a/bsp/stm32f10x/applications/canapp.c b/bsp/stm32f10x/applications/canapp.c index 7a77df4265..01ca1c9cbb 100644 --- a/bsp/stm32f10x/applications/canapp.c +++ b/bsp/stm32f10x/applications/canapp.c @@ -8,8 +8,11 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes + * Date Author Notes + * 2015-05-14 aubrcool@qq.com first version */ + +#ifdef RT_USING_CAN #include #include #include @@ -139,3 +142,4 @@ int rt_can_app_init(void) } INIT_APP_EXPORT(rt_can_app_init); +#endif /*RT_USING_CAN*/ diff --git a/bsp/stm32f10x/drivers/bxcan.c b/bsp/stm32f10x/drivers/bxcan.c index 0454991708..a21f9f1c4d 100644 --- a/bsp/stm32f10x/drivers/bxcan.c +++ b/bsp/stm32f10x/drivers/bxcan.c @@ -8,7 +8,8 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes + * Date Author Notes + * 2015-05-14 aubrcool@qq.com first version */ #include #include diff --git a/bsp/stm32f10x/drivers/bxcan.h b/bsp/stm32f10x/drivers/bxcan.h index 60ee996a3c..7ef77bde16 100644 --- a/bsp/stm32f10x/drivers/bxcan.h +++ b/bsp/stm32f10x/drivers/bxcan.h @@ -9,6 +9,7 @@ * * Change Logs: * Date Author Notes + * 2015-05-14 aubrcool@qq.com first version */ #ifndef BXCAN_H_ diff --git a/components/drivers/can/can.c b/components/drivers/can/can.c index 3d31409756..8ac3029533 100644 --- a/components/drivers/can/can.c +++ b/components/drivers/can/can.c @@ -8,7 +8,8 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes + * Date Author Notes + * 2015-05-14 aubrcool@qq.com first version */ #include #include diff --git a/components/drivers/include/drivers/can.h b/components/drivers/include/drivers/can.h index 0bd4106ee0..3a24162f03 100644 --- a/components/drivers/include/drivers/can.h +++ b/components/drivers/include/drivers/can.h @@ -8,7 +8,8 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes + * Date Author Notes + * 2015-05-14 aubrcool@qq.com first version */ #ifndef CAN_H_ #define CAN_H_ From c7d703158ad312ba6731a17e2f470492adf19dc4 Mon Sep 17 00:00:00 2001 From: "Aubr.Cool" Date: Fri, 15 May 2015 08:00:14 +0800 Subject: [PATCH 17/18] Add SConscript for can --- components/drivers/can/SConscript | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 components/drivers/can/SConscript diff --git a/components/drivers/can/SConscript b/components/drivers/can/SConscript new file mode 100644 index 0000000000..84ae2a10da --- /dev/null +++ b/components/drivers/can/SConscript @@ -0,0 +1,8 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd + '/../include'] +group = DefineGroup('DeviceDrivers', src, depend = ['RT_USING_CAN'], CPPPATH = CPPPATH) + +Return('group') From 9ea3219ab7ae71741b7158762ed9aeb26a8b069e Mon Sep 17 00:00:00 2001 From: "Aubr.Cool" Date: Fri, 15 May 2015 11:31:12 +0800 Subject: [PATCH 18/18] Add can driver doc --- components/drivers/can/readme-zh.txt | 132 +++++++++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 components/drivers/can/readme-zh.txt diff --git a/components/drivers/can/readme-zh.txt b/components/drivers/can/readme-zh.txt new file mode 100644 index 0000000000..3eb63d155f --- /dev/null +++ b/components/drivers/can/readme-zh.txt @@ -0,0 +1,132 @@ +说明: +本驱动完成了can控制器硬件抽象 +一 CAN Driver 注册 + Can driver注册需要填充以下几个数据结构： + 1、struct can_configure + { + rt_uint32_t baud_rate; + rt_uint32_t msgboxsz; + rt_uint32_t sndboxnumber; + rt_uint32_t mode :8; + rt_uint32_t privmode :8; + rt_uint32_t reserved :16; + #ifdef RT_CAN_USING_LED + const struct rt_can_led* rcvled; + const struct rt_can_led* sndled; + const struct rt_can_led* errled; + #endif /*RT_CAN_USING_LED*/ + rt_uint32_t ticks; + #ifdef RT_CAN_USING_HDR + rt_uint32_t maxhdr; + #endif + }; + struct can_configure 为can驱动的基本配置信息: + baud_rate : + enum CANBAUD + { + CAN1MBaud=0, // 1 MBit/sec + CAN800kBaud, // 800 kBit/sec + CAN500kBaud, // 500 kBit/sec + CAN250kBaud, // 250 kBit/sec + CAN125kBaud, // 125 kBit/sec + CAN100kBaud, // 100 kBit/sec + CAN50kBaud, // 50 kBit/sec + CAN20kBaud, // 20 kBit/sec + CAN10kBaud // 10 kBit/sec + }; + 配置Can的波特率。 + msgboxsz : Can接收邮箱缓冲数量，本驱动在软件层开辟msgboxsz个接收邮箱。 + sndboxnumber : can 发送通道数量，该配置为Can控制器实际的发送通道数量。 + mode ： + #define RT_CAN_MODE_NORMAL 0 正常模式 + #define RT_CAN_MODE_LISEN 1 只听模式 + #define RT_CAN_MODE_LOOPBACK 2 自发自收模式 + #define RT_CAN_MODE_LOOPBACKANLISEN 3 自发自收只听模式 + 配置Can 的工作状态。 + privmode : + #define RT_CAN_MODE_PRIV 0x01 处于优先级模式，高优先级的消息优先发送。 + #define RT_CAN_MODE_NOPRIV 0x00 + 配置Can driver的优先级模式。 + #ifdef RT_CAN_USING_LED + const struct rt_can_led* rcvled; + const struct rt_can_led* sndled; + const struct rt_can_led* errled; + #endif /*RT_CAN_USING_LED*/ + 配置can led信息, 当前can驱动的led使用了 pin驱动， + 开启RT_CAN_USING_LED时要确保当前系统已实现pin驱动。 + rt_uint32_t ticks : 配置Can driver timer周期。 + #ifdef RT_CAN_USING_HDR + rt_uint32_t maxhdr; + #endif + 如果使用硬件过滤，则开启RT_CAN_USING_HDR, maxhdr 为Can控制器过滤表的数量。 + 2、struct rt_can_ops + { + rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg); + rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg); + int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno); + int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno); + }; + struct rt_can_ops 为要实现的特定的can控制器操作。 + rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg); + configure根据配置信息初始化Can控制器工作模式。 + rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg); + control 当前接受以下cmd参数： + #define RT_CAN_CMD_SET_FILTER 0x13 + #define RT_CAN_CMD_SET_BAUD 0x14 + #define RT_CAN_CMD_SET_MODE 0x15 + #define RT_CAN_CMD_SET_PRIV 0x16 + #define RT_CAN_CMD_GET_STATUS 0x17 + #define RT_CAN_CMD_SET_STATUS_IND 0x18 + int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno); + sendmsg向Can控制器发送数，boxno为发送通道号。 + int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno); + recvmsg从Can控制器接收数据，boxno为接收通道号。 + struct rt_can_device + { + struct rt_device parent; + + const struct rt_can_ops *ops; + struct can_configure config; + struct rt_can_status status; + rt_uint32_t timerinitflag; + struct rt_timer timer; + struct rt_can_status_ind_type status_indicate; + #ifdef RT_CAN_USING_HDR + struct rt_can_hdr* hdr; + #endif + void *can_rx; + void *can_tx; + }; + 填充完成后，便可调用rt_hw_can_register完成can驱动的注册。 +二、 CAN Driver 的添加： + 要添加一个新的Can驱动，至少要完成以下接口。 + 1、struct rt_can_ops + { + rt_err_t (*configure)(struct rt_can_device *can, struct can_configure *cfg); + rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg); + int (*sendmsg)(struct rt_can_device *can, const void* buf, rt_uint32_t boxno); + int (*recvmsg)(struct rt_can_device *can,void* buf, rt_uint32_t boxno); + }; + 2、 rt_err_t (*control)(struct rt_can_device *can, int cmd, void *arg); + 接口的 + #define RT_CAN_CMD_SET_FILTER 0x13 + #define RT_CAN_CMD_SET_BAUD 0x14 + #define RT_CAN_CMD_SET_MODE 0x15 + #define RT_CAN_CMD_SET_PRIV 0x16 + #define RT_CAN_CMD_GET_STATUS 0x17 + #define RT_CAN_CMD_SET_STATUS_IND 0x18 + 若干命令。 + 3、can口中断，要完接收，发送结束，以及错误中断。 + #define RT_CAN_EVENT_RX_IND 0x01 /* Rx indication */ + #define RT_CAN_EVENT_TX_DONE 0x02 /* Tx complete */ + #define RT_CAN_EVENT_TX_FAIL 0x03 /* Tx complete */ + #define RT_CAN_EVENT_RX_TIMEOUT 0x05 /* Rx timeout */ + #define RT_CAN_EVENT_RXOF_IND 0x06 /* Rx overflow */ + 中断产生后，调用rt_hw_can_isr(struct rt_can_device *can, int event) + 进入相应的操作，其中接收发送中断的event，最低8位为上面的事件，16到24位为通信通道号。 + 一个作为一个例子，参见bsp/stm32f10x/driver下的bxcan.c 。 +三、CAN Driver的使用： + 一个使用的例子，参数bsp/stm32f10x/applications下的canapp.c +四、当前Can驱动，没有实现轮模式，采用中断模式，bxcan驱动工作在loopback模式下的时候不能读数据。 + +五、当前Can驱动，在stm32f105上测试，暂无问题。