mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-03-27 01:10:20 +08:00
更正stm32/stm32f103-100ask-mini和pro的默认下载器为st-link，添加基于mm32f3270系列由百问网自主设计的火龙果开发板的bsp
This commit is contained in:
slhuan
guo
1
.github/workflows/action.yml
vendored
1
.github/workflows/action.yml
vendored
@@ -86,6 +86,7 @@ jobs:
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- {RTT_BSP: "fujitsu/mb9x/mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "fujitsu/mb9x/mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "mm32/mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "nrf5x/nrf51822", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "nrf5x/nrf52832", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "nrf5x/nrf52833", RTT_TOOL_CHAIN: "sourcery-arm"}
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10
bsp/mm32/README.md
Normal file
10
bsp/mm32/README.md
Normal file
@@ -0,0 +1,10 @@
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# MM32 BSP 说明
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MM32 系列 BSP 目前支持情况如下表所示：
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| **BSP 文件夹名称** | **开发板名称** |
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|:------------------------- |:-------------------------- |
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| **F3270 系列** | |
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| [mm32f3270-100ask-pitaya](mm32f3270-100ask-pitaya) | 百问网MM32F3273G8P火龙果开发板 |
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可以通过阅读相应 BSP 下的 README 来快速上手。
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25
bsp/mm32/libraries/HAL_Drivers/Kconfig
Normal file
25
bsp/mm32/libraries/HAL_Drivers/Kconfig
Normal file
@@ -0,0 +1,25 @@
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if BSP_USING_USBD
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config BSP_USBD_TYPE_FS
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bool
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# "USB Full Speed (FS) Core"
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config BSP_USBD_TYPE_HS
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bool
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# "USB High Speed (HS) Core"
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config BSP_USBD_SPEED_HS
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bool
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# "USB High Speed (HS) Mode"
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config BSP_USBD_SPEED_HSINFS
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bool
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# "USB High Speed (HS) Core in FS mode"
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config BSP_USBD_PHY_EMBEDDED
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bool
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# "Using Embedded phy interface"
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config BSP_USBD_PHY_UTMI
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bool
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# "UTMI: USB 2.0 Transceiver Macrocell Interace"
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config BSP_USBD_PHY_ULPI
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bool
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# "ULPI: UTMI+ Low Pin Interface"
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endif
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24
bsp/mm32/libraries/HAL_Drivers/SConscript
Normal file
24
bsp/mm32/libraries/HAL_Drivers/SConscript
Normal file
@@ -0,0 +1,24 @@
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Import('RTT_ROOT')
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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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# add the general drivers.
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src = Split("""
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""")
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if GetDepend(['RT_USING_PIN']):
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src += ['drv_gpio.c']
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if GetDepend(['RT_USING_SERIAL']):
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src += ['drv_uart.c']
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src += ['drv_common.c']
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path = [cwd]
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path += [cwd + '/config']
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group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
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Return('group')
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206
bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/dma_config.h
Normal file
206
bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/dma_config.h
Normal file
@@ -0,0 +1,206 @@
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/**
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* @file dma_config.h
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* @author 100ask development team
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* @brief
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* @version 0.1
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* @date 2022-06-16
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*
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* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
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*
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 channel1 */
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#if defined(BSP_ADC1_USING_DMA) && !defined(ADC1_DMA_INSTANCE)
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#define ADC1_DMA_INSTANCE DMA1
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#define ADC1_DMA_REQ DMA_REQ_DMA1_ADC1
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#define ADC1_DMA_IRQ DMA1_CH1_IRQn
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#define ADC1_DMA_IRQHandler DMA1_Channel1_IRQHandler
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#define ADC1_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE)
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#define UART6_DMA_INSTANCE DMA1
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#define UART6_RX_DMA_REQ DMA_REQ_DMA1_UART6_RX
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#define UART6_RX_DMA_IRQ DMA1_CH1_IRQn
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#define UART6_DMA_RX_IRQHandler DMA1_Channel1_IRQHandler
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#define UART6_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel2 */
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#if defined(BSP_ADC2_USING_DMA) && !defined(ADC2_DMA_INSTANCE)
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#define ADC2_DMA_INSTANCE DMA1
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#define ADC2_DMA_REQ DMA_REQ_DMA1_ADC2
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#define ADC2_DMA_IRQ DMA1_CH2_IRQn
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#define ADC2_DMA_IRQHandler DMA1_Channel2_IRQHandler
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#define ADC2_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_RX_DMA_INSTANCE DMA1
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#define SPI1_RX_DMA_REQ DMA_REQ_DMA1_SPI1_RX
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#define SPI1_RX_DMA_IRQ DMA1_CH2_IRQn
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#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
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#define UART3_TX_DMA_INSTANCE DMA1
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#define UART3_TX_DMA_REQ DMA_REQ_DMA1_UART3_TX
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#define UART3_TX_DMA_IRQ DMA1_CH2_IRQn
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#define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler
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#define UART3_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel3 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_TX_DMA_INSTANCE DMA1
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#define SPI1_TX_DMA_REQ DMA_REQ_DMA1_SPI1_TX
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#define SPI1_TX_DMA_IRQ DMA1_CH3_IRQn
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#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
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#define UART3_RX_DMA_INSTANCE DMA1
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#define UART3_RX_DMA_REQ DMA_REQ_DMA1_UART3_RX
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#define UART3_RX_DMA_IRQ DMA1_CH3_IRQn
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#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
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#define UART3_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel4 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_RX_DMA_INSTANCE DMA1
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#define SPI2_RX_DMA_REQ DMA_REQ_DMA1_SPI2_RX
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#define SPI2_RX_DMA_IRQ DMA1_CH4_IRQn
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#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART1_TX_DMA_INSTANCE DMA1
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#define UART1_TX_DMA_REQ DMA_REQ_DMA1_UART1_TX
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#define UART1_TX_DMA_IRQ DMA1_CH4_IRQn
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#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
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#define UART1_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel5 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_TX_DMA_INSTANCE DMA1
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#define SPI2_TX_DMA_REQ DMA_REQ_DMA1_SPI2_TX
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#define SPI2_TX_DMA_IRQ DMA1_CH5_IRQn
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#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_RX_DMA_INSTANCE DMA1
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#define UART1_RX_DMA_REQ DMA_REQ_DMA1_UART1_RX
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#define UART1_RX_DMA_IRQ DMA1_CH5_IRQn
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#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel6 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART6_RX_DMA_INSTANCE DMA1
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#define UART6_RX_DMA_REQ DMA_REQ_DMA1_UART6_RX
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#define UART6_RX_DMA_IRQ DMA1_CH6_IRQn
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#define UART6_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
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#define UART6_RX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA1 channel7 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_TX_DMA_INSTANCE DMA1
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#define UART2_TX_DMA_REQ DMA_REQ_DMA1_UART2_TX
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#define UART2_TX_DMA_IRQ DMA1_CH7_IRQn
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#define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHB1_PERIPH_DMA1
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#endif
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/* DMA2 channel1 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_RX_DMA_INSTANCE DMA2
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#define SPI3_RX_DMA_REQ DMA_REQ_DMA2_SPI3_RX
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#define SPI3_RX_DMA_IRQ DMA2_CH1_IRQn
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#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
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#define UART5_RX_DMA_INSTANCE DMA2
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#define UART5_RX_DMA_REQ DMA_REQ_DMA2_UART5_RX
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#define UART5_RX_DMA_IRQ DMA2_CH1_IRQn
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#define UART5_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define UART5_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE)
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#define UART7_RX_DMA_INSTANCE DMA2
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#define UART7_RX_DMA_REQ DMA_REQ_DMA2_UART7_RX
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#define UART7_RX_DMA_IRQ DMA2_CH1_IRQn
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#define UART7_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define UART7_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#endif
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/* DMA2 channel2 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_TX_DMA_INSTANCE DMA2
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#define SPI3_TX_DMA_REQ DMA_REQ_DMA2_SPI3_TX
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#define SPI3_TX_DMA_IRQ DMA2_CH2_IRQn
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#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
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#define UART5_TX_DMA_INSTANCE DMA2
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#define UART5_TX_DMA_REQ DMA_REQ_DMA2_UART5_TX
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#define UART5_TX_DMA_IRQ DMA2_CH2_IRQn
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#define UART5_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define UART5_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE)
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#define UART7_TX_DMA_INSTANCE DMA2
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#define UART7_TX_DMA_REQ DMA_REQ_DMA2_UART7_TX
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#define UART7_TX_DMA_IRQ DMA2_CH2_IRQn
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#define UART7_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define UART7_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#endif
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|
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/* DMA2 channel3 */
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#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
|
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#define UART4_RX_DMA_INSTANCE DMA2
|
||||
#define UART4_RX_DMA_REQ DMA_REQ_DMA2_UART4_RX
|
||||
#define UART4_RX_DMA_IRQ DMA2_CH3_IRQn
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||||
#define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
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||||
#define UART4_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
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#elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE)
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||||
#define UART8_RX_DMA_INSTANCE DMA2
|
||||
#define UART8_RX_DMA_REQ DMA_REQ_DMA2_UART8_RX
|
||||
#define UART8_RX_DMA_IRQ DMA2_CH3_IRQn
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||||
#define UART8_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
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#define UART8_RX_DMA_RCC RCC_AHB1_PERIPH_DMA2
|
||||
#endif
|
||||
|
||||
/* DMA2 channel4 */
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||||
#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE)
|
||||
#define UART6_TX_DMA_INSTANCE DMA2
|
||||
#define UART6_TX_DMA_REQ DMA_REQ_DMA2_UART6_TX
|
||||
#define UART6_TX_DMA_IRQ DMA2_CH4_IRQn
|
||||
#define UART6_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
|
||||
#define UART6_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
|
||||
#endif
|
||||
|
||||
/* DMA2 channel5 */
|
||||
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
|
||||
#define UART4_TX_DMA_INSTANCE DMA2
|
||||
#define UART4_TX_DMA_REQ DMA_REQ_DMA2_UART4_TX
|
||||
#define UART4_TX_DMA_IRQ DMA2_CH5_IRQn
|
||||
#define UART4_DMA_TX_IRQHandler DMA2_Channel5_IRQHandler
|
||||
#define UART4_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
|
||||
#elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE)
|
||||
#define UART8_TX_DMA_INSTANCE DMA2
|
||||
#define UART8_TX_DMA_REQ DMA_REQ_DMA2_UART8_TX
|
||||
#define UART8_TX_DMA_IRQ DMA2_CH5_IRQn
|
||||
#define UART8_DMA_TX_IRQHandler DMA2_Channel5_IRQHandler
|
||||
#define UART8_TX_DMA_RCC RCC_AHB1_PERIPH_DMA2
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
|
||||
124
bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/spi_config.h
Normal file
124
bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/spi_config.h
Normal file
@@ -0,0 +1,124 @@
|
||||
/**
|
||||
* @file spi_config.h
|
||||
* @author 100ask development team
|
||||
* @brief
|
||||
* @version 0.1
|
||||
* @date 2022-06-16
|
||||
*
|
||||
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_port = SPI1_TX_DMA_PORT, \
|
||||
.dma_rcc = SPI1_TX_DMA_RCC, \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI1_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI1_RX_DMA_RCC, \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI1_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
}
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_TX_DMA_RCC, \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI2_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI2_RX_DMA_RCC, \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI2_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
#ifndef SPI3_BUS_CONFIG
|
||||
#define SPI3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3, \
|
||||
.bus_name = "spi3", \
|
||||
}
|
||||
#endif /* SPI3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI3 */
|
||||
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
#ifndef SPI3_TX_DMA_CONFIG
|
||||
#define SPI3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_TX_DMA_RCC, \
|
||||
.Instance = SPI3_TX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI3_TX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
#ifndef SPI3_RX_DMA_CONFIG
|
||||
#define SPI3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.dma_rcc = SPI3_RX_DMA_RCC, \
|
||||
.Instance = SPI3_RX_DMA_INSTANCE, \
|
||||
.dma_irq = SPI3_RX_DMA_IRQ, \
|
||||
}
|
||||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
|
||||
110
bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/uart_config.h
Normal file
110
bsp/mm32/libraries/HAL_Drivers/config/mm32f3277g8p/uart_config.h
Normal file
@@ -0,0 +1,110 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, CQ 100ask Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-29 Alen first version
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = UART1, \
|
||||
.irq_type = UART1_IRQn, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = UART2, \
|
||||
.irq_type = UART2_IRQn, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = UART3, \
|
||||
.irq_type = UART3_IRQn, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = UART4, \
|
||||
.irq_type = UART4_IRQn, \
|
||||
}
|
||||
#endif /* UART4_CONFIG */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#ifndef UART5_CONFIG
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = UART5, \
|
||||
.irq_type = UART5_IRQn, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#ifndef UART6_CONFIG
|
||||
#define UART6_CONFIG \
|
||||
{ \
|
||||
.name = "uart6", \
|
||||
.Instance = UART6, \
|
||||
.irq_type = UART6_IRQn, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_USING_UART7)
|
||||
#ifndef UART7_CONFIG
|
||||
#define UART7_CONFIG \
|
||||
{ \
|
||||
.name = "uart7", \
|
||||
.Instance = UART7, \
|
||||
.irq_type = UART7_IRQn, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_USING_UART8)
|
||||
#ifndef UART8_CONFIG
|
||||
#define UART8_CONFIG \
|
||||
{ \
|
||||
.name = "uart8", \
|
||||
.Instance = UART8, \
|
||||
.irq_type = UART8_IRQn, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
167
bsp/mm32/libraries/HAL_Drivers/drv_common.c
Normal file
167
bsp/mm32/libraries/HAL_Drivers/drv_common.c
Normal file
@@ -0,0 +1,167 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, CQ 100ask Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-29 Alen first version
|
||||
*/
|
||||
|
||||
#include "drv_common.h"
|
||||
|
||||
#define DBG_TAG "drv_common"
|
||||
#define DBG_LVL DBG_INFO
|
||||
#include <rtdbg.h>
|
||||
|
||||
#ifdef RT_USING_FINSH
|
||||
#include <finsh.h>
|
||||
static void reboot(uint8_t argc, char **argv)
|
||||
{
|
||||
rt_hw_cpu_reset();
|
||||
}
|
||||
MSH_CMD_EXPORT(reboot, Reboot System);
|
||||
#endif /* RT_USING_FINSH */
|
||||
|
||||
volatile uint32_t uwTick;
|
||||
static uint32_t _systick_ms = 1;
|
||||
void HAL_IncTick(void);
|
||||
|
||||
/* SysTick configuration */
|
||||
void rt_hw_systick_init(void)
|
||||
{
|
||||
uint32_t prioritygroup = 0x00U;
|
||||
uint32_t SystemCoreClock = HAL_GetSysClockFreq();
|
||||
/* Configure the SysTick to have interrupt in 1ms time basis*/
|
||||
if(SysTick_Config(SystemCoreClock/1000) > 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
/* Configure the SysTick IRQ priority */
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, 15, 0));
|
||||
|
||||
_systick_ms = 1000u / RT_TICK_PER_SECOND;
|
||||
if(_systick_ms == 0)
|
||||
_systick_ms = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* This is the timer interrupt service routine.
|
||||
*
|
||||
*/
|
||||
void SysTick_Handler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
if(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
|
||||
HAL_IncTick();
|
||||
|
||||
rt_tick_increase();
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
|
||||
void HAL_IncTick(void)
|
||||
{
|
||||
uwTick += _systick_ms;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is executed in case of error occurrence.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void _Error_Handler(char *s, int num)
|
||||
{
|
||||
/* USER CODE BEGIN Error_Handler */
|
||||
/* User can add his own implementation to report the HAL error return state */
|
||||
LOG_E("Error_Handler at file:%s num:%d", s, num);
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
/* USER CODE END Error_Handler */
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will delay for some us.
|
||||
*
|
||||
* @param us the delay time of us
|
||||
*/
|
||||
void rt_hw_us_delay(rt_uint32_t us)
|
||||
{
|
||||
rt_uint32_t ticks;
|
||||
rt_uint32_t told, tnow, tcnt = 0;
|
||||
rt_uint32_t reload = SysTick->LOAD;
|
||||
|
||||
ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
|
||||
told = SysTick->VAL;
|
||||
while (1)
|
||||
{
|
||||
tnow = SysTick->VAL;
|
||||
if (tnow != told)
|
||||
{
|
||||
if (tnow < told)
|
||||
{
|
||||
tcnt += told - tnow;
|
||||
}
|
||||
else
|
||||
{
|
||||
tcnt += reload - tnow + told;
|
||||
}
|
||||
told = tnow;
|
||||
if (tcnt >= ticks)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* This function will initial STM32 board.
|
||||
*/
|
||||
RT_WEAK void rt_hw_board_init()
|
||||
{
|
||||
#ifdef BSP_SCB_ENABLE_I_CACHE
|
||||
/* Enable I-Cache---------------------------------------------------------*/
|
||||
SCB_EnableICache();
|
||||
#endif
|
||||
|
||||
#ifdef BSP_SCB_ENABLE_D_CACHE
|
||||
/* Enable D-Cache---------------------------------------------------------*/
|
||||
SCB_EnableDCache();
|
||||
#endif
|
||||
|
||||
/* System clock initialization */
|
||||
SystemClock_Config();
|
||||
|
||||
rt_hw_systick_init();
|
||||
|
||||
/* Heap initialization */
|
||||
#if defined(RT_USING_HEAP)
|
||||
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
|
||||
#endif
|
||||
|
||||
/* Pin driver initialization is open by default */
|
||||
#ifdef RT_USING_PIN
|
||||
rt_hw_pin_init();
|
||||
#endif
|
||||
|
||||
/* USART driver initialization is open by default */
|
||||
#ifdef RT_USING_SERIAL
|
||||
rt_hw_uart_init();
|
||||
#endif
|
||||
|
||||
/* Set the shell console output device */
|
||||
#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
#endif
|
||||
|
||||
/* Board underlying hardware initialization */
|
||||
#ifdef RT_USING_COMPONENTS_INIT
|
||||
rt_components_board_init();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
55
bsp/mm32/libraries/HAL_Drivers/drv_common.h
Normal file
55
bsp/mm32/libraries/HAL_Drivers/drv_common.h
Normal file
@@ -0,0 +1,55 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, CQ 100ask Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-29 Alen first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_COMMON_H__
|
||||
#define __DRV_COMMON_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rthw.h>
|
||||
|
||||
#include <board.h>
|
||||
|
||||
#include <hal_common.h>
|
||||
#include <hal_dma.h>
|
||||
#include <hal_rcc.h>
|
||||
|
||||
#ifdef RT_USING_PIN
|
||||
#include <hal_exti.h>
|
||||
#include <hal_syscfg.h>
|
||||
#include <hal_gpio.h>
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
#include <hal_uart.h>
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_SPI
|
||||
#include <hal_spi.h>
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_DEVICE
|
||||
#include <rtdevice.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void _Error_Handler(char *s, int num);
|
||||
|
||||
#ifndef Error_Handler
|
||||
#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
|
||||
#endif
|
||||
|
||||
#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
29
bsp/mm32/libraries/HAL_Drivers/drv_config.h
Normal file
29
bsp/mm32/libraries/HAL_Drivers/drv_config.h
Normal file
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, CQ 100ask Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-29 Alen first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(SOC_SERIES_MM32F3277)
|
||||
#include "mm32f3277g8p/dma_config.h"
|
||||
#include "mm32f3277g8p/uart_config.h"
|
||||
#include "mm32f3277g8p/spi_config.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
33
bsp/mm32/libraries/HAL_Drivers/drv_dma.h
Normal file
33
bsp/mm32/libraries/HAL_Drivers/drv_dma.h
Normal file
@@ -0,0 +1,33 @@
|
||||
/**
|
||||
* @file drv_dma.h
|
||||
* @author 100ask development team
|
||||
* @brief
|
||||
* @version 0.1
|
||||
* @date 2022-06-16
|
||||
*
|
||||
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DRV_DMA_H_
|
||||
#define __DRV_DMA_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "drv_common.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
struct dma_config {
|
||||
DMA_Type *dma_port;
|
||||
rt_uint32_t dma_req;
|
||||
IRQn_Type dma_irq;
|
||||
rt_uint32_t dma_rcc;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__DRV_DMA_H_ */
|
||||
516
bsp/mm32/libraries/HAL_Drivers/drv_gpio.c
Normal file
516
bsp/mm32/libraries/HAL_Drivers/drv_gpio.c
Normal file
File diff suppressed because it is too large
Load Diff
37
bsp/mm32/libraries/HAL_Drivers/drv_gpio.h
Normal file
37
bsp/mm32/libraries/HAL_Drivers/drv_gpio.h
Normal file
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, CQ 100ask Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-29 Alen first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_GPIO_H__
|
||||
#define __DRV_GPIO_H__
|
||||
|
||||
#include <drv_common.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define __MM32_PORT(port) GPIO##port##_BASE
|
||||
|
||||
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__MM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
|
||||
|
||||
struct pin_irq_map
|
||||
{
|
||||
rt_uint16_t pinbit;
|
||||
IRQn_Type irqno;
|
||||
rt_uint32_t extiline;
|
||||
SYSCFG_EXTILine_Type syscfg_extiline;
|
||||
};
|
||||
|
||||
int rt_hw_pin_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRV_GPIO_H__ */
|
||||
|
||||
833
bsp/mm32/libraries/HAL_Drivers/drv_spi.c
Normal file
833
bsp/mm32/libraries/HAL_Drivers/drv_spi.c
Normal file
File diff suppressed because it is too large
Load Diff
67
bsp/mm32/libraries/HAL_Drivers/drv_spi.h
Normal file
67
bsp/mm32/libraries/HAL_Drivers/drv_spi.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/**
|
||||
* @file drv_spi.h
|
||||
* @author 100ask development team
|
||||
* @brief
|
||||
* @version 0.1
|
||||
* @date 2022-06-16
|
||||
*
|
||||
* @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DRV_SPI_H_
|
||||
#define __DRV_SPI_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include "drv_common.h"
|
||||
#include "drv_dma.h"
|
||||
|
||||
rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
|
||||
|
||||
struct mm32_hw_spi_cs
|
||||
{
|
||||
GPIO_Type* GPIOx;
|
||||
uint16_t GPIO_Pin;
|
||||
};
|
||||
|
||||
struct mm32_spi_config
|
||||
{
|
||||
SPI_Type *Instance;
|
||||
char *bus_name;
|
||||
struct dma_config *dma_rx, *dma_tx;
|
||||
};
|
||||
|
||||
struct stm32_spi_device
|
||||
{
|
||||
rt_uint32_t pin;
|
||||
char *bus_name;
|
||||
char *device_name;
|
||||
};
|
||||
|
||||
#define SPI_USING_RX_DMA_FLAG (1<<0)
|
||||
#define SPI_USING_TX_DMA_FLAG (1<<1)
|
||||
|
||||
/* stm32 spi dirver class */
|
||||
struct mm32_spi
|
||||
{
|
||||
SPI_Master_Init_Type handle;
|
||||
struct mm32_spi_config *config;
|
||||
struct rt_spi_configuration *cfg;
|
||||
|
||||
struct
|
||||
{
|
||||
rt_uint16_t rx_buf_len;
|
||||
rt_uint8_t *rx_buf;
|
||||
DMA_Channel_Init_Type handle_rx;
|
||||
rt_uint16_t tx_buf_len;
|
||||
rt_uint8_t *tx_buf;
|
||||
DMA_Channel_Init_Type handle_tx;
|
||||
} dma;
|
||||
|
||||
rt_uint8_t spi_dma_flag;
|
||||
struct rt_spi_bus spi_bus;
|
||||
};
|
||||
|
||||
#endif /* __DRV_SPI_H_ */
|
||||
432
bsp/mm32/libraries/HAL_Drivers/drv_uart.c
Normal file
432
bsp/mm32/libraries/HAL_Drivers/drv_uart.c
Normal file
@@ -0,0 +1,432 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, CQ 100ask Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-29 Alen first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "drv_uart.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
#ifdef RT_USING_SERIAL
|
||||
|
||||
//#define DRV_DEBUG
|
||||
#define LOG_TAG "drv.usart"
|
||||
|
||||
#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \
|
||||
!defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \
|
||||
!defined(BSP_USING_UART7) && !defined(BSP_USING_UART8)
|
||||
#error "Please define at least one BSP_USING_UARTx"
|
||||
/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
|
||||
#endif
|
||||
|
||||
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->CSR & (__FLAG__)) == (__FLAG__))
|
||||
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->CSR = ~(__FLAG__))
|
||||
#define __HAL_UART_GET_INT_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ISR & (__FLAG__)) == (__FLAG__))
|
||||
#define __HAL_UART_CLEAR_INT_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->ICR &= (__FLAG__))
|
||||
|
||||
enum
|
||||
{
|
||||
#ifdef BSP_USING_UART1
|
||||
UART1_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART2
|
||||
UART2_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART3
|
||||
UART3_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART4
|
||||
UART4_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART5
|
||||
UART5_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART6
|
||||
UART6_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART7
|
||||
UART7_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART8
|
||||
UART8_INDEX,
|
||||
#endif
|
||||
#ifdef BSP_USING_LPUART1
|
||||
LPUART1_INDEX,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct mm32_uart_config uart_config[] =
|
||||
{
|
||||
#ifdef BSP_USING_UART1
|
||||
UART1_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART2
|
||||
UART2_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART3
|
||||
UART3_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART4
|
||||
UART4_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART5
|
||||
UART5_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART6
|
||||
UART6_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART7
|
||||
UART7_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_UART8
|
||||
UART8_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_LPUART1
|
||||
LPUART1_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct mm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
|
||||
|
||||
static rt_err_t mm32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
|
||||
{
|
||||
struct mm32_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
RT_ASSERT(cfg != RT_NULL);
|
||||
|
||||
uart = rt_container_of(serial, struct mm32_uart, serial);
|
||||
uart->handle.ClockFreqHz = HAL_Get_APB2_Clock();
|
||||
uart->handle.BaudRate = cfg->baud_rate;
|
||||
uart->handle.XferMode = UART_XferMode_RxTx;
|
||||
|
||||
switch (cfg->flowcontrol)
|
||||
{
|
||||
case RT_SERIAL_FLOWCONTROL_NONE:
|
||||
uart->handle.HwFlowControl = UART_HwFlowControl_None;
|
||||
break;
|
||||
case RT_SERIAL_FLOWCONTROL_CTSRTS:
|
||||
uart->handle.HwFlowControl = UART_HwFlowControl_RTS_CTS;
|
||||
break;
|
||||
default:
|
||||
uart->handle.HwFlowControl = UART_HwFlowControl_None;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (cfg->data_bits)
|
||||
{
|
||||
case DATA_BITS_5:
|
||||
uart->handle.WordLength = UART_WordLength_5b;
|
||||
break;
|
||||
case DATA_BITS_6:
|
||||
uart->handle.WordLength = UART_WordLength_6b;
|
||||
break;
|
||||
case DATA_BITS_7:
|
||||
uart->handle.WordLength = UART_WordLength_7b;
|
||||
break;
|
||||
case DATA_BITS_8:
|
||||
uart->handle.WordLength = UART_WordLength_8b;
|
||||
break;
|
||||
default:
|
||||
uart->handle.WordLength = UART_WordLength_8b;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (cfg->stop_bits)
|
||||
{
|
||||
case STOP_BITS_1:
|
||||
uart->handle.StopBits = UART_StopBits_1;
|
||||
break;
|
||||
case STOP_BITS_2:
|
||||
uart->handle.StopBits = UART_StopBits_2;
|
||||
break;
|
||||
default:
|
||||
uart->handle.StopBits = UART_StopBits_1;
|
||||
break;
|
||||
}
|
||||
|
||||
switch (cfg->parity)
|
||||
{
|
||||
case PARITY_NONE:
|
||||
uart->handle.Parity = UART_Parity_None;
|
||||
break;
|
||||
case PARITY_ODD:
|
||||
uart->handle.Parity = UART_Parity_Odd;
|
||||
break;
|
||||
case PARITY_EVEN:
|
||||
uart->handle.Parity = UART_Parity_Even;
|
||||
break;
|
||||
default:
|
||||
uart->handle.Parity = UART_Parity_None;
|
||||
break;
|
||||
}
|
||||
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) {
|
||||
uart->dma_rx.last_index = 0;
|
||||
}
|
||||
#endif
|
||||
extern void UART_MspInit(UART_Type *muart);
|
||||
UART_MspInit(uart->config->Instance);
|
||||
UART_Init(uart->config->Instance, &uart->handle);
|
||||
UART_Enable(uart->config->Instance, true);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
static rt_err_t mm32_control(struct rt_serial_device *serial, int cmd, void *arg)
|
||||
{
|
||||
struct mm32_uart *uart;
|
||||
rt_uint32_t prioritygroup = 0x00U;
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
|
||||
#endif
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = rt_container_of(serial, struct mm32_uart, serial);
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
/* disable interrupt */
|
||||
case RT_DEVICE_CTRL_CLR_INT:
|
||||
/* disable rx irq */
|
||||
NVIC_DisableIRQ(uart->config->irq_type);
|
||||
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
/* disable DMA */
|
||||
if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX)
|
||||
{
|
||||
|
||||
}
|
||||
else if(ctrl_arg == RT_DEVICE_FLAG_DMA_TX)
|
||||
{
|
||||
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
|
||||
/* enable interrupt */
|
||||
case RT_DEVICE_CTRL_SET_INT:
|
||||
/* enable rx irq */
|
||||
UART_EnableInterrupts(uart->config->Instance, UART_INT_RX_DONE, true);
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, 1, 0));
|
||||
NVIC_EnableIRQ(uart->config->irq_type);
|
||||
break;
|
||||
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
case RT_DEVICE_CTRL_CONFIG:
|
||||
|
||||
break;
|
||||
#endif
|
||||
|
||||
case RT_DEVICE_CTRL_CLOSE:
|
||||
|
||||
break;
|
||||
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
rt_uint32_t mm32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity)
|
||||
{
|
||||
rt_uint32_t mask;
|
||||
if (word_length == UART_WordLength_8b)
|
||||
{
|
||||
if (parity == UART_Parity_None)
|
||||
{
|
||||
mask = 0x00FFU ;
|
||||
}
|
||||
else
|
||||
{
|
||||
mask = 0x007FU ;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef UART_WORDLENGTH_7B
|
||||
else if (word_length == UART_WordLength_7b)
|
||||
{
|
||||
if (parity == UART_Parity_None)
|
||||
{
|
||||
mask = 0x007FU ;
|
||||
}
|
||||
else
|
||||
{
|
||||
mask = 0x003FU ;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
mask = 0x0000U;
|
||||
}
|
||||
#endif
|
||||
return mask;
|
||||
}
|
||||
|
||||
static int mm32_putc(struct rt_serial_device *serial, char c)
|
||||
{
|
||||
struct mm32_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
|
||||
uart = rt_container_of(serial, struct mm32_uart, serial);
|
||||
|
||||
uart->config->Instance->TDR = c;
|
||||
|
||||
while ( 0u == (UART_STATUS_TX_EMPTY & UART_GetStatus(uart->config->Instance)) )
|
||||
{}
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int mm32_getc(struct rt_serial_device *serial)
|
||||
{
|
||||
int ch;
|
||||
struct mm32_uart *uart;
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = rt_container_of(serial, struct mm32_uart, serial);
|
||||
|
||||
ch = -1;
|
||||
if ((UART_STATUS_RX_DONE & UART_GetStatus(uart->config->Instance)) != 0)
|
||||
{
|
||||
|
||||
ch = uart->config->Instance->RDR & mm32_uart_get_mask(uart->handle.WordLength, uart->handle.Parity);
|
||||
}
|
||||
return ch;
|
||||
}
|
||||
|
||||
/**
|
||||
* Uart common interrupt process. This need add to uart ISR.
|
||||
*
|
||||
* @param serial serial device
|
||||
*/
|
||||
static void uart_isr(struct rt_serial_device *serial)
|
||||
{
|
||||
struct mm32_uart *uart;
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
rt_size_t recv_total_index, recv_len;
|
||||
rt_base_t level;
|
||||
#endif
|
||||
|
||||
RT_ASSERT(serial != RT_NULL);
|
||||
uart = rt_container_of(serial, struct mm32_uart, serial);
|
||||
|
||||
/* UART in mode Receiver -------------------------------------------------*/
|
||||
if ( (0u != __HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE))
|
||||
&& (0u != __HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_RX_DONE)) )
|
||||
{
|
||||
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
|
||||
}
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
|
||||
#endif
|
||||
else
|
||||
{
|
||||
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_RX_DONE) != 0)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_RX_DONE);
|
||||
}
|
||||
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_DONE) != 0)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_DONE);
|
||||
}
|
||||
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_FULL) != 0)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_FULL);
|
||||
}
|
||||
if (__HAL_UART_GET_FLAG(uart->config->Instance, UART_STATUS_TX_EMPTY) != 0)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(uart->config->Instance, UART_STATUS_TX_EMPTY);
|
||||
}
|
||||
|
||||
if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE) != 0)
|
||||
{
|
||||
__HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_RX_DONE);
|
||||
}
|
||||
if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_TX_DONE) != 0)
|
||||
{
|
||||
__HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_TX_DONE);
|
||||
}
|
||||
if (__HAL_UART_GET_INT_FLAG(uart->config->Instance, UART_INT_TX_EMPTY) != 0)
|
||||
{
|
||||
__HAL_UART_CLEAR_INT_FLAG(uart->config->Instance, UART_INT_TX_EMPTY);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
void UART1_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART1_INDEX].serial));
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
void UART2_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART2_INDEX].serial));
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
void UART3_IRQHandler(void)
|
||||
{
|
||||
/* enter interrupt */
|
||||
rt_interrupt_enter();
|
||||
|
||||
uart_isr(&(uart_obj[UART3_INDEX].serial));
|
||||
|
||||
/* leave interrupt */
|
||||
rt_interrupt_leave();
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct rt_uart_ops mm32_uart_ops =
|
||||
{
|
||||
.configure = mm32_configure,
|
||||
.control = mm32_control,
|
||||
.putc = mm32_putc,
|
||||
.getc = mm32_getc,
|
||||
.dma_transmit = RT_NULL
|
||||
};
|
||||
|
||||
int rt_hw_uart_init(void)
|
||||
{
|
||||
rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct mm32_uart);
|
||||
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
|
||||
rt_err_t result = 0;
|
||||
|
||||
for (int i = 0; i < obj_num; i++)
|
||||
{
|
||||
/* init UART object */
|
||||
uart_obj[i].config = &uart_config[i];
|
||||
uart_obj[i].serial.ops = &mm32_uart_ops;
|
||||
uart_obj[i].serial.config = config;
|
||||
|
||||
/* register UART device */
|
||||
result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
|
||||
RT_DEVICE_FLAG_RDWR
|
||||
| RT_DEVICE_FLAG_INT_RX
|
||||
| RT_DEVICE_FLAG_INT_TX
|
||||
| uart_obj[i].uart_dma_flag
|
||||
, NULL);
|
||||
RT_ASSERT(result == RT_EOK);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
#endif /* RT_USING_SERIAL */
|
||||
51
bsp/mm32/libraries/HAL_Drivers/drv_uart.h
Normal file
51
bsp/mm32/libraries/HAL_Drivers/drv_uart.h
Normal file
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright (c) 2020-2022, CQ 100ask Development Team
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2022-05-29 Alen first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_USART_H__
|
||||
#define __DRV_USART_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "rtdevice.h"
|
||||
#include <rthw.h>
|
||||
#include <drv_common.h>
|
||||
|
||||
int rt_hw_uart_init(void);
|
||||
|
||||
#define DMA_INSTANCE_TYPE MA_Channel_TypeDef
|
||||
|
||||
#define UART_INSTANCE_CLEAR_FUNCTION __HAL_UART_CLEAR_FLAG
|
||||
|
||||
|
||||
/* stm32 config class */
|
||||
struct mm32_uart_config
|
||||
{
|
||||
const char *name;
|
||||
UART_Type *Instance;
|
||||
IRQn_Type irq_type;
|
||||
struct dma_config *dma_rx;
|
||||
struct dma_config *dma_tx;
|
||||
};
|
||||
|
||||
/* stm32 uart dirver class */
|
||||
struct mm32_uart
|
||||
{
|
||||
UART_Init_Type handle;
|
||||
struct mm32_uart_config *config;
|
||||
|
||||
#ifdef RT_SERIAL_USING_DMA
|
||||
struct
|
||||
{
|
||||
DMA_Type handle;
|
||||
rt_size_t last_index;
|
||||
} dma_rx;
|
||||
#endif
|
||||
rt_uint16_t uart_dma_flag;
|
||||
struct rt_serial_device serial;
|
||||
};
|
||||
|
||||
#endif /* __DRV_USART_H__ */
|
||||
7
bsp/mm32/libraries/Kconfig
Normal file
7
bsp/mm32/libraries/Kconfig
Normal file
@@ -0,0 +1,7 @@
|
||||
config SOC_FAMILY_MM32
|
||||
bool
|
||||
|
||||
config SOC_SERIES_MM32F3277
|
||||
bool
|
||||
select ARCH_ARM_CORTEX_M3
|
||||
select SOC_FAMILY_MM32
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __HAL_DEVICE_REGISTER_H__
|
||||
#define __HAL_DEVICE_REGISTER_H__
|
||||
|
||||
//#include "./mm32f327x/mm32_device.h"
|
||||
|
||||
#include "mm32f3277g.h"
|
||||
#include "mm32f3277g_features.h"
|
||||
#include "system_mm32f3277g.h"
|
||||
|
||||
#endif /* __HAL_DEVICE_REGISTER_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,14 @@
|
||||
/*
|
||||
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __SYSTEM_MM32F327X_H__
|
||||
#define __SYSTEM_MM32F327X_H__
|
||||
|
||||
void SystemInit(void);
|
||||
|
||||
#endif /* __SYSTEM_MM32F327X_H__ */
|
||||
@@ -0,0 +1,16 @@
|
||||
; *************************************************************
|
||||
; *** Scatter-Loading Description File generated by uVision ***
|
||||
; *************************************************************
|
||||
|
||||
LR_IROM1 0x08000000 0x00080000 { ; load region size_region
|
||||
ER_IROM1 0x08000000 0x00080000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x20000000 0x00020000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,375 @@
|
||||
; ////////////////////////////////////////////////////////////////////////////////
|
||||
; /// @file startup_mm32f327x_keil.s
|
||||
; /// @author AE TEAM
|
||||
; /// @brief THIS FILE PROVIDES ALL THE Device Startup File of MM32 Cortex-M
|
||||
; /// Core Device for ARM KEIL toolchain.
|
||||
; ////////////////////////////////////////////////////////////////////////////////
|
||||
; /// @attention
|
||||
; ///
|
||||
; /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
|
||||
; /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
|
||||
; /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
|
||||
; /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
|
||||
; /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
|
||||
; /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
|
||||
; ///
|
||||
; /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
|
||||
; //////////////////////////////////////////////////////////////////////////////
|
||||
;
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; -14 NMI Handler
|
||||
DCD HardFault_Handler ; -13 Hard Fault Handler
|
||||
DCD MemManage_Handler ; -12 MPU Fault Handler
|
||||
DCD BusFault_Handler ; -11 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; -10 Usage Fault Handler
|
||||
__vector_table_0x1c
|
||||
DCD 0 ; -9 Reserved
|
||||
DCD 0 ; -8 Reserved
|
||||
DCD 0 ; -7 Reserved
|
||||
DCD 0 ; -6 Reserved
|
||||
DCD SVC_Handler ; -5 SVCall Handler
|
||||
DCD DebugMon_Handler ; -4 Debug Monitor Handler
|
||||
DCD 0 ; -3 Reserved
|
||||
DCD PendSV_Handler ; -2 PendSV Handler
|
||||
DCD SysTick_Handler ; -1 SysTick Handler ; External Interrupts
|
||||
DCD WWDG_IRQHandler ; 0 Window Watchdog
|
||||
DCD PVD_IRQHandler ; 1 PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 2 Tamper
|
||||
DCD RTC_IRQHandler ; 3 RTC
|
||||
DCD FLASH_IRQHandler ; 4 Flash
|
||||
DCD RCC_CRS_IRQHandler ; 5 RCC
|
||||
DCD EXTI0_IRQHandler ; 6 EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 7 EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 8 EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 9 EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 10 EXTI Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; 11 DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; 12 DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; 13 DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; 14 DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; 15 DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; 16 DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; 17 DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; 18 ADC1 and ADC2
|
||||
DCD FlashCache_IRQHandler ; 19 FlashCache outage
|
||||
DCD 0 ; 20 Reserved
|
||||
DCD CAN1_RX_IRQHandler ; 21 CAN1_RX
|
||||
DCD 0 ; 22 Reserved
|
||||
DCD EXTI9_5_IRQHandler ; 23 EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; 24 TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; 25 TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; 26 TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; 27 TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; 28 TIM2
|
||||
DCD TIM3_IRQHandler ; 29 TIM3
|
||||
DCD TIM4_IRQHandler ; 30 TIM4
|
||||
DCD I2C1_IRQHandler ; 31 I2C1 Event
|
||||
DCD 0 ; 32 Reserved
|
||||
DCD I2C2_IRQHandler ; 33 I2C2 Event
|
||||
DCD 0 ; 34 Reserved
|
||||
DCD SPI1_IRQHandler ; 35 SPI1
|
||||
DCD SPI2_IRQHandler ; 36 SPI2
|
||||
DCD UART1_IRQHandler ; 37 UART1
|
||||
DCD UART2_IRQHandler ; 38 UART2
|
||||
DCD UART3_IRQHandler ; 39 UART3
|
||||
DCD EXTI15_10_IRQHandler ; 40 EXTI Line 15..10
|
||||
DCD RTCAlarm_IRQHandler ; 41 RTC Alarm through EXTI Line 17
|
||||
DCD OTG_FS_WKUP_IRQHandler ; 42 USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_IRQHandler ; 43 TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; 44 TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; 45 TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; 46 TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; 47 ADC3
|
||||
DCD 0 ; 48 Reserved
|
||||
DCD SDIO_IRQHandler ; 49 SDIO
|
||||
DCD TIM5_IRQHandler ; 50 TIM5
|
||||
DCD SPI3_IRQHandler ; 51 SPI3
|
||||
DCD UART4_IRQHandler ; 52 UART4
|
||||
DCD UART5_IRQHandler ; 53 UART5
|
||||
DCD TIM6_IRQHandler ; 54 TIM6
|
||||
DCD TIM7_IRQHandler ; 55 TIM7
|
||||
DCD DMA2_Channel1_IRQHandler ; 56 DMA2 Channel 1
|
||||
DCD DMA2_Channel2_IRQHandler ; 57 DMA2 Channel 2
|
||||
DCD DMA2_Channel3_IRQHandler ; 58 DMA2 Channel 3
|
||||
DCD DMA2_Channel4_IRQHandler ; 59 DMA2 Channel 4
|
||||
DCD DMA2_Channel5_IRQHandler ; 60 DMA2 Channel 5
|
||||
DCD ETH_IRQHandler ; 61 Ethernet
|
||||
DCD 0 ; 62 Reserved
|
||||
DCD 0 ; 63 Reserved
|
||||
DCD COMP1_2_IRQHandler ; 64 COMP1,COMP2
|
||||
DCD 0 ; 65 Reserved
|
||||
DCD 0 ; 66 Reserved
|
||||
DCD OTG_FS_IRQHandler ; 67 USB OTG_FullSpeed
|
||||
DCD 0 ; 68 Reserved
|
||||
DCD 0 ; 69 Reserved
|
||||
DCD 0 ; 70 Reserved
|
||||
DCD UART6_IRQHandler ; 71 UART6
|
||||
DCD 0 ; 72 Reserved
|
||||
DCD 0 ; 73 Reserved
|
||||
DCD 0 ; 74 Reserved
|
||||
DCD 0 ; 75 Reserved
|
||||
DCD 0 ; 76 Reserved
|
||||
DCD 0 ; 77 Reserved
|
||||
DCD 0 ; 78 Reserved
|
||||
DCD 0 ; 79 Reserved
|
||||
DCD 0 ; 80 Reserved
|
||||
DCD 0 ; 81 Reserved
|
||||
DCD UART7_IRQHandler ; 82 UART7
|
||||
DCD UART8_IRQHandler ; 83 UART8
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT RCC_CRS_IRQHandler [WEAK]
|
||||
EXPORT EXTI0_IRQHandler [WEAK]
|
||||
EXPORT EXTI1_IRQHandler [WEAK]
|
||||
EXPORT EXTI2_IRQHandler [WEAK]
|
||||
EXPORT EXTI3_IRQHandler [WEAK]
|
||||
EXPORT EXTI4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT FlashCache_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX_IRQHandler [WEAK]
|
||||
EXPORT EXTI9_5_IRQHandler [WEAK]
|
||||
EXPORT TIM1_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM1_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM1_CC_IRQHandler [WEAK]
|
||||
EXPORT TIM2_IRQHandler [WEAK]
|
||||
EXPORT TIM3_IRQHandler [WEAK]
|
||||
EXPORT TIM4_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT I2C2_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT UART3_IRQHandler [WEAK]
|
||||
EXPORT EXTI15_10_IRQHandler [WEAK]
|
||||
EXPORT RTCAlarm_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_BRK_IRQHandler [WEAK]
|
||||
EXPORT TIM8_UP_IRQHandler [WEAK]
|
||||
EXPORT TIM8_TRG_COM_IRQHandler [WEAK]
|
||||
EXPORT TIM8_CC_IRQHandler [WEAK]
|
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT TIM5_IRQHandler [WEAK]
|
||||
EXPORT SPI3_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TIM6_IRQHandler [WEAK]
|
||||
EXPORT TIM7_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel5_IRQHandler [WEAK]
|
||||
EXPORT ETH_IRQHandler [WEAK]
|
||||
EXPORT COMP1_2_IRQHandler [WEAK]
|
||||
EXPORT OTG_FS_IRQHandler [WEAK]
|
||||
EXPORT UART6_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_CRS_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
FlashCache_IRQHandler
|
||||
CAN1_RX_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTCAlarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_IRQHandler
|
||||
DMA2_Channel5_IRQHandler
|
||||
ETH_IRQHandler
|
||||
COMP1_2_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
UART6_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
||||
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: MM32F3277G
|
||||
**
|
||||
** Compiler: GNU C Compiler
|
||||
** Build: b211202
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the GNU C Compiler
|
||||
**
|
||||
** Copyright 2021 MindMotion Microelectronics Co., Ltd.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
|
||||
STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
m_interrupts (RX) : ORIGIN = 0x08000000, LENGTH = 0x00000400
|
||||
m_text (RX) : ORIGIN = 0x08000400, LENGTH = 0x0007FC00 /* 512KB. */
|
||||
m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128KB. */
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into internal flash */
|
||||
.interrupts :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} > m_interrupts
|
||||
|
||||
|
||||
/* The program code and other data goes into internal flash */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
. = ALIGN(4);
|
||||
} > m_text
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > m_text
|
||||
|
||||
.ARM :
|
||||
{
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} > m_text
|
||||
|
||||
.ctors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
from the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
__CTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.dtors :
|
||||
{
|
||||
__DTOR_LIST__ = .;
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
__DTOR_END__ = .;
|
||||
} > m_text
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} > m_text
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} > m_text
|
||||
|
||||
__etext = .; /* define a global symbol at end of code */
|
||||
__DATA_ROM = .; /* Symbol is used by startup for data initialization */
|
||||
|
||||
.data : AT(__DATA_ROM)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__DATA_RAM = .;
|
||||
__data_start__ = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
KEEP(*(.jcr*))
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .; /* define a global symbol at data end */
|
||||
} > m_data
|
||||
|
||||
__NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
|
||||
.ncache.init : AT(__NDATA_ROM)
|
||||
{
|
||||
__noncachedata_start__ = .; /* create a global symbol at ncache data start */
|
||||
*(NonCacheable.init)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
|
||||
} > m_data
|
||||
|
||||
. = __noncachedata_init_end__;
|
||||
.ncache :
|
||||
{
|
||||
*(NonCacheable)
|
||||
. = ALIGN(4);
|
||||
__noncachedata_end__ = .; /* define a global symbol at ncache data end */
|
||||
} > m_data
|
||||
|
||||
__DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
|
||||
text_end = ORIGIN(m_text) + LENGTH(m_text);
|
||||
ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
|
||||
|
||||
/* Uninitialized data section */
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss section */
|
||||
. = ALIGN(4);
|
||||
__START_BSS = .;
|
||||
__bss_start__ = .;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
__END_BSS = .;
|
||||
} > m_data
|
||||
|
||||
.heap :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
__HeapBase = .;
|
||||
. += HEAP_SIZE;
|
||||
__HeapLimit = .;
|
||||
__heap_limit = .; /* Add for _sbrk */
|
||||
} > m_data
|
||||
|
||||
.stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. += STACK_SIZE;
|
||||
} > m_data
|
||||
|
||||
/* Initializes stack on the end of block */
|
||||
__StackTop = ORIGIN(m_data) + LENGTH(m_data);
|
||||
__StackLimit = __StackTop - STACK_SIZE;
|
||||
PROVIDE(__stack = __StackTop);
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
|
||||
}
|
||||
|
||||
@@ -0,0 +1,399 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* @file: startup_MM32F3270.s */
|
||||
/* @purpose: CMSIS Cortex-M3 Core Device Startup File */
|
||||
/* */
|
||||
/* @version: 1.0 */
|
||||
/* @date: 2021-7-21 */
|
||||
/* @build: b210721 */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* */
|
||||
/* Copyright 2021 MindMotion */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*****************************************************************************/
|
||||
/* Version: GCC for ARM Embedded Processors */
|
||||
/*****************************************************************************/
|
||||
.syntax unified
|
||||
.arch armv7-m
|
||||
|
||||
.section .isr_vector, "a"
|
||||
.align 2
|
||||
.globl __isr_vector
|
||||
__isr_vector:
|
||||
.long __StackTop /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler*/
|
||||
.long HardFault_Handler /* Hard Fault Handler*/
|
||||
.long MemManage_Handler /* MPU Fault Handler*/
|
||||
.long BusFault_Handler /* Bus Fault Handler*/
|
||||
.long UsageFault_Handler /* Usage Fault Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long SVC_Handler /* SVCall Handler*/
|
||||
.long DebugMon_Handler /* Debug Monitor Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long PendSV_Handler /* PendSV Handler*/
|
||||
.long SysTick_Handler /* SysTick Handler*/
|
||||
|
||||
.long WWDG_IRQHandler /* 0 Window Watchdog */
|
||||
.long PVD_IRQHandler /* 1 PVD through EXTI Line detect */
|
||||
.long TAMPER_IRQHandler /* 2 Tamper */
|
||||
.long RTC_IRQHandler /* 3 RTC */
|
||||
.long FLASH_IRQHandler /* 4 Flash */
|
||||
.long RCC_CRS_IRQHandler /* 5 RCC */
|
||||
.long EXTI0_IRQHandler /* 6 EXTI Line 0 */
|
||||
.long EXTI1_IRQHandler /* 7 EXTI Line 1 */
|
||||
.long EXTI2_IRQHandler /* 8 EXTI Line 2 */
|
||||
.long EXTI3_IRQHandler /* 9 EXTI Line 3 */
|
||||
.long EXTI4_IRQHandler /* 10 EXTI Line 4 */
|
||||
.long DMA1_Channel1_IRQHandler /* 11 DMA1 Channel 1 */
|
||||
.long DMA1_Channel2_IRQHandler /* 12 DMA1 Channel 2 */
|
||||
.long DMA1_Channel3_IRQHandler /* 13 DMA1 Channel 3 */
|
||||
.long DMA1_Channel4_IRQHandler /* 14 DMA1 Channel 4 */
|
||||
.long DMA1_Channel5_IRQHandler /* 15 DMA1 Channel 5 */
|
||||
.long DMA1_Channel6_IRQHandler /* 16 DMA1 Channel 6 */
|
||||
.long DMA1_Channel7_IRQHandler /* 17 DMA1 Channel 7 */
|
||||
.long ADC1_2_IRQHandler /* 18 ADC1 and ADC2 */
|
||||
.long FlashCache_IRQHandler /* 19 FlashCache outage */
|
||||
.long 0 /* 20 Reserved */
|
||||
.long CAN1_RX_IRQHandler /* 21 CAN1_RX */
|
||||
.long 0 /* 22 Reserved */
|
||||
.long EXTI9_5_IRQHandler /* 23 EXTI Line 9..5 */
|
||||
.long TIM1_BRK_IRQHandler /* 24 TIM1 Break */
|
||||
.long TIM1_UP_IRQHandler /* 25 TIM1 Update */
|
||||
.long TIM1_TRG_COM_IRQHandler /* 26 TIM1 Trigger and Commutation */
|
||||
.long TIM1_CC_IRQHandler /* 27 TIM1 Capture Compare */
|
||||
.long TIM2_IRQHandler /* 28 TIM2 */
|
||||
.long TIM3_IRQHandler /* 29 TIM3 */
|
||||
.long TIM4_IRQHandler /* 30 TIM4 */
|
||||
.long I2C1_IRQHandler /* 31 I2C1 Event */
|
||||
.long 0 /* 32 Reserved */
|
||||
.long I2C2_IRQHandler /* 33 I2C2 Event */
|
||||
.long 0 /* 34 Reserved */
|
||||
.long SPI1_IRQHandler /* 35 SPI1 */
|
||||
.long SPI2_IRQHandler /* 36 SPI2 */
|
||||
.long UART1_IRQHandler /* 37 UART1 */
|
||||
.long UART2_IRQHandler /* 38 UART2 */
|
||||
.long UART3_IRQHandler /* 39 UART3 */
|
||||
.long EXTI15_10_IRQHandler /* 40 EXTI Line 15..10 */
|
||||
.long RTCAlarm_IRQHandler /* 41 RTC Alarm through EXTI Line 17 */
|
||||
.long OTG_FS_WKUP_IRQHandler /* 42 USB OTG FS Wakeup through EXTI line */
|
||||
.long TIM8_BRK_IRQHandler /* 43 TIM8 Break */
|
||||
.long TIM8_UP_IRQHandler /* 44 TIM8 Update */
|
||||
.long TIM8_TRG_COM_IRQHandler /* 45 TIM8 Trigger and Commutation */
|
||||
.long TIM8_CC_IRQHandler /* 46 TIM8 Capture Compare */
|
||||
.long ADC3_IRQHandler /* 47 ADC3 */
|
||||
.long 0 /* 48 Reserved */
|
||||
.long SDIO_IRQHandler /* 49 SDIO */
|
||||
.long TIM5_IRQHandler /* 50 TIM5 */
|
||||
.long SPI3_IRQHandler /* 51 SPI3 */
|
||||
.long UART4_IRQHandler /* 52 UART4 */
|
||||
.long UART5_IRQHandler /* 53 UART5 */
|
||||
.long TIM6_IRQHandler /* 54 TIM6 */
|
||||
.long TIM7_IRQHandler /* 55 TIM7 */
|
||||
.long DMA2_Channel1_IRQHandler /* 56 DMA2 Channel 1 */
|
||||
.long DMA2_Channel2_IRQHandler /* 57 DMA2 Channel 2 */
|
||||
.long DMA2_Channel3_IRQHandler /* 58 DMA2 Channel 3 */
|
||||
.long DMA2_Channel4_IRQHandler /* 59 DMA2 Channel 4 */
|
||||
.long DMA2_Channel5_IRQHandler /* 60 DMA2 Channel 5 */
|
||||
.long ETH_IRQHandler /* 61 Ethernet */
|
||||
.long 0 /* 62 Reserved */
|
||||
.long 0 /* 63 Reserved */
|
||||
.long COMP1_2_IRQHandler /* 64 COMP1,COMP2 */
|
||||
.long 0 /* 65 Reserved */
|
||||
.long 0 /* 66 Reserved */
|
||||
.long OTG_FS_IRQHandler /* 67 USB OTG_FullSpeed */
|
||||
.long 0 /* 68 Reserved */
|
||||
.long 0 /* 69 Reserved */
|
||||
.long 0 /* 70 Reserved */
|
||||
.long UART6_IRQHandler /* 71 UART6 */
|
||||
.long 0 /* 72 Reserved */
|
||||
.long 0 /* 73 Reserved */
|
||||
.long 0 /* 74 Reserved */
|
||||
.long 0 /* 75 Reserved */
|
||||
.long 0 /* 76 Reserved */
|
||||
.long 0 /* 77 Reserved */
|
||||
.long 0 /* 78 Reserved */
|
||||
.long 0 /* 79 Reserved */
|
||||
.long 0 /* 80 Reserved */
|
||||
.long 0 /* 81 Reserved */
|
||||
.long UART7_IRQHandler /* 82 UART7 */
|
||||
.long UART8_IRQHandler /* 83 UART8 */
|
||||
|
||||
.long DefaultISR /* 254*/
|
||||
|
||||
.size __isr_vector, . - __isr_vector
|
||||
|
||||
|
||||
|
||||
.text
|
||||
.thumb
|
||||
|
||||
/* Reset Handler */
|
||||
|
||||
.thumb_func
|
||||
.align 2
|
||||
.globl Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
cpsid i /* Mask interrupts */
|
||||
.equ VTOR, 0xE000ED08
|
||||
ldr r0, =VTOR
|
||||
ldr r1, =__isr_vector
|
||||
str r1, [r0]
|
||||
ldr r2, [r1]
|
||||
msr msp, r2
|
||||
#ifndef __NO_SYSTEM_INIT
|
||||
ldr r0,=SystemInit
|
||||
blx r0
|
||||
#endif
|
||||
/* Loop to copy data from read only memory to RAM. The ranges
|
||||
* of copy from/to are specified by following symbols evaluated in
|
||||
* linker script.
|
||||
* __etext: End of code section, i.e., begin of data sections to copy from.
|
||||
* __data_start__/__data_end__: RAM address range that data should be
|
||||
* __noncachedata_start__/__noncachedata_end__ : none cachable region
|
||||
* copied to. Both must be aligned to 4 bytes boundary. */
|
||||
|
||||
ldr r1, =__etext
|
||||
ldr r2, =__data_start__
|
||||
ldr r3, =__data_end__
|
||||
|
||||
#ifdef __PERFORMANCE_IMPLEMENTATION
|
||||
/* Here are two copies of loop implementations. First one favors performance
|
||||
* and the second one favors code size. Default uses the second one.
|
||||
* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
|
||||
subs r3, r2
|
||||
ble .LC1
|
||||
.LC0:
|
||||
subs r3, #4
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
bgt .LC0
|
||||
.LC1:
|
||||
#else /* code size implemenation */
|
||||
.LC0:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .LC0
|
||||
#endif
|
||||
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
|
||||
ldr r2, =__noncachedata_start__
|
||||
ldr r3, =__noncachedata_init_end__
|
||||
#ifdef __PERFORMANCE_IMPLEMENTATION
|
||||
/* Here are two copies of loop implementations. First one favors performance
|
||||
* and the second one favors code size. Default uses the second one.
|
||||
* Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
|
||||
subs r3, r2
|
||||
ble .LC3
|
||||
.LC2:
|
||||
subs r3, #4
|
||||
ldr r0, [r1, r3]
|
||||
str r0, [r2, r3]
|
||||
bgt .LC2
|
||||
.LC3:
|
||||
#else /* code size implemenation */
|
||||
.LC2:
|
||||
cmp r2, r3
|
||||
ittt lt
|
||||
ldrlt r0, [r1], #4
|
||||
strlt r0, [r2], #4
|
||||
blt .LC2
|
||||
#endif
|
||||
/* zero inited ncache section initialization */
|
||||
ldr r3, =__noncachedata_end__
|
||||
movs r0,0
|
||||
.LC4:
|
||||
cmp r2,r3
|
||||
itt lt
|
||||
strlt r0,[r2],#4
|
||||
blt .LC4
|
||||
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
|
||||
|
||||
#ifdef __STARTUP_CLEAR_BSS
|
||||
/* This part of work usually is done in C library startup code. Otherwise,
|
||||
* define this macro to enable it in this startup.
|
||||
*
|
||||
* Loop to zero out BSS section, which uses following symbols
|
||||
* in linker script:
|
||||
* __bss_start__: start of BSS section. Must align to 4
|
||||
* __bss_end__: end of BSS section. Must align to 4
|
||||
*/
|
||||
ldr r1, =__bss_start__
|
||||
ldr r2, =__bss_end__
|
||||
|
||||
movs r0, 0
|
||||
.LC5:
|
||||
cmp r1, r2
|
||||
itt lt
|
||||
strlt r0, [r1], #4
|
||||
blt .LC5
|
||||
#endif /* __STARTUP_CLEAR_BSS */
|
||||
|
||||
cpsie i /* Unmask interrupts */
|
||||
#ifndef __START
|
||||
#define __START _start
|
||||
#endif
|
||||
#ifndef __ATOLLIC__
|
||||
ldr r0,=__START
|
||||
blx r0
|
||||
#else
|
||||
ldr r0,=__libc_init_array
|
||||
blx r0
|
||||
ldr r0,=main
|
||||
bx r0
|
||||
#endif
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
# DefaultISR
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DefaultISR
|
||||
.type DefaultISR, %function
|
||||
DefaultISR:
|
||||
b DefaultISR
|
||||
.size DefaultISR, . - DefaultISR
|
||||
|
||||
# NMI_Handler
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
ldr r0,=NMI_Handler
|
||||
bx r0
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
# HardFault_Handler
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
ldr r0,=HardFault_Handler
|
||||
bx r0
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
# MemManage_Handler
|
||||
# BusFault_Handler
|
||||
# UsageFault_Handler
|
||||
# DebugMon_Handler
|
||||
|
||||
# SVC_Handler
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
ldr r0,=SVC_Handler
|
||||
bx r0
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
# PendSV_Handler
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
ldr r0,=PendSV_Handler
|
||||
bx r0
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
# SysTick_Handler
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
ldr r0,=SysTick_Handler
|
||||
bx r0
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, DefaultISR
|
||||
.endm
|
||||
|
||||
/* Exception Handlers */
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
|
||||
|
||||
def_irq_handler WWDG_IRQHandler /* 0 Window Watchdog */
|
||||
def_irq_handler PVD_IRQHandler /* 1 PVD through EXTI Line detect */
|
||||
def_irq_handler TAMPER_IRQHandler /* 2 Tamper */
|
||||
def_irq_handler RTC_IRQHandler /* 3 RTC */
|
||||
def_irq_handler FLASH_IRQHandler /* 4 Flash */
|
||||
def_irq_handler RCC_CRS_IRQHandler /* 5 RCC */
|
||||
def_irq_handler EXTI0_IRQHandler /* 6 EXTI Line 0 */
|
||||
def_irq_handler EXTI1_IRQHandler /* 7 EXTI Line 1 */
|
||||
def_irq_handler EXTI2_IRQHandler /* 8 EXTI Line 2 */
|
||||
def_irq_handler EXTI3_IRQHandler /* 9 EXTI Line 3 */
|
||||
def_irq_handler EXTI4_IRQHandler /* 10 EXTI Line 4 */
|
||||
def_irq_handler DMA1_Channel1_IRQHandler /* 11 DMA1 Channel 1 */
|
||||
def_irq_handler DMA1_Channel2_IRQHandler /* 12 DMA1 Channel 2 */
|
||||
def_irq_handler DMA1_Channel3_IRQHandler /* 13 DMA1 Channel 3 */
|
||||
def_irq_handler DMA1_Channel4_IRQHandler /* 14 DMA1 Channel 4 */
|
||||
def_irq_handler DMA1_Channel5_IRQHandler /* 15 DMA1 Channel 5 */
|
||||
def_irq_handler DMA1_Channel6_IRQHandler /* 16 DMA1 Channel 6 */
|
||||
def_irq_handler DMA1_Channel7_IRQHandler /* 17 DMA1 Channel 7 */
|
||||
def_irq_handler ADC1_2_IRQHandler /* 18 ADC1 and ADC2 */
|
||||
def_irq_handler FlashCache_IRQHandler /* 19 FlashCache outage */
|
||||
def_irq_handler CAN1_RX_IRQHandler /* 21 CAN1_RX */
|
||||
def_irq_handler EXTI9_5_IRQHandler /* 23 EXTI Line 9..5 */
|
||||
def_irq_handler TIM1_BRK_IRQHandler /* 24 TIM1 Break */
|
||||
def_irq_handler TIM1_UP_IRQHandler /* 25 TIM1 Update */
|
||||
def_irq_handler TIM1_TRG_COM_IRQHandler /* 26 TIM1 Trigger and Commutation */
|
||||
def_irq_handler TIM1_CC_IRQHandler /* 27 TIM1 Capture Compare */
|
||||
def_irq_handler TIM2_IRQHandler /* 28 TIM2 */
|
||||
def_irq_handler TIM3_IRQHandler /* 29 TIM3 */
|
||||
def_irq_handler TIM4_IRQHandler /* 30 TIM4 */
|
||||
def_irq_handler I2C1_IRQHandler /* 31 I2C1 Event */
|
||||
def_irq_handler I2C2_IRQHandler /* 33 I2C2 Event */
|
||||
def_irq_handler SPI1_IRQHandler /* 35 SPI1 */
|
||||
def_irq_handler SPI2_IRQHandler /* 36 SPI2 */
|
||||
def_irq_handler UART1_IRQHandler /* 37 UART1 */
|
||||
def_irq_handler UART2_IRQHandler /* 38 UART2 */
|
||||
def_irq_handler UART3_IRQHandler /* 39 UART3 */
|
||||
def_irq_handler EXTI15_10_IRQHandler /* 40 EXTI Line 15..10 */
|
||||
def_irq_handler RTCAlarm_IRQHandler /* 41 RTC Alarm through EXTI Line 17 */
|
||||
def_irq_handler OTG_FS_WKUP_IRQHandler /* 42 USB OTG FS Wakeup through EXTI line */
|
||||
def_irq_handler TIM8_BRK_IRQHandler /* 43 TIM8 Break */
|
||||
def_irq_handler TIM8_UP_IRQHandler /* 44 TIM8 Update */
|
||||
def_irq_handler TIM8_TRG_COM_IRQHandler /* 45 TIM8 Trigger and Commutation */
|
||||
def_irq_handler TIM8_CC_IRQHandler /* 46 TIM8 Capture Compare */
|
||||
def_irq_handler ADC3_IRQHandler /* 47 ADC3 */
|
||||
def_irq_handler SDIO_IRQHandler /* 49 SDIO */
|
||||
def_irq_handler TIM5_IRQHandler /* 50 TIM5 */
|
||||
def_irq_handler SPI3_IRQHandler /* 51 SPI3 */
|
||||
def_irq_handler UART4_IRQHandler /* 52 UART4 */
|
||||
def_irq_handler UART5_IRQHandler /* 53 UART5 */
|
||||
def_irq_handler TIM6_IRQHandler /* 54 TIM6 */
|
||||
def_irq_handler TIM7_IRQHandler /* 55 TIM7 */
|
||||
def_irq_handler DMA2_Channel1_IRQHandler /* 56 DMA2 Channel 1 */
|
||||
def_irq_handler DMA2_Channel2_IRQHandler /* 57 DMA2 Channel 2 */
|
||||
def_irq_handler DMA2_Channel3_IRQHandler /* 58 DMA2 Channel 3 */
|
||||
def_irq_handler DMA2_Channel4_IRQHandler /* 59 DMA2 Channel 4 */
|
||||
def_irq_handler DMA2_Channel5_IRQHandler /* 60 DMA2 Channel 5 */
|
||||
def_irq_handler ETH_IRQHandler /* 61 Ethernet */
|
||||
def_irq_handler COMP1_2_IRQHandler /* 64 COMP1,COMP2 */
|
||||
def_irq_handler OTG_FS_IRQHandler /* 67 USB OTG_FullSpeed */
|
||||
def_irq_handler UART6_IRQHandler /* 71 UART6 */
|
||||
def_irq_handler UART7_IRQHandler /* 82 UART7 */
|
||||
def_irq_handler UART8_IRQHandler /* 83 UART8 */
|
||||
|
||||
|
||||
.end
|
||||
@@ -0,0 +1,30 @@
|
||||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x800;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
@@ -0,0 +1,306 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* @file: startup_MM32F3273.s */
|
||||
/* @purpose: CMSIS Cortex-M0 Core Device Startup File */
|
||||
/* */
|
||||
/* @version: 1.0 */
|
||||
/* @date: 2021-07-21 */
|
||||
/* @build: b210721 */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* */
|
||||
/* Copyright 2021 MindMotion */
|
||||
/* All rights reserved. */
|
||||
/* */
|
||||
/* SPDX-License-Identifier: BSD-3-Clause */
|
||||
/*****************************************************************************/
|
||||
/* Version: ICC for ARM Embedded Processors */
|
||||
/*****************************************************************************/
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
PUBLIC __vector_table_0x1c
|
||||
PUBLIC __Vectors
|
||||
PUBLIC __Vectors_End
|
||||
PUBLIC __Vectors_Size
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK) ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; -14 NMI Handler
|
||||
DCD HardFault_Handler ; -13 Hard Fault Handler
|
||||
DCD MemManage_Handler ; -12 MPU Fault Handler
|
||||
DCD BusFault_Handler ; -11 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; -10 Usage Fault Handler
|
||||
__vector_table_0x1c
|
||||
DCD 0 ; -9 Reserved
|
||||
DCD 0 ; -8 Reserved
|
||||
DCD 0 ; -7 Reserved
|
||||
DCD 0 ; -6 Reserved
|
||||
DCD SVC_Handler ; -5 SVCall Handler
|
||||
DCD DebugMon_Handler ; -4 Debug Monitor Handler
|
||||
DCD 0 ; -3 Reserved
|
||||
DCD PendSV_Handler ; -2 PendSV Handler
|
||||
DCD SysTick_Handler ; -1 SysTick Handler ; External Interrupts
|
||||
DCD WWDG_IRQHandler ; 0 Window Watchdog
|
||||
DCD PVD_IRQHandler ; 1 PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; 2 Tamper
|
||||
DCD RTC_IRQHandler ; 3 RTC
|
||||
DCD FLASH_IRQHandler ; 4 Flash
|
||||
DCD RCC_CRS_IRQHandler ; 5 RCC
|
||||
DCD EXTI0_IRQHandler ; 6 EXTI Line 0
|
||||
DCD EXTI1_IRQHandler ; 7 EXTI Line 1
|
||||
DCD EXTI2_IRQHandler ; 8 EXTI Line 2
|
||||
DCD EXTI3_IRQHandler ; 9 EXTI Line 3
|
||||
DCD EXTI4_IRQHandler ; 10 EXTI Line 4
|
||||
DCD DMA1_CH1_IRQHandler ; 11 DMA1 Channel 1
|
||||
DCD DMA1_CH2_IRQHandler ; 12 DMA1 Channel 2
|
||||
DCD DMA1_CH3_IRQHandler ; 13 DMA1 Channel 3
|
||||
DCD DMA1_CH4_IRQHandler ; 14 DMA1 Channel 4
|
||||
DCD DMA1_CH5_IRQHandler ; 15 DMA1 Channel 5
|
||||
DCD DMA1_CH6_IRQHandler ; 16 DMA1 Channel 6
|
||||
DCD DMA1_CH7_IRQHandler ; 17 DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; 18 ADC1 and ADC2
|
||||
DCD FlashCache_IRQHandler ; 19 FlashCache outage
|
||||
DCD 0 ; 20 Reserved
|
||||
DCD CAN1_RX_IRQHandler ; 21 CAN1_RX
|
||||
DCD 0 ; 22 Reserved
|
||||
DCD EXTI9_5_IRQHandler ; 23 EXTI Line 9..5
|
||||
DCD TIM1_BRK_IRQHandler ; 24 TIM1 Break
|
||||
DCD TIM1_UP_IRQHandler ; 25 TIM1 Update
|
||||
DCD TIM1_TRG_COM_IRQHandler ; 26 TIM1 Trigger and Commutation
|
||||
DCD TIM1_CC_IRQHandler ; 27 TIM1 Capture Compare
|
||||
DCD TIM2_IRQHandler ; 28 TIM2
|
||||
DCD TIM3_IRQHandler ; 29 TIM3
|
||||
DCD TIM4_IRQHandler ; 30 TIM4
|
||||
DCD I2C1_IRQHandler ; 31 I2C1 Event
|
||||
DCD 0 ; 32 Reserved
|
||||
DCD I2C2_IRQHandler ; 33 I2C2 Event
|
||||
DCD 0 ; 34 Reserved
|
||||
DCD SPI1_IRQHandler ; 35 SPI1
|
||||
DCD SPI2_IRQHandler ; 36 SPI2
|
||||
DCD UART1_IRQHandler ; 37 UART1
|
||||
DCD UART2_IRQHandler ; 38 UART2
|
||||
DCD UART3_IRQHandler ; 39 UART3
|
||||
DCD EXTI15_10_IRQHandler ; 40 EXTI Line 15..10
|
||||
DCD RTCAlarm_IRQHandler ; 41 RTC Alarm through EXTI Line 17
|
||||
DCD OTG_FS_WKUP_IRQHandler ; 42 USB OTG FS Wakeup through EXTI line
|
||||
DCD TIM8_BRK_IRQHandler ; 43 TIM8 Break
|
||||
DCD TIM8_UP_IRQHandler ; 44 TIM8 Update
|
||||
DCD TIM8_TRG_COM_IRQHandler ; 45 TIM8 Trigger and Commutation
|
||||
DCD TIM8_CC_IRQHandler ; 46 TIM8 Capture Compare
|
||||
DCD ADC3_IRQHandler ; 47 ADC3
|
||||
DCD 0 ; 48 Reserved
|
||||
DCD SDIO_IRQHandler ; 49 SDIO
|
||||
DCD TIM5_IRQHandler ; 50 TIM5
|
||||
DCD SPI3_IRQHandler ; 51 SPI3
|
||||
DCD UART4_IRQHandler ; 52 UART4
|
||||
DCD UART5_IRQHandler ; 53 UART5
|
||||
DCD TIM6_IRQHandler ; 54 TIM6
|
||||
DCD TIM7_IRQHandler ; 55 TIM7
|
||||
DCD DMA2_CH1_IRQHandler ; 56 DMA2 Channel 1
|
||||
DCD DMA2_CH2_IRQHandler ; 57 DMA2 Channel 2
|
||||
DCD DMA2_CH3_IRQHandler ; 58 DMA2 Channel 3
|
||||
DCD DMA2_CH4_IRQHandler ; 59 DMA2 Channel 4
|
||||
DCD DMA2_CH5_IRQHandler ; 60 DMA2 Channel 5
|
||||
DCD 0 ; 61 Reserved
|
||||
DCD 0 ; 62 Reserved
|
||||
DCD 0 ; 63 Reserved
|
||||
DCD COMP1_2_IRQHandler ; 64 COMP1,COMP2
|
||||
DCD 0 ; 65 Reserved
|
||||
DCD 0 ; 66 Reserved
|
||||
DCD OTG_FS_IRQHandler ; 67 USB OTG_FullSpeed
|
||||
DCD 0 ; 68 Reserved
|
||||
DCD 0 ; 69 Reserved
|
||||
DCD 0 ; 70 Reserved
|
||||
DCD UART6_IRQHandler ; 71 UART6
|
||||
DCD 0 ; 72 Reserved
|
||||
DCD 0 ; 73 Reserved
|
||||
DCD 0 ; 74 Reserved
|
||||
DCD 0 ; 75 Reserved
|
||||
DCD 0 ; 76 Reserved
|
||||
DCD 0 ; 77 Reserved
|
||||
DCD 0 ; 78 Reserved
|
||||
DCD 0 ; 79 Reserved
|
||||
DCD 0 ; 80 Reserved
|
||||
DCD 0 ; 81 Reserved
|
||||
DCD UART7_IRQHandler ; 82 UART7
|
||||
DCD UART8_IRQHandler ; 83 UART8
|
||||
|
||||
|
||||
__Vectors_End
|
||||
|
||||
__Vectors EQU __vector_table
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
|
||||
THUMB
|
||||
|
||||
; Reset Handler
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
PUBWEAK HardFault_Handler
|
||||
PUBWEAK MemManage_Handler
|
||||
PUBWEAK BusFault_Handler
|
||||
PUBWEAK UsageFault_Handler
|
||||
PUBWEAK SVC_Handler
|
||||
PUBWEAK DebugMon_Handler
|
||||
PUBWEAK PendSV_Handler
|
||||
PUBWEAK SysTick_Handler
|
||||
PUBWEAK WWDG_IRQHandler
|
||||
PUBWEAK PVD_IRQHandler
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
PUBWEAK RTC_IRQHandler
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
PUBWEAK RCC_CRS_IRQHandler
|
||||
PUBWEAK EXTI0_IRQHandler
|
||||
PUBWEAK EXTI1_IRQHandler
|
||||
PUBWEAK EXTI2_IRQHandler
|
||||
PUBWEAK EXTI3_IRQHandler
|
||||
PUBWEAK EXTI4_IRQHandler
|
||||
PUBWEAK DMA1_CH1_IRQHandler
|
||||
PUBWEAK DMA1_CH2_IRQHandler
|
||||
PUBWEAK DMA1_CH3_IRQHandler
|
||||
PUBWEAK DMA1_CH4_IRQHandler
|
||||
PUBWEAK DMA1_CH5_IRQHandler
|
||||
PUBWEAK DMA1_CH6_IRQHandler
|
||||
PUBWEAK DMA1_CH7_IRQHandler
|
||||
PUBWEAK ADC1_2_IRQHandler
|
||||
PUBWEAK FlashCache_IRQHandler
|
||||
PUBWEAK CAN1_RX_IRQHandler
|
||||
PUBWEAK EXTI9_5_IRQHandler
|
||||
PUBWEAK TIM1_BRK_IRQHandler
|
||||
PUBWEAK TIM1_UP_IRQHandler
|
||||
PUBWEAK TIM1_TRG_COM_IRQHandler
|
||||
PUBWEAK TIM1_CC_IRQHandler
|
||||
PUBWEAK TIM2_IRQHandler
|
||||
PUBWEAK TIM3_IRQHandler
|
||||
PUBWEAK TIM4_IRQHandler
|
||||
PUBWEAK I2C1_IRQHandler
|
||||
PUBWEAK I2C2_IRQHandler
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
PUBWEAK SPI2_IRQHandler
|
||||
PUBWEAK UART1_IRQHandler
|
||||
PUBWEAK UART2_IRQHandler
|
||||
PUBWEAK UART3_IRQHandler
|
||||
PUBWEAK EXTI15_10_IRQHandler
|
||||
PUBWEAK RTCAlarm_IRQHandler
|
||||
PUBWEAK OTG_FS_WKUP_IRQHandler
|
||||
PUBWEAK TIM8_BRK_IRQHandler
|
||||
PUBWEAK TIM8_UP_IRQHandler
|
||||
PUBWEAK TIM8_TRG_COM_IRQHandler
|
||||
PUBWEAK TIM8_CC_IRQHandler
|
||||
PUBWEAK ADC3_IRQHandler
|
||||
PUBWEAK SDIO_IRQHandler
|
||||
PUBWEAK TIM5_IRQHandler
|
||||
PUBWEAK SPI3_IRQHandler
|
||||
PUBWEAK UART4_IRQHandler
|
||||
PUBWEAK UART5_IRQHandler
|
||||
PUBWEAK TIM6_IRQHandler
|
||||
PUBWEAK TIM7_IRQHandler
|
||||
PUBWEAK DMA2_CH1_IRQHandler
|
||||
PUBWEAK DMA2_CH2_IRQHandler
|
||||
PUBWEAK DMA2_CH3_IRQHandler
|
||||
PUBWEAK DMA2_CH4_IRQHandler
|
||||
PUBWEAK DMA2_CH5_IRQHandler
|
||||
PUBWEAK COMP1_2_IRQHandler
|
||||
PUBWEAK OTG_FS_IRQHandler
|
||||
PUBWEAK UART6_IRQHandler
|
||||
PUBWEAK UART7_IRQHandler
|
||||
PUBWEAK UART8_IRQHandler
|
||||
|
||||
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
|
||||
|
||||
NMI_Handler
|
||||
HardFault_Handler
|
||||
MemManage_Handler
|
||||
BusFault_Handler
|
||||
UsageFault_Handler
|
||||
SVC_Handler
|
||||
DebugMon_Handler
|
||||
PendSV_Handler
|
||||
SysTick_Handler
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
RCC_CRS_IRQHandler
|
||||
EXTI0_IRQHandler
|
||||
EXTI1_IRQHandler
|
||||
EXTI2_IRQHandler
|
||||
EXTI3_IRQHandler
|
||||
EXTI4_IRQHandler
|
||||
DMA1_CH1_IRQHandler
|
||||
DMA1_CH2_IRQHandler
|
||||
DMA1_CH3_IRQHandler
|
||||
DMA1_CH4_IRQHandler
|
||||
DMA1_CH5_IRQHandler
|
||||
DMA1_CH6_IRQHandler
|
||||
DMA1_CH7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
FlashCache_IRQHandler
|
||||
CAN1_RX_IRQHandler
|
||||
EXTI9_5_IRQHandler
|
||||
TIM1_BRK_IRQHandler
|
||||
TIM1_UP_IRQHandler
|
||||
TIM1_TRG_COM_IRQHandler
|
||||
TIM1_CC_IRQHandler
|
||||
TIM2_IRQHandler
|
||||
TIM3_IRQHandler
|
||||
TIM4_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
I2C2_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
UART3_IRQHandler
|
||||
EXTI15_10_IRQHandler
|
||||
RTCAlarm_IRQHandler
|
||||
OTG_FS_WKUP_IRQHandler
|
||||
TIM8_BRK_IRQHandler
|
||||
TIM8_UP_IRQHandler
|
||||
TIM8_TRG_COM_IRQHandler
|
||||
TIM8_CC_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
TIM5_IRQHandler
|
||||
SPI3_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TIM6_IRQHandler
|
||||
TIM7_IRQHandler
|
||||
DMA2_CH1_IRQHandler
|
||||
DMA2_CH2_IRQHandler
|
||||
DMA2_CH3_IRQHandler
|
||||
DMA2_CH4_IRQHandler
|
||||
DMA2_CH5_IRQHandler
|
||||
COMP1_2_IRQHandler
|
||||
OTG_FS_IRQHandler
|
||||
UART6_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
|
||||
|
||||
Default_Handler
|
||||
B .
|
||||
END
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* Copyright 2021 MindMotion Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
|
||||
#include "hal_device_registers.h"
|
||||
|
||||
void SystemInit(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
/* EOF. */
|
||||
@@ -0,0 +1,378 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
/* floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
|
||||
extern const float32_t realCoefA[8192];
|
||||
extern const float32_t realCoefB[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
|
||||
extern const q31_t realCoefAQ31[8192];
|
||||
extern const q31_t realCoefBQ31[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
|
||||
extern const q15_t realCoefAQ15[8192];
|
||||
extern const q15_t realCoefBQ15[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
|
||||
extern const float32_t Weights_128[256];
|
||||
extern const float32_t cos_factors_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
|
||||
extern const float32_t Weights_512[1024];
|
||||
extern const float32_t cos_factors_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
|
||||
extern const float32_t Weights_2048[4096];
|
||||
extern const float32_t cos_factors_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
|
||||
extern const float32_t Weights_8192[16384];
|
||||
extern const float32_t cos_factors_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
|
||||
extern const q15_t WeightsQ15_128[256];
|
||||
extern const q15_t cos_factorsQ15_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
|
||||
extern const q15_t WeightsQ15_512[1024];
|
||||
extern const q15_t cos_factorsQ15_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
|
||||
extern const q15_t WeightsQ15_2048[4096];
|
||||
extern const q15_t cos_factorsQ15_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
|
||||
extern const q15_t WeightsQ15_8192[16384];
|
||||
extern const q15_t cos_factorsQ15_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
|
||||
extern const q31_t WeightsQ31_128[256];
|
||||
extern const q31_t cos_factorsQ31_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
|
||||
extern const q31_t WeightsQ31_512[1024];
|
||||
extern const q31_t cos_factorsQ31_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
|
||||
extern const q31_t WeightsQ31_2048[4096];
|
||||
extern const q31_t cos_factorsQ31_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
|
||||
extern const q31_t WeightsQ31_8192[16384];
|
||||
extern const q31_t cos_factorsQ31_8192[8192];
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
@@ -0,0 +1,66 @@
|
||||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* $Date: 27. January 2017
|
||||
* $Revision: V.1.5.1
|
||||
*
|
||||
* Target Processor: Cortex-M cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math.h"
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#endif
|
||||
7361
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/arm_math.h
Normal file
7361
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/arm_math.h
Normal file
File diff suppressed because it is too large
Load Diff
894
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_armcc.h
Normal file
894
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_armcc.h
Normal file
File diff suppressed because it is too large
Load Diff
1444
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_armclang.h
Normal file
1444
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_armclang.h
Normal file
File diff suppressed because it is too large
Load Diff
1891
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_armclang_ltm.h
Normal file
1891
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_armclang_ltm.h
Normal file
File diff suppressed because it is too large
Load Diff
283
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_compiler.h
Normal file
283
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_compiler.h
Normal file
@@ -0,0 +1,283 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
2168
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_gcc.h
Normal file
2168
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
964
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_iccarm.h
Normal file
964
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/cmsis_iccarm.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.3
|
||||
* @date 24. June 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
2968
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_armv81mml.h
Normal file
2968
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_armv81mml.h
Normal file
File diff suppressed because it is too large
Load Diff
1921
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_armv8mbl.h
Normal file
1921
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_armv8mbl.h
Normal file
File diff suppressed because it is too large
Load Diff
2835
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_armv8mml.h
Normal file
2835
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_armv8mml.h
Normal file
File diff suppressed because it is too large
Load Diff
952
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm0.h
Normal file
952
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm0.h
Normal file
File diff suppressed because it is too large
Load Diff
1085
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm0plus.h
Normal file
1085
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm0plus.h
Normal file
File diff suppressed because it is too large
Load Diff
979
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm1.h
Normal file
979
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm1.h
Normal file
File diff suppressed because it is too large
Load Diff
1996
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm23.h
Normal file
1996
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm23.h
Normal file
File diff suppressed because it is too large
Load Diff
1937
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm3.h
Normal file
1937
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm3.h
Normal file
File diff suppressed because it is too large
Load Diff
2910
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm33.h
Normal file
2910
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm33.h
Normal file
File diff suppressed because it is too large
Load Diff
2910
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm35p.h
Normal file
2910
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm35p.h
Normal file
File diff suppressed because it is too large
Load Diff
2124
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm4.h
Normal file
2124
bsp/mm32/libraries/MM32F3270_HAL/CMSIS/Include/core_cm4.h
Normal file
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user