更正stm32/stm32f103-100ask-mini和pro的默认下载器为st-link，添加基于mm32f3270系列由百问网自主设计的火龙果开发板的bsp

2026-10-07 00:59:00 +08:00 · 2022-09-02 10:04:47 +08:00
parent cbbea1a0f5
commit 75133af2e7
133 changed files with 78635 additions and 13 deletions
@@ -86,6 +86,7 @@ jobs:
         - {RTT_BSP: "fujitsu/mb9x/mb9bf618s", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "fujitsu/mb9x/mb9bf568r", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "mini2440", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "mm32/mm32f3270-100ask-pitaya", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "nrf5x/nrf51822", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "nrf5x/nrf52832", RTT_TOOL_CHAIN: "sourcery-arm"}
         - {RTT_BSP: "nrf5x/nrf52833", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -0,0 +1,10 @@
+# MM32 BSP 说明
+
+MM32 系列 BSP 目前支持情况如下表所示：
+
+| **BSP 文件夹名称**       | **开发板名称**                 |
+|:------------------------- |:-------------------------- |
+| **F3270 系列** |  |
+| [mm32f3270-100ask-pitaya](mm32f3270-100ask-pitaya) | 百问网MM32F3273G8P火龙果开发板 |
+
+可以通过阅读相应 BSP 下的 README 来快速上手。
@@ -0,0 +1,25 @@
+if BSP_USING_USBD
+    config BSP_USBD_TYPE_FS
+        bool
+        # "USB Full Speed (FS) Core"
+    config BSP_USBD_TYPE_HS
+        bool
+        # "USB High Speed (HS) Core"
+
+    config BSP_USBD_SPEED_HS
+        bool 
+        # "USB High Speed (HS) Mode"
+    config BSP_USBD_SPEED_HSINFS
+        bool 
+        # "USB High Speed (HS) Core in FS mode"
+
+    config BSP_USBD_PHY_EMBEDDED
+        bool 
+        # "Using Embedded phy interface"
+    config BSP_USBD_PHY_UTMI
+        bool 
+        # "UTMI: USB 2.0 Transceiver Macrocell Interace"
+    config BSP_USBD_PHY_ULPI
+        bool 
+        # "ULPI: UTMI+ Low Pin Interface"
+endif
@@ -0,0 +1,24 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+        src += ['drv_uart.c']
+
+src += ['drv_common.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
@@ -0,0 +1,124 @@
+/**
+ * @file spi_config.h
+ * @author 100ask development team
+ * @brief 
+ * @version 0.1
+ * @date 2022-06-16
+ * 
+ * @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
+ * 
+ */
+
+
+#ifndef __SPI_CONFIG_H__
+#define __SPI_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_SPI1
+#ifndef SPI1_BUS_CONFIG
+#define SPI1_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI1,                           \
+        .bus_name = "spi1",                         \
+    }
+#endif /* SPI1_BUS_CONFIG */
+#endif /* BSP_USING_SPI1 */
+    
+#ifdef BSP_SPI1_TX_USING_DMA
+#ifndef SPI1_TX_DMA_CONFIG
+#define SPI1_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_port = SPI1_TX_DMA_PORT,               \
+        .dma_rcc = SPI1_TX_DMA_RCC,                 \
+        .Instance = SPI1_TX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_TX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_TX_DMA_CONFIG */
+#endif /* BSP_SPI1_TX_USING_DMA */
+
+#ifdef BSP_SPI1_RX_USING_DMA
+#ifndef SPI1_RX_DMA_CONFIG
+#define SPI1_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc = SPI1_RX_DMA_RCC,                 \
+        .Instance = SPI1_RX_DMA_INSTANCE,           \
+        .dma_irq = SPI1_RX_DMA_IRQ,                 \
+    }
+#endif /* SPI1_RX_DMA_CONFIG */
+#endif /* BSP_SPI1_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI2
+#ifndef SPI2_BUS_CONFIG
+#define SPI2_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI2,                           \
+        .bus_name = "spi2",                         \
+    }
+#endif /* SPI2_BUS_CONFIG */
+#endif /* BSP_USING_SPI2 */
+    
+#ifdef BSP_SPI2_TX_USING_DMA
+#ifndef SPI2_TX_DMA_CONFIG
+#define SPI2_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_TX_DMA_RCC,                \
+        .Instance = SPI2_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_TX_DMA_IRQ,                \
+    }
+#endif /* SPI2_TX_DMA_CONFIG */
+#endif /* BSP_SPI2_TX_USING_DMA */
+
+#ifdef BSP_SPI2_RX_USING_DMA
+#ifndef SPI2_RX_DMA_CONFIG
+#define SPI2_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI2_RX_DMA_RCC,                \
+        .Instance = SPI2_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI2_RX_DMA_IRQ,                \
+    }
+#endif /* SPI2_RX_DMA_CONFIG */
+#endif /* BSP_SPI2_RX_USING_DMA */
+
+#ifdef BSP_USING_SPI3
+#ifndef SPI3_BUS_CONFIG
+#define SPI3_BUS_CONFIG                             \
+    {                                               \
+        .Instance = SPI3,                           \
+        .bus_name = "spi3",                         \
+    }
+#endif /* SPI3_BUS_CONFIG */
+#endif /* BSP_USING_SPI3 */
+    
+#ifdef BSP_SPI3_TX_USING_DMA
+#ifndef SPI3_TX_DMA_CONFIG
+#define SPI3_TX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_TX_DMA_RCC,                \
+        .Instance = SPI3_TX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_TX_DMA_IRQ,                \
+    }
+#endif /* SPI3_TX_DMA_CONFIG */
+#endif /* BSP_SPI3_TX_USING_DMA */
+
+#ifdef BSP_SPI3_RX_USING_DMA
+#ifndef SPI3_RX_DMA_CONFIG
+#define SPI3_RX_DMA_CONFIG                          \
+    {                                               \
+        .dma_rcc  = SPI3_RX_DMA_RCC,                \
+        .Instance = SPI3_RX_DMA_INSTANCE,           \
+        .dma_irq  = SPI3_RX_DMA_IRQ,                \
+    }
+#endif /* SPI3_RX_DMA_CONFIG */
+#endif /* BSP_SPI3_RX_USING_DMA */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SPI_CONFIG_H__ */
+
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART1)
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                         \
+        .irq_type = UART1_IRQn,                                    \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                         \
+        .irq_type = UART2_IRQn,                                    \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                         \
+        .irq_type = UART3_IRQn,                                    \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#if defined(BSP_USING_UART5)
+#ifndef UART5_CONFIG
+#define UART5_CONFIG                                                \
+    {                                                               \
+        .name = "uart5",                                            \
+        .Instance = UART5,                                          \
+        .irq_type = UART5_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+    
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .Instance = UART6,                                          \
+        .irq_type = UART6_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+    
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG                                                \
+    {                                                               \
+        .name = "uart7",                                            \
+        .Instance = UART7,                                          \
+        .irq_type = UART7_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+    
+#if defined(BSP_USING_UART8)
+#ifndef UART8_CONFIG
+#define UART8_CONFIG                                                \
+    {                                                               \
+        .name = "uart8",                                            \
+        .Instance = UART8,                                          \
+        .irq_type = UART8_IRQn,                                     \
+    }
+#endif /* UART5_CONFIG */
+#endif /* BSP_USING_UART5 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#include "drv_common.h"
+
+#define DBG_TAG    "drv_common"
+#define DBG_LVL    DBG_INFO
+#include <rtdbg.h>
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+volatile uint32_t uwTick;
+static uint32_t _systick_ms = 1;
+void HAL_IncTick(void);
+
+/* SysTick configuration */
+void rt_hw_systick_init(void)
+{
+    uint32_t prioritygroup = 0x00U;
+    uint32_t SystemCoreClock = HAL_GetSysClockFreq();
+    /* Configure the SysTick to have interrupt in 1ms time basis*/
+    if(SysTick_Config(SystemCoreClock/1000) > 0)
+    {
+        return;
+    }
+    /* Configure the SysTick IRQ priority */
+    prioritygroup = NVIC_GetPriorityGrouping();
+    NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, 15, 0));
+
+    _systick_ms = 1000u / RT_TICK_PER_SECOND;
+    if(_systick_ms == 0)
+        _systick_ms = 1;
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk)
+        HAL_IncTick();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void HAL_IncTick(void)
+{
+    uwTick += _systick_ms;
+}
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void _Error_Handler(char *s, int num)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    LOG_E("Error_Handler at file:%s num:%d", s, num);
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+#ifdef BSP_SCB_ENABLE_I_CACHE
+    /* Enable I-Cache---------------------------------------------------------*/
+    SCB_EnableICache();
+#endif
+
+#ifdef BSP_SCB_ENABLE_D_CACHE
+    /* Enable D-Cache---------------------------------------------------------*/
+    SCB_EnableDCache();
+#endif
+
+    /* System clock initialization */
+    SystemClock_Config();
+    
+    rt_hw_systick_init();
+
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* Pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_COMMON_H__
+#define __DRV_COMMON_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include <board.h>
+
+#include <hal_common.h>
+#include <hal_dma.h>
+#include <hal_rcc.h>
+
+#ifdef RT_USING_PIN
+#include <hal_exti.h>
+#include <hal_syscfg.h>
+#include <hal_gpio.h>
+#endif
+
+#ifdef RT_USING_SERIAL
+#include <hal_uart.h>
+#endif
+
+#ifdef RT_USING_SPI
+#include <hal_spi.h>
+#endif
+
+#ifdef RT_USING_DEVICE
+#include <rtdevice.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _Error_Handler(char *s, int num);
+
+#ifndef Error_Handler
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#endif
+
+#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(SOC_SERIES_MM32F3277)
+#include "mm32f3277g8p/dma_config.h"
+#include "mm32f3277g8p/uart_config.h"
+#include "mm32f3277g8p/spi_config.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
@@ -0,0 +1,33 @@
+/**
+ * @file drv_dma.h
+ * @author 100ask development team
+ * @brief 
+ * @version 0.1
+ * @date 2022-06-16
+ * 
+ * @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
+ * 
+ */
+
+#ifndef __DRV_DMA_H_
+#define __DRV_DMA_H_
+
+#include <rtthread.h>
+#include "drv_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct dma_config {
+    DMA_Type *dma_port;
+    rt_uint32_t dma_req;
+    IRQn_Type dma_irq;
+    rt_uint32_t dma_rcc;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__DRV_DMA_H_ */
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __MM32_PORT(port)  GPIO##port##_BASE
+
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__MM32_PORT(PORTx) - (rt_base_t)GPIOA_BASE)/(0x0400UL) )) + PIN)
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+    rt_uint32_t extiline;
+    SYSCFG_EXTILine_Type syscfg_extiline;
+};
+
+int rt_hw_pin_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
+
@@ -0,0 +1,67 @@
+/**
+ * @file drv_spi.h
+ * @author 100ask development team
+ * @brief 
+ * @version 0.1
+ * @date 2022-06-16
+ * 
+ * @copyright Copyright (c) 2022 Chongqing 100ASK Technology Co., LTD
+ * 
+ */
+
+#ifndef __DRV_SPI_H_
+#define __DRV_SPI_H_
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include "drv_common.h"
+#include "drv_dma.h"
+
+rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, GPIO_TypeDef* cs_gpiox, uint16_t cs_gpio_pin);
+
+struct mm32_hw_spi_cs
+{
+    GPIO_Type* GPIOx;
+    uint16_t GPIO_Pin;
+};
+
+struct mm32_spi_config
+{
+    SPI_Type *Instance;
+    char *bus_name;
+    struct dma_config *dma_rx, *dma_tx;
+};
+
+struct stm32_spi_device
+{
+    rt_uint32_t pin;
+    char *bus_name;
+    char *device_name;
+};
+
+#define SPI_USING_RX_DMA_FLAG   (1<<0)
+#define SPI_USING_TX_DMA_FLAG   (1<<1)
+
+/* stm32 spi dirver class */
+struct mm32_spi
+{
+    SPI_Master_Init_Type handle;
+    struct mm32_spi_config *config;
+    struct rt_spi_configuration *cfg;
+
+    struct
+    {
+        rt_uint16_t rx_buf_len;
+        rt_uint8_t *rx_buf;
+        DMA_Channel_Init_Type handle_rx;
+        rt_uint16_t tx_buf_len;
+        rt_uint8_t *tx_buf;
+        DMA_Channel_Init_Type handle_tx;
+    } dma;
+    
+    rt_uint8_t spi_dma_flag;
+    struct rt_spi_bus spi_bus;
+};
+
+#endif /* __DRV_SPI_H_ */
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020-2022, CQ 100ask Development Team
+ *
+ * Change Logs:
+ *   Date           Author          Notes
+ * 2022-05-29        Alen       first version
+ */
+
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+int rt_hw_uart_init(void);
+
+#define DMA_INSTANCE_TYPE               MA_Channel_TypeDef
+
+#define UART_INSTANCE_CLEAR_FUNCTION    __HAL_UART_CLEAR_FLAG
+
+
+/* stm32 config class */
+struct mm32_uart_config
+{
+    const char *name;
+    UART_Type *Instance;
+    IRQn_Type irq_type;
+    struct dma_config *dma_rx;
+    struct dma_config *dma_tx;
+};
+
+/* stm32 uart dirver class */
+struct mm32_uart
+{
+    UART_Init_Type handle;
+    struct mm32_uart_config *config;
+
+#ifdef RT_SERIAL_USING_DMA
+    struct
+    {
+        DMA_Type handle;
+        rt_size_t last_index;
+    } dma_rx;
+#endif
+    rt_uint16_t uart_dma_flag;
+    struct rt_serial_device serial;
+};
+
+#endif  /* __DRV_USART_H__ */
@@ -0,0 +1,7 @@
+config SOC_FAMILY_MM32
+    bool
+
+config SOC_SERIES_MM32F3277
+    bool
+    select ARCH_ARM_CORTEX_M3
+    select SOC_FAMILY_MM32
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef __HAL_DEVICE_REGISTER_H__
+#define __HAL_DEVICE_REGISTER_H__
+
+//#include "./mm32f327x/mm32_device.h"
+
+#include "mm32f3277g.h"
+#include "mm32f3277g_features.h"
+#include "system_mm32f3277g.h"
+
+#endif /* __HAL_DEVICE_REGISTER_H__ */
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef __SYSTEM_MM32F327X_H__
+#define __SYSTEM_MM32F327X_H__
+
+void SystemInit(void);
+
+#endif /* __SYSTEM_MM32F327X_H__ */
@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x08000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x08000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00020000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+
@@ -0,0 +1,30 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2001FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__   = 0x800;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#include "hal_device_registers.h"
+
+void SystemInit(void)
+{
+
+}
+
+/* EOF. */
@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.3
+ * @date     24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
@@ -0,0 +1,74 @@
+/**************************************************************************//**
+ * @file     cmsis_xcc.h
+ * @brief    CMSIS DSP Core Peripheral Access Layer Header File
+ * @version  V1.0
+ * @date     20. January 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CORE_DSP_H_GENERIC
+#define __CORE_DSP_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+#define __STATIC_INLINE static inline
+
+#define __BKPT(value) do {} while(0)
+#define __NOP() do {} while(0)
+
+#define NVIC_SetPriorityGrouping(value) do {} while(0)
+#define NVIC_GetPriorityGrouping() do {} while(0)
+#define NVIC_EnableIRQ(value) do {} while(0)
+#define NVIC_GetEnableIRQ(value) do {} while(0)
+#define NVIC_DisableIRQ(value) do {} while(0)
+#define NVIC_GetPendingIRQ(value) do {} while(0)
+#define NVIC_SetPendingIRQ(value) do {} while(0)
+#define NVIC_ClearPendingIRQ(value) do {} while(0)
+#define NVIC_GetActive(value) do {} while(0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_DSP_H_GENERIC */
@@ -0,0 +1,70 @@
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __HAL_COMMON_H__
+#define __HAL_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include "hal_device_registers.h"
+
+#endif /* __HAL_COMMON_H__ */
+
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_DMA_H__
+#define __HAL_DMA_H__
+
+#include "hal_common.h"
+
+/*!
+ * @addtogroup DMA
+ * @{
+ */
+
+/*!
+ * @addtogroup DMA_CHANNEL_INT
+ * @{
+ */
+#define DMA_CHN_INT_XFER_GLOBAL      (0x1u << 0u) /*!< DMA global interrupt channel. */
+#define DMA_CHN_INT_XFER_DONE        (0x1u << 1u) /*!< DMA end of transfer interrupt channel. */
+#define DMA_CHN_INT_XFER_HALF_DONE   (0x1u << 2u) /*!< DMA half transfer interrupt channel. */
+#define DMA_CHN_INT_XFER_ERR         (0x1u << 3u) /*!< DMA transfer error interrupt channel. */
+/*!
+ * @}
+ */
+
+
+/*!
+ * @brief Define the enum type of DMA_XferMode_Type.
+ */
+typedef enum
+{
+    DMA_XferMode_PeriphToMemory = 0u,      /*!< memory to memory mode, from periph addr to memory addr. */
+    DMA_XferMode_MemoryToPeriph = 1u,      /*!< memory to memory mode, from periph addr to memory addr. */
+    DMA_XferMode_PeriphToMemoryBurst = 2u, /*!< memory to memory mode, from periph addr to memory addr. */
+    DMA_XferMode_MemoryToPeriphBurst = 3u, /*!< memory to memory mode, from memory addr to periph addr. */
+} DMA_XferMode_Type;
+
+/*!
+ * @brief Define the enum type of DMA_ReloadMode_Type.
+ */
+typedef enum
+{
+    DMA_ReloadMode_OneTime    = 0u, /*!< the count is exhausted after the xfer is done.  */
+    DMA_ReloadMode_AutoReload = 1u, /*!< auto reload the count for the new xfer. */
+    DMA_ReloadMode_AutoReloadContinuous = 2u, /*!< auto reload the count for the next xfer, and always run. */
+} DMA_ReloadMode_Type;
+
+/*!
+ * @brief Incremental mode of peripherals and memories.
+ */
+typedef enum
+{
+    DMA_AddrIncMode_StayAfterXfer = 0u, /*!< Peripheral access address accumulation. */
+    DMA_AddrIncMode_IncAfterXfer  = 1u, /*!< Memory access address accumulation. */
+} DMA_AddrIncMode_Type;
+
+/*!
+ * @brief Define the enum type of DMA xfer width type.
+ */
+typedef enum
+{
+    DMA_XferWidth_8b  = 0u, /*!< Xfer width 8 bits. */
+    DMA_XferWidth_16b = 1u, /*!< Xfer width 16 bits. */
+    DMA_XferWidth_32b = 2u, /*!< Xfer width 32 bits. */
+} DMA_XferWidth_Type;
+
+/*!
+ * @brief Configure DMA Priority.
+ */
+typedef enum
+{
+    DMA_Priority_Low     = 0u, /*!< Low Priority. */
+    DMA_Priority_Middle  = 1u, /*!< Middle Priority. */
+    DMA_Priority_High    = 2u, /*!< High Priority. */
+    DMA_Priority_Highest = 3u, /*!< Highest Priority. */
+} DMA_Priority_Type;
+
+/*!
+ * @brief This type of structure instance is used to keep the settings when calling the @ref DMA_InitChannel() to initialize the DMA module.
+ */
+typedef struct
+{
+    DMA_XferMode_Type     XferMode;             /*!< Specify whether the Receive or Transmit mode is enabled or not. */
+    DMA_ReloadMode_Type   ReloadMode;           /*!< Specify whether to automatically reload the next transfer count when the count is exhausted. */
+    DMA_AddrIncMode_Type  PeriphAddrIncMode;    /*!< Specify peripheral Address Inc Mode. */
+    DMA_AddrIncMode_Type  MemAddrIncMode;       /*!< Specify Memory Address Inc Mode. */
+    DMA_XferWidth_Type    XferWidth;            /*!< Specify the transmission data width. */
+    DMA_Priority_Type     Priority;             /*!< Specify priority mode. */
+    uint32_t              XferCount;            /*!< Specify CircularMode's count. */
+    uint32_t              MemAddr;              /*!< Specify Memory Address. */
+    uint32_t              PeriphAddr;           /*!< Specify Periph Address. */
+} DMA_Channel_Init_Type;
+
+/*!
+ * @brief Initialize the DMA module.
+ *
+ * @param DMAx DMA instance.
+ * @param channel Channel corresponding to DMA controller.
+ * @param init  Pointer to the initialization structure. See to @ref DMA_Channel_Init_Type.
+ * @return None.
+ */
+uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init);
+
+/*!
+ * @brief enable the DMA channel interrupts of the DMA module.
+ *
+ * @param DMAx DMA instance.
+ * @param channel Channel corresponding to DMA controller.
+ * @param interrupts Interrupt code masks. See to @ref DMA_CHANNEL_INT.
+ * @param enable 'true' to enable the DMA channel interrupts, 'false' to disable the DMA channel interrupts.
+ * @return None.
+ */
+void     DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable);
+
+/*!
+ * @brief Get the channel interrupts status flags of the DMA module.
+ *
+ * @param DMAx DMA instance.
+ * @param channel Channel corresponding to DMA controller in DMA. See to @ref DMA_CHANNEL_INT.
+ * @return Interrupt status flags.
+ */
+uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel);
+
+/*!
+ * @brief Clear the channel interrupts status flags of the DMA module.
+ *
+ * @param DMAx DMA instance.
+ * @param channel Channel corresponding to DMA controller. See to @ref DMA_CHANNEL_INT.
+ * @param interrupts Interrupt code masks.
+ * @return None.
+ */
+void     DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts);
+
+/*!
+ * @brief Enable the channel of the DMA module.
+ *
+ * @param DMAx DMA instance.
+ * @param channel Channel corresponding to DMA controller. See to @ref DMA_CHANNEL_INT.
+ * @param enable 'true' to enable the DMA controller sends a reply signal to the peripheral, 'false' to disable the DMA controller sends a reply signal to the peripheral.
+ * @return None.
+ */
+void     DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable);
+
+/*!
+ *@}
+ */
+
+#endif /* __HAL_DMA_H__ */
+
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef __HAL_DMA_REQUESET_H__
+#define __HAL_DMA_REQUESET_H__
+
+#if 0
+
+#define DMA_REQ_GET_DMA_INSTANCE(code) (uint32_t)((code) >> 8u)
+#define DMA_REQ_GET_DMA_CHANNEL(code)  (uint32_t)((code) & 0xFF)
+#define DMA_REQ_DMA_INSTANCE(dmax)     (uint32_t)((dmax) << 8u)
+#define DMA_REQ_DMA_CHANNEL(channel)   (uint32_t)((channel) & 0xFF)
+
+
+#define DMA_REQ_DMA1_ADC1        0u
+#define DMA_REQ_DMA1_UART6_RX    0u
+#define DMA_REQ_DMA1_TIM2_CC3    0u
+#define DMA_REQ_DMA1_TIM4_CC1    0u
+#define DMA_REQ_DMA1_ADC2        1u
+#define DMA_REQ_DMA1_SPI1_RX     1u
+#define DMA_REQ_DMA1_UART3_TX    1u
+#define DMA_REQ_DMA1_TIM1_CC1    1u
+#define DMA_REQ_DMA1_TIM2_UP     1u
+#define DMA_REQ_DMA1_TIM3_CC3    1u
+#define DMA_REQ_DMA1_SPI1_TX     2u
+#define DMA_REQ_DMA1_UART3_RX    2u
+#define DMA_REQ_DMA1_TIM1_CC2    2u
+#define DMA_REQ_DMA1_TIM3_CC4    2u
+#define DMA_REQ_DMA1_TIM2_UP     2u
+#define DMA_REQ_DMA1_SPI2_RX     3u
+#define DMA_REQ_DMA1_UART1_TX    3u
+#define DMA_REQ_DMA1_I2C2_TX     3u
+#define DMA_REQ_DMA1_TIM1_CC4    3u
+#define DMA_REQ_DMA1_TIM1_TRIG   3u
+#define DMA_REQ_DMA1_TIM1_COM    3u
+#define DMA_REQ_DMA1_TIM4_CC2    3u
+#define DMA_REQ_DMA1_SPI2_TX     4u
+#define DMA_REQ_DMA1_UART1_RX    4u
+#define DMA_REQ_DMA1_I2C2_RX     4u
+#define DMA_REQ_DMA1_TIM1_UP     4u
+#define DMA_REQ_DMA1_TIM2_CC1    4u
+#define DMA_REQ_DMA1_TIM4_CC3    4u
+#define DMA_REQ_DMA1_UART2_RX    5u
+#define DMA_REQ_DMA1_I2C1_TX     5u
+#define DMA_REQ_DMA1_TIM1_CC3    5u
+#define DMA_REQ_DMA1_TIM3_CC1    5u
+#define DMA_REQ_DMA1_TIM3_TRIG   5u
+#define DMA_REQ_DMA1_UART2_TX    6u
+#define DMA_REQ_DMA1_I2C1_RX     6u
+#define DMA_REQ_DMA1_TIM2_CC2    6u
+#define DMA_REQ_DMA1_TIM2_CC4    6u
+#define DMA_REQ_DMA1_TIM4_UP     6u
+
+#define DMA_REQ_DMA2_SPI3_RX     0u
+#define DMA_REQ_DMA2_UART5_RX    0u
+#define DMA_REQ_DMA2_UART7_RX    0u
+#define DMA_REQ_DMA2_TIM5_CC4    0u
+#define DMA_REQ_DMA2_TIM5_TRIG   0u
+#define DMA_REQ_DMA2_TIM8_CC3    0u
+#define DMA_REQ_DMA2_TIM8_UP     0u
+#define DMA_REQ_DMA2_SPI3_TX     1u
+#define DMA_REQ_DMA2_UART5_TX    1u
+#define DMA_REQ_DMA2_UART7_TX    1u
+#define DMA_REQ_DMA2_TIM5_CC3    1u
+#define DMA_REQ_DMA2_TIM5_UP     1u
+#define DMA_REQ_DMA2_TIM8_CC4    1u
+#define DMA_REQ_DMA2_TIM8_TRIG   1u
+#define DMA_REQ_DMA2_TIM8_COM    1u
+#define DMA_REQ_DMA2_UART4_RX    2u
+#define DMA_REQ_DMA2_UART8_RX    2u
+#define DMA_REQ_DMA2_TIM6_UP     2u
+#define DMA_REQ_DMA2_DAC_CH1     2u
+#define DMA_REQ_DMA2_TIM8_CC1    2u
+#define DMA_REQ_DMA2_UART6_TX    3u
+#define DMA_REQ_DMA2_SDIO        3u
+#define DMA_REQ_DMA2_TIM5_CC2    3u
+#define DMA_REQ_DMA2_TIM6_UP     3u
+#define DMA_REQ_DMA2_DAC_CH2     3u
+#define DMA_REQ_DMA2_ADC3        4u
+#define DMA_REQ_DMA2_UART4_TX    4u
+#define DMA_REQ_DMA2_UART8_TX    4u
+#define DMA_REQ_DMA2_TIM5_CC1    4u
+#define DMA_REQ_DMA2_TIM8_CC2    4u
+#endif
+
+/* ADC. */
+#define DMA_REQ_DMA1_ADC1        0u
+#define DMA_REQ_DMA1_ADC2        1u
+#define DMA_REQ_DMA2_ADC3        4u
+
+/* DAC. */
+#define DMA_REQ_DMA2_DAC_CH1     2u
+#define DMA_REQ_DMA2_DAC_CH2     3u
+
+/* UART. */
+#define DMA_REQ_DMA1_UART1_TX    3u
+#define DMA_REQ_DMA1_UART1_RX    4u
+#define DMA_REQ_DMA1_UART2_RX    5u
+#define DMA_REQ_DMA1_UART2_TX    6u
+#define DMA_REQ_DMA1_UART3_RX    2u
+#define DMA_REQ_DMA1_UART3_TX    1u
+#define DMA_REQ_DMA2_UART4_RX    2u
+#define DMA_REQ_DMA2_UART4_TX    4u
+#define DMA_REQ_DMA2_UART5_RX    0u
+#define DMA_REQ_DMA2_UART5_TX    1u
+#define DMA_REQ_DMA1_UART6_RX    0u
+#define DMA_REQ_DMA2_UART6_TX    3u
+#define DMA_REQ_DMA2_UART7_RX    0u
+#define DMA_REQ_DMA2_UART7_TX    1u
+#define DMA_REQ_DMA2_UART8_RX    2u
+#define DMA_REQ_DMA2_UART8_TX    4u
+
+/* SPI. */
+#define DMA_REQ_DMA1_SPI1_RX     1u
+#define DMA_REQ_DMA1_SPI1_TX     2u
+#define DMA_REQ_DMA1_SPI2_RX     3u
+#define DMA_REQ_DMA1_SPI2_TX     4u
+#define DMA_REQ_DMA2_SPI3_RX     0u
+#define DMA_REQ_DMA2_SPI3_TX     1u
+
+/* I2C. */
+#define DMA_REQ_DMA1_I2C1_RX     6u
+#define DMA_REQ_DMA1_I2C1_TX     5u
+#define DMA_REQ_DMA1_I2C2_RX     4u
+#define DMA_REQ_DMA1_I2C2_TX     3u
+
+/* TIM1. */
+#define DMA_REQ_DMA1_TIM1_CC1    1u
+#define DMA_REQ_DMA1_TIM1_CC2    2u
+#define DMA_REQ_DMA1_TIM1_CC3    5u
+#define DMA_REQ_DMA1_TIM1_CC4    3u
+#define DMA_REQ_DMA1_TIM1_TRIG   3u
+#define DMA_REQ_DMA1_TIM1_COM    3u
+#define DMA_REQ_DMA1_TIM1_UP     4u
+
+/* TIM2. */
+#define DMA_REQ_DMA1_TIM2_CC1    4u
+#define DMA_REQ_DMA1_TIM2_CC2    6u
+#define DMA_REQ_DMA1_TIM2_CC3    0u
+#define DMA_REQ_DMA1_TIM2_CC4    6u
+#define DMA_REQ_DMA1_TIM2_UP     1u
+
+/* TIM3. */
+#define DMA_REQ_DMA1_TIM3_CC1    5u
+#define DMA_REQ_DMA1_TIM3_CC3    1u
+#define DMA_REQ_DMA1_TIM3_CC4    2u
+#define DMA_REQ_DMA1_TIM3_UP     2u
+#define DMA_REQ_DMA1_TIM3_TRIG   5u
+
+/* TIM4. */
+#define DMA_REQ_DMA1_TIM4_CC1    0u
+#define DMA_REQ_DMA1_TIM4_CC2    3u
+#define DMA_REQ_DMA1_TIM4_CC3    4u
+#define DMA_REQ_DMA1_TIM4_UP     6u
+
+/* TIM5. */
+#define DMA_REQ_DMA2_TIM5_CC1    4u
+#define DMA_REQ_DMA2_TIM5_CC2    3u
+#define DMA_REQ_DMA2_TIM5_CC3    1u
+#define DMA_REQ_DMA2_TIM5_CC4    0u
+#define DMA_REQ_DMA2_TIM5_TRIG   0u
+#define DMA_REQ_DMA2_TIM5_UP     1u
+
+/* TIM6. */
+#define DMA_REQ_DMA2_TIM6_UP     2u
+
+/* TIM7. */
+#define DMA_REQ_DMA2_TIM7_UP     3u /* DMA_REQ_DMA2_TIM7_UP */
+
+/* TIM8. */
+#define DMA_REQ_DMA2_TIM8_CC1    2u
+#define DMA_REQ_DMA2_TIM8_CC2    4u
+#define DMA_REQ_DMA2_TIM8_CC3    0u
+#define DMA_REQ_DMA2_TIM8_CC4    1u
+#define DMA_REQ_DMA2_TIM8_UP     0u
+#define DMA_REQ_DMA2_TIM8_COM    1u
+#define DMA_REQ_DMA2_TIM8_TRIG   1u
+
+/* SDIO. */
+#define DMA_REQ_DMA2_SDIO        3u
+
+#endif /* __HAL_DMA_REQUESET_H__ */
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_EXTI_H__
+#define __HAL_EXTI_H__
+
+#include "hal_common.h"
+
+/*!
+ * @addtogroup EXTI
+ * @{
+ */
+
+/*!
+ * @brief EXTI driver version number.
+ */
+#define EXTI_DRIVER_VERSION 0u /*!< exti_0. */
+
+/*!
+ * @addtogroup EXTI_LINE
+ * @{
+ */
+#define EXTI_LINE_0  (1u << 0u)   /*!<External Interrupt Line 0  switcher. */
+#define EXTI_LINE_1  (1u << 1u)   /*!<External Interrupt Line 1  switcher. */
+#define EXTI_LINE_2  (1u << 2u)   /*!<External Interrupt Line 2  switcher. */
+#define EXTI_LINE_3  (1u << 3u)   /*!<External Interrupt Line 3  switcher. */
+#define EXTI_LINE_4  (1u << 4u)   /*!<External Interrupt Line 4  switcher. */
+#define EXTI_LINE_5  (1u << 5u)   /*!<External Interrupt Line 5  switcher. */
+#define EXTI_LINE_6  (1u << 6u)   /*!<External Interrupt Line 6  switcher. */
+#define EXTI_LINE_7  (1u << 7u)   /*!<External Interrupt Line 7  switcher. */
+#define EXTI_LINE_8  (1u << 8u)   /*!<External Interrupt Line 8  switcher. */
+#define EXTI_LINE_9  (1u << 9u)   /*!<External Interrupt Line 9  switcher. */
+#define EXTI_LINE_10 (1u << 10u)  /*!<External Interrupt Line 10 switcher. */
+#define EXTI_LINE_11 (1u << 11u)  /*!<External Interrupt Line 11 switcher. */
+#define EXTI_LINE_12 (1u << 12u)  /*!<External Interrupt Line 12 switcher. */
+#define EXTI_LINE_13 (1u << 13u)  /*!<External Interrupt Line 13 switcher. */
+#define EXTI_LINE_14 (1u << 14u)  /*!<External Interrupt Line 14 switcher. */
+#define EXTI_LINE_15 (1u << 15u)  /*!<External Interrupt Line 15 switcher. */
+#define EXTI_LINE_16 (1u << 16u)  /*!<External Interrupt Line 16 switcher. */
+#define EXTI_LINE_17 (1u << 17u)  /*!<External Interrupt Line 17 switcher. */
+#define EXTI_LINE_18 (1u << 18u)  /*!<External Interrupt Line 18 switcher. */
+#define EXTI_LINE_19 (1u << 19u)  /*!<External Interrupt Line 19 switcher. */
+#define EXTI_LINE_20 (1u << 20u)  /*!<External Interrupt Line 20 switcher. */
+#define EXTI_LINE_21 (1u << 21u)  /*!<External Interrupt Line 21 switcher. */
+#define EXTI_LINE_22 (1u << 22u)  /*!<External Interrupt Line 22 switcher. */
+#define EXTI_LINE_23 (1u << 23u)  /*!<External Interrupt Line 23 switcher. */
+#define EXTI_LINE_24 (1u << 24u)  /*!<External Interrupt Line 24 switcher. */
+/*!
+ * @}
+ */
+
+/*!
+ * @brief EXTI trigger input detection edge alt.
+ */
+typedef enum
+{
+    EXTI_TriggerIn_Disable     = 0u, /*!< Disable the trigger input interrupt. */
+    EXTI_TriggerIn_RisingEdge  = 1u, /*!< Trigger input rising edge interrupt.*/
+    EXTI_TriggerIn_FallingEdge = 2u, /*!< Trigger input falling edge interrupt.*/
+    EXTI_TriggerIn_BothEdges   = 3u, /*!< Both trigger input rising and falling edge interrupt.*/
+} EXTI_TriggerIn_Type;
+
+/*!
+ * @brief Enable the external interrupt line's interrupts.
+ *
+ * @param EXTIx EXTI instance.
+ * @param lines External interrupt lines. See to @ref EXTI_LINE.
+ * @param enable 'true' to unmask the external interrupt lines' interrupt, 'false' to mask the external interrupt lines' interrupt.
+ * @return None.
+ */
+void EXTI_EnableLineInterrupt(EXTI_Type * EXTIx, uint32_t lines, bool enable);
+
+/*!
+ * @brief Enable the external interrupt line's events.
+ *
+ * @param EXTIx EXTI instance.
+ * @param lines External interrupt lines. See to @ref EXTI_LINE.
+ * @param enable 'true' to unmask the external interrupt lines' event, 'false' to disable the external interrupt lines' event.
+ * @return None.
+ */
+void EXTI_EnableLineEvent(EXTI_Type * EXTIx, uint32_t lines, bool enable);
+
+/*!
+ * @brief Set the line input for triggering interrupts.
+ *
+ * @param EXTIx EXTI instance.
+ * @param lines External interrupt lines. See to @ref EXTI_LINE.
+ * @param trgin The active signal for triggering interrupts. See to @ref EXTI_TriggerIn_Type;
+ * @return None.
+ */
+void EXTI_SetTriggerIn(EXTI_Type * EXTIx, uint32_t lines, EXTI_TriggerIn_Type trgin);
+
+/*!
+ * @brief Do software trigger to trigger interrupts of the indicated lines.
+ *
+ * @param EXTIx EXTI instance.
+ * @param lines External interrupt lines. See to @ref EXTI_LINE.
+ * @return None.
+ */
+void EXTI_DoSwTrigger(EXTI_Type * EXTIx, uint32_t lines);
+
+/*!
+ * @brief Get the interrupt status of the indicated EXTI module.
+ *
+ * @param EXTIx EXTI instance.
+ * @return Line status flags. See to @ref EXTI_LINE.
+ */
+uint32_t EXTI_GetLineStatus(EXTI_Type * EXTIx);
+
+/*!
+ * @brief Clear the interrupt status of the indicated EXTI module.
+ *
+ * @param EXTIx EXTI instance.
+ * @param lines Interrupt status flags. See to @ref EXTI_LINE.
+ * @return None.
+ */
+void EXTI_ClearLineStatus(EXTI_Type * EXTIx, uint32_t lines);
+
+/*!
+ * @}
+ */
+
+#endif /* __HAL_EXTI_H__ */
+
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_IWDG_H__
+#define __HAL_IWDG_H__
+
+#include "hal_common.h"
+
+/*!
+ * @addtogroup IWDG
+ * @{
+ */
+
+/*!
+ * @brief IWDG driver version number.
+ */
+#define IWDG_DRIVER_VERSION 0u /*!< IWDG_0. */
+
+/*!
+ * @brief IWDG key values
+ */
+#define IWDG_KEY_ENABLE  0xCCCC /*!< IWDG Peripheral Enable . */
+#define IWDG_KEY_RELOAD  0xAAAA /*!< IWDG Reload Counter Enable. */
+#define IWDG_KEY_UNLOCK  0x5555 /*!< IWDG KR Write Access Enable*/
+ 
+/*!
+ * @addtogroup IWDG_STATUS
+ * @{
+ */
+#define IWDG_STATUS_RELOAD_UPDATE     IWDG_SR_RVU_MASK           /*!< Status flag when IWDG counter reload value update, can not be cleared. */
+#define IWDG_STATUS_PRESCALER_UPDATE  IWDG_SR_PVU_MASK           /*!< Status flag when IWDG prescaler value update, can not be cleared. */
+#define IWDG_STATUS_ALMOST_TIMEOUT    IWDG_SR_IVU_MASK           /*!< Status flag when IWDG almost timeout. */    
+/*!
+ * @}
+ */
+
+/*!
+ * @addtogroup IWDG_INT
+ * @{
+ */
+#define IWDG_INT_ALMOST_TIMEOUT  IWDG_CR_IRQSEL_MASK           /*!< IWDG Interrupt: Select IWDG interrupt method */
+/*!
+ * @}
+ */
+ 
+/*!
+ * @brief IWDG prescaler type.
+ *
+ * Select the prescaler of time base as the IWDG counter clock.
+ */
+typedef enum
+{
+    IWDG_Prescaler_4   = 0u, /*!< IWDG prescaler 4. */
+    IWDG_Prescaler_8   = 1u, /*!< IWDG prescaler 8. */
+    IWDG_Prescaler_16  = 2u, /*!< IWDG prescaler 16. */
+    IWDG_Prescaler_32  = 3u, /*!< IWDG prescaler 32. */
+    IWDG_Prescaler_64  = 4u, /*!< IWDG prescaler 64. */
+    IWDG_Prescaler_128 = 5u, /*!< IWDG prescaler 128. */
+    IWDG_Prescaler_256 = 6u, /*!< IWDG prescaler 256. */
+} IWDG_Prescaler_Type;
+
+/*!
+ * @brief This type of structure instance is used to keep the settings when calling the @ref IWDG_Init() to initialize the IWDG module.
+ */
+typedef struct
+{
+    IWDG_Prescaler_Type  Prescaler; /*!< Specify the IWDG counter time base division value. */
+    uint32_t             Relaod;    /*!< Specify the IWDG counter reload value. */
+} IWDG_Init_Type;
+
+/*!
+ * @brief Initialize the IWDG module.
+ *
+ * @param IWDGx IWDG instance.
+ * @param init Pointer to the initialization structure. See to @ref IWDG_Init_Type.
+ * @return None.
+ */
+void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init);
+
+/*!
+ * @brief Start the IWDG counter.
+ *
+ * Once IWDG counter is started, it cannot be stopped unless reset MCU.
+ *
+ * @param IWDGx IWDG instance.
+ * @return None.
+ */
+void IWDG_Start(IWDG_Type * IWDGx);
+
+/*!
+ * @brief Get the current status flags of the IWDG module.
+ *
+ * @param IWDGx IWDG instance.
+ * @return Status flags. See to @ref IWDG_STATUS.
+ */
+uint32_t IWDG_GetStatus(IWDG_Type * IWDGx);
+
+/*!
+ * @brief Clear the status flags of the IWDG module.
+ *
+ * @param IWDGx IWDG instance.
+ * @param status Status flags. See to @ref IWDG_STATUS.
+ * @return None.
+ */
+void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status);
+
+/*!
+ * @brief Do reload IWDG counter (i.e. "feed dog").
+ * 
+ * @param IWDGx IWDG instance.
+ * @return None.
+ */
+void IWDG_DoReload(IWDG_Type * IWDGx);
+
+/*!
+ * @brief Enable interrupts of the IWDG module.
+ *
+ * @param IWDGx IWDG instance.
+ * @param interrupts Interrupt code masks. See to @ref IWDG_INT.
+ * @param enable 'true' to enable the indicated interrupts, 'false' has no effect.
+ * @return None.
+ */
+void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable);
+
+/*!
+ *@}
+ */
+
+#endif /* __HAL_IWDG_H__ */
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_TIM_BASIC_H__
+#define __HAL_TIM_BASIC_H__
+
+#include "hal_common.h"
+
+/*!
+ * @addtogroup TIM_BASIC
+ * @{
+ */
+
+/*!
+ * @brief TIM_BASIC driver version number.
+ */
+#define TIM_BASIC_DRIVER_VERSION 0u /*!< TIM_BASIC_0. */
+
+/*!
+ * @addtogroup TIM_BASIC_INT
+ * @brief Enable interrupt.
+ * @{
+ */
+#define TIM_BASIC_INT_UPDATE_PERIOD           (1u << 0u) /*!< Timer update period interrupt switchers. */
+/*!
+ * @}
+ */
+
+/*!
+ * @addtogroup TIM_BASIC_DMA
+ * @brief Enable DMA.
+ * @{
+ */
+#define TIM_BASIC_DMA_UPDATE_PERIOD           (1u << 8u) /*!< Timer update period interrupt switchers. */
+/*!
+ * @}
+ */
+
+/*!
+ * @addtogroup TIM_BASIC_INT_STATUS
+ * @brief Check interrupt status.
+ * @{
+ */
+#define TIM_BASIC_STATUS_UPDATE_PERIOD            (1u << 0u) /*!< Timer update period interrupt flag. */
+/*!
+ * @}
+ */
+
+/*!
+ * @addtogroup TIM_BASIC_SWTRG
+ * @brief Events to be triggered by software.
+ * @{
+ */
+#define TIM_BASIC_SWTRG_UPDATE_PERIOD            (1u << 0u) /*!< Timer update period trigger. */
+/*!
+ * @}
+ */
+
+/*!
+ * @brief Counter period working mode.
+ */
+typedef enum
+{
+    TIM_BASIC_PeriodMode_Continuous = 0u, /*!< The counter would count from zero to indicated period value then generate an update circularly. */
+    TIM_BASIC_PeriodMode_OneTimeRun = 1u, /*!< The counter would count from zero to indicated period value then generate an update then stop. */
+} TIM_BASIC_PeriodMode_Type;
+
+/*!
+ * @brief This type of structure instance is used to keep the settings when calling the @ref TIM_BASIC_Init() to initialize the TIM module time base unit.
+ */
+typedef struct
+{
+    uint32_t ClockFreqHz;                   /*!< Frequence of clock source for counter. */
+    uint32_t StepFreqHz;                    /*!< Step length value. Counter's StepFreqHz = ClockSourceFreqHz / (ClockSourceDiv+1). */
+    uint32_t Period;                        /*!< Counter counting period length, from 0 to Period. */
+    bool EnablePreloadPeriod;               /*!< Enable the preload of period value. If enable, it will be updated in next period, otherwise immediately. */
+    TIM_BASIC_PeriodMode_Type PeriodMode;   /*!< Counting working mode. */
+} TIM_BASIC_Init_Type;
+
+/*!
+ * @brief Set the timer's step for indicated TIM module.
+ * 
+ * @param TIMx TIM_BASIC instance.
+ * @param init Pointer to the initialization structure. See to @ref TIM_BASIC_Init_Type.
+ * @return 'true' to set the timer's step successfully, 'false' to fail because the invalid StepFreqHz.
+ */
+bool TIM_BASIC_Init(TIM_BASIC_Type * TIMx, TIM_BASIC_Init_Type * init);
+
+/*!
+ * @brief Start counting.
+ * 
+ * @param TIMx TIM_BASIC instance.
+ * @return None.
+ */
+void TIM_BASIC_Start(TIM_BASIC_Type * TIMx);
+
+/*!
+ * @brief Stop counting immediately.
+ * 
+ * @param TIMx TIM_BASIC instance.
+ * @return None.
+ */
+void TIM_BASIC_Stop(TIM_BASIC_Type * TIMx);
+
+/*!
+ * @brief Get the indicated TIMx Counter value.
+ *
+ * @param TIMx TIM_BASIC_Type instance.
+ * @return The current value of the counter register.
+ */
+uint32_t TIM_BASIC_GetCounterValue(TIM_BASIC_Type * TIMx);
+
+/*!
+ * @brief Enable the TIM_BASIC interrupts.
+ *
+ * @param TIMx TIM_BASIC_Type instance.
+ * @param interrupts Interrupts to be enabled.See to @ref TIM_BASIC_INT.
+ * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
+ * @return None.
+ */
+void TIM_BASIC_EnableInterrupts(TIM_BASIC_Type *TIMx, uint32_t interrupts, bool enable);
+
+/*!
+ * @brief Enable the TIM_BASIC DMAs.
+ *
+ * @param TIMx TIM_BASIC_Type instance.
+ * @param dmas DMA masks to be enabled. See to @ref TIM_BASIC_DMA.
+ * @param enable 'true' to enable the indicated interrupts or DMAs, 'false' to disable the indicated interrupts or DMAs.
+ * @return None.
+ */
+void TIM_BASIC_EnableDMA(TIM_BASIC_Type *TIMx, uint32_t dmas, bool enable);
+
+/*!
+ * @brief Software trigger events to call interrupts or DMAs.
+ *
+ * Can simultaneously trigger multiple events.
+ * 
+ * @param TIMx TIM_BASIC instance. See to @ref TIM_BASIC_SWTRG.
+ * @param swtrgs Trigger the events to generate interrupts.
+ */
+void TIM_BASIC_DoSwTrigger(TIM_BASIC_Type *TIMx, uint32_t swtrgs);
+
+/*!
+ * @brief Get the status of the indicated timer.
+ *
+ * @param TIMx TIM_BASIC_Type instance.
+ * @return Interrupt status flags. See to @ref TIM_BASIC_INT_STATUS.
+ */
+uint32_t TIM_BASIC_GetInterruptStatus(TIM_BASIC_Type * TIMx);
+
+/*!
+ * @brief Clear the status of indicated interrupt.
+ *
+ * @param TIMx TIM_BASIC_Type instance.
+ * @param status The required clear flag type. See to @ref TIM_BASIC_INT_STATUS.
+ * @return None.
+ */
+void TIM_BASIC_ClearInterruptStatus(TIM_BASIC_Type *TIMx, uint32_t status);
+
+/*!
+ *@}
+ */
+#endif /* __HAL_TIM_BASIC_H__ */
+
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_USB_BDT_H__
+#define __HAL_USB_BDT_H__
+
+#include "hal_common.h"
+
+/*!
+ * @addtogroup USB
+ * @{
+ */
+
+/*!
+ * @brief USB BufDesp EndPoint number.
+ */
+#define USB_BDT_EP_NUM          16u  /*!< USB BufDesp EndPoint num. */
+
+/*!
+ * @brief USB BufDesp EndPoint direction number.
+ */
+#define USB_BDT_DIRECTION_NUM   2u  /*!< USB BufDesp EndPoint direction num. */
+
+/*!
+ * @brief  USB BufDesp EndPoint buffer number.
+ */
+#define USB_BDT_BUF_NUM         2u  /*!< USB BufDesp EndPoint buffer num. */
+
+/*!
+ * @brief This type of structure instance is used to implement the buffer descriptor for USB.
+ */
+typedef struct
+{
+    union
+    {
+        uint32_t HEAD; /*!< Head. */
+        struct
+        {
+            uint32_t RESEVED0   :2;  /*!< RESEVED. */
+            uint32_t BDT_STALL  :1;  /*!< Stall. */
+            uint32_t DTS        :1;  /*!< Data shift sync. */
+            uint32_t NINC       :1;  /*!< DMA addr cannot increasing. */
+            uint32_t KEEP       :1;  /*!< Keep BD held by USB. */
+            uint32_t DATA       :1;  /*!< DATA0 or DATA1. */
+            uint32_t OWN        :1;  /*!< Owner, 0 is CPU, 1 is USB. */
+            uint32_t RESEVED1   :8;  /*!< RESEVED. */
+            uint32_t BC         :10; /*!< Packet size. */
+            uint32_t RESEVED2   :6;  /*!< RESEVED. */
+        };
+        struct
+        {
+            uint32_t RESEVED3   :2;  /*!< RESEVED. */
+            uint32_t TOK_PID    :4;  /*!< Token pid. */
+            uint32_t RESEVED4   :26; /*!< RESEVED. */
+        };
+    };
+    uint32_t ADDR; /*!< Buffer addr. */
+} USB_BufDesp_Type;
+
+/*!
+ * @brief This type of structure instance is used to implement the buffer descriptor table for USB.
+ */
+typedef union
+{
+    USB_BufDesp_Type Table[USB_BDT_EP_NUM][ USB_BDT_DIRECTION_NUM][ USB_BDT_BUF_NUM]; /*!< [EndPoint] [Direction] [Odd_Even]. */
+    USB_BufDesp_Type Index[USB_BDT_EP_NUM * USB_BDT_DIRECTION_NUM * USB_BDT_BUF_NUM]; /*!< Index. */
+} USB_BufDespTable_Type;
+
+/*!
+ * @}
+ */
+
+#endif /* __HAL_USB_BDT_H__ */
+
@@ -0,0 +1,128 @@
+/* hal_wwdg.h */
+
+#ifndef __HAL_WWDG_H__
+#define __HAL_WWDG_H__
+
+/*!
+ * @addtogroup WWDG
+ * @{
+ */
+
+#include "hal_common.h"
+
+/*!
+ * @brief WWDG driver version number.
+ */
+#define WWDG_DRIVER_VERSION 0u /*!< WWDG_0. */
+
+/*!
+ * @brief The lower limit value of WWDG counter.
+ */
+#define WWDG_LOWER_LIMIT 0x40u /*!< If WWDG counter Below this value, WWDG will generate a reset request. */
+
+/*!
+ * @addtogroup WWDG_INT
+ * @brief WWDG_STATUS mask codes
+ * @{
+ */
+#define WWDG_INT_ALMOST_TIMEOUT WWDG_CFGR_EWI_MASK /*!< WWDG interrupt: Almost timeout. */
+/*!
+ * @}
+ */
+
+/*!
+ * @addtogroup WWDG_STATUS
+ * @brief WWDG_STATUS mask codes
+ * @{
+ */
+#define WWDG_STATUS_ALMOST_TIMEOUT WWDG_SR_EWIF_MASK /*!< WWDG status: Almost timeout. */
+/*!
+ * @}
+ */
+
+/*!
+ * @brief WWDG prescaler type.
+ *
+ * Select the prescaler of WWDG counter clock.
+ */
+typedef enum
+{
+    WWDG_Prescaler_1 = 0u, /*!< WWDG Prescaler 1. */
+    WWDG_Prescaler_2 = 1u, /*!< WWDG Prescaler 2. */
+    WWDG_Prescaler_4 = 2u, /*!< WWDG Prescaler 4. */
+    WWDG_Prescaler_8 = 3u, /*!< WWDG Prescaler 8. */
+} WWDG_Prescaler_Type;
+
+/*!
+ * @brief This type of structure instance is used to keep the settings when calling the @ref WWDG_Init() to initialize the USB module.
+ */
+typedef struct
+{
+    WWDG_Prescaler_Type Prescaler;  /*!< Specify the WWDG counter prescaler. */
+    uint32_t            UpperLimit; /*!< Specify the upperLimit, WWDG will generate a reset request if reload WWDG counter before the counter value greater than UpperLimit. */
+} WWDG_Init_Type;
+
+/*!
+ * @brief Initialize the WWDG module.
+ *
+ * @param WWDGx WWDG instance.
+ * @param init Pointer to the initialization structure. See to @ref WWDG_Init_Type.
+ * @return None.
+ */
+void WWDG_Init(WWDG_Type * WWDGx, WWDG_Init_Type * init);
+
+/*!
+ * @brief Start counting.
+ *
+ * If the counter is started, it cannot be stoped unless reset MCU.
+ *
+ * @param WWDGx WWDG instance.
+ * @return None.
+ */
+void WWDG_Start(WWDG_Type * WWDGx);
+
+/*!
+ * @brief Reolad WWDG counter (Feed dog).
+ *
+ * Reload WWDG counter to ensure that the counter value greater than WWDG_LOWER_LIMIT_VALUE and prevent generate a reset request.
+ *
+ * @param WWDGx WWDG instance.
+ * @param value The value of reload WWDG counter, the value ranges from 0x40 to 0x7f.
+ * @return None.
+ */
+void WWDG_Reload(WWDG_Type * WWDGx, uint32_t value);
+
+/*!
+ * @brief Enable interrupts of the WWDG module.
+ *
+ * @param WWDGx WWDG instance.
+ * @param interrupts Interrupt code masks. See to @ref WWDG_INT.
+ * @param enable 'true' to enable the indicated interrupts, 'false' has no effect.
+ * @return None.
+ */
+void WWDG_EnableInterrupts(WWDG_Type * WWDGx, uint32_t interrupts, bool enable);
+
+/*!
+ * @brief Get the status flags of the WWDG module.
+ *
+ * @param WWDGx WWDG instance.
+ * @return status flags. See to @ref WWDG_STATUS.
+ */
+uint32_t WWDG_GetStatus(WWDG_Type * WWDGx);
+
+/*!
+ * @brief Clear the status flags of the WWDG module.
+ *
+ * @param WWDGx WWDG instance.
+ * @param status status flags. See to @ref WWDG_STATUS.
+ * @return None.
+ */
+void WWDG_ClearStatus(WWDG_Type * WWDGx, uint32_t status);
+
+/*!
+ *@}
+ */
+
+#endif /* __HAL_WWDG_H__. */
+
+/* EOF. */
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hal_comp.h"
+
+void COMP_Init(COMP_Type * COMPx, uint32_t channel, COMP_Init_Type * init)
+{
+    if ( channel < COMP_CHANNEL_NUM )
+    {
+        COMPx->CSR[channel] = COMP_CSR_OFLT(init->OutFilter)
+                            | COMP_CSR_HYST(init->Hysteresis)
+                            | COMP_CSR_POL(init->OutInvert)
+                            | COMP_CSR_OUTSEL(init->OutMux)
+                            | COMP_CSR_INPSEL(init->PosInMux)
+                            | COMP_CSR_INMSEL(init->InvInMux)
+                            | COMP_CSR_MODE(init->Speed)
+                            ;
+    }
+}
+
+void COMP_Enable(COMP_Type * COMPx, uint32_t channel, bool enable)
+{
+    if ( channel < COMP_CHANNEL_NUM )
+    {
+        if ( true == enable )
+        {
+            COMPx->CSR[channel] |=  COMP_CSR_EN_MASK;
+        }
+        else
+        {
+            COMPx->CSR[channel] &= ~COMP_CSR_EN_MASK;
+        }
+    }
+}
+
+void COMP_Lock(COMP_Type * COMPx, uint32_t channel)
+{
+    if ( channel < COMP_CHANNEL_NUM )
+    {
+        COMPx->CSR[channel] |= COMP_CSR_LOCK_MASK;
+    }
+}
+
+bool COMP_GetOutputStatus(COMP_Type * COMPx, uint32_t channel)
+{
+    if ( channel < COMP_CHANNEL_NUM )
+    {
+        if ( 0u != ( COMP_CSR_OUT_MASK & COMPx->CSR[channel] ) )
+        {
+            return true;
+        }
+        else
+        {
+            return false; /* normal input voltage lower than inverting input. */
+        }
+    }
+    else
+    {
+        return false;
+    }
+}
+
+void COMP_EnableExtVrefConf(COMP_Type * COMPx, COMP_ExtVrefConf_Type * conf)
+{
+    if ( NULL == conf ) /* disable the ext vref. */
+    {
+        COMPx->CRV &= ~COMP_CRV_CRVEN_MASK;
+    }
+    else /* init & enable ext vref. */
+    {
+        COMPx->CRV = COMP_CRV_CRVSRC    (conf->VrefSource)
+                   | COMP_CRV_CRVSEL    (conf->Volt)
+                   | COMP_CRV_CRVEN_MASK
+                   ;
+    }
+}
+
+void COMP_EnableRoundRobinConf(COMP_Type * COMPx, uint32_t channel, COMP_RoundRobinConf_Type * conf)
+{
+    if ( channel < COMP_CHANNEL_NUM )
+    {
+        if ( NULL == conf )
+        {
+            COMPx->POLL[channel] &= ~COMP_POLL_POLLEN_MASK;
+        }
+        else
+        {
+            COMPx->POLL[channel] = COMP_POLL_PERIOD(conf->Period)
+                                 | COMP_POLL_FIXN(conf->InvInFix)
+                                 | COMP_POLL_POLLCH(conf->ChnGroup)
+                                 | COMP_POLL_POLLEN_MASK;
+                                 ;
+        }
+    }
+}
+
+bool COMP_GetRoundRobinOutStatus(COMP_Type * COMPx, uint32_t channel, COMP_InMux_Type pos_in)
+{
+    if ( channel < COMP_CHANNEL_NUM )
+    {
+        uint32_t flag = COMP_POLL_POUT(1 << ( (uint32_t)pos_in - 1 ) );
+        if ( 0 != (COMPx->POLL[channel] & flag ) )
+        {
+            return true;
+        }
+        else
+        {
+            return false;
+        }
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* EOF. */
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hal_dma.h"
+
+/* clear all the interrupt enables and disable the dma channel. */
+uint32_t DMA_InitChannel(DMA_Type * DMAx, uint32_t channel, DMA_Channel_Init_Type * init)
+{
+    uint32_t ccr = 0u;
+    
+    if (   (init->XferMode == DMA_XferMode_MemoryToPeriph)
+        || (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
+    {
+        ccr |= DMA_CCR_DIR_MASK;
+    }
+    
+    if (   (init->XferMode == DMA_XferMode_PeriphToMemoryBurst)
+        || (init->XferMode == DMA_XferMode_MemoryToPeriphBurst) )
+    {
+        ccr |= DMA_CCR_MEM2MEM_MASK;
+    }
+    
+    if (init->ReloadMode == DMA_ReloadMode_AutoReload)
+    {
+        ccr |= DMA_CCR_ARE_MASK;
+    }
+    else if (init->ReloadMode == DMA_ReloadMode_AutoReloadContinuous)
+    {
+        ccr |= (DMA_CCR_ARE_MASK | DMA_CCR_CIRC_MASK);
+    }
+
+    ccr |= DMA_CCR_PINC(init->PeriphAddrIncMode)
+         | DMA_CCR_MINC(init->MemAddrIncMode)
+         | DMA_CCR_PSIZE(init->XferWidth)
+         | DMA_CCR_MSIZE(init->XferWidth)
+         | DMA_CCR_PL(init->Priority)
+         ;
+    
+    DMAx->CH[channel].CCR = ccr;
+    DMAx->CH[channel].CNDTR = init->XferCount;
+    DMAx->CH[channel].CPAR = init->PeriphAddr;
+    DMAx->CH[channel].CMAR = init->MemAddr;
+    
+    return 0u;
+}
+
+void DMA_EnableChannelInterrupts(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts, bool enable)
+{
+    if (enable)
+    {
+        DMAx->CH[channel].CCR |= (interrupts & 0xEu);
+    }
+    else
+    {
+        DMAx->CH[channel].CCR &= ~(interrupts & 0xEu);
+    }
+}
+
+uint32_t DMA_GetChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel)
+{
+    return (DMAx->ISR >> (channel * 4u)) & 0xFu;
+}
+
+void DMA_ClearChannelInterruptStatus(DMA_Type * DMAx, uint32_t channel, uint32_t interrupts)
+{
+    DMAx->IFCR = ( (interrupts & 0xFu) << (channel * 4u) );
+}
+
+void DMA_EnableChannel(DMA_Type * DMAx, uint32_t channel, bool enable)
+{
+    if (enable)
+    {
+        DMAx->CH[channel].CCR |= DMA_CCR_EN_MASK;
+    }
+    else
+    {
+        DMAx->CH[channel].CCR &= ~DMA_CCR_EN_MASK;
+    }
+}
+
+/* EOF. */
+
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "hal_exti.h"
+
+void EXTI_EnableLineInterrupt(EXTI_Type * EXTIx, uint32_t lines, bool enable)
+{
+    if (enable)
+    {
+        EXTIx->IMR |= lines;
+    }
+    else
+    {
+        EXTIx->IMR &= ~ lines;
+    }
+}
+
+void EXTI_EnableLineEvent(EXTI_Type * EXTIx, uint32_t lines, bool enable)
+{
+    if (enable)
+    {
+        EXTIx->EMR |= lines;
+    }
+    else
+    {
+        EXTIx->EMR &= ~ lines;
+    }
+}
+
+void EXTI_SetTriggerIn(EXTI_Type * EXTIx, uint32_t lines, EXTI_TriggerIn_Type trgin)
+{
+    switch (trgin)
+    {
+        case EXTI_TriggerIn_Disable:
+            EXTIx->RTSR &= ~ lines;
+            EXTIx->FTSR &= ~ lines;
+            break;
+        case EXTI_TriggerIn_RisingEdge:
+            EXTI->RTSR |= lines;
+            EXTIx->FTSR &= ~ lines;            
+            break;
+        case EXTI_TriggerIn_FallingEdge:
+            EXTI->RTSR &= ~ lines;
+            EXTI->FTSR |= lines;
+            break;
+        case EXTI_TriggerIn_BothEdges:
+            EXTI->RTSR |= lines;
+            EXTI->FTSR |= lines;
+            break;
+        default:
+            break;
+    }
+}
+
+void EXTI_DoSwTrigger(EXTI_Type * EXTIx, uint32_t lines)
+{
+    EXTIx->SWIER = lines;
+}
+
+uint32_t EXTI_GetLineStatus(EXTI_Type * EXTIx)
+{
+    return EXTIx->PR;
+}
+
+void EXTI_ClearLineStatus(EXTI_Type * EXTIx, uint32_t lines)
+{
+    EXTIx->PR |= lines;
+}
+
+/* EOF. */
+
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "hal_fsmc.h"
+
+const uint32_t FSMC_BankBases[] = 
+{
+    FSMC_BANK0_BASE,
+    FSMC_BANK1_BASE,
+    FSMC_BANK2_BASE,
+    FSMC_BANK3_BASE
+};
+
+void FSMC_Init(FSMC_Type * FSMCx, FSMC_Init_Type * init)
+{
+    FSMCx->SMSKR0 = ( (FSMCx->SMSKR0 & ~(FSMC_SMSKR0_MEMSIZE_MASK | FSMC_SMSKR0_MEMTYPE_MASK) )
+                                     |  FSMC_SMSKR0_MEMSIZE(init->MemSize)
+                                     |  FSMC_SMSKR0_MEMTYPE(init->MemType) )
+                                     ;
+}
+
+void FSMC_SetConf(FSMC_Type * FSMCx, uint32_t index, FSMC_Conf_Type * init)
+{
+    if (index >= FSMC_SMTMGR_REG_NUM)
+    {
+        return;
+    }
+    FSMCx->SMTMGRSET[index] = FSMC_SMTMGRSET_TRC(init->ReadPeriod)
+                            | FSMC_SMTMGRSET_TAS(init->AddrSetTime)
+                            | FSMC_SMTMGRSET_TWR(init->WriteHoldTime)
+                            | FSMC_SMTMGRSET_TWP(init->WritePeriod)
+                            | FSMC_SMTMGRSET_READYMODE(init->ReadySignal)
+                            | FSMC_SMTMGRSET_SMREADPIPE(init->SMReadPipe)
+                            ;
+    switch (index)
+    {
+        case 0u:
+            FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDATAWIDTHSET0_MASK)
+                                             |  FSMC_SMCTLR_SMDATAWIDTHSET0(init->BusWidth) )
+                                             ;
+            break;
+        case 1u:
+            FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDATAWIDTHSET1_MASK)
+                                             |  FSMC_SMCTLR_SMDATAWIDTHSET1(init->BusWidth) )
+                                             ;
+            break;
+        case 2u:
+            FSMCx->SMCTLR = ( (FSMCx->SMCTLR & ~FSMC_SMCTLR_SMDATAWIDTHSET2_MASK)
+                                             |  FSMC_SMCTLR_SMDATAWIDTHSET2(init->BusWidth) )
+                                             ;
+            break;
+        default:
+            break;
+    }
+}
+
+ /* only last enabled bankn is available. */
+void FSMC_EnableConf(FSMC_Type * FSMCx, uint32_t index)
+{
+    if (index >= FSMC_SMTMGR_REG_NUM)
+    {
+        return;
+    }
+    FSMCx->SMSKR0 = ( (FSMCx->SMSKR0 & ~FSMC_SMSKR0_REGSELECT_MASK)
+                                     |  FSMC_SMSKR0_REGSELECT(index) )
+                                     ;
+}    
+
+void FSMC_PutData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint32_t data)
+{
+    (void)FSMCx;
+    *( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) = data;
+}
+
+uint32_t FSMC_GetData32(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
+{
+    (void)FSMCx;
+    return (*( (uint32_t *)(FSMC_BankBases[bankn] + offset) ) );
+}
+
+uint32_t FSMC_GetXferDataRegAddr(FSMC_Type *FSMCx, uint32_t bankn, uint32_t offset)
+{
+    (void)FSMCx;
+    return (FSMC_BankBases[bankn] + offset);
+}
+
+void FSMC_PutData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint16_t data)
+{
+    (void)FSMCx;
+    *( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) = data;
+}
+
+uint16_t FSMC_GetData16(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
+{
+    (void)FSMCx;
+    return (*( (uint16_t *)(FSMC_BankBases[bankn] + offset) ) );
+}
+
+void     FSMC_PutData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset, uint8_t data)
+{
+    (void)FSMCx;
+    *( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) = data;
+}
+
+uint8_t  FSMC_GetData8(FSMC_Type * FSMCx, uint32_t bankn, uint32_t offset)
+{
+    (void)FSMCx;
+    return (*( (uint8_t *)(FSMC_BankBases[bankn] + offset) ) );
+}
+
+/* EOF. */
+
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hal_gpio.h"
+
+void GPIO_Init(GPIO_Type  * GPIOx, GPIO_Init_Type * init)
+{
+    uint8_t idx;
+    uint8_t i;
+    uint32_t pin;
+    __IO uint32_t * addr;
+
+    /* 1x. */
+    uint32_t dat = init->PinMode & 0xFu;
+    if (init->PinMode & 0x10u)
+    {
+        dat |= init->Speed;
+    }
+
+    /* 0x. */
+    addr = &(GPIOx->CRL);
+    for (i = 0u; i < 8u; i++)
+    {
+        idx = i * 4u;
+        if ( (init->Pins) & (1u << i) )
+        {
+            *addr = ( *addr  & ~(0xFu << idx) ) | (dat << idx);
+        }
+    }
+
+    addr = &(GPIOx->CRH);
+    pin = init->Pins >> 8u;
+    for (i = 0u; i < 8u; i++)
+    {
+        idx = i * 4u;
+        if ( pin & (1u << i) )
+        {
+            *addr  = ( *addr  & ~(0xFu << idx) ) | (dat << idx);
+        }
+    }
+
+    /* 2x,4x. */
+    if (init->PinMode == GPIO_PinMode_In_PullDown)
+    {
+        GPIOx->BRR |= init->Pins;
+    }
+    else if (init->PinMode == GPIO_PinMode_In_PullUp)
+    {
+        GPIOx->BSRR |= init->Pins;
+    }
+}
+
+bool GPIO_ReadInDataBit(GPIO_Type  * GPIOx, uint16_t pin)
+{
+    return (GPIOx->IDR & pin);
+}
+
+uint16_t GPIO_ReadInData(GPIO_Type * GPIOx)
+{
+    return (uint16_t)(GPIOx->IDR);
+}
+
+bool GPIO_ReadOutDataBit(GPIO_Type * GPIOx, uint16_t pins)
+{
+    return (GPIOx->ODR & pins);
+}
+
+uint16_t GPIO_ReadOutData(GPIO_Type * GPIOx)
+{
+    return (uint16_t)GPIOx->ODR;
+}
+
+void GPIO_SetBits(GPIO_Type * GPIOx, uint16_t pins)
+{
+    GPIOx->BSRR = pins;
+}
+
+void GPIO_ClearBits(GPIO_Type * GPIOx, uint16_t pins)
+{
+    GPIOx->BRR = pins;
+}
+
+void GPIO_WriteBit(GPIO_Type * GPIOx, uint16_t pins, uint16_t val)
+{
+    (val != 0u) ? (GPIOx->BSRR = pins) : (GPIOx->BRR = pins);
+}
+
+void GPIO_WriteBits(GPIO_Type * GPIOx, uint16_t val)
+{
+    GPIOx->ODR = val;
+}
+
+void GPIO_PinLock(GPIO_Type * GPIOx, uint16_t pins, bool enable_lock)
+{
+    (enable_lock) ? (GPIOx->LCKR |= pins) : (GPIOx->LCKR &= ~pins);
+}
+
+void GPIO_PinLockConf(GPIO_Type * GPIOx, uint16_t pins)
+{
+    GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins);
+    GPIOx->LCKR = pins;
+    GPIOx->LCKR = GPIO_LCKR_LCKK_MASK | GPIO_LCKR_LCK(pins);
+    GPIOx->LCKR;
+    GPIOx->LCKR;
+}
+
+void GPIO_PinAFConf(GPIO_Type * GPIOx, uint16_t pins, uint8_t af)
+{
+    uint32_t shift = 0u;
+    uint32_t idx = 0u;
+    uint32_t val = GPIOx->AFRL;
+    while (idx < 8u)
+    {
+        if ( ( (1u << idx) & pins) != 0u )
+        {
+            shift = idx * 4u;
+            val &= ~(0xFu << shift);
+            val |= (uint32_t)af << shift;
+        }
+        idx++;
+    }
+    GPIOx->AFRL = val;
+
+    val = GPIOx->AFRH;
+    while (idx < 16u)
+    {
+        if ( ( (1u << idx) & pins) != 0u )
+        {
+            shift = (idx - 8u) * 4u;
+            val &= ~(0xFu << shift);
+            val |= (uint32_t)af << shift;
+        }
+        idx++;
+    }
+    GPIOx->AFRH = val;
+}
+
+void GPIO_PortAFConfig(GPIO_Type * GPIOx, uint32_t af_high, uint32_t af_low)
+{
+    GPIOx->AFRL = af_low;
+    GPIOx->AFRH = af_high;
+}
+
+/* EOF. */
+
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hal_iwdg.h"
+
+void IWDG_Init(IWDG_Type * IWDGx, IWDG_Init_Type * init)
+{   
+    if ( NULL != init )
+    {
+        IWDGx->KR = IWDG_KEY_UNLOCK;    
+        IWDGx->PR = init->Prescaler;
+        
+        IWDGx->KR = IWDG_KEY_UNLOCK;
+        IWDGx->RLR = init->Relaod;
+
+        IWDG_DoReload(IWDGx);
+    }
+}
+
+void IWDG_Start(IWDG_Type * IWDGx)
+{
+    IWDGx->KR = IWDG_KEY_ENABLE;
+}
+
+uint32_t IWDG_GetStatus(IWDG_Type * IWDGx)
+{
+    return IWDGx->SR;
+}
+
+void IWDG_DoReload(IWDG_Type * IWDGx)
+{
+    IWDGx->KR = IWDG_KEY_RELOAD;
+}
+
+void IWDG_EnableInterrupts(IWDG_Type * IWDGx, uint32_t interrupts, bool enable)
+{
+    if( (true == enable ) && (IWDG_INT_ALMOST_TIMEOUT == interrupts) )
+    {
+        IWDGx->CR |= IWDG_CR_IRQSEL_MASK;
+    }
+    else
+    {
+        /* if IWDG_EnableInterrupts interrupt was enabled, only MCU reset can close it. */
+    }
+}
+
+void IWDG_ClearStatus(IWDG_Type * IWDGx, uint32_t status)
+{
+    if( 0u != ( status & IWDG_CR_IRQCLR_MASK ) )
+    {
+        IWDGx->CR |=  IWDG_CR_IRQCLR_MASK;
+    }
+}
+
+/* EOF. */
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#include "hal_common.h"
+#include "hal_rcc.h"
+
+void RCC_EnableAHB1Periphs(uint32_t ahb1_periphs, bool enable)
+{
+    (enable) ? (RCC->AHB1ENR |= ahb1_periphs) : (RCC->AHB1ENR &= ~ahb1_periphs);
+}
+
+void RCC_EnableAHB2Periphs(uint32_t ahb2_periphs, bool enable)
+{
+    (enable) ? (RCC->AHB2ENR |= ahb2_periphs) : (RCC->AHB2ENR &= ~ahb2_periphs);
+}
+
+void RCC_EnableAHB3Periphs(uint32_t ahb3_periphs, bool enable)
+{
+    (enable) ? (RCC->AHB3ENR |= ahb3_periphs) : (RCC->AHB3ENR &= ~ahb3_periphs);
+}
+
+void RCC_EnableAPB1Periphs(uint32_t apb1_periphs, bool enable)
+{
+    (enable) ? (RCC->APB1ENR |= apb1_periphs) : (RCC->APB1ENR &= ~apb1_periphs);
+}
+
+void RCC_EnableAPB2Periphs(uint32_t apb2_periphs, bool enable)
+{
+    (enable) ? (RCC->APB2ENR |= apb2_periphs) : (RCC->APB2ENR &= ~apb2_periphs);
+}
+
+void RCC_ResetAHB1Periphs(uint32_t ahb1_periphs)
+{
+    RCC->AHB1RSTR |= ahb1_periphs;
+    RCC->AHB1RSTR &= ~ahb1_periphs;
+}
+
+void RCC_ResetAHB2Periphs(uint32_t ahb2_periphs)
+{
+    RCC->AHB2RSTR |= ahb2_periphs;
+    RCC->AHB2RSTR &= ~ahb2_periphs;
+}
+
+void RCC_ResetAHB3Periphs(uint32_t ahb3_periphs)
+{
+    RCC->AHB3RSTR |= ahb3_periphs;
+    RCC->AHB3RSTR &= ~ahb3_periphs;
+}
+
+void RCC_ResetAPB1Periphs(uint32_t apb1_periphs)
+{
+    RCC->APB1RSTR |= apb1_periphs;
+    RCC->APB1RSTR &= ~apb1_periphs;
+}
+
+void RCC_ResetAPB2Periphs(uint32_t apb2_periphs)
+{
+    RCC->APB2RSTR |= apb2_periphs;
+    RCC->APB2RSTR &= ~apb2_periphs;
+}
+
+void RCC_MCOConf(RCC_MCO_Type source)
+{
+    RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCO_MASK) | RCC_CFGR_MCO(source);
+}
+
+/* EOF. */
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "hal_spi.h"
+
+void SPI_SetBaudrate(SPI_Type * SPIx, uint32_t src_clk, uint32_t baudrate)
+{
+    uint32_t div = src_clk / baudrate;
+    if (div < 2u)
+    {
+        /* div = 0, 1 is not allowed. */
+        div = 2u;
+    }
+    SPIx->SPBRG = div;
+    if (div <= 4)
+    {
+        /* to support high speed mode. */
+        SPIx->CCTL |= (SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK);
+    }
+    else
+    {
+        SPIx->CCTL &= ~(SPI_I2S_CCTL_TXEDGE_MASK | SPI_I2S_CCTL_RXEDGE_MASK);
+    }
+}
+
+/* SPI peripheral is disabled just after the initialization.
+ * user needs to call SPI_Enable() before using the module.
+ */
+void SPI_InitMaster(SPI_Type * SPIx, SPI_Master_Init_Type * init)
+{
+
+    /* Master. */
+    SPIx->GCTL = SPI_I2S_GCTL_MODE_MASK; /* master mode, disable spi, and reset the other bits in CCTL. */
+
+    /* XferMode. */
+    switch (init->XferMode)
+    {
+        case SPI_XferMode_RxOnly:
+            SPIx->GCTL |= SPI_I2S_GCTL_RXEN_MASK;
+            break;
+
+        case SPI_XferMode_TxRx:
+            SPIx->GCTL |= (SPI_I2S_GCTL_RXEN_MASK | SPI_I2S_GCTL_TXEN_MASK);
+            break;
+
+        default:
+            break;
+    }
+
+    /* AutoCS. */
+    if (init->AutoCS)
+    {
+        SPIx->GCTL |= SPI_I2S_GCTL_NSS_MASK;
+    }
+    else
+    {
+        SPIx->GCTL &= ~SPI_I2S_GCTL_NSS_MASK;
+    }
+
+    /* Interrupts. Always enable the global interrupt. The specific events are controlled by each bits in INTEN register. */
+    SPIx->GCTL |= SPI_I2S_GCTL_INTEN_MASK;
+
+    /* BaudRate. */
+    SPI_SetBaudrate(SPIx, init->ClockFreqHz, init->BaudRate);
+
+    /* DataWidth. */
+    if (init->DataWidth == SPI_DataWidth_8b)
+    {
+        SPIx->GCTL &= ~SPI_I2S_GCTL_DW832_MASK;
+    }
+    else
+    {
+        SPIx->GCTL |= SPI_I2S_GCTL_DW832_MASK;
+        SPIx->EXTCTL = SPI_I2S_EXTCTL_EXTLEN(init->DataWidth);
+    }
+
+    /* CPOL & CPHA. */
+    SPIx->CCTL = (SPIx->CCTL & ~(SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK))
+               | ( (SPI_I2S_CCTL_CPHA_MASK | SPI_I2S_CCTL_CPOL_MASK) & ((init->PolarityPhase) << SPI_I2S_CCTL_CPHA_SHIFT) );
+
+    /* MSB. */
+    if (init->LSB)
+    {
+        SPIx->CCTL |= SPI_I2S_CCTL_LSBFE_MASK;
+    }
+    else
+    {
+        SPIx->CCTL &= ~SPI_I2S_CCTL_LSBFE_MASK;
+    }
+}
+
+void SPI_Enable(SPI_Type * SPIx, bool enable)
+{
+    if (enable)
+    {
+        SPIx->GCTL |= SPI_I2S_GCTL_SPIEN_MASK;
+    }
+    else
+    {
+        SPIx->GCTL &= ~SPI_I2S_GCTL_SPIEN_MASK;
+    }
+}
+
+uint32_t SPI_GetStatus(SPI_Type * SPIx)
+{
+    return SPIx->CSTAT;
+}
+
+void SPI_EnableInterrupts(SPI_Type * SPIx, uint32_t interrupts, bool enable)
+{
+    if (enable)
+    {
+        SPIx->INTEN |= interrupts;
+    }
+    else
+    {
+        SPIx->INTEN &= ~interrupts;
+    }
+}
+
+uint32_t SPI_GetInterruptStatus(SPI_Type * SPIx)
+{
+    return SPIx->INTSTAT;
+}
+
+void SPI_ClearInterruptStatus(SPI_Type * SPIx, uint32_t interrupts)
+{
+    SPIx->INTCLR = interrupts;
+}
+
+void SPI_PutData(SPI_Type * SPIx, uint32_t dat)
+{
+    SPIx->TXREG = dat;
+}
+
+uint32_t SPI_GetData(SPI_Type * SPIx)
+{
+    return SPIx->RXREG;
+}
+
+void SPI_EnableDMA(SPI_Type * SPIx, bool enable)
+{
+    if (enable)
+    {
+        SPIx->GCTL |= SPI_I2S_GCTL_DMAMODE_MASK;
+    }
+    else
+    {
+        SPIx->GCTL &= ~SPI_I2S_GCTL_DMAMODE_MASK;
+    }
+}
+
+uint32_t SPI_GetEnabledInterrupts(SPI_Type * SPIx)
+{
+    return SPIx->INTEN;
+}
+
+uint32_t SPI_GetRxDataRegAddr(SPI_Type * SPIx)
+{
+    return (uint32_t)(&(SPIx->RXREG));
+}
+
+uint32_t SPI_GetTxDataRegAddr(SPI_Type * SPIx)
+{
+    return (uint32_t)(&(SPIx->TXREG));
+}
+
+void SPI_EnableCS(SPI_Type * SPIx, uint32_t cs_mask)
+{
+    SPIx->NSSR = ~(cs_mask);
+}
+
+/* EOF. */
+
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#include "hal_syscfg.h"
+
+#define SYSCFG_EXTICR_MASK(x)   ( (0x0Fu) << ( ( (uint32_t)(x) & 0x3u ) << 2u ) ) /* mask bit for clear exti line. */
+#define SYSCFG_EXTICR(x, y)     ( (uint32_t)( (uint32_t)(x) << ( ( (uint32_t)(y) & 0x3u ) << 2u ) ) ) /* set the data for indicated exti port and line. */
+
+void SYSCFG_SetBootMemMode(SYSCFG_BootMemMode_Type mode)
+{
+    SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_MEMMODE_MASK )
+                 | SYSCFG_CFGR_MEMMODE(mode);
+}
+
+void SYSCFG_SetFSMCPinUseMode(SYSCFG_FSMCPinUseMode_Type mode)
+{
+    SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_FCODATAEN_MASK )
+                 | SYSCFG_CFGR_FCODATAEN(mode);
+}
+
+void SYSCFG_SetFSMCMode(SYSCFG_FSMCMode_Type mode)
+{
+    SYSCFG->CFGR = ( SYSCFG->CFGR & ~ SYSCFG_CFGR_MODESEL_MASK )
+                 | SYSCFG_CFGR_MODESEL(mode);
+}
+
+void SYSCFG_SetExtIntMux(SYSCFG_EXTIPort_Type port, SYSCFG_EXTILine_Type line)
+{
+    if ( line < SYSCFG_EXTILine_4)
+    {
+        SYSCFG->EXTICR1 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
+                        | ( SYSCFG_EXTICR(port, line) );
+    }
+    else if ( line < SYSCFG_EXTILine_8 )
+    {
+        SYSCFG->EXTICR2 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
+                        | ( SYSCFG_EXTICR(port, line) );
+    }
+    else if ( line < SYSCFG_EXTILine_12 )
+    {
+        SYSCFG->EXTICR3 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
+                        | ( SYSCFG_EXTICR(port, line) );
+    }
+    else
+    {
+        SYSCFG->EXTICR4 = ( SYSCFG->EXTICR1 & ~ SYSCFG_EXTICR_MASK(line) )
+                        | ( SYSCFG_EXTICR(port, line) );
+    }
+}
+
+void SYSCFG_SetI2C0PortMode(SYSCFG_I2CPortMode_Type mode)
+{
+    SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C1MODESEL_MASK )
+                  | SYSCFG_CFGR2_I2C1MODESEL(mode);
+}
+
+void SYSCFG_SetI2C1PortMode(SYSCFG_I2CPortMode_Type mode)
+{
+    SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_I2C2MODESEL_MASK )
+                  | SYSCFG_CFGR2_I2C2MODESEL(mode);
+}
+
+void SYSCFG_SetENETPortMode(SYSCFG_ENETPortMode_Type mode)
+{
+    SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_MIIRMIISEL_MASK )
+                  | SYSCFG_CFGR2_MIIRMIISEL(mode);
+}
+
+void SYSCFG_SetENETSpeedMode(SYSCFG_ENETSpeedMode_Type mode)
+{
+    SYSCFG->CFGR2 = ( SYSCFG->CFGR2 & ~ SYSCFG_CFGR2_MACSPDSEL_MASK )
+                  | SYSCFG_CFGR2_MACSPDSEL(mode);
+}
+
+void SYSCFG_EnablePVD(SYSCFG_PVDConf_Type * conf)
+{
+    if (conf == NULL)
+    {
+        SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_PVDE_MASK;
+    }
+    else
+    {
+        SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_PVDE_MASK
+                                              | SYSCFG_PDETCSR_PLS_MASK
+                                              | SYSCFG_PDETCSR_PVDO_MASK
+                                              ) )
+                        | SYSCFG_PDETCSR_PLS(conf->Thold)
+                        | SYSCFG_PDETCSR_PVDO(conf->Output)
+                        | SYSCFG_PDETCSR_PVDE_MASK
+                        );
+
+    }
+}
+
+void SYSCFG_EnableVDT(SYSCFG_VDTConf_Type * conf)
+{
+    if (conf == NULL)
+    {
+        SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VDTE_MASK;
+    }
+    else
+    {
+        SYSCFG->PDETCSR = ( ( SYSCFG->PDETCSR & ~ ( SYSCFG_PDETCSR_VDTE_MASK
+                                              | SYSCFG_PDETCSR_VDTLS_MASK
+                                              | SYSCFG_PDETCSR_VDTO_MASK
+                                              ) )
+                        | SYSCFG_PDETCSR_VDTLS(conf->Thold)
+                        | SYSCFG_PDETCSR_VDTO(conf->Output)
+                        | SYSCFG_PDETCSR_VDTE_MASK
+                        );
+    }
+}
+
+void SYSCFG_EnableADCCheckVBatDiv3(bool enable)
+{
+    if (enable)
+    {
+        SYSCFG->PDETCSR |= SYSCFG_PDETCSR_VBATDIV3EN_MASK;
+    }
+    else
+    {
+        SYSCFG->PDETCSR &= ~ SYSCFG_PDETCSR_VBATDIV3EN_MASK;
+    }
+}
+
+void SYSCFG_SetVOSDelayValue(uint32_t val)
+{
+    SYSCFG->VOSDLY = val;
+}
+
+/* EOF. */
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hal_tim_basic.h"
+
+bool TIM_BASIC_Init(TIM_BASIC_Type * TIMx, TIM_BASIC_Init_Type * init)
+{
+    TIMx->CR1 = (TIMx->CR1 & ~(TIM_BASIC_CR1_OPM_MASK | TIM_BASIC_CR1_APRE_MASK) )
+              | TIM_BASIC_CR1_OPM(init->PeriodMode)
+              | ((init->EnablePreloadPeriod) ? TIM_BASIC_CR1_APRE_MASK: 0u)
+              ;
+
+    /* Check StepFreqHz validity. */
+    if ( (init->StepFreqHz == 0u) || (init->StepFreqHz > init->ClockFreqHz) ) 
+    {
+        return false;
+    }
+    /* Calculate prescaler of the timer.*/
+    TIMx->PSC = init->ClockFreqHz / init->StepFreqHz - 1u; 
+    /* Set the period length. */
+    TIMx->ARR = init->Period;
+    return true;
+}
+
+void TIM_BASIC_Start(TIM_BASIC_Type * TIMx)
+{
+    TIMx->CR1 |= TIM_BASIC_CR1_CEN_MASK;
+}
+
+void TIM_BASIC_Stop(TIM_BASIC_Type * TIMx)
+{
+    TIMx->CR1 &= ~TIM_BASIC_CR1_CEN_MASK;
+}
+
+uint32_t TIM_BASIC_GetCounterValue(TIM_BASIC_Type * TIMx)
+{
+    return TIMx->CNT;
+}
+
+void TIM_BASIC_EnableInterrupts(TIM_BASIC_Type *TIMx, uint32_t interrupts, bool enable)
+{
+    if (enable)
+    {
+        TIMx->DIER |= interrupts;
+    }
+    else
+    {
+        TIMx->DIER &= ~interrupts;
+    }
+}
+
+void TIM_BASIC_EnableDMA(TIM_BASIC_Type *TIMx, uint32_t dmas, bool enable)
+{
+    if (enable)
+    {
+        TIMx->DIER |= dmas;
+    }
+    else
+    {
+        TIMx->DIER &= ~dmas;
+    }
+}
+
+void TIM_BASIC_DoSwTrigger(TIM_BASIC_Type *TIMx, uint32_t swtrgs)
+{
+    TIMx->EGR = swtrgs;
+}
+
+uint32_t TIM_BASIC_GetInterruptStatus(TIM_BASIC_Type * TIMx)
+{
+    return TIMx->SR;
+}
+
+void TIM_BASIC_ClearInterruptStatus(TIM_BASIC_Type *TIMx, uint32_t status)
+{
+    TIMx->SR &= ~status;
+}
+
+/* EOF. */
+
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2021 MindMotion Microelectronics Co., Ltd.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hal_uart.h"
+
+void UART_Init(UART_Type * UARTx, UART_Init_Type * init)
+{
+    uint32_t ccr = UARTx->CCR & ~(    UART_CCR_PEN_MASK
+                                    | UART_CCR_PSEL_MASK
+                                    | UART_CCR_SPB0_MASK
+                                    | UART_CCR_CHAR_MASK
+                                    | UART_CCR_SPB1_MASK
+                                 );
+    /* WordLength. */
+    ccr |= UART_CCR_CHAR(init->WordLength);
+
+    /* StopBits. */
+    if ( (init->StopBits == UART_StopBits_2) || (init->StopBits == UART_StopBits_1_5) )
+    {
+        ccr |= UART_CCR_SPB0_MASK;
+    }
+    if ( (init->StopBits == UART_StopBits_0_5) || (init->StopBits == UART_StopBits_1_5) )
+    {
+        ccr |= UART_CCR_SPB1_MASK;
+    }
+
+    /* Parity. */
+    if (init->Parity == UART_Parity_Even)
+    {
+        ccr |= UART_CCR_PEN_MASK;
+    }
+    if (init->Parity == UART_Parity_Odd)
+    {
+        ccr |= UART_CCR_PEN_MASK | UART_CCR_PSEL_MASK;
+    }
+    UARTx->CCR = ccr;
+
+    /* XferMode. */
+    uint32_t gcr = UARTx->GCR & ~(   UART_GCR_RXEN_MASK
+                                   | UART_GCR_TXEN_MASK
+                                   | UART_GCR_AUTOFLOWEN_MASK
+                                 );
+    gcr |= ((uint32_t)(init->XferMode) << UART_GCR_RXEN_SHIFT);
+    if (init->HwFlowControl == UART_HwFlowControl_RTS_CTS)
+    {
+        gcr |= UART_GCR_AUTOFLOWEN_MASK;
+    }
+    UARTx->GCR = gcr;
+
+    /* Setup the baudrate. */
+    UARTx->BRR = (init->ClockFreqHz / init->BaudRate) / 16u;
+    UARTx->FRA = (init->ClockFreqHz / init->BaudRate) % 16u;
+}
+
+void UART_Enable(UART_Type * UARTx, bool enable)
+{
+    if (enable)
+    {
+        UARTx->GCR |= UART_GCR_UARTEN_MASK;
+    }
+    else
+    {
+        UARTx->GCR &= ~UART_GCR_UARTEN_MASK;
+    }
+}
+
+void UART_EnableInterrupts(UART_Type * UARTx, uint32_t interrupts, bool enable)
+{
+    (enable) ? (UARTx->IER |= interrupts) : (UARTx->IER &= ~interrupts);
+}
+
+uint32_t UART_GetEnabledInterrupts(UART_Type * UARTx)
+{
+    return UARTx->IER;
+}
+
+void UART_EnableDMA(UART_Type * UARTx, bool enable)
+{
+    if (enable)
+    {
+        UARTx->GCR |= UART_GCR_DMAMODE_MASK;
+    }
+    else
+    {
+        UARTx->GCR &= ~UART_GCR_DMAMODE_MASK;
+    }
+}
+
+void UART_PutData(UART_Type * UARTx, uint8_t value)
+{
+    UARTx->TDR = value;
+}
+
+uint8_t UART_GetData(UART_Type * UARTx)
+{
+    return (uint8_t)(UARTx->RDR & 0xFFU);
+}
+
+/* return flags */
+uint32_t UART_GetStatus(UART_Type * UARTx)
+{
+    return UARTx->CSR;
+}
+
+/* return flags. */
+uint32_t UART_GetInterruptStatus(UART_Type * UARTx)
+{
+    return UARTx->ISR;
+}
+
+void UART_ClearInterruptStatus(UART_Type * UARTx, uint32_t interrupts)
+{
+    UARTx->ICR = interrupts;
+}
+
+uint32_t   UART_GetRxDataRegAddr(UART_Type * UARTx)
+{
+    return (uint32_t)(&(UARTx->RDR));
+}
+
+uint32_t   UART_GetTxDataRegAddr(UART_Type * UARTx)
+{
+    return (uint32_t)(&(UARTx->TDR));
+}
+
+/* EOF. */
--- a/Show More
+++ b/Show More