mirror of
https://github.com/RT-Thread/rt-thread.git
synced 2026-02-06 17:12:01 +08:00
[bsp][hc32] support hc32f448
This commit is contained in:
skllii
GitHub
1
.github/workflows/bsp_buildings.yml
vendored
1
.github/workflows/bsp_buildings.yml
vendored
@@ -76,6 +76,7 @@ jobs:
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||||
- "at32/at32f437-start"
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- "yichip/yc3122-pos"
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- "hc32/ev_hc32f4a0_lqfp176"
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- "hc32/ev_hc32f448_lqfp80"
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- "hc32/ev_hc32f460_lqfp100_v2"
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- "hc32l196"
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- "mm32/mm32f3270-100ask-pitaya"
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@@ -9,6 +9,7 @@ HC32 系列 BSP 目前支持情况如下表所示：
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| **F4 系列** | |
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||||
| [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 |
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| [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 |
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| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 |
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| **M1 系列** | |
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| **M4 系列** | |
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1095
bsp/hc32/ev_hc32f448_lqfp80/.config
Normal file
1095
bsp/hc32/ev_hc32f448_lqfp80/.config
Normal file
File diff suppressed because it is too large
Load Diff
214
bsp/hc32/ev_hc32f448_lqfp80/.cproject
Normal file
214
bsp/hc32/ev_hc32f448_lqfp80/.cproject
Normal file
File diff suppressed because one or more lines are too long
42
bsp/hc32/ev_hc32f448_lqfp80/.gitignore
vendored
Normal file
42
bsp/hc32/ev_hc32f448_lqfp80/.gitignore
vendored
Normal file
@@ -0,0 +1,42 @@
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*.pyc
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*.map
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*.dblite
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*.elf
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*.bin
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*.hex
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*.axf
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*.exe
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*.pdb
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*.idb
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*.ilk
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*.old
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build
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Debug
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documentation/html
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packages/
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*~
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*.o
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*.obj
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*.out
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*.bak
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*.dep
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||||
*.lib
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*.i
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*.d
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.DS_Stor*
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.config 3
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.config 4
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.config 5
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Midea-X1
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*.uimg
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GPATH
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GRTAGS
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GTAGS
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.vscode
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JLinkLog.txt
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||||
JLinkSettings.ini
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DebugConfig/
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RTE/
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settings/
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*.uvguix*
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cconfig.h
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68
bsp/hc32/ev_hc32f448_lqfp80/.project
Normal file
68
bsp/hc32/ev_hc32f448_lqfp80/.project
Normal file
@@ -0,0 +1,68 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>project</name>
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<comment />
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<projects>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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<triggers>clean,full,incremental,</triggers>
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<arguments>
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</arguments>
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</buildCommand>
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<buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
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<triggers>full,incremental,</triggers>
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<arguments>
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</arguments>
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||||
</buildCommand>
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</buildSpec>
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<natures>
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<nature>org.eclipse.cdt.core.cnature</nature>
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<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
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||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
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</natures>
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<linkedResources>
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<link>
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<name>rt-thread</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/components</name>
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<type>2</type>
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<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/components</locationURI>
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</link>
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<link>
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<name>rt-thread/include</name>
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<type>2</type>
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<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/include</locationURI>
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</link>
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<link>
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||||
<name>rt-thread/libcpu</name>
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<type>2</type>
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||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/libcpu</locationURI>
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</link>
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<link>
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<name>rt-thread/src</name>
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<type>2</type>
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||||
<locationURI>$%7BPARENT-3-PROJECT_LOC%7D/src</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>rt-thread/bsp/hc32/libraries</name>
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<type>2</type>
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||||
<locationURI>$%7BPARENT-1-PROJECT_LOC%7D/libraries</locationURI>
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</link>
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</linkedResources>
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</projectDescription>
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21
bsp/hc32/ev_hc32f448_lqfp80/Kconfig
Normal file
21
bsp/hc32/ev_hc32f448_lqfp80/Kconfig
Normal file
@@ -0,0 +1,21 @@
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mainmenu "RT-Thread Configuration"
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config BSP_DIR
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string
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option env="BSP_ROOT"
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default "."
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config RTT_DIR
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string
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option env="RTT_ROOT"
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default "../../.."
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config PKGS_DIR
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string
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||||
option env="PKGS_ROOT"
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default "packages"
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source "$RTT_DIR/Kconfig"
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source "$PKGS_DIR/Kconfig"
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source "../libraries/Kconfig"
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source "board/Kconfig"
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128
bsp/hc32/ev_hc32f448_lqfp80/README.md
Normal file
128
bsp/hc32/ev_hc32f448_lqfp80/README.md
Normal file
@@ -0,0 +1,128 @@
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# XHSC EV_F448_LQ80_Rev1.0 开发板 BSP 说明
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## 简介
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本文档为小华半导体为 EV_F448_LQ80_Rev1.0 开发板提供的 BSP (板级支持包) 说明。
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主要内容如下：
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- 开发板资源介绍
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- BSP 快速上手
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||||
- 进阶使用方法
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||||
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||||
通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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||||
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||||
## 开发板介绍
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||||
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EV_F448_LQ80_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F448MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F448MCTI 的芯片性能。
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开发板外观如下图所示：
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||||
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||||
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EV_F448_LQ80_Rev1.0 开发板常用 **板载资源** 如下：
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- **MCU**
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- HC32F448MCTI
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- 主频200MHz
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- 256KB FLASH
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- 68KB RAM
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- **外部Memory**
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- BL24C256（EEPROM, 256Kbits）
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- W25Q64（SPI NOR，64MB）
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- IS62WV51216（SRAM， 1MB）
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- **常用外设**
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- LED: 4 个，User LED（LED0，LED1，LED2，LED3）。
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- 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0）
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- **常用接口**
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- USB转串口
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- CAN DB9接口 * 2
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- TFT接口
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- SmartCard接口
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||||
- I2C/USART/SPI接口
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||||
- **调试接口**
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||||
- 板载DAP调试器
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||||
- 标准JTAG/SWD/Trace
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||||
|
||||
开发板更多详细信息请参考小华半导体半导体[EV_F448_LQ80_Rev1.0](https://www.xhsc.com.cn)
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||||
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||||
## 外设支持
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||||
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||||
本 BSP 目前对外设的支持情况如下：
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||||
| **板载外设** | **支持情况** | **备注** |
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| :------------ | :-----------: | :-----------------------------------: |
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| USB 转串口 | 支持 | 使用 UART2 |
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| LED | 支持 | LED1~4 |
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| **片上外设** | **支持情况** | **备注** |
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| :------------ | :-----------: | :-----------------------------------: |
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| ADC | 支持 | ADC1: CH10, CH11, <br>ADC3: CH1 |
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| CAN | 支持 | CAN1、CAN2 |
|
||||
| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 |
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| I2C | 支持 | 软件模拟<br>硬件I2C1~2<br>I2C1支持EEPROM（BL24C256） |
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| Hwtimer | 支持 | Hwtimer1~5 |
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| SPI | 支持 | SPI1~3<br>SPI1支持W25Q |
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| UART | 支持 | UART1~6<br>UART2为console使用 |
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||||
|
||||
|
||||
## 使用说明
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||||
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||||
使用说明分为如下两个章节：
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||||
|
||||
- 快速上手
|
||||
|
||||
本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
|
||||
|
||||
- 进阶使用
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||||
|
||||
本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
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|
||||
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### 快速上手
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||||
|
||||
本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
|
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|
||||
#### 硬件连接
|
||||
|
||||
使用Type-A to MircoUSB线连接开发板和PC供电。
|
||||
|
||||
#### 编译下载
|
||||
|
||||
双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。
|
||||
|
||||
> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。
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||||
|
||||
#### 运行结果
|
||||
|
||||
下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。
|
||||
|
||||
USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息:
|
||||
|
||||
```
|
||||
\ | /
|
||||
- RT - Thread Operating System
|
||||
/ | \ 5.0.1 build Feb 4 2024 16:44:26
|
||||
2006 - 2022 Copyright by RT-Thread team
|
||||
msh >
|
||||
```
|
||||
|
||||
### 进阶使用
|
||||
|
||||
此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下：
|
||||
|
||||
1. 在 bsp 下打开 env 工具。
|
||||
|
||||
2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
|
||||
|
||||
3. 输入`pkgs --update`命令更新软件包。
|
||||
|
||||
4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
|
||||
|
||||
## 注意事项
|
||||
无
|
||||
## 联系人信息
|
||||
|
||||
维护人:
|
||||
|
||||
- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱：<xhsc_mcu@xhsc.com.cn>
|
||||
15
bsp/hc32/ev_hc32f448_lqfp80/SConscript
Normal file
15
bsp/hc32/ev_hc32f448_lqfp80/SConscript
Normal file
@@ -0,0 +1,15 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
list = os.listdir(cwd)
|
||||
|
||||
for d in list:
|
||||
path = os.path.join(cwd, d)
|
||||
if os.path.isfile(os.path.join(path, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(d, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
62
bsp/hc32/ev_hc32f448_lqfp80/SConstruct
Normal file
62
bsp/hc32/ev_hc32f448_lqfp80/SConstruct
Normal file
@@ -0,0 +1,62 @@
|
||||
import os
|
||||
import sys
|
||||
import rtconfig
|
||||
|
||||
if os.getenv('RTT_ROOT'):
|
||||
RTT_ROOT = os.getenv('RTT_ROOT')
|
||||
else:
|
||||
RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
|
||||
|
||||
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
|
||||
try:
|
||||
from building import *
|
||||
except:
|
||||
print('Cannot found RT-Thread root directory, please check RTT_ROOT')
|
||||
print(RTT_ROOT)
|
||||
exit(-1)
|
||||
|
||||
TARGET = 'rtthread.' + rtconfig.TARGET_EXT
|
||||
|
||||
DefaultEnvironment(tools=[])
|
||||
env = Environment(tools = ['mingw'],
|
||||
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
|
||||
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
|
||||
AR = rtconfig.AR, ARFLAGS = '-rc',
|
||||
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
|
||||
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
|
||||
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
|
||||
|
||||
if rtconfig.PLATFORM in ['iccarm']:
|
||||
env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
|
||||
env.Replace(ARFLAGS = [''])
|
||||
env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map')
|
||||
|
||||
Export('RTT_ROOT')
|
||||
Export('rtconfig')
|
||||
|
||||
SDK_ROOT = os.path.abspath('./')
|
||||
|
||||
if os.path.exists(SDK_ROOT + '/libraries'):
|
||||
libraries_path_prefix = SDK_ROOT + '/libraries'
|
||||
else:
|
||||
libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
|
||||
|
||||
SDK_LIB = libraries_path_prefix
|
||||
Export('SDK_LIB')
|
||||
|
||||
# prepare building environment
|
||||
objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
|
||||
|
||||
hc32_library = 'hc32f448_ddl'
|
||||
rtconfig.BSP_LIBRARY_TYPE = hc32_library
|
||||
|
||||
# include libraries
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript')))
|
||||
|
||||
# include drivers
|
||||
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript')))
|
||||
|
||||
objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript')))
|
||||
|
||||
# make a building
|
||||
DoBuilding(TARGET, objs)
|
||||
15
bsp/hc32/ev_hc32f448_lqfp80/applications/SConscript
Normal file
15
bsp/hc32/ev_hc32f448_lqfp80/applications/SConscript
Normal file
@@ -0,0 +1,15 @@
|
||||
from building import *
|
||||
import os
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
src = Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
group = group + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('group')
|
||||
32
bsp/hc32/ev_hc32f448_lqfp80/applications/main.c
Normal file
32
bsp/hc32/ev_hc32f448_lqfp80/applications/main.c
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2024, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
/* defined the LED_GREEN pin: PA2 */
|
||||
#define LED_GREEN_PIN GET_PIN(A, 2)
|
||||
|
||||
int main(void)
|
||||
{
|
||||
/* set LED_GREEN_PIN pin mode to output */
|
||||
rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT);
|
||||
|
||||
while (1)
|
||||
{
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_HIGH);
|
||||
rt_thread_mdelay(500);
|
||||
rt_pin_write(LED_GREEN_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
|
||||
99
bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c
Normal file
99
bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c
Normal file
@@ -0,0 +1,99 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <board.h>
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
|
||||
#define XTAL32_FCM_THREAD_STACK_SIZE (1024)
|
||||
|
||||
/**
|
||||
* @brief This thread is used to monitor whether XTAL32 is stable.
|
||||
* This thread only runs once after the system starts.
|
||||
* When stability is detected or 2s times out, the thread will end.
|
||||
* (When a timeout occurs it will be prompted via rt_kprintf)
|
||||
*/
|
||||
void xtal32_fcm_thread_entry(void *parameter)
|
||||
{
|
||||
stc_fcm_init_t stcFcmInit;
|
||||
uint32_t u32TimeOut = 0UL;
|
||||
uint32_t u32Time = 200UL; /* 200*10ms = 2s */
|
||||
|
||||
/* FCM config */
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE);
|
||||
(void)FCM_StructInit(&stcFcmInit);
|
||||
stcFcmInit.u32RefClock = FCM_REF_CLK_MRC;
|
||||
stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */
|
||||
stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING;
|
||||
stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32;
|
||||
stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1;
|
||||
stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL);
|
||||
stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL);
|
||||
(void)FCM_Init(&stcFcmInit);
|
||||
/* Enable FCM, to ensure xtal32 stable */
|
||||
FCM_Cmd(ENABLE);
|
||||
|
||||
while (1)
|
||||
{
|
||||
if (SET == FCM_GetStatus(FCM_FLAG_END))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_END);
|
||||
if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF)))
|
||||
{
|
||||
FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF);
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
/* XTAL32 stabled */
|
||||
break;
|
||||
}
|
||||
}
|
||||
u32TimeOut++;
|
||||
if (u32TimeOut > u32Time)
|
||||
{
|
||||
(void)FCM_DeInit();
|
||||
FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE);
|
||||
rt_kprintf("Error: XTAL32 still unstable, timeout.\n");
|
||||
break;
|
||||
}
|
||||
rt_thread_mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
int xtal32_fcm_thread_create(void)
|
||||
{
|
||||
rt_thread_t tid;
|
||||
|
||||
tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL,
|
||||
XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10);
|
||||
if (tid != RT_NULL)
|
||||
{
|
||||
rt_thread_startup(tid);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_kprintf("create xtal32_fcm thread err!");
|
||||
}
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_APP_EXPORT(xtal32_fcm_thread_create);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
652
bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig
Normal file
652
bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig
Normal file
File diff suppressed because it is too large
Load Diff
37
bsp/hc32/ev_hc32f448_lqfp80/board/SConscript
Normal file
37
bsp/hc32/ev_hc32f448_lqfp80/board/SConscript
Normal file
@@ -0,0 +1,37 @@
|
||||
import os
|
||||
import rtconfig
|
||||
from building import *
|
||||
|
||||
Import('SDK_LIB')
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add general drivers
|
||||
src = Split('''
|
||||
board.c
|
||||
board_config.c
|
||||
''')
|
||||
|
||||
if GetDepend(['BSP_USING_TCA9539']):
|
||||
src += Glob('ports/tca9539.c')
|
||||
|
||||
if GetDepend(['BSP_USING_SPI_FLASH']):
|
||||
src += Glob('ports/drv_spi_flash.c')
|
||||
|
||||
path = [cwd]
|
||||
path += [cwd + '/ports']
|
||||
path += [cwd + '/config']
|
||||
|
||||
startup_path_prefix = SDK_LIB
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc']:
|
||||
src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S']
|
||||
elif rtconfig.PLATFORM in ['armcc', 'armclang']:
|
||||
src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s']
|
||||
elif rtconfig.PLATFORM in ['iccarm']:
|
||||
src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s']
|
||||
|
||||
CPPDEFINES = ['HC32F448', '__DEBUG']
|
||||
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
113
bsp/hc32/ev_hc32f448_lqfp80/board/board.c
Normal file
113
bsp/hc32/ev_hc32f448_lqfp80/board/board.c
Normal file
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "board_config.h"
|
||||
|
||||
/* unlock/lock peripheral */
|
||||
#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
|
||||
LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
|
||||
#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
|
||||
|
||||
/** System Base Configuration
|
||||
*/
|
||||
void SystemBase_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE)
|
||||
EFM_ICacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE)
|
||||
EFM_DCacheCmd(ENABLE);
|
||||
#endif
|
||||
#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH)
|
||||
EFM_PrefetchCmd(ENABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** System Clock Configuration
|
||||
*/
|
||||
void SystemClock_Config(void)
|
||||
{
|
||||
stc_clock_xtal_init_t stcXtalInit;
|
||||
stc_clock_pll_init_t stcPLLHInit;
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
stc_clock_xtal32_init_t stcXtal32Init;
|
||||
#endif
|
||||
|
||||
/* PCLK0, HCLK Max 200MHz */
|
||||
/* PCLK1, PCLK4 Max 100MHz */
|
||||
/* PCLK2, EXCLK Max 60MHz */
|
||||
/* PCLK3 Max 50MHz */
|
||||
CLK_SetClockDiv(CLK_BUS_CLK_ALL,
|
||||
(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 |
|
||||
CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 |
|
||||
CLK_HCLK_DIV1));
|
||||
|
||||
GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE);
|
||||
(void)CLK_XtalStructInit(&stcXtalInit);
|
||||
/* Config Xtal and enable Xtal */
|
||||
stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
|
||||
stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
|
||||
stcXtalInit.u8State = CLK_XTAL_ON;
|
||||
stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
|
||||
(void)CLK_XtalInit(&stcXtalInit);
|
||||
|
||||
(void)CLK_PLLStructInit(&stcPLLHInit);
|
||||
/* VCO = (8/1)*100 = 800MHz*/
|
||||
stcPLLHInit.u8PLLState = CLK_PLL_ON;
|
||||
stcPLLHInit.PLLCFGR = 0UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
|
||||
stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
|
||||
(void)CLK_PLLInit(&stcPLLHInit);
|
||||
|
||||
/* 3 cycles for 150 ~ 200MHz */
|
||||
(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE3);
|
||||
/* 3 cycles for 150 ~ 200MHz */
|
||||
GPIO_SetReadWaitCycle(GPIO_RD_WAIT3);
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
|
||||
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
/* Xtal32 config */
|
||||
GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE);
|
||||
(void)CLK_Xtal32StructInit(&stcXtal32Init);
|
||||
stcXtal32Init.u8State = CLK_XTAL32_ON;
|
||||
stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH;
|
||||
stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD;
|
||||
(void)CLK_Xtal32Init(&stcXtal32Init);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Clock Configuration
|
||||
*/
|
||||
void PeripheralClock_Config(void)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1)
|
||||
CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
#if defined(BSP_USING_CAN2)
|
||||
CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6);
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK);
|
||||
#endif
|
||||
}
|
||||
|
||||
/** Peripheral Registers Unlock
|
||||
*/
|
||||
void PeripheralRegister_Unlock(void)
|
||||
{
|
||||
LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
|
||||
}
|
||||
54
bsp/hc32/ev_hc32f448_lqfp80/board/board.h
Normal file
54
bsp/hc32/ev_hc32f448_lqfp80/board/board.h
Normal file
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __BOARD_H__
|
||||
#define __BOARD_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_gpio.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024)
|
||||
#define HC32_FLASH_SIZE (256 * 1024)
|
||||
#define HC32_FLASH_START_ADDRESS (0)
|
||||
#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE)
|
||||
|
||||
#define HC32_SRAM_SIZE (64)
|
||||
#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024)
|
||||
|
||||
#ifdef __ARMCC_VERSION
|
||||
extern int Image$$RW_IRAM2$$ZI$$Limit;
|
||||
#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit)
|
||||
#elif __ICCARM__
|
||||
#pragma section="HEAP"
|
||||
#define HEAP_BEGIN (__segment_end("HEAP"))
|
||||
#else
|
||||
extern int __bss_end;
|
||||
#define HEAP_BEGIN (&__bss_end)
|
||||
#endif
|
||||
|
||||
#define HEAP_END HC32_SRAM_END
|
||||
|
||||
void PeripheralRegister_Unlock(void);
|
||||
void PeripheralClock_Config(void);
|
||||
void SystemBase_Config(void);
|
||||
void SystemClock_Config(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
497
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c
Normal file
497
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c
Normal file
@@ -0,0 +1,497 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtdevice.h>
|
||||
#include "board_config.h"
|
||||
#include "tca9539.h"
|
||||
|
||||
/**
|
||||
* The below functions will initialize HC32 board.
|
||||
*/
|
||||
|
||||
#if defined RT_USING_SERIAL
|
||||
rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)USARTx)
|
||||
{
|
||||
#if defined(BSP_USING_UART1)
|
||||
case (rt_uint32_t)CM_USART1:
|
||||
/* Configure USART RX/TX pin. */
|
||||
GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC);
|
||||
GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_UART2)
|
||||
case (rt_uint32_t)CM_USART2:
|
||||
/* Configure USART RX/TX pin. */
|
||||
GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC);
|
||||
GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_UART6)
|
||||
case (rt_uint32_t)CM_USART6:
|
||||
/* Configure USART RX/TX pin. */
|
||||
GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC);
|
||||
GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_I2C)
|
||||
rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
|
||||
switch ((rt_uint32_t)I2Cx)
|
||||
{
|
||||
#if defined(BSP_USING_I2C1)
|
||||
case (rt_uint32_t)CM_I2C1:
|
||||
/* Configure I2C1 SDA/SCL pin. */
|
||||
GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC);
|
||||
GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_I2C2) // TODO, ch2 for test only
|
||||
case (rt_uint32_t)CM_I2C2:
|
||||
/* Configure I2C2 SDA/SCL pin. */
|
||||
GPIO_SetFunc(I2C2_SDA_PORT, I2C2_SDA_PIN, I2C2_SDA_FUNC);
|
||||
GPIO_SetFunc(I2C2_SCL_PORT, I2C2_SCL_PIN, I2C2_SCL_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_ADC)
|
||||
rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
switch ((rt_uint32_t)ADCx)
|
||||
{
|
||||
#if defined(BSP_USING_ADC1)
|
||||
case (rt_uint32_t)CM_ADC1:
|
||||
(void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_ADC2)
|
||||
case (rt_uint32_t)CM_ADC2:
|
||||
(void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_ADC3)
|
||||
case (rt_uint32_t)CM_ADC3:
|
||||
(void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_DAC)
|
||||
rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG;
|
||||
switch ((rt_uint32_t)DACx)
|
||||
{
|
||||
#if defined(BSP_USING_DAC1)
|
||||
case (rt_uint32_t)CM_DAC1:
|
||||
(void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_CAN)
|
||||
void CanPhyEnable(void)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1)
|
||||
TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET);
|
||||
TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT);
|
||||
#endif
|
||||
#if defined(BSP_USING_CAN2)
|
||||
TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET);
|
||||
TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT);
|
||||
#endif
|
||||
}
|
||||
rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
|
||||
switch ((rt_uint32_t)CANx)
|
||||
{
|
||||
#if defined(BSP_USING_CAN1)
|
||||
case (rt_uint32_t)CM_CAN1:
|
||||
GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_CAN2)
|
||||
case (rt_uint32_t)CM_CAN2:
|
||||
GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC);
|
||||
GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if defined (RT_USING_SPI)
|
||||
rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
#if defined(BSP_USING_SPI1)
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
#endif
|
||||
|
||||
switch ((rt_uint32_t)CM_SPIx)
|
||||
{
|
||||
#if defined(BSP_USING_SPI1)
|
||||
case (rt_uint32_t)CM_SPI1:
|
||||
GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinState = PIN_STAT_SET;
|
||||
stcGpioInit.u16PinDir = PIN_DIR_OUT;
|
||||
GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit);
|
||||
GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit);
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS;
|
||||
(void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC);
|
||||
GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC);
|
||||
GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PWM)
|
||||
#if defined(BSP_USING_PWM_TMRA)
|
||||
rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMRAx)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
case (rt_uint32_t)CM_TMRA_1:
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_1_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2)
|
||||
case (rt_uint32_t)CM_TMRA_2:
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH1
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH2
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH3
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMRA_2_CH4
|
||||
GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMR4)
|
||||
rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMR4x)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMR4_1)
|
||||
case (rt_uint32_t)CM_TMR4_1:
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OUH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OUL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OVH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OVL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OWH
|
||||
GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR4_1_OWL
|
||||
GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMR6)
|
||||
rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x)
|
||||
{
|
||||
rt_err_t result = RT_EOK;
|
||||
switch ((rt_uint32_t)TMR6x)
|
||||
{
|
||||
#if defined(BSP_USING_PWM_TMR6_1)
|
||||
case (rt_uint32_t)CM_TMR6_1:
|
||||
#ifdef BSP_USING_PWM_TMR6_1_A
|
||||
GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC);
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM_TMR6_1_B
|
||||
GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC);
|
||||
#endif
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = -RT_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef RT_USING_PM
|
||||
#define EFM_ERASE_TIME_MAX_IN_MILLISECOND (20)
|
||||
#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
|
||||
|
||||
static void _pm_sleep_common_init(rt_bool_t b_disable_unused_clk)
|
||||
{
|
||||
CLK_Xtal32Cmd(ENABLE);
|
||||
|
||||
rt_tick_t tick_start = rt_tick_get_millisecond();
|
||||
rt_err_t rt_stat = RT_EOK;
|
||||
//wait flash idle
|
||||
while (SET != EFM_GetStatus(EFM_FLAG_RDY))
|
||||
{
|
||||
if (rt_tick_get_millisecond() - tick_start > EFM_ERASE_TIME_MAX_IN_MILLISECOND)
|
||||
{
|
||||
rt_stat = RT_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
RT_ASSERT(rt_stat == RT_EOK);
|
||||
|
||||
if (b_disable_unused_clk)
|
||||
{
|
||||
uint32_t cur_clk_src = READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW);
|
||||
|
||||
switch (cur_clk_src)
|
||||
{
|
||||
case CLK_SYSCLK_SRC_HRC:
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_MrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
CLK_XtalCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL, DISABLE);
|
||||
break;
|
||||
case CLK_SYSCLK_SRC_MRC:
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_HrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
CLK_XtalCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
case CLK_SYSCLK_SRC_XTAL:
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_HrcCmd(DISABLE);
|
||||
CLK_MrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
case CLK_SYSCLK_SRC_XTAL32:
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_HrcCmd(DISABLE);
|
||||
CLK_MrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
CLK_XtalCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
case CLK_SYSCLK_SRC_PLL:
|
||||
if (CLK_PLL_SRC_XTAL == PLL_SRC)
|
||||
{
|
||||
CLK_HrcCmd(DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
CLK_XtalCmd(DISABLE);
|
||||
}
|
||||
CLK_MrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_HRC, DISABLE);
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_board_pm_sleep_deep_init(void)
|
||||
{
|
||||
#if (PM_SLEEP_DEEP_CFG_CLK == PWC_STOP_CLK_KEEP)
|
||||
_pm_sleep_common_init(RT_TRUE);
|
||||
#else
|
||||
_pm_sleep_common_init(RT_FALSE);
|
||||
CLK_PLLCmd(DISABLE);
|
||||
CLK_HrcCmd(DISABLE);
|
||||
CLK_LrcCmd(DISABLE);
|
||||
CLK_XtalCmd(DISABLE);
|
||||
PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE);
|
||||
#endif
|
||||
}
|
||||
|
||||
void rt_hw_board_pm_sleep_shutdown_init(void)
|
||||
{
|
||||
_pm_sleep_common_init(RT_TRUE);
|
||||
}
|
||||
|
||||
void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode)
|
||||
{
|
||||
switch (run_mode)
|
||||
{
|
||||
case PM_RUN_MODE_HIGH_SPEED:
|
||||
case PM_RUN_MODE_NORMAL_SPEED:
|
||||
SystemClock_Config();
|
||||
break;
|
||||
|
||||
case PM_RUN_MODE_LOW_SPEED:
|
||||
CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_QSPI)
|
||||
rt_err_t rt_hw_qspi_board_init(void)
|
||||
{
|
||||
stc_gpio_init_t stcGpioInit;
|
||||
|
||||
(void)GPIO_StructInit(&stcGpioInit);
|
||||
stcGpioInit.u16PinDrv = PIN_HIGH_DRV;
|
||||
#ifndef BSP_QSPI_USING_SOFT_CS
|
||||
(void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC);
|
||||
#endif
|
||||
(void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit);
|
||||
(void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit);
|
||||
GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC);
|
||||
GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC);
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
|
||||
rt_err_t rt_hw_board_pulse_encoder_tmra_init(void)
|
||||
{
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC);
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC);
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
|
||||
rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void)
|
||||
{
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC);
|
||||
GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC);
|
||||
#endif
|
||||
return RT_EOK;
|
||||
}
|
||||
#endif
|
||||
310
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h
Normal file
310
bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h
Normal file
@@ -0,0 +1,310 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __BOARD_CONFIG_H__
|
||||
#define __BOARD_CONFIG_H__
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include "hc32_ll.h"
|
||||
#include "drv_config.h"
|
||||
|
||||
|
||||
/************************* XTAL port **********************/
|
||||
#define XTAL_PORT (GPIO_PORT_H)
|
||||
#define XTAL_IN_PIN (GPIO_PIN_00)
|
||||
#define XTAL_OUT_PIN (GPIO_PIN_01)
|
||||
|
||||
/************************ USART port **********************/
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define USART1_RX_PORT (GPIO_PORT_A)
|
||||
#define USART1_RX_PIN (GPIO_PIN_10)
|
||||
#define USART1_RX_FUNC (GPIO_FUNC_33)
|
||||
|
||||
#define USART1_TX_PORT (GPIO_PORT_A)
|
||||
#define USART1_TX_PIN (GPIO_PIN_09)
|
||||
#define USART1_TX_FUNC (GPIO_FUNC_32)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#define USART2_RX_PORT (GPIO_PORT_C)
|
||||
#define USART2_RX_PIN (GPIO_PIN_11)
|
||||
#define USART2_RX_FUNC (GPIO_FUNC_37)
|
||||
|
||||
#define USART2_TX_PORT (GPIO_PORT_C)
|
||||
#define USART2_TX_PIN (GPIO_PIN_10)
|
||||
#define USART2_TX_FUNC (GPIO_FUNC_36)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#define USART6_RX_PORT (GPIO_PORT_D)
|
||||
#define USART6_RX_PIN (GPIO_PIN_01)
|
||||
#define USART6_RX_FUNC (GPIO_FUNC_55)
|
||||
|
||||
#define USART6_TX_PORT (GPIO_PORT_D)
|
||||
#define USART6_TX_PIN (GPIO_PIN_02)
|
||||
#define USART6_TX_FUNC (GPIO_FUNC_54)
|
||||
#endif
|
||||
|
||||
/************************ I2C port **********************/
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#define I2C1_SDA_PORT (GPIO_PORT_E)
|
||||
#define I2C1_SDA_PIN (GPIO_PIN_00)
|
||||
#define I2C1_SDA_FUNC (GPIO_FUNC_48)
|
||||
|
||||
#define I2C1_SCL_PORT (GPIO_PORT_E)
|
||||
#define I2C1_SCL_PIN (GPIO_PIN_01)
|
||||
#define I2C1_SCL_FUNC (GPIO_FUNC_49)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C2) // TODO, ch2 for test only
|
||||
#define I2C2_SDA_PORT (GPIO_PORT_A)
|
||||
#define I2C2_SDA_PIN (GPIO_PIN_09)
|
||||
#define I2C2_SDA_FUNC (GPIO_FUNC_50)
|
||||
|
||||
#define I2C2_SCL_PORT (GPIO_PORT_A)
|
||||
#define I2C2_SCL_PIN (GPIO_PIN_10)
|
||||
#define I2C2_SCL_FUNC (GPIO_FUNC_51)
|
||||
#endif
|
||||
|
||||
|
||||
/*********** ADC configure *********/
|
||||
#if defined(BSP_USING_ADC1)
|
||||
#define ADC1_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC1_CH_PIN (GPIO_PIN_00)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC2)
|
||||
#define ADC2_CH_PORT (GPIO_PORT_C)
|
||||
#define ADC2_CH_PIN (GPIO_PIN_01)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_ADC3)
|
||||
#define ADC3_CH_PORT (GPIO_PORT_E)
|
||||
#define ADC3_CH_PIN (GPIO_PIN_03)
|
||||
#endif
|
||||
|
||||
/*********** DAC configure *********/
|
||||
#if defined(BSP_USING_DAC1)
|
||||
#define DAC1_CH1_PORT (GPIO_PORT_A)
|
||||
#define DAC1_CH1_PIN (GPIO_PIN_04)
|
||||
#define DAC1_CH2_PORT (GPIO_PORT_A)
|
||||
#define DAC1_CH2_PIN (GPIO_PIN_05)
|
||||
#endif
|
||||
|
||||
/*********** CAN configure *********/
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define CAN1_TX_PORT (GPIO_PORT_C)
|
||||
#define CAN1_TX_PIN (GPIO_PIN_12)
|
||||
#define CAN1_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
|
||||
#define CAN1_RX_PORT (GPIO_PORT_D)
|
||||
#define CAN1_RX_PIN (GPIO_PIN_00)
|
||||
#define CAN1_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_CAN2)
|
||||
#define CAN2_TX_PORT (GPIO_PORT_H)
|
||||
#define CAN2_TX_PIN (GPIO_PIN_02)
|
||||
#define CAN2_TX_PIN_FUNC (GPIO_FUNC_56)
|
||||
|
||||
#define CAN2_RX_PORT (GPIO_PORT_E)
|
||||
#define CAN2_RX_PIN (GPIO_PIN_04)
|
||||
#define CAN2_RX_PIN_FUNC (GPIO_FUNC_57)
|
||||
#endif
|
||||
|
||||
/************************* SPI port ***********************/
|
||||
#if defined(BSP_USING_SPI1)
|
||||
#define SPI1_CS_PORT (GPIO_PORT_C)
|
||||
#define SPI1_CS_PIN (GPIO_PIN_07)
|
||||
|
||||
#define SPI1_SCK_PORT (GPIO_PORT_B)
|
||||
#define SPI1_SCK_PIN (GPIO_PIN_14)
|
||||
#define SPI1_SCK_FUNC (GPIO_FUNC_47)
|
||||
|
||||
#define SPI1_MOSI_PORT (GPIO_PORT_B)
|
||||
#define SPI1_MOSI_PIN (GPIO_PIN_13)
|
||||
#define SPI1_MOSI_FUNC (GPIO_FUNC_44)
|
||||
|
||||
#define SPI1_MISO_PORT (GPIO_PORT_D)
|
||||
#define SPI1_MISO_PIN (GPIO_PIN_09)
|
||||
#define SPI1_MISO_FUNC (GPIO_FUNC_45)
|
||||
|
||||
#define SPI1_WP_PORT (GPIO_PORT_D)
|
||||
#define SPI1_WP_PIN (GPIO_PIN_10)
|
||||
|
||||
#define SPI1_HOLD_PORT (GPIO_PORT_D)
|
||||
#define SPI1_HOLD_PIN (GPIO_PIN_11)
|
||||
#endif
|
||||
|
||||
/************************ RTC/PM *****************************/
|
||||
#if defined(BSP_USING_RTC) || defined(RT_USING_PM)
|
||||
#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM)
|
||||
#define XTAL32_PORT (GPIO_PORT_C)
|
||||
#define XTAL32_IN_PIN (GPIO_PIN_14)
|
||||
#define XTAL32_OUT_PIN (GPIO_PIN_15)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(RT_USING_PWM)
|
||||
/*********** PWM_TMRA configure *********/
|
||||
#if defined(BSP_USING_PWM_TMRA_1)
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH1)
|
||||
#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH2)
|
||||
#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09)
|
||||
#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH3)
|
||||
#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_1_CH4)
|
||||
#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11)
|
||||
#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_PWM_TMRA_2)
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH1)
|
||||
#define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00)
|
||||
#define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH2)
|
||||
#define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01)
|
||||
#define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH3)
|
||||
#define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02)
|
||||
#define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMRA_2_CH4)
|
||||
#define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03)
|
||||
#define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********** PWM_TMR4 configure *********/
|
||||
#if defined(BSP_USING_PWM_TMR4_1)
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OUH)
|
||||
#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OUL)
|
||||
#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07)
|
||||
#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OVH)
|
||||
#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09)
|
||||
#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OVL)
|
||||
#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B)
|
||||
#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00)
|
||||
#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OWH)
|
||||
#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10)
|
||||
#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR4_1_OWL)
|
||||
#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B)
|
||||
#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01)
|
||||
#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*********** PWM_TMR6 configure *********/
|
||||
#if defined(BSP_USING_PWM_TMR6_1)
|
||||
#if defined(BSP_USING_PWM_TMR6_1_A)
|
||||
#define PWM_TMR6_1_A_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR6_1_A_PIN (GPIO_PIN_08)
|
||||
#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#if defined(BSP_USING_PWM_TMR6_1_B)
|
||||
#define PWM_TMR6_1_B_PORT (GPIO_PORT_A)
|
||||
#define PWM_TMR6_1_B_PIN (GPIO_PIN_07)
|
||||
#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_QSPI)
|
||||
#ifndef BSP_QSPI_USING_SOFT_CS
|
||||
/* QSSN */
|
||||
#define QSPI_FLASH_CS_PORT (GPIO_PORT_C)
|
||||
#define QSPI_FLASH_CS_PIN (GPIO_PIN_07)
|
||||
#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7)
|
||||
#endif
|
||||
/* QSCK */
|
||||
#define QSPI_FLASH_SCK_PORT (GPIO_PORT_B)
|
||||
#define QSPI_FLASH_SCK_PIN (GPIO_PIN_14)
|
||||
#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7)
|
||||
/* QSIO0 */
|
||||
#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B)
|
||||
#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13)
|
||||
#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7)
|
||||
/* QSIO1 */
|
||||
#define QSPI_FLASH_IO1_PORT (GPIO_PORT_D)
|
||||
#define QSPI_FLASH_IO1_PIN (GPIO_PIN_09)
|
||||
#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7)
|
||||
/* QSIO2 */
|
||||
#define QSPI_FLASH_IO2_PORT (GPIO_PORT_D)
|
||||
#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10)
|
||||
#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7)
|
||||
/* QSIO3 */
|
||||
#define QSPI_FLASH_IO3_PORT (GPIO_PORT_D)
|
||||
#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11)
|
||||
#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7)
|
||||
#endif
|
||||
|
||||
/*********** TMRA_PULSE_ENCODER configure *********/
|
||||
#if defined(RT_USING_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_TMRA_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMRA_1)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08)
|
||||
#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09)
|
||||
#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4)
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */
|
||||
#endif /* BSP_USING_TMRA_PULSE_ENCODER */
|
||||
|
||||
#if defined(BSP_USING_TMR6_PULSE_ENCODER)
|
||||
#if defined(BSP_USING_PULSE_ENCODER_TMR6_1)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_08)
|
||||
#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_A)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_07)
|
||||
#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3)
|
||||
#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */
|
||||
#endif /* BSP_USING_TMR6_PULSE_ENCODER */
|
||||
#endif /* RT_USING_PULSE_ENCODER */
|
||||
|
||||
#endif
|
||||
|
||||
155
bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h
Normal file
155
bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h
Normal file
@@ -0,0 +1,155 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __ADC_CONFIG_H__
|
||||
#define __ADC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_ADC1
|
||||
#ifndef ADC1_INIT_PARAMS
|
||||
#define ADC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc1", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC1_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC1_USING_DMA)
|
||||
#ifndef ADC1_EOCA_DMA_CONFIG
|
||||
#define ADC1_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC1_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC1_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC1_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC1_EOCA, \
|
||||
.flag = ADC1_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC1_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC1_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC1_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC1_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC1_USING_DMA */
|
||||
#endif /* BSP_USING_ADC1 */
|
||||
|
||||
#ifdef BSP_USING_ADC2
|
||||
#ifndef ADC2_INIT_PARAMS
|
||||
#define ADC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc2", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC2_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC2_USING_DMA)
|
||||
#ifndef ADC2_EOCA_DMA_CONFIG
|
||||
#define ADC2_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC2_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC2_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC2_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC2_EOCA, \
|
||||
.flag = ADC2_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC2_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC2_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC2_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC2_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC2_USING_DMA */
|
||||
#endif /* BSP_USING_ADC2 */
|
||||
|
||||
#ifdef BSP_USING_ADC3
|
||||
#ifndef ADC3_INIT_PARAMS
|
||||
#define ADC3_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "adc3", \
|
||||
.vref = 3300, \
|
||||
.resolution = ADC_RESOLUTION_12BIT, \
|
||||
.data_align = ADC_DATAALIGN_RIGHT, \
|
||||
.eoc_poll_time_max = 100, \
|
||||
.hard_trig_enable = RT_FALSE, \
|
||||
.hard_trig_src = ADC_HARDTRIG_EVT0, \
|
||||
.internal_trig0_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig0_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \
|
||||
.internal_trig1_comtrg0_enable = RT_FALSE, \
|
||||
.internal_trig1_comtrg1_enable = RT_FALSE, \
|
||||
.internal_trig1_sel = EVT_SRC_MAX, \
|
||||
.continue_conv_mode_enable = RT_FALSE, \
|
||||
.data_reg_auto_clear = RT_TRUE, \
|
||||
}
|
||||
#endif /* ADC3_INIT_PARAMS */
|
||||
|
||||
#if defined (BSP_ADC3_USING_DMA)
|
||||
#ifndef ADC3_EOCA_DMA_CONFIG
|
||||
#define ADC3_EOCA_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = ADC3_EOCA_DMA_INSTANCE, \
|
||||
.channel = ADC3_EOCA_DMA_CHANNEL, \
|
||||
.clock = ADC3_EOCA_DMA_CLOCK, \
|
||||
.trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_ADC3_EOCA, \
|
||||
.flag = ADC3_EOCA_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = ADC3_EOCA_DMA_IRQn, \
|
||||
.irq_prio = ADC3_EOCA_DMA_INT_PRIO, \
|
||||
.int_src = ADC3_EOCA_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* ADC3_EOCA_DMA_CONFIG */
|
||||
#endif /* BSP_ADC3_USING_DMA */
|
||||
#endif /* BSP_USING_ADC3 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ADC_CONFIG_H__ */
|
||||
139
bsp/hc32/ev_hc32f448_lqfp80/board/config/can_config.h
Normal file
139
bsp/hc32/ev_hc32f448_lqfp80/board/config/can_config.h
Normal file
@@ -0,0 +1,139 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __CAN_CONFIG_H__
|
||||
#define __CAN_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_CAN1
|
||||
#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN1_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN1_NAME ("can1")
|
||||
#ifndef CAN1_INIT_PARAMS
|
||||
#define CAN1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN1_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN1 */
|
||||
|
||||
#ifdef BSP_USING_CAN2
|
||||
#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M)
|
||||
#ifdef RT_CAN_USING_CANFD
|
||||
#define CAN2_CANFD_MODE (CAN_FD_MD_ISO)
|
||||
#endif
|
||||
#define CAN2_NAME ("can2")
|
||||
#ifndef CAN2_INIT_PARAMS
|
||||
#define CAN2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = CAN2_NAME, \
|
||||
.single_trans_mode = RT_FALSE \
|
||||
}
|
||||
#endif /* CAN2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_CAN2 */
|
||||
|
||||
/* Bit time config
|
||||
Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW.
|
||||
|
||||
Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2))
|
||||
TQ = u32Prescaler / CANClock.
|
||||
Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ.
|
||||
|
||||
The following bit time configures are based on CAN Clock 40M
|
||||
*/
|
||||
#define CAN_BIT_TIME_CONFIG_1M_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_800K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 2, \
|
||||
.u32TimeSeg1 = 20, \
|
||||
.u32TimeSeg2 = 5, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_500K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 4, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_250K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 8, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_125K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 16, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_100K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 20, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_50K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 40, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_20K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 100, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#define CAN_BIT_TIME_CONFIG_10K_BAUD \
|
||||
{ \
|
||||
.u32Prescaler = 200, \
|
||||
.u32TimeSeg1 = 16, \
|
||||
.u32TimeSeg2 = 4, \
|
||||
.u32SJW = 4 \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CAN_CONFIG_H__ */
|
||||
|
||||
|
||||
43
bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h
Normal file
43
bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DAC_CONFIG_H__
|
||||
#define __DAC_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_DAC1
|
||||
#ifndef DAC1_INIT_PARAMS
|
||||
#define DAC1_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac1", \
|
||||
}
|
||||
#endif /* DAC1_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC1 */
|
||||
|
||||
#ifdef BSP_USING_DAC2
|
||||
#ifndef DAC2_INIT_PARAMS
|
||||
#define DAC2_INIT_PARAMS \
|
||||
{ \
|
||||
.name = "dac2", \
|
||||
}
|
||||
#endif /* DAC2_INIT_PARAMS */
|
||||
#endif /* BSP_USING_DAC2 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DAC_CONFIG_H__ */
|
||||
263
bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h
Normal file
263
bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h
Normal file
@@ -0,0 +1,263 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DMA_CONFIG_H__
|
||||
#define __DMA_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* DMA1 ch0 */
|
||||
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
|
||||
#define SPI1_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI1_RX_DMA_CHANNEL DMA_CH0
|
||||
#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0
|
||||
#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
|
||||
|
||||
#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
|
||||
#define SPI3_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI3_RX_DMA_CHANNEL DMA_CH0
|
||||
#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0
|
||||
#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0
|
||||
|
||||
#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE)
|
||||
#define I2C1_TX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C1_TX_DMA_CHANNEL DMA_CH0
|
||||
#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0
|
||||
#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM
|
||||
#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO
|
||||
#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0
|
||||
#endif
|
||||
|
||||
/* DMA1 ch1 */
|
||||
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
|
||||
#define SPI1_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI1_TX_DMA_CHANNEL DMA_CH1
|
||||
#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1
|
||||
#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
|
||||
|
||||
#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
|
||||
#define SPI3_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI3_TX_DMA_CHANNEL DMA_CH1
|
||||
#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1
|
||||
#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1
|
||||
|
||||
#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE)
|
||||
#define I2C1_RX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C1_RX_DMA_CHANNEL DMA_CH1
|
||||
#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1
|
||||
#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM
|
||||
#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO
|
||||
#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1
|
||||
#endif
|
||||
|
||||
/* DMA1 ch2 */
|
||||
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
|
||||
#define SPI2_RX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI2_RX_DMA_CHANNEL DMA_CH2
|
||||
#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2
|
||||
#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
|
||||
#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE)
|
||||
#define I2C2_TX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C2_TX_DMA_CHANNEL DMA_CH2
|
||||
#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2
|
||||
#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM
|
||||
#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO
|
||||
#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2
|
||||
#endif
|
||||
|
||||
/* DMA1 ch3 */
|
||||
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
|
||||
#define SPI2_TX_DMA_INSTANCE CM_DMA1
|
||||
#define SPI2_TX_DMA_CHANNEL DMA_CH3
|
||||
#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
|
||||
|
||||
#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE)
|
||||
#define I2C2_RX_DMA_INSTANCE CM_DMA1
|
||||
#define I2C2_RX_DMA_CHANNEL DMA_CH3
|
||||
#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
|
||||
#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE)
|
||||
#define ADC1_EOCA_DMA_INSTANCE CM_DMA1
|
||||
#define ADC1_EOCA_DMA_CHANNEL DMA_CH3
|
||||
#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3
|
||||
#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM
|
||||
#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO
|
||||
#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3
|
||||
|
||||
#endif
|
||||
|
||||
/* DMA1 ch4 */
|
||||
#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
|
||||
#define UART5_RX_DMA_INSTANCE CM_DMA1
|
||||
#define UART5_RX_DMA_CHANNEL DMA_CH4
|
||||
#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4
|
||||
#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4
|
||||
|
||||
#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE)
|
||||
#define ADC2_EOCA_DMA_INSTANCE CM_DMA1
|
||||
#define ADC2_EOCA_DMA_CHANNEL DMA_CH4
|
||||
#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4
|
||||
#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM
|
||||
#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO
|
||||
#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4
|
||||
#endif
|
||||
|
||||
/* DMA1 ch5 */
|
||||
#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
|
||||
#define UART5_TX_DMA_INSTANCE CM_DMA1
|
||||
#define UART5_TX_DMA_CHANNEL DMA_CH5
|
||||
#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5
|
||||
#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5
|
||||
|
||||
#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE)
|
||||
#define ADC3_EOCA_DMA_INSTANCE CM_DMA1
|
||||
#define ADC3_EOCA_DMA_CHANNEL DMA_CH5
|
||||
#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS)
|
||||
#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5
|
||||
#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM
|
||||
#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO
|
||||
#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5
|
||||
#endif
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
|
||||
#define UART1_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART1_RX_DMA_CHANNEL DMA_CH0
|
||||
#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0
|
||||
#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0
|
||||
#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM
|
||||
#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO
|
||||
#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0
|
||||
#endif
|
||||
|
||||
/* DMA2 ch1 */
|
||||
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
|
||||
#define UART1_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART1_TX_DMA_CHANNEL DMA_CH1
|
||||
#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1
|
||||
#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1
|
||||
#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM
|
||||
#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO
|
||||
#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1
|
||||
#endif
|
||||
|
||||
/* DMA2 ch2 */
|
||||
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
|
||||
#define UART2_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART2_RX_DMA_CHANNEL DMA_CH2
|
||||
#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2
|
||||
#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2
|
||||
#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM
|
||||
#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO
|
||||
#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2
|
||||
#endif
|
||||
|
||||
/* DMA2 ch3 */
|
||||
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
|
||||
#define UART2_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART2_TX_DMA_CHANNEL DMA_CH3
|
||||
#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3
|
||||
#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3
|
||||
#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM
|
||||
#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO
|
||||
#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3
|
||||
#endif
|
||||
|
||||
/* DMA2 ch4 */
|
||||
#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
|
||||
#define UART4_RX_DMA_INSTANCE CM_DMA2
|
||||
#define UART4_RX_DMA_CHANNEL DMA_CH4
|
||||
#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4
|
||||
#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4
|
||||
#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM
|
||||
#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO
|
||||
#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4
|
||||
#endif
|
||||
|
||||
/* DMA2 ch5 */
|
||||
#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
|
||||
#define UART4_TX_DMA_INSTANCE CM_DMA2
|
||||
#define UART4_TX_DMA_CHANNEL DMA_CH5
|
||||
#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS)
|
||||
#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5
|
||||
#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5
|
||||
#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM
|
||||
#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO
|
||||
#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __DMA_CONFIG_H__ */
|
||||
176
bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h
Normal file
176
bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h
Normal file
@@ -0,0 +1,176 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __GPIO_CONFIG_H__
|
||||
#define __GPIO_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(RT_USING_PIN)
|
||||
|
||||
#ifndef EXTINT0_IRQ_CONFIG
|
||||
#define EXTINT0_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT0_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT0_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ0, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT1_IRQ_CONFIG
|
||||
#define EXTINT1_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT1_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT1_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ1, \
|
||||
}
|
||||
#endif /* EXTINT1_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT2_IRQ_CONFIG
|
||||
#define EXTINT2_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT2_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT2_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ2, \
|
||||
}
|
||||
#endif /* EXTINT2_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT3_IRQ_CONFIG
|
||||
#define EXTINT3_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT3_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT3_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ3, \
|
||||
}
|
||||
#endif /* EXTINT3_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT4_IRQ_CONFIG
|
||||
#define EXTINT4_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT4_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT4_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ4, \
|
||||
}
|
||||
#endif /* EXTINT4_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT5_IRQ_CONFIG
|
||||
#define EXTINT5_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT5_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT5_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ5, \
|
||||
}
|
||||
#endif /* EXTINT5_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT6_IRQ_CONFIG
|
||||
#define EXTINT6_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT6_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT6_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ6, \
|
||||
}
|
||||
#endif /* EXTINT6_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT7_IRQ_CONFIG
|
||||
#define EXTINT7_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT7_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT7_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ7, \
|
||||
}
|
||||
#endif /* EXTINT7_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT8_IRQ_CONFIG
|
||||
#define EXTINT8_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT8_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT8_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ8, \
|
||||
}
|
||||
#endif /* EXTINT8_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT9_IRQ_CONFIG
|
||||
#define EXTINT9_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT9_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT9_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ9, \
|
||||
}
|
||||
#endif /* EXTINT9_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT10_IRQ_CONFIG
|
||||
#define EXTINT10_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT10_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT10_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ10, \
|
||||
}
|
||||
#endif /* EXTINT10_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT11_IRQ_CONFIG
|
||||
#define EXTINT11_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT11_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT11_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ11, \
|
||||
}
|
||||
#endif /* EXTINT11_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT12_IRQ_CONFIG
|
||||
#define EXTINT12_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT12_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT12_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ12, \
|
||||
}
|
||||
#endif /* EXTINT12_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT13_IRQ_CONFIG
|
||||
#define EXTINT13_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT13_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT13_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ13, \
|
||||
}
|
||||
#endif /* EXTINT13_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT14_IRQ_CONFIG
|
||||
#define EXTINT14_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT14_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT14_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ14, \
|
||||
}
|
||||
#endif /* EXTINT14_IRQ_CONFIG */
|
||||
|
||||
#ifndef EXTINT15_IRQ_CONFIG
|
||||
#define EXTINT15_IRQ_CONFIG \
|
||||
{ \
|
||||
.irq_num = BSP_EXTINT15_IRQ_NUM, \
|
||||
.irq_prio = BSP_EXTINT15_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_PORT_EIRQ15, \
|
||||
}
|
||||
#endif /* EXTINT15_IRQ_CONFIG */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __GPIO_CONFIG_H__ */
|
||||
332
bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h
Normal file
332
bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h
Normal file
@@ -0,0 +1,332 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __I2C_CONFIG_H__
|
||||
#define __I2C_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C1)
|
||||
#ifndef I2C1_CONFIG
|
||||
#define I2C1_CONFIG \
|
||||
{ \
|
||||
.name = "i2c1", \
|
||||
.Instance = CM_I2C1, \
|
||||
.clock = FCG1_PERIPH_I2C1, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C1_CONFIG */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_I2C1_USING_DMA)
|
||||
#ifndef I2C1_TX_DMA_CONFIG
|
||||
#define I2C1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_TX_DMA_INSTANCE, \
|
||||
.channel = I2C1_TX_DMA_CHANNEL, \
|
||||
.clock = I2C1_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C1_TEI, \
|
||||
.flag = I2C1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C1_RX_DMA_CONFIG
|
||||
#define I2C1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C1_RX_DMA_INSTANCE, \
|
||||
.channel = I2C1_RX_DMA_CHANNEL, \
|
||||
.clock = I2C1_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C1_RXI, \
|
||||
.flag = I2C1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C1_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C1_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C1_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C1_USING_DMA */
|
||||
|
||||
#if defined(BSP_USING_I2C2)
|
||||
#ifndef I2C2_CONFIG
|
||||
#define I2C2_CONFIG \
|
||||
{ \
|
||||
.name = "i2c2", \
|
||||
.Instance = CM_I2C2, \
|
||||
.clock = FCG1_PERIPH_I2C2, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C2_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C2_USING_DMA)
|
||||
#ifndef I2C2_TX_DMA_CONFIG
|
||||
#define I2C2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C2_TX_DMA_INSTANCE, \
|
||||
.channel = I2C2_TX_DMA_CHANNEL, \
|
||||
.clock = I2C2_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C2_TEI, \
|
||||
.flag = I2C2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C2_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C2_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C2_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C2_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C2_RX_DMA_CONFIG
|
||||
#define I2C2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C2_RX_DMA_INSTANCE, \
|
||||
.channel = I2C2_RX_DMA_CHANNEL, \
|
||||
.clock = I2C2_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C2_RXI, \
|
||||
.flag = I2C2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C2_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C2_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C2_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C2_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C3)
|
||||
#ifndef I2C3_CONFIG
|
||||
#define I2C3_CONFIG \
|
||||
{ \
|
||||
.name = "i2c3", \
|
||||
.Instance = CM_I2C3, \
|
||||
.clock = FCG1_PERIPH_I2C3, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C3_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C3_USING_DMA)
|
||||
#ifndef I2C3_TX_DMA_CONFIG
|
||||
#define I2C3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C3_TX_DMA_INSTANCE, \
|
||||
.channel = I2C3_TX_DMA_CHANNEL, \
|
||||
.clock = I2C3_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C3_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C3_TEI, \
|
||||
.flag = I2C3_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C3_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C3_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C3_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C3_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C3_RX_DMA_CONFIG
|
||||
#define I2C3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C3_RX_DMA_INSTANCE, \
|
||||
.channel = I2C3_RX_DMA_CHANNEL, \
|
||||
.clock = I2C3_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C3_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C3_RXI, \
|
||||
.flag = I2C3_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C3_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C3_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C3_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C3_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C4)
|
||||
#ifndef I2C4_CONFIG
|
||||
#define I2C4_CONFIG \
|
||||
{ \
|
||||
.name = "i2c4", \
|
||||
.Instance = CM_I2C4, \
|
||||
.clock = FCG1_PERIPH_I2C4, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C4_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C4_USING_DMA)
|
||||
#ifndef I2C4_TX_DMA_CONFIG
|
||||
#define I2C4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C4_TX_DMA_INSTANCE, \
|
||||
.channel = I2C4_TX_DMA_CHANNEL, \
|
||||
.clock = I2C4_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C4_TEI, \
|
||||
.flag = I2C4_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C4_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C4_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C4_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C4_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C4_RX_DMA_CONFIG
|
||||
#define I2C4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C4_RX_DMA_INSTANCE, \
|
||||
.channel = I2C4_RX_DMA_CHANNEL, \
|
||||
.clock = I2C4_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C4_RXI, \
|
||||
.flag = I2C4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C4_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C4_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C4_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C4_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C5)
|
||||
#ifndef I2C5_CONFIG
|
||||
#define I2C5_CONFIG \
|
||||
{ \
|
||||
.name = "i2c5", \
|
||||
.Instance = CM_I2C5, \
|
||||
.clock = FCG1_PERIPH_I2C5, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C5_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C5_USING_DMA)
|
||||
#ifndef I2C5_TX_DMA_CONFIG
|
||||
#define I2C5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C5_TX_DMA_INSTANCE, \
|
||||
.channel = I2C5_TX_DMA_CHANNEL, \
|
||||
.clock = I2C5_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C5_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C5_TEI, \
|
||||
.flag = I2C5_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C5_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C5_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C5_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C5_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C5_RX_DMA_CONFIG
|
||||
#define I2C5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C5_RX_DMA_INSTANCE, \
|
||||
.channel = I2C5_RX_DMA_CHANNEL, \
|
||||
.clock = I2C5_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C5_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C5_RXI, \
|
||||
.flag = I2C5_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C5_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C5_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C5_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C5_USING_DMA */
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_I2C6)
|
||||
#ifndef I2C6_CONFIG
|
||||
#define I2C6_CONFIG \
|
||||
{ \
|
||||
.name = "i2c6", \
|
||||
.Instance = CM_I2C6, \
|
||||
.clock = FCG1_PERIPH_I2C6, \
|
||||
.baudrate = 100000UL, \
|
||||
.timeout = 10000UL, \
|
||||
}
|
||||
#endif /* I2C6_CONFIG */
|
||||
|
||||
#if defined(BSP_I2C6_USING_DMA)
|
||||
#ifndef I2C6_TX_DMA_CONFIG
|
||||
#define I2C6_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C6_TX_DMA_INSTANCE, \
|
||||
.channel = I2C6_TX_DMA_CHANNEL, \
|
||||
.clock = I2C6_TX_DMA_CLOCK, \
|
||||
.trigger_select = I2C6_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C6_TEI, \
|
||||
.flag = I2C6_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C6_TX_DMA_IRQn, \
|
||||
.irq_prio = I2C6_TX_DMA_INT_PRIO, \
|
||||
.int_src = I2C6_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C6_TX_DMA_CONFIG */
|
||||
|
||||
#ifndef I2C6_RX_DMA_CONFIG
|
||||
#define I2C6_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = I2C6_RX_DMA_INSTANCE, \
|
||||
.channel = I2C6_RX_DMA_CHANNEL, \
|
||||
.clock = I2C6_RX_DMA_CLOCK, \
|
||||
.trigger_select = I2C6_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_I2C6_RXI, \
|
||||
.flag = I2C6_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = I2C6_RX_DMA_IRQn, \
|
||||
.irq_prio = I2C6_RX_DMA_INT_PRIO, \
|
||||
.int_src = I2C6_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* I2C6_RX_DMA_CONFIG */
|
||||
#endif /* BSP_I2C6_USING_DMA */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
200
bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h
Normal file
200
bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h
Normal file
@@ -0,0 +1,200 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_CONFIG_H__
|
||||
#define __IRQ_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn
|
||||
#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn
|
||||
#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn
|
||||
#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn
|
||||
#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn
|
||||
#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn
|
||||
#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn
|
||||
#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn
|
||||
#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn
|
||||
#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn
|
||||
#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn
|
||||
#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn
|
||||
#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn
|
||||
#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn
|
||||
#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn
|
||||
#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn
|
||||
#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
/* DMA1 ch0 */
|
||||
#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn
|
||||
#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch1 */
|
||||
#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn
|
||||
#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch2 */
|
||||
#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn
|
||||
#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch3 */
|
||||
#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn
|
||||
#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch4 */
|
||||
#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn
|
||||
#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA1 ch5 */
|
||||
#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn
|
||||
#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
/* DMA2 ch0 */
|
||||
#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn
|
||||
#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch1 */
|
||||
#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn
|
||||
#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch2 */
|
||||
#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn
|
||||
#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch3 */
|
||||
#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn
|
||||
#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch4 */
|
||||
#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn
|
||||
#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
/* DMA2 ch5 */
|
||||
#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn
|
||||
#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#define BSP_UART1_IRQ_NUM USART1_IRQn
|
||||
#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn
|
||||
#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#define BSP_UART2_IRQ_NUM USART2_IRQn
|
||||
#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn
|
||||
#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#define BSP_UART3_IRQ_NUM USART3_IRQn
|
||||
#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#define BSP_UART4_IRQ_NUM USART4_IRQn
|
||||
#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn
|
||||
#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#define BSP_UART5_IRQ_NUM USART5_IRQn
|
||||
#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
|
||||
#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \
|
||||
defined(RT_USING_SERIAL_V2)
|
||||
#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn
|
||||
#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#define BSP_UART6_IRQ_NUM USART6_IRQn
|
||||
#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif /* BSP_USING_UART6 */
|
||||
|
||||
#if defined(BSP_USING_SPI1)
|
||||
#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn
|
||||
#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI2)
|
||||
#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn
|
||||
#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_SPI3)
|
||||
#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn
|
||||
#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif
|
||||
|
||||
#if defined(BSP_USING_TMRA_1)
|
||||
#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_1 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_2)
|
||||
#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_2 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_3)
|
||||
#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_3 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_4)
|
||||
#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_4 */
|
||||
|
||||
#if defined(BSP_USING_TMRA_5)
|
||||
#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn
|
||||
#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_TMRA_5 */
|
||||
|
||||
#if defined(BSP_USING_CAN1)
|
||||
#define BSP_CAN1_IRQ_NUM MCAN1_INT0_IRQn
|
||||
#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* BSP_USING_CAN1 */
|
||||
|
||||
#if defined(RT_USING_ALARM)
|
||||
#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn
|
||||
#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT
|
||||
#endif/* RT_USING_ALARM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IRQ_CONFIG_H__ */
|
||||
100
bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h
Normal file
100
bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __PM_CONFIG_H__
|
||||
#define __PM_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_PM
|
||||
extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode);
|
||||
|
||||
#ifndef PM_TICKLESS_TIMER_ENABLE_MASK
|
||||
#define PM_TICKLESS_TIMER_ENABLE_MASK \
|
||||
( (1UL << PM_SLEEP_MODE_IDLE) | \
|
||||
(1UL << PM_SLEEP_MODE_DEEP))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief run mode config @ref pm_run_mode_config structure
|
||||
*/
|
||||
#ifndef PM_RUN_MODE_CFG
|
||||
#define PM_RUN_MODE_CFG \
|
||||
{ \
|
||||
.sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \
|
||||
}
|
||||
#endif /* PM_RUN_MODE_CFG */
|
||||
|
||||
/**
|
||||
* @brief sleep idle config @ref pm_sleep_mode_idle_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_IDLE_CFG
|
||||
#define PM_SLEEP_IDLE_CFG \
|
||||
{ \
|
||||
.pwc_sleep_type = PWC_SLEEP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_IDLE_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep deep config @ref pm_sleep_mode_deep_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_DEEP_CFG
|
||||
#define PM_SLEEP_DEEP_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u16Clock = PWC_STOP_CLK_KEEP, \
|
||||
.u8StopDrv = PWC_STOP_DRV_HIGH, \
|
||||
.u16ExBusHold = PWC_STOP_EXBUS_HIZ, \
|
||||
.u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \
|
||||
}, \
|
||||
.pwc_stop_type = PWC_STOP_WFE_INT, \
|
||||
}
|
||||
#endif /*PM_SLEEP_DEEP_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep standby config @ref pm_sleep_mode_standby_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_STANDBY_CFG
|
||||
#define PM_SLEEP_STANDBY_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD1, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_STANDBY_CFG*/
|
||||
|
||||
/**
|
||||
* @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure
|
||||
*/
|
||||
#ifndef PM_SLEEP_SHUTDOWN_CFG
|
||||
#define PM_SLEEP_SHUTDOWN_CFG \
|
||||
{ \
|
||||
{ \
|
||||
.u8Mode = PWC_PD_MD3, \
|
||||
.u8IOState = PWC_PD_IO_KEEP1, \
|
||||
.u8VcapCtrl = PWC_PD_VCAP_0P047UF, \
|
||||
}, \
|
||||
}
|
||||
#endif /*PM_SLEEP_SHUTDOWN_CFG*/
|
||||
|
||||
#endif /* BSP_USING_PM */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __PM_CONFIG_H__ */
|
||||
545
bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h
Normal file
545
bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h
Normal file
File diff suppressed because it is too large
Load Diff
882
bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h
Normal file
882
bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h
Normal file
File diff suppressed because it is too large
Load Diff
75
bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h
Normal file
75
bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h
Normal file
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __QSPI_CONFIG_H__
|
||||
#define __QSPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_QSPI
|
||||
#ifndef QSPI_BUS_CONFIG
|
||||
#define QSPI_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_QSPI, \
|
||||
.clock = FCG1_PERIPH_QSPI, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_QSPI_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_QSPI_INTR, \
|
||||
}, \
|
||||
}
|
||||
#endif /* QSPI_BUS_CONFIG */
|
||||
|
||||
#ifndef QSPI_INIT_PARAMS
|
||||
#define QSPI_INIT_PARAMS \
|
||||
{ \
|
||||
.u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \
|
||||
.u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \
|
||||
.u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \
|
||||
.u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \
|
||||
}
|
||||
#endif /* QSPI_INIT_PARAMS */
|
||||
|
||||
#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH
|
||||
|
||||
#ifdef BSP_QSPI_USING_DMA
|
||||
#ifndef QSPI_DMA_CONFIG
|
||||
#define QSPI_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = QSPI_DMA_INSTANCE, \
|
||||
.channel = QSPI_DMA_CHANNEL, \
|
||||
.clock = QSPI_DMA_CLOCK, \
|
||||
.trigger_select = QSPI_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_AOS_STRG, \
|
||||
.flag = QSPI_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = QSPI_DMA_IRQn, \
|
||||
.irq_prio = QSPI_DMA_INT_PRIO, \
|
||||
.int_src = QSPI_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* QSPI_DMA_CONFIG */
|
||||
#endif /* BSP_QSPI_USING_DMA */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__QSPI_CONFIG_H__ */
|
||||
377
bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h
Normal file
377
bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h
Normal file
@@ -0,0 +1,377 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __SPI_CONFIG_H__
|
||||
#define __SPI_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef BSP_USING_SPI1
|
||||
#ifndef SPI1_BUS_CONFIG
|
||||
#define SPI1_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI1, \
|
||||
.bus_name = "spi1", \
|
||||
.clock = FCG1_PERIPH_SPI1, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI1_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI1_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI1_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI1 */
|
||||
|
||||
#ifdef BSP_SPI1_TX_USING_DMA
|
||||
#ifndef SPI1_TX_DMA_CONFIG
|
||||
#define SPI1_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_TX_DMA_INSTANCE, \
|
||||
.channel = SPI1_TX_DMA_CHANNEL, \
|
||||
.clock = SPI1_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI1_SPTI, \
|
||||
.flag = SPI1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI1_RX_USING_DMA
|
||||
#ifndef SPI1_RX_DMA_CONFIG
|
||||
#define SPI1_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI1_RX_DMA_INSTANCE, \
|
||||
.channel = SPI1_RX_DMA_CHANNEL, \
|
||||
.clock = SPI1_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI1_SPRI, \
|
||||
.flag = SPI1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI1_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI1_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI1_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI1_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI1_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI2
|
||||
#ifndef SPI2_BUS_CONFIG
|
||||
#define SPI2_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI2, \
|
||||
.bus_name = "spi2", \
|
||||
.clock = FCG1_PERIPH_SPI2, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI2_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI2_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI2_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI2 */
|
||||
|
||||
#ifdef BSP_SPI2_TX_USING_DMA
|
||||
#ifndef SPI2_TX_DMA_CONFIG
|
||||
#define SPI2_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2_TX_DMA_INSTANCE, \
|
||||
.channel = SPI2_TX_DMA_CHANNEL, \
|
||||
.clock = SPI2_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI2_SPTI, \
|
||||
.flag = SPI2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI2_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI2_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI2_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI2_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI2_RX_USING_DMA
|
||||
#ifndef SPI2_RX_DMA_CONFIG
|
||||
#define SPI2_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI2_RX_DMA_INSTANCE, \
|
||||
.channel = SPI2_RX_DMA_CHANNEL, \
|
||||
.clock = SPI2_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI2_SPRI, \
|
||||
.flag = SPI2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI2_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI2_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI2_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI2_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI2_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI3
|
||||
#ifndef SPI3_BUS_CONFIG
|
||||
#define SPI3_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI3, \
|
||||
.bus_name = "spi3", \
|
||||
.clock = FCG1_PERIPH_SPI3, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI3_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI3_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI3_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI3 */
|
||||
|
||||
|
||||
#ifdef BSP_SPI3_TX_USING_DMA
|
||||
#ifndef SPI3_TX_DMA_CONFIG
|
||||
#define SPI3_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3_TX_DMA_INSTANCE, \
|
||||
.channel = SPI3_TX_DMA_CHANNEL, \
|
||||
.clock = SPI3_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI3_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI3_SPTI, \
|
||||
.flag = SPI3_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI3_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI3_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI3_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI3_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI3_RX_USING_DMA
|
||||
#ifndef SPI3_RX_DMA_CONFIG
|
||||
#define SPI3_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI3_RX_DMA_INSTANCE, \
|
||||
.channel = SPI3_RX_DMA_CHANNEL, \
|
||||
.clock = SPI3_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI3_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI3_SPRI, \
|
||||
.flag = SPI3_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI3_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI3_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI3_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI3_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI3_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI4
|
||||
#ifndef SPI4_BUS_CONFIG
|
||||
#define SPI4_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI4, \
|
||||
.bus_name = "spi4", \
|
||||
.clock = FCG1_PERIPH_SPI4, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI4_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI4_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI4_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI4 */
|
||||
|
||||
#ifdef BSP_SPI4_TX_USING_DMA
|
||||
#ifndef SPI4_TX_DMA_CONFIG
|
||||
#define SPI4_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4_TX_DMA_INSTANCE, \
|
||||
.channel = SPI4_TX_DMA_CHANNEL, \
|
||||
.clock = SPI4_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI4_SPTI, \
|
||||
.flag = SPI4_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI4_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI4_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI4_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI4_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI4_RX_USING_DMA
|
||||
#ifndef SPI4_RX_DMA_CONFIG
|
||||
#define SPI4_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI4_RX_DMA_INSTANCE, \
|
||||
.channel = SPI4_RX_DMA_CHANNEL, \
|
||||
.clock = SPI4_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI4_SPRI, \
|
||||
.flag = SPI4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI4_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI4_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI4_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI4_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI4_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI5
|
||||
#ifndef SPI5_BUS_CONFIG
|
||||
#define SPI5_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI5, \
|
||||
.bus_name = "spi5", \
|
||||
.clock = FCG1_PERIPH_SPI5, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI5_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI5_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI5_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI5 */
|
||||
|
||||
#ifdef BSP_SPI5_TX_USING_DMA
|
||||
#ifndef SPI5_TX_DMA_CONFIG
|
||||
#define SPI5_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_TX_DMA_INSTANCE, \
|
||||
.channel = SPI5_TX_DMA_CHANNEL, \
|
||||
.clock = SPI5_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPTI, \
|
||||
.flag = SPI5_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI5_RX_USING_DMA
|
||||
#ifndef SPI5_RX_DMA_CONFIG
|
||||
#define SPI5_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI5_RX_DMA_INSTANCE, \
|
||||
.channel = SPI5_RX_DMA_CHANNEL, \
|
||||
.clock = SPI5_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI5_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI5_SPRI, \
|
||||
.flag = SPI5_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI5_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI5_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI5_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI5_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI5_RX_USING_DMA */
|
||||
|
||||
#ifdef BSP_USING_SPI6
|
||||
#ifndef SPI6_BUS_CONFIG
|
||||
#define SPI6_BUS_CONFIG \
|
||||
{ \
|
||||
.Instance = CM_SPI6, \
|
||||
.bus_name = "spi6", \
|
||||
.clock = FCG1_PERIPH_SPI6, \
|
||||
.timeout = 5000UL, \
|
||||
.err_irq.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_SPI6_ERR_IRQ_NUM, \
|
||||
.irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_SPI6_SPEI, \
|
||||
}, \
|
||||
}
|
||||
#endif /* SPI6_BUS_CONFIG */
|
||||
#endif /* BSP_USING_SPI6 */
|
||||
|
||||
#ifdef BSP_SPI6_TX_USING_DMA
|
||||
#ifndef SPI6_TX_DMA_CONFIG
|
||||
#define SPI6_TX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_TX_DMA_INSTANCE, \
|
||||
.channel = SPI6_TX_DMA_CHANNEL, \
|
||||
.clock = SPI6_TX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPTI, \
|
||||
.flag = SPI6_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_TX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_TX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_TX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_TX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_TX_USING_DMA */
|
||||
|
||||
#ifdef BSP_SPI6_RX_USING_DMA
|
||||
#ifndef SPI6_RX_DMA_CONFIG
|
||||
#define SPI6_RX_DMA_CONFIG \
|
||||
{ \
|
||||
.Instance = SPI6_RX_DMA_INSTANCE, \
|
||||
.channel = SPI6_RX_DMA_CHANNEL, \
|
||||
.clock = SPI6_RX_DMA_CLOCK, \
|
||||
.trigger_select = SPI6_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_SPI6_SPRI, \
|
||||
.flag = SPI6_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = SPI6_RX_DMA_IRQn, \
|
||||
.irq_prio = SPI6_RX_DMA_INT_PRIO, \
|
||||
.int_src = SPI6_RX_DMA_INT_SRC, \
|
||||
} \
|
||||
}
|
||||
#endif /* SPI6_RX_DMA_CONFIG */
|
||||
#endif /* BSP_SPI6_RX_USING_DMA */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SPI_CONFIG_H__ */
|
||||
115
bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h
Normal file
115
bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h
Normal file
@@ -0,0 +1,115 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TMR_CONFIG_H__
|
||||
#define __TMR_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef BSP_USING_TMRA_1
|
||||
#ifndef TMRA_1_CONFIG
|
||||
#define TMRA_1_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_1, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_1, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_1_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_1" \
|
||||
}
|
||||
#endif /* TMRA_1_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_1 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_2
|
||||
#ifndef TMRA_2_CONFIG
|
||||
#define TMRA_2_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_2, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_2, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_2_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_2" \
|
||||
}
|
||||
#endif /* TMRA_2_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_2 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_3
|
||||
#ifndef TMRA_3_CONFIG
|
||||
#define TMRA_3_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_3, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_3, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_3_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_3" \
|
||||
}
|
||||
#endif /* TMRA_3_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_3 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_4
|
||||
#ifndef TMRA_4_CONFIG
|
||||
#define TMRA_4_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_4, \
|
||||
.clock_source = CLK_BUS_PCLK0, \
|
||||
.clock = FCG2_PERIPH_TMRA_4, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_4_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_4" \
|
||||
}
|
||||
#endif /* TMRA_4_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_4 */
|
||||
|
||||
#ifdef BSP_USING_TMRA_5
|
||||
#ifndef TMRA_5_CONFIG
|
||||
#define TMRA_5_CONFIG \
|
||||
{ \
|
||||
.tmr_handle = CM_TMRA_5, \
|
||||
.clock_source = CLK_BUS_PCLK1, \
|
||||
.clock = FCG2_PERIPH_TMRA_5, \
|
||||
.flag = TMRA_FLAG_OVF, \
|
||||
.isr = \
|
||||
{ \
|
||||
.enIntSrc = INT_SRC_TMRA_5_OVF, \
|
||||
.enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \
|
||||
.u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \
|
||||
}, \
|
||||
.name = "tmra_5" \
|
||||
}
|
||||
#endif /* TMRA_5_CONFIG */
|
||||
#endif /* BSP_USING_TMRA_5 */
|
||||
#endif /* __TMR_CONFIG_H__ */
|
||||
449
bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h
Normal file
449
bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h
Normal file
@@ -0,0 +1,449 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __UART_CONFIG_H__
|
||||
#define __UART_CONFIG_H__
|
||||
|
||||
#include <rtthread.h>
|
||||
#include "irq_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(BSP_USING_UART1)
|
||||
#ifndef UART1_CONFIG
|
||||
#define UART1_CONFIG \
|
||||
{ \
|
||||
.name = "uart1", \
|
||||
.Instance = CM_USART1, \
|
||||
.clock = FCG3_PERIPH_USART1, \
|
||||
.irq_num = BSP_UART1_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART1_EI, \
|
||||
.rx_int_src = INT_SRC_USART1_RI, \
|
||||
.tx_int_src = INT_SRC_USART1_TI, \
|
||||
}
|
||||
#endif /* UART1_CONFIG */
|
||||
|
||||
#if defined(BSP_UART1_RX_USING_DMA)
|
||||
#ifndef UART1_DMA_RX_CONFIG
|
||||
#define UART1_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_RX_DMA_INSTANCE, \
|
||||
.channel = UART1_RX_DMA_CHANNEL, \
|
||||
.clock = UART1_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART1_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART1_RI, \
|
||||
.flag = UART1_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART1_RX_DMA_IRQn, \
|
||||
.irq_prio = UART1_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART1_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART1_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART1_RXTO_CONFIG
|
||||
#define UART1_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_1, \
|
||||
.channel = TMR0_CH_A, \
|
||||
.clock = FCG2_PERIPH_TMR0_1, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART1_RXTO_CONFIG */
|
||||
#endif /* BSP_UART1_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_TX_CPLT_CONFIG
|
||||
#define UART1_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART1_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART1_TX_CPLT_CONFIG
|
||||
#define UART1_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART1_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART1_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART1_TX_USING_DMA)
|
||||
#ifndef UART1_DMA_TX_CONFIG
|
||||
#define UART1_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART1_TX_DMA_INSTANCE, \
|
||||
.channel = UART1_TX_DMA_CHANNEL, \
|
||||
.clock = UART1_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART1_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART1_TI, \
|
||||
.flag = UART1_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART1_TX_DMA_IRQn, \
|
||||
.irq_prio = UART1_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART1_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART1_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART1_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART1 */
|
||||
|
||||
#if defined(BSP_USING_UART2)
|
||||
#ifndef UART2_CONFIG
|
||||
#define UART2_CONFIG \
|
||||
{ \
|
||||
.name = "uart2", \
|
||||
.Instance = CM_USART2, \
|
||||
.clock = FCG3_PERIPH_USART2, \
|
||||
.irq_num = BSP_UART2_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART2_EI, \
|
||||
.rx_int_src = INT_SRC_USART2_RI, \
|
||||
.tx_int_src = INT_SRC_USART2_TI, \
|
||||
}
|
||||
#endif /* UART2_CONFIG */
|
||||
|
||||
#if defined(BSP_UART2_RX_USING_DMA)
|
||||
#ifndef UART2_DMA_RX_CONFIG
|
||||
#define UART2_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_RX_DMA_INSTANCE, \
|
||||
.channel = UART2_RX_DMA_CHANNEL, \
|
||||
.clock = UART2_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART2_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART2_RI, \
|
||||
.flag = UART2_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART2_RX_DMA_IRQn, \
|
||||
.irq_prio = UART2_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART2_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART2_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART2_RXTO_CONFIG
|
||||
#define UART2_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_1, \
|
||||
.channel = TMR0_CH_B, \
|
||||
.clock = FCG2_PERIPH_TMR0_1, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART2_RXTO_CONFIG */
|
||||
#endif /* BSP_UART2_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_TX_CPLT_CONFIG
|
||||
#define UART2_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART2_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART2_TX_CPLT_CONFIG
|
||||
#define UART2_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART2_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART2_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART2_TX_USING_DMA)
|
||||
#ifndef UART2_DMA_TX_CONFIG
|
||||
#define UART2_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART2_TX_DMA_INSTANCE, \
|
||||
.channel = UART2_TX_DMA_CHANNEL, \
|
||||
.clock = UART2_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART2_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART2_TI, \
|
||||
.flag = UART2_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART2_TX_DMA_IRQn, \
|
||||
.irq_prio = UART2_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART2_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART2_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART2_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART2 */
|
||||
|
||||
#if defined(BSP_USING_UART3)
|
||||
#ifndef UART3_CONFIG
|
||||
#define UART3_CONFIG \
|
||||
{ \
|
||||
.name = "uart3", \
|
||||
.Instance = CM_USART3, \
|
||||
.clock = FCG3_PERIPH_USART3, \
|
||||
.irq_num = BSP_UART3_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART3_EI, \
|
||||
.rx_int_src = INT_SRC_USART3_RI, \
|
||||
.tx_int_src = INT_SRC_USART3_TI, \
|
||||
}
|
||||
#endif /* UART3_CONFIG */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART3_TX_CPLT_CONFIG
|
||||
#define UART3_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART3_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART3_TX_CPLT_CONFIG */
|
||||
#endif /* BSP_USING_UART3 */
|
||||
|
||||
#if defined(BSP_USING_UART4)
|
||||
#ifndef UART4_CONFIG
|
||||
#define UART4_CONFIG \
|
||||
{ \
|
||||
.name = "uart4", \
|
||||
.Instance = CM_USART4, \
|
||||
.clock = FCG3_PERIPH_USART4, \
|
||||
.irq_num = BSP_UART4_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART4_EI, \
|
||||
.rx_int_src = INT_SRC_USART4_RI, \
|
||||
.tx_int_src = INT_SRC_USART4_TI, \
|
||||
}
|
||||
#endif /* UART4_CONFIG */
|
||||
|
||||
#if defined(BSP_UART4_RX_USING_DMA)
|
||||
#ifndef UART4_DMA_RX_CONFIG
|
||||
#define UART4_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_RX_DMA_INSTANCE, \
|
||||
.channel = UART4_RX_DMA_CHANNEL, \
|
||||
.clock = UART4_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART4_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART4_RI, \
|
||||
.flag = UART4_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART4_RX_DMA_IRQn, \
|
||||
.irq_prio = UART4_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART4_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART4_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART4_RXTO_CONFIG
|
||||
#define UART4_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_2, \
|
||||
.channel = TMR0_CH_A, \
|
||||
.clock = FCG2_PERIPH_TMR0_2, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART4_RXTO_CONFIG */
|
||||
#endif /* BSP_UART4_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_TX_CPLT_CONFIG
|
||||
#define UART4_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART4_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART4_TX_CPLT_CONFIG
|
||||
#define UART4_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART4_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART4_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART4_TX_USING_DMA)
|
||||
#ifndef UART4_DMA_TX_CONFIG
|
||||
#define UART4_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART4_TX_DMA_INSTANCE, \
|
||||
.channel = UART4_TX_DMA_CHANNEL, \
|
||||
.clock = UART4_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART4_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART4_TI, \
|
||||
.flag = UART4_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART4_TX_DMA_IRQn, \
|
||||
.irq_prio = UART4_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART4_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART4_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART4_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART4 */
|
||||
|
||||
#if defined(BSP_USING_UART5)
|
||||
#ifndef UART5_CONFIG
|
||||
#define UART5_CONFIG \
|
||||
{ \
|
||||
.name = "uart5", \
|
||||
.Instance = CM_USART5, \
|
||||
.clock = FCG3_PERIPH_USART5, \
|
||||
.irq_num = BSP_UART5_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART5_EI, \
|
||||
.rx_int_src = INT_SRC_USART5_RI, \
|
||||
.tx_int_src = INT_SRC_USART5_TI, \
|
||||
}
|
||||
#endif /* UART5_CONFIG */
|
||||
|
||||
#if defined(BSP_UART5_RX_USING_DMA)
|
||||
#ifndef UART5_DMA_RX_CONFIG
|
||||
#define UART5_DMA_RX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART5_RX_DMA_INSTANCE, \
|
||||
.channel = UART5_RX_DMA_CHANNEL, \
|
||||
.clock = UART5_RX_DMA_CLOCK, \
|
||||
.trigger_select = UART5_RX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART5_RI, \
|
||||
.flag = UART5_RX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART5_RX_DMA_IRQn, \
|
||||
.irq_prio = UART5_RX_DMA_INT_PRIO, \
|
||||
.int_src = UART5_RX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART5_DMA_RX_CONFIG */
|
||||
|
||||
#ifndef UART5_RXTO_CONFIG
|
||||
#define UART5_RXTO_CONFIG \
|
||||
{ \
|
||||
.TMR0_Instance = CM_TMR0_2, \
|
||||
.channel = TMR0_CH_B, \
|
||||
.clock = FCG2_PERIPH_TMR0_2, \
|
||||
.timeout_bits = 20UL, \
|
||||
}
|
||||
#endif /* UART5_RXTO_CONFIG */
|
||||
#endif /* BSP_UART5_RX_USING_DMA */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)
|
||||
#ifndef UART5_TX_CPLT_CONFIG
|
||||
#define UART5_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART5_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#elif defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART5_TX_CPLT_CONFIG
|
||||
#define UART5_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART5_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART5_TX_CPLT_CONFIG */
|
||||
|
||||
#if defined(BSP_UART5_TX_USING_DMA)
|
||||
#ifndef UART5_DMA_TX_CONFIG
|
||||
#define UART5_DMA_TX_CONFIG \
|
||||
{ \
|
||||
.Instance = UART5_TX_DMA_INSTANCE, \
|
||||
.channel = UART5_TX_DMA_CHANNEL, \
|
||||
.clock = UART5_TX_DMA_CLOCK, \
|
||||
.trigger_select = UART5_TX_DMA_TRIG_SELECT, \
|
||||
.trigger_event = EVT_SRC_USART5_TI, \
|
||||
.flag = UART5_TX_DMA_TRANS_FLAG, \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = UART5_TX_DMA_IRQn, \
|
||||
.irq_prio = UART5_TX_DMA_INT_PRIO, \
|
||||
.int_src = UART5_TX_DMA_INT_SRC, \
|
||||
}, \
|
||||
}
|
||||
#endif /* UART5_DMA_TX_CONFIG */
|
||||
#endif /* BSP_UART5_TX_USING_DMA */
|
||||
#endif /* BSP_USING_UART5 */
|
||||
|
||||
#if defined(BSP_USING_UART6)
|
||||
#ifndef UART6_CONFIG
|
||||
#define UART6_CONFIG \
|
||||
{ \
|
||||
.name = "uart6", \
|
||||
.Instance = CM_USART6, \
|
||||
.clock = FCG3_PERIPH_USART6, \
|
||||
.irq_num = BSP_UART6_IRQ_NUM, \
|
||||
.rxerr_int_src = INT_SRC_USART6_EI, \
|
||||
.rx_int_src = INT_SRC_USART6_RI, \
|
||||
.tx_int_src = INT_SRC_USART6_TI, \
|
||||
}
|
||||
#endif /* UART6_CONFIG */
|
||||
|
||||
#if defined(RT_USING_SERIAL_V2)
|
||||
#ifndef UART6_TX_CPLT_CONFIG
|
||||
#define UART6_TX_CPLT_CONFIG \
|
||||
{ \
|
||||
.irq_config = \
|
||||
{ \
|
||||
.irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \
|
||||
.irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \
|
||||
.int_src = INT_SRC_USART6_TCI, \
|
||||
}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* UART6_TX_CPLT_CONFIG */
|
||||
#endif /* BSP_USING_UART6 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
39
bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h
Normal file
39
bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __DRV_CONFIG_H__
|
||||
#define __DRV_CONFIG_H__
|
||||
|
||||
#include <board.h>
|
||||
#include <rtthread.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "dma_config.h"
|
||||
#include "uart_config.h"
|
||||
#include "spi_config.h"
|
||||
#include "adc_config.h"
|
||||
#include "dac_config.h"
|
||||
#include "gpio_config.h"
|
||||
#include "can_config.h"
|
||||
#include "pm_config.h"
|
||||
#include "i2c_config.h"
|
||||
#include "qspi_config.h"
|
||||
#include "pulse_encoder_config.h"
|
||||
#include "timer_config.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
136
bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h
Normal file
136
bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h
Normal file
@@ -0,0 +1,136 @@
|
||||
/**
|
||||
*******************************************************************************
|
||||
* @file template/source/hc32f4xx_conf.h
|
||||
* @brief This file contains HC32 Series Device Driver Library usage management.
|
||||
@verbatim
|
||||
Change Logs:
|
||||
Date Author Notes
|
||||
2023-05-31 CDT First version
|
||||
@endverbatim
|
||||
*******************************************************************************
|
||||
* Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*******************************************************************************
|
||||
*/
|
||||
#ifndef __HC32F4XX_CONF_H__
|
||||
#define __HC32F4XX_CONF_H__
|
||||
|
||||
/*******************************************************************************
|
||||
* Include files
|
||||
******************************************************************************/
|
||||
#include <rtconfig.h>
|
||||
|
||||
/* C binding of definitions if building with C++ compiler */
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Global type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
|
||||
/**
|
||||
* @brief This is the list of modules to be used in the Device Driver Library.
|
||||
* Select the modules you need to use to DDL_ON.
|
||||
* @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works
|
||||
* properly.
|
||||
* @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver
|
||||
* Library.
|
||||
* @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function.
|
||||
*/
|
||||
#define LL_ICG_ENABLE (DDL_ON)
|
||||
#define LL_UTILITY_ENABLE (DDL_ON)
|
||||
#define LL_PRINT_ENABLE (DDL_OFF)
|
||||
|
||||
#define LL_ADC_ENABLE (DDL_ON)
|
||||
#define LL_AES_ENABLE (DDL_ON)
|
||||
#define LL_AOS_ENABLE (DDL_ON)
|
||||
#define LL_CLK_ENABLE (DDL_ON)
|
||||
#define LL_CMP_ENABLE (DDL_ON)
|
||||
#define LL_CRC_ENABLE (DDL_ON)
|
||||
#define LL_CTC_ENABLE (DDL_ON)
|
||||
#define LL_DAC_ENABLE (DDL_ON)
|
||||
#define LL_DBGC_ENABLE (DDL_OFF)
|
||||
#define LL_DCU_ENABLE (DDL_ON)
|
||||
#define LL_DMA_ENABLE (DDL_ON)
|
||||
#define LL_EFM_ENABLE (DDL_ON)
|
||||
#define LL_EMB_ENABLE (DDL_ON)
|
||||
#define LL_EVENT_PORT_ENABLE (DDL_OFF)
|
||||
#define LL_FCG_ENABLE (DDL_ON)
|
||||
#define LL_FCM_ENABLE (DDL_ON)
|
||||
#define LL_GPIO_ENABLE (DDL_ON)
|
||||
#define LL_HASH_ENABLE (DDL_ON)
|
||||
#define LL_I2C_ENABLE (DDL_ON)
|
||||
#define LL_INTERRUPTS_ENABLE (DDL_ON)
|
||||
#define LL_KEYSCAN_ENABLE (DDL_ON)
|
||||
#define LL_MCAN_ENABLE (DDL_ON)
|
||||
#define LL_MPU_ENABLE (DDL_ON)
|
||||
#define LL_PWC_ENABLE (DDL_ON)
|
||||
#define LL_QSPI_ENABLE (DDL_ON)
|
||||
#define LL_RMU_ENABLE (DDL_ON)
|
||||
#define LL_RTC_ENABLE (DDL_ON)
|
||||
#define LL_SMC_ENABLE (DDL_ON)
|
||||
#define LL_SPI_ENABLE (DDL_ON)
|
||||
#define LL_SRAM_ENABLE (DDL_ON)
|
||||
#define LL_SWDT_ENABLE (DDL_ON)
|
||||
#define LL_TMR0_ENABLE (DDL_ON)
|
||||
#define LL_TMR4_ENABLE (DDL_ON)
|
||||
#define LL_TMR6_ENABLE (DDL_ON)
|
||||
#define LL_TMRA_ENABLE (DDL_ON)
|
||||
#define LL_TRNG_ENABLE (DDL_ON)
|
||||
#define LL_USART_ENABLE (DDL_ON)
|
||||
#define LL_WDT_ENABLE (DDL_ON)
|
||||
|
||||
/**
|
||||
* @brief The following is a list of currently supported BSP boards.
|
||||
*/
|
||||
#define BSP_EV_HC32F448_LQFP80 (9U)
|
||||
|
||||
/**
|
||||
* @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently
|
||||
* in use.
|
||||
* The value should be set to one of the list of currently supported BSP boards.
|
||||
* @note If there is no supported BSP board or the BSP function is not used,
|
||||
* the value needs to be set to 0U.
|
||||
*/
|
||||
#define BSP_EV_HC32F4XX (BSP_EV_HC32F448_LQFP80)
|
||||
|
||||
/**
|
||||
* @brief This is the list of BSP components to be used.
|
||||
* Select the components you need to use to DDL_ON.
|
||||
*/
|
||||
#define BSP_24CXX_ENABLE (DDL_OFF)
|
||||
#define BSP_GT9XX_ENABLE (DDL_OFF)
|
||||
#define BSP_IS61LV6416_ENABLE (DDL_OFF)
|
||||
#define BSP_NT35510_ENABLE (DDL_OFF)
|
||||
#define BSP_TCA9539_ENABLE (DDL_OFF)
|
||||
#define BSP_W25QXX_ENABLE (DDL_OFF)
|
||||
#define BSP_INT_KEY_ENABLE (DDL_OFF)
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions ('extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Global function prototypes (definition in C source)
|
||||
******************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __HC32F4XX_CONF_H__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* EOF (not truncated)
|
||||
******************************************************************************/
|
||||
103
bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf
Normal file
103
bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf
Normal file
@@ -0,0 +1,103 @@
|
||||
/***************************************************************************//**
|
||||
* \file HC32F448.icf
|
||||
* \version 1.0
|
||||
*
|
||||
* \brief Linker file for the IAR compiler.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*******************************************************************************/
|
||||
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
|
||||
|
||||
// Check that necessary symbols have been passed to linker via command line interface
|
||||
if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) {
|
||||
error "Link location not defined or not supported!";
|
||||
}
|
||||
if((!isdefinedsymbol(_HC32F448_256K_)) && (!isdefinedsymbol(_HC32F448_128K_))) {
|
||||
error "Mcu type or size not defined or not supported!";
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory address and size definitions
|
||||
******************************************************************************/
|
||||
define symbol ram1_base_address = 0x1FFF8000;
|
||||
define symbol ram1_end_address = 0x20007FFF;
|
||||
if(isdefinedsymbol(_LINK_RAM_)) {
|
||||
define symbol ram_start_reserve = 0x8000;
|
||||
define symbol rom1_base_address = ram1_base_address;
|
||||
define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01;
|
||||
define symbol rom2_base_address = 0x0;
|
||||
define symbol rom2_end_address = 0x0;
|
||||
} else {
|
||||
define symbol ram_start_reserve = 0x0;
|
||||
define symbol rom1_base_address = 0x0;
|
||||
define symbol rom2_base_address = 0x03000C00;
|
||||
define symbol rom2_end_address = 0x03000FFF;
|
||||
|
||||
if(isdefinedsymbol(_HC32F448_256K_)) {
|
||||
define symbol rom1_end_address = 0x0003FFFF;
|
||||
} else if (isdefinedsymbol(_HC32F448_128K_)) {
|
||||
define symbol rom1_end_address = 0x0001FFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = rom1_base_address;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address;
|
||||
define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address;
|
||||
define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address;
|
||||
define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address;
|
||||
define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_EROM3_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve;
|
||||
define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address;
|
||||
define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000;
|
||||
define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF;
|
||||
define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM1_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM2_end__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
|
||||
define symbol __ICFEDIT_region_ERAM3_end__ = 0x0;
|
||||
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0xC00;
|
||||
define symbol __ICFEDIT_size_proc_stack__ = 0x0;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x400;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory definitions
|
||||
******************************************************************************/
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
|
||||
define region OTP_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]
|
||||
| mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in OTP_region { readonly section .otp_data };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
270
bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.ld
Normal file
270
bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.ld
Normal file
@@ -0,0 +1,270 @@
|
||||
/******************************************************************************
|
||||
* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved.
|
||||
*
|
||||
* This software component is licensed by XHSC under BSD 3-Clause license
|
||||
* (the "License"); You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/* File HC32F448xC.ld */
|
||||
/* Abstract Linker script for HC32F448 Device with */
|
||||
/* 256KByte FLASH, 68KByte RAM */
|
||||
/* Version V1.0 */
|
||||
/* Date 2023-05-31 */
|
||||
/*****************************************************************************/
|
||||
|
||||
/* Custom defines, according to section 7.7 of the user manual.
|
||||
Take OTP sector 16 for example. */
|
||||
__OTP_DATA_START = 0x03000C00;
|
||||
__OTP_DATA_SIZE = 1024;
|
||||
__OTP_LOCK_START = 0x03000A80;
|
||||
__OTP_LOCK_SIZE = 128;
|
||||
|
||||
/* Use contiguous memory regions for simple. */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K
|
||||
OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE
|
||||
OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE
|
||||
RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 64K
|
||||
RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K
|
||||
}
|
||||
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.vectors :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.vectors))
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.icg_sec 0x00000400 :
|
||||
{
|
||||
KEEP(*(.icg_sec))
|
||||
} >FLASH
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_stext = .;
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
*(.text) /* remaining code */
|
||||
*(.text.*) /* remaining code */
|
||||
*(.rodata) /* read-only data (constants) */
|
||||
*(.rodata*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.gnu.linkonce.t*)
|
||||
|
||||
/* section information for finsh shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
/* section information for initial. */
|
||||
. = ALIGN(4);
|
||||
__rt_init_start = .;
|
||||
KEEP(*(SORT(.rti_fn*)))
|
||||
__rt_init_end = .;
|
||||
. = ALIGN(4);
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .;
|
||||
} >FLASH
|
||||
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab :
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} >FLASH
|
||||
|
||||
__exidx_start = .;
|
||||
.ARM.exidx :
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} >FLASH
|
||||
__exidx_end = .;
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* preinit data */
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP(*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.init_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* init data */
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
KEEP(*(.init_array))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
/* finit data */
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
KEEP(*(.fini_array))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
__etext = ALIGN(4);
|
||||
|
||||
.otp_data_sec :
|
||||
{
|
||||
KEEP(*(.otp_data_sec))
|
||||
} >OTP_DATA
|
||||
|
||||
.otp_lock_sec :
|
||||
{
|
||||
KEEP(*(.otp_lock_sec))
|
||||
} >OTP_LOCK
|
||||
|
||||
.data : AT (__etext)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start__ = .;
|
||||
*(vtable)
|
||||
*(.data)
|
||||
*(.data*)
|
||||
*(.gnu.linkonce.d*)
|
||||
. = ALIGN(4);
|
||||
*(.ramfunc)
|
||||
*(.ramfunc*)
|
||||
. = ALIGN(4);
|
||||
__data_end__ = .;
|
||||
} >RAM
|
||||
|
||||
.heap_stack (COPY) :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
__end__ = .;
|
||||
PROVIDE(end = .);
|
||||
PROVIDE(_end = .);
|
||||
*(.heap*)
|
||||
. = ALIGN(8);
|
||||
__HeapLimit = .;
|
||||
|
||||
__StackLimit = .;
|
||||
*(.stack*)
|
||||
. = ALIGN(8);
|
||||
__StackTop = .;
|
||||
} >RAM
|
||||
|
||||
__etext_ramb = __etext + ALIGN (SIZEOF(.data), 4);
|
||||
.ramb_data : AT (__etext_ramb)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__data_start_ramb__ = .;
|
||||
*(.ramb_data)
|
||||
*(.ramb_data*)
|
||||
. = ALIGN(4);
|
||||
__data_end_ramb__ = .;
|
||||
} >RAMB
|
||||
|
||||
__bss_start = .;
|
||||
.bss __StackTop (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sbss = .;
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = .;
|
||||
__bss_end__ = _ebss;
|
||||
. = ALIGN(4);
|
||||
*(.noinit*)
|
||||
. = ALIGN(4);
|
||||
} >RAM
|
||||
__bss_end = .;
|
||||
|
||||
.ramb_bss :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start_ramb__ = .;
|
||||
*(.ramb_bss)
|
||||
*(.ramb_bss*)
|
||||
. = ALIGN(4);
|
||||
__bss_end_ramb__ = .;
|
||||
} >RAMB
|
||||
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a (*)
|
||||
libm.a (*)
|
||||
libgcc.a (*)
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
|
||||
PROVIDE(_stack = __StackTop);
|
||||
PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase);
|
||||
PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit);
|
||||
|
||||
__RamEnd = ORIGIN(RAM) + LENGTH(RAM);
|
||||
ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack")
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
/* DWARF debug sections.
|
||||
* Symbols in the DWARF debugging sections are relative to the beginning
|
||||
* of the section so we begin them at 0. */
|
||||
/* DWARF 1 */
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
/* GNU DWARF 1 extensions */
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
/* DWARF 2 */
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
}
|
||||
22
bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.sct
Normal file
22
bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.sct
Normal file
@@ -0,0 +1,22 @@
|
||||
; ****************************************************************
|
||||
; Scatter-Loading Description File
|
||||
; ****************************************************************
|
||||
LR_IROM1 0x00000000 0x00040000 { ; load region size_region
|
||||
ER_IROM1 0x00000000 0x00040000 { ; load address = execution address
|
||||
*.o (RESET, +First)
|
||||
*(InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
.ANY (+XO)
|
||||
}
|
||||
RW_IRAM1 0x1FFF8000 UNINIT 0x00000008 { ; RW data
|
||||
*(.bss.noinit)
|
||||
}
|
||||
RW_IRAM2 0x1FFF8008 0x0000FFF8 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
.ANY (RAMCODE)
|
||||
}
|
||||
RW_IRAMB 0x200F0000 0x00001000 { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
}
|
||||
|
||||
12
bsp/hc32/ev_hc32f448_lqfp80/board/ports/SConscript
Normal file
12
bsp/hc32/ev_hc32f448_lqfp80/board/ports/SConscript
Normal file
@@ -0,0 +1,12 @@
|
||||
import os
|
||||
from building import *
|
||||
|
||||
objs = []
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
list = os.listdir(cwd)
|
||||
for item in list:
|
||||
if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
|
||||
objs = objs + SConscript(os.path.join(item, 'SConscript'))
|
||||
|
||||
Return('objs')
|
||||
123
bsp/hc32/ev_hc32f448_lqfp80/board/ports/drv_spi_flash.c
Normal file
123
bsp/hc32/ev_hc32f448_lqfp80/board/ports/drv_spi_flash.c
Normal file
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <board.h>
|
||||
#include <drv_spi.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rthw.h>
|
||||
#include <finsh.h>
|
||||
#include <dfs_fs.h>
|
||||
#include <fal.h>
|
||||
|
||||
#ifdef BSP_USING_SPI_FLASH
|
||||
|
||||
#include "spi_flash.h"
|
||||
#ifdef RT_USING_SFUD
|
||||
#include "spi_flash_sfud.h"
|
||||
#endif
|
||||
|
||||
#define SPI_BUS_NAME "spi1"
|
||||
#define SPI_FLASH_DEVICE_NAME "spi10"
|
||||
#define SPI_FLASH_CHIP "w25q64"
|
||||
#define SPI_FLASH_SS_PORT GPIO_PORT_C
|
||||
#define SPI_FLASH_SS_PIN GPIO_PIN_07
|
||||
/* Partition Name */
|
||||
#define FS_PARTITION_NAME "filesystem"
|
||||
|
||||
#ifdef RT_USING_SFUD
|
||||
static void rt_hw_spi_flash_reset(char *spi_dev_name)
|
||||
{
|
||||
struct rt_spi_device *spi_dev_w25;
|
||||
rt_uint8_t w25_en_reset = 0x66;
|
||||
rt_uint8_t w25_reset_dev = 0x99;
|
||||
|
||||
spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name);
|
||||
if (!spi_dev_w25)
|
||||
{
|
||||
rt_kprintf("Can't find %s device!\n", spi_dev_name);
|
||||
}
|
||||
else
|
||||
{
|
||||
rt_spi_send(spi_dev_w25, &w25_en_reset, 1U);
|
||||
rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U);
|
||||
DDL_DelayMS(1U);
|
||||
rt_kprintf("Reset ext flash!\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int rt_hw_spi_flash_with_sfud_init(void)
|
||||
{
|
||||
rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN);
|
||||
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME);
|
||||
if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init);
|
||||
|
||||
static int rt_hw_fs_init(void)
|
||||
{
|
||||
struct rt_device *mtd_dev = RT_NULL;
|
||||
|
||||
/* 初始化 fal */
|
||||
fal_init();
|
||||
/* 生成 mtd 设备 */
|
||||
mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME);
|
||||
if (!mtd_dev)
|
||||
{
|
||||
LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 格式化文件系统 */
|
||||
if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME))
|
||||
{
|
||||
/* 挂载 littlefs */
|
||||
if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0))
|
||||
{
|
||||
LOG_I("Filesystem initialized!");
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to initialize filesystem!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG_E("Failed to Format fs!");
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
INIT_APP_EXPORT(rt_hw_fs_init);
|
||||
|
||||
#endif /* RT_USING_SFUD */
|
||||
|
||||
#endif /* BSP_USING_SPI_FLASH */
|
||||
20
bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/SConscript
Normal file
20
bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/SConscript
Normal file
@@ -0,0 +1,20 @@
|
||||
|
||||
from building import *
|
||||
import rtconfig
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = []
|
||||
|
||||
src += Glob('*.c')
|
||||
CPPPATH = [cwd]
|
||||
LOCAL_CFLAGS = ''
|
||||
|
||||
if rtconfig.PLATFORM in ['gcc', 'armclang']:
|
||||
LOCAL_CFLAGS += ' -std=c99'
|
||||
elif rtconfig.PLATFORM in ['armcc']:
|
||||
LOCAL_CFLAGS += ' --c99'
|
||||
|
||||
group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
|
||||
|
||||
Return('group')
|
||||
43
bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_cfg.h
Normal file
43
bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_cfg.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <board.h>
|
||||
|
||||
/* enable hc32f4 onchip flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_HC32F4
|
||||
/* enable SFUD flash driver sample */
|
||||
#define FAL_FLASH_PORT_DRIVER_SFUD
|
||||
|
||||
extern const struct fal_flash_dev hc32_onchip_flash;
|
||||
extern struct fal_flash_dev ext_nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&hc32_onchip_flash, \
|
||||
&ext_nor_flash0, \
|
||||
}
|
||||
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 256 * 1024, 0}, \
|
||||
{FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \
|
||||
}
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <fal.h>
|
||||
|
||||
#include <sfud.h>
|
||||
#ifdef RT_USING_SFUD
|
||||
#include <spi_flash_sfud.h>
|
||||
#endif
|
||||
|
||||
#ifndef FAL_USING_NOR_FLASH_DEV_NAME
|
||||
#define FAL_USING_NOR_FLASH_DEV_NAME "w25q64"
|
||||
#endif
|
||||
|
||||
static int init(void);
|
||||
static int read(long offset, uint8_t *buf, size_t size);
|
||||
static int write(long offset, const uint8_t *buf, size_t size);
|
||||
static int erase(long offset, size_t size);
|
||||
|
||||
static sfud_flash_t sfud_dev = NULL;
|
||||
struct fal_flash_dev ext_nor_flash0 =
|
||||
{
|
||||
.name = FAL_USING_NOR_FLASH_DEV_NAME,
|
||||
.addr = 0,
|
||||
.len = 8 * 1024 * 1024,
|
||||
.blk_size = 4096,
|
||||
.ops = {init, read, write, erase},
|
||||
.write_gran = 1
|
||||
};
|
||||
|
||||
static int init(void)
|
||||
{
|
||||
/* RT-Thread RTOS platform */
|
||||
sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME);
|
||||
if (NULL == sfud_dev)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
/* update the flash chip information */
|
||||
ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran;
|
||||
ext_nor_flash0.len = sfud_dev->chip.capacity;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read(long offset, uint8_t *buf, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int write(long offset, const uint8_t *buf, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
static int erase(long offset, size_t size)
|
||||
{
|
||||
assert(sfud_dev);
|
||||
assert(sfud_dev->init_ok);
|
||||
if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
return size;
|
||||
}
|
||||
320
bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.c
Normal file
320
bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.c
Normal file
@@ -0,0 +1,320 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include <rtdbg.h>
|
||||
|
||||
#ifdef BSP_USING_TCA9539
|
||||
|
||||
#include "tca9539.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Local type definitions ('typedef')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local pre-processor symbols/macros ('#define')
|
||||
******************************************************************************/
|
||||
/* Define for TCA9539 */
|
||||
#define BSP_TCA9539_I2C_BUS_NAME "i2c1"
|
||||
#define BSP_TCA9539_DEV_ADDR (0x74U)
|
||||
|
||||
#define TCA9539_RST_PIN (32) /* PB15 */
|
||||
|
||||
/*******************************************************************************
|
||||
* Global variable definitions (declared in header file with 'extern')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local function prototypes ('static')
|
||||
******************************************************************************/
|
||||
|
||||
/*******************************************************************************
|
||||
* Local variable definitions ('static')
|
||||
******************************************************************************/
|
||||
static struct rt_i2c_bus_device *i2c_bus = RT_NULL;
|
||||
|
||||
/*******************************************************************************
|
||||
* Function implementation - global ('extern') and local ('static')
|
||||
******************************************************************************/
|
||||
/**
|
||||
* @brief BSP TCA9539 write data.
|
||||
* @param [in] bus: Pointer to the i2c bus device.
|
||||
* @param [in] reg: Register to be written.
|
||||
* @param [in] data: The pointer to the buffer contains the data to be written.
|
||||
* @param [in] len: Buffer size in byte.
|
||||
* @retval rt_err_t:
|
||||
* - RT_EOK
|
||||
* - -RT_ERROR
|
||||
*/
|
||||
static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
|
||||
{
|
||||
struct rt_i2c_msg msgs;
|
||||
rt_uint8_t buf[6];
|
||||
|
||||
buf[0] = reg;
|
||||
if (len > 0)
|
||||
{
|
||||
if (len < 6)
|
||||
{
|
||||
rt_memcpy(buf + 1, data, len);
|
||||
}
|
||||
else
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
msgs.addr = BSP_TCA9539_DEV_ADDR;
|
||||
msgs.flags = RT_I2C_WR;
|
||||
msgs.buf = buf;
|
||||
msgs.len = len + 1;
|
||||
if (rt_i2c_transfer(bus, &msgs, 1) == 1)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief BSP TCA9539 Read data.
|
||||
* @param [in] bus: Pointer to the i2c bus device.
|
||||
* @param [in] reg: Register to be read.
|
||||
* @param [out] data: The pointer to the buffer contains the data to be read.
|
||||
* @param [in] len: Buffer size in byte.
|
||||
* @retval rt_err_t:
|
||||
* - RT_EOK
|
||||
* - -RT_ERROR
|
||||
*/
|
||||
static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len)
|
||||
{
|
||||
struct rt_i2c_msg msgs;
|
||||
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
msgs.addr = BSP_TCA9539_DEV_ADDR;
|
||||
msgs.flags = RT_I2C_RD;
|
||||
msgs.buf = data;
|
||||
msgs.len = len;
|
||||
if (rt_i2c_transfer(bus, &msgs, 1) == 1)
|
||||
{
|
||||
return RT_EOK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Reset TCA9539.
|
||||
* @param [in] None
|
||||
* @retval None
|
||||
*/
|
||||
static void TCA9539_Reset(void)
|
||||
{
|
||||
rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT);
|
||||
/* Reset the device */
|
||||
rt_pin_write(TCA9539_RST_PIN, PIN_LOW);
|
||||
rt_thread_mdelay(3U);
|
||||
rt_pin_write(TCA9539_RST_PIN, PIN_HIGH);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write TCA9539 pin output value.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @param [in] u8PinState Pin state to be written.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Pin_State_Definition
|
||||
* @retval rt_err_t:
|
||||
* - RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (0U == u8PinState)
|
||||
{
|
||||
u8TempData[1] &= (uint8_t)(~u8Pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
u8TempData[1] |= u8Pin;
|
||||
}
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read TCA9539 pin input value.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @param [in] u8PinState Pin state to be written.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Pin_State_Definition
|
||||
* @retval rt_err_t:
|
||||
* - RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (0U != (u8TempData[1] & u8Pin))
|
||||
{
|
||||
*pu8PinState = TCA9539_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
*pu8PinState = TCA9539_PIN_RESET;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggle TCA9539 pin output value.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @retval rt_err_t:
|
||||
* - -RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
u8TempData[1] ^= u8Pin;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configuration TCA9539 pin.
|
||||
* @param [in] u8Port Port number.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Port_Definition
|
||||
* @param [in] u8Pin Pin number.
|
||||
* This parameter can be one or any combination of the following values:
|
||||
* @arg @ref TCA9539_Pin_Definition
|
||||
* @param [in] u8Dir Pin output direction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref TCA9539_Direction_Definition
|
||||
* @retval rt_err_t:
|
||||
* - -RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir)
|
||||
{
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
if (TCA9539_DIR_OUT == u8Dir)
|
||||
{
|
||||
u8TempData[1] &= (uint8_t)(~u8Pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
u8TempData[1] |= u8Pin;
|
||||
}
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize TCA9539.
|
||||
* @param [in] None
|
||||
* @retval rt_err_t:
|
||||
* - -RT_ERROR
|
||||
* - RT_EOK
|
||||
*/
|
||||
int TCA9539_Init(void)
|
||||
{
|
||||
char name[RT_NAME_MAX];
|
||||
uint8_t u8TempData[2];
|
||||
|
||||
TCA9539_Reset();
|
||||
rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX);
|
||||
i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name);
|
||||
if (i2c_bus == RT_NULL)
|
||||
{
|
||||
rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME);
|
||||
return -RT_ERROR;
|
||||
}
|
||||
/* All Pins are input as default */
|
||||
u8TempData[0] = TCA9539_REG_CONFIG_PORT0;
|
||||
u8TempData[1] = 0xFFU;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
u8TempData[0] = TCA9539_REG_CONFIG_PORT1;
|
||||
if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U))
|
||||
{
|
||||
return -RT_ERROR;
|
||||
}
|
||||
|
||||
return RT_EOK;
|
||||
}
|
||||
INIT_PREV_EXPORT(TCA9539_Init);
|
||||
|
||||
#endif /* BSP_USING_TCA9539 */
|
||||
133
bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.h
Normal file
133
bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.h
Normal file
@@ -0,0 +1,133 @@
|
||||
/*
|
||||
* Copyright (c) 2006-2022, RT-Thread Development Team
|
||||
* Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2024-02-20 CDT first version
|
||||
*/
|
||||
|
||||
#ifndef __TCA9539_H__
|
||||
#define __TCA9539_H__
|
||||
|
||||
#include <rtdevice.h>
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_REG_INPUT_PORT0 (0x00U)
|
||||
#define TCA9539_REG_INPUT_PORT1 (0x01U)
|
||||
#define TCA9539_REG_OUTPUT_PORT0 (0x02U)
|
||||
#define TCA9539_REG_OUTPUT_PORT1 (0x03U)
|
||||
#define TCA9539_REG_INVERT_PORT0 (0x04U)
|
||||
#define TCA9539_REG_INVERT_PORT1 (0x05U)
|
||||
#define TCA9539_REG_CONFIG_PORT0 (0x06U)
|
||||
#define TCA9539_REG_CONFIG_PORT1 (0x07U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Port_Definition TCA9539 Port Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PORT0 (0x00U)
|
||||
#define TCA9539_IO_PORT1 (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_IO_PIN0 (0x01U)
|
||||
#define TCA9539_IO_PIN1 (0x02U)
|
||||
#define TCA9539_IO_PIN2 (0x04U)
|
||||
#define TCA9539_IO_PIN3 (0x08U)
|
||||
#define TCA9539_IO_PIN4 (0x10U)
|
||||
#define TCA9539_IO_PIN5 (0x20U)
|
||||
#define TCA9539_IO_PIN6 (0x40U)
|
||||
#define TCA9539_IO_PIN7 (0x80U)
|
||||
#define TCA9539_IO_PIN_ALL (0xFFU)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_DIR_OUT (0x00U)
|
||||
#define TCA9539_DIR_IN (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition
|
||||
* @{
|
||||
*/
|
||||
#define TCA9539_PIN_RESET (0x00U)
|
||||
#define TCA9539_PIN_SET (0x01U)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition
|
||||
* @{
|
||||
*/
|
||||
#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */
|
||||
#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */
|
||||
#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */
|
||||
#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */
|
||||
#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */
|
||||
|
||||
#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */
|
||||
#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */
|
||||
#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */
|
||||
#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */
|
||||
#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */
|
||||
#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define LED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_RED_PIN (EIO_LED_RED)
|
||||
#define LED_YELLOW_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_YELLOW_PIN (EIO_LED_YELLOW)
|
||||
#define LED_BLUE_PORT (TCA9539_IO_PORT1)
|
||||
#define LED_BLUE_PIN (EIO_LED_BLUE)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup BSP CAN PHY STB port/pin definition
|
||||
* @{
|
||||
*/
|
||||
#define CAN1_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN1_STB_PIN (EIO_CAN1_STB)
|
||||
#define CAN2_STB_PORT (TCA9539_IO_PORT1)
|
||||
#define CAN2_STB_PIN (EIO_CAN2_STB)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
int TCA9539_Init(void);
|
||||
rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState);
|
||||
rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState);
|
||||
rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin);
|
||||
rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir);
|
||||
|
||||
#endif
|
||||
BIN
bsp/hc32/ev_hc32f448_lqfp80/figures/board.png
Normal file
BIN
bsp/hc32/ev_hc32f448_lqfp80/figures/board.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 7.5 MiB |
@@ -0,0 +1,80 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.jlink.launchConfigurationType">
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <peripherals/> "/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doConnectToRunning" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doContinue" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doDebugInRam" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doFirstReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerAllocateSemihostingConsole" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerInitRegs" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerLocalOnly" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerSilent" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doGdbServerVerifyDownload" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doSecondReset" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.doStartGdbServer" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableFlashBreakpoints" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihosting" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientGdbClient" value="false"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSemihostingIoclientTelnet" value="true"/>
|
||||
<booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.enableSwo" value="true"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.firstResetType" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherCommands" value="set mem inaccessible-by-default off"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbClientOtherOptions" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnection" value="usb"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerConnectionAddress" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDebugInterface" value="swd"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceEndianness" value="little"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceName" value="HC32F448"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerDeviceSpeed" value="1000"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerExecutable" value="${jlink_path}/${jlink_gdbserver}"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerGdbPortNumber" value="2331"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerLog" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerOther" value="-singlerun -strict -timeout 0 -nogui"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerSwoPortNumber" value="2332"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.gdbServerTelnetPortNumber" value="2333"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.interfaceSpeed" value="auto"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherInitCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.otherRunCommands" value=""/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.secondResetType" value=""/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetCpuFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetPortMask" value="0x1"/>
|
||||
<intAttribute key="ilg.gnumcueclipse.debug.gdbjtag.jlink.swoEnableTargetSwoFreq" value="0"/>
|
||||
<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="GNU MCU J-Link"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
|
||||
<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="2331"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="${cross_prefix}gdb${cross_suffix}"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
|
||||
<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/rtthread.elf"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="project"/>
|
||||
<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
|
||||
<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="ilg.gnuarmeclipse.managedbuild.cross.config.elf.debug.553091094"/>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
|
||||
<listEntry value="/project"/>
|
||||
</listAttribute>
|
||||
<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
|
||||
<listEntry value="4"/>
|
||||
</listAttribute>
|
||||
<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="Context string"/> "/>
|
||||
<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
|
||||
</launchConfiguration>
|
||||
2974
bsp/hc32/ev_hc32f448_lqfp80/project.ewd
Normal file
2974
bsp/hc32/ev_hc32f448_lqfp80/project.ewd
Normal file
File diff suppressed because it is too large
Load Diff
2224
bsp/hc32/ev_hc32f448_lqfp80/project.ewp
Normal file
2224
bsp/hc32/ev_hc32f448_lqfp80/project.ewp
Normal file
File diff suppressed because it is too large
Load Diff
10
bsp/hc32/ev_hc32f448_lqfp80/project.eww
Normal file
10
bsp/hc32/ev_hc32f448_lqfp80/project.eww
Normal file
@@ -0,0 +1,10 @@
|
||||
<?xml version="1.0" encoding="iso-8859-1"?>
|
||||
|
||||
<workspace>
|
||||
<project>
|
||||
<path>$WS_DIR$\project.ewp</path>
|
||||
</project>
|
||||
<batchBuild/>
|
||||
</workspace>
|
||||
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user