From 6fe69d7431ed54fcea863ed68d7c4f9746e771b0 Mon Sep 17 00:00:00 2001 From: skllii <48580851+skllii@users.noreply.github.com> Date: Fri, 23 Feb 2024 01:34:35 +0800 Subject: [PATCH] [bsp][hc32] support hc32f448 --- .github/workflows/bsp_buildings.yml | 1 + bsp/hc32/README.md | 1 + bsp/hc32/ev_hc32f448_lqfp80/.config | 1095 + bsp/hc32/ev_hc32f448_lqfp80/.cproject | 214 + bsp/hc32/ev_hc32f448_lqfp80/.gitignore | 42 + bsp/hc32/ev_hc32f448_lqfp80/.project | 68 + bsp/hc32/ev_hc32f448_lqfp80/Kconfig | 21 + bsp/hc32/ev_hc32f448_lqfp80/README.md | 128 + bsp/hc32/ev_hc32f448_lqfp80/SConscript | 15 + bsp/hc32/ev_hc32f448_lqfp80/SConstruct | 62 + .../applications/SConscript | 15 + .../ev_hc32f448_lqfp80/applications/main.c | 32 + .../applications/xtal32_fcm.c | 99 + bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig | 652 + bsp/hc32/ev_hc32f448_lqfp80/board/SConscript | 37 + bsp/hc32/ev_hc32f448_lqfp80/board/board.c | 113 + bsp/hc32/ev_hc32f448_lqfp80/board/board.h | 54 + .../ev_hc32f448_lqfp80/board/board_config.c | 497 + .../ev_hc32f448_lqfp80/board/board_config.h | 310 + .../board/config/adc_config.h | 155 + .../board/config/can_config.h | 139 + .../board/config/dac_config.h | 43 + .../board/config/dma_config.h | 263 + .../board/config/gpio_config.h | 176 + .../board/config/i2c_config.h | 332 + .../board/config/irq_config.h | 200 + .../board/config/pm_config.h | 100 + .../board/config/pulse_encoder_config.h | 545 + .../board/config/pwm_tmr_config.h | 882 + .../board/config/qspi_config.h | 75 + .../board/config/spi_config.h | 377 + .../board/config/timer_config.h | 115 + .../board/config/uart_config.h | 449 + .../ev_hc32f448_lqfp80/board/drv_config.h | 39 + .../ev_hc32f448_lqfp80/board/hc32f4xx_conf.h | 136 + .../board/linker_scripts/link.icf | 103 + .../board/linker_scripts/link.ld | 270 + .../board/linker_scripts/link.sct | 22 + .../ev_hc32f448_lqfp80/board/ports/SConscript | 12 + .../board/ports/drv_spi_flash.c | 123 + .../board/ports/fal/SConscript | 20 + .../board/ports/fal/fal_cfg.h | 43 + .../board/ports/fal/fal_flash_sfud_port.c | 85 + .../ev_hc32f448_lqfp80/board/ports/tca9539.c | 320 + .../ev_hc32f448_lqfp80/board/ports/tca9539.h | 133 + bsp/hc32/ev_hc32f448_lqfp80/figures/board.png | Bin 0 -> 7822856 bytes .../jlink/ev_hc32f448_lqfp80 Debug.launch | 80 + bsp/hc32/ev_hc32f448_lqfp80/project.ewd | 2974 + bsp/hc32/ev_hc32f448_lqfp80/project.ewp | 2224 + bsp/hc32/ev_hc32f448_lqfp80/project.eww | 10 + bsp/hc32/ev_hc32f448_lqfp80/project.uvoptx | 189 + bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx | 867 + bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h | 276 + bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py | 150 + bsp/hc32/ev_hc32f448_lqfp80/template.ewp | 1927 + bsp/hc32/ev_hc32f448_lqfp80/template.eww | 10 + bsp/hc32/ev_hc32f448_lqfp80/template.uvoptx | 189 + bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx | 391 + bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig | 46 +- .../board/ports/sdram_port.h | 19 +- bsp/hc32/libraries/.ignore_format.yml | 1 + bsp/hc32/libraries/hc32_drivers/drv_adc.c | 151 +- bsp/hc32/libraries/hc32_drivers/drv_adc.h | 21 +- bsp/hc32/libraries/hc32_drivers/drv_gpio.c | 3 + bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c | 79 +- bsp/hc32/libraries/hc32_drivers/drv_i2c.c | 2 + bsp/hc32/libraries/hc32_drivers/drv_irq.c | 22 + bsp/hc32/libraries/hc32_drivers/drv_irq.h | 4 + bsp/hc32/libraries/hc32_drivers/drv_pm.c | 2 +- bsp/hc32/libraries/hc32_drivers/drv_sdram.c | 18 +- bsp/hc32/libraries/hc32_drivers/drv_spi.c | 75 +- bsp/hc32/libraries/hc32_drivers/drv_usart.c | 422 +- bsp/hc32/libraries/hc32_drivers/drv_usart.h | 12 +- .../libraries/hc32_drivers/drv_usart_v2.c | 472 +- .../libraries/hc32_drivers/drv_usart_v2.h | 8 + bsp/hc32/libraries/hc32_drivers/drv_wktm.c | 4 +- bsp/hc32/libraries/hc32_drivers/drv_wktm.h | 2 +- bsp/hc32/libraries/hc32f448_ddl/ChangeLog.md | 362 + bsp/hc32/libraries/hc32f448_ddl/LICENSE | 29 + bsp/hc32/libraries/hc32f448_ddl/SConscript | 97 + .../config/flashloader/FlashHC32F448.mac | 16 + .../config/flashloader/FlashHC32F448.out | Bin 0 -> 48368 bytes .../flashloader/FlashHC32F448_otp.flash | 10 + .../config/flashloader/FlashHC32F448_otp.out | Bin 0 -> 47664 bytes .../flashloader/FlashHC32F448_qspi.flash | 9 + .../config/flashloader/FlashHC32F448_qspi.out | Bin 0 -> 53876 bytes .../config/flashloader/FlashHC32F448xA.board | 16 + .../config/flashloader/FlashHC32F448xA.flash | 10 + .../config/flashloader/FlashHC32F448xC.board | 16 + .../config/flashloader/FlashHC32F448xC.flash | 10 + .../drivers/bsp/components/24cxx/24cxx.c | 278 + .../drivers/bsp/components/24cxx/24cxx.h | 121 + .../drivers/bsp/components/gt9xx/gt9xx.c | 183 + .../drivers/bsp/components/gt9xx/gt9xx.h | 150 + .../drivers/bsp/components/nt35510/nt35510.c | 2078 + .../drivers/bsp/components/nt35510/nt35510.h | 202 + .../drivers/bsp/components/tca9539/tca9539.c | 337 + .../drivers/bsp/components/tca9539/tca9539.h | 193 + .../drivers/bsp/components/w25qxx/w25qxx.c | 596 + .../drivers/bsp/components/w25qxx/w25qxx.h | 199 + .../ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.c | 672 + .../ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.h | 249 + .../ev_hc32f448_lqfp80_24cxx.c | 290 + .../ev_hc32f448_lqfp80_24cxx.h | 126 + .../ev_hc32f448_lqfp80_bsp.h | 91 + .../ev_hc32f448_lqfp80_gt9xx.c | 261 + .../ev_hc32f448_lqfp80_gt9xx.h | 135 + .../ev_hc32f448_lqfp80_is61lv6416.c | 321 + .../ev_hc32f448_lqfp80_is61lv6416.h | 203 + .../ev_hc32f448_lqfp80_nt35510.c | 535 + .../ev_hc32f448_lqfp80_nt35510.h | 205 + .../ev_hc32f448_lqfp80_tca9539.c | 387 + .../ev_hc32f448_lqfp80_tca9539.h | 290 + .../ev_hc32f448_lqfp80_w25qxx.c | 324 + .../ev_hc32f448_lqfp80_w25qxx.h | 162 + .../Device/HDSC/hc32f4xx/Include/hc32f448.h | 13622 ++++ .../Device/HDSC/hc32f4xx/Include/hc32f4xx.h | 66 + .../HDSC/hc32f4xx/Include/system_hc32f448.h | 140 + .../Source/ARM/flashloader/HC32F448_128K.FLM | Bin 0 -> 32976 bytes .../Source/ARM/flashloader/HC32F448_256K.FLM | Bin 0 -> 32972 bytes .../Source/ARM/flashloader/HC32F448_RAM.FLM | Bin 0 -> 13664 bytes .../Source/ARM/flashloader/HC32F448_otp.FLM | Bin 0 -> 32496 bytes .../hc32f4xx/Source/ARM/flashloader/ram.ini | 16 + .../HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR | Bin 0 -> 1640452 bytes .../hc32f4xx/Source/ARM/startup_hc32f448.s | 559 + .../hc32f4xx/Source/GCC/linker/HC32F448xA.ld | 216 + .../hc32f4xx/Source/GCC/linker/HC32F448xC.ld | 216 + .../hc32f4xx/Source/GCC/startup_hc32f448.S | 510 + .../HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd | 56794 ++++++++++++++++ .../Source/IAR/flashloader/FlashHC32F448.mac | 16 + .../Source/IAR/flashloader/FlashHC32F448.out | Bin 0 -> 48368 bytes .../IAR/flashloader/FlashHC32F448_otp.out | Bin 0 -> 47664 bytes .../Source/IAR/linker/HC32F448_RAM.icf | 55 + .../hc32f4xx/Source/IAR/linker/HC32F448xA.icf | 52 + .../hc32f4xx/Source/IAR/linker/HC32F448xC.icf | 52 + .../hc32f4xx/Source/IAR/startup_hc32f448.s | 902 + .../HDSC/hc32f4xx/Source/IAR/svd/HC32F448.svd | 56794 ++++++++++++++++ .../HDSC/hc32f4xx/Source/system_hc32f448.c | 205 + .../drivers/cmsis/Include/arm_common_tables.h | 517 + .../drivers/cmsis/Include/arm_const_structs.h | 76 + .../drivers/cmsis/Include/arm_helium_utils.h | 348 + .../drivers/cmsis/Include/arm_math.h | 8970 +++ .../drivers/cmsis/Include/arm_mve_tables.h | 235 + .../drivers/cmsis/Include/arm_vec_math.h | 372 + .../drivers/cmsis/Include/cachel1_armv7.h | 411 + .../drivers/cmsis/Include/cmsis_armcc.h | 885 + .../drivers/cmsis/Include/cmsis_armclang.h | 1467 + .../cmsis/Include/cmsis_armclang_ltm.h | 1893 + .../drivers/cmsis/Include/cmsis_compiler.h | 283 + .../drivers/cmsis/Include/cmsis_gcc.h | 2177 + .../drivers/cmsis/Include/cmsis_iccarm.h | 968 + .../drivers/cmsis/Include/cmsis_version.h | 39 + .../drivers/cmsis/Include/core_armv81mml.h | 4191 ++ .../drivers/cmsis/Include/core_armv8mbl.h | 2222 + .../drivers/cmsis/Include/core_armv8mml.h | 3196 + .../drivers/cmsis/Include/core_cm0.h | 952 + .../drivers/cmsis/Include/core_cm0plus.h | 1087 + .../drivers/cmsis/Include/core_cm1.h | 979 + .../drivers/cmsis/Include/core_cm23.h | 2297 + .../drivers/cmsis/Include/core_cm3.h | 1943 + .../drivers/cmsis/Include/core_cm33.h | 3264 + .../drivers/cmsis/Include/core_cm35p.h | 3264 + .../drivers/cmsis/Include/core_cm4.h | 2129 + .../drivers/cmsis/Include/core_cm55.h | 4215 ++ .../drivers/cmsis/Include/core_cm7.h | 2362 + .../drivers/cmsis/Include/core_sc000.h | 1030 + .../drivers/cmsis/Include/core_sc300.h | 1917 + .../drivers/cmsis/Include/mpu_armv7.h | 275 + .../drivers/cmsis/Include/mpu_armv8.h | 352 + .../drivers/cmsis/Include/pmu_armv8.h | 337 + .../drivers/cmsis/Include/tz_context.h | 70 + .../drivers/hc32_ll_driver/inc/hc32_ll.h | 337 + .../drivers/hc32_ll_driver/inc/hc32_ll_adc.h | 524 + .../drivers/hc32_ll_driver/inc/hc32_ll_aes.h | 117 + .../drivers/hc32_ll_driver/inc/hc32_ll_aos.h | 247 + .../drivers/hc32_ll_driver/inc/hc32_ll_clk.h | 681 + .../drivers/hc32_ll_driver/inc/hc32_ll_cmp.h | 484 + .../drivers/hc32_ll_driver/inc/hc32_ll_crc.h | 163 + .../drivers/hc32_ll_driver/inc/hc32_ll_ctc.h | 249 + .../drivers/hc32_ll_driver/inc/hc32_ll_dac.h | 190 + .../drivers/hc32_ll_driver/inc/hc32_ll_dbgc.h | 148 + .../drivers/hc32_ll_driver/inc/hc32_ll_dcu.h | 298 + .../drivers/hc32_ll_driver/inc/hc32_ll_def.h | 390 + .../drivers/hc32_ll_driver/inc/hc32_ll_dma.h | 587 + .../drivers/hc32_ll_driver/inc/hc32_ll_efm.h | 511 + .../drivers/hc32_ll_driver/inc/hc32_ll_emb.h | 528 + .../hc32_ll_driver/inc/hc32_ll_event_port.h | 231 + .../drivers/hc32_ll_driver/inc/hc32_ll_fcg.h | 198 + .../drivers/hc32_ll_driver/inc/hc32_ll_fcm.h | 290 + .../drivers/hc32_ll_driver/inc/hc32_ll_gpio.h | 451 + .../drivers/hc32_ll_driver/inc/hc32_ll_hash.h | 94 + .../drivers/hc32_ll_driver/inc/hc32_ll_i2c.h | 396 + .../drivers/hc32_ll_driver/inc/hc32_ll_icg.h | 428 + .../hc32_ll_driver/inc/hc32_ll_interrupts.h | 472 + .../hc32_ll_driver/inc/hc32_ll_keyscan.h | 240 + .../drivers/hc32_ll_driver/inc/hc32_ll_mcan.h | 1126 + .../drivers/hc32_ll_driver/inc/hc32_ll_mpu.h | 451 + .../drivers/hc32_ll_driver/inc/hc32_ll_pwc.h | 664 + .../drivers/hc32_ll_driver/inc/hc32_ll_qspi.h | 446 + .../drivers/hc32_ll_driver/inc/hc32_ll_rmu.h | 208 + .../drivers/hc32_ll_driver/inc/hc32_ll_rtc.h | 366 + .../drivers/hc32_ll_driver/inc/hc32_ll_smc.h | 361 + .../drivers/hc32_ll_driver/inc/hc32_ll_spi.h | 509 + .../drivers/hc32_ll_driver/inc/hc32_ll_sram.h | 234 + .../drivers/hc32_ll_driver/inc/hc32_ll_swdt.h | 227 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h | 231 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h | 849 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h | 873 + .../drivers/hc32_ll_driver/inc/hc32_ll_tmra.h | 574 + .../drivers/hc32_ll_driver/inc/hc32_ll_trng.h | 128 + .../hc32_ll_driver/inc/hc32_ll_usart.h | 543 + .../hc32_ll_driver/inc/hc32_ll_utility.h | 131 + .../drivers/hc32_ll_driver/inc/hc32_ll_wdt.h | 228 + .../drivers/hc32_ll_driver/src/hc32_ll.c | 182 + .../drivers/hc32_ll_driver/src/hc32_ll_adc.c | 1153 + .../drivers/hc32_ll_driver/src/hc32_ll_aes.c | 315 + .../drivers/hc32_ll_driver/src/hc32_ll_aos.c | 316 + .../drivers/hc32_ll_driver/src/hc32_ll_clk.c | 1507 + .../drivers/hc32_ll_driver/src/hc32_ll_cmp.c | 1002 + .../drivers/hc32_ll_driver/src/hc32_ll_crc.c | 565 + .../drivers/hc32_ll_driver/src/hc32_ll_ctc.c | 524 + .../drivers/hc32_ll_driver/src/hc32_ll_dac.c | 560 + .../drivers/hc32_ll_driver/src/hc32_ll_dbgc.c | 176 + .../drivers/hc32_ll_driver/src/hc32_ll_dcu.c | 607 + .../drivers/hc32_ll_driver/src/hc32_ll_dma.c | 1355 + .../drivers/hc32_ll_driver/src/hc32_ll_efm.c | 1479 + .../drivers/hc32_ll_driver/src/hc32_ll_emb.c | 696 + .../hc32_ll_driver/src/hc32_ll_event_port.c | 442 + .../drivers/hc32_ll_driver/src/hc32_ll_fcg.c | 194 + .../drivers/hc32_ll_driver/src/hc32_ll_fcm.c | 394 + .../drivers/hc32_ll_driver/src/hc32_ll_gpio.c | 751 + .../drivers/hc32_ll_driver/src/hc32_ll_hash.c | 350 + .../drivers/hc32_ll_driver/src/hc32_ll_i2c.c | 1379 + .../drivers/hc32_ll_driver/src/hc32_ll_icg.c | 138 + .../hc32_ll_driver/src/hc32_ll_interrupts.c | 764 + .../hc32_ll_driver/src/hc32_ll_keyscan.c | 257 + .../drivers/hc32_ll_driver/src/hc32_ll_mcan.c | 2883 + .../drivers/hc32_ll_driver/src/hc32_ll_mpu.c | 1193 + .../drivers/hc32_ll_driver/src/hc32_ll_pwc.c | 1257 + .../drivers/hc32_ll_driver/src/hc32_ll_qspi.c | 495 + .../drivers/hc32_ll_driver/src/hc32_ll_rmu.c | 290 + .../drivers/hc32_ll_driver/src/hc32_ll_rtc.c | 943 + .../drivers/hc32_ll_driver/src/hc32_ll_smc.c | 520 + .../drivers/hc32_ll_driver/src/hc32_ll_spi.c | 1148 + .../drivers/hc32_ll_driver/src/hc32_ll_sram.c | 359 + .../drivers/hc32_ll_driver/src/hc32_ll_swdt.c | 257 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr0.c | 624 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr4.c | 2455 + .../drivers/hc32_ll_driver/src/hc32_ll_tmr6.c | 1849 + .../drivers/hc32_ll_driver/src/hc32_ll_tmra.c | 1206 + .../drivers/hc32_ll_driver/src/hc32_ll_trng.c | 257 + .../hc32_ll_driver/src/hc32_ll_usart.c | 2177 + .../hc32_ll_driver/src/hc32_ll_utility.c | 439 + .../drivers/hc32_ll_driver/src/hc32_ll_wdt.c | 257 + .../hc32/iec60730_class_b_stl/stl_common.h | 145 + .../hc32/iec60730_class_b_stl/stl_conf.h | 106 + .../stl_test_item/inc/stl_sw_crc32.h | 93 + .../stl_test_item/inc/stl_test_cpu.h | 85 + .../stl_test_item/inc/stl_test_flash.h | 85 + .../stl_test_item/inc/stl_test_interrupt.h | 99 + .../stl_test_item/inc/stl_test_pc.h | 84 + .../stl_test_item/inc/stl_test_ram.h | 88 + .../src/EWARM/stl_test_cpu_cm0_startup.s | 372 + .../src/EWARM/stl_test_cpu_cm4_startup.s | 420 + .../src/EWARM/stl_test_cpu_runtime.s | 245 + .../src/EWARM/stl_test_full_ram_startup.s | 186 + .../stl_test_item/src/EWARM/stl_test_pc.s | 148 + .../src/MDK/stl_test_cpu_cm0_startup.s | 378 + .../src/MDK/stl_test_cpu_cm4_startup.s | 426 + .../src/MDK/stl_test_cpu_runtime.s | 251 + .../src/MDK/stl_test_full_ram_startup.s | 191 + .../stl_test_item/src/MDK/stl_test_pc.s | 147 + .../stl_test_item/src/stl_sw_crc32.c | 154 + .../stl_test_item/src/stl_test_flash.c | 179 + .../stl_test_item/src/stl_test_interrupt.c | 165 + .../stl_test_item/src/stl_test_ram_runtime.c | 269 + .../iec60730_class_b_stl/stl_test_runtime.c | 145 + .../iec60730_class_b_stl/stl_test_runtime.h | 114 + .../iec60730_class_b_stl/stl_test_startup.c | 120 + .../iec60730_class_b_stl/stl_test_startup.h | 111 + .../hc32/iec60730_class_b_stl/stl_utility.c | 236 + .../hc32/iec60730_class_b_stl/stl_utility.h | 107 + 282 files changed, 268408 insertions(+), 223 deletions(-) create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/.config create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/.cproject create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/.gitignore create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/.project create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/Kconfig create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/README.md create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/SConscript create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/SConstruct create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/applications/SConscript create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/applications/main.c create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/SConscript create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/board.c create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/board.h create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/config/can_config.h create mode 100644 bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h create mode 100644 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bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c create mode 100644 bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h diff --git a/.github/workflows/bsp_buildings.yml b/.github/workflows/bsp_buildings.yml index 348cb690ec..4314224a60 100644 --- a/.github/workflows/bsp_buildings.yml +++ b/.github/workflows/bsp_buildings.yml @@ -76,6 +76,7 @@ jobs: - "at32/at32f437-start" - "yichip/yc3122-pos" - "hc32/ev_hc32f4a0_lqfp176" + - "hc32/ev_hc32f448_lqfp80" - "hc32/ev_hc32f460_lqfp100_v2" - "hc32l196" - "mm32/mm32f3270-100ask-pitaya" diff --git a/bsp/hc32/README.md b/bsp/hc32/README.md index 36bd07cdbd..e815037a35 100644 --- a/bsp/hc32/README.md +++ b/bsp/hc32/README.md @@ -9,6 +9,7 @@ HC32 系列 BSP 目前支持情况如下表所示： | **F4 系列** | | | [ev_hc32f460_lqfp100_v2](ev_hc32f460_lqfp100_v2) | 小华 官方 EV_F460_LQ100_V2 开发板 | | [ev_hc32f4a0_lqfp176](ev_hc32f4a0_lqfp176) | 小华 官方 EV_F4A0_LQ176 开发板 | +| [ev_hc32f448_lqfp80](ev_hc32f448_lqfp80) | 小华 官方 EV_F448_LQ80 开发板 | | **M1 系列** | | | **M4 系列** | | diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.config b/bsp/hc32/ev_hc32f448_lqfp80/.config new file mode 100644 index 0000000000..248d745eb4 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/.config @@ -0,0 +1,1095 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREDSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x50100 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# CONFIG_RT_USING_CACHE is not set +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +# CONFIG_RT_USING_KTIME is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F448MC=y + +# +# On-chip Drivers +# +CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_TCA9539 is not set +# CONFIG_BSP_USING_SPI_FLASH is not set + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +CONFIG_BSP_UART2_RX_USING_DMA=y +CONFIG_BSP_UART2_TX_USING_DMA=y +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_WDT_TMR is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_PM is not set +# CONFIG_BSP_USING_HWCRYPTO is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_HWTIMER is not set +# CONFIG_BSP_USING_SENSOR is not set + +# +# Board extended module Drivers +# diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.cproject b/bsp/hc32/ev_hc32f448_lqfp80/.cproject new file mode 100644 index 0000000000..5cfcd3d9d9 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/.cproject @@ -0,0 +1,214 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.gitignore b/bsp/hc32/ev_hc32f448_lqfp80/.gitignore new file mode 100644 index 0000000000..7221bde019 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.project b/bsp/hc32/ev_hc32f448_lqfp80/.project new file mode 100644 index 0000000000..d8904aee72 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/.project @@ -0,0 +1,68 @@ + + + project + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/bsp + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-3-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-3-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-3-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-3-PROJECT_LOC%7D/src + + + rt-thread/bsp/hc32 + 2 + virtual:/virtual + + + rt-thread/bsp/hc32/libraries + 2 + $%7BPARENT-1-PROJECT_LOC%7D/libraries + + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/Kconfig b/bsp/hc32/ev_hc32f448_lqfp80/Kconfig new file mode 100644 index 0000000000..79b160b856 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/Kconfig @@ -0,0 +1,21 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "../libraries/Kconfig" +source "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f448_lqfp80/README.md b/bsp/hc32/ev_hc32f448_lqfp80/README.md new file mode 100644 index 0000000000..8fb4018734 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/README.md @@ -0,0 +1,128 @@ +# XHSC EV_F448_LQ80_Rev1.0 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F448_LQ80_Rev1.0 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F448_LQ80_Rev1.0 是 XHSC 官方推出的开发板，搭载 HC32F448MCTI 芯片，基于 ARM Cortex-M4 内核，最高主频 200 MHz，具有丰富的板载资源，可以充分发挥 HC32F448MCTI 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.png) + +EV_F448_LQ80_Rev1.0 开发板常用 **板载资源** 如下： + +- **MCU** + - HC32F448MCTI + - 主频200MHz + - 256KB FLASH + - 68KB RAM +- **外部Memory** + - BL24C256（EEPROM, 256Kbits） + - W25Q64（SPI NOR，64MB） + - IS62WV51216（SRAM， 1MB） +- **常用外设** + - LED: 4 个，User LED（LED0，LED1，LED2，LED3）。 + - 按键: 5 个，矩阵键盘（K1~K4）， WAKEUP（K5），RESET（K0） +- **常用接口** + - USB转串口 + - CAN DB9接口 * 2 + - TFT接口 + - SmartCard接口 + - I2C/USART/SPI接口 +- **调试接口** + - 板载DAP调试器 + - 标准JTAG/SWD/Trace + +开发板更多详细信息请参考小华半导体半导体[EV_F448_LQ80_Rev1.0](https://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART2 | +| LED | 支持 | LED1~4 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | ADC1: CH10, CH11,
ADC3: CH1 | +| CAN | 支持 | CAN1、CAN2 | +| GPIO | 支持 | PA0, PA1... PH2 ---> PIN: 0, 1...82 | +| I2C | 支持 | 软件模拟
硬件I2C1~2
I2C1支持EEPROM（BL24C256） | +| Hwtimer | 支持 | Hwtimer1~5 | +| SPI | 支持 | SPI1~3
SPI1支持W25Q | +| UART | 支持 | UART1~6
UART2为console使用 | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED3会周期性闪烁。 + +USB虚拟COM端口默认连接串口2，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 5.0.1 build Feb 4 2024 16:44:26 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 2 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 +无 +## 联系人信息 + +维护人: + +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f448_lqfp80/SConscript b/bsp/hc32/ev_hc32f448_lqfp80/SConscript new file mode 100644 index 0000000000..20f7689c53 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f448_lqfp80/SConstruct b/bsp/hc32/ev_hc32f448_lqfp80/SConstruct new file mode 100644 index 0000000000..ded3f4c66f --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/SConstruct @@ -0,0 +1,62 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +hc32_library = 'hc32f448_ddl' +rtconfig.BSP_LIBRARY_TYPE = hc32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, hc32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +objs.extend(SConscript(os.path.join(os.getcwd(), 'board', 'ports', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f448_lqfp80/applications/SConscript b/bsp/hc32/ev_hc32f448_lqfp80/applications/SConscript new file mode 100644 index 0000000000..9bb9abae89 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/hc32/ev_hc32f448_lqfp80/applications/main.c b/bsp/hc32/ev_hc32f448_lqfp80/applications/main.c new file mode 100644 index 0000000000..07080dcd0d --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/applications/main.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include +#include +#include + +/* defined the LED_GREEN pin: PA2 */ +#define LED_GREEN_PIN GET_PIN(A, 2) + +int main(void) +{ + /* set LED_GREEN_PIN pin mode to output */ + rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_GREEN_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c new file mode 100644 index 0000000000..0e35671323 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include +#include +#include + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) + +/** + * @brief This thread is used to monitor whether XTAL32 is stable. + * This thread only runs once after the system starts. + * When stability is detected or 2s times out, the thread will end. + * (When a timeout occurs it will be prompted via rt_kprintf) + */ +void xtal32_fcm_thread_entry(void *parameter) +{ + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = 200UL; /* 200*10ms = 2s */ + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(&stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(ENABLE); + + while (1) + { + if (SET == FCM_GetStatus(FCM_FLAG_END)) + { + FCM_ClearStatus(FCM_FLAG_END); + if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF))) + { + FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF); + } + else + { + (void)FCM_DeInit(); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + /* XTAL32 stabled */ + break; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) + { + (void)FCM_DeInit(); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); + break; + } + rt_thread_mdelay(10); + } +} + +int xtal32_fcm_thread_create(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL, + XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + rt_kprintf("create xtal32_fcm thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(xtal32_fcm_thread_create); + +#endif + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig new file mode 100644 index 0000000000..5af9b90959 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig @@ -0,0 +1,652 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F448MC + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Drivers" + menuconfig BSP_USING_ON_CHIP_FLASH_CACHE + bool "Enable on-chip Flash Cache" + default y + if BSP_USING_ON_CHIP_FLASH_CACHE + config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE + bool "Enable on-chip Flash ICODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE + bool "Enable on-chip Flash DCODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + bool "Enable on-chip Flash ICODE Prefetch" + default y + endif +endmenu + +menu "Onboard Peripheral Drivers" + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C + select BSP_USING_I2C1 + default n + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select BSP_USING_ON_CHIP_FLASH + select RT_USING_SFUD + select RT_USING_DFS + select RT_USING_FAL + select RT_USING_MTD_NOR + default n + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_USING_DMA + bool "Enable UART5 RX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_UART5_TX_USING_DMA + bool "Enable UART5 TX DMA" + depends on BSP_USING_UART5 && RT_SERIAL_USING_DMA + default n + + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + + if BSP_USING_I2C + menuconfig BSP_USING_I2C1_SW + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1_SW + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 51 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 90 + endif + endif + + if BSP_USING_I2C + config BSP_I2C_USING_DMA + bool + default n + config BSP_USING_I2C_HW + bool + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool + default n + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool + default n + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_SPI_USING_DMA + bool + default n + + menuconfig BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + if BSP_USING_SPI3 + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI3_TX_USING_DMA + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config BSP_ADC1_USING_DMA + bool "using adc1 dma" + default n + endif + menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config BSP_ADC2_USING_DMA + bool "using adc2 dma" + default n + endif + menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config BSP_ADC3_USING_DMA + bool "using adc3 dma" + default n + endif + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "using dac1" + default n + config BSP_USING_DAC2 + bool "using dac2" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_TCA9539 + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using can1" + default n + config BSP_USING_CAN2 + bool "using can2" + default n + endif + + menuconfig BSP_USING_WDT_TMR + bool "Enable Watchdog Timer" + default n + select RT_USING_WDT + if BSP_USING_WDT_TMR + choice + prompt "Select SWDT/WDT" + default BSP_USING_SWDT + + config BSP_USING_SWDT + bool "SWDT(3.72hour(max))" + config BSP_USING_WDT + bool "WDT(10.7s(max))" + endchoice + + config BSP_WDT_CONTINUE_COUNT + bool "Low Power Mode Keeps Counting" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_XTAL32 + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_PM + bool "Enable PM" + default n + select RT_USING_PM + if BSP_USING_PM + choice + prompt "Select WKTM Clock Src" + default BSP_USING_WKTM_LRC + + config BSP_USING_WKTM_XTAL32 + bool "Using Xtal32" + config BSP_USING_WKTM_LRC + bool "Using LRC" + if BSP_RTC_USING_XTAL32 + config BSP_USING_WKTM_64HZ + bool "Using 64HZ(Note:must use XTAL32 and run RTC)" + endif + endchoice + endif + + menuconfig BSP_USING_HWCRYPTO + bool "Using Hardware Crypto drivers" + default n + select RT_USING_HWCRYPTO + if BSP_USING_HWCRYPTO + config BSP_USING_UQID + bool "Enable UQID (unique id)" + default n + + config BSP_USING_RNG + bool "Using Hardware RNG" + default n + select RT_HWCRYPTO_USING_RNG + + config BSP_USING_CRC + bool "Using Hardware CRC" + default n + select RT_HWCRYPTO_USING_CRC + + config BSP_USING_AES + bool "Using Hardware AES" + default n + select RT_HWCRYPTO_USING_AES + if BSP_USING_AES + choice + prompt "Select AES Mode" + default BSP_USING_AES_ECB + + config BSP_USING_AES_ECB + bool "ECB mode" + select RT_HWCRYPTO_USING_AES_ECB + endchoice + endif + + config BSP_USING_HASH + bool "Using Hardware Hash" + default n + select RT_HWCRYPTO_USING_SHA2 + if BSP_USING_HASH + choice + prompt "Select Hash Mode" + default BSP_USING_SHA2_256 + + config BSP_USING_SHA2_256 + bool "SHA2_256 Mode" + select RT_HWCRYPTO_USING_SHA2_256 + endchoice + endif + + endif + + menuconfig BSP_USING_PWM + bool "Enable output PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM_TMRA + bool "Enable timerA output PWM" + default n + if BSP_USING_PWM_TMRA + menuconfig BSP_USING_PWM_TMRA_1 + bool "Enable timerA-1 output PWM" + default n + if BSP_USING_PWM_TMRA_1 + config BSP_USING_PWM_TMRA_1_CH1 + bool "Enable timerA-1 channel1" + default n + config BSP_USING_PWM_TMRA_1_CH2 + bool "Enable timerA-1 channel2" + default n + endif + menuconfig BSP_USING_PWM_TMRA_2 + bool "Enable timerA-2 output PWM" + default n + if BSP_USING_PWM_TMRA_2 + config BSP_USING_PWM_TMRA_2_CH1 + bool "Enable timerA-2 channel1" + default n + config BSP_USING_PWM_TMRA_2_CH2 + bool "Enable timerA-2 channel2" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM_TMR4 + menuconfig BSP_USING_PWM_TMR4_1 + bool "Enable timer4-1 output PWM" + default n + if BSP_USING_PWM_TMR4_1 + config BSP_USING_PWM_TMR4_1_OUH + bool "Enable TMR4_1_OUH channel0" + default n + config BSP_USING_PWM_TMR4_1_OUL + bool "Enable TMR4_1_OUL channel1" + default n + config BSP_USING_PWM_TMR4_1_OVH + bool "Enable TMR4_1_OVH channel2" + default n + config BSP_USING_PWM_TMR4_1_OVL + bool "Enable TMR4_1_OVL channel3" + default n + config BSP_USING_PWM_TMR4_1_OWH + bool "Enable TMR4_1_OWH channel4" + default n + config BSP_USING_PWM_TMR4_1_OWL + bool "Enable TMR4_1_OWL channel5" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR6 + bool "Enable timer6 output PWM" + default n + if BSP_USING_PWM_TMR6 + menuconfig BSP_USING_PWM_TMR6_1 + bool "Enable timer6-1 output PWM" + default n + if BSP_USING_PWM_TMR6_1 + config BSP_USING_PWM_TMR6_1_A + bool "Enable TMR6_1_A channel0" + default n + config BSP_USING_PWM_TMR6_1_B + bool "Enable TMR6_1_B channel1" + default n + endif + endif + endif + + menuconfig BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + if BSP_USING_QSPI + config BSP_QSPI_USING_DMA + bool "Enable QSPI DMA support" + default n + config BSP_QSPI_USING_SOFT_CS + bool "Enable QSPI Soft CS Pin" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + menuconfig BSP_USING_TMRA_PULSE_ENCODER + bool "Use TIMERA As The Pulse Encoder" + default n + if BSP_USING_TMRA_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMRA_1 + bool "Use TIMERA_1 As The Pulse Encoder" + default n + endif + menuconfig BSP_USING_TMR6_PULSE_ENCODER + bool "Use TIMER6 As The Pulse Encoder" + default n + if BSP_USING_TMR6_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMR6_1 + bool "Use TIMER6_1 As The Pulse Encoder" + default n + endif + endif + + menuconfig BSP_USING_HWTIMER + bool "Enable Hw Timer" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_TMRA_1 + bool "Use Timer_a1 As The Hw Timer" + default n + config BSP_USING_TMRA_2 + bool "Use Timer_a2 As The Hw Timer" + default n + config BSP_USING_TMRA_3 + bool "Use Timer_a3 As The Hw Timer" + default n + config BSP_USING_TMRA_4 + bool "Use Timer_a4 As The Hw Timer" + default n + config BSP_USING_TMRA_5 + bool "Use Timer_a5 As The Hw Timer" + default n + endif + + menuconfig BSP_USING_SENSOR + bool "Enable SENSOR" + default n + select RT_USING_HWTIMER + if BSP_USING_SENSOR + config BSP_USING_TMR0_2B + bool "Use KEYSCAN" + select RT_USING_KEYSCAN + default n + endif +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/SConscript b/bsp/hc32/ev_hc32f448_lqfp80/board/SConscript new file mode 100644 index 0000000000..2062a20a60 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/SConscript @@ -0,0 +1,37 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +if GetDepend(['BSP_USING_TCA9539']): + src += Glob('ports/tca9539.c') + +if GetDepend(['BSP_USING_SPI_FLASH']): + src += Glob('ports/drv_spi_flash.c') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] + +startup_path_prefix = SDK_LIB + +if rtconfig.PLATFORM in ['gcc']: + src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/startup_hc32f448.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += [startup_path_prefix + '/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/IAR/startup_hc32f448.s'] + +CPPDEFINES = ['HC32F448', '__DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board.c b/bsp/hc32/ev_hc32f448_lqfp80/board/board.c new file mode 100644 index 0000000000..13dd21c597 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include "board.h" +#include "board_config.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** System Base Configuration +*/ +void SystemBase_Config(void) +{ +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE) + EFM_ICacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE) + EFM_DCacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH) + EFM_PrefetchCmd(ENABLE); +#endif +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + stc_clock_xtal32_init_t stcXtal32Init; +#endif + + /* PCLK0, HCLK Max 200MHz */ + /* PCLK1, PCLK4 Max 100MHz */ + /* PCLK2, EXCLK Max 60MHz */ + /* PCLK3 Max 50MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 | + CLK_HCLK_DIV1)); + + GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*100 = 800MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* 3 cycles for 150 ~ 200MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE3); + /* 3 cycles for 150 ~ 200MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT3); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + /* Xtal32 config */ + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; + (void)CLK_Xtal32Init(&stcXtal32Init); +#endif +} + +/** Peripheral Clock Configuration +*/ +void PeripheralClock_Config(void) +{ +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif +} + +/** Peripheral Registers Unlock +*/ +void PeripheralRegister_Unlock(void) +{ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); +} diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board.h b/bsp/hc32/ev_hc32f448_lqfp80/board/board.h new file mode 100644 index 0000000000..19ac6e3525 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define HC32_FLASH_SIZE_GRANULARITY (8 * 1024) +#define HC32_FLASH_SIZE (256 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) + +#define HC32_SRAM_SIZE (64) +#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM2$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +void PeripheralRegister_Unlock(void); +void PeripheralClock_Config(void); +void SystemBase_Config(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c new file mode 100644 index 0000000000..486db6c828 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include +#include "board_config.h" +#include "tca9539.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART2) + case (rt_uint32_t)CM_USART2: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART2_RX_PORT, USART2_RX_PIN, USART2_RX_FUNC); + GPIO_SetFunc(USART2_TX_PORT, USART2_TX_PIN, USART2_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART6) + case (rt_uint32_t)CM_USART6: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC); + GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_I2C) +rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + (void)GPIO_StructInit(&stcGpioInit); + + switch ((rt_uint32_t)I2Cx) + { +#if defined(BSP_USING_I2C1) + case (rt_uint32_t)CM_I2C1: + /* Configure I2C1 SDA/SCL pin. */ + GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC); + GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC); + break; +#endif +#if defined(BSP_USING_I2C2) // TODO, ch2 for test only + case (rt_uint32_t)CM_I2C2: + /* Configure I2C2 SDA/SCL pin. */ + GPIO_SetFunc(I2C2_SDA_PORT, I2C2_SDA_PIN, I2C2_SDA_FUNC); + GPIO_SetFunc(I2C2_SCL_PORT, I2C2_SCL_PIN, I2C2_SCL_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(RT_USING_ADC) +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_DAC) +rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)DACx) + { +#if defined(BSP_USING_DAC1) + case (rt_uint32_t)CM_DAC1: + (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ +#if defined(BSP_USING_CAN1) + TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT); +#endif +#if defined(BSP_USING_CAN2) + TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT); +#endif +} +rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CANx) + { +#if defined(BSP_USING_CAN1) + case (rt_uint32_t)CM_CAN1: + GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC); + GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_CAN2) + case (rt_uint32_t)CM_CAN2: + GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC); + GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + + +#if defined (RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; +#if defined(BSP_USING_SPI1) + stc_gpio_init_t stcGpioInit; +#endif + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); + GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +#if defined(BSP_USING_PWM_TMRA) +rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM_TMRA_1) + case (rt_uint32_t)CM_TMRA_1: +#ifdef BSP_USING_PWM_TMRA_1_CH1 + GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH2 + GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH3 + GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH4 + GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); +#endif + break; +#endif +#if defined(BSP_USING_PWM_TMRA_2) + case (rt_uint32_t)CM_TMRA_2: +#ifdef BSP_USING_PWM_TMRA_2_CH1 + GPIO_SetFunc(PWM_TMRA_2_CH1_PORT, PWM_TMRA_2_CH1_PIN, PWM_TMRA_2_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_2_CH2 + GPIO_SetFunc(PWM_TMRA_2_CH2_PORT, PWM_TMRA_2_CH2_PIN, PWM_TMRA_2_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_2_CH3 + GPIO_SetFunc(PWM_TMRA_2_CH3_PORT, PWM_TMRA_2_CH3_PIN, PWM_TMRA_2_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_2_CH4 + GPIO_SetFunc(PWM_TMRA_2_CH4_PORT, PWM_TMRA_2_CH4_PIN, PWM_TMRA_2_CH4_PIN_FUNC); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR4) +rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR4x) + { +#if defined(BSP_USING_PWM_TMR4_1) + case (rt_uint32_t)CM_TMR4_1: +#ifdef BSP_USING_PWM_TMR4_1_OUH + GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OUL + GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVH + GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVL + GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWH + GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWL + GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR6) +rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR6x) + { +#if defined(BSP_USING_PWM_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: +#ifdef BSP_USING_PWM_TMR6_1_A + GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR6_1_B + GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif +#endif + +#ifdef RT_USING_PM +#define EFM_ERASE_TIME_MAX_IN_MILLISECOND (20) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) + +static void _pm_sleep_common_init(rt_bool_t b_disable_unused_clk) +{ + CLK_Xtal32Cmd(ENABLE); + + rt_tick_t tick_start = rt_tick_get_millisecond(); + rt_err_t rt_stat = RT_EOK; + //wait flash idle + while (SET != EFM_GetStatus(EFM_FLAG_RDY)) + { + if (rt_tick_get_millisecond() - tick_start > EFM_ERASE_TIME_MAX_IN_MILLISECOND) + { + rt_stat = RT_ERROR; + break; + } + } + RT_ASSERT(rt_stat == RT_EOK); + + if (b_disable_unused_clk) + { + uint32_t cur_clk_src = READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW); + + switch (cur_clk_src) + { + case CLK_SYSCLK_SRC_HRC: + CLK_PLLCmd(DISABLE); + CLK_MrcCmd(DISABLE); + CLK_LrcCmd(DISABLE); + CLK_XtalCmd(DISABLE); + PWC_LDO_Cmd(PWC_LDO_PLL, DISABLE); + break; + case CLK_SYSCLK_SRC_MRC: + CLK_PLLCmd(DISABLE); + CLK_HrcCmd(DISABLE); + CLK_LrcCmd(DISABLE); + CLK_XtalCmd(DISABLE); + PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE); + + break; + case CLK_SYSCLK_SRC_XTAL: + CLK_PLLCmd(DISABLE); + CLK_HrcCmd(DISABLE); + CLK_MrcCmd(DISABLE); + CLK_LrcCmd(DISABLE); + PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE); + + break; + case CLK_SYSCLK_SRC_XTAL32: + CLK_PLLCmd(DISABLE); + CLK_HrcCmd(DISABLE); + CLK_MrcCmd(DISABLE); + CLK_LrcCmd(DISABLE); + CLK_XtalCmd(DISABLE); + PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE); + + break; + case CLK_SYSCLK_SRC_PLL: + if (CLK_PLL_SRC_XTAL == PLL_SRC) + { + CLK_HrcCmd(DISABLE); + } + else + { + CLK_XtalCmd(DISABLE); + } + CLK_MrcCmd(DISABLE); + CLK_LrcCmd(DISABLE); + PWC_LDO_Cmd(PWC_LDO_HRC, DISABLE); + + break; + default: + break; + } + } +} + +void rt_hw_board_pm_sleep_deep_init(void) +{ +#if (PM_SLEEP_DEEP_CFG_CLK == PWC_STOP_CLK_KEEP) + _pm_sleep_common_init(RT_TRUE); +#else + _pm_sleep_common_init(RT_FALSE); + CLK_PLLCmd(DISABLE); + CLK_HrcCmd(DISABLE); + CLK_LrcCmd(DISABLE); + CLK_XtalCmd(DISABLE); + PWC_LDO_Cmd(PWC_LDO_PLL | PWC_LDO_HRC, DISABLE); +#endif +} + +void rt_hw_board_pm_sleep_shutdown_init(void) +{ + _pm_sleep_common_init(RT_TRUE); +} + +void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) +{ + switch (run_mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + SystemClock_Config(); + break; + + case PM_RUN_MODE_LOW_SPEED: + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); + + default: + break; + } +} +#endif + +#if defined(BSP_USING_QSPI) +rt_err_t rt_hw_qspi_board_init(void) +{ + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; +#ifndef BSP_QSPI_USING_SOFT_CS + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); +#endif + (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmra_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC); +#endif + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC); +#endif + return RT_EOK; +} +#endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h new file mode 100644 index 0000000000..0469ffb049 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" + + +/************************* XTAL port **********************/ +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_00) +#define XTAL_OUT_PIN (GPIO_PIN_01) + +/************************ USART port **********************/ +#if defined(BSP_USING_UART1) + #define USART1_RX_PORT (GPIO_PORT_A) + #define USART1_RX_PIN (GPIO_PIN_10) + #define USART1_RX_FUNC (GPIO_FUNC_33) + + #define USART1_TX_PORT (GPIO_PORT_A) + #define USART1_TX_PIN (GPIO_PIN_09) + #define USART1_TX_FUNC (GPIO_FUNC_32) +#endif + +#if defined(BSP_USING_UART2) + #define USART2_RX_PORT (GPIO_PORT_C) + #define USART2_RX_PIN (GPIO_PIN_11) + #define USART2_RX_FUNC (GPIO_FUNC_37) + + #define USART2_TX_PORT (GPIO_PORT_C) + #define USART2_TX_PIN (GPIO_PIN_10) + #define USART2_TX_FUNC (GPIO_FUNC_36) +#endif + +#if defined(BSP_USING_UART6) + #define USART6_RX_PORT (GPIO_PORT_D) + #define USART6_RX_PIN (GPIO_PIN_01) + #define USART6_RX_FUNC (GPIO_FUNC_55) + + #define USART6_TX_PORT (GPIO_PORT_D) + #define USART6_TX_PIN (GPIO_PIN_02) + #define USART6_TX_FUNC (GPIO_FUNC_54) +#endif + +/************************ I2C port **********************/ +#if defined(BSP_USING_I2C1) + #define I2C1_SDA_PORT (GPIO_PORT_E) + #define I2C1_SDA_PIN (GPIO_PIN_00) + #define I2C1_SDA_FUNC (GPIO_FUNC_48) + + #define I2C1_SCL_PORT (GPIO_PORT_E) + #define I2C1_SCL_PIN (GPIO_PIN_01) + #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#endif + +#if defined(BSP_USING_I2C2) // TODO, ch2 for test only + #define I2C2_SDA_PORT (GPIO_PORT_A) + #define I2C2_SDA_PIN (GPIO_PIN_09) + #define I2C2_SDA_FUNC (GPIO_FUNC_50) + + #define I2C2_SCL_PORT (GPIO_PORT_A) + #define I2C2_SCL_PIN (GPIO_PIN_10) + #define I2C2_SCL_FUNC (GPIO_FUNC_51) +#endif + + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) + #define ADC1_CH_PORT (GPIO_PORT_C) + #define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) + #define ADC2_CH_PORT (GPIO_PORT_C) + #define ADC2_CH_PIN (GPIO_PIN_01) +#endif + +#if defined(BSP_USING_ADC3) + #define ADC3_CH_PORT (GPIO_PORT_E) + #define ADC3_CH_PIN (GPIO_PIN_03) +#endif + +/*********** DAC configure *********/ +#if defined(BSP_USING_DAC1) + #define DAC1_CH1_PORT (GPIO_PORT_A) + #define DAC1_CH1_PIN (GPIO_PIN_04) + #define DAC1_CH2_PORT (GPIO_PORT_A) + #define DAC1_CH2_PIN (GPIO_PIN_05) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_CAN1) + #define CAN1_TX_PORT (GPIO_PORT_C) + #define CAN1_TX_PIN (GPIO_PIN_12) + #define CAN1_TX_PIN_FUNC (GPIO_FUNC_56) + + #define CAN1_RX_PORT (GPIO_PORT_D) + #define CAN1_RX_PIN (GPIO_PIN_00) + #define CAN1_RX_PIN_FUNC (GPIO_FUNC_57) +#endif + +#if defined(BSP_USING_CAN2) + #define CAN2_TX_PORT (GPIO_PORT_H) + #define CAN2_TX_PIN (GPIO_PIN_02) + #define CAN2_TX_PIN_FUNC (GPIO_FUNC_56) + + #define CAN2_RX_PORT (GPIO_PORT_E) + #define CAN2_RX_PIN (GPIO_PIN_04) + #define CAN2_RX_PIN_FUNC (GPIO_FUNC_57) +#endif + +/************************* SPI port ***********************/ +#if defined(BSP_USING_SPI1) + #define SPI1_CS_PORT (GPIO_PORT_C) + #define SPI1_CS_PIN (GPIO_PIN_07) + + #define SPI1_SCK_PORT (GPIO_PORT_B) + #define SPI1_SCK_PIN (GPIO_PIN_14) + #define SPI1_SCK_FUNC (GPIO_FUNC_47) + + #define SPI1_MOSI_PORT (GPIO_PORT_B) + #define SPI1_MOSI_PIN (GPIO_PIN_13) + #define SPI1_MOSI_FUNC (GPIO_FUNC_44) + + #define SPI1_MISO_PORT (GPIO_PORT_D) + #define SPI1_MISO_PIN (GPIO_PIN_09) + #define SPI1_MISO_FUNC (GPIO_FUNC_45) + + #define SPI1_WP_PORT (GPIO_PORT_D) + #define SPI1_WP_PIN (GPIO_PIN_10) + + #define SPI1_HOLD_PORT (GPIO_PORT_D) + #define SPI1_HOLD_PIN (GPIO_PIN_11) +#endif + +/************************ RTC/PM *****************************/ +#if defined(BSP_USING_RTC) || defined(RT_USING_PM) + #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + #define XTAL32_PORT (GPIO_PORT_C) + #define XTAL32_IN_PIN (GPIO_PIN_14) + #define XTAL32_OUT_PIN (GPIO_PIN_15) + #endif +#endif + +#if defined(RT_USING_PWM) + /*********** PWM_TMRA configure *********/ + #if defined(BSP_USING_PWM_TMRA_1) + #if defined(BSP_USING_PWM_TMRA_1_CH1) + #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) + #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH2) + #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) + #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH3) + #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) + #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_1_CH4) + #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) + #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) + #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) + #endif + #endif + + #if defined(BSP_USING_PWM_TMRA_2) + #if defined(BSP_USING_PWM_TMRA_2_CH1) + #define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00) + #define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_2_CH2) + #define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01) + #define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_2_CH3) + #define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02) + #define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4) + #endif + #if defined(BSP_USING_PWM_TMRA_2_CH4) + #define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A) + #define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03) + #define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4) + #endif + #endif + + /*********** PWM_TMR4 configure *********/ + #if defined(BSP_USING_PWM_TMR4_1) + #if defined(BSP_USING_PWM_TMR4_1_OUH) + #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08) + #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OUL) + #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07) + #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVH) + #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09) + #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OVL) + #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B) + #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00) + #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWH) + #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) + #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10) + #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) + #endif + #if defined(BSP_USING_PWM_TMR4_1_OWL) + #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) + #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01) + #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) + #endif + #endif + + /*********** PWM_TMR6 configure *********/ + #if defined(BSP_USING_PWM_TMR6_1) + #if defined(BSP_USING_PWM_TMR6_1_A) + #define PWM_TMR6_1_A_PORT (GPIO_PORT_A) + #define PWM_TMR6_1_A_PIN (GPIO_PIN_08) + #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #endif + #if defined(BSP_USING_PWM_TMR6_1_B) + #define PWM_TMR6_1_B_PORT (GPIO_PORT_A) + #define PWM_TMR6_1_B_PIN (GPIO_PIN_07) + #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif + #endif + +#endif + +#if defined(BSP_USING_QSPI) + #ifndef BSP_QSPI_USING_SOFT_CS + /* QSSN */ + #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) + #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) + #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7) + #endif + /* QSCK */ + #define QSPI_FLASH_SCK_PORT (GPIO_PORT_B) + #define QSPI_FLASH_SCK_PIN (GPIO_PIN_14) + #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7) + /* QSIO0 */ + #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) + #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) + #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7) + /* QSIO1 */ + #define QSPI_FLASH_IO1_PORT (GPIO_PORT_D) + #define QSPI_FLASH_IO1_PIN (GPIO_PIN_09) + #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7) + /* QSIO2 */ + #define QSPI_FLASH_IO2_PORT (GPIO_PORT_D) + #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) + #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7) + /* QSIO3 */ + #define QSPI_FLASH_IO3_PORT (GPIO_PORT_D) + #define QSPI_FLASH_IO3_PIN (GPIO_PIN_11) + #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7) +#endif + +/*********** TMRA_PULSE_ENCODER configure *********/ +#if defined(RT_USING_PULSE_ENCODER) + #if defined(BSP_USING_TMRA_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) + #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) + #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) + #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + #endif /* BSP_USING_TMRA_PULSE_ENCODER */ + + #if defined(BSP_USING_TMR6_PULSE_ENCODER) + #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_08) + #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) + #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_A) + #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_07) + #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) + #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#endif /* RT_USING_PULSE_ENCODER */ + +#endif + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h new file mode 100644 index 0000000000..7fdc0d3e0f --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_INIT_PARAMS */ + +#if defined (BSP_ADC1_USING_DMA) +#ifndef ADC1_EOCA_DMA_CONFIG +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC1_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC1_USING_DMA */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_INIT_PARAMS */ + +#if defined (BSP_ADC2_USING_DMA) +#ifndef ADC2_EOCA_DMA_CONFIG +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC2_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC2_USING_DMA */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_A, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_INIT_PARAMS */ + +#if defined (BSP_ADC3_USING_DMA) +#ifndef ADC3_EOCA_DMA_CONFIG +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC3_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC3_USING_DMA */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/can_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/can_config.h new file mode 100644 index 0000000000..eb25e85687 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/can_config.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CAN1 +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#ifdef RT_CAN_USING_CANFD +#define CAN1_CANFD_MODE (CAN_FD_MD_ISO) +#endif +#define CAN1_NAME ("can1") +#ifndef CAN1_INIT_PARAMS +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN1_INIT_PARAMS */ +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CAN2 +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#ifdef RT_CAN_USING_CANFD +#define CAN2_CANFD_MODE (CAN_FD_MD_ISO) +#endif +#define CAN2_NAME ("can2") +#ifndef CAN2_INIT_PARAMS +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN2_INIT_PARAMS */ +#endif /* BSP_USING_CAN2 */ + +/* Bit time config + Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + + Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + TQ = u32Prescaler / CANClock. + Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + + The following bit time configures are based on CAN Clock 40M +*/ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h new file mode 100644 index 0000000000..10de0c1734 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_INIT_PARAMS +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + } +#endif /* DAC1_INIT_PARAMS */ +#endif /* BSP_USING_DAC1 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_INIT_PARAMS +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + } +#endif /* DAC2_INIT_PARAMS */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h new file mode 100644 index 0000000000..6a84329063 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 + +#elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH0 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 + +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 + +#elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH1 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 + +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 + +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 + + +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 + +#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 + +#endif + +/* DMA1 ch4 */ +#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) +#define UART5_RX_DMA_INSTANCE CM_DMA1 +#define UART5_RX_DMA_CHANNEL DMA_CH4 +#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 + +#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) +#define UART5_TX_DMA_INSTANCE CM_DMA1 +#define UART5_TX_DMA_CHANNEL DMA_CH5 +#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 + +#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +/* DMA2 ch4 */ +#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_RX_DMA_INSTANCE CM_DMA2 +#define UART4_RX_DMA_CHANNEL DMA_CH4 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#endif + +/* DMA2 ch5 */ +#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) +#define UART4_TX_DMA_INSTANCE CM_DMA2 +#define UART4_TX_DMA_CHANNEL DMA_CH5 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h new file mode 100644 index 0000000000..a0bbb41e1a --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h new file mode 100644 index 0000000000..8f7c6b6296 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_I2C1) +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C1_CONFIG */ +#endif + +#if defined(BSP_I2C1_USING_DMA) +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ + +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_USING_DMA */ + +#if defined(BSP_USING_I2C2) +#ifndef I2C2_CONFIG +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C2_CONFIG */ + +#if defined(BSP_I2C2_USING_DMA) +#ifndef I2C2_TX_DMA_CONFIG +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_TX_DMA_CONFIG */ + +#ifndef I2C2_RX_DMA_CONFIG +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C3) +#ifndef I2C3_CONFIG +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C3_CONFIG */ + +#if defined(BSP_I2C3_USING_DMA) +#ifndef I2C3_TX_DMA_CONFIG +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_TX_DMA_CONFIG */ + +#ifndef I2C3_RX_DMA_CONFIG +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C4) +#ifndef I2C4_CONFIG +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C4_CONFIG */ + +#if defined(BSP_I2C4_USING_DMA) +#ifndef I2C4_TX_DMA_CONFIG +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_TX_DMA_CONFIG */ + +#ifndef I2C4_RX_DMA_CONFIG +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C5) +#ifndef I2C5_CONFIG +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C5_CONFIG */ + +#if defined(BSP_I2C5_USING_DMA) +#ifndef I2C5_TX_DMA_CONFIG +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_TX_DMA_CONFIG */ + +#ifndef I2C5_RX_DMA_CONFIG +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_RX_DMA_CONFIG */ +#endif /* BSP_I2C5_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C6) +#ifndef I2C6_CONFIG +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C6_CONFIG */ + +#if defined(BSP_I2C6_USING_DMA) +#ifndef I2C6_TX_DMA_CONFIG +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_TX_DMA_CONFIG */ + +#ifndef I2C6_RX_DMA_CONFIG +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_RX_DMA_CONFIG */ +#endif /* BSP_I2C6_USING_DMA */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h new file mode 100644 index 0000000000..90d8d4f7ad --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch5 */ +#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_UART1) +#define BSP_UART1_IRQ_NUM USART1_IRQn +#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_IRQ_NUM USART2_IRQn +#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_IRQ_NUM USART3_IRQn +#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_IRQ_NUM USART4_IRQn +#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#define BSP_UART5_IRQ_NUM USART5_IRQn +#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \ + defined(RT_USING_SERIAL_V2) +#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn +#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#define BSP_UART6_IRQ_NUM USART6_IRQn +#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_SPI1) +#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI2) +#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI3) +#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_TMRA_1) +#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_1 */ + +#if defined(BSP_USING_TMRA_2) +#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_2 */ + +#if defined(BSP_USING_TMRA_3) +#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_3 */ + +#if defined(BSP_USING_TMRA_4) +#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_4 */ + +#if defined(BSP_USING_TMRA_5) +#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_5 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM MCAN1_INT0_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_CAN1 */ + +#if defined(RT_USING_ALARM) +#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* RT_USING_ALARM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h new file mode 100644 index 0000000000..e77cc0f20e --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __PM_CONFIG_H__ +#define __PM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PM +extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); + +#ifndef PM_TICKLESS_TIMER_ENABLE_MASK +#define PM_TICKLESS_TIMER_ENABLE_MASK \ +( (1UL << PM_SLEEP_MODE_IDLE) | \ + (1UL << PM_SLEEP_MODE_DEEP)) +#endif + +/** + * @brief run mode config @ref pm_run_mode_config structure + */ +#ifndef PM_RUN_MODE_CFG +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ + } +#endif /* PM_RUN_MODE_CFG */ + +/** + * @brief sleep idle config @ref pm_sleep_mode_idle_config structure + */ +#ifndef PM_SLEEP_IDLE_CFG +#define PM_SLEEP_IDLE_CFG \ +{ \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ +} +#endif /*PM_SLEEP_IDLE_CFG*/ + +/** + * @brief sleep deep config @ref pm_sleep_mode_deep_config structure + */ +#ifndef PM_SLEEP_DEEP_CFG +#define PM_SLEEP_DEEP_CFG \ +{ \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ +} +#endif /*PM_SLEEP_DEEP_CFG*/ + +/** + * @brief sleep standby config @ref pm_sleep_mode_standby_config structure + */ +#ifndef PM_SLEEP_STANDBY_CFG +#define PM_SLEEP_STANDBY_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_STANDBY_CFG*/ + +/** + * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure + */ +#ifndef PM_SLEEP_SHUTDOWN_CFG +#define PM_SLEEP_SHUTDOWN_CFG \ +{ \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ +} +#endif /*PM_SLEEP_SHUTDOWN_CFG*/ + +#endif /* BSP_USING_PM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h new file mode 100644 index 0000000000..47a947c6ab --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h @@ -0,0 +1,545 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_PULSE_ENCODER) + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 +#ifndef PULSE_ENCODER_TMRA_1_CONFIG +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_1, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_1_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_1_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ + } +#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 +#ifndef PULSE_ENCODER_TMRA_2_CONFIG +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_2, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_2_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_2_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ + } +#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 +#ifndef PULSE_ENCODER_TMRA_3_CONFIG +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_3, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_3_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_3_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ + } +#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 +#ifndef PULSE_ENCODER_TMRA_4_CONFIG +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_4, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_4_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_4_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ + } +#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 +#ifndef PULSE_ENCODER_TMRA_5_CONFIG +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_5, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_5_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_5_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ + } +#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_6 +#ifndef PULSE_ENCODER_TMRA_6_CONFIG +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_6, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_6_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_6_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ + } +#endif /* PULSE_ENCODER_TMRA_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_7 +#ifndef PULSE_ENCODER_TMRA_7_CONFIG +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_7, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_7_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_7_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ + } +#endif /* PULSE_ENCODER_TMRA_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_8 +#ifndef PULSE_ENCODER_TMRA_8_CONFIG +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_8, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_8_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_8_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ + } +#endif /* PULSE_ENCODER_TMRA_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_9 +#ifndef PULSE_ENCODER_TMRA_9_CONFIG +#define PULSE_ENCODER_TMRA_9_CONFIG \ + { \ + .tmr_handler = CM_TMRA_9, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_9, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_9_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_9_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a9" \ + } +#endif /* PULSE_ENCODER_TMRA_9_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_10 +#ifndef PULSE_ENCODER_TMRA_10_CONFIG +#define PULSE_ENCODER_TMRA_10_CONFIG \ + { \ + .tmr_handler = CM_TMRA_10, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_10, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_10_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_10_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a10" \ + } +#endif /* PULSE_ENCODER_TMRA_10_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_11 +#ifndef PULSE_ENCODER_TMRA_11_CONFIG +#define PULSE_ENCODER_TMRA_11_CONFIG \ + { \ + .tmr_handler = CM_TMRA_11, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_11, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_11_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_11_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a11" \ + } +#endif /* PULSE_ENCODER_TMRA_11_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_12 +#ifndef PULSE_ENCODER_TMRA_12_CONFIG +#define PULSE_ENCODER_TMRA_12_CONFIG \ + { \ + .tmr_handler = CM_TMRA_12, \ + .u32Fcg2Periph = FCG2_PERIPH_TMRA_12, \ + .hw_count = \ + { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMRA_12_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMRA_12_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a12" \ + } +#endif /* PULSE_ENCODER_TMRA_12_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 +#ifndef PULSE_ENCODER_TMR6_1_CONFIG +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_1, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_1_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_1_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ + } +#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 +#ifndef PULSE_ENCODER_TMR6_2_CONFIG +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_2, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_2_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_2_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ + } +#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_3 +#ifndef PULSE_ENCODER_TMR6_3_CONFIG +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_3, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_3_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_3_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ + } +#endif /* PULSE_ENCODER_TMR6_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_4 +#ifndef PULSE_ENCODER_TMR6_4_CONFIG +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_4, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_4_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_4_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ + } +#endif /* PULSE_ENCODER_TMR6_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_5 +#ifndef PULSE_ENCODER_TMR6_5_CONFIG +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_5, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_5_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_5_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ + } +#endif /* PULSE_ENCODER_TMR6_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_6 +#ifndef PULSE_ENCODER_TMR6_6_CONFIG +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_6, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_6_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_6_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ + } +#endif /* PULSE_ENCODER_TMR6_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_7 +#ifndef PULSE_ENCODER_TMR6_7_CONFIG +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_7, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_7_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_7_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ + } +#endif /* PULSE_ENCODER_TMR6_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_8 +#ifndef PULSE_ENCODER_TMR6_8_CONFIG +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32Fcg2Periph = FCG2_PERIPH_TMR6_8, \ + .hw_count = \ + { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = \ + { \ + .enIntSrc_OVF = INT_SRC_TMR6_8_OVF, \ + .enIRQn_OVF = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_OVF = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_UDF = INT_SRC_TMR6_8_UDF, \ + .enIRQn_UDF = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_UDF = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ + } +#endif /* PULSE_ENCODER_TMR6_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ + +#endif /* RT_USING_PULSE_ENCODER */ + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h new file mode 100644 index 0000000000..f20d64d50d --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h @@ -0,0 +1,882 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __PWM_TMR_CONFIG_H__ +#define __PWM_TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM_TMRA + +#ifdef BSP_USING_PWM_TMRA_1 +#ifndef PWM_TMRA_1_CONFIG +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_1_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_1 */ + +#ifdef BSP_USING_PWM_TMRA_2 +#ifndef PWM_TMRA_2_CONFIG +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_2_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_2 */ + +#ifdef BSP_USING_PWM_TMRA_3 +#ifndef PWM_TMRA_3_CONFIG +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_3_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_3 */ + +#ifdef BSP_USING_PWM_TMRA_4 +#ifndef PWM_TMRA_4_CONFIG +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_4_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_4 */ + +#ifdef BSP_USING_PWM_TMRA_5 +#ifndef PWM_TMRA_5_CONFIG +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_5_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_5 */ + +#ifdef BSP_USING_PWM_TMRA_6 +#ifndef PWM_TMRA_6_CONFIG +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_6_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_6 */ + +#ifdef BSP_USING_PWM_TMRA_7 +#ifndef PWM_TMRA_7_CONFIG +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_7_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_7 */ + +#ifdef BSP_USING_PWM_TMRA_8 +#ifndef PWM_TMRA_8_CONFIG +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_8_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_8 */ + +#ifdef BSP_USING_PWM_TMRA_9 +#ifndef PWM_TMRA_9_CONFIG +#define PWM_TMRA_9_CONFIG \ + { \ + .name = "pwm_a9", \ + .instance = CM_TMRA_9, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_9_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_9 */ + +#ifdef BSP_USING_PWM_TMRA_10 +#ifndef PWM_TMRA_10_CONFIG +#define PWM_TMRA_10_CONFIG \ + { \ + .name = "pwm_a10", \ + .instance = CM_TMRA_10, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_10_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_10 */ + +#ifdef BSP_USING_PWM_TMRA_11 +#ifndef PWM_TMRA_11_CONFIG +#define PWM_TMRA_11_CONFIG \ + { \ + .name = "pwm_a11", \ + .instance = CM_TMRA_11, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_11_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_11 */ + +#ifdef BSP_USING_PWM_TMRA_12 +#ifndef PWM_TMRA_12_CONFIG +#define PWM_TMRA_12_CONFIG \ + { \ + .name = "pwm_a12", \ + .instance = CM_TMRA_12, \ + .channel = 0, \ + .stcTmraInit = \ + { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = \ + { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ + }, \ + .stcPwmInit = \ + { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_12_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_12 */ + +#endif /* BSP_USING_PWM_TMRA */ + +#ifdef BSP_USING_PWM_TMR4 + +#ifdef BSP_USING_PWM_TMR4_1 +#ifndef PWM_TMR4_1_CONFIG +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_1 */ + +#ifdef BSP_USING_PWM_TMR4_2 +#ifndef PWM_TMR4_2_CONFIG +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_2 */ + +#ifdef BSP_USING_PWM_TMR4_3 +#ifndef PWM_TMR4_3_CONFIG +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = \ + { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ + }, \ + .stcTmr4OcInit = \ + { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = \ + { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ + }, \ + } +#endif /* PWM_TMR4_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_3 */ + +#endif /* BSP_USING_PWM_TMR4 */ + +#ifdef BSP_USING_PWM_TMR6 + +#ifdef BSP_USING_PWM_TMR6_1 +#ifndef PWM_TMR6_1_CONFIG +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_1 */ +#ifdef BSP_USING_PWM_TMR6_2 +#ifndef PWM_TMR6_2_CONFIG +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_2 */ +#ifdef BSP_USING_PWM_TMR6_3 +#ifndef PWM_TMR6_3_CONFIG +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_3 */ +#ifdef BSP_USING_PWM_TMR6_4 +#ifndef PWM_TMR6_4_CONFIG +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_4_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_4 */ +#ifdef BSP_USING_PWM_TMR6_5 +#ifndef PWM_TMR6_5_CONFIG +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_5_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_5 */ +#ifdef BSP_USING_PWM_TMR6_6 +#ifndef PWM_TMR6_6_CONFIG +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_6_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_6 */ +#ifdef BSP_USING_PWM_TMR6_7 +#ifndef PWM_TMR6_7_CONFIG +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_7_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_7 */ +#ifdef BSP_USING_PWM_TMR6_8 +#ifndef PWM_TMR6_8_CONFIG +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = \ + { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = \ + { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = \ + { \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } \ + }, \ + } +#endif /* PWM_TMR6_8_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_8 */ + +#endif /* BSP_USING_PWM_TMR6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_TMRA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h new file mode 100644 index 0000000000..f9df3687d2 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ + } +#endif /* QSPI_BUS_CONFIG */ + +#ifndef QSPI_INIT_PARAMS +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ + } +#endif /* QSPI_INIT_PARAMS */ + +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QSPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h new file mode 100644 index 0000000000..3495e6ec34 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = \ + { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h new file mode 100644 index 0000000000..6ac1e5a681 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __TMR_CONFIG_H__ +#define __TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TMRA_1 +#ifndef TMRA_1_CONFIG +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ + } +#endif /* TMRA_1_CONFIG */ +#endif /* BSP_USING_TMRA_1 */ + +#ifdef BSP_USING_TMRA_2 +#ifndef TMRA_2_CONFIG +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ + } +#endif /* TMRA_2_CONFIG */ +#endif /* BSP_USING_TMRA_2 */ + +#ifdef BSP_USING_TMRA_3 +#ifndef TMRA_3_CONFIG +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ + } +#endif /* TMRA_3_CONFIG */ +#endif /* BSP_USING_TMRA_3 */ + +#ifdef BSP_USING_TMRA_4 +#ifndef TMRA_4_CONFIG +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ + } +#endif /* TMRA_4_CONFIG */ +#endif /* BSP_USING_TMRA_4 */ + +#ifdef BSP_USING_TMRA_5 +#ifndef TMRA_5_CONFIG +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = \ + { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ + } +#endif /* TMRA_5_CONFIG */ +#endif /* BSP_USING_TMRA_5 */ +#endif /* __TMR_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h new file mode 100644 index 0000000000..c1ac81ae9e --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .irq_num = BSP_UART1_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART1_EI, \ + .rx_int_src = INT_SRC_USART1_RI, \ + .tx_int_src = INT_SRC_USART1_TI, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#endif /* UART1_TX_CPLT_CONFIG */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .irq_num = BSP_UART2_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART2_EI, \ + .rx_int_src = INT_SRC_USART2_RI, \ + .tx_int_src = INT_SRC_USART2_TI, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#endif /* UART2_TX_CPLT_CONFIG */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .irq_num = BSP_UART3_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART3_EI, \ + .rx_int_src = INT_SRC_USART3_RI, \ + .tx_int_src = INT_SRC_USART3_TI, \ + } +#endif /* UART3_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#endif /* UART3_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .irq_num = BSP_UART4_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART4_EI, \ + .rx_int_src = INT_SRC_USART4_RI, \ + .tx_int_src = INT_SRC_USART4_TI, \ + } +#endif /* UART4_CONFIG */ + +#if defined(BSP_UART4_RX_USING_DMA) +#ifndef UART4_DMA_RX_CONFIG +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .flag = UART4_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART4_DMA_RX_CONFIG */ + +#ifndef UART4_RXTO_CONFIG +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + } +#endif /* UART4_RXTO_CONFIG */ +#endif /* BSP_UART4_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#endif /* UART4_TX_CPLT_CONFIG */ + +#if defined(BSP_UART4_TX_USING_DMA) +#ifndef UART4_DMA_TX_CONFIG +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .flag = UART4_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART4_DMA_TX_CONFIG */ +#endif /* BSP_UART4_TX_USING_DMA */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .irq_num = BSP_UART5_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART5_EI, \ + .rx_int_src = INT_SRC_USART5_RI, \ + .tx_int_src = INT_SRC_USART5_TI, \ + } +#endif /* UART5_CONFIG */ + +#if defined(BSP_UART5_RX_USING_DMA) +#ifndef UART5_DMA_RX_CONFIG +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .channel = UART5_RX_DMA_CHANNEL, \ + .clock = UART5_RX_DMA_CLOCK, \ + .trigger_select = UART5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_RI, \ + .flag = UART5_RX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART5_RX_DMA_IRQn, \ + .irq_prio = UART5_RX_DMA_INT_PRIO, \ + .int_src = UART5_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART5_DMA_RX_CONFIG */ + +#ifndef UART5_RXTO_CONFIG +#define UART5_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + } +#endif /* UART5_RXTO_CONFIG */ +#endif /* BSP_UART5_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_TX_CPLT_CONFIG +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART5_TX_CPLT_CONFIG +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ + } +#endif +#endif /* UART5_TX_CPLT_CONFIG */ + +#if defined(BSP_UART5_TX_USING_DMA) +#ifndef UART5_DMA_TX_CONFIG +#define UART5_DMA_TX_CONFIG \ + { \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .channel = UART5_TX_DMA_CHANNEL, \ + .clock = UART5_TX_DMA_CLOCK, \ + .trigger_select = UART5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_TI, \ + .flag = UART5_TX_DMA_TRANS_FLAG, \ + .irq_config = \ + { \ + .irq_num = UART5_TX_DMA_IRQn, \ + .irq_prio = UART5_TX_DMA_INT_PRIO, \ + .int_src = UART5_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART5_DMA_TX_CONFIG */ +#endif /* BSP_UART5_TX_USING_DMA */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .irq_num = BSP_UART6_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART6_EI, \ + .rx_int_src = INT_SRC_USART6_RI, \ + .tx_int_src = INT_SRC_USART6_TI, \ + } +#endif /* UART6_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = \ + { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#endif /* UART6_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART6 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h new file mode 100644 index 0000000000..64b5b592da --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/drv_config.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "dac_config.h" +#include "gpio_config.h" +#include "can_config.h" +#include "pm_config.h" +#include "i2c_config.h" +#include "qspi_config.h" +#include "pulse_encoder_config.h" +#include "timer_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h new file mode 100644 index 0000000000..438f04eaee --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h @@ -0,0 +1,136 @@ +/** + ******************************************************************************* + * @file template/source/hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MCAN_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F448_LQFP80 (9U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (BSP_EV_HC32F448_LQFP80) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS61LV6416_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_INT_KEY_ENABLE (DDL_OFF) + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf new file mode 100644 index 0000000000..f9aef6bc41 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.icf @@ -0,0 +1,103 @@ +/***************************************************************************//** + * \file HC32F448.icf + * \version 1.0 + * + * \brief Linker file for the IAR compiler. + * +******************************************************************************** +* \copyright + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause +*******************************************************************************/ + +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ + +// Check that necessary symbols have been passed to linker via command line interface +if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) { + error "Link location not defined or not supported!"; +} +if((!isdefinedsymbol(_HC32F448_256K_)) && (!isdefinedsymbol(_HC32F448_128K_))) { + error "Mcu type or size not defined or not supported!"; +} + + +/******************************************************************************* + * Memory address and size definitions + ******************************************************************************/ +define symbol ram1_base_address = 0x1FFF8000; +define symbol ram1_end_address = 0x20007FFF; +if(isdefinedsymbol(_LINK_RAM_)) { + define symbol ram_start_reserve = 0x8000; + define symbol rom1_base_address = ram1_base_address; + define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; +} else { + define symbol ram_start_reserve = 0x0; + define symbol rom1_base_address = 0x0; + define symbol rom2_base_address = 0x03000C00; + define symbol rom2_end_address = 0x03000FFF; + + if(isdefinedsymbol(_HC32F448_256K_)) { + define symbol rom1_end_address = 0x0003FFFF; + } else if (isdefinedsymbol(_HC32F448_128K_)) { + define symbol rom1_end_address = 0x0001FFFF; + } +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = rom1_base_address; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address; +define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address; +define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address; +define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve; +define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0xC00; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x400; +/**** End of ICF editor section. ###ICF###*/ + +/******************************************************************************* + * Memory definitions + ******************************************************************************/ +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region OTP_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in OTP_region { readonly section .otp_data }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.ld new file mode 100644 index 0000000000..5d60e06992 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.ld @@ -0,0 +1,270 @@ +/****************************************************************************** + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F448xC.ld */ +/* Abstract Linker script for HC32F448 Device with */ +/* 256KByte FLASH, 68KByte RAM */ +/* Version V1.0 */ +/* Date 2023-05-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 16 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 1024; +__OTP_LOCK_START = 0x03000A80; +__OTP_LOCK_SIZE = 128; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 64K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + __bss_start = .; + .bss __StackTop (NOLOAD): + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + . = ALIGN(4); + *(.noinit*) + . = ALIGN(4); + } >RAM + __bss_end = .; + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.sct new file mode 100644 index 0000000000..92f3940d28 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/linker_scripts/link.sct @@ -0,0 +1,22 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00040000 { ; load region size_region + ER_IROM1 0x00000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFF8000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFF8008 0x0000FFF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/SConscript b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/SConscript new file mode 100644 index 0000000000..3c57bc9c6d --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/SConscript @@ -0,0 +1,12 @@ +import os +from building import * + +objs = [] +cwd = GetCurrentDir() + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + objs = objs + SConscript(os.path.join(item, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/drv_spi_flash.c b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/drv_spi_flash.c new file mode 100644 index 0000000000..5e69545c7b --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/drv_spi_flash.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef BSP_USING_SPI_FLASH + +#include "spi_flash.h" +#ifdef RT_USING_SFUD + #include "spi_flash_sfud.h" +#endif + +#define SPI_BUS_NAME "spi1" +#define SPI_FLASH_DEVICE_NAME "spi10" +#define SPI_FLASH_CHIP "w25q64" +#define SPI_FLASH_SS_PORT GPIO_PORT_C +#define SPI_FLASH_SS_PIN GPIO_PIN_07 +/* Partition Name */ +#define FS_PARTITION_NAME "filesystem" + +#ifdef RT_USING_SFUD +static void rt_hw_spi_flash_reset(char *spi_dev_name) +{ + struct rt_spi_device *spi_dev_w25; + rt_uint8_t w25_en_reset = 0x66; + rt_uint8_t w25_reset_dev = 0x99; + + spi_dev_w25 = (struct rt_spi_device *)rt_device_find(spi_dev_name); + if (!spi_dev_w25) + { + rt_kprintf("Can't find %s device!\n", spi_dev_name); + } + else + { + rt_spi_send(spi_dev_w25, &w25_en_reset, 1U); + rt_spi_send(spi_dev_w25, &w25_reset_dev, 1U); + DDL_DelayMS(1U); + rt_kprintf("Reset ext flash!\n"); + } +} + +static int rt_hw_spi_flash_with_sfud_init(void) +{ + rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, SPI_FLASH_SS_PORT, SPI_FLASH_SS_PIN); + + if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME)) + { + rt_hw_spi_flash_reset(SPI_FLASH_DEVICE_NAME); + if (RT_NULL == rt_sfud_flash_probe(SPI_FLASH_CHIP, SPI_FLASH_DEVICE_NAME)) + { + return -RT_ERROR; + } + } + + return RT_EOK; +} +INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); + +static int rt_hw_fs_init(void) +{ + struct rt_device *mtd_dev = RT_NULL; + + /* 初始化 fal */ + fal_init(); + /* 生成 mtd 设备 */ + mtd_dev = fal_mtd_nor_device_create(FS_PARTITION_NAME); + if (!mtd_dev) + { + LOG_E("Can't create a mtd device on '%s' partition.", FS_PARTITION_NAME); + return -RT_ERROR; + } + else + { + /* 挂载 littlefs */ + if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0)) + { + LOG_I("Filesystem initialized!"); + return RT_EOK; + } + else + { + /* 格式化文件系统 */ + if (RT_EOK == dfs_mkfs("lfs", FS_PARTITION_NAME)) + { + /* 挂载 littlefs */ + if (RT_EOK == dfs_mount(FS_PARTITION_NAME, "/", "lfs", 0, 0)) + { + LOG_I("Filesystem initialized!"); + return RT_EOK; + } + else + { + LOG_E("Failed to initialize filesystem!"); + return -RT_ERROR; + } + } + else + { + LOG_E("Failed to Format fs!"); + return -RT_ERROR; + } + } + } +} +INIT_APP_EXPORT(rt_hw_fs_init); + +#endif /* RT_USING_SFUD */ + +#endif /* BSP_USING_SPI_FLASH */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/SConscript b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/SConscript new file mode 100644 index 0000000000..cee47c2d7e --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/SConscript @@ -0,0 +1,20 @@ + +from building import * +import rtconfig + +cwd = GetCurrentDir() + +src = [] + +src += Glob('*.c') +CPPPATH = [cwd] +LOCAL_CFLAGS = '' + +if rtconfig.PLATFORM in ['gcc', 'armclang']: + LOCAL_CFLAGS += ' -std=c99' +elif rtconfig.PLATFORM in ['armcc']: + LOCAL_CFLAGS += ' --c99' + +group = DefineGroup('FAL', src, depend = ['RT_USING_FAL'], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS) + +Return('group') diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_cfg.h b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_cfg.h new file mode 100644 index 0000000000..1f8fb29c76 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_cfg.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* enable hc32f4 onchip flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_HC32F4 +/* enable SFUD flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_SFUD + +extern const struct fal_flash_dev hc32_onchip_flash; +extern struct fal_flash_dev ext_nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ +{ \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ +} + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ +{ \ + {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 256 * 1024, 0}, \ + {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ +} +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_flash_sfud_port.c b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_flash_sfud_port.c new file mode 100644 index 0000000000..c1b7851309 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal/fal_flash_sfud_port.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include + +#include +#ifdef RT_USING_SFUD + #include +#endif + +#ifndef FAL_USING_NOR_FLASH_DEV_NAME + #define FAL_USING_NOR_FLASH_DEV_NAME "w25q64" +#endif + +static int init(void); +static int read(long offset, uint8_t *buf, size_t size); +static int write(long offset, const uint8_t *buf, size_t size); +static int erase(long offset, size_t size); + +static sfud_flash_t sfud_dev = NULL; +struct fal_flash_dev ext_nor_flash0 = +{ + .name = FAL_USING_NOR_FLASH_DEV_NAME, + .addr = 0, + .len = 8 * 1024 * 1024, + .blk_size = 4096, + .ops = {init, read, write, erase}, + .write_gran = 1 +}; + +static int init(void) +{ + /* RT-Thread RTOS platform */ + sfud_dev = rt_sfud_flash_find_by_dev_name(FAL_USING_NOR_FLASH_DEV_NAME); + if (NULL == sfud_dev) + { + return -1; + } + /* update the flash chip information */ + ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran; + ext_nor_flash0.len = sfud_dev->chip.capacity; + + return 0; +} + +static int read(long offset, uint8_t *buf, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + sfud_read(sfud_dev, ext_nor_flash0.addr + offset, size, buf); + + return size; +} + +static int write(long offset, const uint8_t *buf, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + if (sfud_write(sfud_dev, ext_nor_flash0.addr + offset, size, buf) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} + +static int erase(long offset, size_t size) +{ + assert(sfud_dev); + assert(sfud_dev->init_ok); + if (sfud_erase(sfud_dev, ext_nor_flash0.addr + offset, size) != SFUD_SUCCESS) + { + return -1; + } + + return size; +} diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.c b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.c new file mode 100644 index 0000000000..40f9a91a98 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.c @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#include +#include +#include + +#ifdef BSP_USING_TCA9539 + +#include "tca9539.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Define for TCA9539 */ +#define BSP_TCA9539_I2C_BUS_NAME "i2c1" +#define BSP_TCA9539_DEV_ADDR (0x74U) + +#define TCA9539_RST_PIN (32) /* PB15 */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static struct rt_i2c_bus_device *i2c_bus = RT_NULL; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @brief BSP TCA9539 write data. + * @param [in] bus: Pointer to the i2c bus device. + * @param [in] reg: Register to be written. + * @param [in] data: The pointer to the buffer contains the data to be written. + * @param [in] len: Buffer size in byte. + * @retval rt_err_t: + * - RT_EOK + * - -RT_ERROR + */ +static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len) +{ + struct rt_i2c_msg msgs; + rt_uint8_t buf[6]; + + buf[0] = reg; + if (len > 0) + { + if (len < 6) + { + rt_memcpy(buf + 1, data, len); + } + else + { + return -RT_ERROR; + } + } + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = len + 1; + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + +/** + * @brief BSP TCA9539 Read data. + * @param [in] bus: Pointer to the i2c bus device. + * @param [in] reg: Register to be read. + * @param [out] data: The pointer to the buffer contains the data to be read. + * @param [in] len: Buffer size in byte. + * @retval rt_err_t: + * - RT_EOK + * - -RT_ERROR + */ +static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t reg, rt_uint8_t *data, rt_uint16_t len) +{ + struct rt_i2c_msg msgs; + + if (RT_EOK != BSP_TCA9539_I2C_Write(bus, reg, RT_NULL, 0)) + { + return -RT_ERROR; + } + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_RD; + msgs.buf = data; + msgs.len = len; + if (rt_i2c_transfer(bus, &msgs, 1) == 1) + { + return RT_EOK; + } + else + { + return -RT_ERROR; + } +} + + +/** + * @brief Reset TCA9539. + * @param [in] None + * @retval None + */ +static void TCA9539_Reset(void) +{ + rt_pin_mode(TCA9539_RST_PIN, PIN_MODE_OUTPUT); + /* Reset the device */ + rt_pin_write(TCA9539_RST_PIN, PIN_LOW); + rt_thread_mdelay(3U); + rt_pin_write(TCA9539_RST_PIN, PIN_HIGH); +} + +/** + * @brief Write TCA9539 pin output value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8PinState Pin state to be written. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Pin_State_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + if (0U == u8PinState) + { + u8TempData[1] &= (uint8_t)(~u8Pin); + } + else + { + u8TempData[1] |= u8Pin; + } + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Read TCA9539 pin input value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8PinState Pin state to be written. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Pin_State_Definition + * @retval rt_err_t: + * - RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + if (0U != (u8TempData[1] & u8Pin)) + { + *pu8PinState = TCA9539_PIN_SET; + } + else + { + *pu8PinState = TCA9539_PIN_RESET; + } + + return RT_EOK; +} + +/** + * @brief Toggle TCA9539 pin output value. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @retval rt_err_t: + * - -RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + u8TempData[1] ^= u8Pin; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Configuration TCA9539 pin. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Port_Definition + * @param [in] u8Pin Pin number. + * This parameter can be one or any combination of the following values: + * @arg @ref TCA9539_Pin_Definition + * @param [in] u8Dir Pin output direction. + * This parameter can be one of the following values: + * @arg @ref TCA9539_Direction_Definition + * @retval rt_err_t: + * - -RT_ERROR + * - RT_EOK + */ +rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir) +{ + uint8_t u8TempData[2]; + + u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0; + if (RT_EOK != BSP_TCA9539_I2C_Read(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + if (TCA9539_DIR_OUT == u8Dir) + { + u8TempData[1] &= (uint8_t)(~u8Pin); + } + else + { + u8TempData[1] |= u8Pin; + } + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} + +/** + * @brief Initialize TCA9539. + * @param [in] None + * @retval rt_err_t: + * - -RT_ERROR + * - RT_EOK + */ +int TCA9539_Init(void) +{ + char name[RT_NAME_MAX]; + uint8_t u8TempData[2]; + + TCA9539_Reset(); + rt_strncpy(name, BSP_TCA9539_I2C_BUS_NAME, RT_NAME_MAX); + i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(name); + if (i2c_bus == RT_NULL) + { + rt_kprintf("can't find %s device!\n", BSP_TCA9539_I2C_BUS_NAME); + return -RT_ERROR; + } + /* All Pins are input as default */ + u8TempData[0] = TCA9539_REG_CONFIG_PORT0; + u8TempData[1] = 0xFFU; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + u8TempData[0] = TCA9539_REG_CONFIG_PORT1; + if (RT_EOK != BSP_TCA9539_I2C_Write(i2c_bus, u8TempData[0], &u8TempData[1], 1U)) + { + return -RT_ERROR; + } + + return RT_EOK; +} +INIT_PREV_EXPORT(TCA9539_Init); + +#endif /* BSP_USING_TCA9539 */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.h b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.h new file mode 100644 index 0000000000..097f3a0675 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-20 CDT first version + */ + +#ifndef __TCA9539_H__ +#define __TCA9539_H__ + +#include + +/** + * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition + * @{ + */ +#define TCA9539_REG_INPUT_PORT0 (0x00U) +#define TCA9539_REG_INPUT_PORT1 (0x01U) +#define TCA9539_REG_OUTPUT_PORT0 (0x02U) +#define TCA9539_REG_OUTPUT_PORT1 (0x03U) +#define TCA9539_REG_INVERT_PORT0 (0x04U) +#define TCA9539_REG_INVERT_PORT1 (0x05U) +#define TCA9539_REG_CONFIG_PORT0 (0x06U) +#define TCA9539_REG_CONFIG_PORT1 (0x07U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Port_Definition TCA9539 Port Definition + * @{ + */ +#define TCA9539_IO_PORT0 (0x00U) +#define TCA9539_IO_PORT1 (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition + * @{ + */ +#define TCA9539_IO_PIN0 (0x01U) +#define TCA9539_IO_PIN1 (0x02U) +#define TCA9539_IO_PIN2 (0x04U) +#define TCA9539_IO_PIN3 (0x08U) +#define TCA9539_IO_PIN4 (0x10U) +#define TCA9539_IO_PIN5 (0x20U) +#define TCA9539_IO_PIN6 (0x40U) +#define TCA9539_IO_PIN7 (0x80U) +#define TCA9539_IO_PIN_ALL (0xFFU) +/** + * @} + */ + +/** + * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition + * @{ + */ +#define TCA9539_DIR_OUT (0x00U) +#define TCA9539_DIR_IN (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition + * @{ + */ +#define TCA9539_PIN_RESET (0x00U) +#define TCA9539_PIN_SET (0x01U) +/** + * @} + */ + +/** + * @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */ +#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */ +#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */ + +#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */ +#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */ +#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN1_STB_PORT (TCA9539_IO_PORT1) +#define CAN1_STB_PIN (EIO_CAN1_STB) +#define CAN2_STB_PORT (TCA9539_IO_PORT1) +#define CAN2_STB_PIN (EIO_CAN2_STB) +/** + * @} + */ + +int TCA9539_Init(void); +rt_err_t TCA9539_WritePin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState); +rt_err_t TCA9539_ReadPin(uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState); +rt_err_t TCA9539_TogglePin(uint8_t u8Port, uint8_t u8Pin); +rt_err_t TCA9539_ConfigPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir); + +#endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/figures/board.png b/bsp/hc32/ev_hc32f448_lqfp80/figures/board.png new file mode 100644 index 0000000000000000000000000000000000000000..f1c984dbd154e36d5487ab27b82b1f2f441f7621 GIT binary patch literal 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    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM)) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx new file mode 100644 index 0000000000..0a7051aa92 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/project.uvprojx @@ -0,0 +1,867 @@ + + + 2.1 +
    ### uVision Project, (C) Keil Software
    + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F448MCTI + HDSC + HDSC.HC32F448.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x40000) IROM2(0x03000C00,0x400) IRAM1(0x1FFF8000,0x10000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL0080000 -FP0($$Device:HC32F448PETB$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)) + 0 + $$Device:HC32F448MCTI$Device\Include\HC32F448MCTI.h + + + + + + + + + + ../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x03000C00 + 0x400 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x10000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, USE_DDL_DRIVER, __RTTHREAD__, __DEBUG, HC32F448 + + applications;board;..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\inc;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\libraries\hc32f448_ddl\drivers\cmsis\Include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\libraries\hc32_drivers;..\..\..\components\finsh;.;..\..\..\include;board\ports;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\cortex-m4;board\config;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\eventfd;..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\poll + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + xtal32_fcm.c + 1 + applications\xtal32_fcm.c + + + + + main.c + 1 + applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + + + completion.c + 1 + ..\..\..\components\drivers\ipc\completion.c + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + pin.c + 1 + ..\..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\..\components\drivers\serial\serial.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + board_config.c + 1 + board\board_config.c + + + + + startup_hc32f448.s + 2 + ..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\ARM\startup_hc32f448.s + + + + + drv_common.c + 1 + ..\libraries\hc32_drivers\drv_common.c + + + + + drv_gpio.c + 1 + ..\libraries\hc32_drivers\drv_gpio.c + + + + + drv_irq.c + 1 + ..\libraries\hc32_drivers\drv_irq.c + + + + + drv_usart.c + 1 + ..\libraries\hc32_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + libcpu + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + Libraries + + + hc32_ll_clk.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_clk.c + + + + + hc32_ll_icg.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_icg.c + + + + + hc32_ll_utility.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_utility.c + + + + + hc32_ll_fcg.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcg.c + + + + + hc32_ll_interrupts.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_interrupts.c + + + + + hc32_ll_sram.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_sram.c + + + + + hc32_ll_pwc.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_pwc.c + + + + + hc32_ll_aos.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_aos.c + + + + + hc32_ll_fcm.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_fcm.c + + + + + hc32_ll.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll.c + + + + + system_hc32f448.c + 1 + ..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\system_hc32f448.c + + + + + hc32_ll_efm.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_efm.c + + + + + hc32_ll_gpio.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_gpio.c + + + + + hc32_ll_usart.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_usart.c + + + + + hc32_ll_rmu.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_rmu.c + + + + + hc32_ll_tmr0.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_tmr0.c + + + + + hc32_ll_dma.c + 1 + ..\libraries\hc32f448_ddl\drivers\hc32_ll_driver\src\hc32_ll_dma.c + + + + + + + + + + + +     diff --git a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h new file mode 100644 index 0000000000..423cb87cf2 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h @@ -0,0 +1,276 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice optimization */ + +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x50100 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Memory protection */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* CYW43012 WiFi */ + + +/* BL808 WiFi */ + + +/* CYW43439 WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects and Demos */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F448MC + +/* On-chip Drivers */ + +#define BSP_USING_ON_CHIP_FLASH_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + +/* Onboard Peripheral Drivers */ + + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART2 +#define BSP_UART2_RX_USING_DMA +#define BSP_UART2_TX_USING_DMA + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py new file mode 100644 index 0000000000..568d50f2a6 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + else: + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f448_lqfp80/template.ewp b/bsp/hc32/ev_hc32f448_lqfp80/template.ewp new file mode 100644 index 0000000000..09889fca31 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/template.ewp @@ -0,0 +1,1927 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/template.eww b/bsp/hc32/ev_hc32f448_lqfp80/template.eww new file mode 100644 index 0000000000..bd036bb4c9 --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f448_lqfp80/template.uvoptx b/bsp/hc32/ev_hc32f448_lqfp80/template.uvoptx new file mode 100644 index 0000000000..93df814b6a --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
    ### uVision Project, (C) Keil Software
    + + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFF8000 -FC1000 -FN1 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM)) + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL080000 -FP0($$Device:HC32F448MCTI$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + +     diff --git a/bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx b/bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx new file mode 100644 index 0000000000..79530b5e3f --- /dev/null +++ b/bsp/hc32/ev_hc32f448_lqfp80/template.uvprojx @@ -0,0 +1,391 @@ + + + + 2.1 + +
    ### uVision Project, (C) Keil Software
    + + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F448MCTI + HDSC + HDSC.HC32F448.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x40000) IROM2(0x03000C00,0x400) IRAM1(0x1FFF8000,0x10000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFF8000 -FC4000 -FN2 -FF0HC32F448_256K -FS00 -FL0080000 -FP0($$Device:HC32F448PETB$FlashARM\HC32F448_256K.FLM) -FF1HC32F448_otp -FS13000C00 -FL1400 -FP1($$Device:HC32F448MCTI$FlashARM\HC32F448_otp.FLM)) + 0 + $$Device:HC32F448MCTI$Device\Include\HC32F448MCTI.h + + + + + + + + + + ../libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/ARM/sfr/HC32F448.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x10000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x03000C00 + 0x400 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFF8000 + 0x10000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + +     diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig index 858a5db449..bc1d72d5c1 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig @@ -64,11 +64,22 @@ menu "Onboard Peripheral Drivers" endif endif - config BSP_USING_TCA9539 - bool "Enable TCA9539" - select BSP_USING_I2C - select BSP_USING_I2C1 + config BSP_USING_EXMC + bool "Enable EXMC" default n + if BSP_USING_EXMC + choice + prompt "Using SDRAM or NAND" + default BSP_USING_NAND + + config BSP_USING_NAND + bool "Using NAND (MT29F2G08AB)" + select RT_USING_MTD_NAND + + config BSP_USING_SDRAM + bool "Using SDRAM (IS42S16400J7TLI)" + endchoice + endif config BSP_USING_SPI_FLASH bool "Enable SPI FLASH (w25q64 spi1)" @@ -81,11 +92,10 @@ menu "Onboard Peripheral Drivers" select RT_USING_MTD_NOR default n - config BSP_USING_MT29F2G08AB - bool "Enable NAND FLASH (MT29F2G08AB)" - select BSP_USING_EXMC - select BSP_USING_NAND - select RT_USING_MTD_NAND + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C + select BSP_USING_I2C1 default n endmenu @@ -633,24 +643,6 @@ menu "On-chip Peripheral Drivers" default n endif - menuconfig BSP_USING_EXMC - bool "Enable EXMC" - default n - select BSP_USING_EXMC - if BSP_USING_EXMC - choice - prompt "Using SDRAM or Nand" - default BSP_USING_SDRAM - - config BSP_USING_SDRAM - bool "Using SDRAM" - - config BSP_USING_NAND - bool "Using Nand" - select RT_USING_MTD_NAND - endchoice - endif - menuconfig BSP_USING_PM bool "Enable PM" default n diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h index 2d0dc0cdd2..48f5437055 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-02-24 CDT first version + * 2024-02-20 CDT modify timing configuration for using exclk clock frequency 30MHz + * add t_rcd/t_rfc/t_rp configuration macros-definition */ #ifndef __SDRAM_PORT_H__ @@ -39,21 +41,24 @@ /* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ #define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED -/* timing configuration(EXCLK clock frequency: 60MHz) for IS42S16400J-7TLI */ +/* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */ /* refresh rate counter (EXCLK clock) */ -#define SDRAM_REFRESH_COUNT (900U) +#define SDRAM_REFRESH_COUNT (450U) /* TMDR: mode register command time (EXCLK clock) */ #define SDRAM_TMDR 2U /* TRAS: RAS to precharge delay time (EXCLK clock) */ -#define SDRAM_TRAS 3U +#define SDRAM_TRAS 2U /* TRC: active bank x to active bank x delay time (EXCLK clock) */ -#define SDRAM_TRC 4U +#define SDRAM_TRC 2U /* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ -#define SDRAM_TRCD 1U +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U /* TRFC: autorefresh command time (EXCLK clock) */ -#define SDRAM_TRFC 4U +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U /* TRP: precharge to RAS delay time (EXCLK clock) */ -#define SDRAM_TRP 1U +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U /* TRRD: active bank x to active bank y delay time (EXCLK clock) */ #define SDRAM_TRRD 1U /* TWR: write to precharge delay time (EXCLK clock). */ diff --git a/bsp/hc32/libraries/.ignore_format.yml b/bsp/hc32/libraries/.ignore_format.yml index 5553dc5b77..f531ea229b 100644 --- a/bsp/hc32/libraries/.ignore_format.yml +++ b/bsp/hc32/libraries/.ignore_format.yml @@ -5,3 +5,4 @@ dir_path: - hc32f4a0_ddl - hc32f460_ddl +- hc32f448_ddl diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.c b/bsp/hc32/libraries/hc32_drivers/drv_adc.c index fd06e65322..2447c05a7d 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.c @@ -8,6 +8,8 @@ * 2022-04-28 CDT first version * 2022-06-08 xiaoxiaolisunny add hc32f460 series * 2022-06-14 CDT fix a bug of internal trigger + * 2024-02-20 CDT support HC32F448 + * add function for associating with the dma */ #include @@ -29,6 +31,19 @@ typedef struct #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3) +enum +{ +#ifdef BSP_USING_ADC1 + ADC1_INDEX, +#endif +#ifdef BSP_USING_ADC2 + ADC2_INDEX, +#endif +#ifdef BSP_USING_ADC3 + ADC3_INDEX, +#endif +}; + static adc_device _g_adc_dev_array[] = { #ifdef BSP_USING_ADC1 @@ -116,12 +131,24 @@ static rt_err_t _adc_enable(struct rt_adc_device *device, rt_int8_t channel, rt_ { adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc); ADC_ChCmd(p_adc_dev->instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled); + + /* user_data != NULL */ + if (device->parent.user_data != RT_NULL) + { + struct adc_dev_priv_params *adc_dev_priv = device->parent.user_data; + if ((ADC_USING_EOCA_DMA_FLAG == adc_dev_priv->flag) && (adc_dev_priv->ops->dma_trig_config != RT_NULL)) + { + adc_dev_priv->ops->dma_trig_config(); + } + } + return 0; } static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value) { rt_err_t rt_ret = -RT_ERROR; + rt_uint32_t timeCnt; if (!value) { @@ -129,27 +156,68 @@ static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt } adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc); - if (p_adc_dev->init.hard_trig_enable == RT_FALSE && p_adc_dev->instance->STR == 0) + if (p_adc_dev->init.hard_trig_enable == RT_FALSE) { - ADC_Start(p_adc_dev->instance); - } - - uint32_t start_time = rt_tick_get(); - do - { - if (ADC_GetStatus(p_adc_dev->instance, ADC_FLAG_EOCA) == SET) + if (p_adc_dev->instance->STR == 0) { - ADC_ClearStatus(p_adc_dev->instance, ADC_FLAG_EOCA); - rt_ret = LL_OK; - break; + ADC_Start(p_adc_dev->instance); + } + + uint32_t start_time = rt_tick_get(); + do + { + if (ADC_GetStatus(p_adc_dev->instance, ADC_FLAG_EOCA) == SET) + { + ADC_ClearStatus(p_adc_dev->instance, ADC_FLAG_EOCA); + rt_ret = LL_OK; + break; + } + } + while ((rt_tick_get() - start_time) < p_adc_dev->init.eoc_poll_time_max); + + if (rt_ret == LL_OK) + { + /* Get any ADC value of sequence A channel that needed. */ + *value = ADC_GetValue(p_adc_dev->instance, channel); } } - while ((rt_tick_get() - start_time) < p_adc_dev->init.eoc_poll_time_max); - - if (rt_ret == LL_OK) + else if (p_adc_dev->init.hard_trig_enable == RT_TRUE) { - /* Get any ADC value of sequence A channel that needed. */ - *value = ADC_GetValue(p_adc_dev->instance, channel); + /* DMA src/dest/tc... config; start/stop trigger */ + if (p_adc_dev->init.adc_eoca_dma != RT_NULL) + { + if (p_adc_dev->rt_adc.parent.user_data != RT_NULL) + { + struct adc_dev_priv_params *adc_dev_priv = device->parent.user_data; + struct dma_config *adc_eoca_dma; + adc_eoca_dma = p_adc_dev->init.adc_eoca_dma; + if ((ADC_USING_EOCA_DMA_FLAG == adc_dev_priv->flag) && (adc_dev_priv->ops->dma_trig_start != RT_NULL)) + { + DMA_ClearTransCompleteStatus(adc_eoca_dma->Instance, adc_eoca_dma->flag); + (void)DMA_SetTransCount(adc_eoca_dma->Instance, adc_eoca_dma->channel, 1U); + (void)DMA_SetSrcAddr(adc_eoca_dma->Instance, adc_eoca_dma->channel, (uint32_t)(&p_adc_dev->instance->DR0) + channel * 2); + (void)DMA_SetDestAddr(adc_eoca_dma->Instance, adc_eoca_dma->channel, (uint32_t)(value)); + (void)DMA_ChCmd(adc_eoca_dma->Instance, adc_eoca_dma->channel, ENABLE); + adc_dev_priv->ops->dma_trig_start(); + timeCnt = 0; + /* wait DMA transfer completed */ + while (RESET == DMA_GetTransCompleteStatus(adc_eoca_dma->Instance, adc_eoca_dma->flag) && (timeCnt < p_adc_dev->init.eoc_poll_time_max)) + { + rt_thread_mdelay(1); + timeCnt++; + } + if (timeCnt >= p_adc_dev->init.eoc_poll_time_max) + { + (void)DMA_ChCmd(adc_eoca_dma->Instance, adc_eoca_dma->channel, DISABLE); + rt_ret = -RT_ETIMEOUT; + } + if (adc_dev_priv->ops->dma_trig_stop != RT_NULL) + { + adc_dev_priv->ops->dma_trig_stop(); + } + } + } + } } return rt_ret; @@ -212,6 +280,51 @@ static void _adc_clock_enable(void) #endif } +static void hc32_adc_get_dma_info(void) +{ +#ifdef BSP_ADC1_USING_DMA + static struct dma_config adc1_eoca_dma = ADC1_EOCA_DMA_CONFIG; + _g_adc_dev_array[ADC1_INDEX].init.adc_eoca_dma = &adc1_eoca_dma; +#endif + +#ifdef BSP_ADC2_USING_DMA + static struct dma_config adc2_eoca_dma = ADC2_EOCA_DMA_CONFIG; + _g_adc_dev_array[ADC2_INDEX].init.adc_eoca_dma = &adc2_eoca_dma; +#endif + +#ifdef BSP_ADC3_USING_DMA + static struct dma_config adc3_eoca_dma = ADC3_EOCA_DMA_CONFIG; + _g_adc_dev_array[ADC3_INDEX].init.adc_eoca_dma = &adc3_eoca_dma; +#endif +} + +static void hc32_adc_dma_config(adc_device *p_adc_dev) +{ + stc_dma_init_t stcDmaInit; + + /* DMA/AOS FCG enable */ + FCG_Fcg0PeriphClockCmd(p_adc_dev->init.adc_eoca_dma->clock, ENABLE); + + (void)DMA_StructInit(&stcDmaInit); + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32TransCount = 1UL; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; + stcDmaInit.u32SrcAddr = (uint32_t)RT_NULL; + stcDmaInit.u32DestAddr = (uint32_t)RT_NULL; + if (LL_OK != DMA_Init(p_adc_dev->init.adc_eoca_dma->Instance, p_adc_dev->init.adc_eoca_dma->channel, &stcDmaInit)) + { + rt_kprintf("[%s:%d]ADC DMA init error!\n", __func__, __LINE__); + } + AOS_SetTriggerEventSrc(p_adc_dev->init.adc_eoca_dma->trigger_select, p_adc_dev->init.adc_eoca_dma->trigger_event); + + /* Clear DMA TC flag */ + DMA_ClearTransCompleteStatus(p_adc_dev->init.adc_eoca_dma->Instance, p_adc_dev->init.adc_eoca_dma->flag); + /* Enable DMA unit */ + DMA_Cmd(p_adc_dev->init.adc_eoca_dma->Instance, ENABLE); +} + extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx); int rt_hw_adc_init(void) { @@ -220,6 +333,7 @@ int rt_hw_adc_init(void) int32_t ll_ret = 0; _adc_clock_enable(); + hc32_adc_get_dma_info(); uint32_t dev_cnt = sizeof(_g_adc_dev_array) / sizeof(_g_adc_dev_array[0]); for (; i < dev_cnt; i++) { @@ -243,6 +357,11 @@ int rt_hw_adc_init(void) _adc_internal_trigger1_set(&_g_adc_dev_array[i]); } + if (_g_adc_dev_array[i].init.adc_eoca_dma != RT_NULL) + { + hc32_adc_dma_config(&_g_adc_dev_array[i]); + } + rt_hw_board_adc_init((void *)_g_adc_dev_array[i].instance); ret = rt_hw_adc_register(&_g_adc_dev_array[i].rt_adc, \ (const char *)_g_adc_dev_array[i].init.name, \ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.h b/bsp/hc32/libraries/hc32_drivers/drv_adc.h index a7d65674f7..c000b2054a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-04-28 CDT first version + * 2024-02-20 CDT add structure for associating with the dma */ @@ -16,7 +17,10 @@ * Include files ******************************************************************************/ #include -#include "rtdevice.h" +#include +#include "board_config.h" +#include "drv_irq.h" +#include "drv_dma.h" #include "hc32_ll.h" @@ -51,11 +55,26 @@ struct adc_dev_init_params rt_bool_t continue_conv_mode_enable; rt_bool_t data_reg_auto_clear; uint32_t eoc_poll_time_max; + struct dma_config *adc_eoca_dma; +}; + +struct adc_dev_dma_priv_ops +{ + rt_err_t (*dma_trig_start)(void); + rt_err_t (*dma_trig_stop)(void); + rt_err_t (*dma_trig_config)(void); +}; + +struct adc_dev_priv_params +{ + uint32_t flag; + struct adc_dev_dma_priv_ops *ops; }; /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ +#define ADC_USING_EOCA_DMA_FLAG (1U) /******************************************************************************* * Global variable definitions ('extern') diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c index 526bd0a426..29c2f57e47 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-04-28 CDT first version + * 2023-10-09 CDT support HC32F448 */ #include @@ -26,6 +27,8 @@ #define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1) #elif defined (HC32F460) #define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1) +#elif defined (HC32F448) + #define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1) #endif #define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c index 210e426399..050224fa6b 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_hwtimer.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2023-06-21 CDT first version + * 2024-02-20 CDT support HC32F448 */ #include @@ -144,12 +145,20 @@ static void _timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) (void)TMRA_Init(tmr_device->tmr_handle, &stcTmraInit); TMRA_IntCmd(tmr_device->tmr_handle, TMRA_INT_OVF, ENABLE); +#if defined (HC32F460) || defined (HC32F4A0) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_TRUE); +#elif defined (HC32F448) + hc32_install_independ_irq_handler(&irq_config, RT_TRUE); +#endif } else /* close */ { TMRA_DeInit(tmr_device->tmr_handle); +#if defined (HC32F460) || defined (HC32F4A0) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_FALSE); +#elif defined (HC32F448) + hc32_install_independ_irq_handler(&irq_config, RT_FALSE); +#endif FCG_Fcg2PeriphClockCmd(tmr_device->clock, DISABLE); } } @@ -238,84 +247,130 @@ static void TMRA_1_callback(void) TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_1_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_1_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_1_INDEX].time_device); } -#endif + +#if defined (HC32F448) +void TMRA_1_Ovf_Udf_Handler(void) +{ + TMRA_1_callback(); +} +#endif /* HC32F448 */ +#endif /* BSP_USING_TMRA_1 */ + #ifdef BSP_USING_TMRA_2 static void TMRA_2_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_2_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_2_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_2_INDEX].time_device); } -#endif + +#if defined (HC32F448) +void TMRA_2_Ovf_Udf_Handler(void) +{ + TMRA_2_callback(); +} +#endif /* HC32F448 */ +#endif /* BSP_USING_TMRA_2 */ + #ifdef BSP_USING_TMRA_3 static void TMRA_3_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_3_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_3_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_3_INDEX].time_device); } -#endif + +#if defined (HC32F448) +void TMRA_3_Ovf_Udf_Handler(void) +{ + TMRA_3_callback(); +} +#endif /* HC32F448 */ +#endif /* BSP_USING_TMRA_3 */ + #ifdef BSP_USING_TMRA_4 static void TMRA_4_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_4_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_4_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_4_INDEX].time_device); } -#endif + +#if defined (HC32F448) +void TMRA_4_Ovf_Udf_Handler(void) +{ + TMRA_4_callback(); +} +#endif /* HC32F448 */ +#endif /* BSP_USING_TMRA_4 */ + #ifdef BSP_USING_TMRA_5 static void TMRA_5_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_5_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_5_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_5_INDEX].time_device); } -#endif + +#if defined (HC32F448) +void TMRA_5_Ovf_Udf_Handler(void) +{ + TMRA_5_callback(); +} +#endif /* HC32F448 */ +#endif /* BSP_USING_TMRA_5 */ + #ifdef BSP_USING_TMRA_6 static void TMRA_6_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_6_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_6_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_6_INDEX].time_device); } -#endif +#endif /* BSP_USING_TMRA_6 */ + #ifdef BSP_USING_TMRA_7 static void TMRA_7_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_7_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_7_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_7_INDEX].time_device); } -#endif +#endif /* BSP_USING_TMRA_7 */ + #ifdef BSP_USING_TMRA_8 static void TMRA_8_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_8_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_8_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_8_INDEX].time_device); } -#endif +#endif /* BSP_USING_TMRA_8 */ + #ifdef BSP_USING_TMRA_9 static void TMRA_9_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_9_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_9_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_9_INDEX].time_device); } -#endif +#endif /* BSP_USING_TMRA_9 */ + #ifdef BSP_USING_TMRA_10 static void TMRA_10_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_10_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_10_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_10_INDEX].time_device); } -#endif +#endif /* BSP_USING_TMRA_10 */ + #ifdef BSP_USING_TMRA_11 static void TMRA_11_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_11_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_11_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_11_INDEX].time_device); } -#endif +#endif /* BSP_USING_TMRA_11 */ + #ifdef BSP_USING_TMRA_12 static void TMRA_12_callback(void) { TMRA_ClearStatus(hc32_hwtimer_obj[TMRA_12_INDEX].tmr_handle, hc32_hwtimer_obj[TMRA_12_INDEX].flag); rt_device_hwtimer_isr(&hc32_hwtimer_obj[TMRA_12_INDEX].time_device); } -#endif +#endif /* BSP_USING_TMRA_12 */ static struct rt_hwtimer_info _info[sizeof(hc32_hwtimer_obj) / sizeof(hc32_hwtimer_obj[0])]; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_i2c.c b/bsp/hc32/libraries/hc32_drivers/drv_i2c.c index 8e676562c6..008ef0f926 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_i2c.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_i2c.c @@ -317,6 +317,7 @@ static int I2C_Master_Transmit_DMA(struct hc32_i2c *i2c_obj, struct rt_i2c_msg * if (msg->len > 1U) { + DMA_ClearTransCompleteStatus(i2c_tx_dma->Instance, i2c_tx_dma->flag); (void)DMA_SetTransCount(i2c_tx_dma->Instance, i2c_tx_dma->channel, msg->len - 1U); (void)DMA_SetSrcAddr(i2c_tx_dma->Instance, i2c_tx_dma->channel, (uint32_t)(&msg->buf[1])); (void)DMA_ChCmd(i2c_tx_dma->Instance, i2c_tx_dma->channel, ENABLE); @@ -362,6 +363,7 @@ static int I2C_Master_Receive_DMA(struct hc32_i2c *i2c_obj, struct rt_i2c_msg *m } else if (msg->len > 2U) { + DMA_ClearTransCompleteStatus(i2c_rx_dma->Instance, i2c_rx_dma->flag); (void)DMA_SetTransCount(i2c_rx_dma->Instance, i2c_rx_dma->channel, msg->len - 2U); (void)DMA_SetDestAddr(i2c_rx_dma->Instance, i2c_rx_dma->channel, (uint32_t)(&msg->buf[0])); (void)DMA_ChCmd(i2c_rx_dma->Instance, i2c_rx_dma->channel, ENABLE); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.c b/bsp/hc32/libraries/hc32_drivers/drv_irq.c index adb2e250c3..a0e0331db0 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_irq.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.c @@ -68,6 +68,28 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, return result; } +#if defined (HC32F448) +rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config, + rt_bool_t irq_enable) +{ + RT_ASSERT(RT_NULL != irq_config); + + NVIC_ClearPendingIRQ(irq_config->irq_num); + NVIC_SetPriority(irq_config->irq_num, irq_config->irq_prio); + if (RT_TRUE == irq_enable) + { + INTC_IntSrcCmd(irq_config->int_src, ENABLE); + NVIC_EnableIRQ(irq_config->irq_num); + } + else + { + INTC_IntSrcCmd(irq_config->int_src, DISABLE); + NVIC_DisableIRQ(irq_config->irq_num); + } + return RT_EOK; +} +#endif + /******************************************************************************* * EOF (not truncated) ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.h b/bsp/hc32/libraries/hc32_drivers/drv_irq.h index 8d0b5c4857..9050ff427a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_irq.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.h @@ -47,6 +47,10 @@ struct hc32_irq_config rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, void (*irq_hdr)(void), rt_bool_t irq_enable); +#if defined (HC32F448) +rt_err_t hc32_install_independ_irq_handler(struct hc32_irq_config *irq_config, + rt_bool_t irq_enable); +#endif #ifdef __cplusplus } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.c b/bsp/hc32/libraries/hc32_drivers/drv_pm.c index 650a279655..076e4e73f3 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdram.c b/bsp/hc32/libraries/hc32_drivers/drv_sdram.c index f1b1514e5d..28daf1c9ea 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdram.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdram.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-02-24 CDT first version + * 2024-02-20 CDT modify exclk clock max frequency to 40MHz for HC32F4A0 + * add t_rcd_p/t_rfc_p/t_rp_p configuration */ @@ -82,8 +84,8 @@ static rt_int32_t _sdram_verify_clock_frequency(void) rt_int32_t ret = RT_EOK; #if defined (HC32F4A0) - /* EXCLK max frequency for SDRAM: 60MHz */ - if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (60 * 1000000)) + /* EXCLK max frequency for SDRAM: 40MHz */ + if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (40 * 1000000)) { ret = -RT_ERROR; } @@ -131,12 +133,12 @@ static rt_int32_t _sdram_init(void) stcDmcInit.stcTimingConfig.u8MRD = SDRAM_TMDR; stcDmcInit.stcTimingConfig.u8RAS = SDRAM_TRAS; stcDmcInit.stcTimingConfig.u8RC = SDRAM_TRC; - stcDmcInit.stcTimingConfig.u8RCD_B = SDRAM_TRCD; - stcDmcInit.stcTimingConfig.u8RCD_P = 0U; - stcDmcInit.stcTimingConfig.u8RFC_B = SDRAM_TRFC; - stcDmcInit.stcTimingConfig.u8RFC_P = 0U; - stcDmcInit.stcTimingConfig.u8RP_B = SDRAM_TRP; - stcDmcInit.stcTimingConfig.u8RP_P = 0U; + stcDmcInit.stcTimingConfig.u8RCD_B = SDRAM_TRCD_B; + stcDmcInit.stcTimingConfig.u8RCD_P = SDRAM_TRCD_P; + stcDmcInit.stcTimingConfig.u8RFC_B = SDRAM_TRFC_B; + stcDmcInit.stcTimingConfig.u8RFC_P = SDRAM_TRFC_P; + stcDmcInit.stcTimingConfig.u8RP_B = SDRAM_TRP_B; + stcDmcInit.stcTimingConfig.u8RP_P = SDRAM_TRP_P; stcDmcInit.stcTimingConfig.u8RRD = SDRAM_TRRD; stcDmcInit.stcTimingConfig.u8WR = SDRAM_TWR; stcDmcInit.stcTimingConfig.u8WTR = SDRAM_TWTR; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_spi.c b/bsp/hc32/libraries/hc32_drivers/drv_spi.c index 65634aa0b4..129e4fc408 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_spi.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_spi.c @@ -7,6 +7,7 @@ * Date Author Notes * 2022-04-28 CDT first version * 2023-09-30 CDT Delete dma transmit interrupt + * 2024-02-20 CDT support HC32F448 */ /******************************************************************************* @@ -292,6 +293,9 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat #endif /* Enable error interrupt */ +#if defined (HC32F448) + INTC_IntSrcCmd(spi_drv->config->err_irq.irq_config.int_src, ENABLE); +#endif NVIC_EnableIRQ(spi_drv->config->err_irq.irq_config.irq_num); SPI_IntCmd(spi_instance, SPI_INT_ERR, ENABLE); @@ -302,14 +306,24 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat static void hc32_spi_enable(CM_SPI_TypeDef *SPIx) { /* Check if the SPI is already enabled */ +#if defined (HC32F460) || defined (HC32F4A0) if ((SPIx->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { SPI_Cmd(SPIx, ENABLE); } +#elif defined (HC32F448) + if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE) + { + SPI_Cmd(SPIx, ENABLE); + } +#else +#error "Please select first the target HC32xxxx device used in your application." +#endif } static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) { +#if defined (HC32F460) || defined (HC32F4A0) if (SPI_SEND_ONLY == u32Mode) { SET_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); @@ -318,12 +332,30 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) { CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); } +#elif defined (HC32F448) + if (SPI_SEND_ONLY == u32Mode) + { + SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); + } + else + { + CLR_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); + } +#else +#error "Please select first the target HC32xxxx device used in your application." +#endif } #ifdef BSP_SPI_USING_DMA static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx) { +#if defined (HC32F460) || defined (HC32F4A0) return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); +#elif defined (HC32F448) + return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); +#else +#error "Please select first the target HC32xxxx device used in your application." +#endif } /** @@ -647,6 +679,10 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, static void hc32_spi_err_irq_handle(struct hc32_spi *spi) { +#if defined (HC32F448) +#define SPI_FLAG_OVERLOAD SPI_FLAG_OVERRUN +#define SPI_FLAG_UNDERLOAD SPI_FLAG_UNDERRUN +#endif __UNUSED uint32_t UnusedData; CM_SPI_TypeDef *spi_instance = spi->config->Instance; @@ -678,7 +714,15 @@ static void hc32_spi1_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif + +#if defined (HC32F448) +void SPI1_Handler(void) +{ + hc32_spi1_err_irq_handler(); +} +#endif /* HC32F448 */ + +#endif /* BSP_USING_SPI1 */ #if defined(BSP_USING_SPI2) static void hc32_spi2_err_irq_handler(void) @@ -689,7 +733,14 @@ static void hc32_spi2_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif +#if defined (HC32F448) +void SPI2_Handler(void) +{ + hc32_spi2_err_irq_handler(); +} +#endif /* HC32F448 */ + +#endif /* BSP_USING_SPI2 */ #if defined(BSP_USING_SPI3) static void hc32_spi3_err_irq_handler(void) @@ -700,7 +751,14 @@ static void hc32_spi3_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif +#if defined (HC32F448) +void SPI3_Handler(void) +{ + hc32_spi3_err_irq_handler(); +} +#endif /* HC32F448 */ + +#endif /* BSP_USING_SPI3 */ #if defined(BSP_USING_SPI4) static void hc32_spi4_err_irq_handler(void) @@ -711,7 +769,7 @@ static void hc32_spi4_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif +#endif /* BSP_USING_SPI4 */ #if defined(BSP_USING_SPI5) static void hc32_spi5_err_irq_handler(void) @@ -722,7 +780,7 @@ static void hc32_spi5_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif +#endif /* BSP_USING_SPI5 */ #if defined(BSP_USING_SPI6) static void hc32_spi6_err_irq_handler(void) @@ -733,7 +791,7 @@ static void hc32_spi6_err_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif +#endif /* BSP_USING_SPI6 */ /** @@ -848,7 +906,12 @@ static int hc32_hw_spi_bus_init(void) spi_bus_obj[i].config = &spi_config[i]; spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; /* register the handle */ +#if defined (HC32F460) || defined (HC32F4A0) hc32_install_irq_handler(&spi_config[i].err_irq.irq_config, spi_config[i].err_irq.irq_callback, RT_FALSE); +#elif defined (HC32F488) + INTC_IntSrcCmd(spi_config[i].err_irq.irq_config.int_src, DISABLE); + NVIC_DisableIRQ(spi_config[i].err_irq.irq_config.irq_num); +#endif result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &hc32_spi_ops); LOG_D("%s bus init done", spi_config[i].bus_name); } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.c b/bsp/hc32/libraries/hc32_drivers/drv_usart.c index a5ce518f35..f99b01d028 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-04-28 CDT first version + * 2023-10-09 CDT support HC32F448 */ /******************************************************************************* @@ -17,10 +18,10 @@ #ifdef RT_USING_SERIAL -#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \ - defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \ - defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \ - defined(BSP_USING_UART10) +#if defined (BSP_USING_UART1) || defined (BSP_USING_UART2) || defined (BSP_USING_UART3) || \ + defined (BSP_USING_UART4) || defined (BSP_USING_UART5) || defined (BSP_USING_UART6) || \ + defined (BSP_USING_UART7) || defined (BSP_USING_UART8) || defined (BSP_USING_UART9) || \ + defined (BSP_USING_UART10) #include "drv_usart.h" #include "board_config.h" @@ -41,16 +42,12 @@ #define DMA_TRANS_CNT(unit, ch) \ (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) -#define USART_TCI_ENABLE(unit) \ - SET_REG32_BIT(unit->CR1, USART_INT_TX_CPLT) - - #define UART_BAUDRATE_ERR_MAX (0.025F) #if defined (HC32F460) #define FCG_USART_CLK FCG_Fcg1PeriphClockCmd -#elif defined (HC32F4A0) +#elif defined (HC32F4A0) || defined (HC32F448) #define FCG_USART_CLK FCG_Fcg3PeriphClockCmd #endif @@ -165,6 +162,9 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co #elif defined (HC32F460) if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) +#elif defined (HC32F448) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ + (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) #endif { uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE; @@ -220,7 +220,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co { uart_init.u32FirstBit = USART_FIRST_BIT_MSB; } -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F448) switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: @@ -238,7 +238,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co #ifdef RT_SERIAL_USING_DMA if (!(serial->parent.open_flag & RT_DEVICE_OFLAG_OPEN)) { - uart->dma_rx_remain_index = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2; + uart->dma_rx_remaining_cnt = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2; } #endif /* Enable USART clock */ @@ -271,6 +271,11 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co /* Enable error interrupt */ #if defined (HC32F460) || defined (HC32F4A0) NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num); +#elif defined (HC32F448) + INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE); + INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); + INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE); + NVIC_EnableIRQ(uart->config->irq_num); #endif USART_FuncCmd(uart->config->Instance, USART_TX | USART_RX | USART_INT_RX, ENABLE); @@ -294,8 +299,9 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg { #if defined (HC32F460) || defined (HC32F4A0) NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num); - USART_FuncCmd(uart->config->Instance, USART_INT_RX, DISABLE); INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num); +#elif defined (HC32F448) + INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); #endif } else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg) @@ -304,6 +310,8 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num); USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE); INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); +#elif defined (HC32F448) + USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE); #endif } #ifdef RT_SERIAL_USING_DMA @@ -313,6 +321,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg } else if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg) { + USART_FuncCmd(uart->config->Instance, USART_INT_TX_CPLT, DISABLE); NVIC_DisableIRQ(uart->config->dma_tx->irq_config.irq_num); } #endif @@ -327,10 +336,23 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg } else { + INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE); USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE); USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE); } +#elif defined (HC32F448) + /* NVIC config */ + if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) + { + /* intsrc enable */ + INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE); + USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE); + } + else + { + USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE); + } #endif break; #ifdef RT_SERIAL_USING_DMA @@ -388,7 +410,10 @@ static int hc32_getc(struct rt_serial_device *serial) return ch; } -static rt_ssize_t hc32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction) +static rt_ssize_t hc32_dma_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + int direction) { #ifdef RT_SERIAL_USING_DMA struct hc32_uart *uart; @@ -397,7 +422,7 @@ static rt_ssize_t hc32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t RT_ASSERT(RT_NULL != serial); RT_ASSERT(RT_NULL != buf); - if (size == 0) + if (0 == size) { return 0; } @@ -455,10 +480,12 @@ static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { struct hc32_uart *uart; - uint32_t cmp_val; CM_TMR0_TypeDef *TMR0_Instance; uint8_t ch; - uint32_t timeout_bits; + uint32_t rtb; + uint32_t alpha; + uint32_t ckdiv; + uint32_t cmp_val; stc_tmr0_init_t stcTmr0Init; RT_ASSERT(RT_NULL != serial); @@ -467,7 +494,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) TMR0_Instance = uart->config->rx_timeout->TMR0_Instance; ch = uart->config->rx_timeout->channel; - timeout_bits = uart->config->rx_timeout->timeout_bits; + rtb = uart->config->rx_timeout->timeout_bits; #if defined (HC32F460) if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance)) { @@ -486,6 +513,15 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } +#elif defined (HC32F448) + if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) + { + RT_ASSERT(TMR0_CH_A == ch); + } + else if ((CM_USART2 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) + { + RT_ASSERT(TMR0_CH_B == ch); + } #endif FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); @@ -497,16 +533,25 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_XTAL32; if (TMR0_CLK_DIV1 == stcTmr0Init.u32ClockDiv) { - cmp_val = (timeout_bits - 4UL); + alpha = 7UL; } else if (TMR0_CLK_DIV2 == stcTmr0Init.u32ClockDiv) { - cmp_val = (timeout_bits / 2UL - 2UL); + alpha = 5UL; + } + else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || \ + (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || \ + (TMR0_CLK_DIV16 == stcTmr0Init.u32ClockDiv)) + { + alpha = 3UL; } else { - cmp_val = (timeout_bits / (1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS)) - 1UL); + alpha = 2UL; } + /* TMR0_CMPAR calculation formula: CMPAR = (RTB / (2 ^ CKDIVA)) - alpha */ + ckdiv = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS); + cmp_val = ((rtb + ckdiv - 1UL) / ckdiv) - alpha; DDL_ASSERT(cmp_val <= 0xFFFFUL); stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val); TMR0_Init(TMR0_Instance, ch, &stcTmr0Init); @@ -524,7 +569,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) { - rt_uint32_t u32TransCount = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2UL; + rt_uint32_t trans_count = (serial->config.bufsz <= 1UL) ? serial->config.bufsz : serial->config.bufsz / 2UL; struct hc32_uart *uart; stc_dma_init_t dma_init; struct dma_config *uart_dma; @@ -541,6 +586,11 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) RT_ASSERT(RT_NULL != uart->config->rx_timeout->TMR0_Instance); RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance); + RT_ASSERT(RT_NULL != rx_fifo); + +#if defined (HC32F448) + INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); +#endif uart_dma = uart->config->dma_rx; /* Initialization uart rx timeout for DMA */ @@ -556,7 +606,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) dma_init.u32DestAddr = (uint32_t)rx_fifo->buffer; dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; dma_init.u32BlockSize = 1UL; - dma_init.u32TransCount = u32TransCount; + dma_init.u32TransCount = trans_count; dma_init.u32SrcAddrInc = DMA_SRC_ADDR_FIX; dma_init.u32DestAddrInc = DMA_DEST_ADDR_INC; DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init); @@ -617,26 +667,28 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* Enable DMA module */ DMA_Cmd(uart_dma->Instance, ENABLE); AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event); - USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_CPLT, DISABLE); + USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE); NVIC_EnableIRQ(uart->config->tc_irq->irq_config.irq_num); } } -#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ - defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || defined(BSP_UART7_RX_USING_DMA) +#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \ + defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \ + defined (BSP_UART7_RX_USING_DMA) static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart) { - struct rt_serial_device *serial; - rt_size_t recv_len; rt_base_t level; + rt_size_t recv_len; + struct rt_serial_device *serial; RT_ASSERT(RT_NULL != uart); RT_ASSERT(RT_NULL != uart->config->Instance); serial = &uart->serial; + RT_ASSERT(RT_NULL != serial); level = rt_hw_interrupt_disable(); - recv_len = uart->dma_rx_remain_index; - uart->dma_rx_remain_index = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel);; + recv_len = uart->dma_rx_remaining_cnt; + uart->dma_rx_remaining_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); if (recv_len) { @@ -650,24 +702,28 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) rt_base_t level; rt_size_t dma_set_cnt, cnt; rt_size_t recv_len; + struct rt_serial_device *serial; + + serial = &uart->serial; + RT_ASSERT(serial != RT_NULL); cnt = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); dma_set_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); level = rt_hw_interrupt_disable(); - if (cnt <= (uart->dma_rx_remain_index)) + if (cnt <= uart->dma_rx_remaining_cnt) { - recv_len = uart->dma_rx_remain_index - cnt; + recv_len = uart->dma_rx_remaining_cnt - cnt; } else { - recv_len = uart->dma_rx_remain_index + dma_set_cnt - cnt; + recv_len = uart->dma_rx_remaining_cnt + dma_set_cnt - cnt; } if (recv_len) { - uart->dma_rx_remain_index = cnt; - rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + uart->dma_rx_remaining_cnt = cnt; + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); } rt_hw_interrupt_enable(level); TMR0_Stop(uart->config->rx_timeout->TMR0_Instance, uart->config->rx_timeout->channel); @@ -675,8 +731,9 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) } #endif -#if defined(BSP_UART1_TX_USING_DMA) || defined(BSP_UART2_TX_USING_DMA) || defined(BSP_UART3_TX_USING_DMA) || \ - defined(BSP_UART4_TX_USING_DMA) || defined(BSP_UART6_TX_USING_DMA) || defined(BSP_UART7_TX_USING_DMA) +#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \ + defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \ + defined (BSP_UART7_RX_USING_DMA) static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) { RT_ASSERT(uart != RT_NULL); @@ -691,7 +748,46 @@ static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) #endif #endif -#if defined(BSP_USING_UART1) +#if defined (HC32F448) +static void hc32_usart_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + +#if defined (RT_SERIAL_USING_DMA) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src))) + { + hc32_uart_rxto_irq_handler(uart); + } +#endif + + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src))) + { + hc32_uart_rx_irq_handler(uart); + } + + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src))) + { + hc32_uart_tx_irq_handler(uart); + } + + if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | \ + USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src))) + { + hc32_uart_rxerr_irq_handler(uart); + } +} +#endif + +#if defined (BSP_USING_UART1) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart1_rx_irq_handler(void) { /* enter interrupt */ @@ -724,9 +820,31 @@ static void hc32_uart1_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART1_RX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART1_TX_USING_DMA) +static void hc32_uart1_tc_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined (HC32F448) +void USART1_TxComplete_Handler(void) +{ + hc32_uart1_tc_irq_handler(); +} +#endif +#endif /* BSP_UART1_TX_USING_DMA */ + +#if defined (BSP_UART1_RX_USING_DMA) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart1_rxto_irq_handler(void) { /* enter interrupt */ @@ -737,6 +855,7 @@ static void hc32_uart1_rxto_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart1_dma_rx_irq_handler(void) { @@ -749,24 +868,23 @@ static void hc32_uart1_dma_rx_irq_handler(void) rt_interrupt_leave(); } #endif /* BSP_UART1_RX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ -#if defined(BSP_UART1_TX_USING_DMA) -static void hc32_uart1_tc_irq_handler(void) +#if defined (HC32F448) +void USART1_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - hc32_uart_tc_irq_handler(&uart_obj[UART1_INDEX]); + hc32_usart_handler(&uart_obj[UART1_INDEX]); /* leave interrupt */ rt_interrupt_leave(); } -#endif /* BSP_UART1_RX_USING_DMA */ -#endif /* RT_SERIAL_USING_DMA */ - +#endif /* HC32F448 */ #endif /* BSP_USING_UART1 */ -#if defined(BSP_USING_UART2) +#if defined (BSP_USING_UART2) #if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart2_rx_irq_handler(void) { @@ -802,8 +920,8 @@ static void hc32_uart2_rxerr_irq_handler(void) } #endif /* HC32F460, HC32F4A0 */ -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART2_TX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART2_TX_USING_DMA) static void hc32_uart2_tc_irq_handler(void) { /* enter interrupt */ @@ -814,9 +932,16 @@ static void hc32_uart2_tc_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } + +#if defined (HC32F448) +void USART2_TxComplete_Handler(void) +{ + hc32_uart2_tc_irq_handler(); +} +#endif #endif /* BSP_UART2_TX_USING_DMA */ -#if defined(BSP_UART2_RX_USING_DMA) +#if defined (BSP_UART2_RX_USING_DMA) #if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart2_rxto_irq_handler(void) { @@ -828,7 +953,7 @@ static void hc32_uart2_rxto_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart2_dma_rx_irq_handler(void) { @@ -839,14 +964,26 @@ static void hc32_uart2_dma_rx_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); - } #endif /* BSP_UART2_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ +#if defined (HC32F448) +void USART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART2 */ -#if defined(BSP_USING_UART3) +#if defined (BSP_USING_UART3) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart3_rx_irq_handler(void) { /* enter interrupt */ @@ -880,8 +1017,8 @@ static void hc32_uart3_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART3_TX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART3_TX_USING_DMA) static void hc32_uart3_tc_irq_handler(void) { /* enter interrupt */ @@ -894,7 +1031,7 @@ static void hc32_uart3_tc_irq_handler(void) } #endif /* BSP_UART3_TX_USING_DMA */ -#if defined(BSP_UART3_RX_USING_DMA) +#if defined (BSP_UART3_RX_USING_DMA) static void hc32_uart3_rxto_irq_handler(void) { /* enter interrupt */ @@ -919,9 +1056,24 @@ static void hc32_uart3_dma_rx_irq_handler(void) } #endif /* BSP_UART3_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ +#endif /* HC32F460, HC32F4A0 */ + +#if defined (HC32F448) +void USART3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART3 */ -#if defined(BSP_USING_UART4) +#if defined (BSP_USING_UART4) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart4_rx_irq_handler(void) { /* enter interrupt */ @@ -954,8 +1106,10 @@ static void hc32_uart4_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART4_TX_USING_DMA) +#endif /* HC32F460, HC32F4A0 */ + +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART4_TX_USING_DMA) static void hc32_uart4_tc_irq_handler(void) { /* enter interrupt */ @@ -966,9 +1120,17 @@ static void hc32_uart4_tc_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } + +#if defined (HC32F448) +void USART4_TxComplete_Handler(void) +{ + hc32_uart4_tc_irq_handler(); +} +#endif /* HC32F448 */ #endif /* BSP_UART4_TX_USING_DMA */ -#if defined(BSP_UART4_RX_USING_DMA) +#if defined (BSP_UART4_RX_USING_DMA) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart4_rxto_irq_handler(void) { /* enter interrupt */ @@ -979,6 +1141,7 @@ static void hc32_uart4_rxto_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart4_dma_rx_irq_handler(void) { @@ -989,13 +1152,26 @@ static void hc32_uart4_dma_rx_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); - } #endif /* BSP_UART4_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ + +#if defined (HC32F448) +void USART4_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART4 */ -#if defined(BSP_USING_UART5) +#if defined (BSP_USING_UART5) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart5_rx_irq_handler(void) { /* enter interrupt */ @@ -1028,9 +1204,57 @@ static void hc32_uart5_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ + +#if defined (HC32F448) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART5_TX_USING_DMA) +static void hc32_uart5_tc_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void USART5_TxComplete_Handler(void) +{ + hc32_uart5_tc_irq_handler(); +} +#endif /* BSP_UART5_TX_USING_DMA */ + +#if defined (BSP_UART5_RX_USING_DMA) +static void hc32_uart5_dma_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART5_RX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +void USART5_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART5 */ -#if defined(BSP_USING_UART6) +#if defined (BSP_USING_UART6) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart6_rx_irq_handler(void) { /* enter interrupt */ @@ -1064,8 +1288,8 @@ static void hc32_uart6_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART6_TX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART6_TX_USING_DMA) static void hc32_uart6_tc_irq_handler(void) { /* enter interrupt */ @@ -1102,9 +1326,23 @@ static void hc32_uart6_dma_rx_irq_handler(void) } #endif /* BSP_UART6_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ +#endif /* HC32F460, HC32F4A0 */ + +#if defined (HC32F448) +void USART6_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART6 */ -#if defined(BSP_USING_UART7) +#if defined (BSP_USING_UART7) static void hc32_uart7_rx_irq_handler(void) { /* enter interrupt */ @@ -1138,8 +1376,8 @@ static void hc32_uart7_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART7_TX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART7_TX_USING_DMA) static void hc32_uart7_tc_irq_handler(void) { /* enter interrupt */ @@ -1152,7 +1390,7 @@ static void hc32_uart7_tc_irq_handler(void) } #endif /* BSP_UART7_TX_USING_DMA */ -#if defined(BSP_UART7_RX_USING_DMA) +#if defined (BSP_UART7_RX_USING_DMA) static void hc32_uart7_rxto_irq_handler(void) { /* enter interrupt */ @@ -1178,7 +1416,7 @@ static void hc32_uart7_dma_rx_irq_handler(void) #endif /* RT_SERIAL_USING_DMA */ #endif /* BSP_USING_UART7 */ -#if defined(BSP_USING_UART8) +#if defined (BSP_USING_UART8) static void hc32_uart8_rx_irq_handler(void) { /* enter interrupt */ @@ -1213,7 +1451,7 @@ static void hc32_uart8_rxerr_irq_handler(void) } #endif /* BSP_USING_UART8 */ -#if defined(BSP_USING_UART9) +#if defined (BSP_USING_UART9) static void hc32_uart9_rx_irq_handler(void) { /* enter interrupt */ @@ -1248,7 +1486,7 @@ static void hc32_uart9_rxerr_irq_handler(void) } #endif /* BSP_USING_UART9 */ -#if defined(BSP_USING_UART10) +#if defined (BSP_USING_UART10) static void hc32_uart10_rx_irq_handler(void) { /* enter interrupt */ @@ -1298,7 +1536,9 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG; uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler; +#if defined (HC32F460) || defined (HC32F4A0) uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler; +#endif uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout; uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; #endif @@ -1337,6 +1577,7 @@ static void hc32_uart_get_dma_info(void) #ifdef BSP_USING_UART3 uart_obj[UART3_INDEX].uart_dma_flag = 0; +#if defined (HC32F460) || defined (HC32F4A0) #ifdef BSP_UART3_RX_USING_DMA uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; @@ -1355,6 +1596,7 @@ static void hc32_uart_get_dma_info(void) uart_config[UART3_INDEX].tc_irq = &uart3_tc_irq; #endif #endif +#endif #ifdef BSP_USING_UART4 uart_obj[UART4_INDEX].uart_dma_flag = 0; @@ -1363,7 +1605,9 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG; uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler; +#if defined (HC32F460) || defined (HC32F4A0) uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler; +#endif uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout; uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; #endif @@ -1377,8 +1621,31 @@ static void hc32_uart_get_dma_info(void) #endif #endif +#ifdef BSP_USING_UART5 + uart_obj[UART5_INDEX].uart_dma_flag = 0; +#if defined (HC32F448) +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; + static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG; + uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler; + uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout; + uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; +#endif +#ifdef BSP_UART5_TX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; + uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx; + static struct hc32_uart_irq_config uart5_tc_irq = UART5_TX_CPLT_CONFIG; + uart5_tc_irq.irq_callback = hc32_uart5_tc_irq_handler; + uart_config[UART5_INDEX].tc_irq = &uart5_tc_irq; +#endif +#endif +#endif + #ifdef BSP_USING_UART6 uart_obj[UART6_INDEX].uart_dma_flag = 0; +#if defined (HC32F460) || defined (HC32F4A0) #ifdef BSP_UART6_RX_USING_DMA uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; @@ -1397,6 +1664,7 @@ static void hc32_uart_get_dma_info(void) uart_config[UART6_INDEX].tc_irq = &uart6_tc_irq; #endif #endif +#endif #ifdef BSP_USING_UART7 uart_obj[UART7_INDEX].uart_dma_flag = 0; @@ -1418,6 +1686,18 @@ static void hc32_uart_get_dma_info(void) uart_config[UART7_INDEX].tc_irq = &uart7_tc_irq; #endif #endif + +#ifdef BSP_USING_UART8 + uart_obj[UART8_INDEX].uart_dma_flag = 0; +#endif + +#ifdef BSP_USING_UART9 + uart_obj[UART9_INDEX].uart_dma_flag = 0; +#endif + +#ifdef BSP_USING_UART10 + uart_obj[UART10_INDEX].uart_dma_flag = 0; +#endif } #if defined (HC32F460) || defined (HC32F4A0) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.h b/bsp/hc32/libraries/hc32_drivers/drv_usart.h index 2c81ac8bc2..86be002b8a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -57,6 +57,14 @@ struct hc32_uart_config struct hc32_uart_irq_config rxerr_irq; struct hc32_uart_irq_config rx_irq; struct hc32_uart_irq_config tx_irq; +#elif defined (HC32F448) + IRQn_Type irq_num; + en_int_src_t rxerr_int_src; + en_int_src_t tx_int_src; + en_int_src_t rx_int_src; +#ifdef RT_SERIAL_USING_DMA + en_int_src_t rxto_int_src; +#endif #endif #ifdef RT_SERIAL_USING_DMA @@ -73,7 +81,7 @@ struct hc32_uart { struct hc32_uart_config *config; #ifdef RT_SERIAL_USING_DMA - rt_size_t dma_rx_remain_index; + rt_size_t dma_rx_remaining_cnt; #endif rt_uint16_t uart_dma_flag; struct rt_serial_device serial; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c index 866c951153..9299757e60 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-04-28 CDT first version + * 2024-02-06 CDT support HC32F448 */ /******************************************************************************* @@ -17,14 +18,13 @@ #ifdef RT_USING_SERIAL_V2 -#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \ - defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \ - defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \ - defined(BSP_USING_UART10) +#if defined (BSP_USING_UART1) || defined (BSP_USING_UART2) || defined (BSP_USING_UART3) || \ + defined (BSP_USING_UART4) || defined (BSP_USING_UART5) || defined (BSP_USING_UART6) || \ + defined (BSP_USING_UART7) || defined (BSP_USING_UART8) || defined (BSP_USING_UART9) || \ + defined (BSP_USING_UART10) #include "drv_usart_v2.h" #include "board_config.h" -#include "board.h" /******************************************************************************* * Local type definitions ('typedef') @@ -42,16 +42,12 @@ #define DMA_TRANS_CNT(unit, ch) \ (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) -#define USART_TCI_ENABLE(unit) \ - SET_REG32_BIT(unit->CR1, USART_INT_TX_CPLT) - - #define UART_BAUDRATE_ERR_MAX (0.025F) #if defined (HC32F460) #define FCG_USART_CLK FCG_Fcg1PeriphClockCmd -#elif defined(HC32F4A0) +#elif defined(HC32F4A0) || defined (HC32F448) #define FCG_USART_CLK FCG_Fcg3PeriphClockCmd #endif @@ -166,6 +162,9 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co #elif defined (HC32F460) if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) +#elif defined (HC32F448) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ + (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) #endif { uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE; @@ -221,7 +220,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co { uart_init.u32FirstBit = USART_FIRST_BIT_MSB; } -#if defined (HC32F4A0) +#if defined (HC32F4A0) || defined (HC32F448) switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: @@ -269,6 +268,12 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co /* Enable error interrupt */ #if defined (HC32F460) || defined (HC32F4A0) NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num); +#elif defined (HC32F448) + INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE); + INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); + INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE); + NVIC_EnableIRQ(uart->config->irq_num); + INTC_IntSrcCmd(uart->config->tc_irq.irq_config.int_src, ENABLE); #endif USART_FuncCmd(uart->config->Instance, USART_TX | USART_RX | USART_INT_RX, ENABLE); @@ -287,16 +292,24 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING)) { if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { ctrl_arg = RT_DEVICE_FLAG_DMA_RX; + } else + { ctrl_arg = RT_DEVICE_FLAG_INT_RX; + } } else if (ctrl_arg & (RT_DEVICE_FLAG_TX_BLOCKING | RT_DEVICE_FLAG_TX_NON_BLOCKING)) { if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { ctrl_arg = RT_DEVICE_FLAG_DMA_TX; + } else + { ctrl_arg = RT_DEVICE_FLAG_INT_TX; + } } switch (cmd) @@ -307,8 +320,9 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg { #if defined (HC32F460) || defined (HC32F4A0) NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num); - USART_FuncCmd(uart->config->Instance, USART_INT_RX, DISABLE); INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num); +#elif defined (HC32F448) + INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); #endif } else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg) @@ -319,6 +333,10 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE); INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num); +#elif defined (HC32F448) + NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num); + INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num); + USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE); #endif } #ifdef RT_SERIAL_USING_DMA @@ -344,11 +362,26 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg else { INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); + INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num); hc32_install_irq_handler(&uart->config->tx_irq.irq_config, uart->config->tx_irq.irq_callback, RT_TRUE); hc32_install_irq_handler(&uart->config->tc_irq.irq_config, uart->config->tc_irq.irq_callback, RT_TRUE); USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE); USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE); } +#elif defined (HC32F448) + /* NVIC config */ + if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) + { + /* intsrc enable */ + INTC_IntSrcCmd(uart->config->rx_int_src, ENABLE); + USART_FuncCmd(uart->config->Instance, USART_INT_RX, ENABLE); + } + else + { + NVIC_ClearPendingIRQ(uart->config->tc_irq.irq_config.irq_num); + NVIC_EnableIRQ(uart->config->tc_irq.irq_config.irq_num); + USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE); + } #endif break; case RT_DEVICE_CTRL_CONFIG: @@ -417,19 +450,19 @@ static rt_ssize_t hc32_transmit(struct rt_serial_device *serial, rt_size_t size, rt_uint32_t tx_flag) { - struct hc32_uart *uart; #ifdef RT_SERIAL_USING_DMA struct dma_config *uart_dma; #endif - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(buf != RT_NULL); + RT_ASSERT(RT_NULL != serial); + RT_ASSERT(RT_NULL != buf); - if (size == 0) + if (0 == size) { return 0; } + uart = rt_container_of(serial, struct hc32_uart, serial); if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) { @@ -495,18 +528,19 @@ static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) { - RT_ASSERT(uart != RT_NULL); + RT_ASSERT(RT_NULL != uart); + + USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE); + if (uart->uart_dma_flag & RT_DEVICE_FLAG_DMA_TX) { #ifdef RT_SERIAL_USING_DMA DMA_ClearTransCompleteStatus(uart->config->dma_tx->Instance, (DMA_FLAG_TC_CH0 | DMA_FLAG_BTC_CH0) << uart->config->dma_tx->channel); #endif - USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE); rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); } else { - USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_CPLT), DISABLE); rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); } } @@ -515,10 +549,12 @@ static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { struct hc32_uart *uart; - uint32_t cmp_val; CM_TMR0_TypeDef *TMR0_Instance; uint8_t ch; - uint32_t timeout_bits; + uint32_t rtb; + uint32_t alpha; + uint32_t ckdiv; + uint32_t cmp_val; stc_tmr0_init_t stcTmr0Init; RT_ASSERT(RT_NULL != serial); @@ -527,7 +563,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) TMR0_Instance = uart->config->rx_timeout->TMR0_Instance; ch = uart->config->rx_timeout->channel; - timeout_bits = uart->config->rx_timeout->timeout_bits; + rtb = uart->config->rx_timeout->timeout_bits; #if defined (HC32F460) if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance)) { @@ -546,6 +582,15 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } +#elif defined (HC32F448) + if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) + { + RT_ASSERT(TMR0_CH_A == ch); + } + else if ((CM_USART2 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) + { + RT_ASSERT(TMR0_CH_B == ch); + } #endif FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); @@ -557,16 +602,25 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) stcTmr0Init.u32ClockSrc = TMR0_CLK_SRC_XTAL32; if (TMR0_CLK_DIV1 == stcTmr0Init.u32ClockDiv) { - cmp_val = (timeout_bits - 4UL); + alpha = 7UL; } else if (TMR0_CLK_DIV2 == stcTmr0Init.u32ClockDiv) { - cmp_val = (timeout_bits / 2UL - 2UL); + alpha = 5UL; + } + else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || \ + (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || \ + (TMR0_CLK_DIV16 == stcTmr0Init.u32ClockDiv)) + { + alpha = 3UL; } else { - cmp_val = (timeout_bits / (1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS)) - 1UL); + alpha = 2UL; } + /* TMR0_CMPAR calculation formula: CMPAR = (RTB / (2 ^ CKDIVA)) - alpha */ + ckdiv = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS); + cmp_val = ((rtb + ckdiv - 1UL) / ckdiv) - alpha; DDL_ASSERT(cmp_val <= 0xFFFFUL); stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val); TMR0_Init(TMR0_Instance, ch, &stcTmr0Init); @@ -601,7 +655,11 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) RT_ASSERT(RT_NULL != uart->config->rx_timeout->TMR0_Instance); RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance); - RT_ASSERT(rx_fifo != RT_NULL); + RT_ASSERT(RT_NULL != rx_fifo); + +#if defined (HC32F448) + INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); +#endif uart_dma = uart->config->dma_rx; /* Initialization uart rx timeout for DMA */ @@ -678,24 +736,29 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* Enable DMA module */ DMA_Cmd(uart_dma->Instance, ENABLE); AOS_SetTriggerEventSrc(uart_dma->trigger_select, uart_dma->trigger_event); - USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_CPLT, DISABLE); + USART_FuncCmd(uart->config->Instance, (USART_TX | USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE); NVIC_EnableIRQ(uart->config->tc_irq.irq_config.irq_num); } } -#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ - defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || defined(BSP_UART7_RX_USING_DMA) +#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \ + defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \ + defined (BSP_UART7_RX_USING_DMA) static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart) { rt_base_t level; rt_size_t recv_len; struct rt_serial_device *serial; + RT_ASSERT(RT_NULL != uart); + RT_ASSERT(RT_NULL != uart->config->Instance); + serial = &uart->serial; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(RT_NULL != serial); level = rt_hw_interrupt_disable(); recv_len = uart->dma_rx_remaining_cnt; uart->dma_rx_remaining_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); + if (recv_len) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); @@ -706,28 +769,29 @@ static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart) static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) { rt_base_t level; - rt_size_t recv_len, counter, dam_set_count; + rt_size_t dma_set_cnt, cnt; + rt_size_t recv_len; struct rt_serial_device *serial; serial = &uart->serial; RT_ASSERT(serial != RT_NULL); - counter = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); - dam_set_count = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); - level = rt_hw_interrupt_disable(); + cnt = DMA_TRANS_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); + dma_set_cnt = DMA_TRANS_SET_CNT(uart->config->dma_rx->Instance, uart->config->dma_rx->channel); - if (counter <= (uart->dma_rx_remaining_cnt)) + level = rt_hw_interrupt_disable(); + if (cnt <= uart->dma_rx_remaining_cnt) { - recv_len = uart->dma_rx_remaining_cnt - counter; + recv_len = uart->dma_rx_remaining_cnt - cnt; } else { - recv_len = uart->dma_rx_remaining_cnt + dam_set_count - counter; + recv_len = uart->dma_rx_remaining_cnt + dma_set_cnt - cnt; } if (recv_len) { - uart->dma_rx_remaining_cnt = counter; + uart->dma_rx_remaining_cnt = cnt; rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); } rt_hw_interrupt_enable(level); @@ -737,7 +801,46 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) #endif #endif -#if defined(BSP_USING_UART1) +#if defined (HC32F448) +static void hc32_usart_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + +#if defined (RT_SERIAL_USING_DMA) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src))) + { + hc32_uart_rxto_irq_handler(uart); + } +#endif + + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src))) + { + hc32_uart_rx_irq_handler(uart); + } + + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src))) + { + hc32_uart_tx_irq_handler(uart); + } + + if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | \ + USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && \ + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ + (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src))) + { + hc32_uart_rxerr_irq_handler(uart); + } +} +#endif + +#if defined (BSP_USING_UART1) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart1_rx_irq_handler(void) { /* enter interrupt */ @@ -770,6 +873,7 @@ static void hc32_uart1_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart1_tc_irq_handler(void) { @@ -782,8 +886,9 @@ static void hc32_uart1_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART1_RX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART1_RX_USING_DMA) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart1_rxto_irq_handler(void) { /* enter interrupt */ @@ -794,6 +899,7 @@ static void hc32_uart1_rxto_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart1_dma_rx_irq_handler(void) { @@ -806,11 +912,34 @@ static void hc32_uart1_dma_rx_irq_handler(void) rt_interrupt_leave(); } #endif /* BSP_UART1_RX_USING_DMA */ - #endif /* RT_SERIAL_USING_DMA */ + +#if defined (HC32F448) +void USART1_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void USART1_TxComplete_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart1_tc_irq_handler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART1 */ -#if defined(BSP_USING_UART2) +#if defined (BSP_USING_UART2) #if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart2_rx_irq_handler(void) { @@ -844,7 +973,7 @@ static void hc32_uart2_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined (HC32F460) || defined (HC32F4A0) */ +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart2_tc_irq_handler(void) { @@ -857,8 +986,8 @@ static void hc32_uart2_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART2_RX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART2_RX_USING_DMA) #if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart2_rxto_irq_handler(void) { @@ -870,7 +999,7 @@ static void hc32_uart2_rxto_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart2_dma_rx_irq_handler(void) { @@ -881,15 +1010,37 @@ static void hc32_uart2_dma_rx_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); - } - #endif /* BSP_UART2_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ +#if defined (HC32F448) +void USART2_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void USART2_TxComplete_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart2_tc_irq_handler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART2 */ -#if defined(BSP_USING_UART3) +#if defined (BSP_USING_UART3) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart3_rx_irq_handler(void) { /* enter interrupt */ @@ -922,6 +1073,7 @@ static void hc32_uart3_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart3_tc_irq_handler(void) { @@ -934,8 +1086,9 @@ static void hc32_uart3_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART3_RX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART3_RX_USING_DMA) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart3_rxto_irq_handler(void) { /* enter interrupt */ @@ -958,11 +1111,37 @@ static void hc32_uart3_dma_rx_irq_handler(void) rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ #endif /* BSP_UART3_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ + +#if defined (HC32F448) +void USART3_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void USART3_TxComplete_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart3_tc_irq_handler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART3 */ -#if defined(BSP_USING_UART4) +#if defined (BSP_USING_UART4) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart4_rx_irq_handler(void) { /* enter interrupt */ @@ -995,6 +1174,7 @@ static void hc32_uart4_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart4_tc_irq_handler(void) { @@ -1007,8 +1187,9 @@ static void hc32_uart4_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART4_RX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART4_RX_USING_DMA) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart4_rxto_irq_handler(void) { /* enter interrupt */ @@ -1019,6 +1200,7 @@ static void hc32_uart4_rxto_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart4_dma_rx_irq_handler(void) { @@ -1029,13 +1211,37 @@ static void hc32_uart4_dma_rx_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); - } #endif /* BSP_UART4_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ + +#if defined (HC32F448) +void USART4_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void USART4_TxComplete_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart4_tc_irq_handler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART4 */ -#if defined(BSP_USING_UART5) +#if defined (BSP_USING_UART5) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart5_rx_irq_handler(void) { /* enter interrupt */ @@ -1068,6 +1274,7 @@ static void hc32_uart5_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart5_tc_irq_handler(void) { @@ -1079,9 +1286,49 @@ static void hc32_uart5_tc_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } + +#if defined (HC32F448) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART5_RX_USING_DMA) +static void hc32_uart5_dma_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_UART5_RX_USING_DMA */ +#endif /* RT_SERIAL_USING_DMA */ + +void USART5_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void USART5_TxComplete_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart5_tc_irq_handler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART5 */ -#if defined(BSP_USING_UART6) +#if defined (BSP_USING_UART6) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart6_rx_irq_handler(void) { /* enter interrupt */ @@ -1114,6 +1361,7 @@ static void hc32_uart6_rxerr_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ static void hc32_uart6_tc_irq_handler(void) { @@ -1126,8 +1374,9 @@ static void hc32_uart6_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART6_RX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART6_RX_USING_DMA) +#if defined (HC32F460) || defined (HC32F4A0) static void hc32_uart6_rxto_irq_handler(void) { /* enter interrupt */ @@ -1149,11 +1398,36 @@ static void hc32_uart6_dma_rx_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); } +#endif /* HC32F460, HC32F4A0 */ #endif /* BSP_UART6_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ + +#if defined (HC32F448) +void USART6_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_usart_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +void USART6_TxComplete_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart6_tc_irq_handler(); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* HC32F448 */ #endif /* BSP_USING_UART6 */ -#if defined(BSP_USING_UART7) +#if defined (BSP_USING_UART7) static void hc32_uart7_rx_irq_handler(void) { /* enter interrupt */ @@ -1198,8 +1472,8 @@ static void hc32_uart7_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) -#if defined(BSP_UART7_RX_USING_DMA) +#if defined (RT_SERIAL_USING_DMA) +#if defined (BSP_UART7_RX_USING_DMA) static void hc32_uart7_rxto_irq_handler(void) { /* enter interrupt */ @@ -1225,7 +1499,7 @@ static void hc32_uart7_dma_rx_irq_handler(void) #endif /* RT_SERIAL_USING_DMA */ #endif /* BSP_USING_UART7 */ -#if defined(BSP_USING_UART8) +#if defined (BSP_USING_UART8) static void hc32_uart8_rx_irq_handler(void) { /* enter interrupt */ @@ -1271,7 +1545,7 @@ static void hc32_uart8_tc_irq_handler(void) } #endif /* BSP_USING_UART8 */ -#if defined(BSP_USING_UART9) +#if defined (BSP_USING_UART9) static void hc32_uart9_rx_irq_handler(void) { /* enter interrupt */ @@ -1317,7 +1591,7 @@ static void hc32_uart9_tc_irq_handler(void) } #endif /* BSP_USING_UART9 */ -#if defined(BSP_USING_UART10) +#if defined (BSP_USING_UART10) static void hc32_uart10_rx_irq_handler(void) { /* enter interrupt */ @@ -1383,7 +1657,9 @@ static void hc32_uart_get_info(void) static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG; uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler; +#if defined (HC32F460) || defined (HC32F4A0) uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler; +#endif uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout; uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; #endif @@ -1422,6 +1698,7 @@ static void hc32_uart_get_info(void) uart_obj[UART3_INDEX].serial.config = config; uart_obj[UART3_INDEX].serial.config.rx_bufsz = BSP_UART3_RX_BUFSIZE; uart_obj[UART3_INDEX].serial.config.tx_bufsz = BSP_UART3_TX_BUFSIZE; +#if defined (HC32F460) || defined (HC32F4A0) #ifdef BSP_UART3_RX_USING_DMA uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config uart3_dma_rx = UART3_DMA_RX_CONFIG; @@ -1437,6 +1714,7 @@ static void hc32_uart_get_info(void) uart_config[UART3_INDEX].dma_tx = &uart3_dma_tx; #endif #endif +#endif #ifdef BSP_USING_UART4 uart_obj[UART4_INDEX].uart_dma_flag = 0; @@ -1448,7 +1726,9 @@ static void hc32_uart_get_info(void) static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG; uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler; +#if defined (HC32F460) || defined (HC32F4A0) uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler; +#endif uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout; uart_config[UART4_INDEX].dma_rx = &uart4_dma_rx; #endif @@ -1464,6 +1744,21 @@ static void hc32_uart_get_info(void) uart_obj[UART5_INDEX].serial.config = config; uart_obj[UART5_INDEX].serial.config.rx_bufsz = BSP_UART5_RX_BUFSIZE; uart_obj[UART5_INDEX].serial.config.tx_bufsz = BSP_UART5_TX_BUFSIZE; +#if defined (HC32F460) +#ifdef BSP_UART5_RX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; + static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG; + uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler; + uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout; + uart_config[UART5_INDEX].dma_rx = &uart5_dma_rx; +#endif +#ifdef BSP_UART5_TX_USING_DMA + uart_obj[UART5_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config uart5_dma_tx = UART5_DMA_TX_CONFIG; + uart_config[UART5_INDEX].dma_tx = &uart5_dma_tx; +#endif +#endif #endif #ifdef BSP_USING_UART6 @@ -1471,6 +1766,7 @@ static void hc32_uart_get_info(void) uart_obj[UART6_INDEX].serial.config = config; uart_obj[UART6_INDEX].serial.config.rx_bufsz = BSP_UART6_RX_BUFSIZE; uart_obj[UART6_INDEX].serial.config.tx_bufsz = BSP_UART6_TX_BUFSIZE; +#if defined (HC32F460) || defined (HC32F4A0) #ifdef BSP_UART6_RX_USING_DMA uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config uart6_dma_rx = UART6_DMA_RX_CONFIG; @@ -1486,6 +1782,7 @@ static void hc32_uart_get_info(void) uart_config[UART6_INDEX].dma_tx = &uart6_dma_tx; #endif #endif +#endif #ifdef BSP_USING_UART7 uart_obj[UART7_INDEX].uart_dma_flag = 0; @@ -1619,7 +1916,46 @@ static void hc32_get_uart_callback(void) uart_config[UART10_INDEX].tc_irq.irq_callback = hc32_uart10_tc_irq_handler; #endif } -#endif /* defined (HC32F460) || defined (HC32F4A0) */ +#elif defined (HC32F448) +/** + * @brief This function gets uart irq handle. + * @param None + * @retval None + */ +static void hc32_get_uart_callback(void) +{ +#ifdef BSP_USING_UART1 + struct hc32_uart_irq_config uart1_tc_irq = UART1_TX_CPLT_CONFIG; + uart_config[UART1_INDEX].tc_irq = uart1_tc_irq; + uart_config[UART1_INDEX].tc_irq.irq_callback = hc32_uart1_tc_irq_handler; +#endif +#ifdef BSP_USING_UART2 + struct hc32_uart_irq_config uart2_tc_irq = UART2_TX_CPLT_CONFIG; + uart_config[UART2_INDEX].tc_irq = uart2_tc_irq; + uart_config[UART2_INDEX].tc_irq.irq_callback = hc32_uart2_tc_irq_handler; +#endif +#ifdef BSP_USING_UART3 + struct hc32_uart_irq_config uart3_tc_irq = UART3_TX_CPLT_CONFIG; + uart_config[UART3_INDEX].tc_irq = uart3_tc_irq; + uart_config[UART3_INDEX].tc_irq.irq_callback = hc32_uart3_tc_irq_handler; +#endif +#ifdef BSP_USING_UART4 + struct hc32_uart_irq_config uart4_tc_irq = UART4_TX_CPLT_CONFIG; + uart_config[UART4_INDEX].tc_irq = uart4_tc_irq; + uart_config[UART4_INDEX].tc_irq.irq_callback = hc32_uart4_tc_irq_handler; +#endif +#ifdef BSP_USING_UART5 + struct hc32_uart_irq_config uart5_tc_irq = UART5_TX_CPLT_CONFIG; + uart_config[UART5_INDEX].tc_irq = uart5_tc_irq; + uart_config[UART5_INDEX].tc_irq.irq_callback = hc32_uart5_tc_irq_handler; +#endif +#ifdef BSP_USING_UART6 + struct hc32_uart_irq_config uart6_tc_irq = UART6_TX_CPLT_CONFIG; + uart_config[UART6_INDEX].tc_irq = uart6_tc_irq; + uart_config[UART6_INDEX].tc_irq.irq_callback = hc32_uart6_tc_irq_handler; +#endif +} +#endif /* HC32F448 */ static const struct rt_uart_ops hc32_uart_ops = { @@ -1636,9 +1972,7 @@ int rt_hw_usart_init(void) rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart); hc32_uart_get_info(); -#if defined (HC32F460) || defined (HC32F4A0) hc32_get_uart_callback(); -#endif for (int i = 0; i < obj_num; i++) { diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h index fa4cd93b36..f3a386d0d9 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h @@ -57,6 +57,14 @@ struct hc32_uart_config struct hc32_uart_irq_config rxerr_irq; struct hc32_uart_irq_config rx_irq; struct hc32_uart_irq_config tx_irq; +#elif defined (HC32F448) + IRQn_Type irq_num; + en_int_src_t rxerr_int_src; + en_int_src_t tx_int_src; + en_int_src_t rx_int_src; +#ifdef RT_SERIAL_USING_DMA + en_int_src_t rxto_int_src; +#endif #endif struct hc32_uart_irq_config tc_irq; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c index c5e83ddd1d..113e3772c7 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #else #if defined(HC32F4A0) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_RTCLRC) - #elif defined(HC32F460) + #elif defined(HC32F460) || defined(HC32F448) #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_LRC) #endif #define PWC_WKT_COUNT_FRQ (32768UL) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wktm.h b/bsp/hc32/libraries/hc32_drivers/drv_wktm.h index 00f77f81f4..e901ddf0c0 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wktm.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_wktm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022, Xiaohua Semiconductor Co., Ltd. + * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * diff --git a/bsp/hc32/libraries/hc32f448_ddl/ChangeLog.md b/bsp/hc32/libraries/hc32f448_ddl/ChangeLog.md new file mode 100644 index 0000000000..e2059b3611 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/ChangeLog.md @@ -0,0 +1,362 @@ +# Update History +------ +## V1.1.0 Dec 15, 2023 +#### documents +#### drivers +- ##### bsp/components + - **24cxx** + - Add null pointer check + - **gt9xx** + - Add null pointer check + - **nt35510** + - Add null pointer check + - **tca9539** + - Add null pointer check + - **w25qxx** + - Add null pointer check +- ##### bsp/ev_hc32f448_lqfp80 + - Add API BSP_XTAL32_Init() + - Optimize function BSP_I2C_Init() + - Update EXCLK clock frequency: 100MHz -> 50MHZ in function BSP_CLK_Init() + - Add include file named hc32_ll_fcm.h and add declaration of BSP_XTAL32_Init() + - Modify I2C baudrate: 400000 -> 100000 + - Modify the timing: EXCLK 100MHz -> 40MHz +- ##### cmsis/Device + - Optimize TMR4_OCMRxx + - Rename EMB_CTL1 register bit: SRAMERREN -> SRAMECCERREN +- ##### hc32_ll_driver + - **adc** + - Modify typo + - API fixed: ADC_DeInit() + - Add declaration of API ADC_MxChCmd(), ADC_ConvDataAverageMxChCmd(), and add defgroup ADC_Mx_Channel + - Add declaration of API ADC_GetResolution() + - Add API ADC_MxChCmd(),ADC_ConvDataAverageMxChCmd + - Add API ADC_GetResolution() + - **clk** + - Modify comment + - Refine API CLK_XtalStdInit. and add API CLK_XtalStdCmd, CLK_SetXtalStdExceptionType + - Modify API CLK_Xtal32Cmd(), CLK_MrcCmd() and CLK_LrcCmd(), use DDL_DelayUS() to replace CLK_Delay() + - **cmp** + - Modify typo + - **ctc** + - Modify typo + - **dac** + - Refine data validation + - Add assert for set DAC source and modify IS_AMP_CTRL_ALLOWED() + - **dbgc** + - Remove API DBGC_GetChipID() + - Add macro definition DBGC_Trace_Mode + - Add declaration of API DBGC_TraceIoCmd,DBGC_TraceModeConfig + - Remove API DBGC_GetChipID()A + - Add assert to DBGC_PeriphCmd & DBGC_Periph2Cmd + - Add assert IS_DGBC_TRACE_MD and add API DBGC_TraceIoCmd,DBGC_TraceModeConfig + - **dcu** + - Modify typo + - Modify function DCU_IntCmd() for misra + - **dma** + - Add API DMA_SetDataWidth() + - Delete group DMA_AHB_HPROT_Config + - Delete API DMA_AHB_HProtPrivilegeCmd() + - Modify API input param type:u16->u32 + - Add structure stc_dma_rc_nonseq_init_t + - Add API DMA_ReconfigNonSeqStructInit() & DMA_ReconfigNonSeqInit() + - Optimize set blocksize & repeat count process + - Add DMA Repeat size assert + - Use macros replace immediate data, modify IS_DMA_NON_SEQ_TRANS_CNT + - **efm** + - Rename EFM_DataCacheResetCmd() as EFM_CacheRamReset() and modify comment + - Optimized macro group EFM_Remap_Size definitions + - Add structure of stc_efm_location_t and declaration of API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID() + - Modify typo + - Remove address assert from EFM_ReadByte() + - Refine EFM_SequenceProgram() & EFM_ChipErase(), and put them in RAM + - Add API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID() + - Modify flash sector number defined and API EFM_SequenceSectorOperateCmd() + - **emb** + - Update EMB_CTL1_CMPEN0~3 to EMB_CTL1_CMPEN1~4 + - Add stc_emb_monitor_sys_t to combine osc, sram, lockup, lvd + - Replace macro: EMB_CTL1_SRAMERREN -> EMB_CTL1_SRAMECCERREN + - Add marco EMB_FLAG_CLR_ALL + - Function EMB_TMR4_Init don't call EMB_DeInit + - Function EMB_TMR6_Init don't call EMB_DeInit + - Modify stc_emb_monitor_sys_t structure relevant code + - Modify API EMB_ClearStatus assert + - **gpio** + - Modify GPIO_SetFunc() + - Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd + - Optimize API: GPIO_Init(), GPIO_SetFunc(), GPIO_SubFuncCmd(), GPIO_InputMOSCmd(), GPIO_AnalogCmd(), GPIO_ExtIntCmd() + - Add assert for GPIO register lock status in API GPIO_AnalogCmd(), GPIO_ExtIntCmd() + - **i2c** + - Move macro define I2C_SRC_CLK to head file and add marco I2C_WIDTH_MAX_IMME + - Rename I2C_FIFO_FLAG_xx as I2C_FLAG_xx_FIFO_xx, I2C_INT_RFREQ as I2C_INT_RX_FIFO_REQ + - Adjust I2C_FLAG_ALL & I2C_FLAG_CLR_ALL & I2C_INT_ALL + - Add I2C_Flag_Clear def group + - Remove API I2C_FIFO_ClearRequestStatus() & I2C_FIFO_GetStatus + - Fix I2C_Deinit + - Move macro define I2C_SRC_CLK to head file + - Modify I2C_Restart() + - Refine I2C Flag & API I2C_SlaveAddrConfig/I2C_SlaveMaskAddrConfig + - **icg** + - Modify macro defineICG_SWDT_LPM_CNT_CONTINUE -> ICG_SWDT_LPM_CNT_CONT + - **interrupts** + - Add declaration of API INTC_GetIntSrcState() + - Remove space line + - Add API INTC_GetIntSrcState() + - **mcan** + - Removed definitions related to BEC and BEU. + - Optimized driver: + - 1. Integrated stc_mcan_classic_config_t and stc_mcan_fd_config_t into stc_mcan_bit_time_config_t + - 2. Integrated u32FdIso into u32FrameFormat. + - 3. Removed API MCAN_SetFdIsoOperation(), added API MCAN_SetFrameFormat(). + - 4. Optimized the handling of the parameter stc_mcan_filter_t.u32FilterIndex + - 5. Add 5 APIs for better get protocol status(register PSR): + - MCAN_GetTdcValue(), MCAN_GetDataLastErrorCode(), MCAN_GetLastErrorCode(), + - MCAN_GetComState(), MCAN_GetProtocolFlagStatus() + - 6. Changed u8Activity of stc_mcan_protocol_status_t to u8ComState. + - 7. Changed MCAN_Comm_State to MCAN_Com_State and optimized the macros definitions. + - 8. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex. Optimized MCAN_HPM_Storage macros definitions. + - 7. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex. + - 8. Optimized local function MCAN_FilterInitConfig() + - 9. When the frame to be transmitted is a remote frame, do not write the data field to the message RAM. + - When the received frame is a remote frame, do not read the data field from the message RAM. + - Optimized comments. + - **mpu** + - Add structure stc_mpu_unit_init_t, and declaration of MPU_UnitInit(), MPU_UnitStructInit() + - Refine def group MPU_Flag + - Optimize MPU_ClearStatus function + - Add API MPU_UnitInit(), MPU_UnitStructInit() + - **pwc** + - Modify group PWC_Stop_Type + - Add function PWC_LVD_DeInit + - Modify the PWC_LVD_Detection_Voltage_Sel comment + - Modify PWC_RAM_PD_CAN1 as PWC_RAM_PD_MCAN + - Refine API PWC_SLEEP_Enter() + - Remove redundant assert + - Modify API PWC_PD_Enter() #use assert to replace the unlock, and add return value + - Modify API PWC_WKT_SetCompareValue() + - Refine PWC_SLEEP_Enter() + - Add API PWC_PD_SetIoState() & PWC_PD_SetMode() + - **qspi** + - Optimize QSPI_ClearStatus function + - **spi** + - Rename SPI_FLAG_OVERLOAD as SPI_FLAG_OVERRUN, SPI_FLAG_UNDERLOAD as SPI_FLAG_UNDERRUN + - Modify some assert + - Rename some API SPI_xxxConfig as SPI_Setxxx + - Add Send restriction in SPI_TxRx function + - **sram** + - Modify typo + - Refine def group SRAM_ECC_Mode, and refine def group SRAM_Err_Mode as SRAM_Exception_Type + - Remove wait cycle relevant code + - API fixed: SRAM_ClearStatus() + - Refine SRAM_SetEccMode, and refine SRAM_SetErrorMode() as SRAM_SetExceptionType + - **swdt** + - Modify macro define: SWDT_LPM_CNT_CONTINUE -> SWDT_LPM_CNT_CONT + - Optimize SWDT_ClearStatus function timeout + - **tmr6** + - Modify macro define for group TMR6_Emb_Ch_Define + - Modify for headfile update: CM_TMR6CR -> CM_TMR6_COMMON + - Modify typo + - **usart** + - Remove u32StopBit param from stc_usart_smartcard_init_t structure + - Add the declaration of API USART_GetFuncState() + - Modify return type of function USART_DeInit() + - Modify USART_SmartCard_Init() for stc_usart_smartcard_init_t has modified(u32StopBit has removed) + - Fix bug: did not enable MP while USART_MultiProcessor_Init() + - API refined: USART_SetBaudrate() + - Add API USART_GetFuncState() + - **utility** + - Modify register USART DR to USART TDR + - Prohibit DDL_DelayMS and DDL_DelayUS functions from being optimized + - **wdt** + - Modify macro define: WDT_LPM_CNT_CONTINUE -> WDT_LPM_CNT_CONT + - Optimize WDT_ClearStatus function timeout +#### midwares +#### projects +- ##### ev_hc32f448_lqfp80/applications + - **functional_safety/iec60730_class_b** + - Initialize XTAL32 using BSP_XTAL32_Init + - **iap/iap_boot** + - Removed SRAM wait cycle relevant code + - **iap/iap_ymodem_boot** + - Removed SRAM wait cycle relevant code +- ##### ev_hc32f448_lqfp80/examples + - **adc/adc_awd** + - Set XTAL as system clock source + - **adc/adc_base** + - Set XTAL as system clock source + - **adc/adc_buffer_mode** + - Set XTAL as system clock source + - **adc/adc_channel_remap** + - Set XTAL as system clock source + - **adc/adc_dma** + - Set XTAL as system clock source + - **adc/adc_hard_trigger** + - Set XTAL as system clock source + - **adc/adc_internal_analog_channel** + - Set XTAL as system clock source + - **adc/adc_over_sample** + - Set XTAL as system clock source + - **adc/adc_sync_mode** + - Removed SRAM wait cycle relevant code + - **aes/aes_base** + - Set XTAL as system clock source + - **clk/clk_switch_sysclk** + - Modify XTAL32 initialize process + - Removed SRAM wait cycle relevant code + - **clk/clk_xtalstop_detect** + - Use CLK_XtalStdInit() to replace XtalStopDetctInit() + - Modify XTAL_STOP_IrqCallback + - **ctc/ctc_ctcref_single_trimming** + - Initialize XTAL32 using BSP_XTAL32_Init + - **ctc/ctc_xtal32_trimming** + - Initialize XTAL32 using BSP_XTAL32_Init + - **dmac/dmac_base** + - Optimize DMA2_Error_Handler() + - **dmac/dmac_non_sequence** + - Fixed bug #revert test code. + - **efm/efm_chip_erase** + - Fixed bug # release write protect before sector erase + - **efm/efm_dbus** + - Set API DBUS_Protect_test optimization level + - **efm/efm_sequence_program** + - Re-structure + - **efm/efm_swap** + - Use EFM_GetSwapStatus to judge + - **emb/emb_cmp_brake_timer4** + - Fix magic number + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - **emb/emb_cmp_brake_timer6** + - Fix magic number + - **emb/emb_lockup_brake_timer4** + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - Optimize comments: HardFault_Generate and HardFault_Handler + - **emb/emb_lockup_brake_timer6** + - Optimize comments: HardFault_Generate and HardFault_Handler + - **emb/emb_lvd_brake_timer4** + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - **emb/emb_osc_brake_timer4** + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - **emb/emb_port_brake_timer4** + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - **emb/emb_pwm_brake_timer4** + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - **emb/emb_sram_brake_timer4** + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - Optimize the 2nd data in SRAM_GenerateError() + - **emb/emb_sram_brake_timer6** + - Optimize the 2nd data in SRAM_GenerateError() + - **emb/emb_sw_brake_timer4** + - Modify TMR4_PwmConfig: enable main output following PWM initialization + - **event_port/ep_inout** + - Comment revise + - **exmc/exmc_smc_lcd_nt35510** + - Re-implement BSP_CLK_Init() + - **exmc/exmc_smc_sram_is61lv6416** + - Fix typos and modify file brief + - Fix memory address printf value + - Re-implement BSP_CLK_Init() + - **exmc/exmc_smc_sram_is61lv6416_dma** + - Add exmc_smc_sram_is61lv6416_dma example + - **hash/hash_base** + - Set XTAL as system clock source + - **i2c/i2c_master_dma** + - Add definition I2C_ADDR_MD as address condition select + - Configure DMA interrupt disable in I2C_DMA_Initialize() function + - **i2c/i2c_master_polling** + - Add definition I2C_ADDR_MD as address condition select + - **i2c/i2c_master_polling_fifo** + - Add definition I2C_ADDR_MD as address condition select + - **i2c/i2c_slave_dma** + - Remove redundant process for slave address commands + - Add definition I2C_ADDR_MD as address condition select + - Configure DMA interrupt disable in I2C_DMA_Initialize() function + - **i2c/i2c_slave_int** + - Remove redundant process for slave address commands + - Add definition I2C_ADDR_MD as address condition select + - **i2c/i2c_slave_polling** + - Add definition I2C_ADDR_MD as address condition select + - **i2c/i2c_slave_polling_fifo** + - Remove redundant process for slave address commands + - Add definition I2C_ADDR_MD as address condition select + - **icg/icg_wdt_interrupt_hw_startup** + - Add delay before WDT_GetStatus function + - **intc/intc_nmi_xtalstop** + - optimize function NMI_Xtal_Init + - **mcan/mcan_classical** + - Updates related to MCAN driver optimization. + - Peripheral SRAMC not used, removed related code. + - Code and comments optimized. + - **mcan/mcan_fd** + - Updates related to MCAN driver optimization. + - Peripheral SRAMC not used, removed related code. + - Code and comments optimized. + - **mcan/mcan_loopback** + - Optimized the example. + - **mpu/mpu_core_write_protect** + - Fixed parameters error of Core_MPU_Region_Size + - Modify trigger condition for RTC protection + - Optimize RTC init sequence + - **mpu/mpu_dma_write_protect** + - Remove key jitter + - **mpu/mpu_ip_read_protect** + - Optimize RTC init sequence + - **pwc/pwc_lpc** + - Disable HRC when enter sleep mode + - **pwc/pwc_stop_wake** + - Delete redundant code + - **qspi/qspi_base** + - Add read function of direct communication mode + - **rtc/rtc_alarm** + - Optimize RTC init sequence + - Replace XTAL32_ClkInit to BSP_XTAL32_Init + - **rtc/rtc_calendar** + - Optimize RTC init sequence + - **rtc/rtc_calibration_output** + - Optimize RTC init sequence + - Replace XTAL32_ClkInit to BSP_XTAL32_Init + - **rtc/rtc_low_power** + - Optimize RTC init sequence + - **sram/sram_error_check** + - sample code changed according to driver change + - **timer0/timer0_basetimer** + - Replace XTAL32_Config to BSP_XTAL32_Init + - **timer4/timer4_pwm_through** + - Modify the initial configuration to achieve 0% or 100% duty cycle + - **timer6/timer6_cmp_deadtime** + - Remove redundant code + - **timer6/timer6_cmp_sawtooth** + - Remove redundant code + - **timer6/timer6_cmp_sawtooth_dual_buf** + - Remove redundant code + - Modify compare register buffer initialization value + - **timer6/timer6_cmp_triangular_buf** + - Remove redundant code + - Modify compare register buffer initialization value + - **timer6/timer6_pwm_dynamic_dutycycle** + - Add timer6_pwm_dynamic_dutycycle example + - **timer6/timer6_valid_period** + - Modify compare register buffer initialization value + - **timera/timera_capture** + - Set XTAL as system clock source + - **timera/timera_compare_value_buffer** + - Set XTAL as system clock source + - **timera/timera_position_overflow_count** + - Set XTAL as system clock source + - **trng/trng_base** + - TRNG_Handler add __DSB for Arm Errata 838869 + - Add TRNG_Cmd function + - Set XTAL as system clock source + - **usart/usart_clocksync_dma** + - Fix bug: possible null pointer for ClockSync_DMAConfig parameter pstcHandle + - **usart/usart_smartcard_atr** + - Remove u32StopBit from stcSmartCardInit structure + - **usart/usart_uart_dma** + - Optimize function: USART_TxComplete_IrqCallback + - **usart/usart_uart_multiprocessor** + - Optimize the RX process + - **wdt/wdt_interrupt_sw_startup** + - Add delay before WDT_GetStatus function +#### utils +------ +## V1.0.0 May 31, 2023 +- Initial release. \ No newline at end of file diff --git a/bsp/hc32/libraries/hc32f448_ddl/LICENSE b/bsp/hc32/libraries/hc32f448_ddl/LICENSE new file mode 100644 index 0000000000..c19f1185ec --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2022-2023, Xiaohua Semiconductor Co., Ltd. ("XHSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32/libraries/hc32f448_ddl/SConscript b/bsp/hc32/libraries/hc32f448_ddl/SConscript new file mode 100644 index 0000000000..f5da405212 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/SConscript @@ -0,0 +1,97 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = Split(''' +drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f448.c +drivers/hc32_ll_driver/src/hc32_ll.c +drivers/hc32_ll_driver/src/hc32_ll_aos.c +drivers/hc32_ll_driver/src/hc32_ll_clk.c +drivers/hc32_ll_driver/src/hc32_ll_dma.c +drivers/hc32_ll_driver/src/hc32_ll_efm.c +drivers/hc32_ll_driver/src/hc32_ll_fcg.c +drivers/hc32_ll_driver/src/hc32_ll_fcm.c +drivers/hc32_ll_driver/src/hc32_ll_gpio.c +drivers/hc32_ll_driver/src/hc32_ll_icg.c +drivers/hc32_ll_driver/src/hc32_ll_interrupts.c +drivers/hc32_ll_driver/src/hc32_ll_pwc.c +drivers/hc32_ll_driver/src/hc32_ll_rmu.c +drivers/hc32_ll_driver/src/hc32_ll_sram.c +drivers/hc32_ll_driver/src/hc32_ll_utility.c +''') + +if GetDepend(['RT_USING_SERIAL']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_usart.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr0.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_spi.c'] + +if GetDepend(['RT_USING_QSPI']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_qspi.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_mcan.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_adc.c'] + +if GetDepend(['RT_USING_DAC']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_dac.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_rtc.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_swdt.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_wdt.c'] + +if GetDepend(['RT_USING_ON_CHIP_FLASH']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_efm.c'] + +if GetDepend(['RT_USING_HWTIMER']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr4.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr6.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c'] + +if GetDepend(['RT_USING_PULSE_ENCODER']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr6.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c'] + +if GetDepend(['RT_USING_PWM']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr4.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmr6.c'] + src += ['drivers/hc32_ll_driver/src/hc32_ll_tmra.c'] + +if GetDepend(['RT_HWCRYPTO_USING_RNG']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_trng.c'] + +if GetDepend(['RT_HWCRYPTO_USING_CRC']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_crc.c'] + +if GetDepend(['RT_HWCRYPTO_USING_AES']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_aes.c'] + +if GetDepend(['RT_HWCRYPTO_USING_SHA2']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_hash.c'] + +if GetDepend(['BSP_RTC_USING_XTAL32']) or GetDepend(['RT_USING_PM']): + src += ['drivers/hc32_ll_driver/src/hc32_ll_fcm.c'] + +path = [ + cwd + '/drivers/cmsis/Device/HDSC/hc32f4xx/Include', + cwd + '/drivers/cmsis/Include', + cwd + '/drivers/hc32_ll_driver/inc',] + +CPPDEFINES = ['USE_DDL_DRIVER'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448.mac b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448.mac new file mode 100644 index 0000000000..e30bd40aa2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448.mac @@ -0,0 +1,16 @@ +setup() +{ + ; +} + +execUserPreload() +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} +execUserFlashInit() // Called by debugger before loading flash loader in RAM. +{ + __message "----- Prepare hardware for Flashloader -----\n"; + setup(); +} + diff --git a/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448.out b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448.out new file mode 100644 index 0000000000000000000000000000000000000000..6f1a92a02b5ea2f300ef1a42e13ccc713118a4eb GIT binary patch literal 48368 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b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xA.board new file mode 100644 index 0000000000..17ca9a72d5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xA.board @@ -0,0 +1,16 @@ + + + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448xA.flash + CODE 0x0 0x1FFFF + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_otp.flash + CODE 0x03000C00 0x03000FFF + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_qspi.flash + CODE 0x98000000 0x987FFFFF + + diff --git a/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xA.flash b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xA.flash new file mode 100644 index 0000000000..613f653918 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xA.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.out + 4 + 16 0x2000 + 0x00000000 + $PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.mac + 0 + diff --git a/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.board b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.board new file mode 100644 index 0000000000..6f837fe0f8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.board @@ -0,0 +1,16 @@ + + + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448xC.flash + CODE 0x0 0x3FFFF + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_otp.flash + CODE 0x03000C00 0x03000FFF + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\config\flashloader\FlashHC32F448_qspi.flash + CODE 0x98000000 0x987FFFFF + + diff --git a/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.flash b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.flash new file mode 100644 index 0000000000..34237d795d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/config/flashloader/FlashHC32F448xC.flash @@ -0,0 +1,10 @@ + + + + $PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.out + 4 + 32 0x2000 + 0x00000000 + $PROJ_DIR$\..\libraries\hc32f448_ddl\drivers\cmsis\Device\HDSC\hc32f4xx\Source\IAR\flashloader\FlashHC32F448.mac + 0 + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.c new file mode 100644 index 0000000000..50548d35d4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.c @@ -0,0 +1,278 @@ +/** + ******************************************************************************* + * @file 24cxx.c + * @brief This midware file provides firmware functions to 24cxx EEPROM. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-12-15 CDT Add null pointer check + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "24cxx.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @defgroup 24CXX EEPROM Driver for 24CXX + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup 24CXX_Local_Macros 24CXX Local Macros + * @{ + */ +#define EE_24CXX_WAIT_TIMEOUT (0x20000UL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup 24CXX_Local_Types 24CXX Local Types + * @{ + */ +static uint32_t u32PageSize; +static uint32_t u32Capacity; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup 24CXX_Global_Functions 24CXX Global Functions + * @{ + */ + +/** + * @brief Initializes I2C for 24CXX. + * @param [in] pstc24cxxLL Pointer to a @ref stc_24cxx_ll_t structure. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t EE_24CXX_Init(const stc_24cxx_ll_t *pstc24cxxLL) +{ + int32_t i32Ret; + if ((pstc24cxxLL == NULL) || (pstc24cxxLL->u32PageSize == 0U) || (pstc24cxxLL->u32Capacity == 0U) || + (pstc24cxxLL->Init == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u32PageSize = pstc24cxxLL->u32PageSize; + u32Capacity = pstc24cxxLL->u32Capacity; + i32Ret = pstc24cxxLL->Init(); + } + return i32Ret; +} + +/** + * @brief De-Initializes I2C for 24CXX. + * @param [in] pstc24cxxLL Pointer to a @ref stc_24cxx_ll_t structure. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t EE_24CXX_DeInit(const stc_24cxx_ll_t *pstc24cxxLL) +{ + int32_t i32Ret = LL_OK; + if ((pstc24cxxLL == NULL) || (pstc24cxxLL->DeInit == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstc24cxxLL->DeInit(); + } + return i32Ret; +} + +/** + * @brief 24CXX read data. + * @param [in] pstc24cxxLL Pointer to a @ref stc_24cxx_ll_t structure. + * @param [in] u16Addr: The start address of the data to be read. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be stored. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t EE_24CXX_Read(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret; + + if (((u16Addr + u32Len) > u32Capacity) || (pstc24cxxLL == NULL) || (pstc24cxxLL->Read == NULL) || + (pu8Buf == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + i32Ret = pstc24cxxLL->Read(u16Addr, pu8Buf, u32Len); + } + return i32Ret; +} + +/** + * @brief 24CXX write data. + * @param [in] pstc24cxxLL Pointer to a @ref stc_24cxx_ll_t structure. + * @param [in] u16Addr: The start address of the data to be write. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be write. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t EE_24CXX_Write(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len) +{ + uint32_t u32PageNum; + uint8_t u8SingleNumStart; + uint8_t u8SingleNumEnd; + uint32_t u32NumRemainTemp = u32Len; + uint32_t u32WriteOffset = 0UL; + uint16_t u16WriteAddrTemp = u16Addr; + int32_t i32Ret = LL_OK; + uint32_t i; + + if (((u16Addr + u32Len) > u32Capacity) || (u32PageSize == 0U) || (pstc24cxxLL == NULL) || + (pstc24cxxLL->WritePage == NULL) || (pstc24cxxLL->Delay == NULL) || (pu8Buf == NULL)) { + return LL_ERR_INVD_PARAM; + } + + /* If start write address is align with page size */ + if (0U == (u16WriteAddrTemp % u32PageSize)) { + /* If Write number is less than page size */ + if (u32Len < u32PageSize) { + u8SingleNumStart = (uint8_t)u32Len; + } else { + /* If Write number is more than page size */ + u8SingleNumStart = 0U; + } + u32NumRemainTemp -= (uint32_t)u8SingleNumStart; + } else { + /* If start write address is not align with page size */ + u8SingleNumStart = (uint8_t)(u32PageSize - (u16WriteAddrTemp % u32PageSize)); + if ((uint32_t)u8SingleNumStart > u32Len) { + u8SingleNumStart = (uint8_t)u32Len; + } + u32NumRemainTemp -= (uint32_t)u8SingleNumStart; + } + + u32PageNum = u32NumRemainTemp / u32PageSize; + u8SingleNumEnd = (uint8_t)(u32NumRemainTemp % u32PageSize); + + if (0UL != u8SingleNumStart) { + i32Ret = pstc24cxxLL->WritePage(u16WriteAddrTemp, &pu8Buf[u32WriteOffset], (uint32_t)u8SingleNumStart); + /* Delay about 5ms for EEPROM */ + pstc24cxxLL->Delay(5000U); + u16WriteAddrTemp += u8SingleNumStart; + u32WriteOffset += (uint32_t)u8SingleNumStart; + } + + if (LL_OK == i32Ret) { + if (0UL != u32PageNum) { + for (i = 0UL; i < u32PageNum; i++) { + i32Ret = pstc24cxxLL->WritePage(u16WriteAddrTemp, &pu8Buf[u32WriteOffset], u32PageSize); + /* Delay about 5ms for EEPROM */ + pstc24cxxLL->Delay(5000U); + u16WriteAddrTemp += (uint16_t)u32PageSize; + u32WriteOffset += u32PageSize; + if (LL_OK != i32Ret) { + break; + } + } + } + + if (LL_OK == i32Ret) { + if (0UL != u8SingleNumEnd) { + i32Ret = pstc24cxxLL->WritePage(u16WriteAddrTemp, &pu8Buf[u32WriteOffset], (uint32_t)u8SingleNumEnd); + /* Delay about 5ms for EEPROM */ + pstc24cxxLL->Delay(5000U); + } + } + } + return i32Ret; +} + +/** + * @brief 24CXX wait idle. + * @param [in] pstc24cxxLL Pointer to a @ref stc_24cxx_ll_t structure. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t EE_24CXX_WaitIdle(const stc_24cxx_ll_t *pstc24cxxLL) +{ + int32_t i32Ret = LL_OK; + volatile uint32_t u32Tmp = 0UL; + + if ((pstc24cxxLL == NULL) || (pstc24cxxLL->GetStatus == NULL)) { + return LL_ERR_INVD_PARAM; + } + while (LL_OK != pstc24cxxLL->GetStatus()) { + if (EE_24CXX_WAIT_TIMEOUT == u32Tmp++) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.h new file mode 100644 index 0000000000..261444d593 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/24cxx/24cxx.h @@ -0,0 +1,121 @@ +/** + ******************************************************************************* + * @file 24cxx.h + * @brief This file provides firmware functions to 24CXX EEPROM. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __24CXX_H__ +#define __24CXX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @addtogroup 24CXX + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup 24CXX_Global_Types 24CXX Global Types + * @{ + */ + +/** + * @brief 24CXX low layer structure definition + */ +typedef struct { + /* Properties */ + uint32_t u32PageSize; + uint32_t u32Capacity; + /* Methods */ + void (*Delay)(uint32_t); + int32_t (*Init)(void); + void (*DeInit)(void); + int32_t (*WritePage)(uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len); + int32_t (*Read)(uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len); + int32_t (*GetStatus)(void); +} stc_24cxx_ll_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup 24CXX_Global_Functions 24CXX Global Functions + * @{ + */ +int32_t EE_24CXX_Init(const stc_24cxx_ll_t *pstc24cxxLL); +int32_t EE_24CXX_DeInit(const stc_24cxx_ll_t *pstc24cxxLL); +int32_t EE_24CXX_Read(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EE_24CXX_Write(const stc_24cxx_ll_t *pstc24cxxLL, uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len); +int32_t EE_24CXX_WaitIdle(const stc_24cxx_ll_t *pstc24cxxLL); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __24CXX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.c new file mode 100644 index 0000000000..0683a8e3e1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.c @@ -0,0 +1,183 @@ +/** + ******************************************************************************* + * @file gt9xx.c + * @brief This file provides firmware functions for Touch Pad GT9XX. + @verbatim + Change Logs: + Date Author Notes + 2022-12-31 CDT First version + 2023-12-15 CDT Add null pointer check + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "gt9xx.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @defgroup GT9XX Touch Pad GT9XX + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup GT9XX_Global_Functions GT9XX Global Functions + * @{ + */ + +/** + * @brief Read register on touch pad register. + * @param [in] pstcGt9xxLL Pointer to a @ref stc_gt9xx_ll_t structure + * @param [in] u16Reg Register to be read + * @param [out] pu8RegValue The buffer for reading + * @param [in] u32Len The buffer size for bytes + * @retval None + */ +void GT9XX_REG_Read(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, uint8_t *pu8RegValue, uint32_t u32Len) +{ + uint8_t au8RegAddr[2]; + + if ((NULL != pstcGt9xxLL) && (NULL != pstcGt9xxLL->Read) && (NULL != pu8RegValue)) { + au8RegAddr[0] = (uint8_t)((u16Reg & 0xFF00U) >> 8); + au8RegAddr[1] = (uint8_t)(u16Reg & 0x00FFU); + (void)pstcGt9xxLL->Read(au8RegAddr, ARRAY_SZ(au8RegAddr), pu8RegValue, u32Len); + } +} + +/** + * @brief Write register on touch pad register. + * @param [in] pstcGt9xxLL Pointer to a @ref stc_gt9xx_ll_t structure + * @param [in] u16Reg Register to be write + * @param [in] pu8RegValue The buffer for writing + * @param [in] u32Len The buffer size for bytes + * @retval None + */ +void GT9XX_REG_Write(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, const uint8_t *pu8RegValue, uint32_t u32Len) +{ + uint8_t au8RegAddr[2]; + + if ((NULL != pstcGt9xxLL) && (NULL != pstcGt9xxLL->Write) && (NULL != pu8RegValue)) { + au8RegAddr[0] = (uint8_t)((u16Reg & 0xFF00U) >> 8); + au8RegAddr[1] = (uint8_t)(u16Reg & 0x00FFU); + (void)pstcGt9xxLL->Write(au8RegAddr, ARRAY_SZ(au8RegAddr), pu8RegValue, u32Len); + } +} + +/** + * @brief Reset GT9XX. + * @param [in] pstcGt9xxLL Pointer to a @ref stc_gt9xx_ll_t structure. + * @retval None + */ +void GT9XX_SoftReset(const stc_gt9xx_ll_t *pstcGt9xxLL) +{ + uint8_t u8RegValue = 0x02U; + + GT9XX_REG_Write(pstcGt9xxLL, GT9XX_COMMAND, &u8RegValue, 1UL); +} + +/** + * @brief Read GT9XX touch status. + * @param [in] pstcGt9xxLL Pointer to a @ref stc_gt9xx_ll_t structure. + * @retval Touch status + */ +uint8_t GT9XX_ReadTouchStatus(const stc_gt9xx_ll_t *pstcGt9xxLL) +{ + uint8_t u8Status = 0U; + + GT9XX_REG_Read(pstcGt9xxLL, GT9XX_TOUCH_STATUS, &u8Status, 1UL); + return u8Status; +} + +/** + * @brief Read GT9XX ID. + * @param [in] pstcGt9xxLL Pointer to a @ref stc_gt9xx_ll_t structure. + * @param [out] pu8IDValue The buffer for reading ID + * @param [in] u32Len The buffer size for bytes + * @retval None + */ +void GT9XX_ReadProductID(const stc_gt9xx_ll_t *pstcGt9xxLL, uint8_t *pu8IDValue, uint32_t u32Len) +{ + GT9XX_REG_Read(pstcGt9xxLL, GT9XX_PRODUCT_ID, pu8IDValue, u32Len); +} + +/** + * @brief Read GT9XX point. + * @param [in] pstcGt9xxLL Pointer to a @ref stc_gt9xx_ll_t structure. + * @param [in] u16Point Touch pad point + * @param [out] pu16X Point x coordinate + * @param [out] pu16Y Point y coordinate + * @retval None + */ +void GT9XX_GetXY(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Point, uint16_t *pu16X, uint16_t *pu16Y) +{ + uint8_t au8Tmp[4]; + + if ((pu16X != NULL) && (pu16Y != NULL)) { + GT9XX_REG_Read(pstcGt9xxLL, u16Point, au8Tmp, 4UL); + (*pu16X) = (uint16_t)au8Tmp[0] | ((uint16_t)au8Tmp[1] << 8); + (*pu16Y) = (uint16_t)au8Tmp[2] | ((uint16_t)au8Tmp[3] << 8); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.h new file mode 100644 index 0000000000..83a4792ad4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/gt9xx/gt9xx.h @@ -0,0 +1,150 @@ +/** + ******************************************************************************* + * @file gt9XX.h + * @brief This file contains all the functions prototypes of the touch pad GT9XX + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-12-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __GT9XX_H__ +#define __GT9XX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @addtogroup GT9XX + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GT9XX_Global_Types GT9XX Global Types + * @{ + */ + +/** + * @brief GT9XX low layer structure definition + */ +typedef struct { + /* Methods */ + void (*Init)(void); + void (*Read)(const uint8_t *pu8Reg, uint8_t u8RegLen, uint8_t *pu8Buf, uint32_t u32Len); + void (*Write)(const uint8_t *pu8Reg, uint8_t u8RegLen, const uint8_t *pu8Buf, uint32_t u32Len); +} stc_gt9xx_ll_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GT9XX_Global_Macros GT9XX Global Macros + * @{ + */ +/** + * @defgroup GT9XX_Local_Macros GT9XX Local Macros + * @{ + */ +#define GT9XX_COMMAND (0x8040U) +#define GT9XX_CONFIG (0x8047U) + +#define GT9XX_CHECK_SUM (0X80FF) + +#define GT9XX_PRODUCT_ID (0x8140U) +#define GT9XX_TOUCH_STATUS (0x814EU) + +#define GT9XX_POINT1 (0x8150U) +#define GT9XX_POINT2 (0x8158U) +#define GT9XX_POINT3 (0X8160U) +#define GT9XX_POINT4 (0X8168U) +#define GT9XX_POINT5 (0X8170U) +#define GT9XX_POINT6 (0X8178U) +#define GT9XX_POINT7 (0X8180U) +#define GT9XX_POINT8 (0X8188U) +#define GT9XX_POINT9 (0X8190U) +#define GT9XX_POINT10 (0X8198U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup GT9XX_Global_Functions + * @{ + */ +void GT9XX_REG_Read(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, uint8_t *pu8RegValue, uint32_t u32Len); +void GT9XX_REG_Write(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Reg, const uint8_t *pu8RegValue, uint32_t u32Len); +void GT9XX_SoftReset(const stc_gt9xx_ll_t *pstcGt9xxLL); +uint8_t GT9XX_ReadTouchStatus(const stc_gt9xx_ll_t *pstcGt9xxLL); +void GT9XX_ReadProductID(const stc_gt9xx_ll_t *pstcGt9xxLL, uint8_t *pu8IDValue, uint32_t u32Len); +void GT9XX_GetXY(const stc_gt9xx_ll_t *pstcGt9xxLL, uint16_t u16Point, uint16_t *pu16X, uint16_t *pu16Y); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GT9XX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/nt35510/nt35510.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/nt35510/nt35510.c new file mode 100644 index 0000000000..d560a91b4f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/nt35510/nt35510.c @@ -0,0 +1,2078 @@ +/** + ******************************************************************************* + * @file nt35510.c + * @brief This file provides firmware functions for LCD NT35510. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-12-31 CDT Compliant LCD drive IC: NT35310 + 2023-12-15 CDT Add null pointer check + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "nt35510.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @defgroup NT35510 LCD NT35510 + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup NT35510_Local_Types NT35510 Local Types + * @{ + */ + +/** + * @brief LCD Device Structure Definition + */ +typedef struct { + uint16_t u16Dir; /*!< Direction: 0, Vertical; 1, Horizontal */ + uint16_t u16ID; /*!< LCD ID */ + uint16_t u16Width; /*!< LCD Width */ + uint16_t u16Height; /*!< LCD Heigth */ + uint16_t u16WRamCmd; /*!< Start to write GRAM */ + uint16_t u16SetXCmd; /*!< Set X axis */ + uint16_t u16SetYCmd; /*!< Set Y axis */ +} stc_lcd_device_t; + +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup NT35510_Local_Macros NT35510 Local Macros + * @{ + */ + +/* LCD Scan Direction */ +#define LCD_SCAN_DIR (LCD_SCAN_DIR_L2R_U2D) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/** + * @defgroup NT35510_Local_Variables NT35510 Local Variables + * @{ + */ +static stc_lcd_device_t m_stcLcdDevice; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup NT35510_Local_Functions NT35510 Local Functions + * @{ + */ + +/** + * @brief LCD delay + * @param [in] u32Delay: Delay in ms + * @retval None + */ +static void LCD_Delay(uint32_t u32Delay) +{ + volatile uint32_t i; + const uint32_t u32Cyc = 24000UL; + + while (u32Delay-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + ; + } + } +} + +/** + * @brief Configure LCD NT35310 + * @param [in] pstcLCD: LCD controller + * @retval None + */ +static void LCD_NT35310_Config(stc_lcd_controller_t *pstcLCD) +{ + NT35510_WriteReg(pstcLCD, 0xED); + NT35510_WriteData(pstcLCD, 0x01); + NT35510_WriteData(pstcLCD, 0xFE); + + NT35510_WriteReg(pstcLCD, 0xEE); + NT35510_WriteData(pstcLCD, 0xDE); + NT35510_WriteData(pstcLCD, 0x21); + + NT35510_WriteReg(pstcLCD, 0xF1); + NT35510_WriteData(pstcLCD, 0x01); + NT35510_WriteReg(pstcLCD, 0xDF); + NT35510_WriteData(pstcLCD, 0x10); + + //VCOMvoltage// + NT35510_WriteReg(pstcLCD, 0xC4); + NT35510_WriteData(pstcLCD, 0x8F); + + NT35510_WriteReg(pstcLCD, 0xC6); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xE2); + NT35510_WriteData(pstcLCD, 0xE2); + NT35510_WriteData(pstcLCD, 0xE2); + NT35510_WriteReg(pstcLCD, 0xBF); + NT35510_WriteData(pstcLCD, 0xAA); + + NT35510_WriteReg(pstcLCD, 0xB0); + NT35510_WriteData(pstcLCD, 0x0D); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x0D); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x11); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x19); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x21); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x2D); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x3D); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x5D); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x5D); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB1); + NT35510_WriteData(pstcLCD, 0x80); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x8B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x96); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB2); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x02); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x03); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB4); + NT35510_WriteData(pstcLCD, 0x8B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x96); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA1); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB5); + NT35510_WriteData(pstcLCD, 0x02); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x03); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x04); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB6); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB7); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x3F); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x5E); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x64); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x8C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xAC); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xDC); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x70); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x90); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xEB); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xDC); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xB8); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xBA); + NT35510_WriteData(pstcLCD, 0x24); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC1); + NT35510_WriteData(pstcLCD, 0x20); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x54); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xFF); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC2); + NT35510_WriteData(pstcLCD, 0x0A); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x04); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC3); + NT35510_WriteData(pstcLCD, 0x3C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x3A); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x39); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x37); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x3C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x36); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x32); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x2F); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x2C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x29); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x26); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x24); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x24); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x23); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x3C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x36); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x32); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x2F); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x2C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x29); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x26); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x24); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x24); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x23); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC4); + NT35510_WriteData(pstcLCD, 0x62); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x05); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x84); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF0); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x18); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA4); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x18); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x50); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x0C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x17); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x95); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xE6); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC5); + NT35510_WriteData(pstcLCD, 0x32); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x44); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x65); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x76); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x88); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC6); + NT35510_WriteData(pstcLCD, 0x20); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x17); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x01); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC7); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC8); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xC9); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE0); + NT35510_WriteData(pstcLCD, 0x16); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x1C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x21); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x36); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x46); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x52); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x64); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x7A); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x8B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA8); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xB9); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC4); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xCA); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD2); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD9); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xE0); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE1); + NT35510_WriteData(pstcLCD, 0x16); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x1C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x22); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x36); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x45); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x52); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x64); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x7A); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x8B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA8); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xB9); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC4); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xCA); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD2); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD8); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xE0); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE2); + NT35510_WriteData(pstcLCD, 0x05); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x0B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x1B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x34); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x44); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x4F); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x61); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x79); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x88); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x97); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA6); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xB7); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC2); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC7); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD1); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD6); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xDD); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteReg(pstcLCD, 0xE3); + NT35510_WriteData(pstcLCD, 0x05); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x1C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x33); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x44); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x50); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x62); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x78); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x88); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x97); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA6); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xB7); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC2); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC7); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD1); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD5); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xDD); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE4); + NT35510_WriteData(pstcLCD, 0x01); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x01); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x02); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x2A); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x3C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x4B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x5D); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x74); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x84); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x93); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA2); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xB3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xBE); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC4); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xCD); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xDD); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteReg(pstcLCD, 0xE5); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x02); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x29); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x3C); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x4B); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x5D); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x74); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x84); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x93); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xA2); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xB3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xBE); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xC4); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xCD); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xD3); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xDC); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE6); + NT35510_WriteData(pstcLCD, 0x11); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x34); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x56); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x76); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x77); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x66); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x88); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xBB); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x66); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x55); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x55); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x45); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x43); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x44); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE7); + NT35510_WriteData(pstcLCD, 0x32); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x55); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x76); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x66); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x67); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x67); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x87); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xBB); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x77); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x44); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x56); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x23); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x33); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x45); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE8); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x87); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x88); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x77); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x66); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x88); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xAA); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xBB); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x99); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x66); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x55); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x55); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x44); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x44); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x55); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xE9); + NT35510_WriteData(pstcLCD, 0xAA); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0xAA); + + NT35510_WriteReg(pstcLCD, 0xCF); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xF0); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x50); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xF3); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0xF9); + NT35510_WriteData(pstcLCD, 0x06); + NT35510_WriteData(pstcLCD, 0x10); + NT35510_WriteData(pstcLCD, 0x29); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0x3A); + NT35510_WriteData(pstcLCD, 0x55); + + NT35510_WriteReg(pstcLCD, 0x11); + LCD_Delay(100); + NT35510_WriteReg(pstcLCD, 0x29); + NT35510_WriteReg(pstcLCD, 0x35); + NT35510_WriteData(pstcLCD, 0x00); + + NT35510_WriteReg(pstcLCD, 0x51); + NT35510_WriteData(pstcLCD, 0xFF); + NT35510_WriteReg(pstcLCD, 0x53); + NT35510_WriteData(pstcLCD, 0x2C); + NT35510_WriteReg(pstcLCD, 0x55); + NT35510_WriteData(pstcLCD, 0x82); + NT35510_WriteReg(pstcLCD, 0x2c); +} + +/** + * @brief Configure LCD NT35510 + * @param [in] pstcLCD: LCD controller + * @retval None + */ +static void LCD_NT35510_Config(stc_lcd_controller_t *pstcLCD) +{ + /* Config LCD */ + NT35510_WriteRegData(pstcLCD, 0xF000U, 0x55U); + NT35510_WriteRegData(pstcLCD, 0xF001U, 0xAAU); + NT35510_WriteRegData(pstcLCD, 0xF002U, 0x52U); + NT35510_WriteRegData(pstcLCD, 0xF003U, 0x08U); + NT35510_WriteRegData(pstcLCD, 0xF004U, 0x01U); + /* AVDD Set AVDD 5.2V */ + NT35510_WriteRegData(pstcLCD, 0xB000U, 0x0DU); + NT35510_WriteRegData(pstcLCD, 0xB001U, 0x0DU); + NT35510_WriteRegData(pstcLCD, 0xB002U, 0x0DU); + /* AVDD ratio */ + NT35510_WriteRegData(pstcLCD, 0xB600U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xB601U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xB602U, 0x34U); + /* AVEE -5.2V */ + NT35510_WriteRegData(pstcLCD, 0xB100U, 0x0DU); + NT35510_WriteRegData(pstcLCD, 0xB101U, 0x0DU); + NT35510_WriteRegData(pstcLCD, 0xB102U, 0x0DU); + /* AVEE ratio */ + NT35510_WriteRegData(pstcLCD, 0xB700U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xB701U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xB702U, 0x34U); + /* VCL -2.5V */ + NT35510_WriteRegData(pstcLCD, 0xB200U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xB201U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xB202U, 0x00U); + /* VCL ratio */ + NT35510_WriteRegData(pstcLCD, 0xB800U, 0x24U); + NT35510_WriteRegData(pstcLCD, 0xB801U, 0x24U); + NT35510_WriteRegData(pstcLCD, 0xB802U, 0x24U); + /* VGH 15V (Free pump) */ + NT35510_WriteRegData(pstcLCD, 0xBF00U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xB300U, 0x0FU); + NT35510_WriteRegData(pstcLCD, 0xB301U, 0x0FU); + NT35510_WriteRegData(pstcLCD, 0xB302U, 0x0FU); + /* VGH ratio */ + NT35510_WriteRegData(pstcLCD, 0xB900U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xB901U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xB902U, 0x34U); + /* VGL_REG -10V */ + NT35510_WriteRegData(pstcLCD, 0xB500U, 0x08U); + NT35510_WriteRegData(pstcLCD, 0xB501U, 0x08U); + NT35510_WriteRegData(pstcLCD, 0xB502U, 0x08U); + NT35510_WriteRegData(pstcLCD, 0xC200U, 0x03U); + /* VGLX ratio */ + NT35510_WriteRegData(pstcLCD, 0xBA00U, 0x24U); + NT35510_WriteRegData(pstcLCD, 0xBA01U, 0x24U); + NT35510_WriteRegData(pstcLCD, 0xBA02U, 0x24U); + /* VGMP/VGSP 4.5V/0V */ + NT35510_WriteRegData(pstcLCD, 0xBC00U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xBC01U, 0x78U); + NT35510_WriteRegData(pstcLCD, 0xBC02U, 0x00U); + /* VGMN/VGSN -4.5V/0V */ + NT35510_WriteRegData(pstcLCD, 0xBD00U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xBD01U, 0x78U); + NT35510_WriteRegData(pstcLCD, 0xBD02U, 0x00U); + /* VCOM */ + NT35510_WriteRegData(pstcLCD, 0xBE00U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xBE01U, 0x64U); + /* Gamma Setting */ + NT35510_WriteRegData(pstcLCD, 0xD100U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD101U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD102U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD103U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD104U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD105U, 0x3AU); + NT35510_WriteRegData(pstcLCD, 0xD106U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD107U, 0x4AU); + NT35510_WriteRegData(pstcLCD, 0xD108U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD109U, 0x5CU); + NT35510_WriteRegData(pstcLCD, 0xD10AU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD10BU, 0x81U); + NT35510_WriteRegData(pstcLCD, 0xD10CU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD10DU, 0xA6U); + NT35510_WriteRegData(pstcLCD, 0xD10EU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD10FU, 0xE5U); + NT35510_WriteRegData(pstcLCD, 0xD110U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD111U, 0x13U); + NT35510_WriteRegData(pstcLCD, 0xD112U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD113U, 0x54U); + NT35510_WriteRegData(pstcLCD, 0xD114U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD115U, 0x82U); + NT35510_WriteRegData(pstcLCD, 0xD116U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD117U, 0xCAU); + NT35510_WriteRegData(pstcLCD, 0xD118U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD119U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD11AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD11BU, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD11CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD11DU, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD11EU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD11FU, 0x67U); + NT35510_WriteRegData(pstcLCD, 0xD120U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD121U, 0x84U); + NT35510_WriteRegData(pstcLCD, 0xD122U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD123U, 0xA4U); + NT35510_WriteRegData(pstcLCD, 0xD124U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD125U, 0xB7U); + NT35510_WriteRegData(pstcLCD, 0xD126U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD127U, 0xCFU); + NT35510_WriteRegData(pstcLCD, 0xD128U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD129U, 0xDEU); + NT35510_WriteRegData(pstcLCD, 0xD12AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD12BU, 0xF2U); + NT35510_WriteRegData(pstcLCD, 0xD12CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD12DU, 0xFEU); + NT35510_WriteRegData(pstcLCD, 0xD12EU, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD12FU, 0x10U); + NT35510_WriteRegData(pstcLCD, 0xD130U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD131U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD132U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD133U, 0x6DU); + NT35510_WriteRegData(pstcLCD, 0xD200U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD201U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD202U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD203U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD204U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD205U, 0x3AU); + NT35510_WriteRegData(pstcLCD, 0xD206U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD207U, 0x4AU); + NT35510_WriteRegData(pstcLCD, 0xD208U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD209U, 0x5CU); + NT35510_WriteRegData(pstcLCD, 0xD20AU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD20BU, 0x81U); + NT35510_WriteRegData(pstcLCD, 0xD20CU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD20DU, 0xA6U); + NT35510_WriteRegData(pstcLCD, 0xD20EU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD20FU, 0xE5U); + NT35510_WriteRegData(pstcLCD, 0xD210U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD211U, 0x13U); + NT35510_WriteRegData(pstcLCD, 0xD212U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD213U, 0x54U); + NT35510_WriteRegData(pstcLCD, 0xD214U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD215U, 0x82U); + NT35510_WriteRegData(pstcLCD, 0xD216U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD217U, 0xCAU); + NT35510_WriteRegData(pstcLCD, 0xD218U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD219U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD21AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD21BU, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD21CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD21DU, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD21EU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD21FU, 0x67U); + NT35510_WriteRegData(pstcLCD, 0xD220U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD221U, 0x84U); + NT35510_WriteRegData(pstcLCD, 0xD222U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD223U, 0xA4U); + NT35510_WriteRegData(pstcLCD, 0xD224U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD225U, 0xB7U); + NT35510_WriteRegData(pstcLCD, 0xD226U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD227U, 0xCFU); + NT35510_WriteRegData(pstcLCD, 0xD228U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD229U, 0xDEU); + NT35510_WriteRegData(pstcLCD, 0xD22AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD22BU, 0xF2U); + NT35510_WriteRegData(pstcLCD, 0xD22CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD22DU, 0xFEU); + NT35510_WriteRegData(pstcLCD, 0xD22EU, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD22FU, 0x10U); + NT35510_WriteRegData(pstcLCD, 0xD230U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD231U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD232U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD233U, 0x6DU); + NT35510_WriteRegData(pstcLCD, 0xD300U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD301U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD302U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD303U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD304U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD305U, 0x3AU); + NT35510_WriteRegData(pstcLCD, 0xD306U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD307U, 0x4AU); + NT35510_WriteRegData(pstcLCD, 0xD308U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD309U, 0x5CU); + NT35510_WriteRegData(pstcLCD, 0xD30AU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD30BU, 0x81U); + NT35510_WriteRegData(pstcLCD, 0xD30CU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD30DU, 0xA6U); + NT35510_WriteRegData(pstcLCD, 0xD30EU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD30FU, 0xE5U); + NT35510_WriteRegData(pstcLCD, 0xD310U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD311U, 0x13U); + NT35510_WriteRegData(pstcLCD, 0xD312U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD313U, 0x54U); + NT35510_WriteRegData(pstcLCD, 0xD314U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD315U, 0x82U); + NT35510_WriteRegData(pstcLCD, 0xD316U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD317U, 0xCAU); + NT35510_WriteRegData(pstcLCD, 0xD318U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD319U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD31AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD31BU, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD31CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD31DU, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD31EU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD31FU, 0x67U); + NT35510_WriteRegData(pstcLCD, 0xD320U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD321U, 0x84U); + NT35510_WriteRegData(pstcLCD, 0xD322U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD323U, 0xA4U); + NT35510_WriteRegData(pstcLCD, 0xD324U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD325U, 0xB7U); + NT35510_WriteRegData(pstcLCD, 0xD326U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD327U, 0xCFU); + NT35510_WriteRegData(pstcLCD, 0xD328U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD329U, 0xDEU); + NT35510_WriteRegData(pstcLCD, 0xD32AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD32BU, 0xF2U); + NT35510_WriteRegData(pstcLCD, 0xD32CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD32DU, 0xFEU); + NT35510_WriteRegData(pstcLCD, 0xD32EU, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD32FU, 0x10U); + NT35510_WriteRegData(pstcLCD, 0xD330U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD331U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD332U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD333U, 0x6DU); + NT35510_WriteRegData(pstcLCD, 0xD400U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD401U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD402U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD403U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD404U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD405U, 0x3AU); + NT35510_WriteRegData(pstcLCD, 0xD406U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD407U, 0x4AU); + NT35510_WriteRegData(pstcLCD, 0xD408U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD409U, 0x5CU); + NT35510_WriteRegData(pstcLCD, 0xD40AU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD40BU, 0x81U); + NT35510_WriteRegData(pstcLCD, 0xD40CU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD40DU, 0xA6U); + NT35510_WriteRegData(pstcLCD, 0xD40EU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD40FU, 0xE5U); + NT35510_WriteRegData(pstcLCD, 0xD410U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD411U, 0x13U); + NT35510_WriteRegData(pstcLCD, 0xD412U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD413U, 0x54U); + NT35510_WriteRegData(pstcLCD, 0xD414U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD415U, 0x82U); + NT35510_WriteRegData(pstcLCD, 0xD416U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD417U, 0xCAU); + NT35510_WriteRegData(pstcLCD, 0xD418U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD419U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD41AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD41BU, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD41CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD41DU, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD41EU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD41FU, 0x67U); + NT35510_WriteRegData(pstcLCD, 0xD420U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD421U, 0x84U); + NT35510_WriteRegData(pstcLCD, 0xD422U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD423U, 0xA4U); + NT35510_WriteRegData(pstcLCD, 0xD424U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD425U, 0xB7U); + NT35510_WriteRegData(pstcLCD, 0xD426U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD427U, 0xCFU); + NT35510_WriteRegData(pstcLCD, 0xD428U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD429U, 0xDEU); + NT35510_WriteRegData(pstcLCD, 0xD42AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD42BU, 0xF2U); + NT35510_WriteRegData(pstcLCD, 0xD42CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD42DU, 0xFEU); + NT35510_WriteRegData(pstcLCD, 0xD42EU, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD42FU, 0x10U); + NT35510_WriteRegData(pstcLCD, 0xD430U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD431U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD432U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD433U, 0x6DU); + NT35510_WriteRegData(pstcLCD, 0xD500U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD501U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD502U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD503U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD504U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD505U, 0x3AU); + NT35510_WriteRegData(pstcLCD, 0xD506U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD507U, 0x4AU); + NT35510_WriteRegData(pstcLCD, 0xD508U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD509U, 0x5CU); + NT35510_WriteRegData(pstcLCD, 0xD50AU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD50BU, 0x81U); + NT35510_WriteRegData(pstcLCD, 0xD50CU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD50DU, 0xA6U); + NT35510_WriteRegData(pstcLCD, 0xD50EU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD50FU, 0xE5U); + NT35510_WriteRegData(pstcLCD, 0xD510U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD511U, 0x13U); + NT35510_WriteRegData(pstcLCD, 0xD512U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD513U, 0x54U); + NT35510_WriteRegData(pstcLCD, 0xD514U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD515U, 0x82U); + NT35510_WriteRegData(pstcLCD, 0xD516U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD517U, 0xCAU); + NT35510_WriteRegData(pstcLCD, 0xD518U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD519U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD51AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD51BU, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD51CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD51DU, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD51EU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD51FU, 0x67U); + NT35510_WriteRegData(pstcLCD, 0xD520U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD521U, 0x84U); + NT35510_WriteRegData(pstcLCD, 0xD522U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD523U, 0xA4U); + NT35510_WriteRegData(pstcLCD, 0xD524U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD525U, 0xB7U); + NT35510_WriteRegData(pstcLCD, 0xD526U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD527U, 0xCFU); + NT35510_WriteRegData(pstcLCD, 0xD528U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD529U, 0xDEU); + NT35510_WriteRegData(pstcLCD, 0xD52AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD52BU, 0xF2U); + NT35510_WriteRegData(pstcLCD, 0xD52CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD52DU, 0xFEU); + NT35510_WriteRegData(pstcLCD, 0xD52EU, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD52FU, 0x10U); + NT35510_WriteRegData(pstcLCD, 0xD530U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD531U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD532U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD533U, 0x6DU); + NT35510_WriteRegData(pstcLCD, 0xD600U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD601U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD602U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD603U, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD604U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD605U, 0x3AU); + NT35510_WriteRegData(pstcLCD, 0xD606U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD607U, 0x4AU); + NT35510_WriteRegData(pstcLCD, 0xD608U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD609U, 0x5CU); + NT35510_WriteRegData(pstcLCD, 0xD60AU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD60BU, 0x81U); + NT35510_WriteRegData(pstcLCD, 0xD60CU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD60DU, 0xA6U); + NT35510_WriteRegData(pstcLCD, 0xD60EU, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD60FU, 0xE5U); + NT35510_WriteRegData(pstcLCD, 0xD610U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD611U, 0x13U); + NT35510_WriteRegData(pstcLCD, 0xD612U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD613U, 0x54U); + NT35510_WriteRegData(pstcLCD, 0xD614U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD615U, 0x82U); + NT35510_WriteRegData(pstcLCD, 0xD616U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD617U, 0xCAU); + NT35510_WriteRegData(pstcLCD, 0xD618U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD619U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xD61AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD61BU, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xD61CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD61DU, 0x34U); + NT35510_WriteRegData(pstcLCD, 0xD61EU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD61FU, 0x67U); + NT35510_WriteRegData(pstcLCD, 0xD620U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD621U, 0x84U); + NT35510_WriteRegData(pstcLCD, 0xD622U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD623U, 0xA4U); + NT35510_WriteRegData(pstcLCD, 0xD624U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD625U, 0xB7U); + NT35510_WriteRegData(pstcLCD, 0xD626U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD627U, 0xCFU); + NT35510_WriteRegData(pstcLCD, 0xD628U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD629U, 0xDEU); + NT35510_WriteRegData(pstcLCD, 0xD62AU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD62BU, 0xF2U); + NT35510_WriteRegData(pstcLCD, 0xD62CU, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xD62DU, 0xFEU); + NT35510_WriteRegData(pstcLCD, 0xD62EU, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD62FU, 0x10U); + NT35510_WriteRegData(pstcLCD, 0xD630U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD631U, 0x33U); + NT35510_WriteRegData(pstcLCD, 0xD632U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xD633U, 0x6DU); + /* LV2 Page 0 enable */ + NT35510_WriteRegData(pstcLCD, 0xF000U, 0x55U); + NT35510_WriteRegData(pstcLCD, 0xF001U, 0xAAU); + NT35510_WriteRegData(pstcLCD, 0xF002U, 0x52U); + NT35510_WriteRegData(pstcLCD, 0xF003U, 0x08U); + NT35510_WriteRegData(pstcLCD, 0xF004U, 0x00U); + /* Display control */ + NT35510_WriteRegData(pstcLCD, 0xB100U, 0xCCU); + NT35510_WriteRegData(pstcLCD, 0xB101U, 0x00U); + /* Source hold time */ + NT35510_WriteRegData(pstcLCD, 0xB600U, 0x05U); + /* Gate EQ control */ + NT35510_WriteRegData(pstcLCD, 0xB700U, 0x70U); + NT35510_WriteRegData(pstcLCD, 0xB701U, 0x70U); + /* Source EQ control (Mode 2) */ + NT35510_WriteRegData(pstcLCD, 0xB800U, 0x01U); + NT35510_WriteRegData(pstcLCD, 0xB801U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xB802U, 0x03U); + NT35510_WriteRegData(pstcLCD, 0xB803U, 0x03U); + /* Inversion mode (2-dot) */ + NT35510_WriteRegData(pstcLCD, 0xBC00U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xBC01U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0xBC02U, 0x00U); + /* Timing control 4H w/ 4-delay */ + NT35510_WriteRegData(pstcLCD, 0xC900U, 0xD0U); + NT35510_WriteRegData(pstcLCD, 0xC901U, 0x02U); + NT35510_WriteRegData(pstcLCD, 0xC902U, 0x50U); + NT35510_WriteRegData(pstcLCD, 0xC903U, 0x50U); + NT35510_WriteRegData(pstcLCD, 0xC904U, 0x50U); + NT35510_WriteRegData(pstcLCD, 0x3500U, 0x00U); + NT35510_WriteRegData(pstcLCD, 0x3A00U, 0x55U); /* 16-bit/pixel */ + NT35510_WriteReg(pstcLCD, 0x1100U); + LCD_Delay(120UL); + NT35510_WriteReg(pstcLCD, 0x2900U); +} + +/** + * @} + */ + +/** + * @defgroup NT35510_Global_Functions NT35510 Global Functions + * @{ + */ + +/** + * @brief Initialize LCD device. + * @param [in] pstcLCD: LCD controller + * @retval None + */ +void NT35510_Init(stc_lcd_controller_t *pstcLCD) +{ + uint16_t u16ID; + + if (NULL != pstcLCD) { + /* NOP */ + NT35510_WriteRegData(pstcLCD, 0x0000U, 0x00U); + + /* Read ID */ + u16ID = NT35510_ReadID(pstcLCD); + + if (0x5310U == u16ID) { + LCD_NT35310_Config(pstcLCD); + m_stcLcdDevice.u16Width = 320U; + m_stcLcdDevice.u16Height = 480U; + m_stcLcdDevice.u16WRamCmd = 0x2CU; + m_stcLcdDevice.u16SetXCmd = 0x2AU; + m_stcLcdDevice.u16SetYCmd = 0x2BU; + } else if (0x5510U == u16ID) { + LCD_NT35510_Config(pstcLCD); + m_stcLcdDevice.u16Width = 480U; + m_stcLcdDevice.u16Height = 800U; + m_stcLcdDevice.u16WRamCmd = 0x2C00U; + m_stcLcdDevice.u16SetXCmd = 0x2A00U; + m_stcLcdDevice.u16SetYCmd = 0x2B00U; + } else { + /* Unsupported LCD */ + } + + m_stcLcdDevice.u16ID = u16ID; + + NT35510_SetDisplayDir(pstcLCD, LCD_DISPLAY_VERTICAL); + + /* Set cursor */ + NT35510_SetCursor(pstcLCD, 0U, 0U); + + /* Prepare to write to LCD RAM */ + NT35510_PrepareWriteRAM(pstcLCD); + } +} + +/** + * @brief Write data on LCD data register. + * @param [in] pstcLCD: LCD controller @ref stc_lcd_controller_t structure. + * @param [in] u16Data: Data to be written + * @retval None + */ +void NT35510_WriteData(stc_lcd_controller_t *pstcLCD, uint16_t u16Data) +{ + if (NULL != pstcLCD) { + pstcLCD->u16RAM = u16Data; + } +} + +/** + * @brief Write register on LCD register. + * @param [in] pstcLCD: LCD controller @ref stc_lcd_controller_t structure. + * @param [in] u16Reg: Address of the selected register. + * @retval None + */ +void NT35510_WriteReg(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg) +{ + if (NULL != pstcLCD) { + pstcLCD->u16REG = u16Reg; + } +} + +/** + * @brief Read data from LCD data register. + * @param [in] pstcLCD: LCD controller @ref stc_lcd_controller_t structure. + * @retval Read data. + */ +uint16_t NT35510_ReadData(stc_lcd_controller_t *pstcLCD) +{ + uint16_t u16Val = 0U; + + if (NULL != pstcLCD) { + u16Val = pstcLCD->u16RAM; + } + + return u16Val; +} + +/** + * @brief Write to the selected LCD register. + * @param [in] pstcLCD: LCD controller @ref stc_lcd_controller_t structure. + * @param [in] u16Reg: Address of the selected register. + * @param [in] u16Data: Data to be written + * @retval None + */ +void NT35510_WriteRegData(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg, uint16_t u16Data) +{ + if (NULL != pstcLCD) { + /* Write 16-bit index */ + pstcLCD->u16REG = u16Reg; + /* Write 16-bit Reg */ + pstcLCD->u16RAM = u16Data; + } +} + +/** + * @brief Read the selected LCD register. + * @param [in] pstcLCD: LCD controller @ref stc_lcd_controller_t structure. + * @param [in] u16Reg: Address of the selected register. + * @retval Register value + */ +uint16_t NT35510_ReadRegData(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg) +{ + uint16_t u16Val = 0U; + + if (NULL != pstcLCD) { + /* Write 16-bit index*/ + pstcLCD->u16REG = u16Reg; + u16Val = pstcLCD->u16RAM; + } + + return u16Val; +} + +/** + * @brief Read LCD ID. + * @param [in] pstcLCD: LCD controller @ref stc_lcd_controller_t structure. + * @retval LCD Register Value. + */ +uint16_t NT35510_ReadID(stc_lcd_controller_t *pstcLCD) +{ + uint16_t u16ID = 0U; + + if (NULL != pstcLCD) { + /* Try to read ID: 0x9341 */ + NT35510_WriteReg(pstcLCD, 0xD3U); + (void)NT35510_ReadData(pstcLCD); /* dummy read */ + (void)NT35510_ReadData(pstcLCD); /* read: 0x00 */ + u16ID = NT35510_ReadData(pstcLCD) << 8; /* read: 0x93 */ + u16ID |= NT35510_ReadData(pstcLCD); /* read: 0x41 */ + if (u16ID != 0x9341U) { + /* Try to read ID: 0x8552 */ + NT35510_WriteReg(pstcLCD, 0x04U); + (void)NT35510_ReadData(pstcLCD); /* dummy read */ + (void)NT35510_ReadData(pstcLCD); /* read: 0x85 */ + u16ID = NT35510_ReadData(pstcLCD) << 8; /* read: 0x85 */ + u16ID |= NT35510_ReadData(pstcLCD); /* read: 0x41 */ + if (u16ID == 0x8552U) { + u16ID = 0x7789U; /* ID convert to: 0x7789 */ + } else { + /* Try to read ID: 0x5310 (NT35310) */ + NT35510_WriteReg(pstcLCD, 0xD4U); + (void)NT35510_ReadData(pstcLCD); /* dummy read */ + (void)NT35510_ReadData(pstcLCD); /* read: 0x01 */ + u16ID = NT35510_ReadData(pstcLCD) << 8; /* read: 0x53 */ + u16ID |= NT35510_ReadData(pstcLCD); /* read: 0x10 */ + if (u16ID != 0x5310U) { + /* Try to read ID: 0x008000 (NT35510) */ + NT35510_WriteReg(pstcLCD, 0xDA00); + (void)NT35510_ReadData(pstcLCD); /* read 0xDA00: 0x0000 */ + NT35510_WriteReg(pstcLCD, 0xDB00U); + u16ID = NT35510_ReadData(pstcLCD) << 8; /* read 0xDB00: 0x0080 */ + NT35510_WriteReg(pstcLCD, 0xDC00U); + u16ID |= NT35510_ReadData(pstcLCD); /* read 0xDC00: 0x0000 */ + /* Read ID: ID=008000H (5510H) */ + if (u16ID == 0x008000UL) { + u16ID = 0x5510U; /* ID convert to: 0x5510 */ + } else { + u16ID = 0U; /* Unsupported LCD */ + } + } + } + } + } + + return u16ID; +} + +/** + * @brief Enable the Display. + * @param [in] pstcLCD: LCD controller + * @retval None + */ +void NT35510_DisplayOn(stc_lcd_controller_t *pstcLCD) +{ + if (NULL != pstcLCD) { + if (m_stcLcdDevice.u16ID == 0x5510U) { + NT35510_WriteReg(pstcLCD, 0x2900U); /* 5510 */ + } else { + NT35510_WriteReg(pstcLCD, 0x29U); /* 9341/5310/1963/7789 */ + } + } +} + +/** + * @brief Disable the Display. + * @param [in] pstcLCD: LCD controller + * @retval None + */ +void NT35510_DisplayOff(stc_lcd_controller_t *pstcLCD) +{ + if (NULL != pstcLCD) { + if (m_stcLcdDevice.u16ID == 0x5510U) { + NT35510_WriteReg(pstcLCD, 0x2800U); /* 5510 */ + } else { + NT35510_WriteReg(pstcLCD, 0x28U); /* 9341/5310/1963/7789 */ + } + } +} + +/** + * @brief Get LCD PIXEL WIDTH. + * @param None + * @retval LCD PIXEL WIDTH. + */ +uint16_t NT35510_GetPixelWidth(void) +{ + return m_stcLcdDevice.u16Width; +} + +/** + * @brief Get LCD PIXEL HEIGHT. + * @param None + * @retval LCD PIXEL HEIGHT. + */ +uint16_t NT35510_GetPixelHeight(void) +{ + return m_stcLcdDevice.u16Height; +} + +/** + * @brief Set scan direction. + * @param [in] pstcLCD: LCD controller + * @param [in] u16Dir: Scan direction + * This parameter can be one of the following values: + * @arg LCD_SCAN_DIR_L2R_U2D: From left to right && from up to down + * @arg LCD_SCAN_DIR_L2R_D2U: From left to right && from down to up + * @arg LCD_SCAN_DIR_R2L_U2D: From right to left && from up to down + * @arg LCD_SCAN_DIR_R2L_D2U: From right to left && from down to up + * @arg LCD_SCAN_DIR_U2D_L2R: From up to down && from left to right + * @arg LCD_SCAN_DIR_U2D_R2L: From up to down && from right to left + * @arg LCD_SCAN_DIR_D2U_L2R: From down to up && from left to right + * @arg LCD_SCAN_DIR_D2U_R2L: From down to up && from right to left + * @retval None + */ +void NT35510_SetScanDir(stc_lcd_controller_t *pstcLCD, uint16_t u16Dir) +{ + uint16_t u16Temp; + uint16_t dirreg; + uint16_t regval = 0U; + + if (NULL != pstcLCD) { + /* when display dir is VERTICAL, 1963 IC change scan-direction, other IC don't change + when display dir is HORIZONTAL, 1963 IC don't change scan-direction, other IC change */ + if (((0U == m_stcLcdDevice.u16Dir) && (m_stcLcdDevice.u16ID == 0x1963U)) || \ + ((1U == m_stcLcdDevice.u16Dir) && (m_stcLcdDevice.u16ID != 0x1963U))) { + if (0U == u16Dir) { + u16Dir = 6U; + } else if (1U == u16Dir) { + u16Dir = 7U; + } else if (2U == u16Dir) { + u16Dir = 4U; + } else if (3UL == u16Dir) { + u16Dir = 5U; + } else if (4U == u16Dir) { + u16Dir = 1U; + } else if (5U == u16Dir) { + u16Dir = 0U; + } else if (6U == u16Dir) { + u16Dir = 3U; + } else if (7U == u16Dir) { + u16Dir = 2U; + } else { + u16Dir = 6U; + } + } + + switch (u16Dir) { + case LCD_SCAN_DIR_L2R_U2D: + regval |= ((0U << 7) | (0U << 6) | (0U << 5)); + break; + case LCD_SCAN_DIR_L2R_D2U: + regval |= ((1U << 7) | (0U << 6) | (0U << 5)); + break; + case LCD_SCAN_DIR_R2L_U2D: + regval |= ((0U << 7) | (1U << 6) | (0U << 5)); + break; + case LCD_SCAN_DIR_R2L_D2U: + regval |= ((1U << 7) | (1U << 6) | (0U << 5)); + break; + case LCD_SCAN_DIR_U2D_L2R: + regval |= ((0U << 7) | (0U << 6) | (1U << 5)); + break; + case LCD_SCAN_DIR_U2D_R2L: + regval |= ((0U << 7) | (1U << 6) | (1U << 5)); + break; + case LCD_SCAN_DIR_D2U_L2R: + regval |= ((1U << 7) | (0U << 6) | (1U << 5)); + break; + case LCD_SCAN_DIR_D2U_R2L: + regval |= ((1U << 7) | (1U << 6) | (1U << 5)); + break; + default: + break; + } + + if (0x5510U == m_stcLcdDevice.u16ID) { + dirreg = 0x3600U; + } else { + dirreg = 0x36U; + } + + /* 0x9341 & 0x7789 set BGR bit */ + if ((0x9341U == m_stcLcdDevice.u16ID) || (0x7789U == m_stcLcdDevice.u16ID)) { + regval |= 0x08U; + } + + NT35510_WriteRegData(pstcLCD, dirreg, regval); + + /* 1963 don't handle coordinate */ + if (m_stcLcdDevice.u16ID != 0x1963U) { + if ((regval & 0x20U) > 0U) { + /* swap X,Y */ + if (m_stcLcdDevice.u16Width < m_stcLcdDevice.u16Height) { + u16Temp = m_stcLcdDevice.u16Width; + m_stcLcdDevice.u16Width = m_stcLcdDevice.u16Height; + m_stcLcdDevice.u16Height = u16Temp; + } + } else { + /* swap X,Y */ + if (m_stcLcdDevice.u16Width > m_stcLcdDevice.u16Height) { + u16Temp = m_stcLcdDevice.u16Width; + m_stcLcdDevice.u16Width = m_stcLcdDevice.u16Height; + m_stcLcdDevice.u16Height = u16Temp; + } + } + } + + /* Set display window size */ + if (0x5510U == m_stcLcdDevice.u16ID) { + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetXCmd); + NT35510_WriteData(pstcLCD, 0U); + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetXCmd + 1U); + NT35510_WriteData(pstcLCD, 0U); + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetXCmd + 2U); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Width - 1U) >> 8U); + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetXCmd + 3U); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Width - 1U) & 0xFFU); + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd); + NT35510_WriteData(pstcLCD, 0U); + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd + 1U); + NT35510_WriteData(pstcLCD, 0U); + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd + 2U); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Height - 1U) >> 8U); + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd + 3U); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Height - 1U) & 0xFFU); + } else { + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd); + NT35510_WriteData(pstcLCD, 0U); + NT35510_WriteData(pstcLCD, 0U); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Width - 1U) >> 8); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Width - 1U) & 0xFFU); + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd); + NT35510_WriteData(pstcLCD, 0U); + NT35510_WriteData(pstcLCD, 0U); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Height - 1U) >> 8); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Height - 1U) & 0xFFU); + } + } +} + +/** + * @brief Set screen direction. + * @param [in] pstcLCD: LCD controller + * @param [in] u16Dir: Screen direction + * This parameter can be one of the following values: + * @arg LCD_DISPLAY_VERTICAL: LCD vertical display + * @arg LCD_DISPLAY_HORIZONTAL: LCD horizontal display + * @retval None + */ +void NT35510_SetDisplayDir(stc_lcd_controller_t *pstcLCD, uint16_t u16Dir) +{ + if (NULL != pstcLCD) { + if (LCD_DISPLAY_VERTICAL == u16Dir) { /* Vertical */ + if (0x1963U == m_stcLcdDevice.u16ID) { + m_stcLcdDevice.u16WRamCmd = 0x2CU; + m_stcLcdDevice.u16SetXCmd = 0x2BU; + m_stcLcdDevice.u16SetYCmd = 0x2AU; + m_stcLcdDevice.u16Width = 480U; + m_stcLcdDevice.u16Height = 800U; + } else if (0x5510U == m_stcLcdDevice.u16ID) { + /* NT35510 */ + m_stcLcdDevice.u16WRamCmd = 0x2C00U; + m_stcLcdDevice.u16SetXCmd = 0x2A00U; + m_stcLcdDevice.u16SetYCmd = 0x2B00U; + m_stcLcdDevice.u16Width = 480U; + m_stcLcdDevice.u16Height = 800U; + } else { + /* NT35310 / 9341 / 5310 / 7789 etc */ + m_stcLcdDevice.u16WRamCmd = 0x2CU; + m_stcLcdDevice.u16SetXCmd = 0x2AU; + m_stcLcdDevice.u16SetYCmd = 0x2BU; + if (0x5310U == m_stcLcdDevice.u16ID) { + /* NT35310 */ + m_stcLcdDevice.u16Width = 320U; + m_stcLcdDevice.u16Height = 480U; + } else { + m_stcLcdDevice.u16Width = 240U; + m_stcLcdDevice.u16Height = 320U; + } + } + } else { /* Horizontal */ + if (0x1963U == m_stcLcdDevice.u16ID) { + m_stcLcdDevice.u16WRamCmd = 0x2CU; + m_stcLcdDevice.u16SetXCmd = 0x2AU; + m_stcLcdDevice.u16SetYCmd = 0x2BU; + m_stcLcdDevice.u16Width = 800U; + m_stcLcdDevice.u16Height = 480U; + } else if (0x5510U == m_stcLcdDevice.u16ID) { + /* NT35510 */ + m_stcLcdDevice.u16WRamCmd = 0x2C00U; + m_stcLcdDevice.u16SetXCmd = 0x2A00U; + m_stcLcdDevice.u16SetYCmd = 0x2B00U; + m_stcLcdDevice.u16Width = 800U; + m_stcLcdDevice.u16Height = 480U; + } else { + /* NT35310 / 9341 / 5310 / 7789 etc */ + m_stcLcdDevice.u16WRamCmd = 0x2CU; + m_stcLcdDevice.u16SetXCmd = 0x2AU; + m_stcLcdDevice.u16SetYCmd = 0x2BU; + if (0x5310U == m_stcLcdDevice.u16ID) { + /* NT35310 */ + m_stcLcdDevice.u16Width = 480U; + m_stcLcdDevice.u16Height = 320U; + } else { + m_stcLcdDevice.u16Width = 320U; + m_stcLcdDevice.u16Height = 240U; + } + } + } + + m_stcLcdDevice.u16Dir = u16Dir; + NT35510_SetScanDir(pstcLCD, LCD_SCAN_DIR); + } +} + +/** + * @brief Prepare to write LCD RAM. + * @param [in] pstcLCD: LCD controller + * @retval None + */ +void NT35510_PrepareWriteRAM(stc_lcd_controller_t *pstcLCD) +{ + if (NULL != pstcLCD) { + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16WRamCmd); + } +} + +/** + * @brief Set screen backlight. + * @param [in] pstcLCD: LCD controller + * @param [in] u8PWM: PWM level + This parameter can be a value between Min_Data = 0 and Max_Data = 100 + * @retval None + */ +void NT35510_SetBackLight(stc_lcd_controller_t *pstcLCD, uint8_t u8PWM) +{ + float32_t f32PWM = ((float32_t)u8PWM * 2.55F); + + if (NULL != pstcLCD) { + NT35510_WriteReg(pstcLCD, 0xBEU); + NT35510_WriteData(pstcLCD, 0x05U); + NT35510_WriteData(pstcLCD, (uint16_t)f32PWM); + NT35510_WriteData(pstcLCD, 0x01U); + NT35510_WriteData(pstcLCD, 0xFFU); + NT35510_WriteData(pstcLCD, 0x00U); + NT35510_WriteData(pstcLCD, 0x00U); + } +} + +/** + * @brief Set Cursor position. + * @param [in] pstcLCD: LCD controller + * @param u16Xpos: Specifies the X position. + * @param u16Ypos: Specifies the Y position. + * @retval None + */ +void NT35510_SetCursor(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos) +{ + if (NULL != pstcLCD) { + if (0x1963U == m_stcLcdDevice.u16ID) { + /* Convert X coordinate */ + if (m_stcLcdDevice.u16Dir == 0U) { + u16Xpos = m_stcLcdDevice.u16Width - 1U - u16Xpos; + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetXCmd); + NT35510_WriteData(pstcLCD, 0U); + NT35510_WriteData(pstcLCD, 0U); + NT35510_WriteData(pstcLCD, u16Xpos >> 8); + NT35510_WriteData(pstcLCD, u16Xpos & 0xFFU); + } else { + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetXCmd); + NT35510_WriteData(pstcLCD, u16Xpos >> 8); + NT35510_WriteData(pstcLCD, u16Xpos & 0xFFU); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Width - 1U) >> 8); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Width - 1U) & 0xFFU); + } + + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd); + NT35510_WriteData(pstcLCD, u16Ypos >> 8); + NT35510_WriteData(pstcLCD, u16Ypos & 0xFFU); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Height - 1U) >> 8); + NT35510_WriteData(pstcLCD, (m_stcLcdDevice.u16Height - 1U) & 0xFFU); + } else if (0x5510U == m_stcLcdDevice.u16ID) { + NT35510_WriteRegData(pstcLCD, m_stcLcdDevice.u16SetXCmd, (u16Xpos >> 8U)); + NT35510_WriteRegData(pstcLCD, (m_stcLcdDevice.u16SetXCmd + 1U), (u16Xpos & 0xFFU)); + NT35510_WriteRegData(pstcLCD, m_stcLcdDevice.u16SetYCmd, (u16Ypos >> 8U)); + NT35510_WriteRegData(pstcLCD, (m_stcLcdDevice.u16SetYCmd + 1U), (u16Ypos & 0xFFU)); + } else { /* NT35310 / 9341 / 5310 / 7789 etc */ + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetXCmd); + NT35510_WriteData(pstcLCD, (u16Xpos >> 8)); + NT35510_WriteData(pstcLCD, (u16Xpos & 0xFFU)); + NT35510_WriteReg(pstcLCD, m_stcLcdDevice.u16SetYCmd); + NT35510_WriteData(pstcLCD, (u16Ypos >> 8)); + NT35510_WriteData(pstcLCD, (u16Ypos & 0xFFU)); + } + } +} + +/** + * @brief Write pixel. + * @param [in] pstcLCD: LCD controller + * @param u16Xpos: Specifies the X position. + * @param u16Ypos: Specifies the Y position. + * @param u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void NT35510_WritePixel(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos, uint16_t u16RGBCode) +{ + if (NULL != pstcLCD) { + /* Set cursor */ + NT35510_SetCursor(pstcLCD, u16Xpos, u16Ypos); + + /* Prepare to write to LCD RAM */ + NT35510_PrepareWriteRAM(pstcLCD); + + NT35510_WriteData(pstcLCD, u16RGBCode); + } +} + +/** + * @brief Draw line. + * @param [in] pstcLCD: LCD controller + * @param u16X1: Specifies the X position 1. + * @param u16X2: Specifies the X position 2. + * @param u16Y1: Specifies the Y position 1. + * @param u16Y2: Specifies the Y position 2. + * @param u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void NT35510_DrawLine(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode) +{ + int16_t t; + int16_t xerr = 0; + int16_t yerr = 0; + int16_t delta_x; + int16_t delta_y; + int16_t distance; + int16_t incx; + int16_t incy; + int16_t Row; + int16_t Col; + + if (NULL != pstcLCD) { + Row = (int16_t)u16X1; + Col = (int16_t)u16Y1; + delta_x = ((int16_t)u16X2 - (int16_t)u16X1); /* calc delta X, Y*/ + delta_y = ((int16_t)u16Y2 - (int16_t)u16Y1); + + if (delta_x > 0) { + incx = 1; /* forward u8Direction */ + } else if (delta_x == 0) { + incx = 0; /* vertical line */ + } else { + incx = -1; /* reverse direction */ + delta_x = -delta_x; + } + + if (delta_y > 0) { + incy = 1; /* downward direction */ + } else if (delta_y == 0) { + incy = 0; /* horizontal line */ + } else { + incy = -1; /* upward direction */ + delta_y = -delta_y; + } + + if (delta_x > delta_y) { + distance = delta_x; /* set axis */ + } else { + distance = delta_y; + } + + for (t = 0; t <= (distance + 1); t++) { + NT35510_WritePixel(pstcLCD, (uint16_t)Row, (uint16_t)Col, u16RGBCode); /* draw pixel */ + + xerr += delta_x ; + yerr += delta_y ; + + if (xerr > distance) { + xerr -= distance; + Row += incx; + } + + if (yerr > distance) { + yerr -= distance; + Col += incy; + } + } + } +} + +/** + * @brief Draw a circle. + * @param [in] pstcLCD: LCD controller + * @param [in] u16Xpos: X position + * @param [in] u16Ypos: Y position + * @param [in] u16Radius: Circle radius + * @param u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void NT35510_DrawCircle(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos, + uint16_t u16Radius, uint16_t u16RGBCode) +{ + int32_t decision; /* Decision Variable */ + uint32_t current_x; /* Current X Value */ + uint32_t current_y; /* Current Y Value */ + + if (NULL != pstcLCD) { + decision = 3 - ((int32_t)u16Radius * 2); + current_x = 0U; + current_y = u16Radius; + + while (current_x <= current_y) { + NT35510_WritePixel(pstcLCD, (u16Xpos + (uint16_t)current_x), (u16Ypos - (uint16_t)current_y), u16RGBCode); + NT35510_WritePixel(pstcLCD, (u16Xpos + (uint16_t)current_y), (u16Ypos - (uint16_t)current_x), u16RGBCode); + NT35510_WritePixel(pstcLCD, (u16Xpos + (uint16_t)current_y), (u16Ypos + (uint16_t)current_x), u16RGBCode); + NT35510_WritePixel(pstcLCD, (u16Xpos + (uint16_t)current_x), (u16Ypos + (uint16_t)current_y), u16RGBCode); + NT35510_WritePixel(pstcLCD, (u16Xpos - (uint16_t)current_x), (u16Ypos + (uint16_t)current_y), u16RGBCode); + NT35510_WritePixel(pstcLCD, (u16Xpos - (uint16_t)current_y), (u16Ypos + (uint16_t)current_x), u16RGBCode); + NT35510_WritePixel(pstcLCD, (u16Xpos - (uint16_t)current_x), (u16Ypos - (uint16_t)current_y), u16RGBCode); + NT35510_WritePixel(pstcLCD, (u16Xpos - (uint16_t)current_y), (u16Ypos - (uint16_t)current_x), u16RGBCode); + current_x++; + /* Bresenham algorithm */ + if (decision < 0) { + decision += ((4 * (int32_t)current_x) + 6); + } else { + decision += (10 + (4 * ((int32_t)current_x - (int32_t)current_y))); + current_y--; + } + } + } +} + +/** + * @brief Fill a triangle (between 3 points). + * @param [in] pstcLCD: LCD controller + * @param [in] u16X1: Point 1 X position + * @param [in] u16Y1: Point 1 Y position + * @param [in] u16X2: Point 2 X position + * @param [in] u16Y2: Point 2 Y position + * @param [in] u16X3: Point 3 X position + * @param [in] u16Y3: Point 3 Y position + * @param u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void NT35510_FillTriangle(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16X3, uint16_t u16Y3, uint16_t u16RGBCode) +{ + uint16_t deltax; + uint16_t deltay; + int16_t xoff; + int16_t yoff; + int16_t xinc1; + int16_t xinc2; + int16_t yinc1; + int16_t yinc2; + uint16_t den; + uint16_t num; + uint16_t numadd; + uint16_t numpixels; + uint16_t curpixel; + + if (NULL != pstcLCD) { + xoff = (int16_t)u16X1; /* Start x off at the first pixel */ + yoff = (int16_t)u16Y1; /* Start y off at the first pixel */ + + /* The difference between the x's */ + if (u16X2 > u16X1) { + deltax = (u16X2 - u16X1); + } else { + deltax = (u16X1 - u16X2); + } + + /* The difference between the y's */ + if (u16Y2 > u16Y1) { + deltay = (u16Y2 - u16Y1); + } else { + deltay = (u16Y1 - u16Y2); + } + + if (u16X2 >= u16X1) { + /* The x-values are increasing */ + xinc1 = 1; + xinc2 = 1; + } else { + /* The x-values are decreasing */ + xinc1 = -1; + xinc2 = -1; + } + + if (u16Y2 >= u16Y1) { + /* The y-values are increasing */ + yinc1 = 1; + yinc2 = 1; + } else { + /* The y-values are decreasing */ + yinc1 = -1; + yinc2 = -1; + } + + /* There is at least one x-value for every y-value */ + if (deltax >= deltay) { + xinc1 = 0; /* Don't change the x when numerator >= denominator */ + yinc2 = 0; /* Don't change the y for every iteration */ + den = deltax; + num = (deltax / 2U); + numadd = deltay; + numpixels = deltax; /* There are more x-values than y-values */ + } else { + /* There is at least one y-value for every x-value */ + xinc2 = 0; /* Don't change the x for every iteration */ + yinc1 = 0; /* Don't change the y when numerator >= denominator */ + den = deltay; + num = (deltay / 2U); + numadd = deltax; + numpixels = deltay; /* There are more y-values than x-values */ + } + + for (curpixel = 0U; curpixel <= numpixels; curpixel++) { + NT35510_DrawLine(pstcLCD, (uint16_t)xoff, (uint16_t)yoff, u16X3, u16Y3, u16RGBCode); + + num += numadd; /* Increase the numerator by the top of the fraction */ + + /* Check if numerator >= denominator */ + if (num >= den) { + num -= den; /* Calculate the new numerator value */ + xoff += xinc1; /* Change the x as appropriate */ + yoff += yinc1; /* Change the y as appropriate */ + } + xoff += xinc2; /* Change the x as appropriate */ + yoff += yinc2; /* Change the y as appropriate */ + } + } +} + +/** + * @brief Draw rectangle. + * @param [in] pstcLCD: LCD controller + * @param [in] u16X1: Point 1 X position + * @param [in] u16Y1: Point 1 Y position + * @param [in] u16X2: Point 2 X position + * @param [in] u16Y2: Point 2 Y position + * @param u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void NT35510_DrawRectangle(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode) +{ + if (NULL != pstcLCD) { + NT35510_DrawLine(pstcLCD, u16X1, u16Y1, u16X2, u16Y1, u16RGBCode); + NT35510_DrawLine(pstcLCD, u16X1, u16Y1, u16X1, u16Y2, u16RGBCode); + NT35510_DrawLine(pstcLCD, u16X1, u16Y2, u16X2, u16Y2, u16RGBCode); + NT35510_DrawLine(pstcLCD, u16X2, u16Y1, u16X2, u16Y2, u16RGBCode); + } +} + +/** + * @brief Clear screen. + * @param [in] pstcLCD: LCD controller + * @param u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void NT35510_Clear(stc_lcd_controller_t *pstcLCD, uint16_t u16RGBCode) +{ + uint32_t i; + uint32_t u32TotalPoint; + + if (NULL != pstcLCD) { + /* Set cursor */ + NT35510_SetCursor(pstcLCD, 0U, 0U); + /* Prepare to write to LCD RAM */ + NT35510_PrepareWriteRAM(pstcLCD); + + u32TotalPoint = (uint32_t)m_stcLcdDevice.u16Width * (uint32_t)m_stcLcdDevice.u16Height; + for (i = 0UL; i < u32TotalPoint; i++) { + NT35510_WriteData(pstcLCD, u16RGBCode); + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/nt35510/nt35510.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/nt35510/nt35510.h new file mode 100644 index 0000000000..f07c31dad1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/nt35510/nt35510.h @@ -0,0 +1,202 @@ +/** + ******************************************************************************* + * @file nt35510.h + * @brief This file contains all the functions prototypes of the LCD NT35510 + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-05-31 CDT Optimize function arguments + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __NT35510_H__ +#define __NT35510_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @addtogroup NT35510 + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup NT35510_Global_Types NT35510 Global Types + * @{ + */ + +/** + * @brief LCD Device Controller Structure Definition + */ +typedef struct { + volatile uint16_t u16REG; + volatile uint16_t u16RAM; +} stc_lcd_controller_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup NT35510_Global_Macros NT35510 Global Macros + * @{ + */ + +/** + * @defgroup LCD_Scan_Direction LCD Scan Direction + * @{ + */ +#define LCD_SCAN_DIR_L2R_U2D (0U) /* From left to right && from up to down */ +#define LCD_SCAN_DIR_L2R_D2U (1U) /* From left to right && from down to up */ +#define LCD_SCAN_DIR_R2L_U2D (2U) /* From right to left && from up to down */ +#define LCD_SCAN_DIR_R2L_D2U (3U) /* From right to left && from down to up */ +#define LCD_SCAN_DIR_U2D_L2R (4U) /* From up to down && from left to right */ +#define LCD_SCAN_DIR_U2D_R2L (5U) /* From up to down && from right to left */ +#define LCD_SCAN_DIR_D2U_L2R (6U) /* From down to up && from left to right */ +#define LCD_SCAN_DIR_D2U_R2L (7U) /* From down to up && from right to left */ +/** + * @} + */ + +/** + * @defgroup LCD_Display_Direction LCD Display Direction + * @{ + */ +#define LCD_DISPLAY_VERTICAL (0x0000U) +#define LCD_DISPLAY_HORIZONTAL (0x0001U) +/** + * @} + */ + +/** + * @defgroup LCD_Color LCD Color + * @{ + */ +#define LCD_COLOR_WHITE (0xFFFFU) +#define LCD_COLOR_BLACK (0x0000U) +#define LCD_COLOR_BLUE (0x001FU) +#define LCD_COLOR_BRED (0xF81FU) +#define LCD_COLOR_GRED (0xFFE0U) +#define LCD_COLOR_GBLUE (0x07FFU) +#define LCD_COLOR_RED (0xF800U) +#define LCD_COLOR_MAGENTA (0xF81FU) +#define LCD_COLOR_GREEN (0x07E0U) +#define LCD_COLOR_CYAN (0x7FFFU) +#define LCD_COLOR_YELLOW (0xFFE0U) +#define LCD_COLOR_BROWN (0xBC40U) +#define LCD_COLOR_BRRED (0xFC07U) +#define LCD_COLOR_GRAY (0x8430U) + +#define LCD_COLOR_DARKBLUE (0x01CFU) +#define LCD_COLOR_LIGHTBLUE (0x7D7CU) +#define LCD_COLOR_GRAYBLUE (0x5458U) + +#define LCD_COLOR_LIGHTGREEN (0x841FU) +#define LCD_COLOR_LIGHTGRAY (0xEF5BU) +#define LCD_COLOR_LGRAY (0xC618U) +#define LCD_COLOR_LGRAYBLUE (0xA651U) +#define LCD_COLOR_LBBLUE (0x2B12U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup NT35510_Global_Functions + * @{ + */ +void NT35510_Init(stc_lcd_controller_t *pstcLCD); +void NT35510_WriteData(stc_lcd_controller_t *pstcLCD, uint16_t u16Data); +void NT35510_WriteReg(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg); +uint16_t NT35510_ReadData(stc_lcd_controller_t *pstcLCD); +void NT35510_WriteRegData(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg, uint16_t u16Data); +uint16_t NT35510_ReadRegData(stc_lcd_controller_t *pstcLCD, uint16_t u16Reg); +uint16_t NT35510_ReadID(stc_lcd_controller_t *pstcLCD); +void NT35510_DisplayOn(stc_lcd_controller_t *pstcLCD); +void NT35510_DisplayOff(stc_lcd_controller_t *pstcLCD); +uint16_t NT35510_GetPixelWidth(void); +uint16_t NT35510_GetPixelHeight(void); +void NT35510_SetScanDir(stc_lcd_controller_t *pstcLCD, uint16_t u16Dir); +void NT35510_SetDisplayDir(stc_lcd_controller_t *pstcLCD, uint16_t u16Dir); +void NT35510_PrepareWriteRAM(stc_lcd_controller_t *pstcLCD); +void NT35510_SetBackLight(stc_lcd_controller_t *pstcLCD, uint8_t u8PWM); +void NT35510_SetCursor(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos); +void NT35510_WritePixel(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos, uint16_t u16RGBCode); +void NT35510_DrawLine(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode); +void NT35510_DrawCircle(stc_lcd_controller_t *pstcLCD, uint16_t u16Xpos, uint16_t u16Ypos, + uint16_t u16Radius, uint16_t u16RGBCode); +void NT35510_FillTriangle(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16X3, uint16_t u16Y3, uint16_t u16RGBCode); +void NT35510_DrawRectangle(stc_lcd_controller_t *pstcLCD, uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode); +void NT35510_Clear(stc_lcd_controller_t *pstcLCD, uint16_t u16RGBCode); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __NT35510_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.c new file mode 100644 index 0000000000..592713587c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.c @@ -0,0 +1,337 @@ +/** + ******************************************************************************* + * @file tca9539.c + * @brief This file provides firmware functions for IO expand IC TCA9539. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-12-15 CDT Add null pointer check + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "tca9539.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @defgroup TCA9539 IO Expand IC TCA9539 + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TCA9539_Global_Functions TCA9539 Global Functions + * @{ + */ + +/** + * @brief Initialize TCA9539. + * @param [in] pstcTca9539LL Pointer to a @ref stc_tca9539_ll_t structure. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t TCA9539_Init(const stc_tca9539_ll_t *pstcTca9539LL) +{ + int32_t i32Ret = LL_OK; + uint8_t u8TempData[2]; + + if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Reset == NULL) || (pstcTca9539LL->Init == NULL) || + (pstcTca9539LL->Write == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcTca9539LL->Reset(); + pstcTca9539LL->Init(); + /* All Pins are input as default */ + u8TempData[1] = 0xFFU; + u8TempData[0] = TCA9539_REG_CONFIG_PORT0; + pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U); + u8TempData[0] = TCA9539_REG_CONFIG_PORT1; + pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U); + } + + return i32Ret; +} + +/** + * @brief Initialize TCA9539 interrupt. + * @param [in] pstcTca9539LL Pointer to a @ref stc_tca9539_ll_t structure. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t TCA9539_IntInit(const stc_tca9539_ll_t *pstcTca9539LL) +{ + int32_t i32Ret = LL_OK; + + if ((pstcTca9539LL == NULL) || (pstcTca9539LL->IntInit == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcTca9539LL->IntInit(); + } + + return i32Ret; +} + +/** + * @brief Reset TCA9539. + * @param [in] pstcTca9539LL Pointer to a @ref stc_tca9539_ll_t structure. + * @retval int32_t: + * - LL_OK: Reset success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t TCA9539_Reset(const stc_tca9539_ll_t *pstcTca9539LL) +{ + int32_t i32Ret = LL_OK; + + if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Reset == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcTca9539LL->Reset(); + } + + return i32Ret; +} + +/** + * @brief Write TCA9539 pin output value. + * @param [in] pstcTca9539LL Pointer to a @ref stc_tca9539_ll_t structure. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PORT0 + * @arg TCA9539_IO_PORT1 + * @param [in] u8Pin Pin number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PIN0 + * @arg TCA9539_IO_PIN1 + * @arg TCA9539_IO_PIN2 + * @arg TCA9539_IO_PIN3 + * @arg TCA9539_IO_PIN4 + * @arg TCA9539_IO_PIN5 + * @arg TCA9539_IO_PIN6 + * @arg TCA9539_IO_PIN7 + * @arg TCA9539_IO_PIN_ALL: All of the above + * @param [in] u8PinState Pin state to be written. + * This parameter can be one of the following values: + * @arg TCA9539_PIN_RESET + * @arg TCA9539_PIN_SET + * @retval int32_t: + * - LL_OK: Operation success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t TCA9539_WritePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState) +{ + int32_t i32Ret = LL_OK; + uint8_t u8TempData[2]; + + if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pstcTca9539LL->Write == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U); + if (0U == u8PinState) { + u8TempData[1] &= (uint8_t)(~u8Pin); + } else { + u8TempData[1] |= u8Pin; + } + pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U); + } + + return i32Ret; +} + +/** + * @brief Read TCA9539 pin input value. + * @param [in] pstcTca9539LL Pointer to a @ref stc_tca9539_ll_t structure. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PORT0 + * @arg TCA9539_IO_PORT1 + * @param [in] u8Pin Pin number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PIN0 + * @arg TCA9539_IO_PIN1 + * @arg TCA9539_IO_PIN2 + * @arg TCA9539_IO_PIN3 + * @arg TCA9539_IO_PIN4 + * @arg TCA9539_IO_PIN5 + * @arg TCA9539_IO_PIN6 + * @arg TCA9539_IO_PIN7 + * @arg TCA9539_IO_PIN_ALL: All of the above + * @param [out] pu8PinState Pin state to be read. + * This parameter can be one of the following values: + * @arg TCA9539_PIN_RESET + * @arg TCA9539_PIN_SET + * @retval int32_t: + * - LL_OK: Operation success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t TCA9539_ReadPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState) +{ + int32_t i32Ret = LL_OK; + uint8_t u8TempData[2]; + + if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pu8PinState == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u8TempData[0] = u8Port + TCA9539_REG_INPUT_PORT0; + pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U); + if (0U != (u8TempData[1] & u8Pin)) { + *pu8PinState = TCA9539_PIN_SET; + } else { + *pu8PinState = TCA9539_PIN_RESET; + } + } + + return i32Ret; +} + +/** + * @brief Toggle TCA9539 pin output value. + * @param [in] pstcTca9539LL Pointer to a @ref stc_tca9539_ll_t structure. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PORT0 + * @arg TCA9539_IO_PORT1 + * @param [in] u8Pin Pin number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PIN0 + * @arg TCA9539_IO_PIN1 + * @arg TCA9539_IO_PIN2 + * @arg TCA9539_IO_PIN3 + * @arg TCA9539_IO_PIN4 + * @arg TCA9539_IO_PIN5 + * @arg TCA9539_IO_PIN6 + * @arg TCA9539_IO_PIN7 + * @arg TCA9539_IO_PIN_ALL: All of the above + * @retval int32_t: + * - LL_OK: Operation success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t TCA9539_TogglePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin) +{ + int32_t i32Ret = LL_OK; + uint8_t u8TempData[2]; + + if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pstcTca9539LL->Write == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u8TempData[0] = u8Port + TCA9539_REG_OUTPUT_PORT0; + pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U); + u8TempData[1] ^= u8Pin; + pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U); + } + + return i32Ret; +} + +/** + * @brief Configuration TCA9539 pin. + * @param [in] pstcTca9539LL Pointer to a @ref stc_tca9539_ll_t structure. + * @param [in] u8Port Port number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PORT0 + * @arg TCA9539_IO_PORT1 + * @param [in] u8Pin Pin number. + * This parameter can be one of the following values: + * @arg TCA9539_IO_PIN0 + * @arg TCA9539_IO_PIN1 + * @arg TCA9539_IO_PIN2 + * @arg TCA9539_IO_PIN3 + * @arg TCA9539_IO_PIN4 + * @arg TCA9539_IO_PIN5 + * @arg TCA9539_IO_PIN6 + * @arg TCA9539_IO_PIN7 + * @arg TCA9539_IO_PIN_ALL: All of the above + * @param [in] u8Dir Pin output direction. + * This parameter can be one of the following values: + * @arg TCA9539_DIR_OUT + * @arg TCA9539_DIR_IN + * @retval int32_t: + * - LL_OK: Operation success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t TCA9539_ConfigPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir) +{ + int32_t i32Ret = LL_OK; + uint8_t u8TempData[2]; + + if ((pstcTca9539LL == NULL) || (pstcTca9539LL->Read == NULL) || (pstcTca9539LL->Write == NULL)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + u8TempData[0] = u8Port + TCA9539_REG_CONFIG_PORT0; + pstcTca9539LL->Read(&u8TempData[0], &u8TempData[1], 1U); + if (TCA9539_DIR_OUT == u8Dir) { + u8TempData[1] &= (uint8_t)(~u8Pin); + } else { + u8TempData[1] |= u8Pin; + } + pstcTca9539LL->Write(&u8TempData[0], &u8TempData[1], 1U); + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.h new file mode 100644 index 0000000000..c229a78e47 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/tca9539/tca9539.h @@ -0,0 +1,193 @@ +/** + ******************************************************************************* + * @file tca9539.h + * @brief This file contains all the functions prototypes of the TCA9539 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __TCA9539_H__ +#define __TCA9539_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @addtogroup TCA9539 + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TCA9539_Global_Types TCA9539 Global Types + * @{ + */ + +/** + * @brief TCA9539 low layer structure definition + */ +typedef struct { + /* Methods */ + void (*Init)(void); + void (*Write)(const uint8_t *, const uint8_t *, uint32_t); + void (*Read)(const uint8_t *, uint8_t *, uint32_t); + void (*Reset)(void); + void (*IntInit)(void); +} stc_tca9539_ll_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TCA9539_Global_Macros TCA9539 Global Macros + * @{ + */ + +/** + * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition + * @{ + */ +#define TCA9539_REG_INPUT_PORT0 (0x00U) +#define TCA9539_REG_INPUT_PORT1 (0x01U) +#define TCA9539_REG_OUTPUT_PORT0 (0x02U) +#define TCA9539_REG_OUTPUT_PORT1 (0x03U) +#define TCA9539_REG_INVERT_PORT0 (0x04U) +#define TCA9539_REG_INVERT_PORT1 (0x05U) +#define TCA9539_REG_CONFIG_PORT0 (0x06U) +#define TCA9539_REG_CONFIG_PORT1 (0x07U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Port_Definition TCA9539 Port Definition + * @{ + */ +#define TCA9539_IO_PORT0 (0x00U) +#define TCA9539_IO_PORT1 (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition + * @{ + */ +#define TCA9539_IO_PIN0 (0x01U) +#define TCA9539_IO_PIN1 (0x02U) +#define TCA9539_IO_PIN2 (0x04U) +#define TCA9539_IO_PIN3 (0x08U) +#define TCA9539_IO_PIN4 (0x10U) +#define TCA9539_IO_PIN5 (0x20U) +#define TCA9539_IO_PIN6 (0x40U) +#define TCA9539_IO_PIN7 (0x80U) +#define TCA9539_IO_PIN_ALL (0xFFU) +/** + * @} + */ + +/** + * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition + * @{ + */ +#define TCA9539_DIR_OUT (0x00U) +#define TCA9539_DIR_IN (0x01U) +/** + * @} + */ + +/** + * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition + * @{ + */ +#define TCA9539_PIN_RESET (0x00U) +#define TCA9539_PIN_SET (0x01U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @defgroup TCA9539_Global_Functions TCA9539 Global Functions + * @{ + */ +int32_t TCA9539_Init(const stc_tca9539_ll_t *pstcTca9539LL); +int32_t TCA9539_IntInit(const stc_tca9539_ll_t *pstcTca9539LL); +int32_t TCA9539_Reset(const stc_tca9539_ll_t *pstcTca9539LL); + +int32_t TCA9539_WritePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState); +int32_t TCA9539_ReadPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t *pu8PinState); +int32_t TCA9539_TogglePin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin); +int32_t TCA9539_ConfigPin(const stc_tca9539_ll_t *pstcTca9539LL, uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TCA9539_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.c new file mode 100644 index 0000000000..28187b6a9b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.c @@ -0,0 +1,596 @@ +/** + ******************************************************************************* + * @file w25qxx.c + * @brief This midware file provides firmware functions to W25QXX group spi flash. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-12-15 CDT Add null pointer check + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "w25qxx.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @defgroup W25QXX Flash Driver for W25QXX + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup W25QXX_Local_Macros W25QXX Local Macros + * @{ + */ +#define W25QXX_FLAG_BUSY (1UL << 0U) +#define W25QXX_FLAG_WEL (1UL << 1U) /*!< Write Enable Latch */ +#define W25QXX_FLAG_SUSPEND (1UL << 15U) /*!< Write Enable Latch */ + +#define LOAD_CMD(a, cmd, addr) do { \ + (a)[0U] = (cmd); \ + (a)[1U] = (uint8_t)((addr) >> 16U); \ + (a)[2U] = (uint8_t)((addr) >> 8U); \ + (a)[3U] = (uint8_t)(addr); \ + } while (0U) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup W25QXX_Local_Functions W25QXX Local Functions + * @{ + */ + +/** + * @brief W25QXX write command. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u8Cmd Command of W25QXX. + * @param [in] pu8CmdData Pointer to a buffer that contains the data following the command. + * @param [in] u32CmdDataLen The length of the command data in bytes. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout. + * - LL_ERR_INVD_PARAM: Invalid parameter. + */ +static int32_t W25QXX_WriteCmd(const stc_w25qxx_ll_t *pstcW25qxxLL, \ + uint8_t u8Cmd, const uint8_t *pu8CmdData, uint32_t u32CmdDataLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcW25qxxLL == NULL) { + return i32Ret; + } + + if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Inactive != NULL)) { + pstcW25qxxLL->Active(); + i32Ret = pstcW25qxxLL->Trans(&u8Cmd, 1U); + if ((i32Ret == LL_OK) && (pu8CmdData != NULL) && (u32CmdDataLen > 0UL)) { + i32Ret = pstcW25qxxLL->Trans(pu8CmdData, u32CmdDataLen); + } + pstcW25qxxLL->Inactive(); + } + + return i32Ret; +} + +/** + * @brief W25QXX read command. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u8Cmd Command of W25QXX. + * @param [in] pu8CmdData Pointer to a buffer that contains the data following the command. + * @param [in] u32CmdDataLen The length of the command data in bytes. + * @param [in] pu8Info The information of the command. + * @param [in] u8InfoLen The length of the information. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout. + * - LL_ERR_INVD_PARAM: Invalid parameter. + */ +static int32_t W25QXX_ReadCmd(const stc_w25qxx_ll_t *pstcW25qxxLL, \ + uint8_t u8Cmd, uint8_t *pu8CmdData, uint32_t u32CmdDataLen, + uint8_t *pu8Info, uint8_t u8InfoLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcW25qxxLL == NULL) { + return i32Ret; + } + + if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Receive != NULL) && + (pstcW25qxxLL->Inactive != NULL)) { + pstcW25qxxLL->Active(); + i32Ret = pstcW25qxxLL->Trans(&u8Cmd, 1U); + if ((i32Ret == LL_OK) && (pu8CmdData != NULL) && (u32CmdDataLen > 0UL)) { + i32Ret = pstcW25qxxLL->Trans(pu8CmdData, u32CmdDataLen); + } + if ((i32Ret == LL_OK) && (pu8Info != NULL) && (u8InfoLen > 0UL)) { + i32Ret = pstcW25qxxLL->Receive(pu8Info, (uint32_t)u8InfoLen); + } + pstcW25qxxLL->Inactive(); + } + + return i32Ret; +} + +/** + * @brief W25QXX write data. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u8Cmd Command of W25QXX. + * @param [in] u32Addr The start address of the data to be written. + * @param [in] pu8Data The data to be written. + * @param [in] u32DataLen The length of the data in bytes. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout. + * - LL_ERR_INVD_PARAM: Invalid parameter. + */ +static int32_t W25QXX_Wt(const stc_w25qxx_ll_t *pstcW25qxxLL, \ + uint8_t u8Cmd, uint32_t u32Addr, \ + const uint8_t *pu8Data, uint32_t u32DataLen) +{ + uint8_t au8Cmd[4U]; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcW25qxxLL == NULL) { + return i32Ret; + } + + if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Inactive != NULL)) { + LOAD_CMD(au8Cmd, u8Cmd, u32Addr); + pstcW25qxxLL->Active(); + i32Ret = pstcW25qxxLL->Trans(au8Cmd, 4U); + if ((i32Ret == LL_OK) && (pu8Data != NULL) && (u32DataLen > 0UL)) { + i32Ret = pstcW25qxxLL->Trans(pu8Data, u32DataLen); + } + pstcW25qxxLL->Inactive(); + } + + return i32Ret; +} + +/** + * @brief W25QXX read data. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u8Cmd Command of W25QXX. + * @param [in] u32Addr The start address of the data to be written. + * @param [in] pu8Data The data to be stored. + * @param [in] u32DataLen The length of the data in bytes. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout. + * - LL_ERR_INVD_PARAM: Invalid parameter. + */ +static int32_t W25QXX_Rd(const stc_w25qxx_ll_t *pstcW25qxxLL, \ + uint8_t u8Cmd, uint32_t u32Addr, \ + uint8_t *pu8Data, uint32_t u32DataLen) +{ + uint8_t au8Cmd[4U]; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcW25qxxLL == NULL) { + return i32Ret; + } + + if ((pstcW25qxxLL->Active != NULL) && (pstcW25qxxLL->Trans != NULL) && (pstcW25qxxLL->Receive != NULL) && + (pstcW25qxxLL->Inactive != NULL)) { + LOAD_CMD(au8Cmd, u8Cmd, u32Addr); + pstcW25qxxLL->Active(); + i32Ret = pstcW25qxxLL->Trans(au8Cmd, 4U); + if (i32Ret == LL_OK) { + i32Ret = pstcW25qxxLL->Receive(pu8Data, u32DataLen); + } + pstcW25qxxLL->Inactive(); + } + + return i32Ret; +} + +/** + * @brief W25QXX Write enable. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +static int32_t W25QXX_WriteEnable(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + return W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_WRITE_ENABLE, NULL, 0U); +} + +/** + * @brief W25QXX Write disable. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +static int32_t W25QXX_WriteDisable(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + return W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_WRITE_DISABLE, NULL, 0U); +} + +/** + * @brief Wait for processing done. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +static int32_t W25QXX_WaitProcessDone(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + uint8_t u8Status; + int32_t i32Ret = LL_ERR_TIMEOUT; + volatile uint32_t u32Timecount = W25QXX_TIMEOUT; + + while (u32Timecount-- != 0UL) { + i32Ret = W25QXX_ReadStatus(pstcW25qxxLL, W25QXX_READ_STATUS_REGISTER_1, &u8Status); + if ((i32Ret == LL_OK) && ((u8Status & W25QXX_FLAG_BUSY) == 0U)) { + break; + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup W25QXX_Global_Functions W25QXX Global Functions + * @{ + */ +/** + * @brief Initializes W25QXX. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t W25QXX_Init(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->Init != NULL)) { + pstcW25qxxLL->Init(); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize W25QXX. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t W25QXX_DeInit(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->DeInit != NULL)) { + pstcW25qxxLL->DeInit(); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Read manufacturer device ID. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [out] pu16ID Pointer to an address to store the device ID. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +int32_t W25QXX_GetManDeviceId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint16_t *pu16ID) +{ + uint8_t au8TempId[2U]; + uint8_t au8Dummy[3U] = {0U}; + uint16_t u16ManID; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pu16ID != NULL)) { + i32Ret = W25QXX_ReadCmd(pstcW25qxxLL, W25QXX_MANUFACTURER_DEVICE_ID, au8Dummy, 3U, au8TempId, 2U); + if (i32Ret == LL_OK) { + u16ManID = (uint16_t)au8TempId[0U] << 8U; + u16ManID |= au8TempId[1U]; + *pu16ID = u16ManID; + } + } + + return i32Ret; +} + +/** + * @brief Read unique ID. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [out] pu8UniqueId Pointer to a buffer the 64 bit unique ID to be stored. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +int32_t W25QXX_GetUniqueId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t *pu8UniqueId) +{ + uint8_t au8Dummy[4U] = {0U}; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pu8UniqueId != NULL)) { + i32Ret = W25QXX_ReadCmd(pstcW25qxxLL, W25QXX_READ_UNIQUE_ID, au8Dummy, 4U, pu8UniqueId, 8U); + } + + return i32Ret; +} + +/** + * @brief Read status register. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u8SrRdCmd Command of reading status register. + * @arg W25QXX_READ_STATUS_REGISTER_1: Read status register 1. + * @arg W25QXX_READ_STATUS_REGISTER_2: Read status register 2. + * @arg W25QXX_READ_STATUS_REGISTER_3: Read status register 3. + * @param [out] pu8Status Pointer to an address the status value to be stored. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +int32_t W25QXX_ReadStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrRdCmd, uint8_t *pu8Status) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pu8Status != NULL)) { + i32Ret = W25QXX_ReadCmd(pstcW25qxxLL, u8SrRdCmd, NULL, 0U, pu8Status, 1U); + } + + return i32Ret; +} + +/** + * @brief Write status register. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u8SrWtCmd Command of writting status register. + * @arg W25QXX_WRITE_STATUS_REGISTER_1: Write status register 1. + * @arg W25QXX_WRITE_STATUS_REGISTER_2: Write status register 2. + * @arg W25QXX_WRITE_STATUS_REGISTER_3: Write status register 3. + * @param [in] u8Value 8bit value of the specified status register. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +int32_t W25QXX_WriteStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrWtCmd, uint8_t u8Value) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcW25qxxLL != NULL) { + i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, u8SrWtCmd, &u8Value, 1U); + } + + return i32Ret; +} + +/** + * @brief Power down. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +int32_t W25QXX_PowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->Delay != NULL)) { + i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_POWER_DOWN, NULL, 0U); + if (i32Ret == LL_OK) { + pstcW25qxxLL->Delay(1U); + } + } + + return i32Ret; +} + +/** + * @brief Release power down. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +int32_t W25QXX_ReleasePowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pstcW25qxxLL->Delay != NULL)) { + i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_RELEASE_POWER_DOWN_ID, NULL, 0U); + if (i32Ret == LL_OK) { + pstcW25qxxLL->Delay(1U); + } + } + + return i32Ret; +} + +/** + * @brief Ease chip. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +int32_t W25QXX_EraseChip(const stc_w25qxx_ll_t *pstcW25qxxLL) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcW25qxxLL != NULL) { + i32Ret = W25QXX_WriteEnable(pstcW25qxxLL); + if (i32Ret == LL_OK) { + i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL); + } + if (i32Ret == LL_OK) { + i32Ret = W25QXX_WriteCmd(pstcW25qxxLL, W25QXX_CHIP_ERASE, NULL, 0U); + } + if (i32Ret == LL_OK) { + i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL); + } + } + + return i32Ret; +} + +/** + * @brief Ease sector. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u32Addr Any address of the specified sector. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +int32_t W25QXX_EraseSector(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcW25qxxLL != NULL) { + i32Ret = W25QXX_WriteEnable(pstcW25qxxLL); + if (i32Ret == LL_OK) { + i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL); + } + if (i32Ret == LL_OK) { + i32Ret = W25QXX_Wt(pstcW25qxxLL, W25QXX_SECTOR_ERASE, u32Addr, NULL, 0U); + } + if (i32Ret == LL_OK) { + i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL); + } + if (i32Ret == LL_OK) { + i32Ret = W25QXX_WriteDisable(pstcW25qxxLL); + } + } + + return i32Ret; +} + +/** + * @brief W25QXX read data. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u32Addr The start address of the data to be read. + * @param [in] pu8ReadBuf The pointer to the buffer contains the data to be stored. + * @param [in] u32NumByteToRead Buffer size in bytes. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout. + */ +int32_t W25QXX_ReadData(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, \ + uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pu8ReadBuf != NULL) && (u32NumByteToRead != 0UL)) { + i32Ret = W25QXX_Rd(pstcW25qxxLL, W25QXX_READ_DATA, u32Addr, pu8ReadBuf, u32NumByteToRead); + } + + return i32Ret; +} + +/** + * @brief W25QXX page program. + * @param [in] pstcW25qxxLL Pointer to a @ref stc_w25qxx_ll_t structure. + * @param [in] u32Addr Start address of the page. + * @param [in] pu8Data Pointer to a buffer that contains the data to be written. + * @param [in] u32NumByteToProgram Size of the buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +int32_t W25QXX_PageProgram(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, \ + const uint8_t *pu8Data, uint32_t u32NumByteToProgram) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pstcW25qxxLL != NULL) && (pu8Data != NULL) && (u32NumByteToProgram != 0UL)) { + i32Ret = W25QXX_WriteEnable(pstcW25qxxLL); + if (i32Ret == LL_OK) { + i32Ret = W25QXX_Wt(pstcW25qxxLL, W25QXX_PAGE_PROGRAM, u32Addr, pu8Data, u32NumByteToProgram); + } + if (i32Ret == LL_OK) { + i32Ret = W25QXX_WaitProcessDone(pstcW25qxxLL); + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.h new file mode 100644 index 0000000000..850b9e358d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/components/w25qxx/w25qxx.h @@ -0,0 +1,199 @@ +/** + ******************************************************************************* + * @file w25qxx.h + * @brief This file provides firmware functions to W25QXX group spi flash. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __W25QXX_H__ +#define __W25QXX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup Components + * @{ + */ + +/** + * @addtogroup W25QXX + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup W25QXX_Global_Types W25QXX Global Types + * @{ + */ + +/** + * @brief W25QXX low layer structure definition + */ +typedef struct { + void (*Delay)(uint32_t); + void (*Init)(void); + void (*DeInit)(void); + void (*Active)(void); + void (*Inactive)(void); + int32_t (*Trans)(const uint8_t *, uint32_t); + int32_t (*Receive)(uint8_t *, uint32_t); +} stc_w25qxx_ll_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup W25QXX_Global_Macros W25QXX Global Macros + * @{ + */ + +/** + * @defgroup W25QXX_ID W25QXX ID + * @{ + */ +#define W25Q80 (0xEF13U) +#define W25Q16 (0xEF14U) +#define W25Q32 (0xEF15U) +#define W25Q64 (0xEF16U) +#define W25Q128 (0xEF17U) +/** + * @} + */ + +/** + * @defgroup W25QXX_Command W25QXX Command + * @{ + */ +#define W25QXX_WRITE_ENABLE (0x06U) +#define W25QXX_VOLATILE_SR_WRITE_ENABLE (0x50U) +#define W25QXX_WRITE_DISABLE (0x04U) +#define W25QXX_RELEASE_POWER_DOWN_ID (0xABU) +#define W25QXX_MANUFACTURER_DEVICE_ID (0x90U) +#define W25QXX_JEDEC_ID (0x9FU) +#define W25QXX_READ_UNIQUE_ID (0x4BU) +#define W25QXX_READ_DATA (0x03U) +#define W25QXX_FAST_READ (0x0BU) +#define W25QXX_PAGE_PROGRAM (0x02U) +#define W25QXX_SECTOR_ERASE (0x20U) +#define W25QXX_BLOCK_ERASE_32KB (0x52U) +#define W25QXX_BLOCK_ERASE_64KB (0xD8U) +#define W25QXX_CHIP_ERASE (0xC7U) +#define W25QXX_READ_STATUS_REGISTER_1 (0x05U) +#define W25QXX_WRITE_STATUS_REGISTER_1 (0x01U) +#define W25QXX_READ_STATUS_REGISTER_2 (0x35U) +#define W25QXX_WRITE_STATUS_REGISTER_2 (0x31U) +#define W25QXX_READ_STATUS_REGISTER_3 (0x15U) +#define W25QXX_WRITE_STATUS_REGISTER_3 (0x11U) +#define W25QXX_READ_SFDP_REGISTER (0x5AU) +#define W25QXX_ERASE_SECURITY_REGISTER (0x44U) +#define W25QXX_PROGRAM_SECURITY_REGISTER (0x42U) +#define W25QXX_READ_SECURITY_REGISTER (0x48U) +#define W25QXX_GLOBAL_BLOCK_LOCK (0x7EU) +#define W25QXX_GLOBAL_BLOCK_UNLOCK (0x98U) +#define W25QXX_READ_BLOCK_LOCK (0x3DU) +#define W25QXX_INDIVIDUAL_BLOCK_LOCK (0x36U) +#define W25QXX_INDIVIDUAL_BLOCK_UNLOCK (0x39U) +#define W25QXX_ERASE_PROGRAM_SUSPEND (0x75U) +#define W25QXX_ERASE_PROGRAM_RESUME (0x7AU) +#define W25QXX_POWER_DOWN (0xB9U) +#define W25QXX_ENABLE_RESET (0x66U) +#define W25QXX_RESET_DEVICE (0x99U) +/** + * @} + */ + +/** + * @defgroup W25QXX_Timeout_Value W25QXX Timeout Value + * @{ + */ +#define W25QXX_TIMEOUT (100000UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup W25QXX_Global_Functions W25QXX Global Functions + * @{ + */ + +int32_t W25QXX_Init(const stc_w25qxx_ll_t *pstcW25qxxLL); +int32_t W25QXX_DeInit(const stc_w25qxx_ll_t *pstcW25qxxLL); +int32_t W25QXX_GetManDeviceId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint16_t *pu16ID); +int32_t W25QXX_GetUniqueId(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t *pu8UniqueId); +int32_t W25QXX_ReadStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrRdCmd, uint8_t *pu8Status); +int32_t W25QXX_WriteStatus(const stc_w25qxx_ll_t *pstcW25qxxLL, uint8_t u8SrWtCmd, uint8_t u8Value); +int32_t W25QXX_PowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL); +int32_t W25QXX_ReleasePowerDown(const stc_w25qxx_ll_t *pstcW25qxxLL); +int32_t W25QXX_EraseChip(const stc_w25qxx_ll_t *pstcW25qxxLL); +int32_t W25QXX_EraseSector(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr); +int32_t W25QXX_ReadData(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32NumByteToRead); +int32_t W25QXX_PageProgram(const stc_w25qxx_ll_t *pstcW25qxxLL, uint32_t u32Addr, const uint8_t *pu8Data, uint32_t u32NumByteToProgram); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __W25QXX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.c new file mode 100644 index 0000000000..dab7b56085 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.c @@ -0,0 +1,672 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80.c + * @brief This file provides firmware functions for EV_HC32F448_LQFP80 BSP + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Add API BSP_XTAL32_Init() + Optimize function BSP_I2C_Init() + Update EXCLK clock frequency: 100MHz -> 50MHZ in function BSP_CLK_Init() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ev_hc32f448_lqfp80.h" + +/** + * @defgroup BSP BSP + * @{ + */ + +/** + * @defgroup EV_HC32F448_LQFP80 HC32F448_LQFP80_EVB + * @{ + */ + +#if (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/** + * @defgroup BSP_Local_Types BSP Local Types + * @{ + */ +typedef struct { + uint8_t port; + uint16_t pin; + uint16_t func; +} BSP_Port_Pin; + +typedef struct { + uint8_t port; + uint16_t pin; + uint32_t ch; + IRQn_Type irq; +} BSP_KeyIn_Config; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +#if (DDL_ON == LL_KEYSCAN_ENABLE) +/** + * @addtogroup BSP_Local_Functions + * @{ + */ +static void BSP_KEY_ROW_Init(void); +static void BSP_KEY_COL_Init(void); +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** +* @defgroup BSP_Local_Variables BSP Local Variables +* @{ +*/ +static const BSP_Port_Pin BSP_KEYOUT_PORT_PIN[BSP_KEY_COL_NUM] = { + {BSP_KEYOUT3_PORT, BSP_KEYOUT3_PIN, BSP_KEYOUT3_FUNC}, + {BSP_KEYOUT7_PORT, BSP_KEYOUT7_PIN, BSP_KEYOUT7_FUNC}, +}; + +static const BSP_KeyIn_Config BSP_KEYIN_PORT_PIN[BSP_KEY_ROW_NUM + BSP_KEY_INDEPENDENT_NUM] = { + {BSP_KEYIN0_PORT, BSP_KEYIN0_PIN, BSP_KEY_ROW0_EXTINT, BSP_KEY_ROW0_IRQn}, + {BSP_KEYIN1_PORT, BSP_KEYIN1_PIN, BSP_KEY_ROW1_EXTINT, BSP_KEY_ROW1_IRQn}, + {BSP_KEY_KEY5_PORT, BSP_KEY_KEY5_PIN, BSP_KEY_KEY5_EXTINT, BSP_KEY_KEY5_IRQn}, +}; + +static uint32_t m_u32GlobalKey = 0UL; +/** + * @} + */ +#endif +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_Global_Functions BSP Global Functions + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) +/** + * @brief BSP I2C initialize + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2Cx: I2C instance register base. + * @retval int32_t: + * - LL_OK: Configure success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t BSP_I2C_Init(CM_I2C_TypeDef *I2Cx) +{ + int32_t i32Ret; + float32_t fErr; + stc_i2c_init_t stcI2cInit; + uint32_t I2cSrcClk; + uint32_t I2cClkDiv; + uint32_t I2cClkDivReg; + + I2cSrcClk = I2C_SRC_CLK; + I2cClkDiv = I2cSrcClk / BSP_I2C_BAUDRATE / I2C_WIDTH_MAX_IMME; + for (I2cClkDivReg = I2C_CLK_DIV1; I2cClkDivReg <= I2C_CLK_DIV128; I2cClkDivReg++) { + if (I2cClkDiv < (1UL << I2cClkDivReg)) { + break; + } + } + + (void)I2C_DeInit(I2Cx); + (void)I2C_StructInit(&stcI2cInit); + stcI2cInit.u32Baudrate = BSP_I2C_BAUDRATE; + stcI2cInit.u32SclTime = (uint32_t)((uint64_t)180UL * ((uint64_t)I2cSrcClk / ((uint64_t)1UL << I2cClkDivReg)) / (uint64_t)1000000000UL); /* SCL time is about 180nS in EVB board */ + stcI2cInit.u32ClockDiv = I2cClkDivReg; + i32Ret = I2C_Init(I2Cx, &stcI2cInit, &fErr); + + if (LL_OK == i32Ret) { + I2C_BusWaitCmd(I2Cx, ENABLE); + I2C_Cmd(I2Cx, ENABLE); + } + + return i32Ret; +} + +/** + * @brief BSP I2C De-initialize + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2Cx: I2C instance register base. + * @retval None + */ +void BSP_I2C_DeInit(CM_I2C_TypeDef *I2Cx) +{ + (void)I2C_DeInit(I2Cx); +} + +/** + * @brief BSP I2C write. + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2Cx: I2C instance register base. + * @param [in] u16DevAddr: Device address. + * @param [in] pu8Reg: Pointer to the register address or memory address. + * @param [in] u8RegLen: Length of register address or memory address. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be write. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + */ +int32_t BSP_I2C_Write(CM_I2C_TypeDef *I2Cx, uint16_t u16DevAddr, const uint8_t *pu8Reg, uint8_t u8RegLen, const uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret; + + I2C_SWResetCmd(I2Cx, ENABLE); + I2C_SWResetCmd(I2Cx, DISABLE); + i32Ret = I2C_Start(I2Cx, BSP_I2C_TIMEOUT); + if (LL_OK == i32Ret) { + i32Ret = I2C_TransAddr(I2Cx, u16DevAddr, I2C_DIR_TX, BSP_I2C_TIMEOUT); + + if (LL_OK == i32Ret) { + i32Ret = I2C_TransData(I2Cx, pu8Reg, u8RegLen, BSP_I2C_TIMEOUT); + if (LL_OK == i32Ret) { + i32Ret = I2C_TransData(I2Cx, pu8Buf, u32Len, BSP_I2C_TIMEOUT); + } + } + } + (void)I2C_Stop(I2Cx, BSP_I2C_TIMEOUT); + return i32Ret; +} + +/** + * @brief BSP I2C read. + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2Cx: I2C instance register base. + * @param [in] u16DevAddr: Device address. + * @param [in] pu8Reg: Pointer to the register address or memory address. + * @param [in] u8RegLen: Length of register address or memory address. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be read. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + */ +int32_t BSP_I2C_Read(CM_I2C_TypeDef *I2Cx, uint16_t u16DevAddr, const uint8_t *pu8Reg, uint8_t u8RegLen, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret; + I2C_SWResetCmd(I2Cx, ENABLE); + I2C_SWResetCmd(I2Cx, DISABLE); + i32Ret = I2C_Start(I2Cx, BSP_I2C_TIMEOUT); + if (LL_OK == i32Ret) { + i32Ret = I2C_TransAddr(I2Cx, u16DevAddr, I2C_DIR_TX, BSP_I2C_TIMEOUT); + + if (LL_OK == i32Ret) { + i32Ret = I2C_TransData(I2Cx, pu8Reg, u8RegLen, BSP_I2C_TIMEOUT); + if (LL_OK == i32Ret) { + i32Ret = I2C_Restart(I2Cx, BSP_I2C_TIMEOUT); + if (LL_OK == i32Ret) { + if (1UL == u32Len) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + + i32Ret = I2C_TransAddr(I2Cx, u16DevAddr, I2C_DIR_RX, BSP_I2C_TIMEOUT); + if (LL_OK == i32Ret) { + i32Ret = I2C_MasterReceiveDataAndStop(I2Cx, pu8Buf, u32Len, BSP_I2C_TIMEOUT); + } + I2C_AckConfig(I2Cx, I2C_ACK); + } + } + } + } + + if (LL_OK != i32Ret) { + (void)I2C_Stop(I2Cx, BSP_I2C_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief BSP 24CXX status get. + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2Cx: I2C instance register base. + * @param [in] u16DevAddr: Device address. + * @retval int32_t: + * - LL_OK: Idle + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + */ +int32_t BSP_I2C_GetDevStatus(CM_I2C_TypeDef *I2Cx, uint16_t u16DevAddr) +{ + int32_t i32Ret; + + i32Ret = I2C_Start(I2Cx, BSP_I2C_TIMEOUT); + if (LL_OK == i32Ret) { + i32Ret = I2C_TransAddr(I2Cx, u16DevAddr, I2C_DIR_TX, BSP_I2C_TIMEOUT); + + if (LL_OK == i32Ret) { + if (SET == I2C_GetStatus(I2Cx, I2C_FLAG_ACKR)) { + i32Ret = LL_ERR; + } + } + } + (void)I2C_Stop(I2Cx, BSP_I2C_TIMEOUT); + return i32Ret; +} +#endif /* LL_I2C_ENABLE */ + +/** + * @brief BSP clock initialize. + * SET board system clock to PLLH@200MHz + * Flash: 3 wait + * SRAM_H: 0 wait + * SRAM_B: 1 wait + * PCLK0: 200MHz + * PCLK1: 100MHz + * PCLK2: 50MHz + * PCLK3: 50MHz + * PCLK4: 100MHz + * EXCLK: 50MHz + * HCLK: 200MHz + * @param None + * @retval None + */ +__WEAKDEF void BSP_CLK_Init(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; + + /* PCLK0, HCLK Max 200MHz */ + /* PCLK1, PCLK4 Max 100MHz */ + /* PCLK2, EXCLK Max 60MHz */ + /* PCLK3 Max 50MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 | + CLK_HCLK_DIV1)); + + GPIO_AnalogCmd(BSP_XTAL_PORT, BSP_XTAL_IN_PIN | BSP_XTAL_OUT_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*100 = 800MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* 3 cycles for 150 ~ 200MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE3); + /* 3 cycles for 150 ~ 200MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT3); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); +} + +/** + * @brief BSP Xtal32 initialize. + * @param None + * @retval int32_t: + * - LL_OK: XTAL32 enable successfully + * - LL_ERR_TIMEOUT: XTAL32 enable timeout. + */ +__WEAKDEF int32_t BSP_XTAL32_Init(void) +{ + stc_clock_xtal32_init_t stcXtal32Init; + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = HCLK_VALUE / 5UL; + + if (CLK_XTAL32_ON == READ_REG8(CM_CMU->XTAL32CR)) { + /* Disable xtal32 */ + (void)CLK_Xtal32Cmd(DISABLE); + /* Wait 5 * xtal32 cycle */ + DDL_DelayUS(160U); + } + + /* Xtal32 config */ + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_MID; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_ALL_MD; + GPIO_AnalogCmd(BSP_XTAL32_PORT, BSP_XTAL32_IN_PIN | BSP_XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32Init(&stcXtal32Init); + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(&stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(ENABLE); + for (;;) { + if (SET == FCM_GetStatus(FCM_FLAG_END)) { + FCM_ClearStatus(FCM_FLAG_END); + if ((SET == FCM_GetStatus(FCM_FLAG_ERR)) || (SET == FCM_GetStatus(FCM_FLAG_OVF))) { + FCM_ClearStatus(FCM_FLAG_ERR | FCM_FLAG_OVF); + } else { + (void)FCM_DeInit(); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + return LL_OK; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) { + (void)FCM_DeInit(); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + return LL_ERR_TIMEOUT; + } + } +} + +#if (LL_PRINT_ENABLE == DDL_ON) +/** + * @brief BSP printf device, clock and port pre-initialize. + * @param [in] vpDevice Pointer to print device + * @param [in] u32Baudrate Print device communication baudrate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR: Initialize unsuccessfully. + * - LL_ERR_INVD_PARAM: The u32Baudrate value is 0. + */ +int32_t BSP_PRINTF_Preinit(void *vpDevice, uint32_t u32Baudrate) +{ + uint32_t i; + float32_t f32Error; + const uint32_t au32Div[] = {USART_CLK_DIV1, USART_CLK_DIV4, USART_CLK_DIV16, USART_CLK_DIV64, + USART_CLK_DIV128, USART_CLK_DIV256, USART_CLK_DIV512, USART_CLK_DIV1024 + }; + stc_usart_uart_init_t stcUartInit; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + (void)vpDevice; + + if (0UL != u32Baudrate) { + /* Set TX port function */ + GPIO_SetFunc(BSP_PRINTF_PORT, BSP_PRINTF_PIN, BSP_PRINTF_PORT_FUNC); + + /* Enable clock */ + FCG_Fcg3PeriphClockCmd(BSP_PRINTF_DEVICE_FCG, ENABLE); + + /* Configure UART */ + (void)USART_UART_StructInit(&stcUartInit); + stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + (void)USART_UART_Init(BSP_PRINTF_DEVICE, &stcUartInit, NULL); + + for (i = 0UL; i < ARRAY_SZ(au32Div); i++) { + USART_SetClockDiv(BSP_PRINTF_DEVICE, au32Div[i]); + i32Ret = USART_SetBaudrate(BSP_PRINTF_DEVICE, u32Baudrate, &f32Error); + if ((LL_OK == i32Ret) && \ + ((-BSP_PRINTF_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= BSP_PRINTF_BAUDRATE_ERR_MAX))) { + USART_FuncCmd(BSP_PRINTF_DEVICE, USART_TX, ENABLE); + break; + } else { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} +#endif + +/** + * @brief BSP key initialize + * @param None + * @retval None + */ +void BSP_KEY_Init(void) +{ + uint8_t i; + + BSP_KEY_ROW_Init(); + BSP_KEY_COL_Init(); + /* Clear all KEYIN interrupt flag before enable */ + for (i = 0U; i < BSP_KEY_ROW_NUM + BSP_KEY_INDEPENDENT_NUM; i++) { + EXTINT_ClearExtIntStatus(BSP_KEYIN_PORT_PIN[i].ch); + } + KEYSCAN_Cmd(ENABLE); +} + +/** + * @brief Get BSP key status + * @param [in] u32Key chose one macro from below + * @arg BSP_KEY_1 + * @arg BSP_KEY_2 + * @arg BSP_KEY_3 + * @arg BSP_KEY_4 + * @arg BSP_KEY_5 + * @retval An @ref en_flag_status_t enumeration type value. + * - SET, Key pressed. + * - RESET, Key released. + */ +en_flag_status_t BSP_KEY_GetStatus(uint32_t u32Key) +{ + en_flag_status_t enStatus = RESET; + if (0UL != (m_u32GlobalKey & u32Key)) { + enStatus = SET; + m_u32GlobalKey &= ~u32Key; + } else { + } + return enStatus; +} + +/** + * @} + */ + +/** + * @defgroup BSP_Local_Functions BSP Local Functions + * @{ + */ + +#if (DDL_ON == BSP_INT_KEY_ENABLE) +/** + * @brief EXTINT Ch.5 as BSP Key 5 callback function + * @param None + * @retval None + */ +void EXTINT06_SWINT22_Handler(void) +{ + m_u32GlobalKey |= BSP_KEY_5; + EXTINT_ClearExtIntStatus(BSP_KEY_KEY5_EXTINT); + BSP_KEY_KEY5_IrqCallback(); + + __DSB(); /* Arm Errata 838869 */ +} + +/** + * @brief User callback function for BSP KEY5. + * @param None + * @retval None + */ +__WEAKDEF void BSP_KEY_KEY5_IrqCallback(void) +{ + /* This function should be implemented by the user application. */ +} +#endif /* BSP_EV_HC32F448_LQFP80 */ + +/** + * @brief EXTINT Ch.0 as BSP Key row 0 callback function + * @param None + * @retval None + */ +void EXTINT00_SWINT16_Handler(void) +{ + uint8_t u8Idx = (uint8_t)KEYSCAN_GetKeyoutIdx(); + if (SET == EXTINT_GetExtIntStatus(BSP_KEYIN_PORT_PIN[0].ch)) { + for (;;) { + if (PIN_RESET == GPIO_ReadInputPins(BSP_KEYIN_PORT_PIN[0].port, BSP_KEYIN_PORT_PIN[0].pin)) { + m_u32GlobalKey |= (0x01UL) << u8Idx; + } else { + /* clear int request flag after KEY released */ + EXTINT_ClearExtIntStatus(BSP_KEYIN_PORT_PIN[0].ch); + break; + } + } + } + + __DSB(); /* Arm Errata 838869 */ +} + +/** + * @brief EXTINT Ch.1 as BSP Key row 1 callback function + * @param None + * @retval None + */ +void EXTINT01_SWINT17_Handler(void) +{ + uint8_t u8Idx = (uint8_t)KEYSCAN_GetKeyoutIdx(); + if (SET == EXTINT_GetExtIntStatus(BSP_KEYIN_PORT_PIN[1].ch)) { + for (;;) { + if (PIN_RESET == GPIO_ReadInputPins(BSP_KEYIN_PORT_PIN[1].port, BSP_KEYIN_PORT_PIN[1].pin)) { + m_u32GlobalKey |= (0x100UL) << u8Idx; + } else { + /* clear int request flag after KEY released */ + EXTINT_ClearExtIntStatus(BSP_KEYIN_PORT_PIN[1].ch); + break; + } + } + } + + __DSB(); /* Arm Errata 838869 */ +} + +/** + * @brief BSP key row initialize + * @param None + * @retval None + */ +static void BSP_KEY_ROW_Init(void) +{ + uint8_t i; + stc_extint_init_t stcExtIntInit; + stc_gpio_init_t stcGpioInit; + + /* configuration structure initialization */ + (void)GPIO_StructInit(&stcGpioInit); + + /* GPIO config */ + stcGpioInit.u16ExtInt = PIN_EXTINT_ON; + stcGpioInit.u16PullUp = PIN_PU_ON; + for (i = 0U; i < BSP_KEY_ROW_NUM + BSP_KEY_INDEPENDENT_NUM; i++) { + (void)GPIO_Init(BSP_KEYIN_PORT_PIN[i].port, BSP_KEYIN_PORT_PIN[i].pin, &stcGpioInit); + } + + /* Extint config */ + (void)EXTINT_StructInit(&stcExtIntInit); + stcExtIntInit.u32Edge = EXTINT_TRIG_FALLING; + stcExtIntInit.u32FilterB = NMI_EXTINT_FILTER_B_ON; + stcExtIntInit.u32FilterBClock = NMI_EXTINT_FCLK_B_4US; + for (i = 0U; i < BSP_KEY_ROW_NUM + BSP_KEY_INDEPENDENT_NUM; i++) { + (void)EXTINT_Init(BSP_KEYIN_PORT_PIN[i].ch, &stcExtIntInit); + } + + /* IRQ sign-in */ + for (i = 0U; i < BSP_KEY_ROW_NUM + BSP_KEY_INDEPENDENT_NUM; i++) { + /* NVIC config */ + NVIC_ClearPendingIRQ(BSP_KEYIN_PORT_PIN[i].irq); + NVIC_SetPriority(BSP_KEYIN_PORT_PIN[i].irq, DDL_IRQ_PRIO_DEFAULT); + NVIC_EnableIRQ(BSP_KEYIN_PORT_PIN[i].irq); + } +} + +/** + * @brief BSP key column initialize + * @param None + * @retval None + */ +static void BSP_KEY_COL_Init(void) +{ + uint8_t i; + stc_gpio_init_t stcGpioInit; + stc_keyscan_init_t stcKeyscanInit; + + /* configuration structure initialization */ + (void)GPIO_StructInit(&stcGpioInit); + + /* Set corresponding pins to KEYSCAN function */ + for (i = 0U; i < BSP_KEY_COL_NUM; i++) { + (void)GPIO_Init(BSP_KEYOUT_PORT_PIN[i].port, BSP_KEYOUT_PORT_PIN[i].pin, &stcGpioInit); + GPIO_SetFunc(BSP_KEYOUT_PORT_PIN[i].port, BSP_KEYOUT_PORT_PIN[i].pin, BSP_KEYOUT_PORT_PIN[i].func); + } + /* enable KEYSCAN module source clock */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_KEY, ENABLE); + /* ENABLE LRC for scan clock */ + (void)CLK_LrcCmd(ENABLE); + + /* KEYSCAN config */ + (void)KEYSCAN_StructInit(&stcKeyscanInit); + stcKeyscanInit.u32HizCycle = KEYSCAN_HIZ_CYCLE_4; + stcKeyscanInit.u32LowCycle = KEYSCAN_LOW_CYCLE_512; + stcKeyscanInit.u32KeyClock = KEYSCAN_CLK_LRC; + stcKeyscanInit.u32KeyOut = BSP_KEYOUT_SELECT; + stcKeyscanInit.u32KeyIn = BSP_KEYIN_SELECT; + (void)KEYSCAN_Init(&stcKeyscanInit); +} + +/** + * @} + */ +#endif /* BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.h new file mode 100644 index 0000000000..2ca1d69d0d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80.h @@ -0,0 +1,249 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80.h + * @brief This file contains all the functions prototypes of the + * EV_HC32F448_LQFP80 BSP driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Add include file named hc32_ll_fcm.h and add declaration of BSP_XTAL32_Init() + Modify I2C baudrate: 400000 -> 100000 + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_H__ +#define __EV_HC32F448_LQFP80_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aos.h" +#include "hc32_ll_clk.h" +#include "hc32_ll_efm.h" +#include "hc32_ll_fcg.h" +#include "hc32_ll_fcm.h" +#include "hc32_ll_gpio.h" +#include "hc32_ll_i2c.h" +#include "hc32_ll_interrupts.h" +#include "hc32_ll_keyscan.h" +#include "hc32_ll_pwc.h" +#include "hc32_ll_spi.h" +#include "hc32_ll_sram.h" +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + + +#if (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup BSP_Global_Macros BSP Global Macros + * @{ + */ + +/** + * @defgroup BSP_I2C_Configuration BSP I2C Configuration + * @{ + */ +#define BSP_I2C_BAUDRATE (100000UL) +#define BSP_I2C_TIMEOUT (0x40000U) +/** + * @} + */ + +/** + * @defgroup BSP_KEY_Sel BSP Key definition + * @{ + */ +#define BSP_KEY_1 (0x0008UL) /*!< BSP KEY 1 */ +#define BSP_KEY_2 (0x0080UL) /*!< BSP KEY 2 */ +#define BSP_KEY_3 (0x0800UL) /*!< BSP KEY 3 */ +#define BSP_KEY_4 (0x8000UL) /*!< BSP KEY 4 */ +#define BSP_KEY_5 (0x10000UL) /*!< BSP KEY 5. Independent key. */ +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_KEY_Number EV_HC32F448_LQFP80 KEY Number + * @{ + */ +#define BSP_KEY_ROW_NUM (2U) +#define BSP_KEY_COL_NUM (2U) +#define BSP_KEY_INDEPENDENT_NUM (1U) +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_KEY_PortPin EV_HC32F448_LQFP80 KEY port/pin definition + * @{ + */ +#define BSP_KEY_KEY5_PORT (GPIO_PORT_B) +#define BSP_KEY_KEY5_PIN (GPIO_PIN_06) +#define BSP_KEY_KEY5_EXTINT (EXTINT_CH06) +#define BSP_KEY_KEY5_IRQn (EXTINT_PORT_EIRQ6_IRQn) +#define BSP_KEY_KEY5_WAKEUP (INTC_STOP_WKUP_EXTINT_CH6) +#define BSP_KEY_KEY5_EVT (EVT_SRC_PORT_EIRQ6) + +#define BSP_KEYOUT3_PORT (GPIO_PORT_C) +#define BSP_KEYOUT3_PIN (GPIO_PIN_06) +#define BSP_KEYOUT3_FUNC (GPIO_FUNC_8) + +#define BSP_KEYOUT7_PORT (GPIO_PORT_D) +#define BSP_KEYOUT7_PIN (GPIO_PIN_08) +#define BSP_KEYOUT7_FUNC (GPIO_FUNC_8) + +#define BSP_KEYIN0_PORT (GPIO_PORT_A) +#define BSP_KEYIN0_PIN (GPIO_PIN_00) +#define BSP_KEY_ROW0_EXTINT (EXTINT_CH00) +#define BSP_KEY_ROW0_IRQn (EXTINT_PORT_EIRQ0_IRQn) + +#define BSP_KEYIN1_PORT (GPIO_PORT_A) +#define BSP_KEYIN1_PIN (GPIO_PIN_01) +#define BSP_KEY_ROW1_EXTINT (EXTINT_CH01) +#define BSP_KEY_ROW1_IRQn (EXTINT_PORT_EIRQ1_IRQn) +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_KEYSCAN_CONFIG EV_HC32F448_LQFP80 KEYSCAN Configure definition + * @{ + */ +#define BSP_KEYOUT_SELECT (KEYSCAN_OUT_0T7) +#define BSP_KEYIN_SELECT (KEYSCAN_IN_0 | KEYSCAN_IN_1) +/** + * @} + */ + +/** + * @defgroup BSP_PRINT_CONFIG BSP PRINT Configure definition + * @{ + */ +#define BSP_PRINTF_DEVICE (CM_USART2) +#define BSP_PRINTF_DEVICE_FCG (FCG3_PERIPH_USART2) + +#define BSP_PRINTF_BAUDRATE (115200UL) +#define BSP_PRINTF_BAUDRATE_ERR_MAX (0.025F) + +#define BSP_PRINTF_PORT (GPIO_PORT_C) +#define BSP_PRINTF_PIN (GPIO_PIN_10) +#define BSP_PRINTF_PORT_FUNC (GPIO_FUNC_36) +/** + * @} + */ + +/** + * @defgroup BSP_XTAL_CONFIG BSP XTAL Configure definition + * @{ + */ +#define BSP_XTAL_PORT (GPIO_PORT_H) +#define BSP_XTAL_IN_PIN (GPIO_PIN_00) +#define BSP_XTAL_OUT_PIN (GPIO_PIN_01) +/** + * @} + */ + +/** + * @defgroup BSP_XTAL32_CONFIG BSP XTAL32 Configure definition + * @{ + */ +#define BSP_XTAL32_PORT (GPIO_PORT_C) +#define BSP_XTAL32_IN_PIN (GPIO_PIN_14) +#define BSP_XTAL32_OUT_PIN (GPIO_PIN_15) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup BSP_Global_Functions + * @{ + */ +int32_t BSP_XTAL32_Init(void); +void BSP_CLK_Init(void); + +void BSP_KEY_Init(void); +en_flag_status_t BSP_KEY_GetStatus(uint32_t u32Key); + +#if (LL_PRINT_ENABLE == DDL_ON) +int32_t BSP_PRINTF_Preinit(void *vpDevice, uint32_t u32Baudrate); +#endif + +#if (DDL_ON == BSP_INT_KEY_ENABLE) +/* User Callbacks: User has to implement these functions in his code if they're needed. */ +void BSP_KEY_KEY5_IrqCallback(void); +#endif + +#if (LL_I2C_ENABLE == DDL_ON) +int32_t BSP_I2C_Init(CM_I2C_TypeDef *I2Cx); +void BSP_I2C_DeInit(CM_I2C_TypeDef *I2Cx); +int32_t BSP_I2C_Write(CM_I2C_TypeDef *I2Cx, uint16_t u16DevAddr, const uint8_t *pu8Reg, uint8_t u8RegLen, const uint8_t *pu8Buf, uint32_t u32Len); +int32_t BSP_I2C_Read(CM_I2C_TypeDef *I2Cx, uint16_t u16DevAddr, const uint8_t *pu8Reg, uint8_t u8RegLen, uint8_t *pu8Buf, uint32_t u32Len); +int32_t BSP_I2C_GetDevStatus(CM_I2C_TypeDef *I2Cx, uint16_t u16DevAddr); +#endif /* LL_I2C_ENABLE */ + +/** + * @} + */ + +#endif /* BSP_EV_HC32F448_LQFP80 */ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_24cxx.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_24cxx.c new file mode 100644 index 0000000000..0996c9e475 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_24cxx.c @@ -0,0 +1,290 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_24cxx.c + * @brief This file provides firmware functions for EEPROM 24CXX. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ev_hc32f448_lqfp80_24cxx.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @defgroup EV_HC32F448_LQFP80_24CXX EV_HC32F448_LQFP80 24CXX + * @{ + */ + +#if ((BSP_24CXX_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_24CXX_Local_Functions + * @{ + */ +static int32_t BSP_24CXX_I2C_Init(void); +static void BSP_24CXX_I2C_DeInit(void); +static int32_t BSP_24CXX_I2C_WritePage(uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len); +static int32_t BSP_24CXX_I2C_Read(uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len); +static int32_t BSP_24CXX_I2C_GetStatus(void); +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_24CXX_Local_Variables EV_HC32F448_LQFP80 24CXX Local Variables + * @{ + */ +static stc_24cxx_ll_t m_stc24cxxLL = { + .u32PageSize = EE_24CXX_PAGE_SIZE, + .u32Capacity = EE_24CXX_CAPACITY, + .Delay = DDL_DelayUS, + .Init = BSP_24CXX_I2C_Init, + .DeInit = BSP_24CXX_I2C_DeInit, + .WritePage = BSP_24CXX_I2C_WritePage, + .Read = BSP_24CXX_I2C_Read, + .GetStatus = BSP_24CXX_I2C_GetStatus +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EV_HC32F448_LQFP80_24CXX_Local_Functions EV_HC32F448_LQFP80 24CXX Local Functions + * @{ + */ + +/** + * @brief Initializes I2C for 24CXX. + * @param None + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +static int32_t BSP_24CXX_I2C_Init(void) +{ + stc_gpio_init_t stcGpioInit; + /* Configuration I2C GPIO */ + (void)GPIO_StructInit(&stcGpioInit); + (void)GPIO_Init(BSP_24CXX_I2C_SCL_PORT, BSP_24CXX_I2C_SCL_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_24CXX_I2C_SDA_PORT, BSP_24CXX_I2C_SDA_PIN, &stcGpioInit); + GPIO_SetFunc(BSP_24CXX_I2C_SCL_PORT, BSP_24CXX_I2C_SCL_PIN, BSP_24CXX_I2C_SCL_FUNC); + GPIO_SetFunc(BSP_24CXX_I2C_SDA_PORT, BSP_24CXX_I2C_SDA_PIN, BSP_24CXX_I2C_SDA_FUNC); + /* Enable I2C Peripheral*/ + FCG_Fcg1PeriphClockCmd(BSP_24CXX_I2C_FCG, ENABLE); + return BSP_I2C_Init(BSP_24CXX_I2C_UNIT); +} + +/** + * @brief De-Initializes I2C for 24CXX. + * @param None + * @retval None + */ +static void BSP_24CXX_I2C_DeInit(void) +{ + /* Initialize I2C port*/ + GPIO_SetFunc(BSP_24CXX_I2C_SCL_PORT, BSP_24CXX_I2C_SCL_PIN, GPIO_FUNC_0); + GPIO_SetFunc(BSP_24CXX_I2C_SDA_PORT, BSP_24CXX_I2C_SDA_PIN, GPIO_FUNC_0); + (void)I2C_DeInit(BSP_24CXX_I2C_UNIT); +} + +/** + * @brief BSP 24CXX write page data. + * @param [in] u16Addr: The start address of the data to be write. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be write. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + * @note This function don't check if the data write is within one page + */ +static int32_t BSP_24CXX_I2C_WritePage(uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len) +{ + uint16_t u16MemAddrTemp; +#if (EE_24CXX_MEM_ADDR_LEN == 1U) + u16MemAddrTemp = u16Addr; +#else + u16MemAddrTemp = (uint16_t)((((uint32_t)u16Addr >> 8) & 0xFFUL) + (((uint32_t)u16Addr << 8) & 0xFF00UL)); +#endif + return BSP_I2C_Write(BSP_24CXX_I2C_UNIT, EE_24CXX_DEV_ADDR, (const uint8_t *)&u16MemAddrTemp, EE_24CXX_MEM_ADDR_LEN, pu8Buf, u32Len); +} + +/** + * @brief BSP 24CXX Read data. + * @param [in] u16Addr: The start address of the data to be read. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be read. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + */ +static int32_t BSP_24CXX_I2C_Read(uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + uint16_t u16MemAddrTemp; +#if (EE_24CXX_MEM_ADDR_LEN == 1U) + u16MemAddrTemp = u16Addr; +#else + u16MemAddrTemp = (uint16_t)((((uint32_t)u16Addr >> 8) & 0xFFUL) + (((uint32_t)u16Addr << 8) & 0xFF00UL)); +#endif + return BSP_I2C_Read(BSP_24CXX_I2C_UNIT, EE_24CXX_DEV_ADDR, (const uint8_t *)&u16MemAddrTemp, EE_24CXX_MEM_ADDR_LEN, pu8Buf, u32Len); +} + +/** + * @brief BSP 24CXX status get. + * @param None + * @retval int32_t: + * - LL_OK: Idle + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + */ +static int32_t BSP_24CXX_I2C_GetStatus(void) +{ + return BSP_I2C_GetDevStatus(BSP_24CXX_I2C_UNIT, EE_24CXX_DEV_ADDR); +} +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_24CXX_Global_Functions EV_HC32F448_LQFP80 24CXX Global Functions + * @{ + */ + +/** + * @brief BSP Initializes I2C for 24CXX. + * @param None + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t BSP_24CXX_Init(void) +{ + return EE_24CXX_Init(&m_stc24cxxLL); +} + +/** + * @brief BSP De-Initializes I2C for 24CXX. + * @param None + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t BSP_24CXX_DeInit(void) +{ + return EE_24CXX_DeInit(&m_stc24cxxLL); +} + +/** + * @brief BSP 24CXX write data. + * @param [in] u16Addr: The start address of the data to be write. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be write. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + */ +int32_t BSP_24CXX_Write(uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len) +{ + return EE_24CXX_Write(&m_stc24cxxLL, u16Addr, pu8Buf, u32Len); +} + +/** + * @brief 24CXX read data. + * @param [in] u16Addr: The start address of the data to be read. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be stored. + * @param [in] u32Len: Buffer size in byte. + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR: Receive NACK + * - LL_ERR_TIMEOUT: Timeout + * - LL_ERR_INVD_PARAM: pu8Buf is NULL + */ +int32_t BSP_24CXX_Read(uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + return EE_24CXX_Read(&m_stc24cxxLL, u16Addr, pu8Buf, u32Len); +} + +/** + * @brief 24CXX wait idle. + * @param None + * @retval int32_t: + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t BSP_24CXX_WaitIdle(void) +{ + return EE_24CXX_WaitIdle(&m_stc24cxxLL); +} + +/** + * @} + */ + +#endif /* (BSP_24CXX_ENABLE && BSP_EV_HC32F448_LQFP80) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_24cxx.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_24cxx.h new file mode 100644 index 0000000000..9b9c48eb69 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_24cxx.h @@ -0,0 +1,126 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_24cxx.h + * @brief This file contains all the functions prototypes of the + ev_hc32f448_lqfp80_24cxx driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_24CXX_H__ +#define __EV_HC32F448_LQFP80_24CXX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "24cxx.h" +#include "ev_hc32f448_lqfp80.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80_24CXX + * @{ + */ +#if ((BSP_24CXX_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_24CXX_Configure EV_HC32F448_LQFP80 24CXX Configure + * @{ + */ +/* I2C unit define */ +#define BSP_24CXX_I2C_UNIT (CM_I2C1) +#define BSP_24CXX_I2C_FCG (FCG1_PERIPH_I2C1) + +/* Define port and pin for SDA and SCL */ +#define BSP_24CXX_I2C_SCL_PORT (GPIO_PORT_E) +#define BSP_24CXX_I2C_SCL_PIN (GPIO_PIN_01) +#define BSP_24CXX_I2C_SDA_PORT (GPIO_PORT_E) +#define BSP_24CXX_I2C_SDA_PIN (GPIO_PIN_00) +#define BSP_24CXX_I2C_SCL_FUNC (GPIO_FUNC_49) +#define BSP_24CXX_I2C_SDA_FUNC (GPIO_FUNC_48) + +/* Define for EEPROM BL24C256 */ +#define EE_24CXX_DEV_ADDR (0x50U) +#define EE_24CXX_MEM_ADDR_LEN (2U) +#define EE_24CXX_PAGE_SIZE (64U) +#define EE_24CXX_CAPACITY (32000UL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_24CXX_Global_Functions + * @{ + */ +int32_t BSP_24CXX_Init(void); +int32_t BSP_24CXX_DeInit(void); +int32_t BSP_24CXX_Write(uint16_t u16Addr, const uint8_t *pu8Buf, uint32_t u32Len); +int32_t BSP_24CXX_Read(uint16_t u16Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t BSP_24CXX_WaitIdle(void); +/** + * @} + */ + +#endif /* (BSP_24CXX_ENABLE && BSP_EV_HC32F448_LQFP80) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_24CXX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_bsp.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_bsp.h new file mode 100644 index 0000000000..f50743f649 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_bsp.h @@ -0,0 +1,91 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_bsp.h + * @brief This file contains all the header file of the EV_HC32F448_LQFP80 + * BSP driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_BSP__ +#define __EV_HC32F448_LQFP80_BSP__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +/** + * @brief Include BSP board's header file + */ +#if (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX) +#include "ev_hc32f448_lqfp80.h" +#endif /* BSP_EV_HC32F448_LQFP80 */ + +/** + * @brief Include BSP device component's header file + */ +#if (BSP_24CXX_ENABLE == DDL_ON) +#include "ev_hc32f448_lqfp80_24cxx.h" +#endif /* BSP_24CXX_ENABLE */ + +#if (BSP_GT9XX_ENABLE == DDL_ON) +#include "ev_hc32f448_lqfp80_gt9xx.h" +#endif /* BSP_GT9XX_ENABLE */ + +#if (BSP_IS61LV6416_ENABLE == DDL_ON) +#include "ev_hc32f448_lqfp80_is61lv6416.h" +#endif /* BSP_IS61LV6416_ENABLE */ + +#if (BSP_NT35510_ENABLE == DDL_ON) +#include "ev_hc32f448_lqfp80_nt35510.h" +#endif /* BSP_NT35510_ENABLE */ + +#if (BSP_TCA9539_ENABLE == DDL_ON) +#include "ev_hc32f448_lqfp80_tca9539.h" +#endif /* BSP_TCA9539_ENABLE */ + +#if (BSP_W25QXX_ENABLE == DDL_ON) +#include "ev_hc32f448_lqfp80_w25qxx.h" +#endif /* BSP_W25QXX_ENABLE */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_BSP__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_gt9xx.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_gt9xx.c new file mode 100644 index 0000000000..b37ab4c535 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_gt9xx.c @@ -0,0 +1,261 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_gt9xx.c + * @brief This file provides firmware functions of the touch pad gt9xx driver + * library for the board EV_HC32F448_LQFP80. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "ev_hc32f448_lqfp80_gt9xx.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @defgroup EV_HC32F448_LQFP80_GT9XX EV_HC32F448_LQFP80 GT9XX + * @{ + */ + +#if ((BSP_GT9XX_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_GT9XX_Local_Functions + * @{ + */ +static void BSP_GT9XX_I2C_Init(void); +static void BSP_GT9XX_I2C_Read(const uint8_t au8Reg[], uint8_t u8RegLen, uint8_t *pu8Buf, uint32_t u32Len); +static void BSP_GT9XX_I2C_Write(const uint8_t au8Reg[], uint8_t u8RegLen, const uint8_t *pu8Buf, uint32_t u32Len); +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/** + * @defgroup EV_HC32F448_LQFP80_GT9XX_Local_Variables EV_HC32F448_LQFP80 GT9XX Local Variables + * @{ + */ +const static stc_gt9xx_ll_t m_stcGt9xxLL = { + .Init = BSP_GT9XX_I2C_Init, + .Read = BSP_GT9XX_I2C_Read, + .Write = BSP_GT9XX_I2C_Write, +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_GT9XX_Local_Functions EV_HC32F448_LQFP80 GT9XX Local Functions + * @{ + */ + +/** + * @brief Initializes I2C for GT9XX. + * @param None + * @retval None + */ +static void BSP_GT9XX_I2C_Init(void) +{ + stc_gpio_init_t stcGpioInit; + + /* Configuration I2C GPIO */ + (void)GPIO_StructInit(&stcGpioInit); + (void)GPIO_Init(BSP_GT9XX_I2C_SCL_PORT, BSP_GT9XX_I2C_SCL_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_GT9XX_I2C_SCL_PORT, BSP_GT9XX_I2C_SCL_PIN, &stcGpioInit); + + /* Initialize I2C port*/ + GPIO_SetFunc(BSP_GT9XX_I2C_SCL_PORT, BSP_GT9XX_I2C_SCL_PIN, BSP_GT9XX_I2C_SCL_FUNC); + GPIO_SetFunc(BSP_GT9XX_I2C_SDA_PORT, BSP_GT9XX_I2C_SDA_PIN, BSP_GT9XX_I2C_SDA_FUNC); + + /* Enable I2C Peripheral*/ + FCG_Fcg0PeriphClockCmd(BSP_GT9XX_I2C_FCG, ENABLE); + + (void)BSP_I2C_Init(BSP_GT9XX_I2C_UNIT); +} + +/** + * @brief BSP GT9XX I2C read. + * @param [in] pu8Reg: Pointer to the register address. + * @param [in] u8RegLen: Length of register address. + * @param [out] pu8Buf: The pointer to the buffer contains the data to be read. + * @param [in] u32Len: Buffer size in byte. + * @retval None + */ +static void BSP_GT9XX_I2C_Read(const uint8_t *pu8Reg, uint8_t u8RegLen, uint8_t *pu8Buf, uint32_t u32Len) +{ + (void)BSP_I2C_Read(BSP_GT9XX_I2C_UNIT, BSP_GT9XX_I2C_ADDR, pu8Reg, u8RegLen, pu8Buf, u32Len); +} + +/** + * @brief BSP GT9XX I2C write. + * @param [in] pu8Reg: Pointer to the register address. + * @param [in] u8RegLen: Length of register address. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be read. + * @param [in] u32Len: Buffer size in byte. + * @retval None + */ +static void BSP_GT9XX_I2C_Write(const uint8_t *pu8Reg, uint8_t u8RegLen, const uint8_t *pu8Buf, uint32_t u32Len) +{ + (void)BSP_I2C_Write(BSP_GT9XX_I2C_UNIT, BSP_GT9XX_I2C_ADDR, pu8Reg, u8RegLen, pu8Buf, u32Len); +} + +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_GT9XX_Global_Functions EV_HC32F448_LQFP80 GT9XX Global Functions + * @{ + */ + +/** + * @brief GT9XX device initialize. + * @param None + * @retval None + */ +void BSP_GT9XX_Init(void) +{ + char acTmp[4]; + BSP_GT9XX_I2C_Init(); + + BSP_GT9XX_ReadProductID((uint8_t *)acTmp, 4UL); + if (((acTmp[0] == '9') && (acTmp[1] == '1') && (acTmp[2] == '1')) || \ + ((acTmp[0] == '9') && (acTmp[1] == '1') && (acTmp[2] == '7') && (acTmp[3] == 'S'))) { + BSP_GT9XX_SoftReset(); + } else { + DDL_Printf("Unsupoort touch driver IC"); + } +} + +/** + * @brief Reset GT9XX. + * @param None + * @retval None + */ +void BSP_GT9XX_SoftReset(void) +{ + GT9XX_SoftReset(&m_stcGt9xxLL); +} + +/** + * @brief Read GT9XX touch status. + * @param None + * @retval Touch status + */ +uint8_t BSP_GT9XX_ReadTouchStatus(void) +{ + return GT9XX_ReadTouchStatus(&m_stcGt9xxLL); +} + +/** + * @brief Read GT9XX ID. + * @param [out] pu8IDValue The buffer for reading ID + * @param [in] u32Len The buffer size for bytes + * @retval None + */ +void BSP_GT9XX_ReadProductID(uint8_t *pu8IDValue, uint32_t u32Len) +{ + GT9XX_ReadProductID(&m_stcGt9xxLL, pu8IDValue, u32Len); +} + +/** + * @brief Read GT9XX point. + * @param [in] u16Point Touch pad point + * @param [out] pu16X Point x coordinate + * @param [out] pu16Y Point y coordinate + * @retval None + */ +void BSP_GT9XX_GetXY(uint16_t u16Point, uint16_t *pu16X, uint16_t *pu16Y) +{ + GT9XX_GetXY(&m_stcGt9xxLL, u16Point, pu16X, pu16Y); +} + +/** + * @brief Read register on touch pad register. + * @param [in] u16Reg Register to be read + * @param [out] pu8RegValue The buffer for reading + * @param [in] u32Len The buffer size for bytes + * @retval None + */ +void BSP_GT9XX_REG_Read(uint16_t u16Reg, uint8_t *pu8RegValue, uint32_t u32Len) +{ + GT9XX_REG_Read(&m_stcGt9xxLL, u16Reg, pu8RegValue, u32Len); +} + +/** + * @brief Write register on touch pad register. + * @param [in] u16Reg Register to be write + * @param [in] pu8RegValue The buffer for writing + * @param [in] u32Len The buffer size for bytes + * @retval None + */ +void BSP_GT9XX_REG_Write(uint16_t u16Reg, const uint8_t *pu8RegValue, uint32_t u32Len) +{ + GT9XX_REG_Write(&m_stcGt9xxLL, u16Reg, pu8RegValue, u32Len); +} + +/** + * @} + */ + +#endif /* BSP_GT9XX_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_gt9xx.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_gt9xx.h new file mode 100644 index 0000000000..409ac195fc --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_gt9xx.h @@ -0,0 +1,135 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_gt9xx.h + * @brief This file contains all the functions prototypes of the touch pad gt9xx + * driver library for the board EV_HC32F448_LQFP80. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_GT9XX_H__ +#define __EV_HC32F448_LQFP80_GT9XX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "gt9xx.h" +#include "ev_hc32f448_lqfp80.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80_GT9XX + * @{ + */ +#if ((BSP_GT9XX_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_GT9XX_Global_Macros EV_HC32F448_LQFP80 GT9XX Global Macros + * @{ + */ + +/** + * @defgroup GT9XX_I2C_Interface GT9XX I2C Interface + * @{ + */ +/* GT9XX I2C device address: 0x5D or 0x14 */ +#define BSP_GT9XX_I2C_ADDR (0x14U) + +/* I2C unit */ +#define BSP_GT9XX_I2C_UNIT (CM_I2C1) +#define BSP_GT9XX_I2C_FCG (FCG1_PERIPH_I2C1) + +/* SDA and SCL pin define */ +#define BSP_GT9XX_I2C_SCL_PORT (GPIO_PORT_E) +#define BSP_GT9XX_I2C_SCL_PIN (GPIO_PIN_01) +#define BSP_GT9XX_I2C_SCL_FUNC (GPIO_FUNC_49) + +#define BSP_GT9XX_I2C_SDA_PORT (GPIO_PORT_E) +#define BSP_GT9XX_I2C_SDA_PIN (GPIO_PIN_00) +#define BSP_GT9XX_I2C_SDA_FUNC (GPIO_FUNC_48) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_GT9XX_Global_Functions + * @{ + */ +void BSP_GT9XX_Init(void); +void BSP_GT9XX_SoftReset(void); +uint8_t BSP_GT9XX_ReadTouchStatus(void); +void BSP_GT9XX_ReadProductID(uint8_t *pu8IDValue, uint32_t u32Len); +void BSP_GT9XX_GetXY(uint16_t u16Point, uint16_t *pu16X, uint16_t *pu16Y); +void BSP_GT9XX_REG_Read(uint16_t u16Reg, uint8_t *pu8RegValue, uint32_t u32Len); +void BSP_GT9XX_REG_Write(uint16_t u16Reg, const uint8_t *pu8RegValue, uint32_t u32Len); +/** + * @} + */ + +#endif /* BSP_GT9XX_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_GT9XX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_is61lv6416.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_is61lv6416.c new file mode 100644 index 0000000000..4271725ebc --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_is61lv6416.c @@ -0,0 +1,321 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_is61lv6416.c + * @brief This file provides configure functions for is61lv6416 of the board + * EV_HC32F448_LQFP80. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Modify the timing: EXCLK 100MHz -> 40MHz + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +#include "hc32_ll_fcg.h" +#include "ev_hc32f448_lqfp80_is61lv6416.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @defgroup EV_HC32F448_LQFP80_IS61LV6416 EV_HC32F448_LQFP80 IS61LV6416 + * @{ + */ + +#if ((DDL_ON == BSP_IS61LV6416_ENABLE) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_IS61LV6416_Local_Macros EV_HC32F448_LQFP80 IS61LV6416 Local Macros + * @{ + */ + +/** + * @defgroup SMC_Max_Timeout SMC Max Timeout + * @{ + */ +#define SMC_MAX_TIMEOUT (0x100000UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_IS61LV6416_Local_Functions + * @{ + */ +static void BSP_SMC_PortInit(void); +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_IS61LV6416_Global_Functions EV_HC32F448_LQFP80 IS61LV6416 Global Functions + * @{ + */ + +/** + * @brief Initialize SMC for IS61LV6416. + * @param None + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR: Initialize unsuccessfully. + */ +int32_t BSP_IS61LV6416_Init(void) +{ + __IO uint32_t u32To = 0UL; + int32_t i32Ret = LL_OK; + stc_exmc_smc_init_t stcSmcInit; + stc_exmc_smc_chip_config_t stcChipConfig; + stc_exmc_smc_timing_config_t stcTimingConfig; + en_flag_status_t enChipStatus = RESET; + en_flag_status_t enTimingStatus = RESET; + + /* Initialize SMC port. */ + BSP_SMC_PortInit(); + + /* Enable SMC clock */ + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_SMC, ENABLE); + + /* Enable SMC. */ + EXMC_SMC_Cmd(ENABLE); + + EXMC_SMC_ExitLowPower(); + + while (EXMC_SMC_READY != EXMC_SMC_GetStatus()) { + if (u32To > SMC_MAX_TIMEOUT) { + i32Ret = LL_ERR; + break; + } + u32To++; + } + + if (LL_OK == i32Ret) { + /* Configure SMC width && CS &chip & timing. */ + (void)EXMC_SMC_StructInit(&stcSmcInit); + stcSmcInit.stcChipConfig.u32ReadMode = EXMC_SMC_READ_ASYNC; + stcSmcInit.stcChipConfig.u32WriteMode = EXMC_SMC_WRITE_ASYNC; + stcSmcInit.stcChipConfig.u32MemoryWidth = EXMC_SMC_MEMORY_WIDTH_16BIT; + stcSmcInit.stcChipConfig.u32BAA = EXMC_SMC_BAA_PORT_DISABLE; + stcSmcInit.stcChipConfig.u32ADV = EXMC_SMC_ADV_PORT_ENABLE; + stcSmcInit.stcChipConfig.u32BLS = EXMC_SMC_BLS_SYNC_CS; + stcSmcInit.stcChipConfig.u32AddrMatch = BSP_IS61LV6416_MATCH_ADDR; + stcSmcInit.stcChipConfig.u32AddrMask = BSP_IS61LV6416_MASK_ADDR; + + /* EXCLK bus frequency@40MHz: 3.3V */ + stcSmcInit.stcTimingConfig.u8RC = 5U; + stcSmcInit.stcTimingConfig.u8WC = 4U; + stcSmcInit.stcTimingConfig.u8CEOE = 3U; + stcSmcInit.stcTimingConfig.u8WP = 1U; + stcSmcInit.stcTimingConfig.u8TR = 1U; + stcSmcInit.stcTimingConfig.u8ADV = 1U; + (void)EXMC_SMC_Init(BSP_IS61LV6416_CHIP, &stcSmcInit); + + /* Set DATA/ADD Pin mux */ + EXMC_SMC_PinMuxCmd(ENABLE); + + /* Set command: updateregs */ + EXMC_SMC_SetCommand(BSP_IS61LV6416_CHIP, EXMC_SMC_CMD_UPDATEREGS, 0UL, 0UL); + + /* Check timing status */ + u32To = 0UL; + while ((enChipStatus != SET) || (enTimingStatus != SET)) { + (void)EXMC_SMC_GetTimingConfig(BSP_IS61LV6416_CHIP, &stcTimingConfig); + if (0 == memcmp(&stcTimingConfig, &stcSmcInit.stcTimingConfig, sizeof(stcTimingConfig))) { + enTimingStatus = SET; + } + + (void)EXMC_SMC_GetChipConfig(BSP_IS61LV6416_CHIP, &stcChipConfig); + if (0 == memcmp(&stcChipConfig, &stcSmcInit.stcChipConfig, sizeof(stcChipConfig))) { + enChipStatus = SET; + } + + if (u32To > SMC_MAX_TIMEOUT) { + i32Ret = LL_ERR; + break; + } + u32To++; + } + } + + return i32Ret; +} + +/** + * @brief Get memory information. + * @param [out] pu32MemoryStartAddr Pointer to memory start address + * @param [out] pu32MemoryByteSize Pointer to memory size(unit: Byte) + * @retval None + */ +void BSP_IS61LV6416_GetMemInfo(uint32_t *pu32MemoryStartAddr, uint32_t *pu32MemoryByteSize) +{ + if (NULL != pu32MemoryStartAddr) { + *pu32MemoryStartAddr = BSP_IS61LV6416_START_ADDR; + } + + if (NULL != pu32MemoryByteSize) { + *pu32MemoryByteSize = BSP_IS61LV6416_SIZE; + } +} + +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_IS61LV6416_Local_Functions EV_HC32F448_LQFP80 IS61LV6416 Local Functions + * @{ + */ + +/** + * @brief Initialize SMC port. + * @param None + * @retval None + */ +static void BSP_SMC_PortInit(void) +{ + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + /* SMC_ADV */ + stcGpioInit.u16Invert = PIN_INVT_ON; + (void)GPIO_Init(BSP_IS61LV6416_ADV_PORT, BSP_IS61LV6416_ADV_PIN, &stcGpioInit); + + /* Output invert off */ + stcGpioInit.u16Invert = PIN_INVT_OFF; + + /* SMC_CS */ + (void)GPIO_Init(BSP_IS61LV6416_CS_PORT, BSP_IS61LV6416_CS_PIN, &stcGpioInit); + + /* SMC_WE */ + (void)GPIO_Init(BSP_IS61LV6416_WE_PORT, BSP_IS61LV6416_WE_PIN, &stcGpioInit); + + /* SMC_BLS[0:1] */ + (void)GPIO_Init(BSP_IS61LV6416_BLS0_PORT, BSP_IS61LV6416_BLS0_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_BLS1_PORT, BSP_IS61LV6416_BLS1_PIN, &stcGpioInit); + + /* SMC_OE */ + (void)GPIO_Init(BSP_IS61LV6416_OE_PORT, BSP_IS61LV6416_OE_PIN, &stcGpioInit); + + /* SMC_DATA[0:15] */ + (void)GPIO_Init(BSP_IS61LV6416_DATA0_PORT, BSP_IS61LV6416_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA1_PORT, BSP_IS61LV6416_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA2_PORT, BSP_IS61LV6416_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA3_PORT, BSP_IS61LV6416_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA4_PORT, BSP_IS61LV6416_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA5_PORT, BSP_IS61LV6416_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA6_PORT, BSP_IS61LV6416_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA7_PORT, BSP_IS61LV6416_DATA7_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA8_PORT, BSP_IS61LV6416_DATA8_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA9_PORT, BSP_IS61LV6416_DATA9_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA10_PORT, BSP_IS61LV6416_DATA10_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA11_PORT, BSP_IS61LV6416_DATA11_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA12_PORT, BSP_IS61LV6416_DATA12_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA13_PORT, BSP_IS61LV6416_DATA13_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA14_PORT, BSP_IS61LV6416_DATA14_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_IS61LV6416_DATA15_PORT, BSP_IS61LV6416_DATA15_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* SMC_CS */ + GPIO_SetFunc(BSP_IS61LV6416_CS_PORT, BSP_IS61LV6416_CS_PIN, GPIO_FUNC_12); + + /* SMC_WE */ + GPIO_SetFunc(BSP_IS61LV6416_WE_PORT, BSP_IS61LV6416_WE_PIN, GPIO_FUNC_12); + + /* SMC_BLS[0:1] */ + GPIO_SetFunc(BSP_IS61LV6416_BLS0_PORT, BSP_IS61LV6416_BLS0_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_BLS1_PORT, BSP_IS61LV6416_BLS1_PIN, GPIO_FUNC_12); + + /* SMC_OE */ + GPIO_SetFunc(BSP_IS61LV6416_OE_PORT, BSP_IS61LV6416_OE_PIN, GPIO_FUNC_12); + + /* SMC_ADV */ + GPIO_SetFunc(BSP_IS61LV6416_ADV_PORT, BSP_IS61LV6416_ADV_PIN, GPIO_FUNC_12); + + /* SMC_DATA[0:15] */ + GPIO_SetFunc(BSP_IS61LV6416_DATA0_PORT, BSP_IS61LV6416_DATA0_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA1_PORT, BSP_IS61LV6416_DATA1_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA2_PORT, BSP_IS61LV6416_DATA2_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA3_PORT, BSP_IS61LV6416_DATA3_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA4_PORT, BSP_IS61LV6416_DATA4_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA5_PORT, BSP_IS61LV6416_DATA5_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA6_PORT, BSP_IS61LV6416_DATA6_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA7_PORT, BSP_IS61LV6416_DATA7_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA8_PORT, BSP_IS61LV6416_DATA8_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA9_PORT, BSP_IS61LV6416_DATA9_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA10_PORT, BSP_IS61LV6416_DATA10_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA11_PORT, BSP_IS61LV6416_DATA11_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA12_PORT, BSP_IS61LV6416_DATA12_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA13_PORT, BSP_IS61LV6416_DATA13_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA14_PORT, BSP_IS61LV6416_DATA14_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_IS61LV6416_DATA15_PORT, BSP_IS61LV6416_DATA15_PIN, GPIO_FUNC_12); +} + +/** + * @} + */ + +#endif /* BSP_IS61LV6416_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_is61lv6416.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_is61lv6416.h new file mode 100644 index 0000000000..1463e3263a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_is61lv6416.h @@ -0,0 +1,203 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_is61lv6416.h + * @brief This file contains all the functions prototypes for is61lv6416 of the + * board EV_HC32F448_LQFP80. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_IS61LV6416_H__ +#define __EV_HC32F448_LQFP80_IS61LV6416_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_gpio.h" +#include "hc32_ll_smc.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80_IS61LV6416 + * @{ + */ +#if ((BSP_IS61LV6416_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_IS61LV6416_Global_Macros EV_HC32F448_LQFP80 IS61LV6416 Global Macros + * @{ + */ + +/** + * @defgroup IS61LV6416_Map_SMC_Chip IS61LV6416 Map SMC Chip + * @{ + */ +#define BSP_IS61LV6416_CHIP (EXMC_SMC_CHIP0) +/** + * @} + */ + +/** + * @defgroup IS61LV6416_SMC_Address_Space IS61LV6416 SMC Address Space + * @{ + */ +#define BSP_IS61LV6416_MATCH_ADDR (0x60UL) +#define BSP_IS61LV6416_MASK_ADDR (EXMC_SMC_ADDR_MASK_16MB) +/** + * @} + */ + +/** + * @defgroup IS61LV6416_Memory_Size IS61LV6416 Memory Size + * @{ + */ +#define BSP_IS61LV6416_SIZE (1UL * 128UL * 1024UL) /* 128KBytes */ +/** + * @} + */ + +/** + * @defgroup IS61LV6416_SRAM_Address_Space IS61LV6416 SRAM Address Space + * @note SRAM address:[0x60000000, 0x600FFFFF] & SRAM size: 1M bytes + * @{ + */ +#define BSP_IS61LV6416_START_ADDR (EXMC_SMC_GetChipStartAddr(BSP_IS61LV6416_CHIP)) +#define BSP_IS61LV6416_END_ADDR (BSP_IS61LV6416_START_ADDR + BSP_IS61LV6416_SIZE - 1UL) +/** + * @} + */ + +/** + * @defgroup SMC_Interface_Pin EXMC_SMC Interface Pin + * @{ + */ +#define BSP_IS61LV6416_CS_PORT (GPIO_PORT_A) /* PA04 - EXMC_CE0 */ +#define BSP_IS61LV6416_CS_PIN (GPIO_PIN_04) + +#define BSP_IS61LV6416_WE_PORT (GPIO_PORT_B) /* PB08 - EXMC_WE */ +#define BSP_IS61LV6416_WE_PIN (GPIO_PIN_08) + +#define BSP_IS61LV6416_BLS0_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE4 */ +#define BSP_IS61LV6416_BLS0_PIN (GPIO_PIN_02) +#define BSP_IS61LV6416_BLS1_PORT (GPIO_PORT_C) /* PC03 - EXMC_CE5 */ +#define BSP_IS61LV6416_BLS1_PIN (GPIO_PIN_03) + +#define BSP_IS61LV6416_OE_PORT (GPIO_PORT_B) /* PB09 - EXMC_OE */ +#define BSP_IS61LV6416_OE_PIN (GPIO_PIN_09) + +#define BSP_IS61LV6416_ADV_PORT (GPIO_PORT_B) /* PB07 - EXMC_ADV */ +#define BSP_IS61LV6416_ADV_PIN (GPIO_PIN_07) + +#define BSP_IS61LV6416_DATA0_PORT (GPIO_PORT_A) /* PA06 - EXMC_DATA0 */ +#define BSP_IS61LV6416_DATA0_PIN (GPIO_PIN_06) +#define BSP_IS61LV6416_DATA1_PORT (GPIO_PORT_A) /* PA07 - EXMC_DATA1 */ +#define BSP_IS61LV6416_DATA1_PIN (GPIO_PIN_07) +#define BSP_IS61LV6416_DATA2_PORT (GPIO_PORT_B) /* PB00 - EXMC_DATA2 */ +#define BSP_IS61LV6416_DATA2_PIN (GPIO_PIN_00) +#define BSP_IS61LV6416_DATA3_PORT (GPIO_PORT_B) /* PB01 - EXMC_DATA3 */ +#define BSP_IS61LV6416_DATA3_PIN (GPIO_PIN_01) +#define BSP_IS61LV6416_DATA4_PORT (GPIO_PORT_B) /* PB10 - EXMC_DATA4 */ +#define BSP_IS61LV6416_DATA4_PIN (GPIO_PIN_10) +#define BSP_IS61LV6416_DATA5_PORT (GPIO_PORT_B) /* PB12 - EXMC_DATA5 */ +#define BSP_IS61LV6416_DATA5_PIN (GPIO_PIN_12) +#define BSP_IS61LV6416_DATA6_PORT (GPIO_PORT_A) /* PA12 - EXMC_DATA6 */ +#define BSP_IS61LV6416_DATA6_PIN (GPIO_PIN_12) +#define BSP_IS61LV6416_DATA7_PORT (GPIO_PORT_A) /* PA05 - EXMC_DATA7 */ +#define BSP_IS61LV6416_DATA7_PIN (GPIO_PIN_05) +#define BSP_IS61LV6416_DATA8_PORT (GPIO_PORT_C) /* PC04 - EXMC_DATA8 */ +#define BSP_IS61LV6416_DATA8_PIN (GPIO_PIN_04) +#define BSP_IS61LV6416_DATA9_PORT (GPIO_PORT_C) /* PC05 - EXMC_DATA9 */ +#define BSP_IS61LV6416_DATA9_PIN (GPIO_PIN_05) +#define BSP_IS61LV6416_DATA10_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA10 */ +#define BSP_IS61LV6416_DATA10_PIN (GPIO_PIN_12) +#define BSP_IS61LV6416_DATA11_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA11 */ +#define BSP_IS61LV6416_DATA11_PIN (GPIO_PIN_13) +#define BSP_IS61LV6416_DATA12_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA12 */ +#define BSP_IS61LV6416_DATA12_PIN (GPIO_PIN_14) +#define BSP_IS61LV6416_DATA13_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA13 */ +#define BSP_IS61LV6416_DATA13_PIN (GPIO_PIN_15) +#define BSP_IS61LV6416_DATA14_PORT (GPIO_PORT_C) /* PC08 - EXMC_DATA14 */ +#define BSP_IS61LV6416_DATA14_PIN (GPIO_PIN_08) +#define BSP_IS61LV6416_DATA15_PORT (GPIO_PORT_C) /* PC09 - EXMC_DATA15 */ +#define BSP_IS61LV6416_DATA15_PIN (GPIO_PIN_09) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_IS61LV6416_Global_Functions + * @{ + */ +int32_t BSP_IS61LV6416_Init(void); +void BSP_IS61LV6416_GetMemInfo(uint32_t *pu32MemoryStartAddr, uint32_t *pu32MemoryByteSize); +/** + * @} + */ + +#endif /* BSP_IS61LV6416_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_IS61LV6416_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_nt35510.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_nt35510.c new file mode 100644 index 0000000000..cb31d7169f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_nt35510.c @@ -0,0 +1,535 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_nt35510.c + * @brief This file provides firmware functions of the LCD nt35510 driver + * library for the board EV_HC32F448_LQFP80. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Modify the timing: EXCLK 100MHz -> 40MHz + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "nt35510.h" +#include "hc32_ll_smc.h" +#include "ev_hc32f448_lqfp80.h" +#include "ev_hc32f448_lqfp80_nt35510.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @defgroup EV_HC32F448_LQFP80_NT35510 EV_HC32F448_LQFP80 NT35510 + * @{ + */ + +#if ((BSP_NT35510_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_NT35510_Local_Macros EV_HC32F448_LQFP80 NT35510 Local Macros + * @{ + */ + +/** + * @defgroup SMC_Max_Timeout SMC Max Timeout + * @{ + */ +#define SMC_MAX_TIMEOUT (0x100000UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_NT35510_Local_Variables EV_HC32F448_LQFP80 NT35510 Local Variables + * @{ + */ +static stc_lcd_controller_t *LCD = ((stc_lcd_controller_t *)BSP_NT35510_BASE); +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EV_HC32F448_LQFP80_NT35510_Local_Functions EV_HC32F448_LQFP80 NT35510 Local Functions + * @{ + */ + +/** + * @brief Initializes LCD gpio. + */ +static void LCD_Port_Init(void) +{ + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + /* LCD_CS */ + (void)GPIO_Init(BSP_NT35510_CS_PORT, BSP_NT35510_CS_PIN, &stcGpioInit); + + /* LCD_WE */ + (void)GPIO_Init(BSP_NT35510_WE_PORT, BSP_NT35510_WE_PIN, &stcGpioInit); + + /* LCD_OE */ + (void)GPIO_Init(BSP_NT35510_OE_PORT, BSP_NT35510_OE_PIN, &stcGpioInit); + + /* SMC_DATA[0:15] */ + (void)GPIO_Init(BSP_NT35510_DATA0_PORT, BSP_NT35510_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA1_PORT, BSP_NT35510_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA2_PORT, BSP_NT35510_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA3_PORT, BSP_NT35510_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA4_PORT, BSP_NT35510_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA5_PORT, BSP_NT35510_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA6_PORT, BSP_NT35510_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA7_PORT, BSP_NT35510_DATA7_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA8_PORT, BSP_NT35510_DATA8_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA9_PORT, BSP_NT35510_DATA9_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA10_PORT, BSP_NT35510_DATA10_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA11_PORT, BSP_NT35510_DATA11_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA12_PORT, BSP_NT35510_DATA12_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA13_PORT, BSP_NT35510_DATA13_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA14_PORT, BSP_NT35510_DATA14_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_NT35510_DATA15_PORT, BSP_NT35510_DATA15_PIN, &stcGpioInit); + + (void)GPIO_Init(BSP_NT35510_RS_PORT, BSP_NT35510_RS_PIN, &stcGpioInit); + + /* LCD_DATA[0:15] */ + GPIO_SetFunc(BSP_NT35510_DATA0_PORT, BSP_NT35510_DATA0_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA1_PORT, BSP_NT35510_DATA1_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA2_PORT, BSP_NT35510_DATA2_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA3_PORT, BSP_NT35510_DATA3_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA4_PORT, BSP_NT35510_DATA4_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA5_PORT, BSP_NT35510_DATA5_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA6_PORT, BSP_NT35510_DATA6_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA7_PORT, BSP_NT35510_DATA7_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA8_PORT, BSP_NT35510_DATA8_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA9_PORT, BSP_NT35510_DATA9_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA10_PORT, BSP_NT35510_DATA10_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA11_PORT, BSP_NT35510_DATA11_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA12_PORT, BSP_NT35510_DATA12_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA13_PORT, BSP_NT35510_DATA13_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA14_PORT, BSP_NT35510_DATA14_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_DATA15_PORT, BSP_NT35510_DATA15_PIN, GPIO_FUNC_12); + + GPIO_SetFunc(BSP_NT35510_CS_PORT, BSP_NT35510_CS_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_RS_PORT, BSP_NT35510_RS_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_WE_PORT, BSP_NT35510_WE_PIN, GPIO_FUNC_12); + GPIO_SetFunc(BSP_NT35510_OE_PORT, BSP_NT35510_OE_PIN, GPIO_FUNC_12); +} + +/** + * @brief Initializes LCD low level. + * @param None + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR: Initialize unsuccessfully. + */ +static int32_t LCD_SMC_Init(void) +{ + __IO uint32_t u32To = 0UL; + int32_t i32Ret = LL_OK; + stc_exmc_smc_init_t stcSmcInit; + stc_exmc_smc_chip_config_t stcChipConfig; + stc_exmc_smc_timing_config_t stcTimingConfig; + en_flag_status_t enChipStatus = RESET; + en_flag_status_t enTimingStatus = RESET; + + LCD_Port_Init(); + + /* Enable SMC clock */ + FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_SMC, ENABLE); + + /* Enable SMC. */ + EXMC_SMC_Cmd(ENABLE); + + EXMC_SMC_ExitLowPower(); + + while (EXMC_SMC_READY != EXMC_SMC_GetStatus()) { + if (u32To > SMC_MAX_TIMEOUT) { + i32Ret = LL_ERR; + break; + } + u32To++; + } + + if (LL_OK == i32Ret) { + /* Configure SMC width && CS &chip & timing. */ + (void)EXMC_SMC_StructInit(&stcSmcInit); + stcSmcInit.stcChipConfig.u32AddrMatch = BSP_NT35510_MATCH_ADDR; + stcSmcInit.stcChipConfig.u32AddrMask = BSP_NT35510_MASK_ADDR; + stcSmcInit.stcChipConfig.u32MemoryWidth = EXMC_SMC_MEMORY_WIDTH_16BIT; + stcSmcInit.stcChipConfig.u32BAA = EXMC_SMC_BAA_PORT_DISABLE; + stcSmcInit.stcChipConfig.u32ADV = EXMC_SMC_ADV_PORT_DISABLE; + stcSmcInit.stcChipConfig.u32BLS = EXMC_SMC_BLS_SYNC_CS; + stcSmcInit.stcChipConfig.u32ReadMode = EXMC_SMC_READ_ASYNC; + stcSmcInit.stcChipConfig.u32WriteMode = EXMC_SMC_WRITE_ASYNC; + + /* EXCLK bus frequency@40MHz: 3.3V */ + stcSmcInit.stcTimingConfig.u8RC = 4U; + stcSmcInit.stcTimingConfig.u8WC = 2U; + stcSmcInit.stcTimingConfig.u8CEOE = 1U; + stcSmcInit.stcTimingConfig.u8WP = 1U; + stcSmcInit.stcTimingConfig.u8TR = 1U; + (void)EXMC_SMC_Init(BSP_NT35510_CHIP, &stcSmcInit); + + /* Set command: updateregs */ + EXMC_SMC_SetCommand(BSP_NT35510_CHIP, EXMC_SMC_CMD_UPDATEREGS, 0UL, 0UL); + + /* Check timing status */ + u32To = 0UL; + while ((enChipStatus != SET) || (enTimingStatus != SET)) { + (void)EXMC_SMC_GetTimingConfig(BSP_NT35510_CHIP, &stcTimingConfig); + if (0 == memcmp(&stcTimingConfig, &stcSmcInit.stcTimingConfig, sizeof(stcTimingConfig))) { + enTimingStatus = SET; + } + + (void)EXMC_SMC_GetChipConfig(BSP_NT35510_CHIP, &stcChipConfig); + if (0 == memcmp(&stcChipConfig, &stcSmcInit.stcChipConfig, sizeof(stcChipConfig))) { + enChipStatus = SET; + } + + if (u32To > SMC_MAX_TIMEOUT) { + i32Ret = LL_ERR; + break; + } + u32To++; + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_NT35510_Global_Functions EV_HC32F448_LQFP80 NT35510 Global Functions + * @{ + */ + +/** + * @brief LCD device initialize. + * @param None + * @retval None + */ +void BSP_NT35510_Init(void) +{ + (void)LCD_SMC_Init(); + + NT35510_Init(LCD); +} + +/** + * @brief Read LCD ID. + * @param None + * @retval ID. + */ +uint32_t BSP_NT35510_ReadID(void) +{ + return NT35510_ReadID(LCD); +} + +/** + * @brief Enables the Display. + * @param None + * @retval None + */ +void BSP_NT35510_DisplayOn(void) +{ + NT35510_DisplayOn(LCD); +} + +/** + * @brief Disables the Display. + * @param None + * @retval None + */ +void BSP_NT35510_DisplayOff(void) +{ + NT35510_DisplayOff(LCD); +} + +/** + * @brief Get LCD PIXEL WIDTH. + * @param None + * @retval LCD PIXEL WIDTH. + */ +uint16_t BSP_NT35510_GetPixelWidth(void) +{ + return NT35510_GetPixelWidth(); +} + +/** + * @brief Get LCD PIXEL HEIGHT. + * @param None + * @retval LCD PIXEL HEIGHT. + */ +uint16_t BSP_NT35510_GetPixelHeight(void) +{ + return NT35510_GetPixelHeight(); +} + +/** + * @brief Write data on LCD data register. + * @param [in] u16Data: Data to be written + * @retval None + */ +void BSP_NT35510_WriteData(uint16_t u16Data) +{ + NT35510_WriteData(LCD, u16Data); +} + +/** + * @brief Write register on LCD register. + * @param [in] u16Reg: Address of the selected register. + * @retval None + */ +void BSP_NT35510_WriteReg(uint16_t u16Reg) +{ + NT35510_WriteReg(LCD, u16Reg); +} + +/** + * @brief Read data from LCD data register. + * @param None + * @retval Read data. + */ +uint16_t BSP_NT35510_ReadData(void) +{ + return NT35510_ReadData(LCD); +} + +/** + * @brief Write to the selected LCD register. + * @param [in] u16Reg: Address of the selected register. + * @param [in] u16Data: Data to be written + * @retval None + */ +void BSP_NT35510_WriteRegData(uint16_t u16Reg, uint16_t u16Data) +{ + NT35510_WriteRegData(LCD, u16Reg, u16Data); +} + +/** + * @brief Read the selected LCD register. + * @param [in] u16Reg: Address of the selected register. + * @retval Register value + */ +uint16_t BSP_NT35510_ReadRegData(uint16_t u16Reg) +{ + return NT35510_ReadRegData(LCD, u16Reg); +} + +/** + * @brief Set scan direction. + * @param [in] u16Dir: Scan direction + * This parameter can be one of the following values: + * @arg LCD_SCAN_DIR_L2R_U2D: From left to right && from up to down + * @arg LCD_SCAN_DIR_L2R_D2U: From left to right && from down to up + * @arg LCD_SCAN_DIR_R2L_U2D: From right to left && from up to down + * @arg LCD_SCAN_DIR_R2L_D2U: From right to left && from down to up + * @arg LCD_SCAN_DIR_U2D_L2R: From up to down && from left to right + * @arg LCD_SCAN_DIR_U2D_R2L: From up to down && from right to left + * @arg LCD_SCAN_DIR_D2U_L2R: From down to up && from left to right + * @arg LCD_SCAN_DIR_D2U_R2L: From down to up && from right to left + * @retval None + */ +void BSP_NT35510_SetScanDir(uint16_t u16Dir) +{ + NT35510_SetScanDir(LCD, u16Dir); +} + +/** + * @brief Set screen direction. + * @param [in] u16Dir: Screen direction + * This parameter can be one of the following values: + * @arg LCD_DISPLAY_VERTICAL: LCD vertical display + * @arg LCD_DISPLAY_HORIZONTAL: LCD horizontal display + * @retval None + */ +void BSP_NT35510_SetDisplayDir(uint16_t u16Dir) +{ + NT35510_SetDisplayDir(LCD, u16Dir); +} + +/** + * @brief Prepare to write LCD RAM. + * @param None + */ +void BSP_NT35510_PrepareWriteRAM(void) +{ + NT35510_PrepareWriteRAM(LCD); +} + +/** + * @brief Set screen backlight. + * @param [in] u8PWM: PWM level + This parameter can be a value between Min_Data = 0 and Max_Data = 100 + * @retval None + */ +void BSP_NT35510_SetBackLight(uint8_t u8PWM) +{ + NT35510_SetBackLight(LCD, u8PWM); +} + +/** + * @brief Set Cursor position. + * @param u16Xpos: Specifies the X position. + * @param u16Ypos: Specifies the Y position. + * @retval None + */ +void BSP_NT35510_SetCursor(uint16_t u16Xpos, uint16_t u16Ypos) +{ + NT35510_SetCursor(LCD, u16Xpos, u16Ypos); +} + +/** + * @brief Write pixel. + * @param u16Xpos: Specifies the X position. + * @param u16Ypos: Specifies the Y position. + * @param [in] u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void BSP_NT35510_WritePixel(uint16_t u16Xpos, uint16_t u16Ypos, uint16_t u16RGBCode) +{ + NT35510_WritePixel(LCD, u16Xpos, u16Ypos, u16RGBCode); +} + +/** + * @brief Write line. + * @param u16X1: Specifies the X position 1. + * @param u16X2: Specifies the X position 2. + * @param u16Y1: Specifies the Y position 1. + * @param u16Y2: Specifies the Y position 2. + * @param [in] u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void BSP_NT35510_DrawLine(uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode) +{ + NT35510_DrawLine(LCD, u16X1, u16Y1, u16X2, u16Y2, u16RGBCode); +} + +/** + * @brief Draws a circle. + * @param [in] u16Xpos: X position + * @param [in] u16Ypos: Y position + * @param [in] u16Radius: Circle radius + * @param [in] u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void BSP_NT35510_DrawCircle(uint16_t u16Xpos, uint16_t u16Ypos, uint16_t u16Radius, uint16_t u16RGBCode) +{ + NT35510_DrawCircle(LCD, u16Xpos, u16Ypos, u16Radius, u16RGBCode); +} + +/** + * @brief Fills a triangle (between 3 points). + * @param [in] u16X1: Point 1 X position + * @param [in] u16Y1: Point 1 Y position + * @param [in] u16X2: Point 2 X position + * @param [in] u16Y2: Point 2 Y position + * @param [in] u16X3: Point 3 X position + * @param [in] u16Y3: Point 3 Y position + * @param [in] u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void BSP_NT35510_FillTriangle(uint16_t u16X1, uint16_t u16Y1, uint16_t u16X2, uint16_t u16Y2, uint16_t u16X3, + uint16_t u16Y3, uint16_t u16RGBCode) +{ + NT35510_FillTriangle(LCD, u16X1, u16Y1, u16X2, u16Y2, u16X3, u16Y3, u16RGBCode); +} + +/** + * @brief Draw rectangle. + * @param [in] u16X1: Point 1 X position + * @param [in] u16Y1: Point 1 Y position + * @param [in] u16X2: Point 2 X position + * @param [in] u16Y2: Point 2 Y position + * @param [in] u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void BSP_NT35510_DrawRectangle(uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode) +{ + NT35510_DrawRectangle(LCD, u16X1, u16Y1, u16X2, u16Y2, u16RGBCode); +} + +/** + * @brief Clear screen. + * @param [in] u16RGBCode: The RGB pixel color in RGB565 format + * @retval None + */ +void BSP_NT35510_Clear(uint16_t u16RGBCode) +{ + NT35510_Clear(LCD, u16RGBCode); +} + +/** + * @} + */ + +#endif /* BSP_NT35510_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_nt35510.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_nt35510.h new file mode 100644 index 0000000000..5c86c6d3bc --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_nt35510.h @@ -0,0 +1,205 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_nt35510.h + * @brief This file contains all the functions prototypes of the LCD nt35510 + * driver library for the board EV_HC32F448_LQFP80. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_NT35510_H__ +#define __EV_HC32F448_LQFP80_NT35510_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "nt35510.h" +#include "hc32_ll_gpio.h" +#include "hc32_ll_smc.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80_NT35510 + * @{ + */ +#if ((BSP_NT35510_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_NT35510_Global_Macros EV_HC32F448_LQFP80 NT35510 Global Macros + * @{ + */ + +/** + * @defgroup LCD_Map_SMC_Chip LCD Map SMC Chip + * @{ + */ +#define BSP_NT35510_CHIP (EXMC_SMC_CHIP0) +/** + * @} + */ + +/** + * @defgroup LCD_SMC_Address_Space LCD SMC Address Space + * @{ + */ +#define BSP_NT35510_MATCH_ADDR (0x70UL) +#define BSP_NT35510_MASK_ADDR (EXMC_SMC_ADDR_MASK_16MB) +/** + * @} + */ + +/** + * @defgroup LCD_Interface_Pin LCD Interface Pin + * @{ + */ +#define BSP_NT35510_CS_PORT (GPIO_PORT_A) /* PA04 - EXMC_CE0 */ +#define BSP_NT35510_CS_PIN (GPIO_PIN_04) + +#define BSP_NT35510_WE_PORT (GPIO_PORT_B) /* PB08 - EXMC_WE */ +#define BSP_NT35510_WE_PIN (GPIO_PIN_08) + +#define BSP_NT35510_OE_PORT (GPIO_PORT_B) /* PB09 - EXMC_OE */ +#define BSP_NT35510_OE_PIN (GPIO_PIN_09) + +#define BSP_NT35510_RS_PORT (GPIO_PORT_C) /* PC13 - EXMC_ADD16 for LCD_RS */ +#define BSP_NT35510_RS_PIN (GPIO_PIN_13) + +#define BSP_NT35510_DATA0_PORT (GPIO_PORT_A) /* PA06 - EXMC_DATA0 */ +#define BSP_NT35510_DATA0_PIN (GPIO_PIN_06) +#define BSP_NT35510_DATA1_PORT (GPIO_PORT_A) /* PA07 - EXMC_DATA1 */ +#define BSP_NT35510_DATA1_PIN (GPIO_PIN_07) +#define BSP_NT35510_DATA2_PORT (GPIO_PORT_B) /* PB00 - EXMC_DATA2 */ +#define BSP_NT35510_DATA2_PIN (GPIO_PIN_00) +#define BSP_NT35510_DATA3_PORT (GPIO_PORT_B) /* PB01 - EXMC_DATA3 */ +#define BSP_NT35510_DATA3_PIN (GPIO_PIN_01) +#define BSP_NT35510_DATA4_PORT (GPIO_PORT_B) /* PB10 - EXMC_DATA4 */ +#define BSP_NT35510_DATA4_PIN (GPIO_PIN_10) +#define BSP_NT35510_DATA5_PORT (GPIO_PORT_B) /* PB12 - EXMC_DATA5 */ +#define BSP_NT35510_DATA5_PIN (GPIO_PIN_12) +#define BSP_NT35510_DATA6_PORT (GPIO_PORT_A) /* PA12 - EXMC_DATA6 */ +#define BSP_NT35510_DATA6_PIN (GPIO_PIN_12) +#define BSP_NT35510_DATA7_PORT (GPIO_PORT_A) /* PA05 - EXMC_DATA7 */ +#define BSP_NT35510_DATA7_PIN (GPIO_PIN_05) +#define BSP_NT35510_DATA8_PORT (GPIO_PORT_C) /* PC04 - EXMC_DATA8 */ +#define BSP_NT35510_DATA8_PIN (GPIO_PIN_04) +#define BSP_NT35510_DATA9_PORT (GPIO_PORT_C) /* PC05 - EXMC_DATA9 */ +#define BSP_NT35510_DATA9_PIN (GPIO_PIN_05) +#define BSP_NT35510_DATA10_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA10 */ +#define BSP_NT35510_DATA10_PIN (GPIO_PIN_12) +#define BSP_NT35510_DATA11_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA11 */ +#define BSP_NT35510_DATA11_PIN (GPIO_PIN_13) +#define BSP_NT35510_DATA12_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA12 */ +#define BSP_NT35510_DATA12_PIN (GPIO_PIN_14) +#define BSP_NT35510_DATA13_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA13 */ +#define BSP_NT35510_DATA13_PIN (GPIO_PIN_15) +#define BSP_NT35510_DATA14_PORT (GPIO_PORT_C) /* PC08 - EXMC_DATA14 */ +#define BSP_NT35510_DATA14_PIN (GPIO_PIN_08) +#define BSP_NT35510_DATA15_PORT (GPIO_PORT_C) /* PC09 - EXMC_DATA15 */ +#define BSP_NT35510_DATA15_PIN (GPIO_PIN_09) +/** + * @} + */ + +/* Use EXMC A16 as the RS signal */ +#define BSP_NT35510_BASE (0x70000000UL | ((1UL << 17U) - 2UL)) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_NT35510_Global_Functions + * @{ + */ +void BSP_NT35510_Init(void); +uint32_t BSP_NT35510_ReadID(void); +void BSP_NT35510_DisplayOn(void); +void BSP_NT35510_DisplayOff(void); +uint16_t BSP_NT35510_GetPixelWidth(void); +uint16_t BSP_NT35510_GetPixelHeight(void); +void BSP_NT35510_WriteData(uint16_t u16Data); +void BSP_NT35510_WriteReg(uint16_t u16Reg); +uint16_t BSP_NT35510_ReadData(void); +void BSP_NT35510_WriteRegData(uint16_t u16Reg, uint16_t u16Data); +uint16_t BSP_NT35510_ReadRegData(uint16_t u16Reg); +void BSP_NT35510_SetScanDir(uint16_t u16Dir); +void BSP_NT35510_SetDisplayDir(uint16_t u16Dir); +void BSP_NT35510_PrepareWriteRAM(void); +void BSP_NT35510_SetBackLight(uint8_t u8PWM); +void BSP_NT35510_SetCursor(uint16_t u16Xpos, uint16_t u16Ypos); +void BSP_NT35510_WritePixel(uint16_t u16Xpos, uint16_t u16Ypos, uint16_t u16RGBCode); +void BSP_NT35510_DrawLine(uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode); +void BSP_NT35510_DrawCircle(uint16_t u16Xpos, uint16_t u16Ypos, uint16_t u16Radius, uint16_t u16RGBCode); +void BSP_NT35510_FillTriangle(uint16_t u16X1, uint16_t u16Y1, uint16_t u16X2, uint16_t u16Y2, + uint16_t u16X3, uint16_t u16Y3, uint16_t u16RGBCode); +void BSP_NT35510_DrawRectangle(uint16_t u16X1, uint16_t u16Y1, + uint16_t u16X2, uint16_t u16Y2, uint16_t u16RGBCode); +void BSP_NT35510_Clear(uint16_t u16RGBCode); +/** + * @} + */ + +#endif /* BSP_NT35510_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_NT35510_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_tca9539.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_tca9539.c new file mode 100644 index 0000000000..f2101fb2a5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_tca9539.c @@ -0,0 +1,387 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_tca9539.c + * @brief This file provides firmware functions for IO expand IC TCA9539. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ev_hc32f448_lqfp80_tca9539.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @defgroup EV_HC32F448_LQFP80_TCA9539 HC32F448 EVB LQFP80 TCA9539 + * @{ + */ + +#if ((BSP_TCA9539_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static stc_tca9539_ll_t stcTca9539Config = {0}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_TCA9539_Global_Functions HC32F448 LQFP80 EVB TCA9539 Global Functions + * @{ + */ + +/** + * @brief BSP TCA9539 reset. + * @param None + * @retval None + */ +static void BSP_TCA9539_Reset(void) +{ + stc_gpio_init_t stcGpioInit; + + /* Set to low before output enable */ + GPIO_ResetPins(EIO_RST_PORT, EIO_RST_PIN); + (void)GPIO_StructInit(&stcGpioInit); + /* SET to output */ + stcGpioInit.u16PinDir = PIN_DIR_OUT; + (void)GPIO_Init(EIO_RST_PORT, EIO_RST_PIN, &stcGpioInit); + /* Reset the device */ + DDL_DelayMS(3UL); + GPIO_SetPins(EIO_RST_PORT, EIO_RST_PIN); +} + +/** + * @brief Initializes I2C for TCA9539. + * @param None + * @retval None + */ +static void BSP_TCA9539_I2C_Init(void) +{ + stc_gpio_init_t stcGpioInit; + /* Configuration I2C GPIO */ + (void)GPIO_StructInit(&stcGpioInit); + (void)GPIO_Init(BSP_TCA9539_I2C_SCL_PORT, BSP_TCA9539_I2C_SCL_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_TCA9539_I2C_SDA_PORT, BSP_TCA9539_I2C_SDA_PIN, &stcGpioInit); + GPIO_SetFunc(BSP_TCA9539_I2C_SCL_PORT, BSP_TCA9539_I2C_SCL_PIN, BSP_TCA9539_I2C_SCL_FUNC); + GPIO_SetFunc(BSP_TCA9539_I2C_SDA_PORT, BSP_TCA9539_I2C_SDA_PIN, BSP_TCA9539_I2C_SDA_FUNC); + /* Enable I2C Peripheral*/ + FCG_Fcg1PeriphClockCmd(BSP_TCA9539_I2C_FCG, ENABLE); + (void)BSP_I2C_Init(BSP_TCA9539_I2C_UNIT); +} + +/** + * @brief BSP TCA9539 write data. + * @param [in] pu8Reg: Register to be written. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be written. + * @param [in] u32Len: Buffer size in byte. + * @retval None + */ +static void BSP_TCA9539_I2C_Write(const uint8_t *pu8Reg, const uint8_t *pu8Buf, uint32_t u32Len) +{ + (void)BSP_I2C_Write(BSP_TCA9539_I2C_UNIT, BSP_TCA9539_DEV_ADDR, pu8Reg, BSP_TCA9539_REG_ADDR_LEN, pu8Buf, u32Len); +} + +/** + * @brief BSP TCA9539 Read data. + * @param [in] pu8Reg: Register to be read. + * @param [in] pu8Buf: The pointer to the buffer contains the data to be read. + * @param [in] u32Len: Buffer size in byte. + * @retval None + */ +static void BSP_TCA9539_I2C_Read(const uint8_t *pu8Reg, uint8_t *pu8Buf, uint32_t u32Len) +{ + (void)BSP_I2C_Read(BSP_TCA9539_I2C_UNIT, BSP_TCA9539_DEV_ADDR, pu8Reg, BSP_TCA9539_REG_ADDR_LEN, pu8Buf, u32Len); +} + +/** + * @brief Expand IO initialize. + * @param None + * @retval None + */ +void BSP_IO_Init(void) +{ + /* Configuration the low layer of TCA9539 */ + stcTca9539Config.Init = BSP_TCA9539_I2C_Init; + stcTca9539Config.Write = BSP_TCA9539_I2C_Write; + stcTca9539Config.Read = BSP_TCA9539_I2C_Read; + stcTca9539Config.Reset = BSP_TCA9539_Reset; + stcTca9539Config.IntInit = NULL; + /* Configuration the TCA9539 */ + (void)TCA9539_Init(&stcTca9539Config); +} + +/** + * @brief Expand IO interrupt initialize. + * @param None + * @retval None + */ +void BSP_IO_IntInit(void) +{ + (void)TCA9539_IntInit(&stcTca9539Config); +} + +/** + * @brief Set EIO port pin output value + * @param [in] u8Port Port number @ref HC32F448_EV_IO_Port_Definition. + * @param [in] u8Pin Pin number @ref HC32F448_EV_IO_Function_Sel. + * @param [in] u8PinState Pin state @ref HC32F448_EV_IO_Pin_State_Definition. + * @retval None + */ +void BSP_IO_WritePortPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState) +{ + (void)TCA9539_WritePin(&stcTca9539Config, u8Port, u8Pin, u8PinState); +} + +/** + * @brief Get EIO port pin input value + * @param [in] u8Port Port number @ref HC32F448_EV_IO_Port_Definition. + * @param [in] u8Pin Pin number @ref HC32F448_EV_IO_Function_Sel. + * @retval Pin state + */ +uint8_t BSP_IO_ReadPortPin(uint8_t u8Port, uint8_t u8Pin) +{ + uint8_t u8Value; + + (void)TCA9539_ReadPin(&stcTca9539Config, u8Port, u8Pin, &u8Value); + return u8Value; +} + +/** + * @brief Toggle EIO port pin + * @param [in] u8Port Port number @ref HC32F448_EV_IO_Port_Definition. + * @param [in] u8Pin Pin number @ref HC32F448_EV_IO_Function_Sel. + * @retval None + */ +void BSP_IO_TogglePortPin(uint8_t u8Port, uint8_t u8Pin) +{ + (void)TCA9539_TogglePin(&stcTca9539Config, u8Port, u8Pin); +} + +/** + * @brief Config EIO port pin direction + * @param [in] u8Port Port number @ref HC32F448_EV_IO_Port_Definition. + * @param [in] u8Pin Pin number @ref HC32F448_EV_IO_Function_Sel. + * @param [in] u8Dir Pin direction @ref HC32F448_EV_IO_Direction_Definition. + * @retval None + */ +void BSP_IO_ConfigPortPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir) +{ + (void)TCA9539_ConfigPin(&stcTca9539Config, u8Port, u8Pin, u8Dir); +} + +/** + * @brief CAN PYH STB pin initialization. + * @param None + * @retval None + */ +void BSP_CAN_STB_IO_Init(void) +{ + /* SET STB pin high before output */ + BSP_IO_WritePortPin(CAN1_STB_PORT, CAN1_STB_PIN, EIO_PIN_SET); + BSP_IO_WritePortPin(CAN2_STB_PORT, CAN2_STB_PIN, EIO_PIN_SET); + /* STB pin set to output */ + BSP_IO_ConfigPortPin(CAN1_STB_PORT, CAN1_STB_PIN, EIO_DIR_OUT); + BSP_IO_ConfigPortPin(CAN2_STB_PORT, CAN2_STB_PIN, EIO_DIR_OUT); +} + +/** + * @brief CAN PYH STB pin control + * @param [in] u8Cmd + * @arg EIO_PIN_SET + * @arg EIO_PIN_RESET + * @retval None + */ +void BSP_CAN_STBCmd(uint8_t u8Cmd) +{ + BSP_IO_WritePortPin(CAN1_STB_PORT, CAN1_STB_PIN, u8Cmd); + BSP_IO_WritePortPin(CAN2_STB_PORT, CAN2_STB_PIN, u8Cmd); +} + +/** + * @brief Cap panel reset pin config. + * @param [in] u8Cmd + * @arg EIO_PIN_SET + * @arg EIO_PIN_RESET + * @retval None + */ +void BSP_CT_RSTCmd(uint8_t u8Cmd) +{ + BSP_IO_ConfigPortPin(LCD_CTRST_PORT, LCD_CTRST_PIN, EIO_DIR_OUT); + BSP_IO_WritePortPin(LCD_CTRST_PORT, LCD_CTRST_PIN, u8Cmd); + BSP_IO_ConfigPortPin(LCD_CTRST_PORT, LCD_CTRST_PIN, EIO_DIR_IN); +} + +/** + * @brief LCD ctrl IO initialize. + * @param None + * @retval None + */ +void BSP_LCD_IO_Init(void) +{ + /* Init LCD backlight IO */ + BSP_IO_WritePortPin(LCD_BKL_PORT, LCD_BKL_PIN, EIO_PIN_RESET); + BSP_IO_ConfigPortPin(LCD_BKL_PORT, LCD_BKL_PIN, EIO_DIR_OUT); + + /* Init LCD and touch panel control IO before direction setting */ + BSP_IO_WritePortPin(LCD_RST_PORT, LCD_RST_PIN, EIO_PIN_SET); + + /* LCD panel control IO set to output */ + BSP_IO_ConfigPortPin(LCD_RST_PORT, LCD_RST_PIN, EIO_DIR_OUT); + + /* Init touch panel control IO before direction setting */ + BSP_IO_WritePortPin(LCD_CTRST_PORT, LCD_CTRST_PIN, EIO_PIN_RESET); + BSP_IO_WritePortPin(LCD_CTINT_PORT, LCD_CTINT_PIN, EIO_PIN_RESET); + + BSP_IO_ConfigPortPin(LCD_CTRST_PORT, LCD_CTRST_PIN, EIO_DIR_OUT); + BSP_IO_ConfigPortPin(LCD_CTINT_PORT, LCD_CTINT_PIN, EIO_DIR_OUT); + DDL_DelayMS(100UL); + + BSP_IO_WritePortPin(LCD_CTINT_PORT, LCD_CTINT_PIN, EIO_PIN_SET); + DDL_DelayMS(100UL); + + BSP_IO_WritePortPin(LCD_CTRST_PORT, LCD_CTRST_PIN, EIO_PIN_SET); + DDL_DelayMS(10UL); + + BSP_IO_WritePortPin(LCD_CTINT_PORT, LCD_CTINT_PIN, EIO_PIN_RESET); + DDL_DelayMS(100UL); + + BSP_IO_ConfigPortPin(LCD_CTRST_PORT, LCD_CTRST_PIN, EIO_DIR_IN); + BSP_IO_ConfigPortPin(LCD_CTINT_PORT, LCD_CTINT_PIN, EIO_DIR_IN); +} + +/** + * @brief LCD reset pin config. + * @param [in] u8Cmd + * @arg EIO_PIN_SET + * @arg EIO_PIN_RESET + * @retval None + */ +void BSP_LCD_RSTCmd(uint8_t u8Cmd) +{ + BSP_IO_WritePortPin(LCD_RST_PORT, LCD_RST_PIN, u8Cmd); +} + +/** + * @brief LCD backlight pin config. + * @param [in] u8Cmd + * @arg EIO_PIN_SET + * @arg EIO_PIN_RESET + * @retval None + */ +void BSP_LCD_BKLCmd(uint8_t u8Cmd) +{ + BSP_IO_WritePortPin(LCD_BKL_PORT, LCD_BKL_PIN, u8Cmd); +} + +/** + * @brief LED initialize. + * @param None + * @retval None + */ +void BSP_LED_Init(void) +{ + /* Turn off LED before output */ + BSP_IO_WritePortPin(LED_PORT, (LED_RED_PIN | LED_YELLOW_PIN | LED_BLUE_PIN), LED_OFF); + /* LED pins set to output */ + BSP_IO_ConfigPortPin(LED_PORT, (LED_RED_PIN | LED_YELLOW_PIN | LED_BLUE_PIN), EIO_DIR_OUT); +} + +/** + * @brief Turn on LEDs. + * @param [in] u8Led LED + * @arg LED_RED + * @arg LED_YELLOW + * @arg LED_BLUE + * @retval None + */ +void BSP_LED_On(uint8_t u8Led) +{ + BSP_IO_WritePortPin(LED_PORT, u8Led, LED_ON); +} + +/** + * @brief Turn off LEDs. + * @param [in] u8Led LED + * @arg LED_RED + * @arg LED_YELLOW + * @arg LED_BLUE + * @retval None + */ +void BSP_LED_Off(uint8_t u8Led) +{ + BSP_IO_WritePortPin(LED_PORT, u8Led, LED_OFF); +} + +/** + * @brief Toggle LEDs. + * @param [in] u8Led LED + * @arg LED_RED + * @arg LED_YELLOW + * @arg LED_BLUE + * @retval None + */ +void BSP_LED_Toggle(uint8_t u8Led) +{ + BSP_IO_TogglePortPin(LED_PORT, u8Led); +} + +/** + * @} + */ + +#endif /* BSP_TCA9539_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_tca9539.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_tca9539.h new file mode 100644 index 0000000000..d222818060 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_tca9539.h @@ -0,0 +1,290 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_tca9539.h + * @brief This file contains all the functions prototypes of the + * ev_hc32f448_lqfp80_tca9539 driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_TCA9539_H__ +#define __EV_HC32F448_LQFP80_TCA9539_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "tca9539.h" +#include "ev_hc32f448_lqfp80.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80_TCA9539 + * @{ + */ + +#if ((BSP_TCA9539_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup BSP_TCA9539_I2C_Configure BSP TCA9539 I2C Configure + * @{ + */ +#define EIO_RST_PORT (GPIO_PORT_B) +#define EIO_RST_PIN (GPIO_PIN_15) + +/* I2C unit define */ +#define BSP_TCA9539_I2C_UNIT (CM_I2C1) +#define BSP_TCA9539_I2C_FCG (FCG1_PERIPH_I2C1) + +/* Define port and pin for SDA and SCL */ +#define BSP_TCA9539_I2C_SCL_PORT (GPIO_PORT_E) +#define BSP_TCA9539_I2C_SCL_PIN (GPIO_PIN_01) +#define BSP_TCA9539_I2C_SDA_PORT (GPIO_PORT_E) +#define BSP_TCA9539_I2C_SDA_PIN (GPIO_PIN_00) +#define BSP_TCA9539_I2C_SCL_FUNC (GPIO_FUNC_49) +#define BSP_TCA9539_I2C_SDA_FUNC (GPIO_FUNC_48) + +/* Define for TCA9539 */ +#define BSP_TCA9539_DEV_ADDR (0x74U) +#define BSP_TCA9539_REG_ADDR_LEN (1U) +/** + * @} + */ + +/** + * @defgroup HC32F448_EV_IO_Exported_Constants IO Exported Constants + * @{ + */ + +/** + * @defgroup HC32F448_EV_IO_Port_Definition HC32F448_EV_IO Port Definition + * @{ + */ +#define EIO_PORT0 (TCA9539_IO_PORT0) +#define EIO_PORT1 (TCA9539_IO_PORT1) +/** + * @} + */ + +/** + * @defgroup HC32F448_EV_IO_Direction_Definition HC32F448_EV_IO Direction Definition + * @{ + */ +#define EIO_DIR_OUT (TCA9539_DIR_OUT) +#define EIO_DIR_IN (TCA9539_DIR_IN) +/** + * @} + */ + +/** + * @defgroup HC32F448_EV_IO_Pin_State_Definition HC32F448_EV_IO Pin State Definition + * @{ + */ +#define EIO_PIN_RESET (TCA9539_PIN_RESET) +#define EIO_PIN_SET (TCA9539_PIN_SET) +/** + * @} + */ + +/** + * @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */ +#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */ +#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */ + +#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */ +#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */ +#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_CAN_PortPin_Sel BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN1_STB_PORT (EIO_PORT1) +#define CAN1_STB_PIN (EIO_CAN1_STB) +#define CAN2_STB_PORT (EIO_PORT1) +#define CAN2_STB_PIN (EIO_CAN2_STB) +/** + * @} + */ + +/** + * @defgroup BSP_LCD_PortPin_Sel BSP LCD panel port/pin definition + * @{ + */ +#define LCD_RST_PORT (EIO_PORT0) +#define LCD_RST_PIN (EIO_LCD_RST) +#define LCD_CTRST_PORT (EIO_PORT0) +#define LCD_CTRST_PIN (EIO_TOUCH_CTRST) +#define LCD_CTINT_PORT (EIO_PORT0) +#define LCD_CTINT_PIN (EIO_TOUCH_INT) +#define LCD_BKL_PORT (EIO_PORT0) +#define LCD_BKL_PIN (EIO_LCD_BKL) +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_PORT (EIO_PORT1) +#define LED_RED_PORT (EIO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (EIO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (EIO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP_LED_Sel BSP LED definition + * @{ + */ +#define LED_RED (EIO_LED_RED) +#define LED_YELLOW (EIO_LED_YELLOW) +#define LED_BLUE (EIO_LED_BLUE) +#define LED_ALL (LED_RED | LED_YELLOW | LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP_LED_OnOff_Sel BSP LED ON/OFF definition + * @{ + */ +#define LED_OFF (EIO_PIN_RESET) +#define LED_ON (EIO_PIN_SET) +/** + * @} + */ + +/** + * @defgroup BSP_LIN_PHY_PortPin_Sel BSP LIN phy port/pin definition + * @{ + */ +#define LIN_SLEEP_PORT (EIO_PORT1) +#define LIN_SLEEP_PIN (EIO_LIN_SLEEP) +/** + * @} + */ + +/** + * @defgroup BSP_Smartcard_PortPin_Sel BSP smartcard port/pin definition + * @{ + */ +#define SMARTCARD_CD_PORT (EIO_PORT0) +#define SMARTCARD_CD_PIN (EIO_SCI_CD) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_TCA9539_Exported_Functions HC32F448 LQFP80 EVB TCA9539 Exported Functions + * @{ + */ +void BSP_IO_Init(void); +void BSP_IO_IntInit(void); + +void BSP_IO_WritePortPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8PinState); +void BSP_IO_ConfigPortPin(uint8_t u8Port, uint8_t u8Pin, uint8_t u8Dir); +uint8_t BSP_IO_ReadPortPin(uint8_t u8Port, uint8_t u8Pin); +void BSP_IO_TogglePortPin(uint8_t u8Port, uint8_t u8Pin); + +void BSP_CAN_STB_IO_Init(void); +void BSP_CAN_STBCmd(uint8_t u8Cmd); + +void BSP_CT_RSTCmd(uint8_t u8Cmd); + +void BSP_LCD_IO_Init(void); +void BSP_LCD_RSTCmd(uint8_t u8Cmd); +void BSP_LCD_BKLCmd(uint8_t u8Cmd); + +void BSP_LED_Init(void); +void BSP_LED_On(uint8_t u8Led); +void BSP_LED_Off(uint8_t u8Led); +void BSP_LED_Toggle(uint8_t u8Led); + +/** + * @} + */ + +#endif /* BSP_TCA9539_ENABLE && BSP_EV_HC32F448_LQFP80 */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_TCA9539__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_w25qxx.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_w25qxx.c new file mode 100644 index 0000000000..d10e788d5a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_w25qxx.c @@ -0,0 +1,324 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_w25qxx.c + * @brief This file provides firmware functions for QSPI/SPI NOR W25QXX. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "ev_hc32f448_lqfp80_w25qxx.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @defgroup EV_HC32F448_LQFP80_W25QXX EV_HC32F448_LQFP80 W25QXX + * @{ + */ + +#if ((BSP_W25QXX_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void BSP_SPI_Init(void); +static void BSP_SPI_DeInit(void); +static void BSP_SPI_Active(void); +static void BSP_SPI_Inactive(void); +static int32_t BSP_SPI_Trans(const uint8_t *pu8TxBuf, uint32_t u32Size); +static int32_t BSP_SPI_Receive(uint8_t *pu8RxBuf, uint32_t u32Size); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static stc_w25qxx_ll_t m_stcW25qxxLL = { + .Delay = DDL_DelayMS, + .Init = BSP_SPI_Init, + .DeInit = BSP_SPI_DeInit, + .Active = BSP_SPI_Active, + .Inactive = BSP_SPI_Inactive, + .Trans = BSP_SPI_Trans, + .Receive = BSP_SPI_Receive, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EV_HC32F448_LQFP80_W25QXX_Local_Functions EV_HC32F448_LQFP80 W25QXX Local Functions + * @{ + */ + +/** + * @brief SPI CS active. + * @param None + * @retval None + */ +static void BSP_SPI_Active(void) +{ + BSP_SPI_CS_ACTIVE(); +} + +/** + * @brief SPI CS inactive. + * @param None + * @retval None + */ +static void BSP_SPI_Inactive(void) +{ + BSP_SPI_CS_INACTIVE(); +} + +/** + * @brief Initializes the BSP SPI interface. + * @param None + * @retval None + */ +static void BSP_SPI_Init(void) +{ + stc_gpio_init_t stcGpioInit; + stc_spi_init_t stcSpiInit; + stc_spi_delay_t stcSpiDelayCfg; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(BSP_SPI_SCK_PORT, BSP_SPI_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(BSP_SPI_MOSI_PORT, BSP_SPI_MOSI_PIN, &stcGpioInit); + stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinState = PIN_STAT_SET; + (void)GPIO_Init(BSP_SPI_CS_PORT, BSP_SPI_CS_PIN, &stcGpioInit); + + GPIO_SetFunc(BSP_SPI_SCK_PORT, BSP_SPI_SCK_PIN, BSP_SPI_SCK_PIN_FUNC); + GPIO_SetFunc(BSP_SPI_MOSI_PORT, BSP_SPI_MOSI_PIN, BSP_SPI_MOSI_PIN_FUNC); + GPIO_SetFunc(BSP_SPI_MISO_PORT, BSP_SPI_MISO_PIN, BSP_SPI_MISO_PIN_FUNC); + + /* Clear initialize structure */ + (void)SPI_StructInit(&stcSpiInit); + (void)SPI_DelayStructInit(&stcSpiDelayCfg); + + /* Configure peripheral clock */ + FCG_Fcg1PeriphClockCmd(BSP_SPI_PERIPH_CLK, ENABLE); + + /* SPI De-initialize */ + (void)SPI_DeInit(BSP_SPI_UNIT); + /* Configuration SPI structure */ + stcSpiInit.u32WireMode = SPI_4_WIRE; + stcSpiInit.u32TransMode = SPI_FULL_DUPLEX; + stcSpiInit.u32MasterSlave = SPI_MASTER; + stcSpiInit.u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; + stcSpiInit.u32Parity = SPI_PARITY_INVD; + stcSpiInit.u32SpiMode = SPI_MD_0; + stcSpiInit.u32BaudRatePrescaler = SPI_BR_CLK_DIV64; + stcSpiInit.u32DataBits = SPI_DATA_SIZE_8BIT; + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; + (void)SPI_Init(BSP_SPI_UNIT, &stcSpiInit); + + stcSpiDelayCfg.u32IntervalDelay = SPI_INTERVAL_TIME_8SCK; + stcSpiDelayCfg.u32ReleaseDelay = SPI_RELEASE_TIME_8SCK; + stcSpiDelayCfg.u32SetupDelay = SPI_SETUP_TIME_1SCK; + (void)SPI_DelayTimeConfig(BSP_SPI_UNIT, &stcSpiDelayCfg); + SPI_Cmd(BSP_SPI_UNIT, ENABLE); +} + +/** + * @brief De-Initialize the BSP SPI interface. + * @param None + * @retval None + */ +static void BSP_SPI_DeInit(void) +{ + /* SPI De-initialize */ + (void)SPI_DeInit(BSP_SPI_UNIT); +} + +/** + * @brief BSP SPI transmit data. + * @param [in] pu8TxBuf The data buffer that to be transmitted. + * @param [in] u32Size Number of data bytes to be transmitted. + * @retval int32_t: + * - LL_OK: Data transmission successful. + * - LL_ERR_TIMEOUT: Data transmission timeout. + */ +static int32_t BSP_SPI_Trans(const uint8_t *pu8TxBuf, uint32_t u32Size) +{ + return SPI_Trans(BSP_SPI_UNIT, pu8TxBuf, u32Size, BSP_SPI_TIMEOUT); +} + +/** + * @brief BSP SPI receive data. + * @param [in] pu8RxBuf The buffer that received data to be stored. + * @param [in] u32Size Number of data bytes to be received. + * @retval int32_t: + * - LL_OK: Data receive successful. + * - LL_ERR_TIMEOUT: Data receive timeout. + */ +static int32_t BSP_SPI_Receive(uint8_t *pu8RxBuf, uint32_t u32Size) +{ + return SPI_Receive(BSP_SPI_UNIT, pu8RxBuf, u32Size, BSP_SPI_TIMEOUT); +} + +/** + * @} + */ + +/** + * @defgroup EV_HC32F448_LQFP80_W25QXX_Global_Functions EV_HC32F448_LQFP80 W25QXX Global Functions + * @{ + */ + +/** + * @brief Initializes BSP W25QXX. + * @param None + * @retval None + */ +void BSP_W25QXX_Init(void) +{ + (void)W25QXX_Init(&m_stcW25qxxLL); +} + +/** + * @brief De-Initializes BSP W25QXX. + * @param None + * @retval None + */ +void BSP_W25QXX_DeInit(void) +{ + (void)W25QXX_DeInit(&m_stcW25qxxLL); +} + +/** + * @brief Writes an amount of data to W25QXX via SPI interface. + * @param [in] u32Addr Write start address. + * @param [in] pu8Data Pointer to data to be written. + * @param [in] u32NumByteToWrite Size of data to write. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +int32_t BSP_W25QXX_Write(uint32_t u32Addr, const uint8_t *pu8Data, uint32_t u32NumByteToWrite) +{ + uint32_t u32TempSize; + uint32_t u32AddrOfst = 0UL; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT((u32Addr + u32NumByteToWrite) <= W25Q64_MAX_ADDR); + + if ((pu8Data != NULL) && (u32NumByteToWrite > 0UL)) { + while (u32NumByteToWrite != 0UL) { + if (u32NumByteToWrite >= W25Q64_PAGE_SIZE) { + u32TempSize = W25Q64_PAGE_SIZE; + } else { + u32TempSize = u32NumByteToWrite; + } + + i32Ret = W25QXX_PageProgram(&m_stcW25qxxLL, u32Addr, (const uint8_t *)&pu8Data[u32AddrOfst], u32TempSize); + if (i32Ret != LL_OK) { + break; + } + u32NumByteToWrite -= u32TempSize; + u32AddrOfst += u32TempSize; + u32Addr += u32TempSize; + } + } + + return i32Ret; +} + +/** + * @brief Reads an amount of data to W25QXX via SPI interface. + * @param [in] u32Addr Read start address. + * @param [in] pu8Data Pointer to data to be read. + * @param [in] u32NumByteToRead Size of data to read. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +int32_t BSP_W25QXX_Read(uint32_t u32Addr, uint8_t *pu8Data, uint32_t u32NumByteToRead) +{ + DDL_ASSERT((u32Addr + u32NumByteToRead) <= W25Q64_MAX_ADDR); + return W25QXX_ReadData(&m_stcW25qxxLL, u32Addr, pu8Data, u32NumByteToRead); +} + +/** + * @brief Erases specified sector of W25QXX. + * @param [in] u32Addr Any address of the specified sector. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +int32_t BSP_W25QXX_EraseSector(uint32_t u32Addr) +{ + DDL_ASSERT(u32Addr < W25Q64_MAX_ADDR); + return W25QXX_EraseSector(&m_stcW25qxxLL, u32Addr); +} + +/** + * @brief Erases W25QXX whole chip. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: SPI timeout or W25QXX timeout. + */ +int32_t BSP_W25QXX_EraseChip(void) +{ + return W25QXX_EraseChip(&m_stcW25qxxLL); +} + +/** + * @} + */ + +#endif /* (BSP_W25QXX_ENABLE && BSP_EV_HC32F448_LQFP80) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_w25qxx.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_w25qxx.h new file mode 100644 index 0000000000..3d5878359c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/bsp/ev_hc32f448_lqfp80/ev_hc32f448_lqfp80_w25qxx.h @@ -0,0 +1,162 @@ +/** + ******************************************************************************* + * @file ev_hc32f448_lqfp80_w25qxx.h + * @brief This file contains all the functions prototypes of the + ev_hc32f448_lqfp80_w25qxx driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __EV_HC32F448_LQFP80_W25QXX_H__ +#define __EV_HC32F448_LQFP80_W25QXX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "w25qxx.h" +#include "ev_hc32f448_lqfp80.h" + +/** + * @addtogroup BSP + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80 + * @{ + */ + +/** + * @addtogroup EV_HC32F448_LQFP80_W25QXX + * @{ + */ + +#if ((BSP_W25QXX_ENABLE == DDL_ON) && (BSP_EV_HC32F448_LQFP80 == BSP_EV_HC32F4XX)) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup W25Qxx_SPI_Instance W25Qxx SPI Instance + * @{ + */ +#define BSP_SPI_UNIT CM_SPI1 +#define BSP_SPI_PERIPH_CLK FCG1_PERIPH_SPI1 +/** + * @} + */ + +/** + * @defgroup BSP_SPI_Port BSP SPI Port + * @{ + */ +#define BSP_SPI_CS_PORT (GPIO_PORT_C) +#define BSP_SPI_CS_PIN (GPIO_PIN_07) +#define BSP_SPI_CS_PIN_FUNC (GPIO_FUNC_46) +#define BSP_SPI_CS_ACTIVE() (GPIO_ResetPins(BSP_SPI_CS_PORT, BSP_SPI_CS_PIN)) +#define BSP_SPI_CS_INACTIVE() (GPIO_SetPins(BSP_SPI_CS_PORT, BSP_SPI_CS_PIN)) + +#define BSP_SPI_SCK_PORT (GPIO_PORT_B) +#define BSP_SPI_SCK_PIN (GPIO_PIN_14) +#define BSP_SPI_SCK_PIN_FUNC (GPIO_FUNC_47) + +#define BSP_SPI_MOSI_PORT (GPIO_PORT_B) +#define BSP_SPI_MOSI_PIN (GPIO_PIN_13) +#define BSP_SPI_MOSI_PIN_FUNC (GPIO_FUNC_44) + +#define BSP_SPI_MISO_PORT (GPIO_PORT_D) +#define BSP_SPI_MISO_PIN (GPIO_PIN_09) +#define BSP_SPI_MISO_PIN_FUNC (GPIO_FUNC_45) +/** + * @} + */ + +/** + * @defgroup W25Qxx_SPI_Timeout W25Qxx SPI Timeout + * @{ + */ +#define BSP_SPI_TIMEOUT (HCLK_VALUE) +/** + * @} + */ + +/** + * @defgroup W25Q64_Size W25Q64 Size + * @{ + */ +#define W25Q64_PAGE_SIZE (256UL) +#define W25Q64_SECTOR_SIZE (1024UL * 4UL) +#define W25Q64_BLOCK_SIZE (1024UL * 64UL) +#define W25Q64_PAGE_PER_SECTOR (W25Q64_SECTOR_SIZE / W25Qs64_PAGE_SIZE) +#define W25Q64_MAX_ADDR (0x800000UL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EV_HC32F448_LQFP80_W25QXX_Global_Functions + * @{ + */ + +void BSP_W25QXX_Init(void); +void BSP_W25QXX_DeInit(void); +int32_t BSP_W25QXX_Write(uint32_t u32Addr, const uint8_t *pu8Data, uint32_t u32NumByteToWrite); +int32_t BSP_W25QXX_Read(uint32_t u32Addr, uint8_t *pu8Data, uint32_t u32NumByteToRead); +int32_t BSP_W25QXX_EraseSector(uint32_t u32Addr); +int32_t BSP_W25QXX_EraseChip(void); + +/** + * @} + */ + +#endif /* (BSP_W25QXX_ENABLE && BSP_EV_HC32F448_LQFP80) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EV_HC32F448_LQFP80_W25QXX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f448.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f448.h new file mode 100644 index 0000000000..78e39e9916 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f448.h @@ -0,0 +1,13622 @@ +/** + ******************************************************************************* + * @file HC32F448.h + * @brief Headerfile for HC32F448 series MCU + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Optimize TMR4_OCMRxx + Rename EMB_CTL1 register bit: SRAMERREN -> SRAMECCERREN + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + **/ + +#ifndef __HC32F448_H__ +#define __HC32F448_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /*!< HC32F448 provides MPU */ +#define __VTOR_PRESENT 1 /*!< HC32F448 supported vector table registers */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F448 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum { + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManageFault_IRQn = -12, /* 4 MemManage Fault */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SVCall */ + DebugMonitor_IRQn = -4, /* 12 DebugMonitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + INT000_IRQn = 0, + INT001_IRQn = 1, + INT002_IRQn = 2, + INT003_IRQn = 3, + INT004_IRQn = 4, + INT005_IRQn = 5, + INT006_IRQn = 6, + INT007_IRQn = 7, + INT008_IRQn = 8, + INT009_IRQn = 9, + INT010_IRQn = 10, + INT011_IRQn = 11, + INT012_IRQn = 12, + INT013_IRQn = 13, + INT014_IRQn = 14, + INT015_IRQn = 15, + EXTINT_PORT_EIRQ0_IRQn = 16, + EXTINT_PORT_EIRQ1_IRQn = 17, + EXTINT_PORT_EIRQ2_IRQn = 18, + EXTINT_PORT_EIRQ3_IRQn = 19, + EXTINT_PORT_EIRQ4_IRQn = 20, + EXTINT_PORT_EIRQ5_IRQn = 21, + EXTINT_PORT_EIRQ6_IRQn = 22, + EXTINT_PORT_EIRQ7_IRQn = 23, + EXTINT_PORT_EIRQ8_IRQn = 24, + EXTINT_PORT_EIRQ9_IRQn = 25, + EXTINT_PORT_EIRQ10_IRQn = 26, + EXTINT_PORT_EIRQ11_IRQn = 27, + EXTINT_PORT_EIRQ12_IRQn = 28, + EXTINT_PORT_EIRQ13_IRQn = 29, + EXTINT_PORT_EIRQ14_IRQn = 30, + EXTINT_PORT_EIRQ15_IRQn = 31, + SWINT0_IRQn = 0, + SWINT1_IRQn = 1, + SWINT2_IRQn = 2, + SWINT3_IRQn = 3, + SWINT4_IRQn = 4, + SWINT5_IRQn = 5, + SWINT6_IRQn = 6, + SWINT7_IRQn = 7, + SWINT8_IRQn = 8, + SWINT9_IRQn = 9, + SWINT10_IRQn = 10, + SWINT11_IRQn = 11, + SWINT12_IRQn = 12, + SWINT13_IRQn = 13, + SWINT14_IRQn = 14, + SWINT15_IRQn = 15, + SWINT16_IRQn = 16, + SWINT17_IRQn = 17, + SWINT18_IRQn = 18, + SWINT19_IRQn = 19, + SWINT20_IRQn = 20, + SWINT21_IRQn = 21, + SWINT22_IRQn = 22, + SWINT23_IRQn = 23, + SWINT24_IRQn = 24, + SWINT25_IRQn = 25, + SWINT26_IRQn = 26, + SWINT27_IRQn = 27, + SWINT28_IRQn = 28, + SWINT29_IRQn = 29, + SWINT30_IRQn = 30, + SWINT31_IRQn = 31, + DMA1_ERR_IRQn = 32, + DMA1_TC0_BTC0_IRQn = 33, + DMA1_TC1_BTC1_IRQn = 34, + DMA1_TC2_BTC2_IRQn = 35, + DMA1_TC3_BTC3_IRQn = 36, + DMA1_TC4_BTC4_IRQn = 37, + DMA1_TC5_BTC5_IRQn = 38, + EFM_PEERR_RDCOL_IRQn = 39, + EFM_OPTEND_IRQn = 40, + QSPI_IRQn = 41, + DCU1_IRQn = 42, + DCU2_IRQn = 43, + DCU3_IRQn = 44, + DCU4_IRQn = 45, + DMA2_ERR_IRQn = 46, + DMA2_TC0_BTC0_IRQn = 47, + DMA2_TC1_BTC1_IRQn = 48, + DMA2_TC2_BTC2_IRQn = 49, + DMA2_TC3_BTC3_IRQn = 50, + DMA2_TC4_BTC4_IRQn = 51, + DMA2_TC5_BTC5_IRQn = 52, + TMR0_1_IRQn = 53, + TMR0_2_IRQn = 54, + RTC_IRQn = 55, + XTAL_IRQn = 56, + WKTM_IRQn = 57, + SWDT_IRQn = 58, + TMR6_1_GCMP_IRQn = 59, + TMR6_1_OVF_UDF_IRQn = 60, + TMR6_1_DTE_IRQn = 61, + TMR6_1_SCMP_IRQn = 62, + TMRA_1_OVF_UDF_IRQn = 63, + TMRA_1_CMP_IRQn = 64, + TMR6_2_GCMP_IRQn = 65, + TMR6_2_OVF_UDF_IRQn = 66, + TMR6_2_DTE_IRQn = 67, + TMR6_2_SCMP_IRQn = 68, + TMRA_2_OVF_UDF_IRQn = 69, + TMRA_2_CMP_IRQn = 70, + TMRA_3_OVF_UDF_IRQn = 71, + TMRA_3_CMP_IRQn = 72, + TMRA_4_OVF_UDF_IRQn = 73, + TMRA_4_CMP_IRQn = 74, + TMR4_1_GCMP_IRQn = 75, + TMR4_1_OVF_UDF_IRQn = 76, + TMR4_1_RELOAD_IRQn = 77, + TMR4_1_SCMP_IRQn = 78, + TMR4_2_GCMP_IRQn = 79, + TMR4_2_OVF_UDF_IRQn = 80, + TMR4_2_RELOAD_IRQn = 81, + TMR4_2_SCMP_IRQn = 82, + TMR4_3_GCMP_IRQn = 83, + TMR4_3_OVF_UDF_IRQn = 84, + TMR4_3_RELOAD_IRQn = 85, + TMR4_3_SCMP_IRQn = 86, + I2C1_IRQn = 87, + I2C2_IRQn = 88, + CMP1_IRQ_IRQn = 89, + CMP2_IRQ_IRQn = 90, + CMP3_IRQ_IRQn = 91, + CMP4_IRQ_IRQn = 92, + USART1_IRQn = 93, + USART1_TCI_IRQn = 94, + USART2_IRQn = 95, + USART2_TCI_IRQn = 96, + SPI1_IRQn = 97, + TMRA_5_OVF_UDF_IRQn = 98, + TMRA_5_CMP_IRQn = 99, + EVENT_PORT1_IRQn = 100, + EVENT_PORT2_IRQn = 101, + EVENT_PORT3_IRQn = 102, + EVENT_PORT4_IRQn = 103, + USART3_IRQn = 104, + USART3_TCI_IRQn = 105, + USART4_IRQn = 106, + USART4_TCI_IRQn = 107, + SPI2_IRQn = 108, + SPI3_IRQn = 109, + EMB_GR0_IRQn = 110, + EMB_GR1_IRQn = 111, + EMB_GR2_IRQn = 112, + EMB_GR3_IRQn = 113, + USART5_IRQn = 114, + USART5_TCI_IRQn = 115, + USART6_IRQn = 116, + USART6_TCI_IRQn = 117, + MCAN1_INT0_IRQn = 118, + MCAN1_INT1_IRQn = 119, + MCAN2_INT0_IRQn = 120, + MCAN2_INT1_IRQn = 121, + USART1_WUPI_IRQn = 122, + FCM_IRQn = 125, + WDT_IRQn = 126, + CTC_IRQn = 127, + ADC1_IRQn = 128, + ADC2_IRQn = 129, + ADC3_IRQn = 130, + TRNG_IRQn = 131, +} IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum { + EVT_SRC_SWI_IRQ0 = 0U, + EVT_SRC_SWI_IRQ1 = 1U, + EVT_SRC_SWI_IRQ2 = 2U, + EVT_SRC_SWI_IRQ3 = 3U, + EVT_SRC_SWI_IRQ4 = 4U, + EVT_SRC_SWI_IRQ5 = 5U, + EVT_SRC_SWI_IRQ6 = 6U, + EVT_SRC_SWI_IRQ7 = 7U, + EVT_SRC_SWI_IRQ8 = 8U, + EVT_SRC_SWI_IRQ9 = 9U, + EVT_SRC_SWI_IRQ10 = 10U, + EVT_SRC_SWI_IRQ11 = 11U, + EVT_SRC_SWI_IRQ12 = 12U, + EVT_SRC_SWI_IRQ13 = 13U, + EVT_SRC_SWI_IRQ14 = 14U, + EVT_SRC_SWI_IRQ15 = 15U, + EVT_SRC_SWI_IRQ16 = 16U, + EVT_SRC_SWI_IRQ17 = 17U, + EVT_SRC_SWI_IRQ18 = 18U, + EVT_SRC_SWI_IRQ19 = 19U, + EVT_SRC_SWI_IRQ20 = 20U, + EVT_SRC_SWI_IRQ21 = 21U, + EVT_SRC_SWI_IRQ22 = 22U, + EVT_SRC_SWI_IRQ23 = 23U, + EVT_SRC_SWI_IRQ24 = 24U, + EVT_SRC_SWI_IRQ25 = 25U, + EVT_SRC_SWI_IRQ26 = 26U, + EVT_SRC_SWI_IRQ27 = 27U, + EVT_SRC_SWI_IRQ28 = 28U, + EVT_SRC_SWI_IRQ29 = 29U, + EVT_SRC_SWI_IRQ30 = 30U, + EVT_SRC_SWI_IRQ31 = 31U, + /* External Interrupt */ + EVT_SRC_PORT_EIRQ0 = 0U, /* EIRQ0 */ + EVT_SRC_PORT_EIRQ1 = 1U, /* EIRQ1 */ + EVT_SRC_PORT_EIRQ2 = 2U, /* EIRQ2 */ + EVT_SRC_PORT_EIRQ3 = 3U, /* EIRQ3 */ + EVT_SRC_PORT_EIRQ4 = 4U, /* EIRQ4 */ + EVT_SRC_PORT_EIRQ5 = 5U, /* EIRQ5 */ + EVT_SRC_PORT_EIRQ6 = 6U, /* EIRQ6 */ + EVT_SRC_PORT_EIRQ7 = 7U, /* EIRQ7 */ + EVT_SRC_PORT_EIRQ8 = 8U, /* EIRQ8 */ + EVT_SRC_PORT_EIRQ9 = 9U, /* EIRQ9 */ + EVT_SRC_PORT_EIRQ10 = 10U, /* EIRQ10 */ + EVT_SRC_PORT_EIRQ11 = 11U, /* EIRQ11 */ + EVT_SRC_PORT_EIRQ12 = 12U, /* EIRQ12 */ + EVT_SRC_PORT_EIRQ13 = 13U, /* EIRQ13 */ + EVT_SRC_PORT_EIRQ14 = 14U, /* EIRQ14 */ + EVT_SRC_PORT_EIRQ15 = 15U, /* EIRQ15 */ + /* DMA_1 */ + EVT_SRC_DMA1_TC0 = 33U, /* DMA_1_TC0 */ + EVT_SRC_DMA1_BTC0 = 34U, /* DMA_1_BTC0 */ + EVT_SRC_DMA1_TC1 = 35U, /* DMA_1_TC1 */ + EVT_SRC_DMA1_BTC1 = 36U, /* DMA_1_BTC1 */ + EVT_SRC_DMA1_TC2 = 37U, /* DMA_1_TC2 */ + EVT_SRC_DMA1_BTC2 = 38U, /* DMA_1_BTC2 */ + EVT_SRC_DMA1_TC3 = 39U, /* DMA_1_TC3 */ + EVT_SRC_DMA1_BTC3 = 40U, /* DMA_1_BTC3 */ + EVT_SRC_DMA1_TC4 = 41U, /* DMA_1_TC4 */ + EVT_SRC_DMA1_BTC4 = 42U, /* DMA_1_BTC4 */ + EVT_SRC_DMA1_TC5 = 43U, /* DMA_1_TC5 */ + EVT_SRC_DMA1_BTC5 = 44U, /* DMA_1_BTC5 */ + /* EFM */ + EVT_SRC_EFM_OPTEND = 51U, /* EFM_OPTEND */ + /* DCU */ + EVT_SRC_DCU1 = 55U, /* DCU1 */ + EVT_SRC_DCU2 = 56U, /* DCU2 */ + EVT_SRC_DCU3 = 57U, /* DCU3 */ + EVT_SRC_DCU4 = 58U, /* DCU4 */ + /* DMA2 */ + EVT_SRC_DMA2_TC0 = 65U, /* DMA_2_TC0 */ + EVT_SRC_DMA2_BTC0 = 66U, /* DMA_2_BTC0 */ + EVT_SRC_DMA2_TC1 = 67U, /* DMA_2_TC1 */ + EVT_SRC_DMA2_BTC1 = 68U, /* DMA_2_BTC1 */ + EVT_SRC_DMA2_TC2 = 69U, /* DMA_2_TC2 */ + EVT_SRC_DMA2_BTC2 = 70U, /* DMA_2_BTC2 */ + EVT_SRC_DMA2_TC3 = 71U, /* DMA_2_TC3 */ + EVT_SRC_DMA2_BTC3 = 72U, /* DMA_2_BTC3 */ + EVT_SRC_DMA2_TC4 = 73U, /* DMA_2_TC4 */ + EVT_SRC_DMA2_BTC4 = 74U, /* DMA_2_BTC4 */ + EVT_SRC_DMA2_TC5 = 75U, /* DMA_2_TC5 */ + EVT_SRC_DMA2_BTC5 = 76U, /* DMA_2_BTC5 */ + /* TIMER0 */ + EVT_SRC_TMR0_1_CMP_A = 96U, /* TMR0_1_CMPA */ + EVT_SRC_TMR0_1_CMP_B = 97U, /* TMR0_1_CMPB */ + EVT_SRC_TMR0_1_OVF_A = 98U, /* TMR0_1_OVFA */ + EVT_SRC_TMR0_1_OVF_B = 99U, /* TMR0_1_OVFB */ + EVT_SRC_TMR0_2_CMP_A = 100U, /* TMR0_2_CMPA */ + EVT_SRC_TMR0_2_CMP_B = 101U, /* TMR0_2_CMPB */ + EVT_SRC_TMR0_2_OVF_A = 102U, /* TMR0_2_OVFA */ + EVT_SRC_TMR0_2_OVF_B = 103U, /* TMR0_2_OVFB */ + /* RTC */ + EVT_SRC_RTC_ALM = 121U, /* RTC_ALM */ + EVT_SRC_RTC_PRD = 122U, /* RTC_PRD */ + /* TIMER6_1 */ + EVT_SRC_TMR6_1_GCMP_A = 128U, /* TMR6_1_GCMA */ + EVT_SRC_TMR6_1_GCMP_B = 129U, /* TMR6_1_GCMB */ + EVT_SRC_TMR6_1_GCMP_C = 130U, /* TMR6_1_GCMC */ + EVT_SRC_TMR6_1_GCMP_D = 131U, /* TMR6_1_GCMD */ + EVT_SRC_TMR6_1_GCMP_E = 132U, /* TMR6_1_GCME */ + EVT_SRC_TMR6_1_GCMP_F = 133U, /* TMR6_1_GCMF */ + EVT_SRC_TMR6_1_OVF = 134U, /* TMR6_1_GOVF */ + EVT_SRC_TMR6_1_UDF = 135U, /* TMR6_1_GUDF */ + EVT_SRC_TMR6_1_SCMP_A = 137U, /* TMR6_1_SCMA */ + EVT_SRC_TMR6_1_SCMP_B = 138U, /* TMR6_1_SCMB */ + /* TIMERA_1 */ + EVT_SRC_TMRA_1_OVF = 139U, /* TMRA_1_OVF */ + EVT_SRC_TMRA_1_UDF = 140U, /* TMRA_1_UDF */ + EVT_SRC_TMRA_1_CMP = 141U, /* TMRA_1_CMP */ + /* TIMER6_2 */ + EVT_SRC_TMR6_2_GCMP_A = 144U, /* TMR6_2_GCMA */ + EVT_SRC_TMR6_2_GCMP_B = 145U, /* TMR6_2_GCMB */ + EVT_SRC_TMR6_2_GCMP_C = 146U, /* TMR6_2_GCMC */ + EVT_SRC_TMR6_2_GCMP_D = 147U, /* TMR6_2_GCMD */ + EVT_SRC_TMR6_2_GCMP_E = 148U, /* TMR6_2_GCME */ + EVT_SRC_TMR6_2_GCMP_F = 149U, /* TMR6_2_GCMF */ + EVT_SRC_TMR6_2_OVF = 150U, /* TMR6_2_GOVF */ + EVT_SRC_TMR6_2_UDF = 151U, /* TMR6_2_GUDF */ + EVT_SRC_TMR6_2_SCMP_A = 153U, /* TMR6_2_SCMA */ + EVT_SRC_TMR6_2_SCMP_B = 154U, /* TMR6_2_SCMB */ + /* TIMERA_2 */ + EVT_SRC_TMRA_2_OVF = 155U, /* TMRA_2_OVF */ + EVT_SRC_TMRA_2_UDF = 156U, /* TMRA_2_UDF */ + EVT_SRC_TMRA_2_CMP = 157U, /* TMRA_2_CMP */ + /* TIMERA_3 */ + EVT_SRC_TMRA_3_OVF = 171U, /* TMRA_3_OVF */ + EVT_SRC_TMRA_3_UDF = 172U, /* TMRA_3_UDF */ + EVT_SRC_TMRA_3_CMP = 173U, /* TMRA_3_CMP */ + /* TIMERA_4 */ + EVT_SRC_TMRA_4_OVF = 187U, /* TMRA_4_OVF */ + EVT_SRC_TMRA_4_UDF = 188U, /* TMRA_4_UDF */ + EVT_SRC_TMRA_4_CMP = 189U, /* TMRA_4_CMP */ + /* TIMER4_1 */ + EVT_SRC_TMR4_1_GCMP_UH = 192U, /* TMR4_1_GCMUH */ + EVT_SRC_TMR4_1_GCMP_UL = 193U, /* TMR4_1_GCMUL */ + EVT_SRC_TMR4_1_GCMP_VH = 194U, /* TMR4_1_GCMVH */ + EVT_SRC_TMR4_1_GCMP_VL = 195U, /* TMR4_1_GCMVL */ + EVT_SRC_TMR4_1_GCMP_WH = 196U, /* TMR4_1_GCMWH */ + EVT_SRC_TMR4_1_GCMP_WL = 197U, /* TMR4_1_GCMWL */ + EVT_SRC_TMR4_1_GCMP_XH = 198U, /* TMR4_1_GCMXH */ + EVT_SRC_TMR4_1_GCMP_XL = 199U, /* TMR4_1_GCMXL */ + EVT_SRC_TMR4_1_OVF = 200U, /* TMR4_1_GOVF */ + EVT_SRC_TMR4_1_UDF = 201U, /* TMR4_1_GUDF */ + EVT_SRC_TMR4_1_RELOAD_U = 202U, /* TMR4_1_GRLU */ + EVT_SRC_TMR4_1_RELOAD_V = 203U, /* TMR4_1_GRLV */ + EVT_SRC_TMR4_1_RELOAD_W = 204U, /* TMR4_1_GRLW */ + EVT_SRC_TMR4_1_RELOAD_X = 205U, /* TMR4_1_GRLX */ + EVT_SRC_TMR4_1_SCMP0 = 206U, /* TMR4_1_SCM0 */ + EVT_SRC_TMR4_1_SCMP1 = 207U, /* TMR4_1_SCM1 */ + EVT_SRC_TMR4_1_SCMP2 = 208U, /* TMR4_1_SCM2 */ + EVT_SRC_TMR4_1_SCMP3 = 209U, /* TMR4_1_SCM3 */ + EVT_SRC_TMR4_1_SCMP4 = 210U, /* TMR4_1_SCM4 */ + EVT_SRC_TMR4_1_SCMP5 = 211U, /* TMR4_1_SCM5 */ + EVT_SRC_TMR4_1_SCMP6 = 212U, /* TMR4_1_SCM6 */ + EVT_SRC_TMR4_1_SCMP7 = 213U, /* TMR4_1_SCM7 */ + /* TIMER4_2 */ + EVT_SRC_TMR4_2_GCMP_UH = 224U, /* TMR4_2_GCMUH */ + EVT_SRC_TMR4_2_GCMP_UL = 225U, /* TMR4_2_GCMUL */ + EVT_SRC_TMR4_2_GCMP_VH = 226U, /* TMR4_2_GCMVH */ + EVT_SRC_TMR4_2_GCMP_VL = 227U, /* TMR4_2_GCMVL */ + EVT_SRC_TMR4_2_GCMP_WH = 228U, /* TMR4_2_GCMWH */ + EVT_SRC_TMR4_2_GCMP_WL = 229U, /* TMR4_2_GCMWL */ + EVT_SRC_TMR4_2_GCMP_XH = 230U, /* TMR4_2_GCMXH */ + EVT_SRC_TMR4_2_GCMP_XL = 231U, /* TMR4_2_GCMXL */ + EVT_SRC_TMR4_2_OVF = 232U, /* TMR4_2_GOVF */ + EVT_SRC_TMR4_2_UDF = 233U, /* TMR4_2_GUDF */ + EVT_SRC_TMR4_2_RELOAD_U = 234U, /* TMR4_2_GRLU */ + EVT_SRC_TMR4_2_RELOAD_V = 235U, /* TMR4_2_GRLV */ + EVT_SRC_TMR4_2_RELOAD_W = 236U, /* TMR4_2_GRLW */ + EVT_SRC_TMR4_2_RELOAD_X = 237U, /* TMR4_2_GRLX */ + EVT_SRC_TMR4_2_SCMP0 = 238U, /* TMR4_2_SCM0 */ + EVT_SRC_TMR4_2_SCMP1 = 239U, /* TMR4_2_SCM1 */ + EVT_SRC_TMR4_2_SCMP2 = 240U, /* TMR4_2_SCM2 */ + EVT_SRC_TMR4_2_SCMP3 = 241U, /* TMR4_2_SCM3 */ + EVT_SRC_TMR4_2_SCMP4 = 242U, /* TMR4_2_SCM4 */ + EVT_SRC_TMR4_2_SCMP5 = 243U, /* TMR4_2_SCM5 */ + EVT_SRC_TMR4_2_SCMP6 = 244U, /* TMR4_2_SCM6 */ + EVT_SRC_TMR4_2_SCMP7 = 245U, /* TMR4_2_SCM7 */ + /* TIMER4_3 */ + EVT_SRC_TMR4_3_GCMP_UH = 256U, /* TMR4_3_GCMUH */ + EVT_SRC_TMR4_3_GCMP_UL = 257U, /* TMR4_3_GCMUL */ + EVT_SRC_TMR4_3_GCMP_VH = 258U, /* TMR4_3_GCMVH */ + EVT_SRC_TMR4_3_GCMP_VL = 259U, /* TMR4_3_GCMVL */ + EVT_SRC_TMR4_3_GCMP_WH = 260U, /* TMR4_3_GCMWH */ + EVT_SRC_TMR4_3_GCMP_WL = 261U, /* TMR4_3_GCMWL */ + EVT_SRC_TMR4_3_GCMP_XH = 262U, /* TMR4_3_GCMXH */ + EVT_SRC_TMR4_3_GCMP_XL = 263U, /* TMR4_3_GCMXL */ + EVT_SRC_TMR4_3_OVF = 264U, /* TMR4_3_GOVF */ + EVT_SRC_TMR4_3_UDF = 265U, /* TMR4_3_GUDF */ + EVT_SRC_TMR4_3_RELOAD_U = 266U, /* TMR4_3_GRLU */ + EVT_SRC_TMR4_3_RELOAD_V = 267U, /* TMR4_3_GRLV */ + EVT_SRC_TMR4_3_RELOAD_W = 268U, /* TMR4_3_GRLW */ + EVT_SRC_TMR4_3_RELOAD_X = 269U, /* TMR4_3_GRLX */ + EVT_SRC_TMR4_3_SCMP0 = 270U, /* TMR4_3_SCM0 */ + EVT_SRC_TMR4_3_SCMP1 = 271U, /* TMR4_3_SCM1 */ + EVT_SRC_TMR4_3_SCMP2 = 272U, /* TMR4_3_SCM2 */ + EVT_SRC_TMR4_3_SCMP3 = 273U, /* TMR4_3_SCM3 */ + EVT_SRC_TMR4_3_SCMP4 = 274U, /* TMR4_3_SCM4 */ + EVT_SRC_TMR4_3_SCMP5 = 275U, /* TMR4_3_SCM5 */ + EVT_SRC_TMR4_3_SCMP6 = 276U, /* TMR4_3_SCM6 */ + EVT_SRC_TMR4_3_SCMP7 = 277U, /* TMR4_3_SCM7 */ + /* I2C1 */ + EVT_SRC_I2C1_RXI = 288U, /* I2C_1_RXI */ + EVT_SRC_I2C1_TXI = 289U, /* I2C_1_TXI */ + EVT_SRC_I2C1_TEI = 290U, /* I2C_1_TEI */ + EVT_SRC_I2C1_EEI = 291U, /* I2C_1_EEI */ + /* I2C2 */ + EVT_SRC_I2C2_RXI = 292U, /* I2C_2_RXI */ + EVT_SRC_I2C2_TXI = 293U, /* I2C_2_TXI */ + EVT_SRC_I2C2_TEI = 294U, /* I2C_2_TEI */ + EVT_SRC_I2C2_EEI = 295U, /* I2C_2_EEI */ + /* CMP */ + EVT_SRC_CMP1 = 312U, /* CMP_1_IRQ */ + EVT_SRC_CMP2 = 313U, /* CMP_2_IRQ */ + EVT_SRC_CMP3 = 314U, /* CMP_3_IRQ */ + EVT_SRC_CMP4 = 315U, /* CMP_4_IRQ */ + /* USART1 */ + EVT_SRC_USART1_EI = 321U, /* USART_1_EI */ + EVT_SRC_USART1_RI = 322U, /* USART_1_RI */ + EVT_SRC_USART1_TI = 323U, /* USART_1_TI */ + EVT_SRC_USART1_RTO = 324U, /* USART_1_RTO */ + EVT_SRC_USART1_TCI = 326U, /* USART_1_TCI */ + /* USART2 */ + EVT_SRC_USART2_EI = 328U, /* USART_2_EI */ + EVT_SRC_USART2_RI = 329U, /* USART_2_RI */ + EVT_SRC_USART2_TI = 330U, /* USART_2_TI */ + EVT_SRC_USART2_RTO = 331U, /* USART_2_RTO */ + EVT_SRC_USART2_TCI = 333U, /* USART_2_TCI */ + /* SPI1 */ + EVT_SRC_SPI1_SPRI = 334U, /* SPI_1_SPRI */ + EVT_SRC_SPI1_SPTI = 335U, /* SPI_1_SPTI */ + EVT_SRC_SPI1_SPII = 336U, /* SPI_1_SPII */ + EVT_SRC_SPI1_SPEI = 337U, /* SPI_1_SPEI */ + EVT_SRC_SPI1_SPEND = 338U, /* SPI_1_SPEND */ + /* TIMERA_5 */ + EVT_SRC_TMRA_5_OVF = 340U, /* TMRA_5_OVF */ + EVT_SRC_TMRA_5_UDF = 341U, /* TMRA_5_UDF */ + EVT_SRC_TMRA_5_CMP = 342U, /* TMRA_5_CMP */ + /* EVENT PORT */ + EVT_SRC_EVENT_PORT1 = 348U, /* EVENT_PORT1 */ + EVT_SRC_EVENT_PORT2 = 349U, /* EVENT_PORT2 */ + EVT_SRC_EVENT_PORT3 = 350U, /* EVENT_PORT3 */ + EVT_SRC_EVENT_PORT4 = 351U, /* EVENT_PORT4 */ + /* USART3 */ + EVT_SRC_USART3_BRKWKPI = 352U, /* USART_3_BRKWKPI */ + EVT_SRC_USART3_EI = 353U, /* USART_3_EI */ + EVT_SRC_USART3_RI = 354U, /* USART_3_RI */ + EVT_SRC_USART3_TI = 355U, /* USART_3_TI */ + EVT_SRC_USART3_TCI = 358U, /* USART_3_TCI */ + /* USART4 */ + EVT_SRC_USART4_EI = 360U, /* USART_4_EI */ + EVT_SRC_USART4_RI = 361U, /* USART_4_RI */ + EVT_SRC_USART4_TI = 362U, /* USART_4_TI */ + EVT_SRC_USART4_RTO = 363U, /* USART_4_RTO */ + EVT_SRC_USART4_TCI = 365U, /* USART_4_TCI */ + /* SPI2 */ + EVT_SRC_SPI2_SPRI = 366U, /* SPI_2_SPRI */ + EVT_SRC_SPI2_SPTI = 367U, /* SPI_2_SPTI */ + EVT_SRC_SPI2_SPII = 368U, /* SPI_2_SPII */ + EVT_SRC_SPI2_SPEI = 369U, /* SPI_2_SPEI */ + EVT_SRC_SPI2_SPEND = 370U, /* SPI_2_SPEND */ + /* SPI3 */ + EVT_SRC_SPI3_SPRI = 371U, /* SPI_3_SPRI */ + EVT_SRC_SPI3_SPTI = 372U, /* SPI_3_SPTI */ + EVT_SRC_SPI3_SPII = 373U, /* SPI_3_SPII */ + EVT_SRC_SPI3_SPEI = 374U, /* SPI_3_SPEI */ + EVT_SRC_SPI3_SPEND = 375U, /* SPI_3_SPEND */ + /* USART5 */ + EVT_SRC_USART5_EI = 385U, /* USART_5_EI */ + EVT_SRC_USART5_RI = 386U, /* USART_5_RI */ + EVT_SRC_USART5_TI = 387U, /* USART_5_TI */ + EVT_SRC_USART5_RTO = 388U, /* USART_5_RTO */ + EVT_SRC_USART5_TCI = 390U, /* USART_5_TCI */ + /* USART6 */ + EVT_SRC_USART6_BRKWKPI = 391U, /* USART_6_BRKWKPI */ + EVT_SRC_USART6_EI = 392U, /* USART_6_EI */ + EVT_SRC_USART6_RI = 393U, /* USART_6_RI */ + EVT_SRC_USART6_TI = 394U, /* USART_6_TI */ + EVT_SRC_USART6_TCI = 396U, /* USART_6_TCI */ + /* AOS */ + EVT_SRC_AOS_STRG = 415U, /* AOS_STRG */ + /* LVD */ + EVT_SRC_LVD1 = 465U, /* LVD1 */ + EVT_SRC_LVD2 = 466U, /* LVD2 */ + /* WDT */ + EVT_SRC_WDT_REFUDF = 471U, /* WDT_REFUDF */ + /* ADC1 */ + EVT_SRC_ADC1_EOCA = 480U, /* ADC_1_EOCA */ + EVT_SRC_ADC1_EOCB = 481U, /* ADC_1_EOCB */ + EVT_SRC_ADC1_CMP0 = 482U, /* ADC_1_CMP0 */ + EVT_SRC_ADC1_CMP1 = 483U, /* ADC_1_CMP1 */ + /* ADC2 */ + EVT_SRC_ADC2_EOCA = 484U, /* ADC_2_EOCA */ + EVT_SRC_ADC2_EOCB = 485U, /* ADC_2_EOCB */ + EVT_SRC_ADC2_CMP0 = 486U, /* ADC_2_CMP0 */ + EVT_SRC_ADC2_CMP1 = 487U, /* ADC_2_CMP1 */ + /* ADC3 */ + EVT_SRC_ADC3_EOCA = 488U, /* ADC_3_EOCA */ + EVT_SRC_ADC3_EOCB = 489U, /* ADC_3_EOCB */ + EVT_SRC_ADC3_CMP0 = 490U, /* ADC_3_CMP0 */ + EVT_SRC_ADC3_CMP1 = 491U, /* ADC_3_CMP1 */ + /* TRNG */ + EVT_SRC_TRNG_END = 492U, /* TRNG_END */ + EVT_SRC_MAX = 511U, +} en_event_src_t; + +/** + ******************************************************************************* + ** \brief Interrupt number enumeration + ******************************************************************************/ +typedef enum { + INT_SRC_SWI_IRQ0 = 0U, + INT_SRC_SWI_IRQ1 = 1U, + INT_SRC_SWI_IRQ2 = 2U, + INT_SRC_SWI_IRQ3 = 3U, + INT_SRC_SWI_IRQ4 = 4U, + INT_SRC_SWI_IRQ5 = 5U, + INT_SRC_SWI_IRQ6 = 6U, + INT_SRC_SWI_IRQ7 = 7U, + INT_SRC_SWI_IRQ8 = 8U, + INT_SRC_SWI_IRQ9 = 9U, + INT_SRC_SWI_IRQ10 = 10U, + INT_SRC_SWI_IRQ11 = 11U, + INT_SRC_SWI_IRQ12 = 12U, + INT_SRC_SWI_IRQ13 = 13U, + INT_SRC_SWI_IRQ14 = 14U, + INT_SRC_SWI_IRQ15 = 15U, + INT_SRC_SWI_IRQ16 = 16U, + INT_SRC_SWI_IRQ17 = 17U, + INT_SRC_SWI_IRQ18 = 18U, + INT_SRC_SWI_IRQ19 = 19U, + INT_SRC_SWI_IRQ20 = 20U, + INT_SRC_SWI_IRQ21 = 21U, + INT_SRC_SWI_IRQ22 = 22U, + INT_SRC_SWI_IRQ23 = 23U, + INT_SRC_SWI_IRQ24 = 24U, + INT_SRC_SWI_IRQ25 = 25U, + INT_SRC_SWI_IRQ26 = 26U, + INT_SRC_SWI_IRQ27 = 27U, + INT_SRC_SWI_IRQ28 = 28U, + INT_SRC_SWI_IRQ29 = 29U, + INT_SRC_SWI_IRQ30 = 30U, + INT_SRC_SWI_IRQ31 = 31U, + /* External Interrupt */ + INT_SRC_PORT_EIRQ0 = 0U, /* EIRQ0 */ + INT_SRC_PORT_EIRQ1 = 1U, /* EIRQ1 */ + INT_SRC_PORT_EIRQ2 = 2U, /* EIRQ2 */ + INT_SRC_PORT_EIRQ3 = 3U, /* EIRQ3 */ + INT_SRC_PORT_EIRQ4 = 4U, /* EIRQ4 */ + INT_SRC_PORT_EIRQ5 = 5U, /* EIRQ5 */ + INT_SRC_PORT_EIRQ6 = 6U, /* EIRQ6 */ + INT_SRC_PORT_EIRQ7 = 7U, /* EIRQ7 */ + INT_SRC_PORT_EIRQ8 = 8U, /* EIRQ8 */ + INT_SRC_PORT_EIRQ9 = 9U, /* EIRQ9 */ + INT_SRC_PORT_EIRQ10 = 10U, /* EIRQ10 */ + INT_SRC_PORT_EIRQ11 = 11U, /* EIRQ11 */ + INT_SRC_PORT_EIRQ12 = 12U, /* EIRQ12 */ + INT_SRC_PORT_EIRQ13 = 13U, /* EIRQ13 */ + INT_SRC_PORT_EIRQ14 = 14U, /* EIRQ14 */ + INT_SRC_PORT_EIRQ15 = 15U, /* EIRQ15 */ + /* DMA_1 */ + INT_SRC_DMA1_ERR = 32U, /* DMA_1_ERR */ + INT_SRC_DMA1_TC0 = 33U, /* DMA_1_TC0 */ + INT_SRC_DMA1_BTC0 = 34U, /* DMA_1_BTC0 */ + INT_SRC_DMA1_TC1 = 35U, /* DMA_1_TC1 */ + INT_SRC_DMA1_BTC1 = 36U, /* DMA_1_BTC1 */ + INT_SRC_DMA1_TC2 = 37U, /* DMA_1_TC2 */ + INT_SRC_DMA1_BTC2 = 38U, /* DMA_1_BTC2 */ + INT_SRC_DMA1_TC3 = 39U, /* DMA_1_TC3 */ + INT_SRC_DMA1_BTC3 = 40U, /* DMA_1_BTC3 */ + INT_SRC_DMA1_TC4 = 41U, /* DMA_1_TC4 */ + INT_SRC_DMA1_BTC4 = 42U, /* DMA_1_BTC4 */ + INT_SRC_DMA1_TC5 = 43U, /* DMA_1_TC5 */ + INT_SRC_DMA1_BTC5 = 44U, /* DMA_1_BTC5 */ + /* EFM */ + INT_SRC_EFM_PEERR = 49U, /* EFM_PEERR */ + INT_SRC_EFM_RDCOL = 50U, /* EFM_RDCOL */ + INT_SRC_EFM_OPTEND = 51U, /* EFM_OPTEND */ + /* QSPI */ + INT_SRC_QSPI_INTR = 54U, /* QSPI_INTR */ + /* DCU */ + INT_SRC_DCU1 = 55U, /* DCU1 */ + INT_SRC_DCU2 = 56U, /* DCU2 */ + INT_SRC_DCU3 = 57U, /* DCU3 */ + INT_SRC_DCU4 = 58U, /* DCU4 */ + /* DMA2 */ + INT_SRC_DMA2_ERR = 64U, /* DMA_2_ERR */ + INT_SRC_DMA2_TC0 = 65U, /* DMA_2_TC0 */ + INT_SRC_DMA2_BTC0 = 66U, /* DMA_2_BTC0 */ + INT_SRC_DMA2_TC1 = 67U, /* DMA_2_TC1 */ + INT_SRC_DMA2_BTC1 = 68U, /* DMA_2_BTC1 */ + INT_SRC_DMA2_TC2 = 69U, /* DMA_2_TC2 */ + INT_SRC_DMA2_BTC2 = 70U, /* DMA_2_BTC2 */ + INT_SRC_DMA2_TC3 = 71U, /* DMA_2_TC3 */ + INT_SRC_DMA2_BTC3 = 72U, /* DMA_2_BTC3 */ + INT_SRC_DMA2_TC4 = 73U, /* DMA_2_TC4 */ + INT_SRC_DMA2_BTC4 = 74U, /* DMA_2_BTC4 */ + INT_SRC_DMA2_TC5 = 75U, /* DMA_2_TC5 */ + INT_SRC_DMA2_BTC5 = 76U, /* DMA_2_BTC5 */ + /* TIMER0 */ + INT_SRC_TMR0_1_CMP_A = 96U, /* TMR0_1_CMPA */ + INT_SRC_TMR0_1_CMP_B = 97U, /* TMR0_1_CMPB */ + INT_SRC_TMR0_1_OVF_A = 98U, /* TMR0_1_OVFA */ + INT_SRC_TMR0_1_OVF_B = 99U, /* TMR0_1_OVFB */ + INT_SRC_TMR0_2_CMP_A = 100U, /* TMR0_2_CMPA */ + INT_SRC_TMR0_2_CMP_B = 101U, /* TMR0_2_CMPB */ + INT_SRC_TMR0_2_OVF_A = 102U, /* TMR0_2_OVFA */ + INT_SRC_TMR0_2_OVF_B = 103U, /* TMR0_2_OVFB */ + /* RTC */ + INT_SRC_RTC_ALM = 121U, /* RTC_ALM */ + INT_SRC_RTC_PRD = 122U, /* RTC_PRD */ + /* XTAL */ + INT_SRC_XTAL_STOP = 125U, /* XTAL_STOP */ + /* WKTM */ + INT_SRC_WKTM_PRD = 126U, /* WKTM_PRD */ + /* SWDT */ + INT_SRC_SWDT_REFUDF = 127U, /* SWDT_REFUDF */ + /* TIMER6_1 */ + INT_SRC_TMR6_1_GCMP_A = 128U, /* TMR6_1_GCMA */ + INT_SRC_TMR6_1_GCMP_B = 129U, /* TMR6_1_GCMB */ + INT_SRC_TMR6_1_GCMP_C = 130U, /* TMR6_1_GCMC */ + INT_SRC_TMR6_1_GCMP_D = 131U, /* TMR6_1_GCMD */ + INT_SRC_TMR6_1_GCMP_E = 132U, /* TMR6_1_GCME */ + INT_SRC_TMR6_1_GCMP_F = 133U, /* TMR6_1_GCMF */ + INT_SRC_TMR6_1_OVF = 134U, /* TMR6_1_GOVF */ + INT_SRC_TMR6_1_UDF = 135U, /* TMR6_1_GUDF */ + INT_SRC_TMR6_1_DTE = 136U, /* TMR6_1_GDTE */ + INT_SRC_TMR6_1_SCMP_A = 137U, /* TMR6_1_SCMA */ + INT_SRC_TMR6_1_SCMP_B = 138U, /* TMR6_1_SCMB */ + /* TIMERA_1 */ + INT_SRC_TMRA_1_OVF = 139U, /* TMRA_1_OVF */ + INT_SRC_TMRA_1_UDF = 140U, /* TMRA_1_UDF */ + INT_SRC_TMRA_1_CMP = 141U, /* TMRA_1_CMP */ + /* TIMER6_2 */ + INT_SRC_TMR6_2_GCMP_A = 144U, /* TMR6_2_GCMA */ + INT_SRC_TMR6_2_GCMP_B = 145U, /* TMR6_2_GCMB */ + INT_SRC_TMR6_2_GCMP_C = 146U, /* TMR6_2_GCMC */ + INT_SRC_TMR6_2_GCMP_D = 147U, /* TMR6_2_GCMD */ + INT_SRC_TMR6_2_GCMP_E = 148U, /* TMR6_2_GCME */ + INT_SRC_TMR6_2_GCMP_F = 149U, /* TMR6_2_GCMF */ + INT_SRC_TMR6_2_OVF = 150U, /* TMR6_2_GOVF */ + INT_SRC_TMR6_2_UDF = 151U, /* TMR6_2_GUDF */ + INT_SRC_TMR6_2_DTE = 152U, /* TMR6_2_GDTE */ + INT_SRC_TMR6_2_SCMP_A = 153U, /* TMR6_2_SCMA */ + INT_SRC_TMR6_2_SCMP_B = 154U, /* TMR6_2_SCMB */ + /* TIMERA_2 */ + INT_SRC_TMRA_2_OVF = 155U, /* TMRA_2_OVF */ + INT_SRC_TMRA_2_UDF = 156U, /* TMRA_2_UDF */ + INT_SRC_TMRA_2_CMP = 157U, /* TMRA_2_CMP */ + /* TIMERA_3 */ + INT_SRC_TMRA_3_OVF = 171U, /* TMRA_3_OVF */ + INT_SRC_TMRA_3_UDF = 172U, /* TMRA_3_UDF */ + INT_SRC_TMRA_3_CMP = 173U, /* TMRA_3_CMP */ + /* TIMERA_4 */ + INT_SRC_TMRA_4_OVF = 187U, /* TMRA_4_OVF */ + INT_SRC_TMRA_4_UDF = 188U, /* TMRA_4_UDF */ + INT_SRC_TMRA_4_CMP = 189U, /* TMRA_4_CMP */ + + /* TIMER4_1 */ + INT_SRC_TMR4_1_GCMP_UH = 192U, /* TMR4_1_GCMUH */ + INT_SRC_TMR4_1_GCMP_UL = 193U, /* TMR4_1_GCMUL */ + INT_SRC_TMR4_1_GCMP_VH = 194U, /* TMR4_1_GCMVH */ + INT_SRC_TMR4_1_GCMP_VL = 195U, /* TMR4_1_GCMVL */ + INT_SRC_TMR4_1_GCMP_WH = 196U, /* TMR4_1_GCMWH */ + INT_SRC_TMR4_1_GCMP_WL = 197U, /* TMR4_1_GCMWL */ + INT_SRC_TMR4_1_GCMP_XH = 198U, /* TMR4_1_GCMXH */ + INT_SRC_TMR4_1_GCMP_XL = 199U, /* TMR4_1_GCMXL */ + INT_SRC_TMR4_1_OVF = 200U, /* TMR4_1_GOVF */ + INT_SRC_TMR4_1_UDF = 201U, /* TMR4_1_GUDF */ + INT_SRC_TMR4_1_RELOAD_U = 202U, /* TMR4_1_GRLU */ + INT_SRC_TMR4_1_RELOAD_V = 203U, /* TMR4_1_GRLV */ + INT_SRC_TMR4_1_RELOAD_W = 204U, /* TMR4_1_GRLW */ + INT_SRC_TMR4_1_RELOAD_X = 205U, /* TMR4_1_GRLX */ + INT_SRC_TMR4_1_SCMP0 = 206U, /* TMR4_1_SCM0 */ + INT_SRC_TMR4_1_SCMP1 = 207U, /* TMR4_1_SCM1 */ + INT_SRC_TMR4_1_SCMP2 = 208U, /* TMR4_1_SCM2 */ + INT_SRC_TMR4_1_SCMP3 = 209U, /* TMR4_1_SCM3 */ + INT_SRC_TMR4_1_SCMP4 = 210U, /* TMR4_1_SCM4 */ + INT_SRC_TMR4_1_SCMP5 = 211U, /* TMR4_1_SCM5 */ + INT_SRC_TMR4_1_SCMP6 = 212U, /* TMR4_1_SCM6 */ + INT_SRC_TMR4_1_SCMP7 = 213U, /* TMR4_1_SCM7 */ + /* TIMER4_2 */ + INT_SRC_TMR4_2_GCMP_UH = 224U, /* TMR4_2_GCMUH */ + INT_SRC_TMR4_2_GCMP_UL = 225U, /* TMR4_2_GCMUL */ + INT_SRC_TMR4_2_GCMP_VH = 226U, /* TMR4_2_GCMVH */ + INT_SRC_TMR4_2_GCMP_VL = 227U, /* TMR4_2_GCMVL */ + INT_SRC_TMR4_2_GCMP_WH = 228U, /* TMR4_2_GCMWH */ + INT_SRC_TMR4_2_GCMP_WL = 229U, /* TMR4_2_GCMWL */ + INT_SRC_TMR4_2_GCMP_XH = 230U, /* TMR4_2_GCMXH */ + INT_SRC_TMR4_2_GCMP_XL = 231U, /* TMR4_2_GCMXL */ + INT_SRC_TMR4_2_OVF = 232U, /* TMR4_2_GOVF */ + INT_SRC_TMR4_2_UDF = 233U, /* TMR4_2_GUDF */ + INT_SRC_TMR4_2_RELOAD_U = 234U, /* TMR4_2_GRLU */ + INT_SRC_TMR4_2_RELOAD_V = 235U, /* TMR4_2_GRLV */ + INT_SRC_TMR4_2_RELOAD_W = 236U, /* TMR4_2_GRLW */ + INT_SRC_TMR4_2_RELOAD_X = 237U, /* TMR4_2_GRLX */ + INT_SRC_TMR4_2_SCMP0 = 238U, /* TMR4_2_SCM0 */ + INT_SRC_TMR4_2_SCMP1 = 239U, /* TMR4_2_SCM1 */ + INT_SRC_TMR4_2_SCMP2 = 240U, /* TMR4_2_SCM2 */ + INT_SRC_TMR4_2_SCMP3 = 241U, /* TMR4_2_SCM3 */ + INT_SRC_TMR4_2_SCMP4 = 242U, /* TMR4_2_SCM4 */ + INT_SRC_TMR4_2_SCMP5 = 243U, /* TMR4_2_SCM5 */ + INT_SRC_TMR4_2_SCMP6 = 244U, /* TMR4_2_SCM6 */ + INT_SRC_TMR4_2_SCMP7 = 245U, /* TMR4_2_SCM7 */ + /* TIMER4_3 */ + INT_SRC_TMR4_3_GCMP_UH = 256U, /* TMR4_3_GCMUH */ + INT_SRC_TMR4_3_GCMP_UL = 257U, /* TMR4_3_GCMUL */ + INT_SRC_TMR4_3_GCMP_VH = 258U, /* TMR4_3_GCMVH */ + INT_SRC_TMR4_3_GCMP_VL = 259U, /* TMR4_3_GCMVL */ + INT_SRC_TMR4_3_GCMP_WH = 260U, /* TMR4_3_GCMWH */ + INT_SRC_TMR4_3_GCMP_WL = 261U, /* TMR4_3_GCMWL */ + INT_SRC_TMR4_3_GCMP_XH = 262U, /* TMR4_3_GCMXH */ + INT_SRC_TMR4_3_GCMP_XL = 263U, /* TMR4_3_GCMXL */ + INT_SRC_TMR4_3_OVF = 264U, /* TMR4_3_GOVF */ + INT_SRC_TMR4_3_UDF = 265U, /* TMR4_3_GUDF */ + INT_SRC_TMR4_3_RELOAD_U = 266U, /* TMR4_3_GRLU */ + INT_SRC_TMR4_3_RELOAD_V = 267U, /* TMR4_3_GRLV */ + INT_SRC_TMR4_3_RELOAD_W = 268U, /* TMR4_3_GRLW */ + INT_SRC_TMR4_3_RELOAD_X = 269U, /* TMR4_3_GRLX */ + INT_SRC_TMR4_3_SCMP0 = 270U, /* TMR4_3_SCM0 */ + INT_SRC_TMR4_3_SCMP1 = 271U, /* TMR4_3_SCM1 */ + INT_SRC_TMR4_3_SCMP2 = 272U, /* TMR4_3_SCM2 */ + INT_SRC_TMR4_3_SCMP3 = 273U, /* TMR4_3_SCM3 */ + INT_SRC_TMR4_3_SCMP4 = 274U, /* TMR4_3_SCM4 */ + INT_SRC_TMR4_3_SCMP5 = 275U, /* TMR4_3_SCM5 */ + INT_SRC_TMR4_3_SCMP6 = 276U, /* TMR4_3_SCM6 */ + INT_SRC_TMR4_3_SCMP7 = 277U, /* TMR4_3_SCM7 */ + /* I2C1 */ + INT_SRC_I2C1_RXI = 288U, /* I2C_1_RXI */ + INT_SRC_I2C1_TXI = 289U, /* I2C_1_TXI */ + INT_SRC_I2C1_TEI = 290U, /* I2C_1_TEI */ + INT_SRC_I2C1_EEI = 291U, /* I2C_1_EEI */ + /* I2C2 */ + INT_SRC_I2C2_RXI = 292U, /* I2C_2_RXI */ + INT_SRC_I2C2_TXI = 293U, /* I2C_2_TXI */ + INT_SRC_I2C2_TEI = 294U, /* I2C_2_TEI */ + INT_SRC_I2C2_EEI = 295U, /* I2C_2_EEI */ + /* CMP */ + INT_SRC_CMP1 = 312U, /* CMP_1_IRQ */ + INT_SRC_CMP2 = 313U, /* CMP_2_IRQ */ + INT_SRC_CMP3 = 314U, /* CMP_3_IRQ */ + INT_SRC_CMP4 = 315U, /* CMP_4_IRQ */ + /* USART1 */ + INT_SRC_USART1_EI = 321U, /* USART_1_EI */ + INT_SRC_USART1_RI = 322U, /* USART_1_RI */ + INT_SRC_USART1_TI = 323U, /* USART_1_TI */ + INT_SRC_USART1_RTO = 324U, /* USART_1_RTO */ + INT_SRC_USART1_TENDI = 325U, /* USART_1_TENDI */ + INT_SRC_USART1_TCI = 326U, /* USART_1_TCI */ + /* USART2 */ + INT_SRC_USART2_EI = 328U, /* USART_2_EI */ + INT_SRC_USART2_RI = 329U, /* USART_2_RI */ + INT_SRC_USART2_TI = 330U, /* USART_2_TI */ + INT_SRC_USART2_RTO = 331U, /* USART_2_RTO */ + INT_SRC_USART2_TENDI = 332U, /* USART_2_TENDI */ + INT_SRC_USART2_TCI = 333U, /* USART_2_TCI */ + /* SPI1 */ + INT_SRC_SPI1_SPRI = 334U, /* SPI_1_SPRI */ + INT_SRC_SPI1_SPTI = 335U, /* SPI_1_SPTI */ + INT_SRC_SPI1_SPII = 336U, /* SPI_1_SPII */ + INT_SRC_SPI1_SPEI = 337U, /* SPI_1_SPEI */ + /* TIMERA_5 */ + INT_SRC_TMRA_5_OVF = 340U, /* TMRA_5_OVF */ + INT_SRC_TMRA_5_UDF = 341U, /* TMRA_5_UDF */ + INT_SRC_TMRA_5_CMP = 342U, /* TMRA_5_CMP */ + /* EVENT PORT */ + INT_SRC_EVENT_PORT1 = 348U, /* EVENT_PORT1 */ + INT_SRC_EVENT_PORT2 = 349U, /* EVENT_PORT2 */ + INT_SRC_EVENT_PORT3 = 350U, /* EVENT_PORT3 */ + INT_SRC_EVENT_PORT4 = 351U, /* EVENT_PORT4 */ + /* USART3 */ + INT_SRC_USART3_BRKWKPI = 352U, /* USART_3_BRKWKPI */ + INT_SRC_USART3_EI = 353U, /* USART_3_EI */ + INT_SRC_USART3_RI = 354U, /* USART_3_RI */ + INT_SRC_USART3_TI = 355U, /* USART_3_TI */ + INT_SRC_USART3_TENDI = 357U, /* USART_3_TENDI */ + INT_SRC_USART3_TCI = 358U, /* USART_3_TCI */ + /* USART4 */ + INT_SRC_USART4_EI = 360U, /* USART_4_EI */ + INT_SRC_USART4_RI = 361U, /* USART_4_RI */ + INT_SRC_USART4_TI = 362U, /* USART_4_TI */ + INT_SRC_USART4_RTO = 363U, /* USART_4_RTO */ + INT_SRC_USART4_TENDI = 364U, /* USART_4_TENDI */ + INT_SRC_USART4_TCI = 365U, /* USART_4_TCI */ + /* SPI2 */ + INT_SRC_SPI2_SPRI = 366U, /* SPI_2_SPRI */ + INT_SRC_SPI2_SPTI = 367U, /* SPI_2_SPTI */ + INT_SRC_SPI2_SPII = 368U, /* SPI_2_SPII */ + INT_SRC_SPI2_SPEI = 369U, /* SPI_2_SPEI */ + /* SPI3 */ + INT_SRC_SPI3_SPRI = 371U, /* SPI_3_SPRI */ + INT_SRC_SPI3_SPTI = 372U, /* SPI_3_SPTI */ + INT_SRC_SPI3_SPII = 373U, /* SPI_3_SPII */ + INT_SRC_SPI3_SPEI = 374U, /* SPI_3_SPEI */ + /* EMB */ + INT_SRC_EMB_GR0 = 376U, /* EMB_GR0 */ + INT_SRC_EMB_GR1 = 377U, /* EMB_GR1 */ + INT_SRC_EMB_GR2 = 378U, /* EMB_GR2 */ + INT_SRC_EMB_GR3 = 379U, /* EMB_GR3 */ + /* USART5 */ + INT_SRC_USART5_EI = 385U, /* USART_5_EI */ + INT_SRC_USART5_RI = 386U, /* USART_5_RI */ + INT_SRC_USART5_TI = 387U, /* USART_5_TI */ + INT_SRC_USART5_RTO = 388U, /* USART_5_RTO */ + INT_SRC_USART5_TENDI = 389U, /* USART_5_TENDI */ + INT_SRC_USART5_TCI = 390U, /* USART_5_TCI */ + /* USART6 */ + INT_SRC_USART6_BRKWKPI = 391U, /* USART_6_BRKWKPI */ + INT_SRC_USART6_EI = 392U, /* USART_6_EI */ + INT_SRC_USART6_RI = 393U, /* USART_6_RI */ + INT_SRC_USART6_TI = 394U, /* USART_6_TI */ + INT_SRC_USART6_TENDI = 395U, /* USART_6_TENDI */ + INT_SRC_USART6_TCI = 396U, /* USART_6_TCI */ + /* MCAN */ + INT_SRC_MCAN1_INT0 = 408U, /* MCAN1_INT_LINE0 */ + INT_SRC_MCAN1_INT1 = 409U, /* MCAN1_INT_LINE1 */ + INT_SRC_MCAN2_INT0 = 410U, /* MCAN2_INT_LINE0 */ + INT_SRC_MCAN2_INT1 = 411U, /* MCAN2_INT_LINE1 */ + /* USART1 */ + INT_SRC_USART1_WUPI = 464U, /* USART_1_WUPI */ + /* FCM */ + INT_SRC_FCMFERRI = 468U, /* FCMFERRI */ + INT_SRC_FCMMENDI = 469U, /* FCMMENDI */ + INT_SRC_FCMCOVFI = 470U, /* FCMCOVFI */ + /* WDT */ + INT_SRC_WDT_REFUDF = 471U, /* WDT_REFUDF */ + /* CTC */ + INT_SRC_CTC_ERR = 472U, /* CTC_ERR */ + /* ADC1 */ + INT_SRC_ADC1_EOCA = 480U, /* ADC_1_EOCA */ + INT_SRC_ADC1_EOCB = 481U, /* ADC_1_EOCB */ + INT_SRC_ADC1_CMP0 = 482U, /* ADC_1_CMP0 */ + INT_SRC_ADC1_CMP1 = 483U, /* ADC_1_CMP1 */ + /* ADC2 */ + INT_SRC_ADC2_EOCA = 484U, /* ADC_2_EOCA */ + INT_SRC_ADC2_EOCB = 485U, /* ADC_2_EOCB */ + INT_SRC_ADC2_CMP0 = 486U, /* ADC_2_CMP0 */ + INT_SRC_ADC2_CMP1 = 487U, /* ADC_2_CMP1 */ + /* ADC3 */ + INT_SRC_ADC3_EOCA = 488U, /* ADC_3_EOCA */ + INT_SRC_ADC3_EOCB = 489U, /* ADC_3_EOCB */ + INT_SRC_ADC3_CMP0 = 490U, /* ADC_3_CMP0 */ + INT_SRC_ADC3_CMP1 = 491U, /* ADC_3_CMP1 */ + /* TRNG */ + INT_SRC_TRNG_END = 492U, /* TRNG_END */ + INT_SRC_MAX = 511U, +} en_int_src_t; + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +/** + * @brief ADC + */ +typedef struct { + __IO uint8_t STR; + uint8_t RESERVED0[1]; + __IO uint16_t CR0; + __IO uint16_t CR1; + __IO uint16_t CR2; + uint8_t RESERVED1[2]; + __IO uint16_t TRGSR; + __IO uint32_t CHSELRA; + __IO uint32_t CHSELRB; + __IO uint32_t AVCHSELR; + __IO uint8_t EXCHSELR; + uint8_t RESERVED2[7]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + uint8_t RESERVED3[8]; + __IO uint16_t CHMUXR0; + __IO uint16_t CHMUXR1; + __IO uint16_t CHMUXR2; + __IO uint16_t CHMUXR3; + uint8_t RESERVED4[4]; + __I uint8_t ISR; + __IO uint8_t ICR; + __O uint8_t ISCLRR; + uint8_t RESERVED5[5]; + __IO uint16_t SYNCCR; + uint8_t RESERVED6[2]; + __I uint16_t DR0; + __I uint16_t DR1; + __I uint16_t DR2; + __I uint16_t DR3; + __I uint16_t DR4; + __I uint16_t DR5; + __I uint16_t DR6; + __I uint16_t DR7; + __I uint16_t DR8; + __I uint16_t DR9; + __I uint16_t DR10; + __I uint16_t DR11; + __I uint16_t DR12; + __I uint16_t DR13; + __I uint16_t DR14; + __I uint16_t DR15; + uint8_t RESERVED7[48]; + __IO uint16_t AWDCR; + __I uint8_t AWDSR; + __O uint8_t AWDSCLRR; + __IO uint16_t AWD0DR0; + __IO uint16_t AWD0DR1; + __IO uint8_t AWD0CHSR; + uint8_t RESERVED8[3]; + __IO uint16_t AWD1DR0; + __IO uint16_t AWD1DR1; + __IO uint8_t AWD1CHSR; +} CM_ADC_TypeDef; + +/** + * @brief AES + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; + __IO uint32_t KR4; + __IO uint32_t KR5; + __IO uint32_t KR6; + __IO uint32_t KR7; +} CM_AES_TypeDef; + +/** + * @brief AOS + */ +typedef struct { + __O uint32_t INTSFTTRG; + __IO uint32_t DCU_TRGSEL1; + __IO uint32_t DCU_TRGSEL2; + __IO uint32_t DCU_TRGSEL3; + __IO uint32_t DCU_TRGSEL4; + __IO uint32_t DMA1_TRGSEL0; + __IO uint32_t DMA1_TRGSEL1; + __IO uint32_t DMA1_TRGSEL2; + __IO uint32_t DMA1_TRGSEL3; + __IO uint32_t DMA1_TRGSEL4; + __IO uint32_t DMA1_TRGSEL5; + __IO uint32_t DMA2_TRGSEL0; + __IO uint32_t DMA2_TRGSEL1; + __IO uint32_t DMA2_TRGSEL2; + __IO uint32_t DMA2_TRGSEL3; + __IO uint32_t DMA2_TRGSEL4; + __IO uint32_t DMA2_TRGSEL5; + __IO uint32_t DMA_RC_TRGSEL; + __IO uint32_t TMR6_TRGSEL0; + __IO uint32_t TMR6_TRGSEL1; + __IO uint32_t TMR4_TRGSEL0; + __IO uint32_t TMR4_TRGSEL1; + __IO uint32_t TMR4_TRGSEL2; + __IO uint32_t PEVNT_TRGSEL12; + __IO uint32_t PEVNT_TRGSEL34; + __IO uint32_t TMR0_TRGSEL; + __IO uint32_t TMRA_TRGSEL0; + __IO uint32_t TMRA_TRGSEL1; + __IO uint32_t TMRA_TRGSEL2; + __IO uint32_t TMRA_TRGSEL3; + __IO uint32_t ADC1_TRGSEL0; + __IO uint32_t ADC1_TRGSEL1; + __IO uint32_t ADC2_TRGSEL0; + __IO uint32_t ADC2_TRGSEL1; + __IO uint32_t ADC3_TRGSEL0; + __IO uint32_t ADC3_TRGSEL1; + __IO uint32_t COMTRGSEL1; + __IO uint32_t COMTRGSEL2; + uint8_t RESERVED0[104]; + __IO uint32_t PEVNTDIRR1; + __I uint32_t PEVNTIDR1; + __IO uint32_t PEVNTODR1; + __IO uint32_t PEVNTORR1; + __IO uint32_t PEVNTOSR1; + __IO uint32_t PEVNTRISR1; + __IO uint32_t PEVNTFALR1; + __IO uint32_t PEVNTDIRR2; + __I uint32_t PEVNTIDR2; + __IO uint32_t PEVNTODR2; + __IO uint32_t PEVNTORR2; + __IO uint32_t PEVNTOSR2; + __IO uint32_t PEVNTRISR2; + __IO uint32_t PEVNTFALR2; + __IO uint32_t PEVNTDIRR3; + __I uint32_t PEVNTIDR3; + __IO uint32_t PEVNTODR3; + __IO uint32_t PEVNTORR3; + __IO uint32_t PEVNTOSR3; + __IO uint32_t PEVNTRISR3; + __IO uint32_t PEVNTFALR3; + __IO uint32_t PEVNTDIRR4; + __I uint32_t PEVNTIDR4; + __IO uint32_t PEVNTODR4; + __IO uint32_t PEVNTORR4; + __IO uint32_t PEVNTOSR4; + __IO uint32_t PEVNTRISR4; + __IO uint32_t PEVNTFALR4; + __IO uint32_t PEVNTNFCR; + uint8_t RESERVED1[140]; + __IO uint32_t PLU0_CR; + __IO uint32_t PLU1_CR; + __IO uint32_t PLU2_CR; + __IO uint32_t PLU3_CR; + __IO uint32_t PLU0_TRGSELA; + __IO uint32_t PLU0_TRGSELB; + __IO uint32_t PLU0_TRGSELC; + __IO uint32_t PLU0_TRGSELD; + __IO uint32_t PLU1_TRGSELA; + __IO uint32_t PLU1_TRGSELB; + __IO uint32_t PLU1_TRGSELC; + __IO uint32_t PLU1_TRGSELD; + __IO uint32_t PLU2_TRGSELA; + __IO uint32_t PLU2_TRGSELB; + __IO uint32_t PLU2_TRGSELC; + __IO uint32_t PLU2_TRGSELD; + __IO uint32_t PLU3_TRGSELA; + __IO uint32_t PLU3_TRGSELB; + __IO uint32_t PLU3_TRGSELC; + __IO uint32_t PLU3_TRGSELD; +} CM_AOS_TypeDef; + +/** + * @brief CMP + */ +typedef struct { + __IO uint8_t MDR; + __IO uint8_t FIR; + __IO uint8_t OCR; + uint8_t RESERVED0[1]; + __IO uint32_t PMSR; + uint8_t RESERVED1[8]; + __IO uint32_t BWSR1; + __IO uint16_t BWSR2; + uint8_t RESERVED2[2]; + __IO uint32_t SCCR; + __IO uint32_t SCMR; +} CM_CMP_TypeDef; + +/** + * @brief CMU + */ +typedef struct { + uint8_t RESERVED0[24]; + __IO uint32_t XTALDIVR; + __IO uint32_t XTALDIVCR; + uint8_t RESERVED1[19504]; + __IO uint8_t XTALCFGR; + uint8_t RESERVED2[3]; + __IO uint8_t XTAL32CR; + uint8_t RESERVED3[3]; + __IO uint8_t XTAL32CFGR; + uint8_t RESERVED4[15]; + __IO uint8_t XTAL32NFR; + uint8_t RESERVED5[3]; + __IO uint8_t LRCCR; + uint8_t RESERVED6[7]; + __IO uint8_t LRCTRM; + uint8_t RESERVED7[29595]; + __IO uint16_t PERICKSEL; + uint8_t RESERVED8[6]; + __IO uint16_t CANCKCFGR; + uint8_t RESERVED9[6]; + __IO uint32_t SCFGR; + uint8_t RESERVED10[2]; + __IO uint8_t CKSWR; + uint8_t RESERVED11[3]; + __IO uint8_t PLLHCR; + uint8_t RESERVED12[7]; + __IO uint8_t XTALCR; + uint8_t RESERVED13[3]; + __IO uint8_t HRCCR; + uint8_t RESERVED14[1]; + __IO uint8_t MRCCR; + uint8_t RESERVED15[3]; + __IO uint8_t OSCSTBSR; + __IO uint8_t MCO1CFGR; + __IO uint8_t MCO2CFGR; + __IO uint8_t TPIUCKCFGR; + __IO uint8_t XTALSTDCR; + __IO uint8_t XTALSTDSR; + uint8_t RESERVED16[31]; + __IO uint8_t MRCTRM; + __IO uint8_t HRCTRM; + uint8_t RESERVED17[63]; + __IO uint8_t XTALSTBCR; + uint8_t RESERVED18[93]; + __IO uint32_t PLLHCFGR; +} CM_CMU_TypeDef; + +/** + * @brief CRC + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t RESLT; + uint8_t RESERVED0[120]; + __O uint32_t DAT0; + __O uint32_t DAT1; + __O uint32_t DAT2; + __O uint32_t DAT3; + __O uint32_t DAT4; + __O uint32_t DAT5; + __O uint32_t DAT6; + __O uint32_t DAT7; + __O uint32_t DAT8; + __O uint32_t DAT9; + __O uint32_t DAT10; + __O uint32_t DAT11; + __O uint32_t DAT12; + __O uint32_t DAT13; + __O uint32_t DAT14; + __O uint32_t DAT15; + __O uint32_t DAT16; + __O uint32_t DAT17; + __O uint32_t DAT18; + __O uint32_t DAT19; + __O uint32_t DAT20; + __O uint32_t DAT21; + __O uint32_t DAT22; + __O uint32_t DAT23; + __O uint32_t DAT24; + __O uint32_t DAT25; + __O uint32_t DAT26; + __O uint32_t DAT27; + __O uint32_t DAT28; + __O uint32_t DAT29; + __O uint32_t DAT30; + __O uint32_t DAT31; +} CM_CRC_TypeDef; + +/** + * @brief CTC + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __I uint32_t STR; + __I uint16_t CNT; +} CM_CTC_TypeDef; + +/** + * @brief DAC + */ +typedef struct { + __IO uint16_t DADR1; + __IO uint16_t DADR2; + __IO uint16_t DACR; + __IO uint16_t DAADPCR; + uint8_t RESERVED0[20]; + __IO uint16_t DAOCR; +} CM_DAC_TypeDef; + +/** + * @brief DBGC + */ +typedef struct { + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + __I uint32_t CHIPID; + __IO uint32_t MCUSTAT; + uint8_t RESERVED0[4]; + __IO uint32_t FERSCTL; + __IO uint32_t MCUDBGCSTAT; + __IO uint32_t MCUSTPCTL; + __IO uint32_t MCUTRACECTL; + __IO uint32_t MCUSTPCTL2; +} CM_DBGC_TypeDef; + +/** + * @brief DCU + */ +typedef struct { + __IO uint32_t CTL; + __I uint32_t FLAG; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + __O uint32_t FLAGCLR; + __IO uint32_t INTEVTSEL; +} CM_DCU_TypeDef; + +/** + * @brief DMA + */ +typedef struct { + __IO uint32_t EN; + __I uint32_t INTSTAT0; + __I uint32_t INTSTAT1; + __IO uint32_t INTMASK0; + __IO uint32_t INTMASK1; + __O uint32_t INTCLR0; + __O uint32_t INTCLR1; + __IO uint32_t CHEN; + __I uint32_t REQSTAT; + __I uint32_t CHSTAT; + uint8_t RESERVED0[4]; + __IO uint32_t RCFGCTL; + uint8_t RESERVED1[4]; + __O uint32_t CHENCLR; + uint8_t RESERVED2[8]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t DTCTL0; + union { + __IO uint32_t RPT0; + __IO uint32_t RPTB0; + }; + union { + __IO uint32_t SNSEQCTL0; + __IO uint32_t SNSEQCTLB0; + }; + union { + __IO uint32_t DNSEQCTL0; + __IO uint32_t DNSEQCTLB0; + }; + __IO uint32_t LLP0; + __IO uint32_t CHCTL0; + __I uint32_t MONSAR0; + __I uint32_t MONDAR0; + __I uint32_t MONDTCTL0; + __I uint32_t MONRPT0; + __I uint32_t MONSNSEQCTL0; + __I uint32_t MONDNSEQCTL0; + uint8_t RESERVED3[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t DTCTL1; + union { + __IO uint32_t RPT1; + __IO uint32_t RPTB1; + }; + union { + __IO uint32_t SNSEQCTL1; + __IO uint32_t SNSEQCTLB1; + }; + union { + __IO uint32_t DNSEQCTL1; + __IO uint32_t DNSEQCTLB1; + }; + __IO uint32_t LLP1; + __IO uint32_t CHCTL1; + __I uint32_t MONSAR1; + __I uint32_t MONDAR1; + __I uint32_t MONDTCTL1; + __I uint32_t MONRPT1; + __I uint32_t MONSNSEQCTL1; + __I uint32_t MONDNSEQCTL1; + uint8_t RESERVED4[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t DTCTL2; + union { + __IO uint32_t RPT2; + __IO uint32_t RPTB2; + }; + union { + __IO uint32_t SNSEQCTL2; + __IO uint32_t SNSEQCTLB2; + }; + union { + __IO uint32_t DNSEQCTL2; + __IO uint32_t DNSEQCTLB2; + }; + __IO uint32_t LLP2; + __IO uint32_t CHCTL2; + __I uint32_t MONSAR2; + __I uint32_t MONDAR2; + __I uint32_t MONDTCTL2; + __I uint32_t MONRPT2; + __I uint32_t MONSNSEQCTL2; + __I uint32_t MONDNSEQCTL2; + uint8_t RESERVED5[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t DTCTL3; + union { + __IO uint32_t RPT3; + __IO uint32_t RPTB3; + }; + union { + __IO uint32_t SNSEQCTL3; + __IO uint32_t SNSEQCTLB3; + }; + union { + __IO uint32_t DNSEQCTL3; + __IO uint32_t DNSEQCTLB3; + }; + __IO uint32_t LLP3; + __IO uint32_t CHCTL3; + __I uint32_t MONSAR3; + __I uint32_t MONDAR3; + __I uint32_t MONDTCTL3; + __I uint32_t MONRPT3; + __I uint32_t MONSNSEQCTL3; + __I uint32_t MONDNSEQCTL3; + uint8_t RESERVED6[8]; + __IO uint32_t SAR4; + __IO uint32_t DAR4; + __IO uint32_t DTCTL4; + union { + __IO uint32_t RPT4; + __IO uint32_t RPTB4; + }; + union { + __IO uint32_t SNSEQCTL4; + __IO uint32_t SNSEQCTLB4; + }; + union { + __IO uint32_t DNSEQCTL4; + __IO uint32_t DNSEQCTLB4; + }; + __IO uint32_t LLP4; + __IO uint32_t CHCTL4; + __I uint32_t MONSAR4; + __I uint32_t MONDAR4; + __I uint32_t MONDTCTL4; + __I uint32_t MONRPT4; + __I uint32_t MONSNSEQCTL4; + __I uint32_t MONDNSEQCTL4; + uint8_t RESERVED7[8]; + __IO uint32_t SAR5; + __IO uint32_t DAR5; + __IO uint32_t DTCTL5; + union { + __IO uint32_t RPT5; + __IO uint32_t RPTB5; + }; + union { + __IO uint32_t SNSEQCTL5; + __IO uint32_t SNSEQCTLB5; + }; + union { + __IO uint32_t DNSEQCTL5; + __IO uint32_t DNSEQCTLB5; + }; + __IO uint32_t LLP5; + __IO uint32_t CHCTL5; + __I uint32_t MONSAR5; + __I uint32_t MONDAR5; + __I uint32_t MONDTCTL5; + __I uint32_t MONRPT5; + __I uint32_t MONSNSEQCTL5; + __I uint32_t MONDNSEQCTL5; +} CM_DMA_TypeDef; + +/** + * @brief EFM + */ +typedef struct { + __IO uint32_t FAPRT; + __IO uint32_t KEY1; + __IO uint32_t KEY2; + uint8_t RESERVED0[8]; + __IO uint32_t FSTP; + __IO uint32_t FRMC; + __IO uint32_t FWMC; + __I uint32_t FSR; + __IO uint32_t FSCLR; + __IO uint32_t FITE; + __I uint32_t FSWP; + uint8_t RESERVED1[16]; + __I uint32_t CHIPID; + uint8_t RESERVED2[12]; + __I uint32_t UQID0; + __I uint32_t UQID1; + __I uint32_t UQID2; + uint8_t RESERVED3[164]; + __IO uint32_t MMF_REMPRT; + __IO uint32_t MMF_REMCR0; + __IO uint32_t MMF_REMCR1; + uint8_t RESERVED4[116]; + __IO uint32_t WLOCK; + uint8_t RESERVED5[12]; + __IO uint32_t F0NWPRT; +} CM_EFM_TypeDef; + +/** + * @brief EMB + */ +typedef struct { + __IO uint32_t CTL1; + __IO uint32_t CTL2; + __IO uint32_t SOE; + __I uint32_t STAT; + __O uint32_t STATCLR; + __IO uint32_t INTEN; + __IO uint32_t RLSSEL; +} CM_EMB_TypeDef; + +/** + * @brief FCM + */ +typedef struct { + __IO uint32_t LVR; + __IO uint32_t UVR; + __I uint32_t CNTR; + __IO uint32_t STR; + __IO uint32_t MCCR; + __IO uint32_t RCCR; + __IO uint32_t RIER; + __I uint32_t SR; + __O uint32_t CLR; +} CM_FCM_TypeDef; + +/** + * @brief GPIO + */ +typedef struct { + __I uint16_t PIDRA; + uint8_t RESERVED0[2]; + __IO uint16_t PODRA; + __IO uint16_t POERA; + __IO uint16_t POSRA; + __IO uint16_t PORRA; + __IO uint16_t POTRA; + uint8_t RESERVED1[2]; + __I uint16_t PIDRB; + uint8_t RESERVED2[2]; + __IO uint16_t PODRB; + __IO uint16_t POERB; + __IO uint16_t POSRB; + __IO uint16_t PORRB; + __IO uint16_t POTRB; + uint8_t RESERVED3[2]; + __I uint16_t PIDRC; + uint8_t RESERVED4[2]; + __IO uint16_t PODRC; + __IO uint16_t POERC; + __IO uint16_t POSRC; + __IO uint16_t PORRC; + __IO uint16_t POTRC; + uint8_t RESERVED5[2]; + __I uint16_t PIDRD; + uint8_t RESERVED6[2]; + __IO uint16_t PODRD; + __IO uint16_t POERD; + __IO uint16_t POSRD; + __IO uint16_t PORRD; + __IO uint16_t POTRD; + uint8_t RESERVED7[2]; + __I uint16_t PIDRE; + uint8_t RESERVED8[2]; + __IO uint16_t PODRE; + __IO uint16_t POERE; + __IO uint16_t POSRE; + __IO uint16_t PORRE; + __IO uint16_t POTRE; + uint8_t RESERVED9[2]; + __I uint16_t PIDRH; + uint8_t RESERVED10[2]; + __IO uint16_t PODRH; + __IO uint16_t POERH; + __IO uint16_t POSRH; + __IO uint16_t PORRH; + __IO uint16_t POTRH; + uint8_t RESERVED11[918]; + __IO uint16_t PSPCR; + uint8_t RESERVED12[2]; + __IO uint16_t PCCR; + uint8_t RESERVED13[2]; + __IO uint16_t PWPR; + uint8_t RESERVED14[2]; + __IO uint16_t PCRA0; + __IO uint16_t PFSRA0; + __IO uint16_t PCRA1; + __IO uint16_t PFSRA1; + __IO uint16_t PCRA2; + __IO uint16_t PFSRA2; + __IO uint16_t PCRA3; + __IO uint16_t PFSRA3; + __IO uint16_t PCRA4; + __IO uint16_t PFSRA4; + __IO uint16_t PCRA5; + __IO uint16_t PFSRA5; + __IO uint16_t PCRA6; + __IO uint16_t PFSRA6; + __IO uint16_t PCRA7; + __IO uint16_t PFSRA7; + __IO uint16_t PCRA8; + __IO uint16_t PFSRA8; + __IO uint16_t PCRA9; + __IO uint16_t PFSRA9; + __IO uint16_t PCRA10; + __IO uint16_t PFSRA10; + __IO uint16_t PCRA11; + __IO uint16_t PFSRA11; + __IO uint16_t PCRA12; + __IO uint16_t PFSRA12; + __IO uint16_t PCRA13; + __IO uint16_t PFSRA13; + __IO uint16_t PCRA14; + __IO uint16_t PFSRA14; + __IO uint16_t PCRA15; + __IO uint16_t PFSRA15; + __IO uint16_t PCRB0; + __IO uint16_t PFSRB0; + __IO uint16_t PCRB1; + __IO uint16_t PFSRB1; + __IO uint16_t PCRB2; + __IO uint16_t PFSRB2; + __IO uint16_t PCRB3; + __IO uint16_t PFSRB3; + __IO uint16_t PCRB4; + __IO uint16_t PFSRB4; + __IO uint16_t PCRB5; + __IO uint16_t PFSRB5; + __IO uint16_t PCRB6; + __IO uint16_t PFSRB6; + __IO uint16_t PCRB7; + __IO uint16_t PFSRB7; + __IO uint16_t PCRB8; + __IO uint16_t PFSRB8; + __IO uint16_t PCRB9; + __IO uint16_t PFSRB9; + __IO uint16_t PCRB10; + __IO uint16_t PFSRB10; + __IO uint16_t PCRB11; + __IO uint16_t PFSRB11; + __IO uint16_t PCRB12; + __IO uint16_t PFSRB12; + __IO uint16_t PCRB13; + __IO uint16_t PFSRB13; + __IO uint16_t PCRB14; + __IO uint16_t PFSRB14; + __IO uint16_t PCRB15; + __IO uint16_t PFSRB15; + __IO uint16_t PCRC0; + __IO uint16_t PFSRC0; + __IO uint16_t PCRC1; + __IO uint16_t PFSRC1; + __IO uint16_t PCRC2; + __IO uint16_t PFSRC2; + __IO uint16_t PCRC3; + __IO uint16_t PFSRC3; + __IO uint16_t PCRC4; + __IO uint16_t PFSRC4; + __IO uint16_t PCRC5; + __IO uint16_t PFSRC5; + __IO uint16_t PCRC6; + __IO uint16_t PFSRC6; + __IO uint16_t PCRC7; + __IO uint16_t PFSRC7; + __IO uint16_t PCRC8; + __IO uint16_t PFSRC8; + __IO uint16_t PCRC9; + __IO uint16_t PFSRC9; + __IO uint16_t PCRC10; + __IO uint16_t PFSRC10; + __IO uint16_t PCRC11; + __IO uint16_t PFSRC11; + __IO uint16_t PCRC12; + __IO uint16_t PFSRC12; + __IO uint16_t PCRC13; + __IO uint16_t PFSRC13; + __IO uint16_t PCRC14; + __IO uint16_t PFSRC14; + __IO uint16_t PCRC15; + __IO uint16_t PFSRC15; + __IO uint16_t PCRD0; + __IO uint16_t PFSRD0; + __IO uint16_t PCRD1; + __IO uint16_t PFSRD1; + __IO uint16_t PCRD2; + __IO uint16_t PFSRD2; + uint8_t RESERVED15[20]; + __IO uint16_t PCRD8; + __IO uint16_t PFSRD8; + __IO uint16_t PCRD9; + __IO uint16_t PFSRD9; + __IO uint16_t PCRD10; + __IO uint16_t PFSRD10; + __IO uint16_t PCRD11; + __IO uint16_t PFSRD11; + uint8_t RESERVED16[16]; + __IO uint16_t PCRE0; + __IO uint16_t PFSRE0; + __IO uint16_t PCRE1; + __IO uint16_t PFSRE1; + __IO uint16_t PCRE2; + __IO uint16_t PFSRE2; + __IO uint16_t PCRE3; + __IO uint16_t PFSRE3; + __IO uint16_t PCRE4; + __IO uint16_t PFSRE4; + uint8_t RESERVED17[28]; + __IO uint16_t PCRE12; + __IO uint16_t PFSRE12; + __IO uint16_t PCRE13; + __IO uint16_t PFSRE13; + __IO uint16_t PCRE14; + __IO uint16_t PFSRE14; + __IO uint16_t PCRE15; + __IO uint16_t PFSRE15; + __IO uint16_t PCRH0; + __IO uint16_t PFSRH0; + __IO uint16_t PCRH1; + __IO uint16_t PFSRH1; + __IO uint16_t PCRH2; + __IO uint16_t PFSRH2; +} CM_GPIO_TypeDef; + +/** + * @brief HASH + */ +typedef struct { + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED1[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +} CM_HASH_TypeDef; + +/** + * @brief I2C + */ +typedef struct { + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t SLR0; + __IO uint32_t SLR1; + __IO uint32_t SLTR; + __IO uint32_t SR; + __O uint32_t CLR; + __O uint8_t DTR; + uint8_t RESERVED0[3]; + __I uint8_t DRR; + uint8_t RESERVED1[3]; + __IO uint32_t CCR; + __IO uint32_t FLTR; + __IO uint32_t FSTR; + __IO uint32_t SLVADDR; +} CM_I2C_TypeDef; + +/** + * @brief ICG + */ +typedef struct { + __I uint32_t ICG0; + __I uint32_t ICG1; + uint8_t RESERVED0[4]; + __I uint32_t ICG3; + __I uint32_t ICG4; +} CM_ICG_TypeDef; + +/** + * @brief INTC + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint32_t NMIER; + __IO uint32_t NMIFR; + __IO uint32_t NMIFCR; + __IO uint32_t EIRQCR0; + __IO uint32_t EIRQCR1; + __IO uint32_t EIRQCR2; + __IO uint32_t EIRQCR3; + __IO uint32_t EIRQCR4; + __IO uint32_t EIRQCR5; + __IO uint32_t EIRQCR6; + __IO uint32_t EIRQCR7; + __IO uint32_t EIRQCR8; + __IO uint32_t EIRQCR9; + __IO uint32_t EIRQCR10; + __IO uint32_t EIRQCR11; + __IO uint32_t EIRQCR12; + __IO uint32_t EIRQCR13; + __IO uint32_t EIRQCR14; + __IO uint32_t EIRQCR15; + __IO uint32_t WKEN; + __IO uint32_t EIFR; + __IO uint32_t EIFCR; + __IO uint32_t INTSEL0; + __IO uint32_t INTSEL1; + __IO uint32_t INTSEL2; + __IO uint32_t INTSEL3; + __IO uint32_t INTSEL4; + __IO uint32_t INTSEL5; + __IO uint32_t INTSEL6; + __IO uint32_t INTSEL7; + __IO uint32_t INTSEL8; + __IO uint32_t INTSEL9; + __IO uint32_t INTSEL10; + __IO uint32_t INTSEL11; + __IO uint32_t INTSEL12; + __IO uint32_t INTSEL13; + __IO uint32_t INTSEL14; + __IO uint32_t INTSEL15; + __IO uint32_t INTEN0; + __IO uint32_t INTEN1; + __IO uint32_t INTEN2; + __IO uint32_t INTEN3; + __IO uint32_t INTEN4; + __IO uint32_t INTEN5; + __IO uint32_t INTEN6; + __IO uint32_t INTEN7; + __IO uint32_t INTEN8; + __IO uint32_t INTEN9; + __IO uint32_t INTEN10; + __IO uint32_t INTEN11; + __IO uint32_t INTEN12; + __IO uint32_t INTEN13; + __IO uint32_t INTEN14; + __IO uint32_t INTEN15; + __IO uint32_t SWIER; + __IO uint32_t EVTER; + __IO uint32_t IER; +} CM_INTC_TypeDef; + +/** + * @brief KEYSCAN + */ +typedef struct { + __IO uint32_t SCR; + __IO uint32_t SER; + __IO uint32_t SSR; +} CM_KEYSCAN_TypeDef; + +/** + * @brief MCAN + */ +typedef struct { + uint8_t RESERVED0[4]; + __IO uint32_t ENDN; + uint8_t RESERVED1[4]; + __IO uint32_t DBTP; + __IO uint32_t TEST; + __IO uint32_t RWD; + __IO uint32_t CCCR; + __IO uint32_t NBTP; + __IO uint32_t TSCC; + __IO uint32_t TSCV; + __IO uint32_t TOCC; + __IO uint32_t TOCV; + uint8_t RESERVED2[16]; + __I uint32_t ECR; + __I uint32_t PSR; + __IO uint32_t TDCR; + uint8_t RESERVED3[4]; + __IO uint32_t IR; + __IO uint32_t IE; + __IO uint32_t ILS; + __IO uint32_t ILE; + uint8_t RESERVED4[32]; + __IO uint32_t GFC; + __IO uint32_t SIDFC; + __IO uint32_t XIDFC; + uint8_t RESERVED5[4]; + __IO uint32_t XIDAM; + __I uint32_t HPMS; + __IO uint32_t NDAT1; + __IO uint32_t NDAT2; + __IO uint32_t RXF0C; + __I uint32_t RXF0S; + __IO uint32_t RXF0A; + __IO uint32_t RXBC; + __IO uint32_t RXF1C; + __I uint32_t RXF1S; + __IO uint32_t RXF1A; + __IO uint32_t RXESC; + __IO uint32_t TXBC; + __I uint32_t TXFQS; + __IO uint32_t TXESC; + __I uint32_t TXBRP; + __IO uint32_t TXBAR; + __IO uint32_t TXBCR; + __I uint32_t TXBTO; + __I uint32_t TXBCF; + __IO uint32_t TXBTIE; + __IO uint32_t TXBCIE; + uint8_t RESERVED6[8]; + __IO uint32_t TXEFC; + __I uint32_t TXEFS; + __IO uint32_t TXEFA; +} CM_MCAN_TypeDef; + +/** + * @brief MPU + */ +typedef struct { + __IO uint32_t RGD0; + __IO uint32_t RGD1; + __IO uint32_t RGD2; + __IO uint32_t RGD3; + __IO uint32_t RGD4; + __IO uint32_t RGD5; + __IO uint32_t RGD6; + __IO uint32_t RGD7; + __IO uint32_t RGD8; + __IO uint32_t RGD9; + __IO uint32_t RGD10; + __IO uint32_t RGD11; + __IO uint32_t RGD12; + __IO uint32_t RGD13; + __IO uint32_t RGD14; + __IO uint32_t RGD15; + __I uint32_t SR; + __O uint32_t ECLR; + __IO uint32_t WP; + __IO uint32_t IPPR; + __IO uint32_t MSPPBA; + __IO uint32_t MSPPCTL; + __IO uint32_t PSPPBA; + __IO uint32_t PSPPCTL; + __IO uint32_t S1RGE; + __IO uint32_t S1RGWP; + __IO uint32_t S1RGRP; + __IO uint32_t S1CR; + __IO uint32_t S2RGE; + __IO uint32_t S2RGWP; + __IO uint32_t S2RGRP; + __IO uint32_t S2CR; +} CM_MPU_TypeDef; + +/** + * @brief PERIC + */ +typedef struct { + uint8_t RESERVED0[12]; + __IO uint32_t SMC_ENAR; + uint8_t RESERVED1[4]; + __IO uint32_t TMR_SYNENR; + uint8_t RESERVED2[4]; + __IO uint32_t USART1_NFC; +} CM_PERIC_TypeDef; + +/** + * @brief PWC + */ +typedef struct { + __IO uint32_t FCG0; + __IO uint32_t FCG1; + __IO uint32_t FCG2; + __IO uint32_t FCG3; + __IO uint32_t FCG0PC; + uint8_t RESERVED0[17388]; + __IO uint16_t WKTCR; + uint8_t RESERVED1[2046]; + __IO uint8_t PWRC0; + uint8_t RESERVED2[3]; + __IO uint8_t PWRC1; + uint8_t RESERVED3[3]; + __IO uint8_t PWRC2; + uint8_t RESERVED4[3]; + __IO uint8_t PWRC3; + uint8_t RESERVED5[3]; + __IO uint8_t PWRC4; + uint8_t RESERVED6[3]; + __IO uint8_t PVDCR0; + uint8_t RESERVED7[3]; + __IO uint8_t PVDCR1; + uint8_t RESERVED8[3]; + __IO uint8_t PVDFCR; + uint8_t RESERVED9[3]; + __IO uint8_t PVDLCR; + uint8_t RESERVED10[7]; + __IO uint8_t PDWKE0; + uint8_t RESERVED11[3]; + __IO uint8_t PDWKE1; + uint8_t RESERVED12[3]; + __IO uint8_t PDWKE2; + uint8_t RESERVED13[3]; + __IO uint8_t PDWKES; + uint8_t RESERVED14[3]; + __IO uint8_t PDWKF0; + uint8_t RESERVED15[3]; + __IO uint8_t PDWKF1; + uint8_t RESERVED16[3]; + __IO uint8_t PWRC5; + uint8_t RESERVED17[3]; + __IO uint8_t PWRC6; + uint8_t RESERVED18[123]; + __IO uint8_t PVDICR; + uint8_t RESERVED19[3]; + __IO uint8_t PVDDSR; + uint8_t RESERVED20[3]; + __IO uint32_t RAMPC0; + __IO uint32_t RAMOPM; + __IO uint32_t PRAMLPC; + uint8_t RESERVED21[29496]; + __IO uint16_t STPMCR; + uint8_t RESERVED22[1008]; + __IO uint16_t FPRC; +} CM_PWC_TypeDef; + +/** + * @brief QSPI + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t CSCR; + __IO uint32_t FCR; + __I uint32_t SR; + __IO uint32_t DCOM; + __IO uint32_t CCMD; + __IO uint32_t XCMD; + uint8_t RESERVED0[8]; + __O uint32_t SR2; + uint8_t RESERVED1[2012]; + __IO uint32_t EXAR; +} CM_QSPI_TypeDef; + +/** + * @brief RMU + */ +typedef struct { + __IO uint32_t FRST0; + __IO uint32_t FRST1; + __IO uint32_t FRST2; + __IO uint32_t FRST3; + __IO uint8_t PRSTCR0; + uint8_t RESERVED0[3]; + __IO uint32_t RSTF0; +} CM_RMU_TypeDef; + +/** + * @brief RTC + */ +typedef struct { + __IO uint8_t CR0; + uint8_t RESERVED0[3]; + __IO uint8_t CR1; + uint8_t RESERVED1[3]; + __IO uint8_t CR2; + uint8_t RESERVED2[3]; + __IO uint8_t CR3; + uint8_t RESERVED3[3]; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t WEEK; + uint8_t RESERVED7[3]; + __IO uint8_t DAY; + uint8_t RESERVED8[3]; + __IO uint8_t MON; + uint8_t RESERVED9[3]; + __IO uint8_t YEAR; + uint8_t RESERVED10[3]; + __IO uint8_t ALMMIN; + uint8_t RESERVED11[3]; + __IO uint8_t ALMHOUR; + uint8_t RESERVED12[3]; + __IO uint8_t ALMWEEK; + uint8_t RESERVED13[3]; + __IO uint8_t ERRCRH; + uint8_t RESERVED14[3]; + __IO uint8_t ERRCRL; +} CM_RTC_TypeDef; + +/** + * @brief SMC + */ +typedef struct { + __I uint32_t STSR; + uint8_t RESERVED0[4]; + __O uint32_t STCR0; + __O uint32_t STCR1; + __O uint32_t CMDR; + __O uint32_t TMCR; + __O uint32_t CPCR; + uint8_t RESERVED1[4]; + __IO uint32_t RFTR; + uint8_t RESERVED2[220]; + __I uint32_t TMSR0; + __I uint32_t CPSR0; + uint8_t RESERVED3[248]; + __IO uint32_t BACR; + uint8_t RESERVED4[4]; + __IO uint32_t CSCR0; + __IO uint32_t CSCR1; +} CM_SMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct { + __IO uint32_t DR; + __IO uint32_t CR; + uint8_t RESERVED0[4]; + __IO uint32_t CFG1; + uint8_t RESERVED1[4]; + __IO uint32_t SR; + __IO uint32_t CFG2; +} CM_SPI_TypeDef; + +/** + * @brief SRAMC + */ +typedef struct { + __IO uint32_t WTCR; + __IO uint32_t WTPR; + __IO uint32_t CKCR; + __IO uint32_t CKPR; + __IO uint32_t CKSR; + __IO uint32_t SRAM0_EIEN; + __IO uint32_t SRAM0_EIBIT0; + __IO uint32_t SRAM0_EIBIT1; + __I uint32_t SRAM0_ECCERRADDR; + __IO uint32_t SRAMB_EIEN; + __IO uint32_t SRAMB_EIBIT0; + __IO uint32_t SRAMB_EIBIT1; + __I uint32_t SRAMB_ECCERRADDR; +} CM_SRAMC_TypeDef; + +/** + * @brief SWDT + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_SWDT_TypeDef; + +/** + * @brief TMR0 + */ +typedef struct { + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t STFLR; +} CM_TMR0_TypeDef; + +/** + * @brief TMR4 + */ +typedef struct { + __IO uint16_t OCCRUH; + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWL; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRXH; + uint8_t RESERVED6[2]; + __IO uint16_t OCCRXL; + uint8_t RESERVED7[2]; + __IO uint16_t OCSRU; + __IO uint16_t OCERU; + __IO uint16_t OCSRV; + __IO uint16_t OCERV; + __IO uint16_t OCSRW; + __IO uint16_t OCERW; + __IO uint16_t OCSRX; + __IO uint16_t OCERX; + __IO uint16_t OCMRUH; + uint8_t RESERVED8[2]; + __IO uint32_t OCMRUL; + __IO uint16_t OCMRVH; + uint8_t RESERVED9[2]; + __IO uint32_t OCMRVL; + __IO uint16_t OCMRWH; + uint8_t RESERVED10[2]; + __IO uint32_t OCMRWL; + __IO uint16_t OCMRXH; + uint8_t RESERVED11[2]; + __IO uint32_t OCMRXL; + __IO uint16_t CPSR; + uint8_t RESERVED12[2]; + __IO uint16_t CNTR; + uint8_t RESERVED13[2]; + __IO uint16_t CCSR; + __IO uint16_t CVPR; + __IO uint32_t PSCR; + uint8_t RESERVED14[34]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED15[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED16[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + uint8_t RESERVED17[2]; + __IO uint16_t PFSRX; + __IO uint16_t PDARX; + __IO uint16_t PDBRX; + __IO uint16_t POCRU; + uint8_t RESERVED18[2]; + __IO uint16_t POCRV; + uint8_t RESERVED19[2]; + __IO uint16_t POCRW; + uint8_t RESERVED20[2]; + __IO uint16_t POCRX; + uint8_t RESERVED21[2]; + __IO uint16_t SCCRUH; + uint8_t RESERVED22[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED23[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED24[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED25[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED26[2]; + __IO uint16_t SCCRWL; + uint8_t RESERVED27[2]; + __IO uint16_t SCCRXH; + uint8_t RESERVED28[2]; + __IO uint16_t SCCRXL; + uint8_t RESERVED29[2]; + __IO uint16_t SCSRUH; + __IO uint16_t SCMRUH; + __IO uint16_t SCSRUL; + __IO uint16_t SCMRUL; + __IO uint16_t SCSRVH; + __IO uint16_t SCMRVH; + __IO uint16_t SCSRVL; + __IO uint16_t SCMRVL; + __IO uint16_t SCSRWH; + __IO uint16_t SCMRWH; + __IO uint16_t SCSRWL; + __IO uint16_t SCMRWL; + __IO uint16_t SCSRXH; + __IO uint16_t SCMRXH; + __IO uint16_t SCSRXL; + __IO uint16_t SCMRXL; + __IO uint16_t SCER; + uint8_t RESERVED30[2]; + __IO uint32_t RCSR; + __IO uint16_t SCIR; + uint8_t RESERVED31[2]; + __IO uint16_t SCFR; +} CM_TMR4_TypeDef; + +/** + * @brief TMR6 + */ +typedef struct { + __IO uint32_t CNTER; + __IO uint32_t UPDAR; + uint8_t RESERVED0[56]; + __IO uint32_t PERAR; + __IO uint32_t PERBR; + __IO uint32_t PERCR; + uint8_t RESERVED1[52]; + __IO uint32_t GCMAR; + __IO uint32_t GCMBR; + __IO uint32_t GCMCR; + __IO uint32_t GCMDR; + __IO uint32_t GCMER; + __IO uint32_t GCMFR; + uint8_t RESERVED2[40]; + __IO uint32_t SCMAR; + __IO uint32_t SCMBR; + __IO uint32_t SCMCR; + __IO uint32_t SCMDR; + __IO uint32_t SCMER; + __IO uint32_t SCMFR; + uint8_t RESERVED3[40]; + __IO uint32_t DTUAR; + __IO uint32_t DTDAR; + __IO uint32_t DTUBR; + __IO uint32_t DTDBR; + uint8_t RESERVED4[48]; + __IO uint32_t GCONR; + __IO uint32_t ICONR; + __IO uint32_t BCONR; + __IO uint32_t DCONR; + uint8_t RESERVED5[4]; + __IO uint32_t PCNAR; + __IO uint32_t PCNBR; + __IO uint32_t FCNGR; + __IO uint32_t VPERR; + __IO uint32_t STFLR; + uint8_t RESERVED6[24]; + __IO uint32_t HSTAR; + __IO uint32_t HSTPR; + __IO uint32_t HCLRR; + __IO uint32_t HUPDR; + __IO uint32_t HCPAR; + __IO uint32_t HCPBR; + __IO uint32_t HCUPR; + __IO uint32_t HCDOR; +} CM_TMR6_TypeDef; + +/** + * @brief TMR6_COMMON + */ +typedef struct { + uint8_t RESERVED0[236]; + __IO uint32_t FCNTR; + __IO uint32_t SSTAR; + __IO uint32_t SSTPR; + __IO uint32_t SCLRR; + __IO uint32_t SUPDR; +} CM_TMR6_COMMON_TypeDef; + +/** + * @brief TMRA + */ +typedef struct { + __IO uint32_t CNTER; + __IO uint32_t PERAR; + uint8_t RESERVED0[56]; + __IO uint32_t CMPAR1; + __IO uint32_t CMPAR2; + __IO uint32_t CMPAR3; + __IO uint32_t CMPAR4; + __IO uint32_t CMPAR5; + __IO uint32_t CMPAR6; + __IO uint32_t CMPAR7; + __IO uint32_t CMPAR8; + uint8_t RESERVED1[32]; + __IO uint8_t BCSTRL; + __IO uint8_t BCSTRH; + uint8_t RESERVED2[2]; + __IO uint16_t HCONR; + uint8_t RESERVED3[2]; + __IO uint16_t HCUPR; + uint8_t RESERVED4[2]; + __IO uint16_t HCDOR; + uint8_t RESERVED5[2]; + __IO uint16_t ICONR; + uint8_t RESERVED6[2]; + __IO uint16_t ECONR; + uint8_t RESERVED7[2]; + __IO uint16_t FCONR; + uint8_t RESERVED8[2]; + __IO uint16_t STFLR; + uint8_t RESERVED9[34]; + __IO uint16_t BCONR1; + uint8_t RESERVED10[6]; + __IO uint16_t BCONR2; + uint8_t RESERVED11[6]; + __IO uint16_t BCONR3; + uint8_t RESERVED12[6]; + __IO uint16_t BCONR4; + uint8_t RESERVED13[38]; + __IO uint16_t CCONR1; + uint8_t RESERVED14[2]; + __IO uint16_t CCONR2; + uint8_t RESERVED15[2]; + __IO uint16_t CCONR3; + uint8_t RESERVED16[2]; + __IO uint16_t CCONR4; + uint8_t RESERVED17[2]; + __IO uint16_t CCONR5; + uint8_t RESERVED18[2]; + __IO uint16_t CCONR6; + uint8_t RESERVED19[2]; + __IO uint16_t CCONR7; + uint8_t RESERVED20[2]; + __IO uint16_t CCONR8; + uint8_t RESERVED21[34]; + __IO uint16_t PCONR1; + uint8_t RESERVED22[2]; + __IO uint16_t PCONR2; + uint8_t RESERVED23[2]; + __IO uint16_t PCONR3; + uint8_t RESERVED24[2]; + __IO uint16_t PCONR4; + uint8_t RESERVED25[2]; + __IO uint16_t PCONR5; + uint8_t RESERVED26[2]; + __IO uint16_t PCONR6; + uint8_t RESERVED27[2]; + __IO uint16_t PCONR7; + uint8_t RESERVED28[2]; + __IO uint16_t PCONR8; +} CM_TMRA_TypeDef; + +/** + * @brief TRNG + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t MR; + uint8_t RESERVED0[4]; + __I uint32_t DR0; + __I uint32_t DR1; +} CM_TRNG_TypeDef; + +/** + * @brief USART + */ +typedef struct { + __I uint32_t SR; + __IO uint16_t TDR; + __I uint16_t RDR; + __IO uint32_t BRR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t PR; + __I uint32_t LBMC; +} CM_USART_TypeDef; + +/** + * @brief WDT + */ +typedef struct { + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} CM_WDT_TypeDef; + +/******************************************************************************/ +/* Memory Base Address */ +/******************************************************************************/ +#define EFM_BASE (0x00000000UL) /*!< EFM base address in the alias region */ +#define SRAM_BASE (0x1FFF8000UL) /*!< SRAM base address in the alias region */ +#define SMC_BASE (0x60000000UL) /*!< SMC base address in the alias region */ +#define QSPI_BASE (0x98000000UL) /*!< QSPI base address in the alias region */ + +/******************************************************************************/ +/* Device Specific Peripheral Base Address */ +/******************************************************************************/ +#define CM_ADC1_BASE (0x40040000UL) +#define CM_ADC2_BASE (0x40040400UL) +#define CM_ADC3_BASE (0x40040800UL) +#define CM_AES_BASE (0x40008000UL) +#define CM_AOS_BASE (0x40010800UL) +#define CM_CMP1_BASE (0x40038800UL) +#define CM_CMP2_BASE (0x40038900UL) +#define CM_CMP3_BASE (0x40038C00UL) +#define CM_CMP4_BASE (0x40038D00UL) +#define CM_CMU_BASE (0x40048000UL) +#define CM_CRC_BASE (0x40008C00UL) +#define CM_CTC_BASE (0x40049C00UL) +#define CM_DAC_BASE (0x40041000UL) +#define CM_DBGC_BASE (0xE0042000UL) +#define CM_DCU1_BASE (0x40056000UL) +#define CM_DCU2_BASE (0x40056400UL) +#define CM_DCU3_BASE (0x40056800UL) +#define CM_DCU4_BASE (0x40056C00UL) +#define CM_DMA1_BASE (0x40053000UL) +#define CM_DMA2_BASE (0x40053400UL) +#define CM_EFM_BASE (0x40010400UL) +#define CM_EMB0_BASE (0x40017C00UL) +#define CM_EMB1_BASE (0x40017C20UL) +#define CM_EMB2_BASE (0x40017C40UL) +#define CM_EMB3_BASE (0x40017C60UL) +#define CM_FCM_BASE (0x40048400UL) +#define CM_GPIO_BASE (0x40053800UL) +#define CM_HASH_BASE (0x40008400UL) +#define CM_I2C1_BASE (0x4003B400UL) +#define CM_I2C2_BASE (0x4003B800UL) +#define CM_ICG_BASE (0x00000400UL) +#define CM_INTC_BASE (0x40051000UL) +#define CM_KEYSCAN_BASE (0x40050C00UL) +#define CM_MCAN1_BASE (0x40029000UL) +#define CM_MCAN2_BASE (0x40029400UL) +#define CM_MPU_BASE (0x40050000UL) +#define CM_PERIC_BASE (0x40055400UL) +#define CM_PWC_BASE (0x40048000UL) +#define CM_QSPI_BASE (0x9C000000UL) +#define CM_RMU_BASE (0x4004CCE0UL) +#define CM_RTC_BASE (0x4004C000UL) +#define CM_SMC_BASE (0x88000000UL) +#define CM_SPI1_BASE (0x4001C000UL) +#define CM_SPI2_BASE (0x4001C400UL) +#define CM_SPI3_BASE (0x40020000UL) +#define CM_SRAMC_BASE (0x40050800UL) +#define CM_SWDT_BASE (0x40049400UL) +#define CM_TMR0_1_BASE (0x40024000UL) +#define CM_TMR0_2_BASE (0x40024400UL) +#define CM_TMR4_1_BASE (0x40038000UL) +#define CM_TMR4_2_BASE (0x40038400UL) +#define CM_TMR4_3_BASE (0x40038E00UL) +#define CM_TMR6_1_BASE (0x4003C000UL) +#define CM_TMR6_2_BASE (0x4003C400UL) +#define CM_TMR6_COMMON_BASE (0x4003C300UL) +#define CM_TMRA_1_BASE (0x4003A000UL) +#define CM_TMRA_2_BASE (0x4003A400UL) +#define CM_TMRA_3_BASE (0x4003A800UL) +#define CM_TMRA_4_BASE (0x4003AC00UL) +#define CM_TMRA_5_BASE (0x40026000UL) +#define CM_TRNG_BASE (0x40042000UL) +#define CM_USART1_BASE (0x4001CC00UL) +#define CM_USART2_BASE (0x4001D000UL) +#define CM_USART3_BASE (0x4001D400UL) +#define CM_USART4_BASE (0x40020C00UL) +#define CM_USART5_BASE (0x40021000UL) +#define CM_USART6_BASE (0x40021400UL) +#define CM_WDT_BASE (0x40049000UL) + +/******************************************************************************/ +/* Device Specific Peripheral declaration & memory map */ +/******************************************************************************/ +#define CM_ADC1 ((CM_ADC_TypeDef *)CM_ADC1_BASE) +#define CM_ADC2 ((CM_ADC_TypeDef *)CM_ADC2_BASE) +#define CM_ADC3 ((CM_ADC_TypeDef *)CM_ADC3_BASE) +#define CM_AES ((CM_AES_TypeDef *)CM_AES_BASE) +#define CM_AOS ((CM_AOS_TypeDef *)CM_AOS_BASE) +#define CM_CMP1 ((CM_CMP_TypeDef *)CM_CMP1_BASE) +#define CM_CMP2 ((CM_CMP_TypeDef *)CM_CMP2_BASE) +#define CM_CMP3 ((CM_CMP_TypeDef *)CM_CMP3_BASE) +#define CM_CMP4 ((CM_CMP_TypeDef *)CM_CMP4_BASE) +#define CM_CMU ((CM_CMU_TypeDef *)CM_CMU_BASE) +#define CM_CRC ((CM_CRC_TypeDef *)CM_CRC_BASE) +#define CM_CTC ((CM_CTC_TypeDef *)CM_CTC_BASE) +#define CM_DAC ((CM_DAC_TypeDef *)CM_DAC_BASE) +#define CM_DBGC ((CM_DBGC_TypeDef *)CM_DBGC_BASE) +#define CM_DCU1 ((CM_DCU_TypeDef *)CM_DCU1_BASE) +#define CM_DCU2 ((CM_DCU_TypeDef *)CM_DCU2_BASE) +#define CM_DCU3 ((CM_DCU_TypeDef *)CM_DCU3_BASE) +#define CM_DCU4 ((CM_DCU_TypeDef *)CM_DCU4_BASE) +#define CM_DMA1 ((CM_DMA_TypeDef *)CM_DMA1_BASE) +#define CM_DMA2 ((CM_DMA_TypeDef *)CM_DMA2_BASE) +#define CM_EFM ((CM_EFM_TypeDef *)CM_EFM_BASE) +#define CM_EMB0 ((CM_EMB_TypeDef *)CM_EMB0_BASE) +#define CM_EMB1 ((CM_EMB_TypeDef *)CM_EMB1_BASE) +#define CM_EMB2 ((CM_EMB_TypeDef *)CM_EMB2_BASE) +#define CM_EMB3 ((CM_EMB_TypeDef *)CM_EMB3_BASE) +#define CM_FCM ((CM_FCM_TypeDef *)CM_FCM_BASE) +#define CM_GPIO ((CM_GPIO_TypeDef *)CM_GPIO_BASE) +#define CM_HASH ((CM_HASH_TypeDef *)CM_HASH_BASE) +#define CM_I2C1 ((CM_I2C_TypeDef *)CM_I2C1_BASE) +#define CM_I2C2 ((CM_I2C_TypeDef *)CM_I2C2_BASE) +#define CM_ICG ((CM_ICG_TypeDef *)CM_ICG_BASE) +#define CM_INTC ((CM_INTC_TypeDef *)CM_INTC_BASE) +#define CM_KEYSCAN ((CM_KEYSCAN_TypeDef *)CM_KEYSCAN_BASE) +#define CM_MCAN1 ((CM_MCAN_TypeDef *)CM_MCAN1_BASE) +#define CM_MCAN2 ((CM_MCAN_TypeDef *)CM_MCAN2_BASE) +#define CM_MPU ((CM_MPU_TypeDef *)CM_MPU_BASE) +#define CM_PERIC ((CM_PERIC_TypeDef *)CM_PERIC_BASE) +#define CM_PWC ((CM_PWC_TypeDef *)CM_PWC_BASE) +#define CM_QSPI ((CM_QSPI_TypeDef *)CM_QSPI_BASE) +#define CM_RMU ((CM_RMU_TypeDef *)CM_RMU_BASE) +#define CM_RTC ((CM_RTC_TypeDef *)CM_RTC_BASE) +#define CM_SMC ((CM_SMC_TypeDef *)CM_SMC_BASE) +#define CM_SPI1 ((CM_SPI_TypeDef *)CM_SPI1_BASE) +#define CM_SPI2 ((CM_SPI_TypeDef *)CM_SPI2_BASE) +#define CM_SPI3 ((CM_SPI_TypeDef *)CM_SPI3_BASE) +#define CM_SRAMC ((CM_SRAMC_TypeDef *)CM_SRAMC_BASE) +#define CM_SWDT ((CM_SWDT_TypeDef *)CM_SWDT_BASE) +#define CM_TMR0_1 ((CM_TMR0_TypeDef *)CM_TMR0_1_BASE) +#define CM_TMR0_2 ((CM_TMR0_TypeDef *)CM_TMR0_2_BASE) +#define CM_TMR4_1 ((CM_TMR4_TypeDef *)CM_TMR4_1_BASE) +#define CM_TMR4_2 ((CM_TMR4_TypeDef *)CM_TMR4_2_BASE) +#define CM_TMR4_3 ((CM_TMR4_TypeDef *)CM_TMR4_3_BASE) +#define CM_TMR6_1 ((CM_TMR6_TypeDef *)CM_TMR6_1_BASE) +#define CM_TMR6_2 ((CM_TMR6_TypeDef *)CM_TMR6_2_BASE) +#define CM_TMR6_COMMON ((CM_TMR6_COMMON_TypeDef *)CM_TMR6_COMMON_BASE) +#define CM_TMRA_1 ((CM_TMRA_TypeDef *)CM_TMRA_1_BASE) +#define CM_TMRA_2 ((CM_TMRA_TypeDef *)CM_TMRA_2_BASE) +#define CM_TMRA_3 ((CM_TMRA_TypeDef *)CM_TMRA_3_BASE) +#define CM_TMRA_4 ((CM_TMRA_TypeDef *)CM_TMRA_4_BASE) +#define CM_TMRA_5 ((CM_TMRA_TypeDef *)CM_TMRA_5_BASE) +#define CM_TRNG ((CM_TRNG_TypeDef *)CM_TRNG_BASE) +#define CM_USART1 ((CM_USART_TypeDef *)CM_USART1_BASE) +#define CM_USART2 ((CM_USART_TypeDef *)CM_USART2_BASE) +#define CM_USART3 ((CM_USART_TypeDef *)CM_USART3_BASE) +#define CM_USART4 ((CM_USART_TypeDef *)CM_USART4_BASE) +#define CM_USART5 ((CM_USART_TypeDef *)CM_USART5_BASE) +#define CM_USART6 ((CM_USART_TypeDef *)CM_USART6_BASE) +#define CM_WDT ((CM_WDT_TypeDef *)CM_WDT_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************* + Bit definition for Peripheral ADC +*******************************************************************************/ +/* Bit definition for ADC_STR register */ +#define ADC_STR_STRT (0x01U) + +/* Bit definition for ADC_CR0 register */ +#define ADC_CR0_MS_POS (0U) +#define ADC_CR0_MS (0x0007U) +#define ADC_CR0_ACCSEL_POS (4U) +#define ADC_CR0_ACCSEL (0x0030U) +#define ADC_CR0_ACCSEL_0 (0x0010U) +#define ADC_CR0_ACCSEL_1 (0x0020U) +#define ADC_CR0_CLREN_POS (6U) +#define ADC_CR0_CLREN (0x0040U) +#define ADC_CR0_DFMT_POS (7U) +#define ADC_CR0_DFMT (0x0080U) +#define ADC_CR0_AVCNT_POS (8U) +#define ADC_CR0_AVCNT (0x0700U) + +/* Bit definition for ADC_CR1 register */ +#define ADC_CR1_RSCHSEL_POS (2U) +#define ADC_CR1_RSCHSEL (0x0004U) + +/* Bit definition for ADC_CR2 register */ +#define ADC_CR2_OVSS_POS (8U) +#define ADC_CR2_OVSS (0x0F00U) +#define ADC_CR2_OVSMOD_POS (12U) +#define ADC_CR2_OVSMOD (0x1000U) + +/* Bit definition for ADC_TRGSR register */ +#define ADC_TRGSR_TRGSELA_POS (0U) +#define ADC_TRGSR_TRGSELA (0x0003U) +#define ADC_TRGSR_TRGSELA_0 (0x0001U) +#define ADC_TRGSR_TRGSELA_1 (0x0002U) +#define ADC_TRGSR_TRGENA_POS (7U) +#define ADC_TRGSR_TRGENA (0x0080U) +#define ADC_TRGSR_TRGSELB_POS (8U) +#define ADC_TRGSR_TRGSELB (0x0300U) +#define ADC_TRGSR_TRGSELB_0 (0x0100U) +#define ADC_TRGSR_TRGSELB_1 (0x0200U) +#define ADC_TRGSR_TRGENB_POS (15U) +#define ADC_TRGSR_TRGENB (0x8000U) + +/* Bit definition for ADC_CHSELRA register */ +#define ADC_CHSELRA_CHSELA (0x0000FFFFUL) + +/* Bit definition for ADC_CHSELRB register */ +#define ADC_CHSELRB_CHSELB (0x0000FFFFUL) + +/* Bit definition for ADC_AVCHSELR register */ +#define ADC_AVCHSELR_AVCHSEL (0x0000FFFFUL) + +/* Bit definition for ADC_EXCHSELR register */ +#define ADC_EXCHSELR_EXCHSEL (0x01U) + +/* Bit definition for ADC_SSTR0 register */ +#define ADC_SSTR0 (0xFFU) + +/* Bit definition for ADC_SSTR1 register */ +#define ADC_SSTR1 (0xFFU) + +/* Bit definition for ADC_SSTR2 register */ +#define ADC_SSTR2 (0xFFU) + +/* Bit definition for ADC_SSTR3 register */ +#define ADC_SSTR3 (0xFFU) + +/* Bit definition for ADC_SSTR4 register */ +#define ADC_SSTR4 (0xFFU) + +/* Bit definition for ADC_SSTR5 register */ +#define ADC_SSTR5 (0xFFU) + +/* Bit definition for ADC_SSTR6 register */ +#define ADC_SSTR6 (0xFFU) + +/* Bit definition for ADC_SSTR7 register */ +#define ADC_SSTR7 (0xFFU) + +/* Bit definition for ADC_SSTR8 register */ +#define ADC_SSTR8 (0xFFU) + +/* Bit definition for ADC_SSTR9 register */ +#define ADC_SSTR9 (0xFFU) + +/* Bit definition for ADC_SSTR10 register */ +#define ADC_SSTR10 (0xFFU) + +/* Bit definition for ADC_SSTR11 register */ +#define ADC_SSTR11 (0xFFU) + +/* Bit definition for ADC_SSTR12 register */ +#define ADC_SSTR12 (0xFFU) + +/* Bit definition for ADC_SSTR13 register */ +#define ADC_SSTR13 (0xFFU) + +/* Bit definition for ADC_SSTR14 register */ +#define ADC_SSTR14 (0xFFU) + +/* Bit definition for ADC_SSTR15 register */ +#define ADC_SSTR15 (0xFFU) + +/* Bit definition for ADC_CHMUXR0 register */ +#define ADC_CHMUXR0_CH00MUX_POS (0U) +#define ADC_CHMUXR0_CH00MUX (0x000FU) +#define ADC_CHMUXR0_CH01MUX_POS (4U) +#define ADC_CHMUXR0_CH01MUX (0x00F0U) +#define ADC_CHMUXR0_CH02MUX_POS (8U) +#define ADC_CHMUXR0_CH02MUX (0x0F00U) +#define ADC_CHMUXR0_CH03MUX_POS (12U) +#define ADC_CHMUXR0_CH03MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR1 register */ +#define ADC_CHMUXR1_CH04MUX_POS (0U) +#define ADC_CHMUXR1_CH04MUX (0x000FU) +#define ADC_CHMUXR1_CH05MUX_POS (4U) +#define ADC_CHMUXR1_CH05MUX (0x00F0U) +#define ADC_CHMUXR1_CH06MUX_POS (8U) +#define ADC_CHMUXR1_CH06MUX (0x0F00U) +#define ADC_CHMUXR1_CH07MUX_POS (12U) +#define ADC_CHMUXR1_CH07MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR2 register */ +#define ADC_CHMUXR2_CH08MUX_POS (0U) +#define ADC_CHMUXR2_CH08MUX (0x000FU) +#define ADC_CHMUXR2_CH09MUX_POS (4U) +#define ADC_CHMUXR2_CH09MUX (0x00F0U) +#define ADC_CHMUXR2_CH10MUX_POS (8U) +#define ADC_CHMUXR2_CH10MUX (0x0F00U) +#define ADC_CHMUXR2_CH11MUX_POS (12U) +#define ADC_CHMUXR2_CH11MUX (0xF000U) + +/* Bit definition for ADC_CHMUXR3 register */ +#define ADC_CHMUXR3_CH12MUX_POS (0U) +#define ADC_CHMUXR3_CH12MUX (0x000FU) +#define ADC_CHMUXR3_CH13MUX_POS (4U) +#define ADC_CHMUXR3_CH13MUX (0x00F0U) +#define ADC_CHMUXR3_CH14MUX_POS (8U) +#define ADC_CHMUXR3_CH14MUX (0x0F00U) +#define ADC_CHMUXR3_CH15MUX_POS (12U) +#define ADC_CHMUXR3_CH15MUX (0xF000U) + +/* Bit definition for ADC_ISR register */ +#define ADC_ISR_EOCAF_POS (0U) +#define ADC_ISR_EOCAF (0x01U) +#define ADC_ISR_EOCBF_POS (1U) +#define ADC_ISR_EOCBF (0x02U) +#define ADC_ISR_SASTPDF_POS (4U) +#define ADC_ISR_SASTPDF (0x10U) + +/* Bit definition for ADC_ICR register */ +#define ADC_ICR_EOCAIEN_POS (0U) +#define ADC_ICR_EOCAIEN (0x01U) +#define ADC_ICR_EOCBIEN_POS (1U) +#define ADC_ICR_EOCBIEN (0x02U) + +/* Bit definition for ADC_ISCLRR register */ +#define ADC_ISCLRR_CLREOCAF_POS (0U) +#define ADC_ISCLRR_CLREOCAF (0x01U) +#define ADC_ISCLRR_CLREOCBF_POS (1U) +#define ADC_ISCLRR_CLREOCBF (0x02U) +#define ADC_ISCLRR_CLRSASTPDF_POS (4U) +#define ADC_ISCLRR_CLRSASTPDF (0x10U) + +/* Bit definition for ADC_SYNCCR register */ +#define ADC_SYNCCR_SYNCEN_POS (0U) +#define ADC_SYNCCR_SYNCEN (0x0001U) +#define ADC_SYNCCR_SYNCMD_POS (4U) +#define ADC_SYNCCR_SYNCMD (0x0070U) +#define ADC_SYNCCR_SYNCDLY_POS (8U) +#define ADC_SYNCCR_SYNCDLY (0xFF00U) + +/* Bit definition for ADC_DR0 register */ +#define ADC_DR0 (0xFFFFU) + +/* Bit definition for ADC_DR1 register */ +#define ADC_DR1 (0xFFFFU) + +/* Bit definition for ADC_DR2 register */ +#define ADC_DR2 (0xFFFFU) + +/* Bit definition for ADC_DR3 register */ +#define ADC_DR3 (0xFFFFU) + +/* Bit definition for ADC_DR4 register */ +#define ADC_DR4 (0xFFFFU) + +/* Bit definition for ADC_DR5 register */ +#define ADC_DR5 (0xFFFFU) + +/* Bit definition for ADC_DR6 register */ +#define ADC_DR6 (0xFFFFU) + +/* Bit definition for ADC_DR7 register */ +#define ADC_DR7 (0xFFFFU) + +/* Bit definition for ADC_DR8 register */ +#define ADC_DR8 (0xFFFFU) + +/* Bit definition for ADC_DR9 register */ +#define ADC_DR9 (0xFFFFU) + +/* Bit definition for ADC_DR10 register */ +#define ADC_DR10 (0xFFFFU) + +/* Bit definition for ADC_DR11 register */ +#define ADC_DR11 (0xFFFFU) + +/* Bit definition for ADC_DR12 register */ +#define ADC_DR12 (0xFFFFU) + +/* Bit definition for ADC_DR13 register */ +#define ADC_DR13 (0xFFFFU) + +/* Bit definition for ADC_DR14 register */ +#define ADC_DR14 (0xFFFFU) + +/* Bit definition for ADC_DR15 register */ +#define ADC_DR15 (0xFFFFU) + +/* Bit definition for ADC_AWDCR register */ +#define ADC_AWDCR_AWD0EN_POS (0U) +#define ADC_AWDCR_AWD0EN (0x0001U) +#define ADC_AWDCR_AWD0IEN_POS (1U) +#define ADC_AWDCR_AWD0IEN (0x0002U) +#define ADC_AWDCR_AWD0MD_POS (2U) +#define ADC_AWDCR_AWD0MD (0x0004U) +#define ADC_AWDCR_AWD1EN_POS (4U) +#define ADC_AWDCR_AWD1EN (0x0010U) +#define ADC_AWDCR_AWD1IEN_POS (5U) +#define ADC_AWDCR_AWD1IEN (0x0020U) +#define ADC_AWDCR_AWD1MD_POS (6U) +#define ADC_AWDCR_AWD1MD (0x0040U) +#define ADC_AWDCR_AWDCM_POS (8U) +#define ADC_AWDCR_AWDCM (0x0300U) +#define ADC_AWDCR_AWDCM_0 (0x0100U) +#define ADC_AWDCR_AWDCM_1 (0x0200U) + +/* Bit definition for ADC_AWDSR register */ +#define ADC_AWDSR_AWD0F_POS (0U) +#define ADC_AWDSR_AWD0F (0x01U) +#define ADC_AWDSR_AWD1F_POS (1U) +#define ADC_AWDSR_AWD1F (0x02U) +#define ADC_AWDSR_AWDCMF_POS (4U) +#define ADC_AWDSR_AWDCMF (0x10U) + +/* Bit definition for ADC_AWDSCLRR register */ +#define ADC_AWDSCLRR_CLRAWD0F_POS (0U) +#define ADC_AWDSCLRR_CLRAWD0F (0x01U) +#define ADC_AWDSCLRR_CLRAWD1F_POS (1U) +#define ADC_AWDSCLRR_CLRAWD1F (0x02U) +#define ADC_AWDSCLRR_CLRAWDCMF_POS (4U) +#define ADC_AWDSCLRR_CLRAWDCMF (0x10U) + +/* Bit definition for ADC_AWD0DR0 register */ +#define ADC_AWD0DR0 (0xFFFFU) + +/* Bit definition for ADC_AWD0DR1 register */ +#define ADC_AWD0DR1 (0xFFFFU) + +/* Bit definition for ADC_AWD0CHSR register */ +#define ADC_AWD0CHSR_AWDCH (0x1FU) + +/* Bit definition for ADC_AWD1DR0 register */ +#define ADC_AWD1DR0 (0xFFFFU) + +/* Bit definition for ADC_AWD1DR1 register */ +#define ADC_AWD1DR1 (0xFFFFU) + +/* Bit definition for ADC_AWD1CHSR register */ +#define ADC_AWD1CHSR_AWDCH (0x1FU) + +/******************************************************************************* + Bit definition for Peripheral AES +*******************************************************************************/ +/* Bit definition for AES_CR register */ +#define AES_CR_START_POS (0U) +#define AES_CR_START (0x00000001UL) +#define AES_CR_MODE_POS (1U) +#define AES_CR_MODE (0x00000002UL) +#define AES_CR_KEYSIZE_POS (3U) +#define AES_CR_KEYSIZE (0x00000018UL) + +/* Bit definition for AES_DR0 register */ +#define AES_DR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR1 register */ +#define AES_DR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR2 register */ +#define AES_DR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR3 register */ +#define AES_DR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR0 register */ +#define AES_KR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR1 register */ +#define AES_KR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR2 register */ +#define AES_KR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR3 register */ +#define AES_KR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR4 register */ +#define AES_KR4 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR5 register */ +#define AES_KR5 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR6 register */ +#define AES_KR6 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR7 register */ +#define AES_KR7 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral AOS +*******************************************************************************/ +/* Bit definition for AOS_INTSFTTRG register */ +#define AOS_INTSFTTRG_STRG (0x00000001UL) + +/* Bit definition for AOS_DCU_TRGSEL register */ +#define AOS_DCU_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_TRGSEL_PLCHSEL_POS (16U) +#define AOS_DCU_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_DCU_TRGSEL_COMEN_POS (30U) +#define AOS_DCU_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DCU_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DCU_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA1_TRGSEL register */ +#define AOS_DMA1_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA1_TRGSEL_PLCHSEL_POS (16U) +#define AOS_DMA1_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_DMA1_TRGSEL_COMEN_POS (30U) +#define AOS_DMA1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA2_TRGSEL register */ +#define AOS_DMA2_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA2_TRGSEL_PLCHSEL_POS (16U) +#define AOS_DMA2_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_DMA2_TRGSEL_COMEN_POS (30U) +#define AOS_DMA2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_RC_TRGSEL register */ +#define AOS_DMA_RC_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA_RC_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA_RC_TRGSEL_PLCHSEL_POS (16U) +#define AOS_DMA_RC_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_POS (30U) +#define AOS_DMA_RC_TRGSEL_COMEN (0xC0000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_DMA_RC_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR6_TRGSEL register */ +#define AOS_TMR6_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR6_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR6_TRGSEL_PLCHSEL_POS (16U) +#define AOS_TMR6_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_TMR6_TRGSEL_COMEN_POS (30U) +#define AOS_TMR6_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR6_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR6_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR4_TRGSEL register */ +#define AOS_TMR4_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR4_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR4_TRGSEL_PLCHSEL_POS (16U) +#define AOS_TMR4_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_TMR4_TRGSEL_COMEN_POS (30U) +#define AOS_TMR4_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR4_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR4_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_PEVNT_TRGSEL12 register */ +#define AOS_PEVNT_TRGSEL12_TRGSEL_POS (0U) +#define AOS_PEVNT_TRGSEL12_TRGSEL (0x000001FFUL) +#define AOS_PEVNT_TRGSEL12_PLCHSEL_POS (16U) +#define AOS_PEVNT_TRGSEL12_PLCHSEL (0x00070000UL) +#define AOS_PEVNT_TRGSEL12_COMEN_POS (30U) +#define AOS_PEVNT_TRGSEL12_COMEN (0xC0000000UL) +#define AOS_PEVNT_TRGSEL12_COMEN_0 (0x40000000UL) +#define AOS_PEVNT_TRGSEL12_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_PEVNT_TRGSEL34 register */ +#define AOS_PEVNT_TRGSEL34_TRGSEL_POS (0U) +#define AOS_PEVNT_TRGSEL34_TRGSEL (0x000001FFUL) +#define AOS_PEVNT_TRGSEL34_PLCHSEL_POS (16U) +#define AOS_PEVNT_TRGSEL34_PLCHSEL (0x00070000UL) +#define AOS_PEVNT_TRGSEL34_COMEN_POS (30U) +#define AOS_PEVNT_TRGSEL34_COMEN (0xC0000000UL) +#define AOS_PEVNT_TRGSEL34_COMEN_0 (0x40000000UL) +#define AOS_PEVNT_TRGSEL34_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR0_TRGSEL register */ +#define AOS_TMR0_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMR0_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMR0_TRGSEL_PLCHSEL_POS (16U) +#define AOS_TMR0_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_TMR0_TRGSEL_COMEN_POS (30U) +#define AOS_TMR0_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMR0_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMR0_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_TMRA_TRGSEL register */ +#define AOS_TMRA_TRGSEL_TRGSEL_POS (0U) +#define AOS_TMRA_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_TMRA_TRGSEL_PLCHSEL_POS (16U) +#define AOS_TMRA_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_TMRA_TRGSEL_COMEN_POS (30U) +#define AOS_TMRA_TRGSEL_COMEN (0xC0000000UL) +#define AOS_TMRA_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_TMRA_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC1_TRGSEL register */ +#define AOS_ADC1_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC1_TRGSEL_PLCHSEL_POS (16U) +#define AOS_ADC1_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_ADC1_TRGSEL_COMEN_POS (30U) +#define AOS_ADC1_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC1_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC1_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC2_TRGSEL register */ +#define AOS_ADC2_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC2_TRGSEL_PLCHSEL_POS (16U) +#define AOS_ADC2_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_ADC2_TRGSEL_COMEN_POS (30U) +#define AOS_ADC2_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC2_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC2_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC3_TRGSEL register */ +#define AOS_ADC3_TRGSEL_TRGSEL_POS (0U) +#define AOS_ADC3_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_ADC3_TRGSEL_PLCHSEL_POS (16U) +#define AOS_ADC3_TRGSEL_PLCHSEL (0x00070000UL) +#define AOS_ADC3_TRGSEL_COMEN_POS (30U) +#define AOS_ADC3_TRGSEL_COMEN (0xC0000000UL) +#define AOS_ADC3_TRGSEL_COMEN_0 (0x40000000UL) +#define AOS_ADC3_TRGSEL_COMEN_1 (0x80000000UL) + +/* Bit definition for AOS_COMTRGSEL register */ +#define AOS_COMTRGSEL_TRGSEL (0x000001FFUL) + +/* Bit definition for AOS_PEVNTDIRR register */ +#define AOS_PEVNTDIRR_PDIR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTIDR register */ +#define AOS_PEVNTIDR_PIN (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTODR register */ +#define AOS_PEVNTODR_POUT (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTORR register */ +#define AOS_PEVNTORR_POR (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTOSR register */ +#define AOS_PEVNTOSR_POS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTRISR register */ +#define AOS_PEVNTRISR_RIS (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTFALR register */ +#define AOS_PEVNTFALR_FAL (0x0000FFFFUL) + +/* Bit definition for AOS_PEVNTNFCR register */ +#define AOS_PEVNTNFCR_NFEN1_POS (0U) +#define AOS_PEVNTNFCR_NFEN1 (0x00000001UL) +#define AOS_PEVNTNFCR_DIVS1_POS (1U) +#define AOS_PEVNTNFCR_DIVS1 (0x00000006UL) +#define AOS_PEVNTNFCR_NFEN2_POS (8U) +#define AOS_PEVNTNFCR_NFEN2 (0x00000100UL) +#define AOS_PEVNTNFCR_DIVS2_POS (9U) +#define AOS_PEVNTNFCR_DIVS2 (0x00000600UL) +#define AOS_PEVNTNFCR_NFEN3_POS (16U) +#define AOS_PEVNTNFCR_NFEN3 (0x00010000UL) +#define AOS_PEVNTNFCR_DIVS3_POS (17U) +#define AOS_PEVNTNFCR_DIVS3 (0x00060000UL) +#define AOS_PEVNTNFCR_NFEN4_POS (24U) +#define AOS_PEVNTNFCR_NFEN4 (0x01000000UL) +#define AOS_PEVNTNFCR_DIVS4_POS (25U) +#define AOS_PEVNTNFCR_DIVS4 (0x06000000UL) + +/* Bit definition for AOS_PLU_CR register */ +#define AOS_PLU_CR_PLMODE_POS (0U) +#define AOS_PLU_CR_PLMODE (0x00000003UL) +#define AOS_PLU_CR_PLINASEL_POS (8U) +#define AOS_PLU_CR_PLINASEL (0x00000300UL) +#define AOS_PLU_CR_PLINBSEL_POS (10U) +#define AOS_PLU_CR_PLINBSEL (0x00000C00UL) +#define AOS_PLU_CR_PLINCSEL_POS (12U) +#define AOS_PLU_CR_PLINCSEL (0x00003000UL) +#define AOS_PLU_CR_PLINDSEL_POS (14U) +#define AOS_PLU_CR_PLINDSEL (0x0000C000UL) + +/* Bit definition for AOS_PLU_TRGSELA register */ +#define AOS_PLU_TRGSELA_PLTRGSEL (0x000001FFUL) + +/* Bit definition for AOS_PLU_TRGSELB register */ +#define AOS_PLU_TRGSELB_PLTRGSEL (0x000001FFUL) + +/* Bit definition for AOS_PLU_TRGSELC register */ +#define AOS_PLU_TRGSELC_PLTRGSEL (0x000001FFUL) + +/* Bit definition for AOS_PLU_TRGSELD register */ +#define AOS_PLU_TRGSELD_PLTRGSEL (0x000001FFUL) + +/******************************************************************************* + Bit definition for Peripheral CMP +*******************************************************************************/ +/* Bit definition for CMP_MDR register */ +#define CMP_MDR_CENA_POS (0U) +#define CMP_MDR_CENA (0x01U) +#define CMP_MDR_CWDE_POS (1U) +#define CMP_MDR_CWDE (0x02U) +#define CMP_MDR_CSMD_POS (2U) +#define CMP_MDR_CSMD (0x0CU) +#define CMP_MDR_CSMD_0 (0x04U) +#define CMP_MDR_CSMD_1 (0x08U) +#define CMP_MDR_CSST_POS (4U) +#define CMP_MDR_CSST (0x10U) +#define CMP_MDR_CMON_POS (7U) +#define CMP_MDR_CMON (0x80U) + +/* Bit definition for CMP_FIR register */ +#define CMP_FIR_FCKS_POS (0U) +#define CMP_FIR_FCKS (0x07U) +#define CMP_FIR_CIEN_POS (3U) +#define CMP_FIR_CIEN (0x08U) +#define CMP_FIR_EDGS_POS (4U) +#define CMP_FIR_EDGS (0x30U) +#define CMP_FIR_EDGS_0 (0x10U) +#define CMP_FIR_EDGS_1 (0x20U) +#define CMP_FIR_CFF_POS (6U) +#define CMP_FIR_CFF (0x40U) +#define CMP_FIR_CRF_POS (7U) +#define CMP_FIR_CRF (0x80U) + +/* Bit definition for CMP_OCR register */ +#define CMP_OCR_COEN_POS (0U) +#define CMP_OCR_COEN (0x01U) +#define CMP_OCR_COPS_POS (1U) +#define CMP_OCR_COPS (0x02U) +#define CMP_OCR_CPOE_POS (2U) +#define CMP_OCR_CPOE (0x04U) +#define CMP_OCR_BWEN_POS (4U) +#define CMP_OCR_BWEN (0x10U) +#define CMP_OCR_BWMD_POS (5U) +#define CMP_OCR_BWMD (0x20U) +#define CMP_OCR_BWOL_POS (6U) +#define CMP_OCR_BWOL (0xC0U) +#define CMP_OCR_BWOL_0 (0x40U) +#define CMP_OCR_BWOL_1 (0x80U) + +/* Bit definition for CMP_PMSR register */ +#define CMP_PMSR_RVSL_POS (0U) +#define CMP_PMSR_RVSL (0x0000000FUL) +#define CMP_PMSR_RVSL_0 (0x00000001UL) +#define CMP_PMSR_RVSL_1 (0x00000002UL) +#define CMP_PMSR_RVSL_2 (0x00000004UL) +#define CMP_PMSR_RVSL_3 (0x00000008UL) +#define CMP_PMSR_CVSL_POS (16U) +#define CMP_PMSR_CVSL (0x000F0000UL) +#define CMP_PMSR_CVSL_0 (0x00010000UL) +#define CMP_PMSR_CVSL_1 (0x00020000UL) +#define CMP_PMSR_CVSL_2 (0x00040000UL) +#define CMP_PMSR_CVSL_3 (0x00080000UL) + +/* Bit definition for CMP_BWSR1 register */ +#define CMP_BWSR1_CTWS0_POS (0U) +#define CMP_BWSR1_CTWS0 (0x00000001UL) +#define CMP_BWSR1_CTWS1_POS (1U) +#define CMP_BWSR1_CTWS1 (0x00000002UL) +#define CMP_BWSR1_CTWS2_POS (2U) +#define CMP_BWSR1_CTWS2 (0x00000004UL) +#define CMP_BWSR1_CTWS3_POS (3U) +#define CMP_BWSR1_CTWS3 (0x00000008UL) +#define CMP_BWSR1_CTWS4_POS (4U) +#define CMP_BWSR1_CTWS4 (0x00000010UL) +#define CMP_BWSR1_CTWS5_POS (5U) +#define CMP_BWSR1_CTWS5 (0x00000020UL) +#define CMP_BWSR1_CTWS6_POS (6U) +#define CMP_BWSR1_CTWS6 (0x00000040UL) +#define CMP_BWSR1_CTWS7_POS (7U) +#define CMP_BWSR1_CTWS7 (0x00000080UL) +#define CMP_BWSR1_CTWS8_POS (8U) +#define CMP_BWSR1_CTWS8 (0x00000100UL) +#define CMP_BWSR1_CTWS9_POS (9U) +#define CMP_BWSR1_CTWS9 (0x00000200UL) +#define CMP_BWSR1_CTWS10_POS (10U) +#define CMP_BWSR1_CTWS10 (0x00000400UL) +#define CMP_BWSR1_CTWS11_POS (11U) +#define CMP_BWSR1_CTWS11 (0x00000800UL) +#define CMP_BWSR1_CTWS12_POS (12U) +#define CMP_BWSR1_CTWS12 (0x00001000UL) +#define CMP_BWSR1_CTWS13_POS (13U) +#define CMP_BWSR1_CTWS13 (0x00002000UL) +#define CMP_BWSR1_CTWS14_POS (14U) +#define CMP_BWSR1_CTWS14 (0x00004000UL) +#define CMP_BWSR1_CTWS15_POS (15U) +#define CMP_BWSR1_CTWS15 (0x00008000UL) +#define CMP_BWSR1_CTWP0_POS (16U) +#define CMP_BWSR1_CTWP0 (0x00010000UL) +#define CMP_BWSR1_CTWP1_POS (17U) +#define CMP_BWSR1_CTWP1 (0x00020000UL) +#define CMP_BWSR1_CTWP2_POS (18U) +#define CMP_BWSR1_CTWP2 (0x00040000UL) +#define CMP_BWSR1_CTWP3_POS (19U) +#define CMP_BWSR1_CTWP3 (0x00080000UL) +#define CMP_BWSR1_CTWP4_POS (20U) +#define CMP_BWSR1_CTWP4 (0x00100000UL) +#define CMP_BWSR1_CTWP5_POS (21U) +#define CMP_BWSR1_CTWP5 (0x00200000UL) +#define CMP_BWSR1_CTWP6_POS (22U) +#define CMP_BWSR1_CTWP6 (0x00400000UL) +#define CMP_BWSR1_CTWP7_POS (23U) +#define CMP_BWSR1_CTWP7 (0x00800000UL) +#define CMP_BWSR1_CTWP8_POS (24U) +#define CMP_BWSR1_CTWP8 (0x01000000UL) +#define CMP_BWSR1_CTWP9_POS (25U) +#define CMP_BWSR1_CTWP9 (0x02000000UL) +#define CMP_BWSR1_CTWP10_POS (26U) +#define CMP_BWSR1_CTWP10 (0x04000000UL) +#define CMP_BWSR1_CTWP11_POS (27U) +#define CMP_BWSR1_CTWP11 (0x08000000UL) +#define CMP_BWSR1_CTWP12_POS (28U) +#define CMP_BWSR1_CTWP12 (0x10000000UL) +#define CMP_BWSR1_CTWP13_POS (29U) +#define CMP_BWSR1_CTWP13 (0x20000000UL) +#define CMP_BWSR1_CTWP14_POS (30U) +#define CMP_BWSR1_CTWP14 (0x40000000UL) +#define CMP_BWSR1_CTWP15_POS (31U) +#define CMP_BWSR1_CTWP15 (0x80000000UL) + +/* Bit definition for CMP_BWSR2 register */ +#define CMP_BWSR2_MSKW_POS (0U) +#define CMP_BWSR2_MSKW (0x00FFU) +#define CMP_BWSR2_TWEG_POS (8U) +#define CMP_BWSR2_TWEG (0x0300U) +#define CMP_BWSR2_TWEG_0 (0x0100U) +#define CMP_BWSR2_TWEG_1 (0x0200U) + +/* Bit definition for CMP_SCCR register */ +#define CMP_SCCR_SISL_POS (0U) +#define CMP_SCCR_SISL (0x0000000FUL) +#define CMP_SCCR_SPRD_POS (16U) +#define CMP_SCCR_SPRD (0x00FF0000UL) +#define CMP_SCCR_SSTB_POS (24U) +#define CMP_SCCR_SSTB (0x3F000000UL) + +/* Bit definition for CMP_SCMR register */ +#define CMP_SCMR_RVST_POS (0U) +#define CMP_SCMR_RVST (0x0000000FUL) +#define CMP_SCMR_CVST_POS (16U) +#define CMP_SCMR_CVST (0x000F0000UL) + +/******************************************************************************* + Bit definition for Peripheral CMU +*******************************************************************************/ +/* Bit definition for CMU_XTALDIVR register */ +#define CMU_XTALDIVR_DEMON_POS (0U) +#define CMU_XTALDIVR_DEMON (0x000007FFUL) +#define CMU_XTALDIVR_NUMER_POS (12U) +#define CMU_XTALDIVR_NUMER (0x1FFFF000UL) + +/* Bit definition for CMU_XTALDIVCR register */ +#define CMU_XTALDIVCR_FRADIVEN (0x00000001UL) + +/* Bit definition for CMU_XTALCFGR register */ +#define CMU_XTALCFGR_XTALDRV_POS (4U) +#define CMU_XTALCFGR_XTALDRV (0x30U) +#define CMU_XTALCFGR_XTALDRV_0 (0x10U) +#define CMU_XTALCFGR_XTALDRV_1 (0x20U) +#define CMU_XTALCFGR_XTALMS_POS (6U) +#define CMU_XTALCFGR_XTALMS (0x40U) + +/* Bit definition for CMU_XTAL32CR register */ +#define CMU_XTAL32CR_XTAL32STP (0x01U) + +/* Bit definition for CMU_XTAL32CFGR register */ +#define CMU_XTAL32CFGR_XTAL32DRV (0x07U) + +/* Bit definition for CMU_XTAL32NFR register */ +#define CMU_XTAL32NFR_XTAL32NF (0x03U) +#define CMU_XTAL32NFR_XTAL32NF_0 (0x01U) +#define CMU_XTAL32NFR_XTAL32NF_1 (0x02U) + +/* Bit definition for CMU_LRCCR register */ +#define CMU_LRCCR_LRCSTP (0x01U) + +/* Bit definition for CMU_LRCTRM register */ +#define CMU_LRCTRM (0xFFU) + +/* Bit definition for CMU_PERICKSEL register */ +#define CMU_PERICKSEL_PERICKSEL (0x000FU) + +/* Bit definition for CMU_CANCKCFGR register */ +#define CMU_CANCKCFGR_MCAN1CKS_POS (0U) +#define CMU_CANCKCFGR_MCAN1CKS (0x000FU) +#define CMU_CANCKCFGR_MCAN2CKS_POS (4U) +#define CMU_CANCKCFGR_MCAN2CKS (0x00F0U) + +/* Bit definition for CMU_SCFGR register */ +#define CMU_SCFGR_PCLK0S_POS (0U) +#define CMU_SCFGR_PCLK0S (0x00000007UL) +#define CMU_SCFGR_PCLK1S_POS (4U) +#define CMU_SCFGR_PCLK1S (0x00000070UL) +#define CMU_SCFGR_PCLK2S_POS (8U) +#define CMU_SCFGR_PCLK2S (0x00000700UL) +#define CMU_SCFGR_PCLK3S_POS (12U) +#define CMU_SCFGR_PCLK3S (0x00007000UL) +#define CMU_SCFGR_PCLK4S_POS (16U) +#define CMU_SCFGR_PCLK4S (0x00070000UL) +#define CMU_SCFGR_EXCKS_POS (20U) +#define CMU_SCFGR_EXCKS (0x00700000UL) +#define CMU_SCFGR_HCLKS_POS (24U) +#define CMU_SCFGR_HCLKS (0x07000000UL) + +/* Bit definition for CMU_CKSWR register */ +#define CMU_CKSWR_CKSW (0x07U) + +/* Bit definition for CMU_PLLHCR register */ +#define CMU_PLLHCR_PLLHOFF (0x01U) + +/* Bit definition for CMU_XTALCR register */ +#define CMU_XTALCR_XTALSTP (0x01U) + +/* Bit definition for CMU_HRCCR register */ +#define CMU_HRCCR_HRCSTP (0x01U) + +/* Bit definition for CMU_MRCCR register */ +#define CMU_MRCCR_MRCSTP (0x01U) + +/* Bit definition for CMU_OSCSTBSR register */ +#define CMU_OSCSTBSR_HRCSTBF_POS (0U) +#define CMU_OSCSTBSR_HRCSTBF (0x01U) +#define CMU_OSCSTBSR_XTALSTBF_POS (3U) +#define CMU_OSCSTBSR_XTALSTBF (0x08U) +#define CMU_OSCSTBSR_PLLHSTBF_POS (5U) +#define CMU_OSCSTBSR_PLLHSTBF (0x20U) + +/* Bit definition for CMU_MCOCFGR register */ +#define CMU_MCOCFGR_MCOSEL_POS (0U) +#define CMU_MCOCFGR_MCOSEL (0x0FU) +#define CMU_MCOCFGR_MCODIV_POS (4U) +#define CMU_MCOCFGR_MCODIV (0x70U) +#define CMU_MCOCFGR_MCOEN_POS (7U) +#define CMU_MCOCFGR_MCOEN (0x80U) + +/* Bit definition for CMU_TPIUCKCFGR register */ +#define CMU_TPIUCKCFGR_TPIUCKS_POS (0U) +#define CMU_TPIUCKCFGR_TPIUCKS (0x03U) +#define CMU_TPIUCKCFGR_TPIUCKS_0 (0x01U) +#define CMU_TPIUCKCFGR_TPIUCKS_1 (0x02U) +#define CMU_TPIUCKCFGR_TPIUCKOE_POS (7U) +#define CMU_TPIUCKCFGR_TPIUCKOE (0x80U) + +/* Bit definition for CMU_XTALSTDCR register */ +#define CMU_XTALSTDCR_XTALSTDIE_POS (0U) +#define CMU_XTALSTDCR_XTALSTDIE (0x01U) +#define CMU_XTALSTDCR_XTALSTDRE_POS (1U) +#define CMU_XTALSTDCR_XTALSTDRE (0x02U) +#define CMU_XTALSTDCR_XTALSTDRIS_POS (2U) +#define CMU_XTALSTDCR_XTALSTDRIS (0x04U) +#define CMU_XTALSTDCR_XTALSTDE_POS (7U) +#define CMU_XTALSTDCR_XTALSTDE (0x80U) + +/* Bit definition for CMU_XTALSTDSR register */ +#define CMU_XTALSTDSR_XTALSTDF (0x01U) + +/* Bit definition for CMU_MRCTRM register */ +#define CMU_MRCTRM (0xFFU) + +/* Bit definition for CMU_HRCTRM register */ +#define CMU_HRCTRM (0xFFU) + +/* Bit definition for CMU_XTALSTBCR register */ +#define CMU_XTALSTBCR_XTALSTB (0x0FU) + +/* Bit definition for CMU_PLLHCFGR register */ +#define CMU_PLLHCFGR_PLLHM_POS (0U) +#define CMU_PLLHCFGR_PLLHM (0x00000003UL) +#define CMU_PLLHCFGR_PLLHM_0 (0x00000001UL) +#define CMU_PLLHCFGR_PLLHM_1 (0x00000002UL) +#define CMU_PLLHCFGR_PLLSRC_POS (7U) +#define CMU_PLLHCFGR_PLLSRC (0x00000080UL) +#define CMU_PLLHCFGR_PLLHN_POS (8U) +#define CMU_PLLHCFGR_PLLHN (0x0000FF00UL) +#define CMU_PLLHCFGR_PLLHR_POS (20U) +#define CMU_PLLHCFGR_PLLHR (0x00F00000UL) +#define CMU_PLLHCFGR_PLLHQ_POS (24U) +#define CMU_PLLHCFGR_PLLHQ (0x0F000000UL) +#define CMU_PLLHCFGR_PLLHP_POS (28U) +#define CMU_PLLHCFGR_PLLHP (0xF0000000UL) + +/******************************************************************************* + Bit definition for Peripheral CRC +*******************************************************************************/ +/* Bit definition for CRC_CR register */ +#define CRC_CR_CR_POS (0U) +#define CRC_CR_CR (0x00000001UL) +#define CRC_CR_FLAG_POS (1U) +#define CRC_CR_FLAG (0x00000002UL) + +/* Bit definition for CRC_RESLT register */ +#define CRC_RESLT (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT0 register */ +#define CRC_DAT0 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT1 register */ +#define CRC_DAT1 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT2 register */ +#define CRC_DAT2 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT3 register */ +#define CRC_DAT3 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT4 register */ +#define CRC_DAT4 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT5 register */ +#define CRC_DAT5 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT6 register */ +#define CRC_DAT6 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT7 register */ +#define CRC_DAT7 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT8 register */ +#define CRC_DAT8 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT9 register */ +#define CRC_DAT9 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT10 register */ +#define CRC_DAT10 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT11 register */ +#define CRC_DAT11 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT12 register */ +#define CRC_DAT12 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT13 register */ +#define CRC_DAT13 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT14 register */ +#define CRC_DAT14 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT15 register */ +#define CRC_DAT15 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT16 register */ +#define CRC_DAT16 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT17 register */ +#define CRC_DAT17 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT18 register */ +#define CRC_DAT18 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT19 register */ +#define CRC_DAT19 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT20 register */ +#define CRC_DAT20 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT21 register */ +#define CRC_DAT21 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT22 register */ +#define CRC_DAT22 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT23 register */ +#define CRC_DAT23 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT24 register */ +#define CRC_DAT24 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT25 register */ +#define CRC_DAT25 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT26 register */ +#define CRC_DAT26 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT27 register */ +#define CRC_DAT27 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT28 register */ +#define CRC_DAT28 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT29 register */ +#define CRC_DAT29 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT30 register */ +#define CRC_DAT30 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT31 register */ +#define CRC_DAT31 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral CTC +*******************************************************************************/ +/* Bit definition for CTC_CR1 register */ +#define CTC_CR1_REFPSC_POS (0U) +#define CTC_CR1_REFPSC (0x00000007UL) +#define CTC_CR1_REFCKS_POS (4U) +#define CTC_CR1_REFCKS (0x00000030UL) +#define CTC_CR1_REFCKS_0 (0x00000010UL) +#define CTC_CR1_REFCKS_1 (0x00000020UL) +#define CTC_CR1_ERRIE_POS (6U) +#define CTC_CR1_ERRIE (0x00000040UL) +#define CTC_CR1_CTCEN_POS (7U) +#define CTC_CR1_CTCEN (0x00000080UL) +#define CTC_CR1_HRCPSC_POS (8U) +#define CTC_CR1_HRCPSC (0x00000700UL) +#define CTC_CR1_REFEDG_POS (12U) +#define CTC_CR1_REFEDG (0x00003000UL) +#define CTC_CR1_REFEDG_0 (0x00001000UL) +#define CTC_CR1_REFEDG_1 (0x00002000UL) +#define CTC_CR1_TRMVAL_POS (16U) +#define CTC_CR1_TRMVAL (0x003F0000UL) + +/* Bit definition for CTC_CR2 register */ +#define CTC_CR2_OFSVAL_POS (0U) +#define CTC_CR2_OFSVAL (0x000000FFUL) +#define CTC_CR2_RLDVAL_POS (16U) +#define CTC_CR2_RLDVAL (0xFFFF0000UL) + +/* Bit definition for CTC_STR register */ +#define CTC_STR_TRIMOK_POS (0U) +#define CTC_STR_TRIMOK (0x00000001UL) +#define CTC_STR_TRMOVF_POS (1U) +#define CTC_STR_TRMOVF (0x00000002UL) +#define CTC_STR_TRMUDF_POS (2U) +#define CTC_STR_TRMUDF (0x00000004UL) +#define CTC_STR_CTCBSY_POS (3U) +#define CTC_STR_CTCBSY (0x00000008UL) + +/* Bit definition for CTC_CNT register */ +#define CTC_CNT (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral DAC +*******************************************************************************/ +/* Bit definition for DAC_DADR1 register */ +#define DAC_DADR1_DR0_POS (0U) +#define DAC_DADR1_DR0 (0x0001U) +#define DAC_DADR1_DR1_POS (1U) +#define DAC_DADR1_DR1 (0x0002U) +#define DAC_DADR1_DR2_POS (2U) +#define DAC_DADR1_DR2 (0x0004U) +#define DAC_DADR1_DR3_POS (3U) +#define DAC_DADR1_DR3 (0x0008U) +#define DAC_DADR1_DL0R4_POS (4U) +#define DAC_DADR1_DL0R4 (0x0010U) +#define DAC_DADR1_DL1R5_POS (5U) +#define DAC_DADR1_DL1R5 (0x0020U) +#define DAC_DADR1_DL2R6_POS (6U) +#define DAC_DADR1_DL2R6 (0x0040U) +#define DAC_DADR1_DL3R7_POS (7U) +#define DAC_DADR1_DL3R7 (0x0080U) +#define DAC_DADR1_DL4R8_POS (8U) +#define DAC_DADR1_DL4R8 (0x0100U) +#define DAC_DADR1_DL5R9_POS (9U) +#define DAC_DADR1_DL5R9 (0x0200U) +#define DAC_DADR1_DL6R10_POS (10U) +#define DAC_DADR1_DL6R10 (0x0400U) +#define DAC_DADR1_DL7R11_POS (11U) +#define DAC_DADR1_DL7R11 (0x0800U) +#define DAC_DADR1_DL8_POS (12U) +#define DAC_DADR1_DL8 (0x1000U) +#define DAC_DADR1_DL9_POS (13U) +#define DAC_DADR1_DL9 (0x2000U) +#define DAC_DADR1_DL10_POS (14U) +#define DAC_DADR1_DL10 (0x4000U) +#define DAC_DADR1_DL11_POS (15U) +#define DAC_DADR1_DL11 (0x8000U) + +/* Bit definition for DAC_DADR2 register */ +#define DAC_DADR2_DR0_POS (0U) +#define DAC_DADR2_DR0 (0x0001U) +#define DAC_DADR2_DR1_POS (1U) +#define DAC_DADR2_DR1 (0x0002U) +#define DAC_DADR2_DR2_POS (2U) +#define DAC_DADR2_DR2 (0x0004U) +#define DAC_DADR2_DR3_POS (3U) +#define DAC_DADR2_DR3 (0x0008U) +#define DAC_DADR2_DL0R4_POS (4U) +#define DAC_DADR2_DL0R4 (0x0010U) +#define DAC_DADR2_DL1R5_POS (5U) +#define DAC_DADR2_DL1R5 (0x0020U) +#define DAC_DADR2_DL2R6_POS (6U) +#define DAC_DADR2_DL2R6 (0x0040U) +#define DAC_DADR2_DL3R7_POS (7U) +#define DAC_DADR2_DL3R7 (0x0080U) +#define DAC_DADR2_DL4R8_POS (8U) +#define DAC_DADR2_DL4R8 (0x0100U) +#define DAC_DADR2_DL5R9_POS (9U) +#define DAC_DADR2_DL5R9 (0x0200U) +#define DAC_DADR2_DL6R10_POS (10U) +#define DAC_DADR2_DL6R10 (0x0400U) +#define DAC_DADR2_DL7R11_POS (11U) +#define DAC_DADR2_DL7R11 (0x0800U) +#define DAC_DADR2_DL8_POS (12U) +#define DAC_DADR2_DL8 (0x1000U) +#define DAC_DADR2_DL9_POS (13U) +#define DAC_DADR2_DL9 (0x2000U) +#define DAC_DADR2_DL10_POS (14U) +#define DAC_DADR2_DL10 (0x4000U) +#define DAC_DADR2_DL11_POS (15U) +#define DAC_DADR2_DL11 (0x8000U) + +/* Bit definition for DAC_DACR register */ +#define DAC_DACR_DAE_POS (0U) +#define DAC_DACR_DAE (0x0001U) +#define DAC_DACR_DA1E_POS (1U) +#define DAC_DACR_DA1E (0x0002U) +#define DAC_DACR_DA2E_POS (2U) +#define DAC_DACR_DA2E (0x0004U) +#define DAC_DACR_DPSEL_POS (8U) +#define DAC_DACR_DPSEL (0x0100U) +#define DAC_DACR_DAAMP1_POS (9U) +#define DAC_DACR_DAAMP1 (0x0200U) +#define DAC_DACR_DAAMP2_POS (10U) +#define DAC_DACR_DAAMP2 (0x0400U) +#define DAC_DACR_EXTDSL1_POS (11U) +#define DAC_DACR_EXTDSL1 (0x0800U) +#define DAC_DACR_EXTDSL2_POS (12U) +#define DAC_DACR_EXTDSL2 (0x1000U) + +/* Bit definition for DAC_DAADPCR register */ +#define DAC_DAADPCR_ADCSL1_POS (0U) +#define DAC_DAADPCR_ADCSL1 (0x0001U) +#define DAC_DAADPCR_ADCSL2_POS (1U) +#define DAC_DAADPCR_ADCSL2 (0x0002U) +#define DAC_DAADPCR_ADCSL3_POS (2U) +#define DAC_DAADPCR_ADCSL3 (0x0004U) +#define DAC_DAADPCR_DA1SF_POS (8U) +#define DAC_DAADPCR_DA1SF (0x0100U) +#define DAC_DAADPCR_DA2SF_POS (9U) +#define DAC_DAADPCR_DA2SF (0x0200U) +#define DAC_DAADPCR_ADPEN_POS (15U) +#define DAC_DAADPCR_ADPEN (0x8000U) + +/* Bit definition for DAC_DAOCR register */ +#define DAC_DAOCR_DAODIS1_POS (14U) +#define DAC_DAOCR_DAODIS1 (0x4000U) +#define DAC_DAOCR_DAODIS2_POS (15U) +#define DAC_DAOCR_DAODIS2 (0x8000U) + +/******************************************************************************* + Bit definition for Peripheral DBGC +*******************************************************************************/ +/* Bit definition for DBGC_AUTHID0 register */ +#define DBGC_AUTHID0 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID1 register */ +#define DBGC_AUTHID1 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID2 register */ +#define DBGC_AUTHID2 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_CHIPID register */ +#define DBGC_CHIPID (0xFFFFFFFFUL) + +/* Bit definition for DBGC_MCUSTAT register */ +#define DBGC_MCUSTAT_AUTHFG_POS (0U) +#define DBGC_MCUSTAT_AUTHFG (0x00000001UL) +#define DBGC_MCUSTAT_PRTLV1_POS (2U) +#define DBGC_MCUSTAT_PRTLV1 (0x00000004UL) +#define DBGC_MCUSTAT_PRTLV2_POS (3U) +#define DBGC_MCUSTAT_PRTLV2 (0x00000008UL) +#define DBGC_MCUSTAT_PRTLV3_POS (4U) +#define DBGC_MCUSTAT_PRTLV3 (0x00000010UL) + +/* Bit definition for DBGC_FERSCTL register */ +#define DBGC_FERSCTL_ERASEREQ_POS (0U) +#define DBGC_FERSCTL_ERASEREQ (0x00000001UL) +#define DBGC_FERSCTL_ERASEACK_POS (1U) +#define DBGC_FERSCTL_ERASEACK (0x00000002UL) +#define DBGC_FERSCTL_ERASEERR_POS (2U) +#define DBGC_FERSCTL_ERASEERR (0x00000004UL) + +/* Bit definition for DBGC_MCUDBGCSTAT register */ +#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ_POS (0U) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ (0x00000001UL) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK_POS (1U) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK (0x00000002UL) + +/* Bit definition for DBGC_MCUSTPCTL register */ +#define DBGC_MCUSTPCTL_SWDTSTP_POS (0U) +#define DBGC_MCUSTPCTL_SWDTSTP (0x00000001UL) +#define DBGC_MCUSTPCTL_WDTSTP_POS (1U) +#define DBGC_MCUSTPCTL_WDTSTP (0x00000002UL) +#define DBGC_MCUSTPCTL_RTCSTP_POS (2U) +#define DBGC_MCUSTPCTL_RTCSTP (0x00000004UL) +#define DBGC_MCUSTPCTL_M06STP_POS (6U) +#define DBGC_MCUSTPCTL_M06STP (0x00000040UL) +#define DBGC_MCUSTPCTL_M07STP_POS (7U) +#define DBGC_MCUSTPCTL_M07STP (0x00000080UL) +#define DBGC_MCUSTPCTL_M12STP_POS (12U) +#define DBGC_MCUSTPCTL_M12STP (0x00001000UL) +#define DBGC_MCUSTPCTL_M13STP_POS (13U) +#define DBGC_MCUSTPCTL_M13STP (0x00002000UL) +#define DBGC_MCUSTPCTL_M14STP_POS (14U) +#define DBGC_MCUSTPCTL_M14STP (0x00004000UL) +#define DBGC_MCUSTPCTL_M15STP_POS (15U) +#define DBGC_MCUSTPCTL_M15STP (0x00008000UL) +#define DBGC_MCUSTPCTL_M16STP_POS (16U) +#define DBGC_MCUSTPCTL_M16STP (0x00010000UL) + +/* Bit definition for DBGC_MCUTRACECTL register */ +#define DBGC_MCUTRACECTL_TRACEMODE_POS (0U) +#define DBGC_MCUTRACECTL_TRACEMODE (0x00000003UL) +#define DBGC_MCUTRACECTL_TRACEMODE_0 (0x00000001UL) +#define DBGC_MCUTRACECTL_TRACEMODE_1 (0x00000002UL) +#define DBGC_MCUTRACECTL_TRACEIOEN_POS (2U) +#define DBGC_MCUTRACECTL_TRACEIOEN (0x00000004UL) + +/* Bit definition for DBGC_MCUSTPCTL2 register */ +#define DBGC_MCUSTPCTL2_M32STP_POS (0U) +#define DBGC_MCUSTPCTL2_M32STP (0x00000001UL) +#define DBGC_MCUSTPCTL2_M33STP_POS (1U) +#define DBGC_MCUSTPCTL2_M33STP (0x00000002UL) +#define DBGC_MCUSTPCTL2_M34STP_POS (2U) +#define DBGC_MCUSTPCTL2_M34STP (0x00000004UL) +#define DBGC_MCUSTPCTL2_M35STP_POS (3U) +#define DBGC_MCUSTPCTL2_M35STP (0x00000008UL) +#define DBGC_MCUSTPCTL2_M36STP_POS (4U) +#define DBGC_MCUSTPCTL2_M36STP (0x00000010UL) + +/******************************************************************************* + Bit definition for Peripheral DCU +*******************************************************************************/ +/* Bit definition for DCU_CTL register */ +#define DCU_CTL_MODE_POS (0U) +#define DCU_CTL_MODE (0x0000000FUL) +#define DCU_CTL_DATASIZE_POS (4U) +#define DCU_CTL_DATASIZE (0x00000030UL) +#define DCU_CTL_DATASIZE_0 (0x00000010UL) +#define DCU_CTL_DATASIZE_1 (0x00000020UL) +#define DCU_CTL_COMPTRG_POS (8U) +#define DCU_CTL_COMPTRG (0x00000100UL) +#define DCU_CTL_INTEN_POS (31U) +#define DCU_CTL_INTEN (0x80000000UL) + +/* Bit definition for DCU_FLAG register */ +#define DCU_FLAG_FLAG_OP_POS (0U) +#define DCU_FLAG_FLAG_OP (0x00000001UL) +#define DCU_FLAG_FLAG_LS2_POS (1U) +#define DCU_FLAG_FLAG_LS2 (0x00000002UL) +#define DCU_FLAG_FLAG_EQ2_POS (2U) +#define DCU_FLAG_FLAG_EQ2 (0x00000004UL) +#define DCU_FLAG_FLAG_GT2_POS (3U) +#define DCU_FLAG_FLAG_GT2 (0x00000008UL) +#define DCU_FLAG_FLAG_LS1_POS (4U) +#define DCU_FLAG_FLAG_LS1 (0x00000010UL) +#define DCU_FLAG_FLAG_EQ1_POS (5U) +#define DCU_FLAG_FLAG_EQ1 (0x00000020UL) +#define DCU_FLAG_FLAG_GT1_POS (6U) +#define DCU_FLAG_FLAG_GT1 (0x00000040UL) +#define DCU_FLAG_FLAG_RLD_POS (9U) +#define DCU_FLAG_FLAG_RLD (0x00000200UL) +#define DCU_FLAG_FLAG_BTM_POS (10U) +#define DCU_FLAG_FLAG_BTM (0x00000400UL) +#define DCU_FLAG_FLAG_TOP_POS (11U) +#define DCU_FLAG_FLAG_TOP (0x00000800UL) + +/* Bit definition for DCU_DATA0 register */ +#define DCU_DATA0 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA1 register */ +#define DCU_DATA1 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA2 register */ +#define DCU_DATA2 (0xFFFFFFFFUL) + +/* Bit definition for DCU_FLAGCLR register */ +#define DCU_FLAGCLR_CLR_OP_POS (0U) +#define DCU_FLAGCLR_CLR_OP (0x00000001UL) +#define DCU_FLAGCLR_CLR_LS2_POS (1U) +#define DCU_FLAGCLR_CLR_LS2 (0x00000002UL) +#define DCU_FLAGCLR_CLR_EQ2_POS (2U) +#define DCU_FLAGCLR_CLR_EQ2 (0x00000004UL) +#define DCU_FLAGCLR_CLR_GT2_POS (3U) +#define DCU_FLAGCLR_CLR_GT2 (0x00000008UL) +#define DCU_FLAGCLR_CLR_LS1_POS (4U) +#define DCU_FLAGCLR_CLR_LS1 (0x00000010UL) +#define DCU_FLAGCLR_CLR_EQ1_POS (5U) +#define DCU_FLAGCLR_CLR_EQ1 (0x00000020UL) +#define DCU_FLAGCLR_CLR_GT1_POS (6U) +#define DCU_FLAGCLR_CLR_GT1 (0x00000040UL) +#define DCU_FLAGCLR_CLR_RLD_POS (9U) +#define DCU_FLAGCLR_CLR_RLD (0x00000200UL) +#define DCU_FLAGCLR_CLR_BTM_POS (10U) +#define DCU_FLAGCLR_CLR_BTM (0x00000400UL) +#define DCU_FLAGCLR_CLR_TOP_POS (11U) +#define DCU_FLAGCLR_CLR_TOP (0x00000800UL) + +/* Bit definition for DCU_INTEVTSEL register */ +#define DCU_INTEVTSEL_SEL_OP_POS (0U) +#define DCU_INTEVTSEL_SEL_OP (0x00000001UL) +#define DCU_INTEVTSEL_SEL_LS2_POS (1U) +#define DCU_INTEVTSEL_SEL_LS2 (0x00000002UL) +#define DCU_INTEVTSEL_SEL_EQ2_POS (2U) +#define DCU_INTEVTSEL_SEL_EQ2 (0x00000004UL) +#define DCU_INTEVTSEL_SEL_GT2_POS (3U) +#define DCU_INTEVTSEL_SEL_GT2 (0x00000008UL) +#define DCU_INTEVTSEL_SEL_LS1_POS (4U) +#define DCU_INTEVTSEL_SEL_LS1 (0x00000010UL) +#define DCU_INTEVTSEL_SEL_EQ1_POS (5U) +#define DCU_INTEVTSEL_SEL_EQ1 (0x00000020UL) +#define DCU_INTEVTSEL_SEL_GT1_POS (6U) +#define DCU_INTEVTSEL_SEL_GT1 (0x00000040UL) +#define DCU_INTEVTSEL_SEL_WIN_POS (7U) +#define DCU_INTEVTSEL_SEL_WIN (0x00000180UL) +#define DCU_INTEVTSEL_SEL_WIN_0 (0x00000080UL) +#define DCU_INTEVTSEL_SEL_WIN_1 (0x00000100UL) +#define DCU_INTEVTSEL_SEL_BTM_POS (10U) +#define DCU_INTEVTSEL_SEL_BTM (0x00000400UL) +#define DCU_INTEVTSEL_SEL_TOP_POS (11U) +#define DCU_INTEVTSEL_SEL_TOP (0x00000800UL) + +/******************************************************************************* + Bit definition for Peripheral DMA +*******************************************************************************/ +/* Bit definition for DMA_EN register */ +#define DMA_EN_EN (0x00000001UL) + +/* Bit definition for DMA_INTSTAT0 register */ +#define DMA_INTSTAT0_TRNERR_POS (0U) +#define DMA_INTSTAT0_TRNERR (0x0000003FUL) +#define DMA_INTSTAT0_TRNERR_0 (0x00000001UL) +#define DMA_INTSTAT0_TRNERR_1 (0x00000002UL) +#define DMA_INTSTAT0_TRNERR_2 (0x00000004UL) +#define DMA_INTSTAT0_TRNERR_3 (0x00000008UL) +#define DMA_INTSTAT0_TRNERR_4 (0x00000010UL) +#define DMA_INTSTAT0_TRNERR_5 (0x00000020UL) +#define DMA_INTSTAT0_REQERR_POS (16U) +#define DMA_INTSTAT0_REQERR (0x003F0000UL) +#define DMA_INTSTAT0_REQERR_0 (0x00010000UL) +#define DMA_INTSTAT0_REQERR_1 (0x00020000UL) +#define DMA_INTSTAT0_REQERR_2 (0x00040000UL) +#define DMA_INTSTAT0_REQERR_3 (0x00080000UL) +#define DMA_INTSTAT0_REQERR_4 (0x00100000UL) +#define DMA_INTSTAT0_REQERR_5 (0x00200000UL) + +/* Bit definition for DMA_INTSTAT1 register */ +#define DMA_INTSTAT1_TC_POS (0U) +#define DMA_INTSTAT1_TC (0x0000003FUL) +#define DMA_INTSTAT1_TC_0 (0x00000001UL) +#define DMA_INTSTAT1_TC_1 (0x00000002UL) +#define DMA_INTSTAT1_TC_2 (0x00000004UL) +#define DMA_INTSTAT1_TC_3 (0x00000008UL) +#define DMA_INTSTAT1_TC_4 (0x00000010UL) +#define DMA_INTSTAT1_TC_5 (0x00000020UL) +#define DMA_INTSTAT1_BTC_POS (16U) +#define DMA_INTSTAT1_BTC (0x003F0000UL) +#define DMA_INTSTAT1_BTC_0 (0x00010000UL) +#define DMA_INTSTAT1_BTC_1 (0x00020000UL) +#define DMA_INTSTAT1_BTC_2 (0x00040000UL) +#define DMA_INTSTAT1_BTC_3 (0x00080000UL) +#define DMA_INTSTAT1_BTC_4 (0x00100000UL) +#define DMA_INTSTAT1_BTC_5 (0x00200000UL) + +/* Bit definition for DMA_INTMASK0 register */ +#define DMA_INTMASK0_MSKTRNERR_POS (0U) +#define DMA_INTMASK0_MSKTRNERR (0x0000003FUL) +#define DMA_INTMASK0_MSKTRNERR_0 (0x00000001UL) +#define DMA_INTMASK0_MSKTRNERR_1 (0x00000002UL) +#define DMA_INTMASK0_MSKTRNERR_2 (0x00000004UL) +#define DMA_INTMASK0_MSKTRNERR_3 (0x00000008UL) +#define DMA_INTMASK0_MSKTRNERR_4 (0x00000010UL) +#define DMA_INTMASK0_MSKTRNERR_5 (0x00000020UL) +#define DMA_INTMASK0_MSKREQERR_POS (16U) +#define DMA_INTMASK0_MSKREQERR (0x003F0000UL) +#define DMA_INTMASK0_MSKREQERR_0 (0x00010000UL) +#define DMA_INTMASK0_MSKREQERR_1 (0x00020000UL) +#define DMA_INTMASK0_MSKREQERR_2 (0x00040000UL) +#define DMA_INTMASK0_MSKREQERR_3 (0x00080000UL) +#define DMA_INTMASK0_MSKREQERR_4 (0x00100000UL) +#define DMA_INTMASK0_MSKREQERR_5 (0x00200000UL) + +/* Bit definition for DMA_INTMASK1 register */ +#define DMA_INTMASK1_MSKTC_POS (0U) +#define DMA_INTMASK1_MSKTC (0x0000003FUL) +#define DMA_INTMASK1_MSKTC_0 (0x00000001UL) +#define DMA_INTMASK1_MSKTC_1 (0x00000002UL) +#define DMA_INTMASK1_MSKTC_2 (0x00000004UL) +#define DMA_INTMASK1_MSKTC_3 (0x00000008UL) +#define DMA_INTMASK1_MSKTC_4 (0x00000010UL) +#define DMA_INTMASK1_MSKTC_5 (0x00000020UL) +#define DMA_INTMASK1_MSKBTC_POS (16U) +#define DMA_INTMASK1_MSKBTC (0x003F0000UL) +#define DMA_INTMASK1_MSKBTC_0 (0x00010000UL) +#define DMA_INTMASK1_MSKBTC_1 (0x00020000UL) +#define DMA_INTMASK1_MSKBTC_2 (0x00040000UL) +#define DMA_INTMASK1_MSKBTC_3 (0x00080000UL) +#define DMA_INTMASK1_MSKBTC_4 (0x00100000UL) +#define DMA_INTMASK1_MSKBTC_5 (0x00200000UL) + +/* Bit definition for DMA_INTCLR0 register */ +#define DMA_INTCLR0_CLRTRNERR_POS (0U) +#define DMA_INTCLR0_CLRTRNERR (0x0000003FUL) +#define DMA_INTCLR0_CLRTRNERR_0 (0x00000001UL) +#define DMA_INTCLR0_CLRTRNERR_1 (0x00000002UL) +#define DMA_INTCLR0_CLRTRNERR_2 (0x00000004UL) +#define DMA_INTCLR0_CLRTRNERR_3 (0x00000008UL) +#define DMA_INTCLR0_CLRTRNERR_4 (0x00000010UL) +#define DMA_INTCLR0_CLRTRNERR_5 (0x00000020UL) +#define DMA_INTCLR0_CLRREQERR_POS (16U) +#define DMA_INTCLR0_CLRREQERR (0x003F0000UL) +#define DMA_INTCLR0_CLRREQERR_0 (0x00010000UL) +#define DMA_INTCLR0_CLRREQERR_1 (0x00020000UL) +#define DMA_INTCLR0_CLRREQERR_2 (0x00040000UL) +#define DMA_INTCLR0_CLRREQERR_3 (0x00080000UL) +#define DMA_INTCLR0_CLRREQERR_4 (0x00100000UL) +#define DMA_INTCLR0_CLRREQERR_5 (0x00200000UL) + +/* Bit definition for DMA_INTCLR1 register */ +#define DMA_INTCLR1_CLRTC_POS (0U) +#define DMA_INTCLR1_CLRTC (0x0000003FUL) +#define DMA_INTCLR1_CLRTC_0 (0x00000001UL) +#define DMA_INTCLR1_CLRTC_1 (0x00000002UL) +#define DMA_INTCLR1_CLRTC_2 (0x00000004UL) +#define DMA_INTCLR1_CLRTC_3 (0x00000008UL) +#define DMA_INTCLR1_CLRTC_4 (0x00000010UL) +#define DMA_INTCLR1_CLRTC_5 (0x00000020UL) +#define DMA_INTCLR1_CLRBTC_POS (16U) +#define DMA_INTCLR1_CLRBTC (0x003F0000UL) +#define DMA_INTCLR1_CLRBTC_0 (0x00010000UL) +#define DMA_INTCLR1_CLRBTC_1 (0x00020000UL) +#define DMA_INTCLR1_CLRBTC_2 (0x00040000UL) +#define DMA_INTCLR1_CLRBTC_3 (0x00080000UL) +#define DMA_INTCLR1_CLRBTC_4 (0x00100000UL) +#define DMA_INTCLR1_CLRBTC_5 (0x00200000UL) + +/* Bit definition for DMA_CHEN register */ +#define DMA_CHEN_CHEN (0x0000003FUL) +#define DMA_CHEN_CHEN_0 (0x00000001UL) +#define DMA_CHEN_CHEN_1 (0x00000002UL) +#define DMA_CHEN_CHEN_2 (0x00000004UL) +#define DMA_CHEN_CHEN_3 (0x00000008UL) +#define DMA_CHEN_CHEN_4 (0x00000010UL) +#define DMA_CHEN_CHEN_5 (0x00000020UL) + +/* Bit definition for DMA_REQSTAT register */ +#define DMA_REQSTAT_CHREQ_POS (0U) +#define DMA_REQSTAT_CHREQ (0x0000003FUL) +#define DMA_REQSTAT_CHREQ_0 (0x00000001UL) +#define DMA_REQSTAT_CHREQ_1 (0x00000002UL) +#define DMA_REQSTAT_CHREQ_2 (0x00000004UL) +#define DMA_REQSTAT_CHREQ_3 (0x00000008UL) +#define DMA_REQSTAT_CHREQ_4 (0x00000010UL) +#define DMA_REQSTAT_CHREQ_5 (0x00000020UL) +#define DMA_REQSTAT_RCFGREQ_POS (15U) +#define DMA_REQSTAT_RCFGREQ (0x00008000UL) + +/* Bit definition for DMA_CHSTAT register */ +#define DMA_CHSTAT_DMAACT_POS (0U) +#define DMA_CHSTAT_DMAACT (0x00000001UL) +#define DMA_CHSTAT_RCFGACT_POS (1U) +#define DMA_CHSTAT_RCFGACT (0x00000002UL) +#define DMA_CHSTAT_CHACT_POS (16U) +#define DMA_CHSTAT_CHACT (0x003F0000UL) +#define DMA_CHSTAT_CHACT_0 (0x00010000UL) +#define DMA_CHSTAT_CHACT_1 (0x00020000UL) +#define DMA_CHSTAT_CHACT_2 (0x00040000UL) +#define DMA_CHSTAT_CHACT_3 (0x00080000UL) +#define DMA_CHSTAT_CHACT_4 (0x00100000UL) +#define DMA_CHSTAT_CHACT_5 (0x00200000UL) + +/* Bit definition for DMA_RCFGCTL register */ +#define DMA_RCFGCTL_RCFGEN_POS (0U) +#define DMA_RCFGCTL_RCFGEN (0x00000001UL) +#define DMA_RCFGCTL_RCFGLLP_POS (1U) +#define DMA_RCFGCTL_RCFGLLP (0x00000002UL) +#define DMA_RCFGCTL_RCFGCHS_POS (8U) +#define DMA_RCFGCTL_RCFGCHS (0x00000F00UL) +#define DMA_RCFGCTL_SARMD_POS (16U) +#define DMA_RCFGCTL_SARMD (0x00030000UL) +#define DMA_RCFGCTL_SARMD_0 (0x00010000UL) +#define DMA_RCFGCTL_SARMD_1 (0x00020000UL) +#define DMA_RCFGCTL_DARMD_POS (18U) +#define DMA_RCFGCTL_DARMD (0x000C0000UL) +#define DMA_RCFGCTL_DARMD_0 (0x00040000UL) +#define DMA_RCFGCTL_DARMD_1 (0x00080000UL) +#define DMA_RCFGCTL_CNTMD_POS (20U) +#define DMA_RCFGCTL_CNTMD (0x00300000UL) +#define DMA_RCFGCTL_CNTMD_0 (0x00100000UL) +#define DMA_RCFGCTL_CNTMD_1 (0x00200000UL) + +/* Bit definition for DMA_CHENCLR register */ +#define DMA_CHENCLR_CHENCLR (0x0000003FUL) +#define DMA_CHENCLR_CHENCLR_0 (0x00000001UL) +#define DMA_CHENCLR_CHENCLR_1 (0x00000002UL) +#define DMA_CHENCLR_CHENCLR_2 (0x00000004UL) +#define DMA_CHENCLR_CHENCLR_3 (0x00000008UL) +#define DMA_CHENCLR_CHENCLR_4 (0x00000010UL) +#define DMA_CHENCLR_CHENCLR_5 (0x00000020UL) + +/* Bit definition for DMA_SAR register */ +#define DMA_SAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DAR register */ +#define DMA_DAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DTCTL register */ +#define DMA_DTCTL_BLKSIZE_POS (0U) +#define DMA_DTCTL_BLKSIZE (0x000003FFUL) +#define DMA_DTCTL_CNT_POS (16U) +#define DMA_DTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_RPT register */ +#define DMA_RPT_SRPT_POS (0U) +#define DMA_RPT_SRPT (0x000003FFUL) +#define DMA_RPT_DRPT_POS (16U) +#define DMA_RPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_RPTB register */ +#define DMA_RPTB_SRPTB_POS (0U) +#define DMA_RPTB_SRPTB (0x000003FFUL) +#define DMA_RPTB_DRPTB_POS (16U) +#define DMA_RPTB_DRPTB (0x03FF0000UL) + +/* Bit definition for DMA_SNSEQCTL register */ +#define DMA_SNSEQCTL_SOFFSET_POS (0U) +#define DMA_SNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_SNSEQCTL_SNSCNT_POS (20U) +#define DMA_SNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_SNSEQCTLB register */ +#define DMA_SNSEQCTLB_SNSDIST_POS (0U) +#define DMA_SNSEQCTLB_SNSDIST (0x000FFFFFUL) +#define DMA_SNSEQCTLB_SNSCNTB_POS (20U) +#define DMA_SNSEQCTLB_SNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTL register */ +#define DMA_DNSEQCTL_DOFFSET_POS (0U) +#define DMA_DNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_DNSEQCTL_DNSCNT_POS (20U) +#define DMA_DNSEQCTL_DNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTLB register */ +#define DMA_DNSEQCTLB_DNSDIST_POS (0U) +#define DMA_DNSEQCTLB_DNSDIST (0x000FFFFFUL) +#define DMA_DNSEQCTLB_DNSCNTB_POS (20U) +#define DMA_DNSEQCTLB_DNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_LLP register */ +#define DMA_LLP_LLP_POS (2U) +#define DMA_LLP_LLP (0xFFFFFFFCUL) + +/* Bit definition for DMA_CHCTL register */ +#define DMA_CHCTL_SINC_POS (0U) +#define DMA_CHCTL_SINC (0x00000003UL) +#define DMA_CHCTL_SINC_0 (0x00000001UL) +#define DMA_CHCTL_SINC_1 (0x00000002UL) +#define DMA_CHCTL_DINC_POS (2U) +#define DMA_CHCTL_DINC (0x0000000CUL) +#define DMA_CHCTL_DINC_0 (0x00000004UL) +#define DMA_CHCTL_DINC_1 (0x00000008UL) +#define DMA_CHCTL_SRPTEN_POS (4U) +#define DMA_CHCTL_SRPTEN (0x00000010UL) +#define DMA_CHCTL_DRPTEN_POS (5U) +#define DMA_CHCTL_DRPTEN (0x00000020UL) +#define DMA_CHCTL_SNSEQEN_POS (6U) +#define DMA_CHCTL_SNSEQEN (0x00000040UL) +#define DMA_CHCTL_DNSEQEN_POS (7U) +#define DMA_CHCTL_DNSEQEN (0x00000080UL) +#define DMA_CHCTL_HSIZE_POS (8U) +#define DMA_CHCTL_HSIZE (0x00000300UL) +#define DMA_CHCTL_HSIZE_0 (0x00000100UL) +#define DMA_CHCTL_HSIZE_1 (0x00000200UL) +#define DMA_CHCTL_LLPEN_POS (10U) +#define DMA_CHCTL_LLPEN (0x00000400UL) +#define DMA_CHCTL_LLPRUN_POS (11U) +#define DMA_CHCTL_LLPRUN (0x00000800UL) +#define DMA_CHCTL_IE_POS (12U) +#define DMA_CHCTL_IE (0x00001000UL) +#define DMA_CHCTL_HPROT_POS (14U) +#define DMA_CHCTL_HPROT (0x0000C000UL) + +/* Bit definition for DMA_MONSAR register */ +#define DMA_MONSAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDAR register */ +#define DMA_MONDAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDTCTL register */ +#define DMA_MONDTCTL_BLKSIZE_POS (0U) +#define DMA_MONDTCTL_BLKSIZE (0x000003FFUL) +#define DMA_MONDTCTL_CNT_POS (16U) +#define DMA_MONDTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_MONRPT register */ +#define DMA_MONRPT_SRPT_POS (0U) +#define DMA_MONRPT_SRPT (0x000003FFUL) +#define DMA_MONRPT_DRPT_POS (16U) +#define DMA_MONRPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_MONSNSEQCTL register */ +#define DMA_MONSNSEQCTL_SOFFSET_POS (0U) +#define DMA_MONSNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_MONSNSEQCTL_SNSCNT_POS (20U) +#define DMA_MONSNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_MONDNSEQCTL register */ +#define DMA_MONDNSEQCTL_DOFFSET_POS (0U) +#define DMA_MONDNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_MONDNSEQCTL_DNSCNT_POS (20U) +#define DMA_MONDNSEQCTL_DNSCNT (0xFFF00000UL) + +/******************************************************************************* + Bit definition for Peripheral EFM +*******************************************************************************/ +/* Bit definition for EFM_FAPRT register */ +#define EFM_FAPRT_FAPRT (0x0000FFFFUL) + +/* Bit definition for EFM_KEY1 register */ +#define EFM_KEY1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_KEY2 register */ +#define EFM_KEY2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_FSTP register */ +#define EFM_FSTP_FSTP (0x00000001UL) + +/* Bit definition for EFM_FRMC register */ +#define EFM_FRMC_FLWT_POS (0U) +#define EFM_FRMC_FLWT (0x0000000FUL) +#define EFM_FRMC_LVM_POS (8U) +#define EFM_FRMC_LVM (0x00000100UL) +#define EFM_FRMC_ICACHE_POS (16U) +#define EFM_FRMC_ICACHE (0x00010000UL) +#define EFM_FRMC_DCACHE_POS (17U) +#define EFM_FRMC_DCACHE (0x00020000UL) +#define EFM_FRMC_PREFETE_POS (18U) +#define EFM_FRMC_PREFETE (0x00040000UL) +#define EFM_FRMC_CRST_POS (19U) +#define EFM_FRMC_CRST (0x00080000UL) + +/* Bit definition for EFM_FWMC register */ +#define EFM_FWMC_PEMOD_POS (0U) +#define EFM_FWMC_PEMOD (0x00000007UL) +#define EFM_FWMC_BUSHLDCTL_POS (8U) +#define EFM_FWMC_BUSHLDCTL (0x00000100UL) +#define EFM_FWMC_KEY1LOCK_POS (16U) +#define EFM_FWMC_KEY1LOCK (0x00010000UL) +#define EFM_FWMC_KEY2LOCK_POS (17U) +#define EFM_FWMC_KEY2LOCK (0x00020000UL) + +/* Bit definition for EFM_FSR register */ +#define EFM_FSR_OTPWERR_POS (0U) +#define EFM_FSR_OTPWERR (0x00000001UL) +#define EFM_FSR_PRTWERR_POS (1U) +#define EFM_FSR_PRTWERR (0x00000002UL) +#define EFM_FSR_PGSZERR_POS (2U) +#define EFM_FSR_PGSZERR (0x00000004UL) +#define EFM_FSR_MISMTCH_POS (3U) +#define EFM_FSR_MISMTCH (0x00000008UL) +#define EFM_FSR_OPTEND_POS (4U) +#define EFM_FSR_OPTEND (0x00000010UL) +#define EFM_FSR_COLERR_POS (5U) +#define EFM_FSR_COLERR (0x00000020UL) +#define EFM_FSR_RDY_POS (8U) +#define EFM_FSR_RDY (0x00000100UL) + +/* Bit definition for EFM_FSCLR register */ +#define EFM_FSCLR_OTPWERRCLR_POS (0U) +#define EFM_FSCLR_OTPWERRCLR (0x00000001UL) +#define EFM_FSCLR_PRTWERRCLR_POS (1U) +#define EFM_FSCLR_PRTWERRCLR (0x00000002UL) +#define EFM_FSCLR_PGSZERRCLR_POS (2U) +#define EFM_FSCLR_PGSZERRCLR (0x00000004UL) +#define EFM_FSCLR_MISMTCHCLR_POS (3U) +#define EFM_FSCLR_MISMTCHCLR (0x00000008UL) +#define EFM_FSCLR_OPTENDCLR_POS (4U) +#define EFM_FSCLR_OPTENDCLR (0x00000010UL) +#define EFM_FSCLR_COLERRCLR_POS (5U) +#define EFM_FSCLR_COLERRCLR (0x00000020UL) + +/* Bit definition for EFM_FITE register */ +#define EFM_FITE_PEERRITE_POS (0U) +#define EFM_FITE_PEERRITE (0x00000001UL) +#define EFM_FITE_OPTENDITE_POS (1U) +#define EFM_FITE_OPTENDITE (0x00000002UL) +#define EFM_FITE_COLERRITE_POS (2U) +#define EFM_FITE_COLERRITE (0x00000004UL) + +/* Bit definition for EFM_FSWP register */ +#define EFM_FSWP_FSWP (0x00000001UL) + +/* Bit definition for EFM_CHIPID register */ +#define EFM_CHIPID (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID0 register */ +#define EFM_UQID0_Y_LOCATION_POS (0U) +#define EFM_UQID0_Y_LOCATION (0x000000FFUL) +#define EFM_UQID0_X_LOCATION_POS (8U) +#define EFM_UQID0_X_LOCATION (0x0000FF00UL) +#define EFM_UQID0_WAFER_ID_POS (16U) +#define EFM_UQID0_WAFER_ID (0x00FF0000UL) +#define EFM_UQID0_LOT_ID_POS (24U) +#define EFM_UQID0_LOT_ID (0xFF000000UL) + +/* Bit definition for EFM_UQID1 register */ +#define EFM_UQID1_LOT_ID (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID2 register */ +#define EFM_UQID2_LOT_ID (0x000000FFUL) + +/* Bit definition for EFM_MMF_REMPRT register */ +#define EFM_MMF_REMPRT_MMF_REMPRT (0x0000FFFFUL) + +/* Bit definition for EFM_MMF_REMCR register */ +#define EFM_MMF_REMCR_RMSIZE_POS (0U) +#define EFM_MMF_REMCR_RMSIZE (0x0000001FUL) +#define EFM_MMF_REMCR_RMTADDR_POS (12U) +#define EFM_MMF_REMCR_RMTADDR (0x1FFFF000UL) +#define EFM_MMF_REMCR_EN_POS (31U) +#define EFM_MMF_REMCR_EN (0x80000000UL) + +/* Bit definition for EFM_WLOCK register */ +#define EFM_WLOCK_WLOCK0 (0x00000001UL) + +/* Bit definition for EFM_F0NWPRT register */ +#define EFM_F0NWPRT_F0NWPRT0_POS (0U) +#define EFM_F0NWPRT_F0NWPRT0 (0x00000001UL) +#define EFM_F0NWPRT_F0NWPRT1_POS (1U) +#define EFM_F0NWPRT_F0NWPRT1 (0x00000002UL) +#define EFM_F0NWPRT_F0NWPRT2_POS (2U) +#define EFM_F0NWPRT_F0NWPRT2 (0x00000004UL) +#define EFM_F0NWPRT_F0NWPRT3_POS (3U) +#define EFM_F0NWPRT_F0NWPRT3 (0x00000008UL) +#define EFM_F0NWPRT_F0NWPRT4_POS (4U) +#define EFM_F0NWPRT_F0NWPRT4 (0x00000010UL) +#define EFM_F0NWPRT_F0NWPRT5_POS (5U) +#define EFM_F0NWPRT_F0NWPRT5 (0x00000020UL) +#define EFM_F0NWPRT_F0NWPRT6_POS (6U) +#define EFM_F0NWPRT_F0NWPRT6 (0x00000040UL) +#define EFM_F0NWPRT_F0NWPRT7_POS (7U) +#define EFM_F0NWPRT_F0NWPRT7 (0x00000080UL) +#define EFM_F0NWPRT_F0NWPRT8_POS (8U) +#define EFM_F0NWPRT_F0NWPRT8 (0x00000100UL) +#define EFM_F0NWPRT_F0NWPRT9_POS (9U) +#define EFM_F0NWPRT_F0NWPRT9 (0x00000200UL) +#define EFM_F0NWPRT_F0NWPRT10_POS (10U) +#define EFM_F0NWPRT_F0NWPRT10 (0x00000400UL) +#define EFM_F0NWPRT_F0NWPRT11_POS (11U) +#define EFM_F0NWPRT_F0NWPRT11 (0x00000800UL) +#define EFM_F0NWPRT_F0NWPRT12_POS (12U) +#define EFM_F0NWPRT_F0NWPRT12 (0x00001000UL) +#define EFM_F0NWPRT_F0NWPRT13_POS (13U) +#define EFM_F0NWPRT_F0NWPRT13 (0x00002000UL) +#define EFM_F0NWPRT_F0NWPRT14_POS (14U) +#define EFM_F0NWPRT_F0NWPRT14 (0x00004000UL) +#define EFM_F0NWPRT_F0NWPRT15_POS (15U) +#define EFM_F0NWPRT_F0NWPRT15 (0x00008000UL) +#define EFM_F0NWPRT_F0NWPRT16_POS (16U) +#define EFM_F0NWPRT_F0NWPRT16 (0x00010000UL) +#define EFM_F0NWPRT_F0NWPRT17_POS (17U) +#define EFM_F0NWPRT_F0NWPRT17 (0x00020000UL) +#define EFM_F0NWPRT_F0NWPRT18_POS (18U) +#define EFM_F0NWPRT_F0NWPRT18 (0x00040000UL) +#define EFM_F0NWPRT_F0NWPRT19_POS (19U) +#define EFM_F0NWPRT_F0NWPRT19 (0x00080000UL) +#define EFM_F0NWPRT_F0NWPRT20_POS (20U) +#define EFM_F0NWPRT_F0NWPRT20 (0x00100000UL) +#define EFM_F0NWPRT_F0NWPRT21_POS (21U) +#define EFM_F0NWPRT_F0NWPRT21 (0x00200000UL) +#define EFM_F0NWPRT_F0NWPRT22_POS (22U) +#define EFM_F0NWPRT_F0NWPRT22 (0x00400000UL) +#define EFM_F0NWPRT_F0NWPRT23_POS (23U) +#define EFM_F0NWPRT_F0NWPRT23 (0x00800000UL) +#define EFM_F0NWPRT_F0NWPRT24_POS (24U) +#define EFM_F0NWPRT_F0NWPRT24 (0x01000000UL) +#define EFM_F0NWPRT_F0NWPRT25_POS (25U) +#define EFM_F0NWPRT_F0NWPRT25 (0x02000000UL) +#define EFM_F0NWPRT_F0NWPRT26_POS (26U) +#define EFM_F0NWPRT_F0NWPRT26 (0x04000000UL) +#define EFM_F0NWPRT_F0NWPRT27_POS (27U) +#define EFM_F0NWPRT_F0NWPRT27 (0x08000000UL) +#define EFM_F0NWPRT_F0NWPRT28_POS (28U) +#define EFM_F0NWPRT_F0NWPRT28 (0x10000000UL) +#define EFM_F0NWPRT_F0NWPRT29_POS (29U) +#define EFM_F0NWPRT_F0NWPRT29 (0x20000000UL) +#define EFM_F0NWPRT_F0NWPRT30_POS (30U) +#define EFM_F0NWPRT_F0NWPRT30 (0x40000000UL) +#define EFM_F0NWPRT_F0NWPRT31_POS (31U) +#define EFM_F0NWPRT_F0NWPRT31 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral EMB +*******************************************************************************/ +/* Bit definition for EMB_CTL1 register */ +#define EMB_CTL1_CMPEN1_POS (0U) +#define EMB_CTL1_CMPEN1 (0x00000001UL) +#define EMB_CTL1_CMPEN2_POS (1U) +#define EMB_CTL1_CMPEN2 (0x00000002UL) +#define EMB_CTL1_CMPEN3_POS (2U) +#define EMB_CTL1_CMPEN3 (0x00000004UL) +#define EMB_CTL1_CMPEN4_POS (3U) +#define EMB_CTL1_CMPEN4 (0x00000008UL) +#define EMB_CTL1_SYSEN_POS (4U) +#define EMB_CTL1_SYSEN (0x00000010UL) +#define EMB_CTL1_PWMSEN0_POS (5U) +#define EMB_CTL1_PWMSEN0 (0x00000020UL) +#define EMB_CTL1_PWMSEN1_POS (6U) +#define EMB_CTL1_PWMSEN1 (0x00000040UL) +#define EMB_CTL1_PWMSEN2_POS (7U) +#define EMB_CTL1_PWMSEN2 (0x00000080UL) +#define EMB_CTL1_PWMSEN3_POS (8U) +#define EMB_CTL1_PWMSEN3 (0x00000100UL) +#define EMB_CTL1_PORTINEN1_POS (16U) +#define EMB_CTL1_PORTINEN1 (0x00010000UL) +#define EMB_CTL1_PORTINEN2_POS (17U) +#define EMB_CTL1_PORTINEN2 (0x00020000UL) +#define EMB_CTL1_PORTINEN3_POS (18U) +#define EMB_CTL1_PORTINEN3 (0x00040000UL) +#define EMB_CTL1_PORTINEN4_POS (19U) +#define EMB_CTL1_PORTINEN4 (0x00080000UL) +#define EMB_CTL1_INVSEL1_POS (22U) +#define EMB_CTL1_INVSEL1 (0x00400000UL) +#define EMB_CTL1_INVSEL2_POS (23U) +#define EMB_CTL1_INVSEL2 (0x00800000UL) +#define EMB_CTL1_INVSEL3_POS (24U) +#define EMB_CTL1_INVSEL3 (0x01000000UL) +#define EMB_CTL1_INVSEL4_POS (25U) +#define EMB_CTL1_INVSEL4 (0x02000000UL) +#define EMB_CTL1_OSCSTPEN_POS (27U) +#define EMB_CTL1_OSCSTPEN (0x08000000UL) +#define EMB_CTL1_SRAMECCERREN_POS (28U) +#define EMB_CTL1_SRAMECCERREN (0x10000000UL) +#define EMB_CTL1_SRAMPYERREN_POS (29U) +#define EMB_CTL1_SRAMPYERREN (0x20000000UL) +#define EMB_CTL1_LOCKUPEN_POS (30U) +#define EMB_CTL1_LOCKUPEN (0x40000000UL) +#define EMB_CTL1_PVDEN_POS (31U) +#define EMB_CTL1_PVDEN (0x80000000UL) + +/* Bit definition for EMB_CTL2 register */ +#define EMB_CTL2_PWMLV0_POS (0U) +#define EMB_CTL2_PWMLV0 (0x00000001UL) +#define EMB_CTL2_PWMLV1_POS (1U) +#define EMB_CTL2_PWMLV1 (0x00000002UL) +#define EMB_CTL2_PWMLV2_POS (2U) +#define EMB_CTL2_PWMLV2 (0x00000004UL) +#define EMB_CTL2_PWMLV3_POS (3U) +#define EMB_CTL2_PWMLV3 (0x00000008UL) +#define EMB_CTL2_NFSEL1_POS (16U) +#define EMB_CTL2_NFSEL1 (0x00030000UL) +#define EMB_CTL2_NFEN1_POS (18U) +#define EMB_CTL2_NFEN1 (0x00040000UL) +#define EMB_CTL2_NFSEL2_POS (19U) +#define EMB_CTL2_NFSEL2 (0x00180000UL) +#define EMB_CTL2_NFEN2_POS (21U) +#define EMB_CTL2_NFEN2 (0x00200000UL) +#define EMB_CTL2_NFSEL3_POS (22U) +#define EMB_CTL2_NFSEL3 (0x00C00000UL) +#define EMB_CTL2_NFEN3_POS (24U) +#define EMB_CTL2_NFEN3 (0x01000000UL) +#define EMB_CTL2_NFSEL4_POS (25U) +#define EMB_CTL2_NFSEL4 (0x06000000UL) +#define EMB_CTL2_NFEN4_POS (27U) +#define EMB_CTL2_NFEN4 (0x08000000UL) + +/* Bit definition for EMB_SOE register */ +#define EMB_SOE_SOE (0x00000001UL) + +/* Bit definition for EMB_STAT register */ +#define EMB_STAT_PWMSF_POS (1U) +#define EMB_STAT_PWMSF (0x00000002UL) +#define EMB_STAT_CMPF_POS (2U) +#define EMB_STAT_CMPF (0x00000004UL) +#define EMB_STAT_SYSF_POS (3U) +#define EMB_STAT_SYSF (0x00000008UL) +#define EMB_STAT_PWMST_POS (5U) +#define EMB_STAT_PWMST (0x00000020UL) +#define EMB_STAT_CMPST_POS (6U) +#define EMB_STAT_CMPST (0x00000040UL) +#define EMB_STAT_SYSST_POS (7U) +#define EMB_STAT_SYSST (0x00000080UL) +#define EMB_STAT_PORTINF1_POS (8U) +#define EMB_STAT_PORTINF1 (0x00000100UL) +#define EMB_STAT_PORTINF2_POS (9U) +#define EMB_STAT_PORTINF2 (0x00000200UL) +#define EMB_STAT_PORTINF3_POS (10U) +#define EMB_STAT_PORTINF3 (0x00000400UL) +#define EMB_STAT_PORTINF4_POS (11U) +#define EMB_STAT_PORTINF4 (0x00000800UL) +#define EMB_STAT_PORTINST1_POS (14U) +#define EMB_STAT_PORTINST1 (0x00004000UL) +#define EMB_STAT_PORTINST2_POS (15U) +#define EMB_STAT_PORTINST2 (0x00008000UL) +#define EMB_STAT_PORTINST3_POS (16U) +#define EMB_STAT_PORTINST3 (0x00010000UL) +#define EMB_STAT_PORTINST4_POS (17U) +#define EMB_STAT_PORTINST4 (0x00020000UL) + +/* Bit definition for EMB_STATCLR register */ +#define EMB_STATCLR_PWMSFCLR_POS (1U) +#define EMB_STATCLR_PWMSFCLR (0x00000002UL) +#define EMB_STATCLR_CMPFCLR_POS (2U) +#define EMB_STATCLR_CMPFCLR (0x00000004UL) +#define EMB_STATCLR_SYSFCLR_POS (3U) +#define EMB_STATCLR_SYSFCLR (0x00000008UL) +#define EMB_STATCLR_PORTINFCLR1_POS (8U) +#define EMB_STATCLR_PORTINFCLR1 (0x00000100UL) +#define EMB_STATCLR_PORTINFCLR2_POS (9U) +#define EMB_STATCLR_PORTINFCLR2 (0x00000200UL) +#define EMB_STATCLR_PORTINFCLR3_POS (10U) +#define EMB_STATCLR_PORTINFCLR3 (0x00000400UL) +#define EMB_STATCLR_PORTINFCLR4_POS (11U) +#define EMB_STATCLR_PORTINFCLR4 (0x00000800UL) + +/* Bit definition for EMB_INTEN register */ +#define EMB_INTEN_PWMSINTEN_POS (1U) +#define EMB_INTEN_PWMSINTEN (0x00000002UL) +#define EMB_INTEN_CMPINTEN_POS (2U) +#define EMB_INTEN_CMPINTEN (0x00000004UL) +#define EMB_INTEN_SYSINTEN_POS (3U) +#define EMB_INTEN_SYSINTEN (0x00000008UL) +#define EMB_INTEN_PORTININTEN1_POS (8U) +#define EMB_INTEN_PORTININTEN1 (0x00000100UL) +#define EMB_INTEN_PORTININTEN2_POS (9U) +#define EMB_INTEN_PORTININTEN2 (0x00000200UL) +#define EMB_INTEN_PORTININTEN3_POS (10U) +#define EMB_INTEN_PORTININTEN3 (0x00000400UL) +#define EMB_INTEN_PORTININTEN4_POS (11U) +#define EMB_INTEN_PORTININTEN4 (0x00000800UL) + +/* Bit definition for EMB_RLSSEL register */ +#define EMB_RLSSEL_PWMRSEL_POS (1U) +#define EMB_RLSSEL_PWMRSEL (0x00000002UL) +#define EMB_RLSSEL_CMPRSEL_POS (2U) +#define EMB_RLSSEL_CMPRSEL (0x00000004UL) +#define EMB_RLSSEL_SYSRSEL_POS (3U) +#define EMB_RLSSEL_SYSRSEL (0x00000008UL) +#define EMB_RLSSEL_PORTINRSEL1_POS (8U) +#define EMB_RLSSEL_PORTINRSEL1 (0x00000100UL) +#define EMB_RLSSEL_PORTINRSEL2_POS (9U) +#define EMB_RLSSEL_PORTINRSEL2 (0x00000200UL) +#define EMB_RLSSEL_PORTINRSEL3_POS (10U) +#define EMB_RLSSEL_PORTINRSEL3 (0x00000400UL) +#define EMB_RLSSEL_PORTINRSEL4_POS (11U) +#define EMB_RLSSEL_PORTINRSEL4 (0x00000800UL) + +/******************************************************************************* + Bit definition for Peripheral FCM +*******************************************************************************/ +/* Bit definition for FCM_LVR register */ +#define FCM_LVR_LVR (0x0000FFFFUL) + +/* Bit definition for FCM_UVR register */ +#define FCM_UVR_UVR (0x0000FFFFUL) + +/* Bit definition for FCM_CNTR register */ +#define FCM_CNTR_CNTR (0x0000FFFFUL) + +/* Bit definition for FCM_STR register */ +#define FCM_STR_START (0x00000001UL) + +/* Bit definition for FCM_MCCR register */ +#define FCM_MCCR_MDIVS_POS (0U) +#define FCM_MCCR_MDIVS (0x00000003UL) +#define FCM_MCCR_MDIVS_0 (0x00000001UL) +#define FCM_MCCR_MDIVS_1 (0x00000002UL) +#define FCM_MCCR_MCKS_POS (4U) +#define FCM_MCCR_MCKS (0x000000F0UL) + +/* Bit definition for FCM_RCCR register */ +#define FCM_RCCR_RDIVS_POS (0U) +#define FCM_RCCR_RDIVS (0x00000003UL) +#define FCM_RCCR_RDIVS_0 (0x00000001UL) +#define FCM_RCCR_RDIVS_1 (0x00000002UL) +#define FCM_RCCR_RCKS_POS (3U) +#define FCM_RCCR_RCKS (0x00000078UL) +#define FCM_RCCR_INEXS_POS (7U) +#define FCM_RCCR_INEXS (0x00000080UL) +#define FCM_RCCR_DNFS_POS (8U) +#define FCM_RCCR_DNFS (0x00000300UL) +#define FCM_RCCR_DNFS_0 (0x00000100UL) +#define FCM_RCCR_DNFS_1 (0x00000200UL) +#define FCM_RCCR_EDGES_POS (12U) +#define FCM_RCCR_EDGES (0x00003000UL) +#define FCM_RCCR_EDGES_0 (0x00001000UL) +#define FCM_RCCR_EDGES_1 (0x00002000UL) +#define FCM_RCCR_EXREFE_POS (15U) +#define FCM_RCCR_EXREFE (0x00008000UL) + +/* Bit definition for FCM_RIER register */ +#define FCM_RIER_ERRIE_POS (0U) +#define FCM_RIER_ERRIE (0x00000001UL) +#define FCM_RIER_MENDIE_POS (1U) +#define FCM_RIER_MENDIE (0x00000002UL) +#define FCM_RIER_OVFIE_POS (2U) +#define FCM_RIER_OVFIE (0x00000004UL) +#define FCM_RIER_ERRINTRS_POS (4U) +#define FCM_RIER_ERRINTRS (0x00000010UL) +#define FCM_RIER_ERRE_POS (7U) +#define FCM_RIER_ERRE (0x00000080UL) + +/* Bit definition for FCM_SR register */ +#define FCM_SR_ERRF_POS (0U) +#define FCM_SR_ERRF (0x00000001UL) +#define FCM_SR_MENDF_POS (1U) +#define FCM_SR_MENDF (0x00000002UL) +#define FCM_SR_OVF_POS (2U) +#define FCM_SR_OVF (0x00000004UL) + +/* Bit definition for FCM_CLR register */ +#define FCM_CLR_ERRFCLR_POS (0U) +#define FCM_CLR_ERRFCLR (0x00000001UL) +#define FCM_CLR_MENDFCLR_POS (1U) +#define FCM_CLR_MENDFCLR (0x00000002UL) +#define FCM_CLR_OVFCLR_POS (2U) +#define FCM_CLR_OVFCLR (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral GPIO +*******************************************************************************/ +/* Bit definition for GPIO_PIDR register */ +#define GPIO_PIDR_PIN00_POS (0U) +#define GPIO_PIDR_PIN00 (0x0001U) +#define GPIO_PIDR_PIN01_POS (1U) +#define GPIO_PIDR_PIN01 (0x0002U) +#define GPIO_PIDR_PIN02_POS (2U) +#define GPIO_PIDR_PIN02 (0x0004U) +#define GPIO_PIDR_PIN03_POS (3U) +#define GPIO_PIDR_PIN03 (0x0008U) +#define GPIO_PIDR_PIN04_POS (4U) +#define GPIO_PIDR_PIN04 (0x0010U) +#define GPIO_PIDR_PIN05_POS (5U) +#define GPIO_PIDR_PIN05 (0x0020U) +#define GPIO_PIDR_PIN06_POS (6U) +#define GPIO_PIDR_PIN06 (0x0040U) +#define GPIO_PIDR_PIN07_POS (7U) +#define GPIO_PIDR_PIN07 (0x0080U) +#define GPIO_PIDR_PIN08_POS (8U) +#define GPIO_PIDR_PIN08 (0x0100U) +#define GPIO_PIDR_PIN09_POS (9U) +#define GPIO_PIDR_PIN09 (0x0200U) +#define GPIO_PIDR_PIN10_POS (10U) +#define GPIO_PIDR_PIN10 (0x0400U) +#define GPIO_PIDR_PIN11_POS (11U) +#define GPIO_PIDR_PIN11 (0x0800U) +#define GPIO_PIDR_PIN12_POS (12U) +#define GPIO_PIDR_PIN12 (0x1000U) +#define GPIO_PIDR_PIN13_POS (13U) +#define GPIO_PIDR_PIN13 (0x2000U) +#define GPIO_PIDR_PIN14_POS (14U) +#define GPIO_PIDR_PIN14 (0x4000U) +#define GPIO_PIDR_PIN15_POS (15U) +#define GPIO_PIDR_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODR register */ +#define GPIO_PODR_POUT00_POS (0U) +#define GPIO_PODR_POUT00 (0x0001U) +#define GPIO_PODR_POUT01_POS (1U) +#define GPIO_PODR_POUT01 (0x0002U) +#define GPIO_PODR_POUT02_POS (2U) +#define GPIO_PODR_POUT02 (0x0004U) +#define GPIO_PODR_POUT03_POS (3U) +#define GPIO_PODR_POUT03 (0x0008U) +#define GPIO_PODR_POUT04_POS (4U) +#define GPIO_PODR_POUT04 (0x0010U) +#define GPIO_PODR_POUT05_POS (5U) +#define GPIO_PODR_POUT05 (0x0020U) +#define GPIO_PODR_POUT06_POS (6U) +#define GPIO_PODR_POUT06 (0x0040U) +#define GPIO_PODR_POUT07_POS (7U) +#define GPIO_PODR_POUT07 (0x0080U) +#define GPIO_PODR_POUT08_POS (8U) +#define GPIO_PODR_POUT08 (0x0100U) +#define GPIO_PODR_POUT09_POS (9U) +#define GPIO_PODR_POUT09 (0x0200U) +#define GPIO_PODR_POUT10_POS (10U) +#define GPIO_PODR_POUT10 (0x0400U) +#define GPIO_PODR_POUT11_POS (11U) +#define GPIO_PODR_POUT11 (0x0800U) +#define GPIO_PODR_POUT12_POS (12U) +#define GPIO_PODR_POUT12 (0x1000U) +#define GPIO_PODR_POUT13_POS (13U) +#define GPIO_PODR_POUT13 (0x2000U) +#define GPIO_PODR_POUT14_POS (14U) +#define GPIO_PODR_POUT14 (0x4000U) +#define GPIO_PODR_POUT15_POS (15U) +#define GPIO_PODR_POUT15 (0x8000U) + +/* Bit definition for GPIO_POER register */ +#define GPIO_POER_POUTE00_POS (0U) +#define GPIO_POER_POUTE00 (0x0001U) +#define GPIO_POER_POUTE01_POS (1U) +#define GPIO_POER_POUTE01 (0x0002U) +#define GPIO_POER_POUTE02_POS (2U) +#define GPIO_POER_POUTE02 (0x0004U) +#define GPIO_POER_POUTE03_POS (3U) +#define GPIO_POER_POUTE03 (0x0008U) +#define GPIO_POER_POUTE04_POS (4U) +#define GPIO_POER_POUTE04 (0x0010U) +#define GPIO_POER_POUTE05_POS (5U) +#define GPIO_POER_POUTE05 (0x0020U) +#define GPIO_POER_POUTE06_POS (6U) +#define GPIO_POER_POUTE06 (0x0040U) +#define GPIO_POER_POUTE07_POS (7U) +#define GPIO_POER_POUTE07 (0x0080U) +#define GPIO_POER_POUTE08_POS (8U) +#define GPIO_POER_POUTE08 (0x0100U) +#define GPIO_POER_POUTE09_POS (9U) +#define GPIO_POER_POUTE09 (0x0200U) +#define GPIO_POER_POUTE10_POS (10U) +#define GPIO_POER_POUTE10 (0x0400U) +#define GPIO_POER_POUTE11_POS (11U) +#define GPIO_POER_POUTE11 (0x0800U) +#define GPIO_POER_POUTE12_POS (12U) +#define GPIO_POER_POUTE12 (0x1000U) +#define GPIO_POER_POUTE13_POS (13U) +#define GPIO_POER_POUTE13 (0x2000U) +#define GPIO_POER_POUTE14_POS (14U) +#define GPIO_POER_POUTE14 (0x4000U) +#define GPIO_POER_POUTE15_POS (15U) +#define GPIO_POER_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSR register */ +#define GPIO_POSR_POS00_POS (0U) +#define GPIO_POSR_POS00 (0x0001U) +#define GPIO_POSR_POS01_POS (1U) +#define GPIO_POSR_POS01 (0x0002U) +#define GPIO_POSR_POS02_POS (2U) +#define GPIO_POSR_POS02 (0x0004U) +#define GPIO_POSR_POS03_POS (3U) +#define GPIO_POSR_POS03 (0x0008U) +#define GPIO_POSR_POS04_POS (4U) +#define GPIO_POSR_POS04 (0x0010U) +#define GPIO_POSR_POS05_POS (5U) +#define GPIO_POSR_POS05 (0x0020U) +#define GPIO_POSR_POS06_POS (6U) +#define GPIO_POSR_POS06 (0x0040U) +#define GPIO_POSR_POS07_POS (7U) +#define GPIO_POSR_POS07 (0x0080U) +#define GPIO_POSR_POS08_POS (8U) +#define GPIO_POSR_POS08 (0x0100U) +#define GPIO_POSR_POS09_POS (9U) +#define GPIO_POSR_POS09 (0x0200U) +#define GPIO_POSR_POS10_POS (10U) +#define GPIO_POSR_POS10 (0x0400U) +#define GPIO_POSR_POS11_POS (11U) +#define GPIO_POSR_POS11 (0x0800U) +#define GPIO_POSR_POS12_POS (12U) +#define GPIO_POSR_POS12 (0x1000U) +#define GPIO_POSR_POS13_POS (13U) +#define GPIO_POSR_POS13 (0x2000U) +#define GPIO_POSR_POS14_POS (14U) +#define GPIO_POSR_POS14 (0x4000U) +#define GPIO_POSR_POS15_POS (15U) +#define GPIO_POSR_POS15 (0x8000U) + +/* Bit definition for GPIO_PORR register */ +#define GPIO_PORR_POR00_POS (0U) +#define GPIO_PORR_POR00 (0x0001U) +#define GPIO_PORR_POR01_POS (1U) +#define GPIO_PORR_POR01 (0x0002U) +#define GPIO_PORR_POR02_POS (2U) +#define GPIO_PORR_POR02 (0x0004U) +#define GPIO_PORR_POR03_POS (3U) +#define GPIO_PORR_POR03 (0x0008U) +#define GPIO_PORR_POR04_POS (4U) +#define GPIO_PORR_POR04 (0x0010U) +#define GPIO_PORR_POR05_POS (5U) +#define GPIO_PORR_POR05 (0x0020U) +#define GPIO_PORR_POR06_POS (6U) +#define GPIO_PORR_POR06 (0x0040U) +#define GPIO_PORR_POR07_POS (7U) +#define GPIO_PORR_POR07 (0x0080U) +#define GPIO_PORR_POR08_POS (8U) +#define GPIO_PORR_POR08 (0x0100U) +#define GPIO_PORR_POR09_POS (9U) +#define GPIO_PORR_POR09 (0x0200U) +#define GPIO_PORR_POR10_POS (10U) +#define GPIO_PORR_POR10 (0x0400U) +#define GPIO_PORR_POR11_POS (11U) +#define GPIO_PORR_POR11 (0x0800U) +#define GPIO_PORR_POR12_POS (12U) +#define GPIO_PORR_POR12 (0x1000U) +#define GPIO_PORR_POR13_POS (13U) +#define GPIO_PORR_POR13 (0x2000U) +#define GPIO_PORR_POR14_POS (14U) +#define GPIO_PORR_POR14 (0x4000U) +#define GPIO_PORR_POR15_POS (15U) +#define GPIO_PORR_POR15 (0x8000U) + +/* Bit definition for GPIO_POTR register */ +#define GPIO_POTR_POT00_POS (0U) +#define GPIO_POTR_POT00 (0x0001U) +#define GPIO_POTR_POT01_POS (1U) +#define GPIO_POTR_POT01 (0x0002U) +#define GPIO_POTR_POT02_POS (2U) +#define GPIO_POTR_POT02 (0x0004U) +#define GPIO_POTR_POT03_POS (3U) +#define GPIO_POTR_POT03 (0x0008U) +#define GPIO_POTR_POT04_POS (4U) +#define GPIO_POTR_POT04 (0x0010U) +#define GPIO_POTR_POT05_POS (5U) +#define GPIO_POTR_POT05 (0x0020U) +#define GPIO_POTR_POT06_POS (6U) +#define GPIO_POTR_POT06 (0x0040U) +#define GPIO_POTR_POT07_POS (7U) +#define GPIO_POTR_POT07 (0x0080U) +#define GPIO_POTR_POT08_POS (8U) +#define GPIO_POTR_POT08 (0x0100U) +#define GPIO_POTR_POT09_POS (9U) +#define GPIO_POTR_POT09 (0x0200U) +#define GPIO_POTR_POT10_POS (10U) +#define GPIO_POTR_POT10 (0x0400U) +#define GPIO_POTR_POT11_POS (11U) +#define GPIO_POTR_POT11 (0x0800U) +#define GPIO_POTR_POT12_POS (12U) +#define GPIO_POTR_POT12 (0x1000U) +#define GPIO_POTR_POT13_POS (13U) +#define GPIO_POTR_POT13 (0x2000U) +#define GPIO_POTR_POT14_POS (14U) +#define GPIO_POTR_POT14 (0x4000U) +#define GPIO_POTR_POT15_POS (15U) +#define GPIO_POTR_POT15 (0x8000U) + +/* Bit definition for GPIO_PSPCR register */ +#define GPIO_PSPCR_SPFE (0x001FU) + +/* Bit definition for GPIO_PCCR register */ +#define GPIO_PCCR_BFSEL_POS (0U) +#define GPIO_PCCR_BFSEL (0x003FU) +#define GPIO_PCCR_RDWT_POS (12U) +#define GPIO_PCCR_RDWT (0x7000U) + +/* Bit definition for GPIO_PWPR register */ +#define GPIO_PWPR_WE_POS (0U) +#define GPIO_PWPR_WE (0x0001U) +#define GPIO_PWPR_WP_POS (8U) +#define GPIO_PWPR_WP (0xFF00U) + +/* Bit definition for GPIO_PCR register */ +#define GPIO_PCR_POUT_POS (0U) +#define GPIO_PCR_POUT (0x0001U) +#define GPIO_PCR_POUTE_POS (1U) +#define GPIO_PCR_POUTE (0x0002U) +#define GPIO_PCR_NOD_POS (2U) +#define GPIO_PCR_NOD (0x0004U) +#define GPIO_PCR_DRV_POS (4U) +#define GPIO_PCR_DRV (0x0030U) +#define GPIO_PCR_DRV_0 (0x0010U) +#define GPIO_PCR_DRV_1 (0x0020U) +#define GPIO_PCR_PUU_POS (6U) +#define GPIO_PCR_PUU (0x0040U) +#define GPIO_PCR_PUD_POS (7U) +#define GPIO_PCR_PUD (0x0080U) +#define GPIO_PCR_PIN_POS (8U) +#define GPIO_PCR_PIN (0x0100U) +#define GPIO_PCR_INVE_POS (9U) +#define GPIO_PCR_INVE (0x0200U) +#define GPIO_PCR_CINSEL_POS (10U) +#define GPIO_PCR_CINSEL (0x0400U) +#define GPIO_PCR_INTE_POS (12U) +#define GPIO_PCR_INTE (0x1000U) +#define GPIO_PCR_PINAE_POS (13U) +#define GPIO_PCR_PINAE (0x2000U) +#define GPIO_PCR_LTE_POS (14U) +#define GPIO_PCR_LTE (0x4000U) +#define GPIO_PCR_DDIS_POS (15U) +#define GPIO_PCR_DDIS (0x8000U) + +/* Bit definition for GPIO_PFSR register */ +#define GPIO_PFSR_FSEL_POS (0U) +#define GPIO_PFSR_FSEL (0x003FU) +#define GPIO_PFSR_BFE_POS (8U) +#define GPIO_PFSR_BFE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral HASH +*******************************************************************************/ +/* Bit definition for HASH_CR register */ +#define HASH_CR_START_POS (0U) +#define HASH_CR_START (0x00000001UL) +#define HASH_CR_FST_GRP_POS (1U) +#define HASH_CR_FST_GRP (0x00000002UL) + +/* Bit definition for HASH_HR7 register */ +#define HASH_HR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR6 register */ +#define HASH_HR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR5 register */ +#define HASH_HR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR4 register */ +#define HASH_HR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR3 register */ +#define HASH_HR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR2 register */ +#define HASH_HR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR1 register */ +#define HASH_HR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR0 register */ +#define HASH_HR0 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR15 register */ +#define HASH_DR15 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR14 register */ +#define HASH_DR14 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR13 register */ +#define HASH_DR13 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR12 register */ +#define HASH_DR12 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR11 register */ +#define HASH_DR11 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR10 register */ +#define HASH_DR10 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR9 register */ +#define HASH_DR9 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR8 register */ +#define HASH_DR8 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR7 register */ +#define HASH_DR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR6 register */ +#define HASH_DR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR5 register */ +#define HASH_DR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR4 register */ +#define HASH_DR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR3 register */ +#define HASH_DR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR2 register */ +#define HASH_DR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR1 register */ +#define HASH_DR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR0 register */ +#define HASH_DR0 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral I2C +*******************************************************************************/ +/* Bit definition for I2C_CR1 register */ +#define I2C_CR1_PE_POS (0U) +#define I2C_CR1_PE (0x00000001UL) +#define I2C_CR1_SMBUS_POS (1U) +#define I2C_CR1_SMBUS (0x00000002UL) +#define I2C_CR1_SMBALRTEN_POS (2U) +#define I2C_CR1_SMBALRTEN (0x00000004UL) +#define I2C_CR1_SMBDEFAULTEN_POS (3U) +#define I2C_CR1_SMBDEFAULTEN (0x00000008UL) +#define I2C_CR1_SMBHOSTEN_POS (4U) +#define I2C_CR1_SMBHOSTEN (0x00000010UL) +#define I2C_CR1_ENGC_POS (6U) +#define I2C_CR1_ENGC (0x00000040UL) +#define I2C_CR1_RESTART_POS (7U) +#define I2C_CR1_RESTART (0x00000080UL) +#define I2C_CR1_START_POS (8U) +#define I2C_CR1_START (0x00000100UL) +#define I2C_CR1_STOP_POS (9U) +#define I2C_CR1_STOP (0x00000200UL) +#define I2C_CR1_ACK_POS (10U) +#define I2C_CR1_ACK (0x00000400UL) +#define I2C_CR1_SWRST_POS (15U) +#define I2C_CR1_SWRST (0x00008000UL) + +/* Bit definition for I2C_CR2 register */ +#define I2C_CR2_STARTIE_POS (0U) +#define I2C_CR2_STARTIE (0x00000001UL) +#define I2C_CR2_SLADDR0IE_POS (1U) +#define I2C_CR2_SLADDR0IE (0x00000002UL) +#define I2C_CR2_SLADDR1IE_POS (2U) +#define I2C_CR2_SLADDR1IE (0x00000004UL) +#define I2C_CR2_TENDIE_POS (3U) +#define I2C_CR2_TENDIE (0x00000008UL) +#define I2C_CR2_STOPIE_POS (4U) +#define I2C_CR2_STOPIE (0x00000010UL) +#define I2C_CR2_RFULLIE_POS (6U) +#define I2C_CR2_RFULLIE (0x00000040UL) +#define I2C_CR2_TEMPTYIE_POS (7U) +#define I2C_CR2_TEMPTYIE (0x00000080UL) +#define I2C_CR2_ARLOIE_POS (9U) +#define I2C_CR2_ARLOIE (0x00000200UL) +#define I2C_CR2_RFREQIE_POS (11U) +#define I2C_CR2_RFREQIE (0x00000800UL) +#define I2C_CR2_NACKIE_POS (12U) +#define I2C_CR2_NACKIE (0x00001000UL) +#define I2C_CR2_TMOUTIE_POS (14U) +#define I2C_CR2_TMOUTIE (0x00004000UL) +#define I2C_CR2_GENCALLIE_POS (20U) +#define I2C_CR2_GENCALLIE (0x00100000UL) +#define I2C_CR2_SMBDEFAULTIE_POS (21U) +#define I2C_CR2_SMBDEFAULTIE (0x00200000UL) +#define I2C_CR2_SMBHOSTIE_POS (22U) +#define I2C_CR2_SMBHOSTIE (0x00400000UL) +#define I2C_CR2_SMBALRTIE_POS (23U) +#define I2C_CR2_SMBALRTIE (0x00800000UL) + +/* Bit definition for I2C_CR3 register */ +#define I2C_CR3_TMOUTEN_POS (0U) +#define I2C_CR3_TMOUTEN (0x00000001UL) +#define I2C_CR3_LTMOUT_POS (1U) +#define I2C_CR3_LTMOUT (0x00000002UL) +#define I2C_CR3_HTMOUT_POS (2U) +#define I2C_CR3_HTMOUT (0x00000004UL) +#define I2C_CR3_FACKEN_POS (7U) +#define I2C_CR3_FACKEN (0x00000080UL) + +/* Bit definition for I2C_CR4 register */ +#define I2C_CR4_BUSWAIT_POS (10U) +#define I2C_CR4_BUSWAIT (0x00000400UL) +#define I2C_CR4_BUSFREECLREN_POS (12U) +#define I2C_CR4_BUSFREECLREN (0x00001000UL) + +/* Bit definition for I2C_SLR0 register */ +#define I2C_SLR0_SLADDR0_POS (0U) +#define I2C_SLR0_SLADDR0 (0x000003FFUL) +#define I2C_SLR0_SLADDR0EN_POS (12U) +#define I2C_SLR0_SLADDR0EN (0x00001000UL) +#define I2C_SLR0_ADDRMOD0_POS (15U) +#define I2C_SLR0_ADDRMOD0 (0x00008000UL) +#define I2C_SLR0_MSLADDR0_POS (16U) +#define I2C_SLR0_MSLADDR0 (0x03FF0000UL) +#define I2C_SLR0_MASKEN0_POS (26U) +#define I2C_SLR0_MASKEN0 (0x04000000UL) + +/* Bit definition for I2C_SLR1 register */ +#define I2C_SLR1_SLADDR1_POS (0U) +#define I2C_SLR1_SLADDR1 (0x000003FFUL) +#define I2C_SLR1_SLADDR1EN_POS (12U) +#define I2C_SLR1_SLADDR1EN (0x00001000UL) +#define I2C_SLR1_ADDRMOD1_POS (15U) +#define I2C_SLR1_ADDRMOD1 (0x00008000UL) +#define I2C_SLR1_MSLADDR1_POS (16U) +#define I2C_SLR1_MSLADDR1 (0x03FF0000UL) +#define I2C_SLR1_MASKEN1_POS (26U) +#define I2C_SLR1_MASKEN1 (0x04000000UL) + +/* Bit definition for I2C_SLTR register */ +#define I2C_SLTR_TOUTLOW_POS (0U) +#define I2C_SLTR_TOUTLOW (0x0000FFFFUL) +#define I2C_SLTR_TOUTHIGH_POS (16U) +#define I2C_SLTR_TOUTHIGH (0xFFFF0000UL) + +/* Bit definition for I2C_SR register */ +#define I2C_SR_STARTF_POS (0U) +#define I2C_SR_STARTF (0x00000001UL) +#define I2C_SR_SLADDR0F_POS (1U) +#define I2C_SR_SLADDR0F (0x00000002UL) +#define I2C_SR_SLADDR1F_POS (2U) +#define I2C_SR_SLADDR1F (0x00000004UL) +#define I2C_SR_TENDF_POS (3U) +#define I2C_SR_TENDF (0x00000008UL) +#define I2C_SR_STOPF_POS (4U) +#define I2C_SR_STOPF (0x00000010UL) +#define I2C_SR_RFULLF_POS (6U) +#define I2C_SR_RFULLF (0x00000040UL) +#define I2C_SR_TEMPTYF_POS (7U) +#define I2C_SR_TEMPTYF (0x00000080UL) +#define I2C_SR_ARLOF_POS (9U) +#define I2C_SR_ARLOF (0x00000200UL) +#define I2C_SR_ACKRF_POS (10U) +#define I2C_SR_ACKRF (0x00000400UL) +#define I2C_SR_NACKF_POS (12U) +#define I2C_SR_NACKF (0x00001000UL) +#define I2C_SR_TMOUTF_POS (14U) +#define I2C_SR_TMOUTF (0x00004000UL) +#define I2C_SR_MSL_POS (16U) +#define I2C_SR_MSL (0x00010000UL) +#define I2C_SR_BUSY_POS (17U) +#define I2C_SR_BUSY (0x00020000UL) +#define I2C_SR_TRA_POS (18U) +#define I2C_SR_TRA (0x00040000UL) +#define I2C_SR_GENCALLF_POS (20U) +#define I2C_SR_GENCALLF (0x00100000UL) +#define I2C_SR_SMBDEFAULTF_POS (21U) +#define I2C_SR_SMBDEFAULTF (0x00200000UL) +#define I2C_SR_SMBHOSTF_POS (22U) +#define I2C_SR_SMBHOSTF (0x00400000UL) +#define I2C_SR_SMBALRTF_POS (23U) +#define I2C_SR_SMBALRTF (0x00800000UL) +#define I2C_SR_TFEMPTY_POS (24U) +#define I2C_SR_TFEMPTY (0x01000000UL) +#define I2C_SR_TFFULL_POS (25U) +#define I2C_SR_TFFULL (0x02000000UL) +#define I2C_SR_RFEMPTY_POS (26U) +#define I2C_SR_RFEMPTY (0x04000000UL) +#define I2C_SR_RFFULL_POS (27U) +#define I2C_SR_RFFULL (0x08000000UL) +#define I2C_SR_TFST_POS (28U) +#define I2C_SR_TFST (0x30000000UL) +#define I2C_SR_TFST_0 (0x10000000UL) +#define I2C_SR_TFST_1 (0x20000000UL) +#define I2C_SR_RFREQ_POS (31U) +#define I2C_SR_RFREQ (0x80000000UL) + +/* Bit definition for I2C_CLR register */ +#define I2C_CLR_STARTFCLR_POS (0U) +#define I2C_CLR_STARTFCLR (0x00000001UL) +#define I2C_CLR_SLADDR0FCLR_POS (1U) +#define I2C_CLR_SLADDR0FCLR (0x00000002UL) +#define I2C_CLR_SLADDR1FCLR_POS (2U) +#define I2C_CLR_SLADDR1FCLR (0x00000004UL) +#define I2C_CLR_TENDFCLR_POS (3U) +#define I2C_CLR_TENDFCLR (0x00000008UL) +#define I2C_CLR_STOPFCLR_POS (4U) +#define I2C_CLR_STOPFCLR (0x00000010UL) +#define I2C_CLR_RFULLFCLR_POS (6U) +#define I2C_CLR_RFULLFCLR (0x00000040UL) +#define I2C_CLR_TEMPTYFCLR_POS (7U) +#define I2C_CLR_TEMPTYFCLR (0x00000080UL) +#define I2C_CLR_ARLOFCLR_POS (9U) +#define I2C_CLR_ARLOFCLR (0x00000200UL) +#define I2C_CLR_RFREQCLR_POS (10U) +#define I2C_CLR_RFREQCLR (0x00000400UL) +#define I2C_CLR_NACKFCLR_POS (12U) +#define I2C_CLR_NACKFCLR (0x00001000UL) +#define I2C_CLR_TMOUTFCLR_POS (14U) +#define I2C_CLR_TMOUTFCLR (0x00004000UL) +#define I2C_CLR_GENCALLFCLR_POS (20U) +#define I2C_CLR_GENCALLFCLR (0x00100000UL) +#define I2C_CLR_SMBDEFAULTFCLR_POS (21U) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000UL) +#define I2C_CLR_SMBHOSTFCLR_POS (22U) +#define I2C_CLR_SMBHOSTFCLR (0x00400000UL) +#define I2C_CLR_SMBALRTFCLR_POS (23U) +#define I2C_CLR_SMBALRTFCLR (0x00800000UL) + +/* Bit definition for I2C_DTR register */ +#define I2C_DTR_DT (0xFFU) + +/* Bit definition for I2C_DRR register */ +#define I2C_DRR_DR (0xFFU) + +/* Bit definition for I2C_CCR register */ +#define I2C_CCR_SLOWW_POS (0U) +#define I2C_CCR_SLOWW (0x000000FFUL) +#define I2C_CCR_SHIGHW_POS (8U) +#define I2C_CCR_SHIGHW (0x0000FF00UL) +#define I2C_CCR_FREQ_POS (16U) +#define I2C_CCR_FREQ (0x00070000UL) + +/* Bit definition for I2C_FLTR register */ +#define I2C_FLTR_DNF_POS (0U) +#define I2C_FLTR_DNF (0x00000003UL) +#define I2C_FLTR_DNFEN_POS (4U) +#define I2C_FLTR_DNFEN (0x00000010UL) +#define I2C_FLTR_ANFEN_POS (5U) +#define I2C_FLTR_ANFEN (0x00000020UL) + +/* Bit definition for I2C_FSTR register */ +#define I2C_FSTR_FEN_POS (0U) +#define I2C_FSTR_FEN (0x00000001UL) +#define I2C_FSTR_TFFLUSH_POS (1U) +#define I2C_FSTR_TFFLUSH (0x00000002UL) +#define I2C_FSTR_RFFLUSH_POS (2U) +#define I2C_FSTR_RFFLUSH (0x00000004UL) +#define I2C_FSTR_NACKTFFLUSH_POS (3U) +#define I2C_FSTR_NACKTFFLUSH (0x00000008UL) +#define I2C_FSTR_TFST_POS (4U) +#define I2C_FSTR_TFST (0x00000030UL) +#define I2C_FSTR_TFST_0 (0x00000010UL) +#define I2C_FSTR_TFST_1 (0x00000020UL) +#define I2C_FSTR_RFST_POS (6U) +#define I2C_FSTR_RFST (0x000000C0UL) +#define I2C_FSTR_RFST_0 (0x00000040UL) +#define I2C_FSTR_RFST_1 (0x00000080UL) + +/* Bit definition for I2C_SLVADDR register */ +#define I2C_SLVADDR_SLVADRR (0x000003FFUL) + +/******************************************************************************* + Bit definition for Peripheral ICG +*******************************************************************************/ +/* Bit definition for ICG_ICG0 register */ +#define ICG_ICG0_SWDTAUTS_POS (0U) +#define ICG_ICG0_SWDTAUTS (0x00000001UL) +#define ICG_ICG0_SWDTITS_POS (1U) +#define ICG_ICG0_SWDTITS (0x00000002UL) +#define ICG_ICG0_SWDTPERI_POS (2U) +#define ICG_ICG0_SWDTPERI (0x0000000CUL) +#define ICG_ICG0_SWDTPERI_0 (0x00000004UL) +#define ICG_ICG0_SWDTPERI_1 (0x00000008UL) +#define ICG_ICG0_SWDTCKS_POS (4U) +#define ICG_ICG0_SWDTCKS (0x000000F0UL) +#define ICG_ICG0_SWDTWDPT_POS (8U) +#define ICG_ICG0_SWDTWDPT (0x00000F00UL) +#define ICG_ICG0_SWDTSLPOFF_POS (12U) +#define ICG_ICG0_SWDTSLPOFF (0x00001000UL) +#define ICG_ICG0_WDTAUTS_POS (16U) +#define ICG_ICG0_WDTAUTS (0x00010000UL) +#define ICG_ICG0_WDTITS_POS (17U) +#define ICG_ICG0_WDTITS (0x00020000UL) +#define ICG_ICG0_WDTPERI_POS (18U) +#define ICG_ICG0_WDTPERI (0x000C0000UL) +#define ICG_ICG0_WDTPERI_0 (0x00040000UL) +#define ICG_ICG0_WDTPERI_1 (0x00080000UL) +#define ICG_ICG0_WDTCKS_POS (20U) +#define ICG_ICG0_WDTCKS (0x00F00000UL) +#define ICG_ICG0_WDTWDPT_POS (24U) +#define ICG_ICG0_WDTWDPT (0x0F000000UL) +#define ICG_ICG0_WDTSLPOFF_POS (28U) +#define ICG_ICG0_WDTSLPOFF (0x10000000UL) + +/* Bit definition for ICG_ICG1 register */ +#define ICG_ICG1_HRCFREQSEL_POS (0U) +#define ICG_ICG1_HRCFREQSEL (0x00000001UL) +#define ICG_ICG1_HRCSTOP_POS (8U) +#define ICG_ICG1_HRCSTOP (0x00000100UL) +#define ICG_ICG1_BOR_LEV_POS (16U) +#define ICG_ICG1_BOR_LEV (0x00030000UL) +#define ICG_ICG1_BOR_LEV_0 (0x00010000UL) +#define ICG_ICG1_BOR_LEV_1 (0x00020000UL) +#define ICG_ICG1_BORDIS_POS (18U) +#define ICG_ICG1_BORDIS (0x00040000UL) + +/* Bit definition for ICG_ICG3 register */ +#define ICG_ICG3_DBUSPRT (0x0000FFFFUL) + +/* Bit definition for ICG_ICG4 register */ +#define ICG_ICG4 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral INTC +*******************************************************************************/ +/* Bit definition for INTC_NMIER register */ +#define INTC_NMIER_SWDTEN_POS (1U) +#define INTC_NMIER_SWDTEN (0x00000002UL) +#define INTC_NMIER_PVD1EN_POS (2U) +#define INTC_NMIER_PVD1EN (0x00000004UL) +#define INTC_NMIER_PVD2EN_POS (3U) +#define INTC_NMIER_PVD2EN (0x00000008UL) +#define INTC_NMIER_XTALSTPEN_POS (5U) +#define INTC_NMIER_XTALSTPEN (0x00000020UL) +#define INTC_NMIER_RPARERREN_POS (8U) +#define INTC_NMIER_RPARERREN (0x00000100UL) +#define INTC_NMIER_RECCERREN_POS (9U) +#define INTC_NMIER_RECCERREN (0x00000200UL) +#define INTC_NMIER_BUSERREN_POS (10U) +#define INTC_NMIER_BUSERREN (0x00000400UL) +#define INTC_NMIER_WDTEN_POS (11U) +#define INTC_NMIER_WDTEN (0x00000800UL) + +/* Bit definition for INTC_NMIFR register */ +#define INTC_NMIFR_SWDTF_POS (1U) +#define INTC_NMIFR_SWDTF (0x00000002UL) +#define INTC_NMIFR_PVD1F_POS (2U) +#define INTC_NMIFR_PVD1F (0x00000004UL) +#define INTC_NMIFR_PVD2F_POS (3U) +#define INTC_NMIFR_PVD2F (0x00000008UL) +#define INTC_NMIFR_XTALSTPF_POS (5U) +#define INTC_NMIFR_XTALSTPF (0x00000020UL) +#define INTC_NMIFR_RPARERRF_POS (8U) +#define INTC_NMIFR_RPARERRF (0x00000100UL) +#define INTC_NMIFR_RECCERRF_POS (9U) +#define INTC_NMIFR_RECCERRF (0x00000200UL) +#define INTC_NMIFR_BUSERRF_POS (10U) +#define INTC_NMIFR_BUSERRF (0x00000400UL) +#define INTC_NMIFR_WDTF_POS (11U) +#define INTC_NMIFR_WDTF (0x00000800UL) + +/* Bit definition for INTC_NMIFCR register */ +#define INTC_NMIFCR_SWDTFCLR_POS (1U) +#define INTC_NMIFCR_SWDTFCLR (0x00000002UL) +#define INTC_NMIFCR_PVD1FCLR_POS (2U) +#define INTC_NMIFCR_PVD1FCLR (0x00000004UL) +#define INTC_NMIFCR_PVD2FCLR_POS (3U) +#define INTC_NMIFCR_PVD2FCLR (0x00000008UL) +#define INTC_NMIFCR_XTALSTPFCLR_POS (5U) +#define INTC_NMIFCR_XTALSTPFCLR (0x00000020UL) +#define INTC_NMIFCR_RPARERRFCLR_POS (8U) +#define INTC_NMIFCR_RPARERRFCLR (0x00000100UL) +#define INTC_NMIFCR_RECCERRFCLR_POS (9U) +#define INTC_NMIFCR_RECCERRFCLR (0x00000200UL) +#define INTC_NMIFCR_BUSERRFCLR_POS (10U) +#define INTC_NMIFCR_BUSERRFCLR (0x00000400UL) +#define INTC_NMIFCR_WDTFCLR_POS (11U) +#define INTC_NMIFCR_WDTFCLR (0x00000800UL) + +/* Bit definition for INTC_EIRQCR register */ +#define INTC_EIRQCR_EIRQTRG_POS (0U) +#define INTC_EIRQCR_EIRQTRG (0x00000003UL) +#define INTC_EIRQCR_EIRQTRG_0 (0x00000001UL) +#define INTC_EIRQCR_EIRQTRG_1 (0x00000002UL) +#define INTC_EIRQCR_EISMPCLK_POS (4U) +#define INTC_EIRQCR_EISMPCLK (0x00000030UL) +#define INTC_EIRQCR_EISMPCLK_0 (0x00000010UL) +#define INTC_EIRQCR_EISMPCLK_1 (0x00000020UL) +#define INTC_EIRQCR_EFEN_POS (7U) +#define INTC_EIRQCR_EFEN (0x00000080UL) +#define INTC_EIRQCR_NOCSEL_POS (12U) +#define INTC_EIRQCR_NOCSEL (0x00003000UL) +#define INTC_EIRQCR_NOCSEL_0 (0x00001000UL) +#define INTC_EIRQCR_NOCSEL_1 (0x00002000UL) +#define INTC_EIRQCR_NOCEN_POS (15U) +#define INTC_EIRQCR_NOCEN (0x00008000UL) + +/* Bit definition for INTC_WKEN register */ +#define INTC_WKEN_EIRQWKEN_POS (0U) +#define INTC_WKEN_EIRQWKEN (0x0000FFFFUL) +#define INTC_WKEN_EIRQWKEN_0 (0x00000001UL) +#define INTC_WKEN_EIRQWKEN_1 (0x00000002UL) +#define INTC_WKEN_EIRQWKEN_2 (0x00000004UL) +#define INTC_WKEN_EIRQWKEN_3 (0x00000008UL) +#define INTC_WKEN_EIRQWKEN_4 (0x00000010UL) +#define INTC_WKEN_EIRQWKEN_5 (0x00000020UL) +#define INTC_WKEN_EIRQWKEN_6 (0x00000040UL) +#define INTC_WKEN_EIRQWKEN_7 (0x00000080UL) +#define INTC_WKEN_EIRQWKEN_8 (0x00000100UL) +#define INTC_WKEN_EIRQWKEN_9 (0x00000200UL) +#define INTC_WKEN_EIRQWKEN_10 (0x00000400UL) +#define INTC_WKEN_EIRQWKEN_11 (0x00000800UL) +#define INTC_WKEN_EIRQWKEN_12 (0x00001000UL) +#define INTC_WKEN_EIRQWKEN_13 (0x00002000UL) +#define INTC_WKEN_EIRQWKEN_14 (0x00004000UL) +#define INTC_WKEN_EIRQWKEN_15 (0x00008000UL) +#define INTC_WKEN_SWDTWKEN_POS (16U) +#define INTC_WKEN_SWDTWKEN (0x00010000UL) +#define INTC_WKEN_CMP1WKEN_POS (19U) +#define INTC_WKEN_CMP1WKEN (0x00080000UL) +#define INTC_WKEN_WKTMWKEN_POS (20U) +#define INTC_WKEN_WKTMWKEN (0x00100000UL) +#define INTC_WKEN_RTCALMWKEN_POS (21U) +#define INTC_WKEN_RTCALMWKEN (0x00200000UL) +#define INTC_WKEN_RTCPRDWKEN_POS (22U) +#define INTC_WKEN_RTCPRDWKEN (0x00400000UL) +#define INTC_WKEN_TMR0CMPWKEN_POS (23U) +#define INTC_WKEN_TMR0CMPWKEN (0x00800000UL) +#define INTC_WKEN_RXWKEN_POS (26U) +#define INTC_WKEN_RXWKEN (0x04000000UL) +#define INTC_WKEN_CMP2WKEN_POS (29U) +#define INTC_WKEN_CMP2WKEN (0x20000000UL) +#define INTC_WKEN_CMP3WKEN_POS (30U) +#define INTC_WKEN_CMP3WKEN (0x40000000UL) +#define INTC_WKEN_CMP4WKEN_POS (31U) +#define INTC_WKEN_CMP4WKEN (0x80000000UL) + +/* Bit definition for INTC_EIFR register */ +#define INTC_EIFR_EIF0_POS (0U) +#define INTC_EIFR_EIF0 (0x00000001UL) +#define INTC_EIFR_EIF1_POS (1U) +#define INTC_EIFR_EIF1 (0x00000002UL) +#define INTC_EIFR_EIF2_POS (2U) +#define INTC_EIFR_EIF2 (0x00000004UL) +#define INTC_EIFR_EIF3_POS (3U) +#define INTC_EIFR_EIF3 (0x00000008UL) +#define INTC_EIFR_EIF4_POS (4U) +#define INTC_EIFR_EIF4 (0x00000010UL) +#define INTC_EIFR_EIF5_POS (5U) +#define INTC_EIFR_EIF5 (0x00000020UL) +#define INTC_EIFR_EIF6_POS (6U) +#define INTC_EIFR_EIF6 (0x00000040UL) +#define INTC_EIFR_EIF7_POS (7U) +#define INTC_EIFR_EIF7 (0x00000080UL) +#define INTC_EIFR_EIF8_POS (8U) +#define INTC_EIFR_EIF8 (0x00000100UL) +#define INTC_EIFR_EIF9_POS (9U) +#define INTC_EIFR_EIF9 (0x00000200UL) +#define INTC_EIFR_EIF10_POS (10U) +#define INTC_EIFR_EIF10 (0x00000400UL) +#define INTC_EIFR_EIF11_POS (11U) +#define INTC_EIFR_EIF11 (0x00000800UL) +#define INTC_EIFR_EIF12_POS (12U) +#define INTC_EIFR_EIF12 (0x00001000UL) +#define INTC_EIFR_EIF13_POS (13U) +#define INTC_EIFR_EIF13 (0x00002000UL) +#define INTC_EIFR_EIF14_POS (14U) +#define INTC_EIFR_EIF14 (0x00004000UL) +#define INTC_EIFR_EIF15_POS (15U) +#define INTC_EIFR_EIF15 (0x00008000UL) + +/* Bit definition for INTC_EIFCR register */ +#define INTC_EIFCR_EIFCLR0_POS (0U) +#define INTC_EIFCR_EIFCLR0 (0x00000001UL) +#define INTC_EIFCR_EIFCLR1_POS (1U) +#define INTC_EIFCR_EIFCLR1 (0x00000002UL) +#define INTC_EIFCR_EIFCLR2_POS (2U) +#define INTC_EIFCR_EIFCLR2 (0x00000004UL) +#define INTC_EIFCR_EIFCLR3_POS (3U) +#define INTC_EIFCR_EIFCLR3 (0x00000008UL) +#define INTC_EIFCR_EIFCLR4_POS (4U) +#define INTC_EIFCR_EIFCLR4 (0x00000010UL) +#define INTC_EIFCR_EIFCLR5_POS (5U) +#define INTC_EIFCR_EIFCLR5 (0x00000020UL) +#define INTC_EIFCR_EIFCLR6_POS (6U) +#define INTC_EIFCR_EIFCLR6 (0x00000040UL) +#define INTC_EIFCR_EIFCLR7_POS (7U) +#define INTC_EIFCR_EIFCLR7 (0x00000080UL) +#define INTC_EIFCR_EIFCLR8_POS (8U) +#define INTC_EIFCR_EIFCLR8 (0x00000100UL) +#define INTC_EIFCR_EIFCLR9_POS (9U) +#define INTC_EIFCR_EIFCLR9 (0x00000200UL) +#define INTC_EIFCR_EIFCLR10_POS (10U) +#define INTC_EIFCR_EIFCLR10 (0x00000400UL) +#define INTC_EIFCR_EIFCLR11_POS (11U) +#define INTC_EIFCR_EIFCLR11 (0x00000800UL) +#define INTC_EIFCR_EIFCLR12_POS (12U) +#define INTC_EIFCR_EIFCLR12 (0x00001000UL) +#define INTC_EIFCR_EIFCLR13_POS (13U) +#define INTC_EIFCR_EIFCLR13 (0x00002000UL) +#define INTC_EIFCR_EIFCLR14_POS (14U) +#define INTC_EIFCR_EIFCLR14 (0x00004000UL) +#define INTC_EIFCR_EIFCLR15_POS (15U) +#define INTC_EIFCR_EIFCLR15 (0x00008000UL) + +/* Bit definition for INTC_INTSEL register */ +#define INTC_INTSEL_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_INTEN register */ +#define INTC_INTEN_INTEN (0xFFFFFFFFUL) +#define INTC_INTEN_INTEN_0 (0x00000001UL) +#define INTC_INTEN_INTEN_1 (0x00000002UL) +#define INTC_INTEN_INTEN_2 (0x00000004UL) +#define INTC_INTEN_INTEN_3 (0x00000008UL) +#define INTC_INTEN_INTEN_4 (0x00000010UL) +#define INTC_INTEN_INTEN_5 (0x00000020UL) +#define INTC_INTEN_INTEN_6 (0x00000040UL) +#define INTC_INTEN_INTEN_7 (0x00000080UL) +#define INTC_INTEN_INTEN_8 (0x00000100UL) +#define INTC_INTEN_INTEN_9 (0x00000200UL) +#define INTC_INTEN_INTEN_10 (0x00000400UL) +#define INTC_INTEN_INTEN_11 (0x00000800UL) +#define INTC_INTEN_INTEN_12 (0x00001000UL) +#define INTC_INTEN_INTEN_13 (0x00002000UL) +#define INTC_INTEN_INTEN_14 (0x00004000UL) +#define INTC_INTEN_INTEN_15 (0x00008000UL) +#define INTC_INTEN_INTEN_16 (0x00010000UL) +#define INTC_INTEN_INTEN_17 (0x00020000UL) +#define INTC_INTEN_INTEN_18 (0x00040000UL) +#define INTC_INTEN_INTEN_19 (0x00080000UL) +#define INTC_INTEN_INTEN_20 (0x00100000UL) +#define INTC_INTEN_INTEN_21 (0x00200000UL) +#define INTC_INTEN_INTEN_22 (0x00400000UL) +#define INTC_INTEN_INTEN_23 (0x00800000UL) +#define INTC_INTEN_INTEN_24 (0x01000000UL) +#define INTC_INTEN_INTEN_25 (0x02000000UL) +#define INTC_INTEN_INTEN_26 (0x04000000UL) +#define INTC_INTEN_INTEN_27 (0x08000000UL) +#define INTC_INTEN_INTEN_28 (0x10000000UL) +#define INTC_INTEN_INTEN_29 (0x20000000UL) +#define INTC_INTEN_INTEN_30 (0x40000000UL) +#define INTC_INTEN_INTEN_31 (0x80000000UL) + +/* Bit definition for INTC_SWIER register */ +#define INTC_SWIER_SWIE0_POS (0U) +#define INTC_SWIER_SWIE0 (0x00000001UL) +#define INTC_SWIER_SWIE1_POS (1U) +#define INTC_SWIER_SWIE1 (0x00000002UL) +#define INTC_SWIER_SWIE2_POS (2U) +#define INTC_SWIER_SWIE2 (0x00000004UL) +#define INTC_SWIER_SWIE3_POS (3U) +#define INTC_SWIER_SWIE3 (0x00000008UL) +#define INTC_SWIER_SWIE4_POS (4U) +#define INTC_SWIER_SWIE4 (0x00000010UL) +#define INTC_SWIER_SWIE5_POS (5U) +#define INTC_SWIER_SWIE5 (0x00000020UL) +#define INTC_SWIER_SWIE6_POS (6U) +#define INTC_SWIER_SWIE6 (0x00000040UL) +#define INTC_SWIER_SWIE7_POS (7U) +#define INTC_SWIER_SWIE7 (0x00000080UL) +#define INTC_SWIER_SWIE8_POS (8U) +#define INTC_SWIER_SWIE8 (0x00000100UL) +#define INTC_SWIER_SWIE9_POS (9U) +#define INTC_SWIER_SWIE9 (0x00000200UL) +#define INTC_SWIER_SWIE10_POS (10U) +#define INTC_SWIER_SWIE10 (0x00000400UL) +#define INTC_SWIER_SWIE11_POS (11U) +#define INTC_SWIER_SWIE11 (0x00000800UL) +#define INTC_SWIER_SWIE12_POS (12U) +#define INTC_SWIER_SWIE12 (0x00001000UL) +#define INTC_SWIER_SWIE13_POS (13U) +#define INTC_SWIER_SWIE13 (0x00002000UL) +#define INTC_SWIER_SWIE14_POS (14U) +#define INTC_SWIER_SWIE14 (0x00004000UL) +#define INTC_SWIER_SWIE15_POS (15U) +#define INTC_SWIER_SWIE15 (0x00008000UL) +#define INTC_SWIER_SWIE16_POS (16U) +#define INTC_SWIER_SWIE16 (0x00010000UL) +#define INTC_SWIER_SWIE17_POS (17U) +#define INTC_SWIER_SWIE17 (0x00020000UL) +#define INTC_SWIER_SWIE18_POS (18U) +#define INTC_SWIER_SWIE18 (0x00040000UL) +#define INTC_SWIER_SWIE19_POS (19U) +#define INTC_SWIER_SWIE19 (0x00080000UL) +#define INTC_SWIER_SWIE20_POS (20U) +#define INTC_SWIER_SWIE20 (0x00100000UL) +#define INTC_SWIER_SWIE21_POS (21U) +#define INTC_SWIER_SWIE21 (0x00200000UL) +#define INTC_SWIER_SWIE22_POS (22U) +#define INTC_SWIER_SWIE22 (0x00400000UL) +#define INTC_SWIER_SWIE23_POS (23U) +#define INTC_SWIER_SWIE23 (0x00800000UL) +#define INTC_SWIER_SWIE24_POS (24U) +#define INTC_SWIER_SWIE24 (0x01000000UL) +#define INTC_SWIER_SWIE25_POS (25U) +#define INTC_SWIER_SWIE25 (0x02000000UL) +#define INTC_SWIER_SWIE26_POS (26U) +#define INTC_SWIER_SWIE26 (0x04000000UL) +#define INTC_SWIER_SWIE27_POS (27U) +#define INTC_SWIER_SWIE27 (0x08000000UL) +#define INTC_SWIER_SWIE28_POS (28U) +#define INTC_SWIER_SWIE28 (0x10000000UL) +#define INTC_SWIER_SWIE29_POS (29U) +#define INTC_SWIER_SWIE29 (0x20000000UL) +#define INTC_SWIER_SWIE30_POS (30U) +#define INTC_SWIER_SWIE30 (0x40000000UL) +#define INTC_SWIER_SWIE31_POS (31U) +#define INTC_SWIER_SWIE31 (0x80000000UL) + +/* Bit definition for INTC_EVTER register */ +#define INTC_EVTER_EVTE0_POS (0U) +#define INTC_EVTER_EVTE0 (0x00000001UL) +#define INTC_EVTER_EVTE1_POS (1U) +#define INTC_EVTER_EVTE1 (0x00000002UL) +#define INTC_EVTER_EVTE2_POS (2U) +#define INTC_EVTER_EVTE2 (0x00000004UL) +#define INTC_EVTER_EVTE3_POS (3U) +#define INTC_EVTER_EVTE3 (0x00000008UL) +#define INTC_EVTER_EVTE4_POS (4U) +#define INTC_EVTER_EVTE4 (0x00000010UL) +#define INTC_EVTER_EVTE5_POS (5U) +#define INTC_EVTER_EVTE5 (0x00000020UL) +#define INTC_EVTER_EVTE6_POS (6U) +#define INTC_EVTER_EVTE6 (0x00000040UL) +#define INTC_EVTER_EVTE7_POS (7U) +#define INTC_EVTER_EVTE7 (0x00000080UL) +#define INTC_EVTER_EVTE8_POS (8U) +#define INTC_EVTER_EVTE8 (0x00000100UL) +#define INTC_EVTER_EVTE9_POS (9U) +#define INTC_EVTER_EVTE9 (0x00000200UL) +#define INTC_EVTER_EVTE10_POS (10U) +#define INTC_EVTER_EVTE10 (0x00000400UL) +#define INTC_EVTER_EVTE11_POS (11U) +#define INTC_EVTER_EVTE11 (0x00000800UL) +#define INTC_EVTER_EVTE12_POS (12U) +#define INTC_EVTER_EVTE12 (0x00001000UL) +#define INTC_EVTER_EVTE13_POS (13U) +#define INTC_EVTER_EVTE13 (0x00002000UL) +#define INTC_EVTER_EVTE14_POS (14U) +#define INTC_EVTER_EVTE14 (0x00004000UL) +#define INTC_EVTER_EVTE15_POS (15U) +#define INTC_EVTER_EVTE15 (0x00008000UL) +#define INTC_EVTER_EVTE16_POS (16U) +#define INTC_EVTER_EVTE16 (0x00010000UL) +#define INTC_EVTER_EVTE17_POS (17U) +#define INTC_EVTER_EVTE17 (0x00020000UL) +#define INTC_EVTER_EVTE18_POS (18U) +#define INTC_EVTER_EVTE18 (0x00040000UL) +#define INTC_EVTER_EVTE19_POS (19U) +#define INTC_EVTER_EVTE19 (0x00080000UL) +#define INTC_EVTER_EVTE20_POS (20U) +#define INTC_EVTER_EVTE20 (0x00100000UL) +#define INTC_EVTER_EVTE21_POS (21U) +#define INTC_EVTER_EVTE21 (0x00200000UL) +#define INTC_EVTER_EVTE22_POS (22U) +#define INTC_EVTER_EVTE22 (0x00400000UL) +#define INTC_EVTER_EVTE23_POS (23U) +#define INTC_EVTER_EVTE23 (0x00800000UL) +#define INTC_EVTER_EVTE24_POS (24U) +#define INTC_EVTER_EVTE24 (0x01000000UL) +#define INTC_EVTER_EVTE25_POS (25U) +#define INTC_EVTER_EVTE25 (0x02000000UL) +#define INTC_EVTER_EVTE26_POS (26U) +#define INTC_EVTER_EVTE26 (0x04000000UL) +#define INTC_EVTER_EVTE27_POS (27U) +#define INTC_EVTER_EVTE27 (0x08000000UL) +#define INTC_EVTER_EVTE28_POS (28U) +#define INTC_EVTER_EVTE28 (0x10000000UL) +#define INTC_EVTER_EVTE29_POS (29U) +#define INTC_EVTER_EVTE29 (0x20000000UL) +#define INTC_EVTER_EVTE30_POS (30U) +#define INTC_EVTER_EVTE30 (0x40000000UL) +#define INTC_EVTER_EVTE31_POS (31U) +#define INTC_EVTER_EVTE31 (0x80000000UL) + +/* Bit definition for INTC_IER register */ +#define INTC_IER_IEN0_POS (0U) +#define INTC_IER_IEN0 (0x00000001UL) +#define INTC_IER_IEN1_POS (1U) +#define INTC_IER_IEN1 (0x00000002UL) +#define INTC_IER_IEN2_POS (2U) +#define INTC_IER_IEN2 (0x00000004UL) +#define INTC_IER_IEN3_POS (3U) +#define INTC_IER_IEN3 (0x00000008UL) +#define INTC_IER_IEN4_POS (4U) +#define INTC_IER_IEN4 (0x00000010UL) +#define INTC_IER_IEN5_POS (5U) +#define INTC_IER_IEN5 (0x00000020UL) +#define INTC_IER_IEN6_POS (6U) +#define INTC_IER_IEN6 (0x00000040UL) +#define INTC_IER_IEN7_POS (7U) +#define INTC_IER_IEN7 (0x00000080UL) +#define INTC_IER_IEN8_POS (8U) +#define INTC_IER_IEN8 (0x00000100UL) +#define INTC_IER_IEN9_POS (9U) +#define INTC_IER_IEN9 (0x00000200UL) +#define INTC_IER_IEN10_POS (10U) +#define INTC_IER_IEN10 (0x00000400UL) +#define INTC_IER_IEN11_POS (11U) +#define INTC_IER_IEN11 (0x00000800UL) +#define INTC_IER_IEN12_POS (12U) +#define INTC_IER_IEN12 (0x00001000UL) +#define INTC_IER_IEN13_POS (13U) +#define INTC_IER_IEN13 (0x00002000UL) +#define INTC_IER_IEN14_POS (14U) +#define INTC_IER_IEN14 (0x00004000UL) +#define INTC_IER_IEN15_POS (15U) +#define INTC_IER_IEN15 (0x00008000UL) +#define INTC_IER_IEN16_POS (16U) +#define INTC_IER_IEN16 (0x00010000UL) +#define INTC_IER_IEN17_POS (17U) +#define INTC_IER_IEN17 (0x00020000UL) +#define INTC_IER_IEN18_POS (18U) +#define INTC_IER_IEN18 (0x00040000UL) +#define INTC_IER_IEN19_POS (19U) +#define INTC_IER_IEN19 (0x00080000UL) +#define INTC_IER_IEN20_POS (20U) +#define INTC_IER_IEN20 (0x00100000UL) +#define INTC_IER_IEN21_POS (21U) +#define INTC_IER_IEN21 (0x00200000UL) +#define INTC_IER_IEN22_POS (22U) +#define INTC_IER_IEN22 (0x00400000UL) +#define INTC_IER_IEN23_POS (23U) +#define INTC_IER_IEN23 (0x00800000UL) +#define INTC_IER_IEN24_POS (24U) +#define INTC_IER_IEN24 (0x01000000UL) +#define INTC_IER_IEN25_POS (25U) +#define INTC_IER_IEN25 (0x02000000UL) +#define INTC_IER_IEN26_POS (26U) +#define INTC_IER_IEN26 (0x04000000UL) +#define INTC_IER_IEN27_POS (27U) +#define INTC_IER_IEN27 (0x08000000UL) +#define INTC_IER_IEN28_POS (28U) +#define INTC_IER_IEN28 (0x10000000UL) +#define INTC_IER_IEN29_POS (29U) +#define INTC_IER_IEN29 (0x20000000UL) +#define INTC_IER_IEN30_POS (30U) +#define INTC_IER_IEN30 (0x40000000UL) +#define INTC_IER_IEN31_POS (31U) +#define INTC_IER_IEN31 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral KEYSCAN +*******************************************************************************/ +/* Bit definition for KEYSCAN_SCR register */ +#define KEYSCAN_SCR_KEYINSEL_POS (0U) +#define KEYSCAN_SCR_KEYINSEL (0x0000FFFFUL) +#define KEYSCAN_SCR_KEYOUTSEL_POS (16U) +#define KEYSCAN_SCR_KEYOUTSEL (0x00070000UL) +#define KEYSCAN_SCR_CKSEL_POS (20U) +#define KEYSCAN_SCR_CKSEL (0x00300000UL) +#define KEYSCAN_SCR_CKSEL_0 (0x00100000UL) +#define KEYSCAN_SCR_CKSEL_1 (0x00200000UL) +#define KEYSCAN_SCR_T_LLEVEL_POS (24U) +#define KEYSCAN_SCR_T_LLEVEL (0x1F000000UL) +#define KEYSCAN_SCR_T_HIZ_POS (29U) +#define KEYSCAN_SCR_T_HIZ (0xE0000000UL) + +/* Bit definition for KEYSCAN_SER register */ +#define KEYSCAN_SER_SEN (0x00000001UL) + +/* Bit definition for KEYSCAN_SSR register */ +#define KEYSCAN_SSR_INDEX (0x00000007UL) + +/******************************************************************************* + Bit definition for Peripheral MCAN +*******************************************************************************/ +/* Bit definition for MCAN_ENDN register */ +#define MCAN_ENDN (0xFFFFFFFFUL) + +/* Bit definition for MCAN_DBTP register */ +#define MCAN_DBTP_DSJW_POS (0U) +#define MCAN_DBTP_DSJW (0x0000000FUL) +#define MCAN_DBTP_DTSEG2_POS (4U) +#define MCAN_DBTP_DTSEG2 (0x000000F0UL) +#define MCAN_DBTP_DTSEG1_POS (8U) +#define MCAN_DBTP_DTSEG1 (0x00001F00UL) +#define MCAN_DBTP_DBRP_POS (16U) +#define MCAN_DBTP_DBRP (0x001F0000UL) +#define MCAN_DBTP_TDC_POS (23U) +#define MCAN_DBTP_TDC (0x00800000UL) + +/* Bit definition for MCAN_TEST register */ +#define MCAN_TEST_LBCK_POS (4U) +#define MCAN_TEST_LBCK (0x00000010UL) +#define MCAN_TEST_TX_POS (5U) +#define MCAN_TEST_TX (0x00000060UL) +#define MCAN_TEST_TX_0 (0x00000020UL) +#define MCAN_TEST_TX_1 (0x00000040UL) +#define MCAN_TEST_RX_POS (7U) +#define MCAN_TEST_RX (0x00000080UL) +#define MCAN_TEST_TXBNP_POS (8U) +#define MCAN_TEST_TXBNP (0x00001F00UL) +#define MCAN_TEST_PVAL_POS (13U) +#define MCAN_TEST_PVAL (0x00002000UL) +#define MCAN_TEST_TXBNS_POS (16U) +#define MCAN_TEST_TXBNS (0x001F0000UL) +#define MCAN_TEST_SVAL_POS (21U) +#define MCAN_TEST_SVAL (0x00200000UL) + +/* Bit definition for MCAN_RWD register */ +#define MCAN_RWD_WDC_POS (0U) +#define MCAN_RWD_WDC (0x000000FFUL) +#define MCAN_RWD_WDV_POS (8U) +#define MCAN_RWD_WDV (0x0000FF00UL) + +/* Bit definition for MCAN_CCCR register */ +#define MCAN_CCCR_INIT_POS (0U) +#define MCAN_CCCR_INIT (0x00000001UL) +#define MCAN_CCCR_CCE_POS (1U) +#define MCAN_CCCR_CCE (0x00000002UL) +#define MCAN_CCCR_ASM_POS (2U) +#define MCAN_CCCR_ASM (0x00000004UL) +#define MCAN_CCCR_CSA_POS (3U) +#define MCAN_CCCR_CSA (0x00000008UL) +#define MCAN_CCCR_CSR_POS (4U) +#define MCAN_CCCR_CSR (0x00000010UL) +#define MCAN_CCCR_MON_POS (5U) +#define MCAN_CCCR_MON (0x00000020UL) +#define MCAN_CCCR_DAR_POS (6U) +#define MCAN_CCCR_DAR (0x00000040UL) +#define MCAN_CCCR_TEST_POS (7U) +#define MCAN_CCCR_TEST (0x00000080UL) +#define MCAN_CCCR_FDOE_POS (8U) +#define MCAN_CCCR_FDOE (0x00000100UL) +#define MCAN_CCCR_BRSE_POS (9U) +#define MCAN_CCCR_BRSE (0x00000200UL) +#define MCAN_CCCR_UTSU_POS (10U) +#define MCAN_CCCR_UTSU (0x00000400UL) +#define MCAN_CCCR_WMM_POS (11U) +#define MCAN_CCCR_WMM (0x00000800UL) +#define MCAN_CCCR_PXHD_POS (12U) +#define MCAN_CCCR_PXHD (0x00001000UL) +#define MCAN_CCCR_EFBI_POS (13U) +#define MCAN_CCCR_EFBI (0x00002000UL) +#define MCAN_CCCR_TXP_POS (14U) +#define MCAN_CCCR_TXP (0x00004000UL) +#define MCAN_CCCR_NISO_POS (15U) +#define MCAN_CCCR_NISO (0x00008000UL) + +/* Bit definition for MCAN_NBTP register */ +#define MCAN_NBTP_NTSEG2_POS (0U) +#define MCAN_NBTP_NTSEG2 (0x0000007FUL) +#define MCAN_NBTP_NTSEG1_POS (8U) +#define MCAN_NBTP_NTSEG1 (0x0000FF00UL) +#define MCAN_NBTP_NBRP_POS (16U) +#define MCAN_NBTP_NBRP (0x01FF0000UL) +#define MCAN_NBTP_NSJW_POS (25U) +#define MCAN_NBTP_NSJW (0xFE000000UL) + +/* Bit definition for MCAN_TSCC register */ +#define MCAN_TSCC_TSS_POS (0U) +#define MCAN_TSCC_TSS (0x00000003UL) +#define MCAN_TSCC_TSS_0 (0x00000001UL) +#define MCAN_TSCC_TSS_1 (0x00000002UL) +#define MCAN_TSCC_TCP_POS (16U) +#define MCAN_TSCC_TCP (0x000F0000UL) + +/* Bit definition for MCAN_TSCV register */ +#define MCAN_TSCV_TSC (0x0000FFFFUL) + +/* Bit definition for MCAN_TOCC register */ +#define MCAN_TOCC_ETOC_POS (0U) +#define MCAN_TOCC_ETOC (0x00000001UL) +#define MCAN_TOCC_TOS_POS (1U) +#define MCAN_TOCC_TOS (0x00000006UL) +#define MCAN_TOCC_TOS_0 (0x00000002UL) +#define MCAN_TOCC_TOS_1 (0x00000004UL) +#define MCAN_TOCC_TOP_POS (16U) +#define MCAN_TOCC_TOP (0xFFFF0000UL) + +/* Bit definition for MCAN_TOCV register */ +#define MCAN_TOCV_TOC (0x0000FFFFUL) + +/* Bit definition for MCAN_ECR register */ +#define MCAN_ECR_TEC_POS (0U) +#define MCAN_ECR_TEC (0x000000FFUL) +#define MCAN_ECR_REC_POS (8U) +#define MCAN_ECR_REC (0x00007F00UL) +#define MCAN_ECR_RP_POS (15U) +#define MCAN_ECR_RP (0x00008000UL) +#define MCAN_ECR_CEL_POS (16U) +#define MCAN_ECR_CEL (0x00FF0000UL) + +/* Bit definition for MCAN_PSR register */ +#define MCAN_PSR_LEC_POS (0U) +#define MCAN_PSR_LEC (0x00000007UL) +#define MCAN_PSR_ACT_POS (3U) +#define MCAN_PSR_ACT (0x00000018UL) +#define MCAN_PSR_ACT_0 (0x00000008UL) +#define MCAN_PSR_ACT_1 (0x00000010UL) +#define MCAN_PSR_EP_POS (5U) +#define MCAN_PSR_EP (0x00000020UL) +#define MCAN_PSR_EW_POS (6U) +#define MCAN_PSR_EW (0x00000040UL) +#define MCAN_PSR_BO_POS (7U) +#define MCAN_PSR_BO (0x00000080UL) +#define MCAN_PSR_DLEC_POS (8U) +#define MCAN_PSR_DLEC (0x00000700UL) +#define MCAN_PSR_RESI_POS (11U) +#define MCAN_PSR_RESI (0x00000800UL) +#define MCAN_PSR_RBRS_POS (12U) +#define MCAN_PSR_RBRS (0x00001000UL) +#define MCAN_PSR_RFDF_POS (13U) +#define MCAN_PSR_RFDF (0x00002000UL) +#define MCAN_PSR_PXE_POS (14U) +#define MCAN_PSR_PXE (0x00004000UL) +#define MCAN_PSR_TDCV_POS (16U) +#define MCAN_PSR_TDCV (0x007F0000UL) + +/* Bit definition for MCAN_TDCR register */ +#define MCAN_TDCR_TDCF_POS (0U) +#define MCAN_TDCR_TDCF (0x0000007FUL) +#define MCAN_TDCR_TDCO_POS (8U) +#define MCAN_TDCR_TDCO (0x00007F00UL) + +/* Bit definition for MCAN_IR register */ +#define MCAN_IR_RF0N_POS (0U) +#define MCAN_IR_RF0N (0x00000001UL) +#define MCAN_IR_RF0W_POS (1U) +#define MCAN_IR_RF0W (0x00000002UL) +#define MCAN_IR_RF0F_POS (2U) +#define MCAN_IR_RF0F (0x00000004UL) +#define MCAN_IR_RF0L_POS (3U) +#define MCAN_IR_RF0L (0x00000008UL) +#define MCAN_IR_RF1N_POS (4U) +#define MCAN_IR_RF1N (0x00000010UL) +#define MCAN_IR_RF1W_POS (5U) +#define MCAN_IR_RF1W (0x00000020UL) +#define MCAN_IR_RF1F_POS (6U) +#define MCAN_IR_RF1F (0x00000040UL) +#define MCAN_IR_RF1L_POS (7U) +#define MCAN_IR_RF1L (0x00000080UL) +#define MCAN_IR_HPM_POS (8U) +#define MCAN_IR_HPM (0x00000100UL) +#define MCAN_IR_TC_POS (9U) +#define MCAN_IR_TC (0x00000200UL) +#define MCAN_IR_TCF_POS (10U) +#define MCAN_IR_TCF (0x00000400UL) +#define MCAN_IR_TFE_POS (11U) +#define MCAN_IR_TFE (0x00000800UL) +#define MCAN_IR_TEFN_POS (12U) +#define MCAN_IR_TEFN (0x00001000UL) +#define MCAN_IR_TEFW_POS (13U) +#define MCAN_IR_TEFW (0x00002000UL) +#define MCAN_IR_TEFF_POS (14U) +#define MCAN_IR_TEFF (0x00004000UL) +#define MCAN_IR_TEFL_POS (15U) +#define MCAN_IR_TEFL (0x00008000UL) +#define MCAN_IR_TSW_POS (16U) +#define MCAN_IR_TSW (0x00010000UL) +#define MCAN_IR_MRAF_POS (17U) +#define MCAN_IR_MRAF (0x00020000UL) +#define MCAN_IR_TOO_POS (18U) +#define MCAN_IR_TOO (0x00040000UL) +#define MCAN_IR_DRX_POS (19U) +#define MCAN_IR_DRX (0x00080000UL) +#define MCAN_IR_BEC_POS (20U) +#define MCAN_IR_BEC (0x00100000UL) +#define MCAN_IR_BEU_POS (21U) +#define MCAN_IR_BEU (0x00200000UL) +#define MCAN_IR_ELO_POS (22U) +#define MCAN_IR_ELO (0x00400000UL) +#define MCAN_IR_EP_POS (23U) +#define MCAN_IR_EP (0x00800000UL) +#define MCAN_IR_EW_POS (24U) +#define MCAN_IR_EW (0x01000000UL) +#define MCAN_IR_BO_POS (25U) +#define MCAN_IR_BO (0x02000000UL) +#define MCAN_IR_WDI_POS (26U) +#define MCAN_IR_WDI (0x04000000UL) +#define MCAN_IR_PEA_POS (27U) +#define MCAN_IR_PEA (0x08000000UL) +#define MCAN_IR_PED_POS (28U) +#define MCAN_IR_PED (0x10000000UL) +#define MCAN_IR_ARA_POS (29U) +#define MCAN_IR_ARA (0x20000000UL) + +/* Bit definition for MCAN_IE register */ +#define MCAN_IE_RF0NE_POS (0U) +#define MCAN_IE_RF0NE (0x00000001UL) +#define MCAN_IE_RF0WE_POS (1U) +#define MCAN_IE_RF0WE (0x00000002UL) +#define MCAN_IE_RF0FE_POS (2U) +#define MCAN_IE_RF0FE (0x00000004UL) +#define MCAN_IE_RF0LE_POS (3U) +#define MCAN_IE_RF0LE (0x00000008UL) +#define MCAN_IE_RF1NE_POS (4U) +#define MCAN_IE_RF1NE (0x00000010UL) +#define MCAN_IE_RF1WE_POS (5U) +#define MCAN_IE_RF1WE (0x00000020UL) +#define MCAN_IE_RF1FE_POS (6U) +#define MCAN_IE_RF1FE (0x00000040UL) +#define MCAN_IE_RF1LE_POS (7U) +#define MCAN_IE_RF1LE (0x00000080UL) +#define MCAN_IE_HPME_POS (8U) +#define MCAN_IE_HPME (0x00000100UL) +#define MCAN_IE_TCE_POS (9U) +#define MCAN_IE_TCE (0x00000200UL) +#define MCAN_IE_TCFE_POS (10U) +#define MCAN_IE_TCFE (0x00000400UL) +#define MCAN_IE_TFEE_POS (11U) +#define MCAN_IE_TFEE (0x00000800UL) +#define MCAN_IE_TEFNE_POS (12U) +#define MCAN_IE_TEFNE (0x00001000UL) +#define MCAN_IE_TEFWE_POS (13U) +#define MCAN_IE_TEFWE (0x00002000UL) +#define MCAN_IE_TEFFE_POS (14U) +#define MCAN_IE_TEFFE (0x00004000UL) +#define MCAN_IE_TEFLE_POS (15U) +#define MCAN_IE_TEFLE (0x00008000UL) +#define MCAN_IE_TSWE_POS (16U) +#define MCAN_IE_TSWE (0x00010000UL) +#define MCAN_IE_MRAFE_POS (17U) +#define MCAN_IE_MRAFE (0x00020000UL) +#define MCAN_IE_TOOE_POS (18U) +#define MCAN_IE_TOOE (0x00040000UL) +#define MCAN_IE_DRXE_POS (19U) +#define MCAN_IE_DRXE (0x00080000UL) +#define MCAN_IE_BECE_POS (20U) +#define MCAN_IE_BECE (0x00100000UL) +#define MCAN_IE_BEUE_POS (21U) +#define MCAN_IE_BEUE (0x00200000UL) +#define MCAN_IE_ELOE_POS (22U) +#define MCAN_IE_ELOE (0x00400000UL) +#define MCAN_IE_EPE_POS (23U) +#define MCAN_IE_EPE (0x00800000UL) +#define MCAN_IE_EWE_POS (24U) +#define MCAN_IE_EWE (0x01000000UL) +#define MCAN_IE_BOE_POS (25U) +#define MCAN_IE_BOE (0x02000000UL) +#define MCAN_IE_WDIE_POS (26U) +#define MCAN_IE_WDIE (0x04000000UL) +#define MCAN_IE_PEAE_POS (27U) +#define MCAN_IE_PEAE (0x08000000UL) +#define MCAN_IE_PEDE_POS (28U) +#define MCAN_IE_PEDE (0x10000000UL) +#define MCAN_IE_ARAE_POS (29U) +#define MCAN_IE_ARAE (0x20000000UL) + +/* Bit definition for MCAN_ILS register */ +#define MCAN_ILS_RF0NL_POS (0U) +#define MCAN_ILS_RF0NL (0x00000001UL) +#define MCAN_ILS_RF0WL_POS (1U) +#define MCAN_ILS_RF0WL (0x00000002UL) +#define MCAN_ILS_RF0FL_POS (2U) +#define MCAN_ILS_RF0FL (0x00000004UL) +#define MCAN_ILS_RF0LL_POS (3U) +#define MCAN_ILS_RF0LL (0x00000008UL) +#define MCAN_ILS_RF1NL_POS (4U) +#define MCAN_ILS_RF1NL (0x00000010UL) +#define MCAN_ILS_RF1WL_POS (5U) +#define MCAN_ILS_RF1WL (0x00000020UL) +#define MCAN_ILS_RF1FL_POS (6U) +#define MCAN_ILS_RF1FL (0x00000040UL) +#define MCAN_ILS_RF1LL_POS (7U) +#define MCAN_ILS_RF1LL (0x00000080UL) +#define MCAN_ILS_HPML_POS (8U) +#define MCAN_ILS_HPML (0x00000100UL) +#define MCAN_ILS_TCL_POS (9U) +#define MCAN_ILS_TCL (0x00000200UL) +#define MCAN_ILS_TCFL_POS (10U) +#define MCAN_ILS_TCFL (0x00000400UL) +#define MCAN_ILS_TFEL_POS (11U) +#define MCAN_ILS_TFEL (0x00000800UL) +#define MCAN_ILS_TEFNL_POS (12U) +#define MCAN_ILS_TEFNL (0x00001000UL) +#define MCAN_ILS_TEFWL_POS (13U) +#define MCAN_ILS_TEFWL (0x00002000UL) +#define MCAN_ILS_TEFFL_POS (14U) +#define MCAN_ILS_TEFFL (0x00004000UL) +#define MCAN_ILS_TEFLL_POS (15U) +#define MCAN_ILS_TEFLL (0x00008000UL) +#define MCAN_ILS_TSWL_POS (16U) +#define MCAN_ILS_TSWL (0x00010000UL) +#define MCAN_ILS_MRAFL_POS (17U) +#define MCAN_ILS_MRAFL (0x00020000UL) +#define MCAN_ILS_TOOL_POS (18U) +#define MCAN_ILS_TOOL (0x00040000UL) +#define MCAN_ILS_DRXL_POS (19U) +#define MCAN_ILS_DRXL (0x00080000UL) +#define MCAN_ILS_BECL_POS (20U) +#define MCAN_ILS_BECL (0x00100000UL) +#define MCAN_ILS_BEUL_POS (21U) +#define MCAN_ILS_BEUL (0x00200000UL) +#define MCAN_ILS_ELOL_POS (22U) +#define MCAN_ILS_ELOL (0x00400000UL) +#define MCAN_ILS_EPL_POS (23U) +#define MCAN_ILS_EPL (0x00800000UL) +#define MCAN_ILS_EWL_POS (24U) +#define MCAN_ILS_EWL (0x01000000UL) +#define MCAN_ILS_BOL_POS (25U) +#define MCAN_ILS_BOL (0x02000000UL) +#define MCAN_ILS_WDIL_POS (26U) +#define MCAN_ILS_WDIL (0x04000000UL) +#define MCAN_ILS_PEAL_POS (27U) +#define MCAN_ILS_PEAL (0x08000000UL) +#define MCAN_ILS_PEDL_POS (28U) +#define MCAN_ILS_PEDL (0x10000000UL) +#define MCAN_ILS_ARAL_POS (29U) +#define MCAN_ILS_ARAL (0x20000000UL) + +/* Bit definition for MCAN_ILE register */ +#define MCAN_ILE_EINT0_POS (0U) +#define MCAN_ILE_EINT0 (0x00000001UL) +#define MCAN_ILE_EINT1_POS (1U) +#define MCAN_ILE_EINT1 (0x00000002UL) + +/* Bit definition for MCAN_GFC register */ +#define MCAN_GFC_RRFE_POS (0U) +#define MCAN_GFC_RRFE (0x00000001UL) +#define MCAN_GFC_RRFS_POS (1U) +#define MCAN_GFC_RRFS (0x00000002UL) +#define MCAN_GFC_ANFE_POS (2U) +#define MCAN_GFC_ANFE (0x0000000CUL) +#define MCAN_GFC_ANFE_0 (0x00000004UL) +#define MCAN_GFC_ANFE_1 (0x00000008UL) +#define MCAN_GFC_ANFS_POS (4U) +#define MCAN_GFC_ANFS (0x00000030UL) +#define MCAN_GFC_ANFS_0 (0x00000010UL) +#define MCAN_GFC_ANFS_1 (0x00000020UL) + +/* Bit definition for MCAN_SIDFC register */ +#define MCAN_SIDFC_FLSSA_POS (2U) +#define MCAN_SIDFC_FLSSA (0x0000FFFCUL) +#define MCAN_SIDFC_LSS_POS (16U) +#define MCAN_SIDFC_LSS (0x00FF0000UL) + +/* Bit definition for MCAN_XIDFC register */ +#define MCAN_XIDFC_FLESA_POS (2U) +#define MCAN_XIDFC_FLESA (0x0000FFFCUL) +#define MCAN_XIDFC_LSE_POS (16U) +#define MCAN_XIDFC_LSE (0x007F0000UL) + +/* Bit definition for MCAN_XIDAM register */ +#define MCAN_XIDAM_EIDM (0x1FFFFFFFUL) + +/* Bit definition for MCAN_HPMS register */ +#define MCAN_HPMS_BIDX_POS (0U) +#define MCAN_HPMS_BIDX (0x0000003FUL) +#define MCAN_HPMS_MSI_POS (6U) +#define MCAN_HPMS_MSI (0x000000C0UL) +#define MCAN_HPMS_MSI_0 (0x00000040UL) +#define MCAN_HPMS_MSI_1 (0x00000080UL) +#define MCAN_HPMS_FIDX_POS (8U) +#define MCAN_HPMS_FIDX (0x00007F00UL) +#define MCAN_HPMS_FLST_POS (15U) +#define MCAN_HPMS_FLST (0x00008000UL) + +/* Bit definition for MCAN_NDAT1 register */ +#define MCAN_NDAT1_ND0_POS (0U) +#define MCAN_NDAT1_ND0 (0x00000001UL) +#define MCAN_NDAT1_ND1_POS (1U) +#define MCAN_NDAT1_ND1 (0x00000002UL) +#define MCAN_NDAT1_ND2_POS (2U) +#define MCAN_NDAT1_ND2 (0x00000004UL) +#define MCAN_NDAT1_ND3_POS (3U) +#define MCAN_NDAT1_ND3 (0x00000008UL) +#define MCAN_NDAT1_ND4_POS (4U) +#define MCAN_NDAT1_ND4 (0x00000010UL) +#define MCAN_NDAT1_ND5_POS (5U) +#define MCAN_NDAT1_ND5 (0x00000020UL) +#define MCAN_NDAT1_ND6_POS (6U) +#define MCAN_NDAT1_ND6 (0x00000040UL) +#define MCAN_NDAT1_ND7_POS (7U) +#define MCAN_NDAT1_ND7 (0x00000080UL) +#define MCAN_NDAT1_ND8_POS (8U) +#define MCAN_NDAT1_ND8 (0x00000100UL) +#define MCAN_NDAT1_ND9_POS (9U) +#define MCAN_NDAT1_ND9 (0x00000200UL) +#define MCAN_NDAT1_ND10_POS (10U) +#define MCAN_NDAT1_ND10 (0x00000400UL) +#define MCAN_NDAT1_ND11_POS (11U) +#define MCAN_NDAT1_ND11 (0x00000800UL) +#define MCAN_NDAT1_ND12_POS (12U) +#define MCAN_NDAT1_ND12 (0x00001000UL) +#define MCAN_NDAT1_ND13_POS (13U) +#define MCAN_NDAT1_ND13 (0x00002000UL) +#define MCAN_NDAT1_ND14_POS (14U) +#define MCAN_NDAT1_ND14 (0x00004000UL) +#define MCAN_NDAT1_ND15_POS (15U) +#define MCAN_NDAT1_ND15 (0x00008000UL) +#define MCAN_NDAT1_ND16_POS (16U) +#define MCAN_NDAT1_ND16 (0x00010000UL) +#define MCAN_NDAT1_ND17_POS (17U) +#define MCAN_NDAT1_ND17 (0x00020000UL) +#define MCAN_NDAT1_ND18_POS (18U) +#define MCAN_NDAT1_ND18 (0x00040000UL) +#define MCAN_NDAT1_ND19_POS (19U) +#define MCAN_NDAT1_ND19 (0x00080000UL) +#define MCAN_NDAT1_ND20_POS (20U) +#define MCAN_NDAT1_ND20 (0x00100000UL) +#define MCAN_NDAT1_ND21_POS (21U) +#define MCAN_NDAT1_ND21 (0x00200000UL) +#define MCAN_NDAT1_ND22_POS (22U) +#define MCAN_NDAT1_ND22 (0x00400000UL) +#define MCAN_NDAT1_ND23_POS (23U) +#define MCAN_NDAT1_ND23 (0x00800000UL) +#define MCAN_NDAT1_ND24_POS (24U) +#define MCAN_NDAT1_ND24 (0x01000000UL) +#define MCAN_NDAT1_ND25_POS (25U) +#define MCAN_NDAT1_ND25 (0x02000000UL) +#define MCAN_NDAT1_ND26_POS (26U) +#define MCAN_NDAT1_ND26 (0x04000000UL) +#define MCAN_NDAT1_ND27_POS (27U) +#define MCAN_NDAT1_ND27 (0x08000000UL) +#define MCAN_NDAT1_ND28_POS (28U) +#define MCAN_NDAT1_ND28 (0x10000000UL) +#define MCAN_NDAT1_ND29_POS (29U) +#define MCAN_NDAT1_ND29 (0x20000000UL) +#define MCAN_NDAT1_ND30_POS (30U) +#define MCAN_NDAT1_ND30 (0x40000000UL) +#define MCAN_NDAT1_ND31_POS (31U) +#define MCAN_NDAT1_ND31 (0x80000000UL) + +/* Bit definition for MCAN_NDAT2 register */ +#define MCAN_NDAT2_ND32_POS (0U) +#define MCAN_NDAT2_ND32 (0x00000001UL) +#define MCAN_NDAT2_ND33_POS (1U) +#define MCAN_NDAT2_ND33 (0x00000002UL) +#define MCAN_NDAT2_ND34_POS (2U) +#define MCAN_NDAT2_ND34 (0x00000004UL) +#define MCAN_NDAT2_ND35_POS (3U) +#define MCAN_NDAT2_ND35 (0x00000008UL) +#define MCAN_NDAT2_ND36_POS (4U) +#define MCAN_NDAT2_ND36 (0x00000010UL) +#define MCAN_NDAT2_ND37_POS (5U) +#define MCAN_NDAT2_ND37 (0x00000020UL) +#define MCAN_NDAT2_ND38_POS (6U) +#define MCAN_NDAT2_ND38 (0x00000040UL) +#define MCAN_NDAT2_ND39_POS (7U) +#define MCAN_NDAT2_ND39 (0x00000080UL) +#define MCAN_NDAT2_ND40_POS (8U) +#define MCAN_NDAT2_ND40 (0x00000100UL) +#define MCAN_NDAT2_ND41_POS (9U) +#define MCAN_NDAT2_ND41 (0x00000200UL) +#define MCAN_NDAT2_ND42_POS (10U) +#define MCAN_NDAT2_ND42 (0x00000400UL) +#define MCAN_NDAT2_ND43_POS (11U) +#define MCAN_NDAT2_ND43 (0x00000800UL) +#define MCAN_NDAT2_ND44_POS (12U) +#define MCAN_NDAT2_ND44 (0x00001000UL) +#define MCAN_NDAT2_ND45_POS (13U) +#define MCAN_NDAT2_ND45 (0x00002000UL) +#define MCAN_NDAT2_ND46_POS (14U) +#define MCAN_NDAT2_ND46 (0x00004000UL) +#define MCAN_NDAT2_ND47_POS (15U) +#define MCAN_NDAT2_ND47 (0x00008000UL) +#define MCAN_NDAT2_ND48_POS (16U) +#define MCAN_NDAT2_ND48 (0x00010000UL) +#define MCAN_NDAT2_ND49_POS (17U) +#define MCAN_NDAT2_ND49 (0x00020000UL) +#define MCAN_NDAT2_ND50_POS (18U) +#define MCAN_NDAT2_ND50 (0x00040000UL) +#define MCAN_NDAT2_ND51_POS (19U) +#define MCAN_NDAT2_ND51 (0x00080000UL) +#define MCAN_NDAT2_ND52_POS (20U) +#define MCAN_NDAT2_ND52 (0x00100000UL) +#define MCAN_NDAT2_ND53_POS (21U) +#define MCAN_NDAT2_ND53 (0x00200000UL) +#define MCAN_NDAT2_ND54_POS (22U) +#define MCAN_NDAT2_ND54 (0x00400000UL) +#define MCAN_NDAT2_ND55_POS (23U) +#define MCAN_NDAT2_ND55 (0x00800000UL) +#define MCAN_NDAT2_ND56_POS (24U) +#define MCAN_NDAT2_ND56 (0x01000000UL) +#define MCAN_NDAT2_ND57_POS (25U) +#define MCAN_NDAT2_ND57 (0x02000000UL) +#define MCAN_NDAT2_ND58_POS (26U) +#define MCAN_NDAT2_ND58 (0x04000000UL) +#define MCAN_NDAT2_ND59_POS (27U) +#define MCAN_NDAT2_ND59 (0x08000000UL) +#define MCAN_NDAT2_ND60_POS (28U) +#define MCAN_NDAT2_ND60 (0x10000000UL) +#define MCAN_NDAT2_ND61_POS (29U) +#define MCAN_NDAT2_ND61 (0x20000000UL) +#define MCAN_NDAT2_ND62_POS (30U) +#define MCAN_NDAT2_ND62 (0x40000000UL) +#define MCAN_NDAT2_ND63_POS (31U) +#define MCAN_NDAT2_ND63 (0x80000000UL) + +/* Bit definition for MCAN_RXF0C register */ +#define MCAN_RXF0C_F0SA_POS (2U) +#define MCAN_RXF0C_F0SA (0x0000FFFCUL) +#define MCAN_RXF0C_F0S_POS (16U) +#define MCAN_RXF0C_F0S (0x007F0000UL) +#define MCAN_RXF0C_F0WM_POS (24U) +#define MCAN_RXF0C_F0WM (0x7F000000UL) +#define MCAN_RXF0C_F0OM_POS (31U) +#define MCAN_RXF0C_F0OM (0x80000000UL) + +/* Bit definition for MCAN_RXF0S register */ +#define MCAN_RXF0S_F0FL_POS (0U) +#define MCAN_RXF0S_F0FL (0x0000007FUL) +#define MCAN_RXF0S_F0GI_POS (8U) +#define MCAN_RXF0S_F0GI (0x00003F00UL) +#define MCAN_RXF0S_F0PI_POS (16U) +#define MCAN_RXF0S_F0PI (0x003F0000UL) +#define MCAN_RXF0S_F0F_POS (24U) +#define MCAN_RXF0S_F0F (0x01000000UL) +#define MCAN_RXF0S_RF0L_POS (25U) +#define MCAN_RXF0S_RF0L (0x02000000UL) + +/* Bit definition for MCAN_RXF0A register */ +#define MCAN_RXF0A_F0AI (0x0000003FUL) + +/* Bit definition for MCAN_RXBC register */ +#define MCAN_RXBC_RBSA_POS (2U) +#define MCAN_RXBC_RBSA (0x0000FFFCUL) + +/* Bit definition for MCAN_RXF1C register */ +#define MCAN_RXF1C_F1SA_POS (2U) +#define MCAN_RXF1C_F1SA (0x0000FFFCUL) +#define MCAN_RXF1C_F1S_POS (16U) +#define MCAN_RXF1C_F1S (0x007F0000UL) +#define MCAN_RXF1C_F1WM_POS (24U) +#define MCAN_RXF1C_F1WM (0x7F000000UL) +#define MCAN_RXF1C_F1OM_POS (31U) +#define MCAN_RXF1C_F1OM (0x80000000UL) + +/* Bit definition for MCAN_RXF1S register */ +#define MCAN_RXF1S_F1FL_POS (0U) +#define MCAN_RXF1S_F1FL (0x0000007FUL) +#define MCAN_RXF1S_F1GI_POS (8U) +#define MCAN_RXF1S_F1GI (0x00003F00UL) +#define MCAN_RXF1S_F1PI_POS (16U) +#define MCAN_RXF1S_F1PI (0x003F0000UL) +#define MCAN_RXF1S_F1F_POS (24U) +#define MCAN_RXF1S_F1F (0x01000000UL) +#define MCAN_RXF1S_RF1L_POS (25U) +#define MCAN_RXF1S_RF1L (0x02000000UL) +#define MCAN_RXF1S_DMS_POS (30U) +#define MCAN_RXF1S_DMS (0xC0000000UL) +#define MCAN_RXF1S_DMS_0 (0x40000000UL) +#define MCAN_RXF1S_DMS_1 (0x80000000UL) + +/* Bit definition for MCAN_RXF1A register */ +#define MCAN_RXF1A_F1AI (0x0000003FUL) + +/* Bit definition for MCAN_RXESC register */ +#define MCAN_RXESC_F0DS_POS (0U) +#define MCAN_RXESC_F0DS (0x00000007UL) +#define MCAN_RXESC_F1DS_POS (4U) +#define MCAN_RXESC_F1DS (0x00000070UL) +#define MCAN_RXESC_RBDS_POS (8U) +#define MCAN_RXESC_RBDS (0x00000700UL) + +/* Bit definition for MCAN_TXBC register */ +#define MCAN_TXBC_TBSA_POS (2U) +#define MCAN_TXBC_TBSA (0x0000FFFCUL) +#define MCAN_TXBC_NDTB_POS (16U) +#define MCAN_TXBC_NDTB (0x003F0000UL) +#define MCAN_TXBC_TFQS_POS (24U) +#define MCAN_TXBC_TFQS (0x3F000000UL) +#define MCAN_TXBC_TFQM_POS (30U) +#define MCAN_TXBC_TFQM (0x40000000UL) + +/* Bit definition for MCAN_TXFQS register */ +#define MCAN_TXFQS_TFFL_POS (0U) +#define MCAN_TXFQS_TFFL (0x0000003FUL) +#define MCAN_TXFQS_TFGI_POS (8U) +#define MCAN_TXFQS_TFGI (0x00001F00UL) +#define MCAN_TXFQS_TFQPI_POS (16U) +#define MCAN_TXFQS_TFQPI (0x001F0000UL) +#define MCAN_TXFQS_TFQF_POS (21U) +#define MCAN_TXFQS_TFQF (0x00200000UL) + +/* Bit definition for MCAN_TXESC register */ +#define MCAN_TXESC_TBDS (0x00000007UL) + +/* Bit definition for MCAN_TXBRP register */ +#define MCAN_TXBRP_TRP0_POS (0U) +#define MCAN_TXBRP_TRP0 (0x00000001UL) +#define MCAN_TXBRP_TRP1_POS (1U) +#define MCAN_TXBRP_TRP1 (0x00000002UL) +#define MCAN_TXBRP_TRP2_POS (2U) +#define MCAN_TXBRP_TRP2 (0x00000004UL) +#define MCAN_TXBRP_TRP3_POS (3U) +#define MCAN_TXBRP_TRP3 (0x00000008UL) +#define MCAN_TXBRP_TRP4_POS (4U) +#define MCAN_TXBRP_TRP4 (0x00000010UL) +#define MCAN_TXBRP_TRP5_POS (5U) +#define MCAN_TXBRP_TRP5 (0x00000020UL) +#define MCAN_TXBRP_TRP6_POS (6U) +#define MCAN_TXBRP_TRP6 (0x00000040UL) +#define MCAN_TXBRP_TRP7_POS (7U) +#define MCAN_TXBRP_TRP7 (0x00000080UL) +#define MCAN_TXBRP_TRP8_POS (8U) +#define MCAN_TXBRP_TRP8 (0x00000100UL) +#define MCAN_TXBRP_TRP9_POS (9U) +#define MCAN_TXBRP_TRP9 (0x00000200UL) +#define MCAN_TXBRP_TRP10_POS (10U) +#define MCAN_TXBRP_TRP10 (0x00000400UL) +#define MCAN_TXBRP_TRP11_POS (11U) +#define MCAN_TXBRP_TRP11 (0x00000800UL) +#define MCAN_TXBRP_TRP12_POS (12U) +#define MCAN_TXBRP_TRP12 (0x00001000UL) +#define MCAN_TXBRP_TRP13_POS (13U) +#define MCAN_TXBRP_TRP13 (0x00002000UL) +#define MCAN_TXBRP_TRP14_POS (14U) +#define MCAN_TXBRP_TRP14 (0x00004000UL) +#define MCAN_TXBRP_TRP15_POS (15U) +#define MCAN_TXBRP_TRP15 (0x00008000UL) +#define MCAN_TXBRP_TRP16_POS (16U) +#define MCAN_TXBRP_TRP16 (0x00010000UL) +#define MCAN_TXBRP_TRP17_POS (17U) +#define MCAN_TXBRP_TRP17 (0x00020000UL) +#define MCAN_TXBRP_TRP18_POS (18U) +#define MCAN_TXBRP_TRP18 (0x00040000UL) +#define MCAN_TXBRP_TRP19_POS (19U) +#define MCAN_TXBRP_TRP19 (0x00080000UL) +#define MCAN_TXBRP_TRP20_POS (20U) +#define MCAN_TXBRP_TRP20 (0x00100000UL) +#define MCAN_TXBRP_TRP21_POS (21U) +#define MCAN_TXBRP_TRP21 (0x00200000UL) +#define MCAN_TXBRP_TRP22_POS (22U) +#define MCAN_TXBRP_TRP22 (0x00400000UL) +#define MCAN_TXBRP_TRP23_POS (23U) +#define MCAN_TXBRP_TRP23 (0x00800000UL) +#define MCAN_TXBRP_TRP24_POS (24U) +#define MCAN_TXBRP_TRP24 (0x01000000UL) +#define MCAN_TXBRP_TRP25_POS (25U) +#define MCAN_TXBRP_TRP25 (0x02000000UL) +#define MCAN_TXBRP_TRP26_POS (26U) +#define MCAN_TXBRP_TRP26 (0x04000000UL) +#define MCAN_TXBRP_TRP27_POS (27U) +#define MCAN_TXBRP_TRP27 (0x08000000UL) +#define MCAN_TXBRP_TRP28_POS (28U) +#define MCAN_TXBRP_TRP28 (0x10000000UL) +#define MCAN_TXBRP_TRP29_POS (29U) +#define MCAN_TXBRP_TRP29 (0x20000000UL) +#define MCAN_TXBRP_TRP30_POS (30U) +#define MCAN_TXBRP_TRP30 (0x40000000UL) +#define MCAN_TXBRP_TRP31_POS (31U) +#define MCAN_TXBRP_TRP31 (0x80000000UL) + +/* Bit definition for MCAN_TXBAR register */ +#define MCAN_TXBAR_AR0_POS (0U) +#define MCAN_TXBAR_AR0 (0x00000001UL) +#define MCAN_TXBAR_AR1_POS (1U) +#define MCAN_TXBAR_AR1 (0x00000002UL) +#define MCAN_TXBAR_AR2_POS (2U) +#define MCAN_TXBAR_AR2 (0x00000004UL) +#define MCAN_TXBAR_AR3_POS (3U) +#define MCAN_TXBAR_AR3 (0x00000008UL) +#define MCAN_TXBAR_AR4_POS (4U) +#define MCAN_TXBAR_AR4 (0x00000010UL) +#define MCAN_TXBAR_AR5_POS (5U) +#define MCAN_TXBAR_AR5 (0x00000020UL) +#define MCAN_TXBAR_AR6_POS (6U) +#define MCAN_TXBAR_AR6 (0x00000040UL) +#define MCAN_TXBAR_AR7_POS (7U) +#define MCAN_TXBAR_AR7 (0x00000080UL) +#define MCAN_TXBAR_AR8_POS (8U) +#define MCAN_TXBAR_AR8 (0x00000100UL) +#define MCAN_TXBAR_AR9_POS (9U) +#define MCAN_TXBAR_AR9 (0x00000200UL) +#define MCAN_TXBAR_AR10_POS (10U) +#define MCAN_TXBAR_AR10 (0x00000400UL) +#define MCAN_TXBAR_AR11_POS (11U) +#define MCAN_TXBAR_AR11 (0x00000800UL) +#define MCAN_TXBAR_AR12_POS (12U) +#define MCAN_TXBAR_AR12 (0x00001000UL) +#define MCAN_TXBAR_AR13_POS (13U) +#define MCAN_TXBAR_AR13 (0x00002000UL) +#define MCAN_TXBAR_AR14_POS (14U) +#define MCAN_TXBAR_AR14 (0x00004000UL) +#define MCAN_TXBAR_AR15_POS (15U) +#define MCAN_TXBAR_AR15 (0x00008000UL) +#define MCAN_TXBAR_AR16_POS (16U) +#define MCAN_TXBAR_AR16 (0x00010000UL) +#define MCAN_TXBAR_AR17_POS (17U) +#define MCAN_TXBAR_AR17 (0x00020000UL) +#define MCAN_TXBAR_AR18_POS (18U) +#define MCAN_TXBAR_AR18 (0x00040000UL) +#define MCAN_TXBAR_AR19_POS (19U) +#define MCAN_TXBAR_AR19 (0x00080000UL) +#define MCAN_TXBAR_AR20_POS (20U) +#define MCAN_TXBAR_AR20 (0x00100000UL) +#define MCAN_TXBAR_AR21_POS (21U) +#define MCAN_TXBAR_AR21 (0x00200000UL) +#define MCAN_TXBAR_AR22_POS (22U) +#define MCAN_TXBAR_AR22 (0x00400000UL) +#define MCAN_TXBAR_AR23_POS (23U) +#define MCAN_TXBAR_AR23 (0x00800000UL) +#define MCAN_TXBAR_AR24_POS (24U) +#define MCAN_TXBAR_AR24 (0x01000000UL) +#define MCAN_TXBAR_AR25_POS (25U) +#define MCAN_TXBAR_AR25 (0x02000000UL) +#define MCAN_TXBAR_AR26_POS (26U) +#define MCAN_TXBAR_AR26 (0x04000000UL) +#define MCAN_TXBAR_AR27_POS (27U) +#define MCAN_TXBAR_AR27 (0x08000000UL) +#define MCAN_TXBAR_AR28_POS (28U) +#define MCAN_TXBAR_AR28 (0x10000000UL) +#define MCAN_TXBAR_AR29_POS (29U) +#define MCAN_TXBAR_AR29 (0x20000000UL) +#define MCAN_TXBAR_AR30_POS (30U) +#define MCAN_TXBAR_AR30 (0x40000000UL) +#define MCAN_TXBAR_AR31_POS (31U) +#define MCAN_TXBAR_AR31 (0x80000000UL) + +/* Bit definition for MCAN_TXBCR register */ +#define MCAN_TXBCR_CR0_POS (0U) +#define MCAN_TXBCR_CR0 (0x00000001UL) +#define MCAN_TXBCR_CR1_POS (1U) +#define MCAN_TXBCR_CR1 (0x00000002UL) +#define MCAN_TXBCR_CR2_POS (2U) +#define MCAN_TXBCR_CR2 (0x00000004UL) +#define MCAN_TXBCR_CR3_POS (3U) +#define MCAN_TXBCR_CR3 (0x00000008UL) +#define MCAN_TXBCR_CR4_POS (4U) +#define MCAN_TXBCR_CR4 (0x00000010UL) +#define MCAN_TXBCR_CR5_POS (5U) +#define MCAN_TXBCR_CR5 (0x00000020UL) +#define MCAN_TXBCR_CR6_POS (6U) +#define MCAN_TXBCR_CR6 (0x00000040UL) +#define MCAN_TXBCR_CR7_POS (7U) +#define MCAN_TXBCR_CR7 (0x00000080UL) +#define MCAN_TXBCR_CR8_POS (8U) +#define MCAN_TXBCR_CR8 (0x00000100UL) +#define MCAN_TXBCR_CR9_POS (9U) +#define MCAN_TXBCR_CR9 (0x00000200UL) +#define MCAN_TXBCR_CR10_POS (10U) +#define MCAN_TXBCR_CR10 (0x00000400UL) +#define MCAN_TXBCR_CR11_POS (11U) +#define MCAN_TXBCR_CR11 (0x00000800UL) +#define MCAN_TXBCR_CR12_POS (12U) +#define MCAN_TXBCR_CR12 (0x00001000UL) +#define MCAN_TXBCR_CR13_POS (13U) +#define MCAN_TXBCR_CR13 (0x00002000UL) +#define MCAN_TXBCR_CR14_POS (14U) +#define MCAN_TXBCR_CR14 (0x00004000UL) +#define MCAN_TXBCR_CR15_POS (15U) +#define MCAN_TXBCR_CR15 (0x00008000UL) +#define MCAN_TXBCR_CR16_POS (16U) +#define MCAN_TXBCR_CR16 (0x00010000UL) +#define MCAN_TXBCR_CR17_POS (17U) +#define MCAN_TXBCR_CR17 (0x00020000UL) +#define MCAN_TXBCR_CR18_POS (18U) +#define MCAN_TXBCR_CR18 (0x00040000UL) +#define MCAN_TXBCR_CR19_POS (19U) +#define MCAN_TXBCR_CR19 (0x00080000UL) +#define MCAN_TXBCR_CR20_POS (20U) +#define MCAN_TXBCR_CR20 (0x00100000UL) +#define MCAN_TXBCR_CR21_POS (21U) +#define MCAN_TXBCR_CR21 (0x00200000UL) +#define MCAN_TXBCR_CR22_POS (22U) +#define MCAN_TXBCR_CR22 (0x00400000UL) +#define MCAN_TXBCR_CR23_POS (23U) +#define MCAN_TXBCR_CR23 (0x00800000UL) +#define MCAN_TXBCR_CR24_POS (24U) +#define MCAN_TXBCR_CR24 (0x01000000UL) +#define MCAN_TXBCR_CR25_POS (25U) +#define MCAN_TXBCR_CR25 (0x02000000UL) +#define MCAN_TXBCR_CR26_POS (26U) +#define MCAN_TXBCR_CR26 (0x04000000UL) +#define MCAN_TXBCR_CR27_POS (27U) +#define MCAN_TXBCR_CR27 (0x08000000UL) +#define MCAN_TXBCR_CR28_POS (28U) +#define MCAN_TXBCR_CR28 (0x10000000UL) +#define MCAN_TXBCR_CR29_POS (29U) +#define MCAN_TXBCR_CR29 (0x20000000UL) +#define MCAN_TXBCR_CR30_POS (30U) +#define MCAN_TXBCR_CR30 (0x40000000UL) +#define MCAN_TXBCR_CR31_POS (31U) +#define MCAN_TXBCR_CR31 (0x80000000UL) + +/* Bit definition for MCAN_TXBTO register */ +#define MCAN_TXBTO_TO0_POS (0U) +#define MCAN_TXBTO_TO0 (0x00000001UL) +#define MCAN_TXBTO_TO1_POS (1U) +#define MCAN_TXBTO_TO1 (0x00000002UL) +#define MCAN_TXBTO_TO2_POS (2U) +#define MCAN_TXBTO_TO2 (0x00000004UL) +#define MCAN_TXBTO_TO3_POS (3U) +#define MCAN_TXBTO_TO3 (0x00000008UL) +#define MCAN_TXBTO_TO4_POS (4U) +#define MCAN_TXBTO_TO4 (0x00000010UL) +#define MCAN_TXBTO_TO5_POS (5U) +#define MCAN_TXBTO_TO5 (0x00000020UL) +#define MCAN_TXBTO_TO6_POS (6U) +#define MCAN_TXBTO_TO6 (0x00000040UL) +#define MCAN_TXBTO_TO7_POS (7U) +#define MCAN_TXBTO_TO7 (0x00000080UL) +#define MCAN_TXBTO_TO8_POS (8U) +#define MCAN_TXBTO_TO8 (0x00000100UL) +#define MCAN_TXBTO_TO9_POS (9U) +#define MCAN_TXBTO_TO9 (0x00000200UL) +#define MCAN_TXBTO_TO10_POS (10U) +#define MCAN_TXBTO_TO10 (0x00000400UL) +#define MCAN_TXBTO_TO11_POS (11U) +#define MCAN_TXBTO_TO11 (0x00000800UL) +#define MCAN_TXBTO_TO12_POS (12U) +#define MCAN_TXBTO_TO12 (0x00001000UL) +#define MCAN_TXBTO_TO13_POS (13U) +#define MCAN_TXBTO_TO13 (0x00002000UL) +#define MCAN_TXBTO_TO14_POS (14U) +#define MCAN_TXBTO_TO14 (0x00004000UL) +#define MCAN_TXBTO_TO15_POS (15U) +#define MCAN_TXBTO_TO15 (0x00008000UL) +#define MCAN_TXBTO_TO16_POS (16U) +#define MCAN_TXBTO_TO16 (0x00010000UL) +#define MCAN_TXBTO_TO17_POS (17U) +#define MCAN_TXBTO_TO17 (0x00020000UL) +#define MCAN_TXBTO_TO18_POS (18U) +#define MCAN_TXBTO_TO18 (0x00040000UL) +#define MCAN_TXBTO_TO19_POS (19U) +#define MCAN_TXBTO_TO19 (0x00080000UL) +#define MCAN_TXBTO_TO20_POS (20U) +#define MCAN_TXBTO_TO20 (0x00100000UL) +#define MCAN_TXBTO_TO21_POS (21U) +#define MCAN_TXBTO_TO21 (0x00200000UL) +#define MCAN_TXBTO_TO22_POS (22U) +#define MCAN_TXBTO_TO22 (0x00400000UL) +#define MCAN_TXBTO_TO23_POS (23U) +#define MCAN_TXBTO_TO23 (0x00800000UL) +#define MCAN_TXBTO_TO24_POS (24U) +#define MCAN_TXBTO_TO24 (0x01000000UL) +#define MCAN_TXBTO_TO25_POS (25U) +#define MCAN_TXBTO_TO25 (0x02000000UL) +#define MCAN_TXBTO_TO26_POS (26U) +#define MCAN_TXBTO_TO26 (0x04000000UL) +#define MCAN_TXBTO_TO27_POS (27U) +#define MCAN_TXBTO_TO27 (0x08000000UL) +#define MCAN_TXBTO_TO28_POS (28U) +#define MCAN_TXBTO_TO28 (0x10000000UL) +#define MCAN_TXBTO_TO29_POS (29U) +#define MCAN_TXBTO_TO29 (0x20000000UL) +#define MCAN_TXBTO_TO30_POS (30U) +#define MCAN_TXBTO_TO30 (0x40000000UL) +#define MCAN_TXBTO_TO31_POS (31U) +#define MCAN_TXBTO_TO31 (0x80000000UL) + +/* Bit definition for MCAN_TXBCF register */ +#define MCAN_TXBCF_CF0_POS (0U) +#define MCAN_TXBCF_CF0 (0x00000001UL) +#define MCAN_TXBCF_CF1_POS (1U) +#define MCAN_TXBCF_CF1 (0x00000002UL) +#define MCAN_TXBCF_CF2_POS (2U) +#define MCAN_TXBCF_CF2 (0x00000004UL) +#define MCAN_TXBCF_CF3_POS (3U) +#define MCAN_TXBCF_CF3 (0x00000008UL) +#define MCAN_TXBCF_CF4_POS (4U) +#define MCAN_TXBCF_CF4 (0x00000010UL) +#define MCAN_TXBCF_CF5_POS (5U) +#define MCAN_TXBCF_CF5 (0x00000020UL) +#define MCAN_TXBCF_CF6_POS (6U) +#define MCAN_TXBCF_CF6 (0x00000040UL) +#define MCAN_TXBCF_CF7_POS (7U) +#define MCAN_TXBCF_CF7 (0x00000080UL) +#define MCAN_TXBCF_CF8_POS (8U) +#define MCAN_TXBCF_CF8 (0x00000100UL) +#define MCAN_TXBCF_CF9_POS (9U) +#define MCAN_TXBCF_CF9 (0x00000200UL) +#define MCAN_TXBCF_CF10_POS (10U) +#define MCAN_TXBCF_CF10 (0x00000400UL) +#define MCAN_TXBCF_CF11_POS (11U) +#define MCAN_TXBCF_CF11 (0x00000800UL) +#define MCAN_TXBCF_CF12_POS (12U) +#define MCAN_TXBCF_CF12 (0x00001000UL) +#define MCAN_TXBCF_CF13_POS (13U) +#define MCAN_TXBCF_CF13 (0x00002000UL) +#define MCAN_TXBCF_CF14_POS (14U) +#define MCAN_TXBCF_CF14 (0x00004000UL) +#define MCAN_TXBCF_CF15_POS (15U) +#define MCAN_TXBCF_CF15 (0x00008000UL) +#define MCAN_TXBCF_CF16_POS (16U) +#define MCAN_TXBCF_CF16 (0x00010000UL) +#define MCAN_TXBCF_CF17_POS (17U) +#define MCAN_TXBCF_CF17 (0x00020000UL) +#define MCAN_TXBCF_CF18_POS (18U) +#define MCAN_TXBCF_CF18 (0x00040000UL) +#define MCAN_TXBCF_CF19_POS (19U) +#define MCAN_TXBCF_CF19 (0x00080000UL) +#define MCAN_TXBCF_CF20_POS (20U) +#define MCAN_TXBCF_CF20 (0x00100000UL) +#define MCAN_TXBCF_CF21_POS (21U) +#define MCAN_TXBCF_CF21 (0x00200000UL) +#define MCAN_TXBCF_CF22_POS (22U) +#define MCAN_TXBCF_CF22 (0x00400000UL) +#define MCAN_TXBCF_CF23_POS (23U) +#define MCAN_TXBCF_CF23 (0x00800000UL) +#define MCAN_TXBCF_CF24_POS (24U) +#define MCAN_TXBCF_CF24 (0x01000000UL) +#define MCAN_TXBCF_CF25_POS (25U) +#define MCAN_TXBCF_CF25 (0x02000000UL) +#define MCAN_TXBCF_CF26_POS (26U) +#define MCAN_TXBCF_CF26 (0x04000000UL) +#define MCAN_TXBCF_CF27_POS (27U) +#define MCAN_TXBCF_CF27 (0x08000000UL) +#define MCAN_TXBCF_CF28_POS (28U) +#define MCAN_TXBCF_CF28 (0x10000000UL) +#define MCAN_TXBCF_CF29_POS (29U) +#define MCAN_TXBCF_CF29 (0x20000000UL) +#define MCAN_TXBCF_CF30_POS (30U) +#define MCAN_TXBCF_CF30 (0x40000000UL) +#define MCAN_TXBCF_CF31_POS (31U) +#define MCAN_TXBCF_CF31 (0x80000000UL) + +/* Bit definition for MCAN_TXBTIE register */ +#define MCAN_TXBTIE_TIE0_POS (0U) +#define MCAN_TXBTIE_TIE0 (0x00000001UL) +#define MCAN_TXBTIE_TIE1_POS (1U) +#define MCAN_TXBTIE_TIE1 (0x00000002UL) +#define MCAN_TXBTIE_TIE2_POS (2U) +#define MCAN_TXBTIE_TIE2 (0x00000004UL) +#define MCAN_TXBTIE_TIE3_POS (3U) +#define MCAN_TXBTIE_TIE3 (0x00000008UL) +#define MCAN_TXBTIE_TIE4_POS (4U) +#define MCAN_TXBTIE_TIE4 (0x00000010UL) +#define MCAN_TXBTIE_TIE5_POS (5U) +#define MCAN_TXBTIE_TIE5 (0x00000020UL) +#define MCAN_TXBTIE_TIE6_POS (6U) +#define MCAN_TXBTIE_TIE6 (0x00000040UL) +#define MCAN_TXBTIE_TIE7_POS (7U) +#define MCAN_TXBTIE_TIE7 (0x00000080UL) +#define MCAN_TXBTIE_TIE8_POS (8U) +#define MCAN_TXBTIE_TIE8 (0x00000100UL) +#define MCAN_TXBTIE_TIE9_POS (9U) +#define MCAN_TXBTIE_TIE9 (0x00000200UL) +#define MCAN_TXBTIE_TIE10_POS (10U) +#define MCAN_TXBTIE_TIE10 (0x00000400UL) +#define MCAN_TXBTIE_TIE11_POS (11U) +#define MCAN_TXBTIE_TIE11 (0x00000800UL) +#define MCAN_TXBTIE_TIE12_POS (12U) +#define MCAN_TXBTIE_TIE12 (0x00001000UL) +#define MCAN_TXBTIE_TIE13_POS (13U) +#define MCAN_TXBTIE_TIE13 (0x00002000UL) +#define MCAN_TXBTIE_TIE14_POS (14U) +#define MCAN_TXBTIE_TIE14 (0x00004000UL) +#define MCAN_TXBTIE_TIE15_POS (15U) +#define MCAN_TXBTIE_TIE15 (0x00008000UL) +#define MCAN_TXBTIE_TIE16_POS (16U) +#define MCAN_TXBTIE_TIE16 (0x00010000UL) +#define MCAN_TXBTIE_TIE17_POS (17U) +#define MCAN_TXBTIE_TIE17 (0x00020000UL) +#define MCAN_TXBTIE_TIE18_POS (18U) +#define MCAN_TXBTIE_TIE18 (0x00040000UL) +#define MCAN_TXBTIE_TIE19_POS (19U) +#define MCAN_TXBTIE_TIE19 (0x00080000UL) +#define MCAN_TXBTIE_TIE20_POS (20U) +#define MCAN_TXBTIE_TIE20 (0x00100000UL) +#define MCAN_TXBTIE_TIE21_POS (21U) +#define MCAN_TXBTIE_TIE21 (0x00200000UL) +#define MCAN_TXBTIE_TIE22_POS (22U) +#define MCAN_TXBTIE_TIE22 (0x00400000UL) +#define MCAN_TXBTIE_TIE23_POS (23U) +#define MCAN_TXBTIE_TIE23 (0x00800000UL) +#define MCAN_TXBTIE_TIE24_POS (24U) +#define MCAN_TXBTIE_TIE24 (0x01000000UL) +#define MCAN_TXBTIE_TIE25_POS (25U) +#define MCAN_TXBTIE_TIE25 (0x02000000UL) +#define MCAN_TXBTIE_TIE26_POS (26U) +#define MCAN_TXBTIE_TIE26 (0x04000000UL) +#define MCAN_TXBTIE_TIE27_POS (27U) +#define MCAN_TXBTIE_TIE27 (0x08000000UL) +#define MCAN_TXBTIE_TIE28_POS (28U) +#define MCAN_TXBTIE_TIE28 (0x10000000UL) +#define MCAN_TXBTIE_TIE29_POS (29U) +#define MCAN_TXBTIE_TIE29 (0x20000000UL) +#define MCAN_TXBTIE_TIE30_POS (30U) +#define MCAN_TXBTIE_TIE30 (0x40000000UL) +#define MCAN_TXBTIE_TIE31_POS (31U) +#define MCAN_TXBTIE_TIE31 (0x80000000UL) + +/* Bit definition for MCAN_TXBCIE register */ +#define MCAN_TXBCIE_CFIE0_POS (0U) +#define MCAN_TXBCIE_CFIE0 (0x00000001UL) +#define MCAN_TXBCIE_CFIE1_POS (1U) +#define MCAN_TXBCIE_CFIE1 (0x00000002UL) +#define MCAN_TXBCIE_CFIE2_POS (2U) +#define MCAN_TXBCIE_CFIE2 (0x00000004UL) +#define MCAN_TXBCIE_CFIE3_POS (3U) +#define MCAN_TXBCIE_CFIE3 (0x00000008UL) +#define MCAN_TXBCIE_CFIE4_POS (4U) +#define MCAN_TXBCIE_CFIE4 (0x00000010UL) +#define MCAN_TXBCIE_CFIE5_POS (5U) +#define MCAN_TXBCIE_CFIE5 (0x00000020UL) +#define MCAN_TXBCIE_CFIE6_POS (6U) +#define MCAN_TXBCIE_CFIE6 (0x00000040UL) +#define MCAN_TXBCIE_CFIE7_POS (7U) +#define MCAN_TXBCIE_CFIE7 (0x00000080UL) +#define MCAN_TXBCIE_CFIE8_POS (8U) +#define MCAN_TXBCIE_CFIE8 (0x00000100UL) +#define MCAN_TXBCIE_CFIE9_POS (9U) +#define MCAN_TXBCIE_CFIE9 (0x00000200UL) +#define MCAN_TXBCIE_CFIE10_POS (10U) +#define MCAN_TXBCIE_CFIE10 (0x00000400UL) +#define MCAN_TXBCIE_CFIE11_POS (11U) +#define MCAN_TXBCIE_CFIE11 (0x00000800UL) +#define MCAN_TXBCIE_CFIE12_POS (12U) +#define MCAN_TXBCIE_CFIE12 (0x00001000UL) +#define MCAN_TXBCIE_CFIE13_POS (13U) +#define MCAN_TXBCIE_CFIE13 (0x00002000UL) +#define MCAN_TXBCIE_CFIE14_POS (14U) +#define MCAN_TXBCIE_CFIE14 (0x00004000UL) +#define MCAN_TXBCIE_CFIE15_POS (15U) +#define MCAN_TXBCIE_CFIE15 (0x00008000UL) +#define MCAN_TXBCIE_CFIE16_POS (16U) +#define MCAN_TXBCIE_CFIE16 (0x00010000UL) +#define MCAN_TXBCIE_CFIE17_POS (17U) +#define MCAN_TXBCIE_CFIE17 (0x00020000UL) +#define MCAN_TXBCIE_CFIE18_POS (18U) +#define MCAN_TXBCIE_CFIE18 (0x00040000UL) +#define MCAN_TXBCIE_CFIE19_POS (19U) +#define MCAN_TXBCIE_CFIE19 (0x00080000UL) +#define MCAN_TXBCIE_CFIE20_POS (20U) +#define MCAN_TXBCIE_CFIE20 (0x00100000UL) +#define MCAN_TXBCIE_CFIE21_POS (21U) +#define MCAN_TXBCIE_CFIE21 (0x00200000UL) +#define MCAN_TXBCIE_CFIE22_POS (22U) +#define MCAN_TXBCIE_CFIE22 (0x00400000UL) +#define MCAN_TXBCIE_CFIE23_POS (23U) +#define MCAN_TXBCIE_CFIE23 (0x00800000UL) +#define MCAN_TXBCIE_CFIE24_POS (24U) +#define MCAN_TXBCIE_CFIE24 (0x01000000UL) +#define MCAN_TXBCIE_CFIE25_POS (25U) +#define MCAN_TXBCIE_CFIE25 (0x02000000UL) +#define MCAN_TXBCIE_CFIE26_POS (26U) +#define MCAN_TXBCIE_CFIE26 (0x04000000UL) +#define MCAN_TXBCIE_CFIE27_POS (27U) +#define MCAN_TXBCIE_CFIE27 (0x08000000UL) +#define MCAN_TXBCIE_CFIE28_POS (28U) +#define MCAN_TXBCIE_CFIE28 (0x10000000UL) +#define MCAN_TXBCIE_CFIE29_POS (29U) +#define MCAN_TXBCIE_CFIE29 (0x20000000UL) +#define MCAN_TXBCIE_CFIE30_POS (30U) +#define MCAN_TXBCIE_CFIE30 (0x40000000UL) +#define MCAN_TXBCIE_CFIE31_POS (31U) +#define MCAN_TXBCIE_CFIE31 (0x80000000UL) + +/* Bit definition for MCAN_TXEFC register */ +#define MCAN_TXEFC_EFSA_POS (2U) +#define MCAN_TXEFC_EFSA (0x0000FFFCUL) +#define MCAN_TXEFC_EFS_POS (16U) +#define MCAN_TXEFC_EFS (0x003F0000UL) +#define MCAN_TXEFC_EFWM_POS (24U) +#define MCAN_TXEFC_EFWM (0x3F000000UL) + +/* Bit definition for MCAN_TXEFS register */ +#define MCAN_TXEFS_EFFL_POS (0U) +#define MCAN_TXEFS_EFFL (0x0000003FUL) +#define MCAN_TXEFS_EFGI_POS (8U) +#define MCAN_TXEFS_EFGI (0x00001F00UL) +#define MCAN_TXEFS_EFPI_POS (16U) +#define MCAN_TXEFS_EFPI (0x001F0000UL) +#define MCAN_TXEFS_EFF_POS (24U) +#define MCAN_TXEFS_EFF (0x01000000UL) +#define MCAN_TXEFS_TEFL_POS (25U) +#define MCAN_TXEFS_TEFL (0x02000000UL) + +/* Bit definition for MCAN_TXEFA register */ +#define MCAN_TXEFA_EFAI (0x0000001FUL) + +/******************************************************************************* + Bit definition for Peripheral MPU +*******************************************************************************/ +/* Bit definition for MPU_RGD register */ +#define MPU_RGD_MPURGSIZE_POS (0U) +#define MPU_RGD_MPURGSIZE (0x0000001FUL) +#define MPU_RGD_MPURGADDR_POS (5U) +#define MPU_RGD_MPURGADDR (0xFFFFFFE0UL) + +/* Bit definition for MPU_SR register */ +#define MPU_SR_SMPU1EAF_POS (0U) +#define MPU_SR_SMPU1EAF (0x00000001UL) +#define MPU_SR_SMPU2EAF_POS (1U) +#define MPU_SR_SMPU2EAF (0x00000002UL) +#define MPU_SR_PSPEF_POS (2U) +#define MPU_SR_PSPEF (0x00000004UL) +#define MPU_SR_MSPEF_POS (3U) +#define MPU_SR_MSPEF (0x00000008UL) + +/* Bit definition for MPU_ECLR register */ +#define MPU_ECLR_SMPU1ECLR_POS (0U) +#define MPU_ECLR_SMPU1ECLR (0x00000001UL) +#define MPU_ECLR_SMPU2ECLR_POS (1U) +#define MPU_ECLR_SMPU2ECLR (0x00000002UL) +#define MPU_ECLR_PSPECLR_POS (2U) +#define MPU_ECLR_PSPECLR (0x00000004UL) +#define MPU_ECLR_MSPECLR_POS (3U) +#define MPU_ECLR_MSPECLR (0x00000008UL) + +/* Bit definition for MPU_WP register */ +#define MPU_WP_MPUWE_POS (0U) +#define MPU_WP_MPUWE (0x00000001UL) +#define MPU_WP_WKEY_POS (1U) +#define MPU_WP_WKEY (0x0000FFFEUL) + +/* Bit definition for MPU_IPPR register */ +#define MPU_IPPR_AESRDP_POS (0U) +#define MPU_IPPR_AESRDP (0x00000001UL) +#define MPU_IPPR_AESWRP_POS (1U) +#define MPU_IPPR_AESWRP (0x00000002UL) +#define MPU_IPPR_HASHRDP_POS (2U) +#define MPU_IPPR_HASHRDP (0x00000004UL) +#define MPU_IPPR_HASHWRP_POS (3U) +#define MPU_IPPR_HASHWRP (0x00000008UL) +#define MPU_IPPR_TRNGRDP_POS (4U) +#define MPU_IPPR_TRNGRDP (0x00000010UL) +#define MPU_IPPR_TRNGWRP_POS (5U) +#define MPU_IPPR_TRNGWRP (0x00000020UL) +#define MPU_IPPR_CRCRDP_POS (6U) +#define MPU_IPPR_CRCRDP (0x00000040UL) +#define MPU_IPPR_CRCWRP_POS (7U) +#define MPU_IPPR_CRCWRP (0x00000080UL) +#define MPU_IPPR_EFMRDP_POS (8U) +#define MPU_IPPR_EFMRDP (0x00000100UL) +#define MPU_IPPR_EFMWRP_POS (9U) +#define MPU_IPPR_EFMWRP (0x00000200UL) +#define MPU_IPPR_WDTRDP_POS (12U) +#define MPU_IPPR_WDTRDP (0x00001000UL) +#define MPU_IPPR_WDTWRP_POS (13U) +#define MPU_IPPR_WDTWRP (0x00002000UL) +#define MPU_IPPR_SWDTRDP_POS (14U) +#define MPU_IPPR_SWDTRDP (0x00004000UL) +#define MPU_IPPR_SWDTWRP_POS (15U) +#define MPU_IPPR_SWDTWRP (0x00008000UL) +#define MPU_IPPR_BKSRAMRDP_POS (16U) +#define MPU_IPPR_BKSRAMRDP (0x00010000UL) +#define MPU_IPPR_BKSRAMWRP_POS (17U) +#define MPU_IPPR_BKSRAMWRP (0x00020000UL) +#define MPU_IPPR_RTCRDP_POS (18U) +#define MPU_IPPR_RTCRDP (0x00040000UL) +#define MPU_IPPR_RTCWRP_POS (19U) +#define MPU_IPPR_RTCWRP (0x00080000UL) +#define MPU_IPPR_DMPURDP_POS (20U) +#define MPU_IPPR_DMPURDP (0x00100000UL) +#define MPU_IPPR_DMPUWRP_POS (21U) +#define MPU_IPPR_DMPUWRP (0x00200000UL) +#define MPU_IPPR_SRAMCRDP_POS (22U) +#define MPU_IPPR_SRAMCRDP (0x00400000UL) +#define MPU_IPPR_SRAMCWRP_POS (23U) +#define MPU_IPPR_SRAMCWRP (0x00800000UL) +#define MPU_IPPR_INTCRDP_POS (24U) +#define MPU_IPPR_INTCRDP (0x01000000UL) +#define MPU_IPPR_INTCWRP_POS (25U) +#define MPU_IPPR_INTCWRP (0x02000000UL) +#define MPU_IPPR_SYSCRDP_POS (26U) +#define MPU_IPPR_SYSCRDP (0x04000000UL) +#define MPU_IPPR_SYSCWRP_POS (27U) +#define MPU_IPPR_SYSCWRP (0x08000000UL) +#define MPU_IPPR_MSTPRDP_POS (28U) +#define MPU_IPPR_MSTPRDP (0x10000000UL) +#define MPU_IPPR_MSPTWRP_POS (29U) +#define MPU_IPPR_MSPTWRP (0x20000000UL) +#define MPU_IPPR_BUSERRE_POS (31U) +#define MPU_IPPR_BUSERRE (0x80000000UL) + +/* Bit definition for MPU_MSPPBA register */ +#define MPU_MSPPBA_MSPPBA_POS (2U) +#define MPU_MSPPBA_MSPPBA (0xFFFFFFFCUL) + +/* Bit definition for MPU_MSPPCTL register */ +#define MPU_MSPPCTL_MSPPSIZE_POS (2U) +#define MPU_MSPPCTL_MSPPSIZE (0x0000FFFCUL) +#define MPU_MSPPCTL_MSPPACT_POS (30U) +#define MPU_MSPPCTL_MSPPACT (0x40000000UL) +#define MPU_MSPPCTL_MSPPE_POS (31U) +#define MPU_MSPPCTL_MSPPE (0x80000000UL) + +/* Bit definition for MPU_PSPPBA register */ +#define MPU_PSPPBA_PSPPBA_POS (2U) +#define MPU_PSPPBA_PSPPBA (0xFFFFFFFCUL) + +/* Bit definition for MPU_PSPPCTL register */ +#define MPU_PSPPCTL_PSPPSIZE_POS (2U) +#define MPU_PSPPCTL_PSPPSIZE (0x0000FFFCUL) +#define MPU_PSPPCTL_PSPPACT_POS (30U) +#define MPU_PSPPCTL_PSPPACT (0x40000000UL) +#define MPU_PSPPCTL_PSPPE_POS (31U) +#define MPU_PSPPCTL_PSPPE (0x80000000UL) + +/* Bit definition for MPU_SRGE register */ +#define MPU_SRGE_RG0E_POS (0U) +#define MPU_SRGE_RG0E (0x00000001UL) +#define MPU_SRGE_RG1E_POS (1U) +#define MPU_SRGE_RG1E (0x00000002UL) +#define MPU_SRGE_RG2E_POS (2U) +#define MPU_SRGE_RG2E (0x00000004UL) +#define MPU_SRGE_RG3E_POS (3U) +#define MPU_SRGE_RG3E (0x00000008UL) +#define MPU_SRGE_RG4E_POS (4U) +#define MPU_SRGE_RG4E (0x00000010UL) +#define MPU_SRGE_RG5E_POS (5U) +#define MPU_SRGE_RG5E (0x00000020UL) +#define MPU_SRGE_RG6E_POS (6U) +#define MPU_SRGE_RG6E (0x00000040UL) +#define MPU_SRGE_RG7E_POS (7U) +#define MPU_SRGE_RG7E (0x00000080UL) +#define MPU_SRGE_RG8E_POS (8U) +#define MPU_SRGE_RG8E (0x00000100UL) +#define MPU_SRGE_RG9E_POS (9U) +#define MPU_SRGE_RG9E (0x00000200UL) +#define MPU_SRGE_RG10E_POS (10U) +#define MPU_SRGE_RG10E (0x00000400UL) +#define MPU_SRGE_RG11E_POS (11U) +#define MPU_SRGE_RG11E (0x00000800UL) +#define MPU_SRGE_RG12E_POS (12U) +#define MPU_SRGE_RG12E (0x00001000UL) +#define MPU_SRGE_RG13E_POS (13U) +#define MPU_SRGE_RG13E (0x00002000UL) +#define MPU_SRGE_RG14E_POS (14U) +#define MPU_SRGE_RG14E (0x00004000UL) +#define MPU_SRGE_RG15E_POS (15U) +#define MPU_SRGE_RG15E (0x00008000UL) + +/* Bit definition for MPU_SRGWP register */ +#define MPU_SRGWP_RG0WP_POS (0U) +#define MPU_SRGWP_RG0WP (0x00000001UL) +#define MPU_SRGWP_RG1WP_POS (1U) +#define MPU_SRGWP_RG1WP (0x00000002UL) +#define MPU_SRGWP_RG2WP_POS (2U) +#define MPU_SRGWP_RG2WP (0x00000004UL) +#define MPU_SRGWP_RG3WP_POS (3U) +#define MPU_SRGWP_RG3WP (0x00000008UL) +#define MPU_SRGWP_RG4WP_POS (4U) +#define MPU_SRGWP_RG4WP (0x00000010UL) +#define MPU_SRGWP_RG5WP_POS (5U) +#define MPU_SRGWP_RG5WP (0x00000020UL) +#define MPU_SRGWP_RG6WP_POS (6U) +#define MPU_SRGWP_RG6WP (0x00000040UL) +#define MPU_SRGWP_RG7WP_POS (7U) +#define MPU_SRGWP_RG7WP (0x00000080UL) +#define MPU_SRGWP_RG8WP_POS (8U) +#define MPU_SRGWP_RG8WP (0x00000100UL) +#define MPU_SRGWP_RG9WP_POS (9U) +#define MPU_SRGWP_RG9WP (0x00000200UL) +#define MPU_SRGWP_RG10WP_POS (10U) +#define MPU_SRGWP_RG10WP (0x00000400UL) +#define MPU_SRGWP_RG11WP_POS (11U) +#define MPU_SRGWP_RG11WP (0x00000800UL) +#define MPU_SRGWP_RG12WP_POS (12U) +#define MPU_SRGWP_RG12WP (0x00001000UL) +#define MPU_SRGWP_RG13WP_POS (13U) +#define MPU_SRGWP_RG13WP (0x00002000UL) +#define MPU_SRGWP_RG14WP_POS (14U) +#define MPU_SRGWP_RG14WP (0x00004000UL) +#define MPU_SRGWP_RG15WP_POS (15U) +#define MPU_SRGWP_RG15WP (0x00008000UL) + +/* Bit definition for MPU_SRGRP register */ +#define MPU_SRGRP_RG0RP_POS (0U) +#define MPU_SRGRP_RG0RP (0x00000001UL) +#define MPU_SRGRP_RG1RP_POS (1U) +#define MPU_SRGRP_RG1RP (0x00000002UL) +#define MPU_SRGRP_RG2RP_POS (2U) +#define MPU_SRGRP_RG2RP (0x00000004UL) +#define MPU_SRGRP_RG3RP_POS (3U) +#define MPU_SRGRP_RG3RP (0x00000008UL) +#define MPU_SRGRP_RG4RP_POS (4U) +#define MPU_SRGRP_RG4RP (0x00000010UL) +#define MPU_SRGRP_RG5RP_POS (5U) +#define MPU_SRGRP_RG5RP (0x00000020UL) +#define MPU_SRGRP_RG6RP_POS (6U) +#define MPU_SRGRP_RG6RP (0x00000040UL) +#define MPU_SRGRP_RG7RP_POS (7U) +#define MPU_SRGRP_RG7RP (0x00000080UL) +#define MPU_SRGRP_RG8RP_POS (8U) +#define MPU_SRGRP_RG8RP (0x00000100UL) +#define MPU_SRGRP_RG9RP_POS (9U) +#define MPU_SRGRP_RG9RP (0x00000200UL) +#define MPU_SRGRP_RG10RP_POS (10U) +#define MPU_SRGRP_RG10RP (0x00000400UL) +#define MPU_SRGRP_RG11RP_POS (11U) +#define MPU_SRGRP_RG11RP (0x00000800UL) +#define MPU_SRGRP_RG12RP_POS (12U) +#define MPU_SRGRP_RG12RP (0x00001000UL) +#define MPU_SRGRP_RG13RP_POS (13U) +#define MPU_SRGRP_RG13RP (0x00002000UL) +#define MPU_SRGRP_RG14RP_POS (14U) +#define MPU_SRGRP_RG14RP (0x00004000UL) +#define MPU_SRGRP_RG15RP_POS (15U) +#define MPU_SRGRP_RG15RP (0x00008000UL) + +/* Bit definition for MPU_SCR register */ +#define MPU_SCR_SMPUBRP_POS (0U) +#define MPU_SCR_SMPUBRP (0x00000001UL) +#define MPU_SCR_SMPUBWP_POS (1U) +#define MPU_SCR_SMPUBWP (0x00000002UL) +#define MPU_SCR_SMPUACT_POS (2U) +#define MPU_SCR_SMPUACT (0x0000000CUL) +#define MPU_SCR_SMPUACT_0 (0x00000004UL) +#define MPU_SCR_SMPUACT_1 (0x00000008UL) +#define MPU_SCR_SMPUE_POS (7U) +#define MPU_SCR_SMPUE (0x00000080UL) + +/******************************************************************************* + Bit definition for Peripheral PERIC +*******************************************************************************/ +/* Bit definition for PERIC_SMC_ENAR register */ +#define PERIC_SMC_ENAR_SMCEN_POS (1U) +#define PERIC_SMC_ENAR_SMCEN (0x00000002UL) + +/* Bit definition for PERIC_TMR_SYNENR register */ +#define PERIC_TMR_SYNENR_TMR0U1A_POS (0U) +#define PERIC_TMR_SYNENR_TMR0U1A (0x00000001UL) +#define PERIC_TMR_SYNENR_TMR0U1B_POS (1U) +#define PERIC_TMR_SYNENR_TMR0U1B (0x00000002UL) +#define PERIC_TMR_SYNENR_TMR0U2A_POS (2U) +#define PERIC_TMR_SYNENR_TMR0U2A (0x00000004UL) +#define PERIC_TMR_SYNENR_TMR0U2B_POS (3U) +#define PERIC_TMR_SYNENR_TMR0U2B (0x00000008UL) +#define PERIC_TMR_SYNENR_TMR4U1_POS (4U) +#define PERIC_TMR_SYNENR_TMR4U1 (0x00000010UL) +#define PERIC_TMR_SYNENR_TMR4U2_POS (5U) +#define PERIC_TMR_SYNENR_TMR4U2 (0x00000020UL) +#define PERIC_TMR_SYNENR_TMR4U3_POS (6U) +#define PERIC_TMR_SYNENR_TMR4U3 (0x00000040UL) +#define PERIC_TMR_SYNENR_TMR6U1_POS (8U) +#define PERIC_TMR_SYNENR_TMR6U1 (0x00000100UL) +#define PERIC_TMR_SYNENR_TMR6U2_POS (9U) +#define PERIC_TMR_SYNENR_TMR6U2 (0x00000200UL) +#define PERIC_TMR_SYNENR_TMRAU1_POS (10U) +#define PERIC_TMR_SYNENR_TMRAU1 (0x00000400UL) +#define PERIC_TMR_SYNENR_TMRAU2_POS (11U) +#define PERIC_TMR_SYNENR_TMRAU2 (0x00000800UL) +#define PERIC_TMR_SYNENR_TMRAU3_POS (12U) +#define PERIC_TMR_SYNENR_TMRAU3 (0x00001000UL) +#define PERIC_TMR_SYNENR_TMRAU4_POS (13U) +#define PERIC_TMR_SYNENR_TMRAU4 (0x00002000UL) +#define PERIC_TMR_SYNENR_TMRAU5_POS (14U) +#define PERIC_TMR_SYNENR_TMRAU5 (0x00004000UL) + +/* Bit definition for PERIC_USART1_NFC register */ +#define PERIC_USART1_NFC_USASRT1_NFS_POS (0U) +#define PERIC_USART1_NFC_USASRT1_NFS (0x00000003UL) +#define PERIC_USART1_NFC_USASRT1_NFS_0 (0x00000001UL) +#define PERIC_USART1_NFC_USASRT1_NFS_1 (0x00000002UL) +#define PERIC_USART1_NFC_USART1_NFE_POS (2U) +#define PERIC_USART1_NFC_USART1_NFE (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral PWC +*******************************************************************************/ +/* Bit definition for PWC_FCG0 register */ +#define PWC_FCG0_SRAMH_POS (0U) +#define PWC_FCG0_SRAMH (0x00000001UL) +#define PWC_FCG0_SRAM0_POS (4U) +#define PWC_FCG0_SRAM0 (0x00000010UL) +#define PWC_FCG0_SRAMB_POS (10U) +#define PWC_FCG0_SRAMB (0x00000400UL) +#define PWC_FCG0_KEY_POS (13U) +#define PWC_FCG0_KEY (0x00002000UL) +#define PWC_FCG0_DMA1_POS (14U) +#define PWC_FCG0_DMA1 (0x00004000UL) +#define PWC_FCG0_DMA2_POS (15U) +#define PWC_FCG0_DMA2 (0x00008000UL) +#define PWC_FCG0_FCM_POS (16U) +#define PWC_FCG0_FCM (0x00010000UL) +#define PWC_FCG0_AOS_POS (17U) +#define PWC_FCG0_AOS (0x00020000UL) +#define PWC_FCG0_CTC_POS (18U) +#define PWC_FCG0_CTC (0x00040000UL) +#define PWC_FCG0_AES_POS (20U) +#define PWC_FCG0_AES (0x00100000UL) +#define PWC_FCG0_HASH_POS (21U) +#define PWC_FCG0_HASH (0x00200000UL) +#define PWC_FCG0_TRNG_POS (22U) +#define PWC_FCG0_TRNG (0x00400000UL) +#define PWC_FCG0_CRC_POS (23U) +#define PWC_FCG0_CRC (0x00800000UL) +#define PWC_FCG0_DCU1_POS (24U) +#define PWC_FCG0_DCU1 (0x01000000UL) +#define PWC_FCG0_DCU2_POS (25U) +#define PWC_FCG0_DCU2 (0x02000000UL) +#define PWC_FCG0_DCU3_POS (26U) +#define PWC_FCG0_DCU3 (0x04000000UL) +#define PWC_FCG0_DCU4_POS (27U) +#define PWC_FCG0_DCU4 (0x08000000UL) + +/* Bit definition for PWC_FCG1 register */ +#define PWC_FCG1_MCAN1_POS (0U) +#define PWC_FCG1_MCAN1 (0x00000001UL) +#define PWC_FCG1_MCAN2_POS (1U) +#define PWC_FCG1_MCAN2 (0x00000002UL) +#define PWC_FCG1_QSPI_POS (3U) +#define PWC_FCG1_QSPI (0x00000008UL) +#define PWC_FCG1_I2C1_POS (4U) +#define PWC_FCG1_I2C1 (0x00000010UL) +#define PWC_FCG1_I2C2_POS (5U) +#define PWC_FCG1_I2C2 (0x00000020UL) +#define PWC_FCG1_SPI1_POS (16U) +#define PWC_FCG1_SPI1 (0x00010000UL) +#define PWC_FCG1_SPI2_POS (17U) +#define PWC_FCG1_SPI2 (0x00020000UL) +#define PWC_FCG1_SPI3_POS (18U) +#define PWC_FCG1_SPI3 (0x00040000UL) + +/* Bit definition for PWC_FCG2 register */ +#define PWC_FCG2_TMR6_1_POS (0U) +#define PWC_FCG2_TMR6_1 (0x00000001UL) +#define PWC_FCG2_TMR6_2_POS (1U) +#define PWC_FCG2_TMR6_2 (0x00000002UL) +#define PWC_FCG2_TMR4_1_POS (9U) +#define PWC_FCG2_TMR4_1 (0x00000200UL) +#define PWC_FCG2_TMR4_2_POS (10U) +#define PWC_FCG2_TMR4_2 (0x00000400UL) +#define PWC_FCG2_TMR4_3_POS (11U) +#define PWC_FCG2_TMR4_3 (0x00000800UL) +#define PWC_FCG2_TMR0_1_POS (12U) +#define PWC_FCG2_TMR0_1 (0x00001000UL) +#define PWC_FCG2_TMR0_2_POS (13U) +#define PWC_FCG2_TMR0_2 (0x00002000UL) +#define PWC_FCG2_EMB_POS (15U) +#define PWC_FCG2_EMB (0x00008000UL) +#define PWC_FCG2_TMRA_1_POS (20U) +#define PWC_FCG2_TMRA_1 (0x00100000UL) +#define PWC_FCG2_TMRA_2_POS (21U) +#define PWC_FCG2_TMRA_2 (0x00200000UL) +#define PWC_FCG2_TMRA_3_POS (22U) +#define PWC_FCG2_TMRA_3 (0x00400000UL) +#define PWC_FCG2_TMRA_4_POS (23U) +#define PWC_FCG2_TMRA_4 (0x00800000UL) +#define PWC_FCG2_TMRA_5_POS (24U) +#define PWC_FCG2_TMRA_5 (0x01000000UL) + +/* Bit definition for PWC_FCG3 register */ +#define PWC_FCG3_ADC1_POS (0U) +#define PWC_FCG3_ADC1 (0x00000001UL) +#define PWC_FCG3_ADC2_POS (1U) +#define PWC_FCG3_ADC2 (0x00000002UL) +#define PWC_FCG3_ADC3_POS (2U) +#define PWC_FCG3_ADC3 (0x00000004UL) +#define PWC_FCG3_DAC_POS (4U) +#define PWC_FCG3_DAC (0x00000010UL) +#define PWC_FCG3_CMP12_POS (8U) +#define PWC_FCG3_CMP12 (0x00000100UL) +#define PWC_FCG3_CMP34_POS (9U) +#define PWC_FCG3_CMP34 (0x00000200UL) +#define PWC_FCG3_SMC_POS (16U) +#define PWC_FCG3_SMC (0x00010000UL) +#define PWC_FCG3_USART1_POS (20U) +#define PWC_FCG3_USART1 (0x00100000UL) +#define PWC_FCG3_USART2_POS (21U) +#define PWC_FCG3_USART2 (0x00200000UL) +#define PWC_FCG3_USART3_POS (22U) +#define PWC_FCG3_USART3 (0x00400000UL) +#define PWC_FCG3_USART4_POS (23U) +#define PWC_FCG3_USART4 (0x00800000UL) +#define PWC_FCG3_USART5_POS (24U) +#define PWC_FCG3_USART5 (0x01000000UL) +#define PWC_FCG3_USART6_POS (25U) +#define PWC_FCG3_USART6 (0x02000000UL) + +/* Bit definition for PWC_FCG0PC register */ +#define PWC_FCG0PC_PRT0_POS (0U) +#define PWC_FCG0PC_PRT0 (0x00000001UL) +#define PWC_FCG0PC_FCG0PCWE_POS (16U) +#define PWC_FCG0PC_FCG0PCWE (0xFFFF0000UL) + +/* Bit definition for PWC_WKTCR register */ +#define PWC_WKTCR_WKTMCMP_POS (0U) +#define PWC_WKTCR_WKTMCMP (0x0FFFU) +#define PWC_WKTCR_WKOVF_POS (12U) +#define PWC_WKTCR_WKOVF (0x1000U) +#define PWC_WKTCR_WKCKS_POS (13U) +#define PWC_WKTCR_WKCKS (0x6000U) +#define PWC_WKTCR_WKCKS_0 (0x2000U) +#define PWC_WKTCR_WKCKS_1 (0x4000U) +#define PWC_WKTCR_WKTCE_POS (15U) +#define PWC_WKTCR_WKTCE (0x8000U) + +/* Bit definition for PWC_PWRC0 register */ +#define PWC_PWRC0_PDMDS_POS (0U) +#define PWC_PWRC0_PDMDS (0x03U) +#define PWC_PWRC0_PDMDS_0 (0x01U) +#define PWC_PWRC0_PDMDS_1 (0x02U) +#define PWC_PWRC0_IORTN_POS (4U) +#define PWC_PWRC0_IORTN (0x30U) +#define PWC_PWRC0_IORTN_0 (0x10U) +#define PWC_PWRC0_IORTN_1 (0x20U) +#define PWC_PWRC0_PWDN_POS (7U) +#define PWC_PWRC0_PWDN (0x80U) + +/* Bit definition for PWC_PWRC1 register */ +#define PWC_PWRC1_VPLLSD_POS (0U) +#define PWC_PWRC1_VPLLSD (0x03U) +#define PWC_PWRC1_VPLLSD_0 (0x01U) +#define PWC_PWRC1_VPLLSD_1 (0x02U) +#define PWC_PWRC1_VHRCSD_POS (2U) +#define PWC_PWRC1_VHRCSD (0x04U) +#define PWC_PWRC1_PDTS_POS (3U) +#define PWC_PWRC1_PDTS (0x08U) +#define PWC_PWRC1_STPDAS_POS (6U) +#define PWC_PWRC1_STPDAS (0xC0U) +#define PWC_PWRC1_STPDAS_0 (0x40U) +#define PWC_PWRC1_STPDAS_1 (0x80U) + +/* Bit definition for PWC_PWRC2 register */ +#define PWC_PWRC2_DVS_POS (4U) +#define PWC_PWRC2_DVS (0x30U) +#define PWC_PWRC2_DVS_0 (0x10U) +#define PWC_PWRC2_DVS_1 (0x20U) + +/* Bit definition for PWC_PWRC3 register */ +#define PWC_PWRC3_DDAS (0x0FU) + +/* Bit definition for PWC_PWRC4 register */ +#define PWC_PWRC4_ADBUFE_POS (7U) +#define PWC_PWRC4_ADBUFE (0x80U) + +/* Bit definition for PWC_PVDCR0 register */ +#define PWC_PVDCR0_EXVCCINEN_POS (0U) +#define PWC_PVDCR0_EXVCCINEN (0x01U) +#define PWC_PVDCR0_PVD1EN_POS (5U) +#define PWC_PVDCR0_PVD1EN (0x20U) +#define PWC_PVDCR0_PVD2EN_POS (6U) +#define PWC_PVDCR0_PVD2EN (0x40U) + +/* Bit definition for PWC_PVDCR1 register */ +#define PWC_PVDCR1_PVD1IRE_POS (0U) +#define PWC_PVDCR1_PVD1IRE (0x01U) +#define PWC_PVDCR1_PVD1IRS_POS (1U) +#define PWC_PVDCR1_PVD1IRS (0x02U) +#define PWC_PVDCR1_PVD1CMPOE_POS (2U) +#define PWC_PVDCR1_PVD1CMPOE (0x04U) +#define PWC_PVDCR1_PVD2IRE_POS (4U) +#define PWC_PVDCR1_PVD2IRE (0x10U) +#define PWC_PVDCR1_PVD2IRS_POS (5U) +#define PWC_PVDCR1_PVD2IRS (0x20U) +#define PWC_PVDCR1_PVD2CMPOE_POS (6U) +#define PWC_PVDCR1_PVD2CMPOE (0x40U) + +/* Bit definition for PWC_PVDFCR register */ +#define PWC_PVDFCR_PVD1NFDIS_POS (0U) +#define PWC_PVDFCR_PVD1NFDIS (0x01U) +#define PWC_PVDFCR_PVD1NFCKS_POS (1U) +#define PWC_PVDFCR_PVD1NFCKS (0x06U) +#define PWC_PVDFCR_PVD1NFCKS_0 (0x02U) +#define PWC_PVDFCR_PVD1NFCKS_1 (0x04U) +#define PWC_PVDFCR_PVD2NFDIS_POS (4U) +#define PWC_PVDFCR_PVD2NFDIS (0x10U) +#define PWC_PVDFCR_PVD2NFCKS_POS (5U) +#define PWC_PVDFCR_PVD2NFCKS (0x60U) +#define PWC_PVDFCR_PVD2NFCKS_0 (0x20U) +#define PWC_PVDFCR_PVD2NFCKS_1 (0x40U) + +/* Bit definition for PWC_PVDLCR register */ +#define PWC_PVDLCR_PVD1LVL_POS (0U) +#define PWC_PVDLCR_PVD1LVL (0x07U) +#define PWC_PVDLCR_PVD2LVL_POS (4U) +#define PWC_PVDLCR_PVD2LVL (0x70U) + +/* Bit definition for PWC_PDWKE0 register */ +#define PWC_PDWKE0_WKE00_POS (0U) +#define PWC_PDWKE0_WKE00 (0x01U) +#define PWC_PDWKE0_WKE01_POS (1U) +#define PWC_PDWKE0_WKE01 (0x02U) +#define PWC_PDWKE0_WKE02_POS (2U) +#define PWC_PDWKE0_WKE02 (0x04U) +#define PWC_PDWKE0_WKE03_POS (3U) +#define PWC_PDWKE0_WKE03 (0x08U) +#define PWC_PDWKE0_WKE10_POS (4U) +#define PWC_PDWKE0_WKE10 (0x10U) +#define PWC_PDWKE0_WKE11_POS (5U) +#define PWC_PDWKE0_WKE11 (0x20U) +#define PWC_PDWKE0_WKE12_POS (6U) +#define PWC_PDWKE0_WKE12 (0x40U) +#define PWC_PDWKE0_WKE13_POS (7U) +#define PWC_PDWKE0_WKE13 (0x80U) + +/* Bit definition for PWC_PDWKE1 register */ +#define PWC_PDWKE1_WKE20_POS (0U) +#define PWC_PDWKE1_WKE20 (0x01U) +#define PWC_PDWKE1_WKE21_POS (1U) +#define PWC_PDWKE1_WKE21 (0x02U) +#define PWC_PDWKE1_WKE22_POS (2U) +#define PWC_PDWKE1_WKE22 (0x04U) +#define PWC_PDWKE1_WKE23_POS (3U) +#define PWC_PDWKE1_WKE23 (0x08U) +#define PWC_PDWKE1_WKE30_POS (4U) +#define PWC_PDWKE1_WKE30 (0x10U) +#define PWC_PDWKE1_WKE31_POS (5U) +#define PWC_PDWKE1_WKE31 (0x20U) +#define PWC_PDWKE1_WKE32_POS (6U) +#define PWC_PDWKE1_WKE32 (0x40U) +#define PWC_PDWKE1_WKE33_POS (7U) +#define PWC_PDWKE1_WKE33 (0x80U) + +/* Bit definition for PWC_PDWKE2 register */ +#define PWC_PDWKE2_VD1WKE_POS (0U) +#define PWC_PDWKE2_VD1WKE (0x01U) +#define PWC_PDWKE2_VD2WKE_POS (1U) +#define PWC_PDWKE2_VD2WKE (0x02U) +#define PWC_PDWKE2_RTCPRDWKE_POS (4U) +#define PWC_PDWKE2_RTCPRDWKE (0x10U) +#define PWC_PDWKE2_RTCALMWKE_POS (5U) +#define PWC_PDWKE2_RTCALMWKE (0x20U) +#define PWC_PDWKE2_WKTMWKE_POS (7U) +#define PWC_PDWKE2_WKTMWKE (0x80U) + +/* Bit definition for PWC_PDWKES register */ +#define PWC_PDWKES_WK0EGS_POS (0U) +#define PWC_PDWKES_WK0EGS (0x01U) +#define PWC_PDWKES_WK1EGS_POS (1U) +#define PWC_PDWKES_WK1EGS (0x02U) +#define PWC_PDWKES_WK2EGS_POS (2U) +#define PWC_PDWKES_WK2EGS (0x04U) +#define PWC_PDWKES_WK3EGS_POS (3U) +#define PWC_PDWKES_WK3EGS (0x08U) +#define PWC_PDWKES_VD1EGS_POS (4U) +#define PWC_PDWKES_VD1EGS (0x10U) +#define PWC_PDWKES_VD2EGS_POS (5U) +#define PWC_PDWKES_VD2EGS (0x20U) + +/* Bit definition for PWC_PDWKF0 register */ +#define PWC_PDWKF0_PTWK0F_POS (0U) +#define PWC_PDWKF0_PTWK0F (0x01U) +#define PWC_PDWKF0_PTWK1F_POS (1U) +#define PWC_PDWKF0_PTWK1F (0x02U) +#define PWC_PDWKF0_PTWK2F_POS (2U) +#define PWC_PDWKF0_PTWK2F (0x04U) +#define PWC_PDWKF0_PTWK3F_POS (3U) +#define PWC_PDWKF0_PTWK3F (0x08U) +#define PWC_PDWKF0_VD1WKF_POS (4U) +#define PWC_PDWKF0_VD1WKF (0x10U) +#define PWC_PDWKF0_VD2WKF_POS (5U) +#define PWC_PDWKF0_VD2WKF (0x20U) + +/* Bit definition for PWC_PDWKF1 register */ +#define PWC_PDWKF1_RXD0WKF_POS (3U) +#define PWC_PDWKF1_RXD0WKF (0x08U) +#define PWC_PDWKF1_RTCPRDWKF_POS (4U) +#define PWC_PDWKF1_RTCPRDWKF (0x10U) +#define PWC_PDWKF1_RTCALMWKF_POS (5U) +#define PWC_PDWKF1_RTCALMWKF (0x20U) +#define PWC_PDWKF1_WKTMWKF_POS (7U) +#define PWC_PDWKF1_WKTMWKF (0x80U) + +/* Bit definition for PWC_PWRC5 register */ +#define PWC_PWRC5_VVDRSD_POS (0U) +#define PWC_PWRC5_VVDRSD (0x01U) +#define PWC_PWRC5_SRAMBSD_POS (1U) +#define PWC_PWRC5_SRAMBSD (0x02U) +#define PWC_PWRC5_CSDIS_POS (7U) +#define PWC_PWRC5_CSDIS (0x80U) + +/* Bit definition for PWC_PWRC6 register */ +#define PWC_PWRC6_RTCCKSEL (0x03U) +#define PWC_PWRC6_RTCCKSEL_0 (0x01U) +#define PWC_PWRC6_RTCCKSEL_1 (0x02U) + +/* Bit definition for PWC_PVDICR register */ +#define PWC_PVDICR_PVD1EDGS_POS (1U) +#define PWC_PVDICR_PVD1EDGS (0x06U) +#define PWC_PVDICR_PVD1EDGS_0 (0x02U) +#define PWC_PVDICR_PVD1EDGS_1 (0x04U) +#define PWC_PVDICR_PVD2EDGS_POS (5U) +#define PWC_PVDICR_PVD2EDGS (0x60U) +#define PWC_PVDICR_PVD2EDGS_0 (0x20U) +#define PWC_PVDICR_PVD2EDGS_1 (0x40U) + +/* Bit definition for PWC_PVDDSR register */ +#define PWC_PVDDSR_PVD1MON_POS (0U) +#define PWC_PVDDSR_PVD1MON (0x01U) +#define PWC_PVDDSR_PVD1DETFLG_POS (1U) +#define PWC_PVDDSR_PVD1DETFLG (0x02U) +#define PWC_PVDDSR_PVD2MON_POS (4U) +#define PWC_PVDDSR_PVD2MON (0x10U) +#define PWC_PVDDSR_PVD2DETFLG_POS (5U) +#define PWC_PVDDSR_PVD2DETFLG (0x20U) + +/* Bit definition for PWC_RAMPC0 register */ +#define PWC_RAMPC0_RAMPDC0_POS (0U) +#define PWC_RAMPC0_RAMPDC0 (0x00000001UL) +#define PWC_RAMPC0_RAMPDC10_POS (10U) +#define PWC_RAMPC0_RAMPDC10 (0x00000400UL) + +/* Bit definition for PWC_RAMOPM register */ +#define PWC_RAMOPM_RAMOPM (0x0000FFFFUL) + +/* Bit definition for PWC_PRAMLPC register */ +#define PWC_PRAMLPC_PRAMPDC0_POS (0U) +#define PWC_PRAMLPC_PRAMPDC0 (0x00000001UL) +#define PWC_PRAMLPC_PRAMPDC2_POS (2U) +#define PWC_PRAMLPC_PRAMPDC2 (0x00000004UL) + +/* Bit definition for PWC_STPMCR register */ +#define PWC_STPMCR_FLNWT_POS (0U) +#define PWC_STPMCR_FLNWT (0x0001U) +#define PWC_STPMCR_CKSMRC_POS (1U) +#define PWC_STPMCR_CKSMRC (0x0002U) +#define PWC_STPMCR_EXBUSOE_POS (14U) +#define PWC_STPMCR_EXBUSOE (0x4000U) +#define PWC_STPMCR_STOP_POS (15U) +#define PWC_STPMCR_STOP (0x8000U) + +/* Bit definition for PWC_FPRC register */ +#define PWC_FPRC_FPRCB0_POS (0U) +#define PWC_FPRC_FPRCB0 (0x0001U) +#define PWC_FPRC_FPRCB1_POS (1U) +#define PWC_FPRC_FPRCB1 (0x0002U) +#define PWC_FPRC_FPRCB3_POS (3U) +#define PWC_FPRC_FPRCB3 (0x0008U) +#define PWC_FPRC_FPRCWE_POS (8U) +#define PWC_FPRC_FPRCWE (0xFF00U) + +/******************************************************************************* + Bit definition for Peripheral QSPI +*******************************************************************************/ +/* Bit definition for QSPI_CR register */ +#define QSPI_CR_MDSEL_POS (0U) +#define QSPI_CR_MDSEL (0x00000007UL) +#define QSPI_CR_PFE_POS (3U) +#define QSPI_CR_PFE (0x00000008UL) +#define QSPI_CR_PFSAE_POS (4U) +#define QSPI_CR_PFSAE (0x00000010UL) +#define QSPI_CR_DCOME_POS (5U) +#define QSPI_CR_DCOME (0x00000020UL) +#define QSPI_CR_XIPE_POS (6U) +#define QSPI_CR_XIPE (0x00000040UL) +#define QSPI_CR_SPIMD3_POS (7U) +#define QSPI_CR_SPIMD3 (0x00000080UL) +#define QSPI_CR_IPRSL_POS (8U) +#define QSPI_CR_IPRSL (0x00000300UL) +#define QSPI_CR_IPRSL_0 (0x00000100UL) +#define QSPI_CR_IPRSL_1 (0x00000200UL) +#define QSPI_CR_APRSL_POS (10U) +#define QSPI_CR_APRSL (0x00000C00UL) +#define QSPI_CR_APRSL_0 (0x00000400UL) +#define QSPI_CR_APRSL_1 (0x00000800UL) +#define QSPI_CR_DPRSL_POS (12U) +#define QSPI_CR_DPRSL (0x00003000UL) +#define QSPI_CR_DPRSL_0 (0x00001000UL) +#define QSPI_CR_DPRSL_1 (0x00002000UL) +#define QSPI_CR_DIV_POS (16U) +#define QSPI_CR_DIV (0x003F0000UL) + +/* Bit definition for QSPI_CSCR register */ +#define QSPI_CSCR_SSHW_POS (0U) +#define QSPI_CSCR_SSHW (0x0000000FUL) +#define QSPI_CSCR_SSNW_POS (4U) +#define QSPI_CSCR_SSNW (0x00000030UL) +#define QSPI_CSCR_SSNW_0 (0x00000010UL) +#define QSPI_CSCR_SSNW_1 (0x00000020UL) + +/* Bit definition for QSPI_FCR register */ +#define QSPI_FCR_AWSL_POS (0U) +#define QSPI_FCR_AWSL (0x00000003UL) +#define QSPI_FCR_AWSL_0 (0x00000001UL) +#define QSPI_FCR_AWSL_1 (0x00000002UL) +#define QSPI_FCR_FOUR_BIC_POS (2U) +#define QSPI_FCR_FOUR_BIC (0x00000004UL) +#define QSPI_FCR_SSNHD_POS (4U) +#define QSPI_FCR_SSNHD (0x00000010UL) +#define QSPI_FCR_SSNLD_POS (5U) +#define QSPI_FCR_SSNLD (0x00000020UL) +#define QSPI_FCR_WPOL_POS (6U) +#define QSPI_FCR_WPOL (0x00000040UL) +#define QSPI_FCR_DMCYCN_POS (8U) +#define QSPI_FCR_DMCYCN (0x00000F00UL) +#define QSPI_FCR_DUTY_POS (15U) +#define QSPI_FCR_DUTY (0x00008000UL) + +/* Bit definition for QSPI_SR register */ +#define QSPI_SR_BUSY_POS (0U) +#define QSPI_SR_BUSY (0x00000001UL) +#define QSPI_SR_XIPF_POS (6U) +#define QSPI_SR_XIPF (0x00000040UL) +#define QSPI_SR_RAER_POS (7U) +#define QSPI_SR_RAER (0x00000080UL) +#define QSPI_SR_PFNUM_POS (8U) +#define QSPI_SR_PFNUM (0x00001F00UL) +#define QSPI_SR_PFFUL_POS (14U) +#define QSPI_SR_PFFUL (0x00004000UL) +#define QSPI_SR_PFAN_POS (15U) +#define QSPI_SR_PFAN (0x00008000UL) + +/* Bit definition for QSPI_DCOM register */ +#define QSPI_DCOM_DCOM_POS (0U) +#define QSPI_DCOM_DCOM (0x000000FFUL) +#define QSPI_DCOM_DCOMPRSL_POS (8U) +#define QSPI_DCOM_DCOMPRSL (0x00000300UL) +#define QSPI_DCOM_DCOMPRSL_0 (0x00000100UL) +#define QSPI_DCOM_DCOMPRSL_1 (0x00000200UL) + +/* Bit definition for QSPI_CCMD register */ +#define QSPI_CCMD_RIC (0x000000FFUL) + +/* Bit definition for QSPI_XCMD register */ +#define QSPI_XCMD_XIPMC (0x000000FFUL) + +/* Bit definition for QSPI_SR2 register */ +#define QSPI_SR2_RAERCLR_POS (7U) +#define QSPI_SR2_RAERCLR (0x00000080UL) + +/* Bit definition for QSPI_EXAR register */ +#define QSPI_EXAR_EXADR_POS (26U) +#define QSPI_EXAR_EXADR (0xFC000000UL) + +/******************************************************************************* + Bit definition for Peripheral RMU +*******************************************************************************/ +/* Bit definition for RMU_FRST0 register */ +#define RMU_FRST0_KEY_POS (13U) +#define RMU_FRST0_KEY (0x00002000UL) +#define RMU_FRST0_DMA1_POS (14U) +#define RMU_FRST0_DMA1 (0x00004000UL) +#define RMU_FRST0_DMA2_POS (15U) +#define RMU_FRST0_DMA2 (0x00008000UL) +#define RMU_FRST0_FCM_POS (16U) +#define RMU_FRST0_FCM (0x00010000UL) +#define RMU_FRST0_AOS_POS (17U) +#define RMU_FRST0_AOS (0x00020000UL) +#define RMU_FRST0_CTC_POS (18U) +#define RMU_FRST0_CTC (0x00040000UL) +#define RMU_FRST0_AES_POS (20U) +#define RMU_FRST0_AES (0x00100000UL) +#define RMU_FRST0_HASH_POS (21U) +#define RMU_FRST0_HASH (0x00200000UL) +#define RMU_FRST0_TRNG_POS (22U) +#define RMU_FRST0_TRNG (0x00400000UL) +#define RMU_FRST0_CRC_POS (23U) +#define RMU_FRST0_CRC (0x00800000UL) +#define RMU_FRST0_DCU1_POS (24U) +#define RMU_FRST0_DCU1 (0x01000000UL) +#define RMU_FRST0_DCU2_POS (25U) +#define RMU_FRST0_DCU2 (0x02000000UL) +#define RMU_FRST0_DCU3_POS (26U) +#define RMU_FRST0_DCU3 (0x04000000UL) +#define RMU_FRST0_DCU4_POS (27U) +#define RMU_FRST0_DCU4 (0x08000000UL) + +/* Bit definition for RMU_FRST1 register */ +#define RMU_FRST1_QSPI_POS (3U) +#define RMU_FRST1_QSPI (0x00000008UL) +#define RMU_FRST1_SPI1_POS (16U) +#define RMU_FRST1_SPI1 (0x00010000UL) +#define RMU_FRST1_SPI2_POS (17U) +#define RMU_FRST1_SPI2 (0x00020000UL) +#define RMU_FRST1_SPI3_POS (18U) +#define RMU_FRST1_SPI3 (0x00040000UL) + +/* Bit definition for RMU_FRST2 register */ +#define RMU_FRST2_TMR6_POS (0U) +#define RMU_FRST2_TMR6 (0x00000001UL) +#define RMU_FRST2_TMR4_POS (10U) +#define RMU_FRST2_TMR4 (0x00000400UL) +#define RMU_FRST2_TMR0_POS (12U) +#define RMU_FRST2_TMR0 (0x00001000UL) +#define RMU_FRST2_EMB_POS (15U) +#define RMU_FRST2_EMB (0x00008000UL) +#define RMU_FRST2_TMRA_POS (20U) +#define RMU_FRST2_TMRA (0x00100000UL) + +/* Bit definition for RMU_FRST3 register */ +#define RMU_FRST3_ADC1_POS (0U) +#define RMU_FRST3_ADC1 (0x00000001UL) +#define RMU_FRST3_ADC2_POS (1U) +#define RMU_FRST3_ADC2 (0x00000002UL) +#define RMU_FRST3_ADC3_POS (2U) +#define RMU_FRST3_ADC3 (0x00000004UL) +#define RMU_FRST3_DAC_POS (4U) +#define RMU_FRST3_DAC (0x00000010UL) +#define RMU_FRST3_CMP12_POS (8U) +#define RMU_FRST3_CMP12 (0x00000100UL) +#define RMU_FRST3_CMP34_POS (9U) +#define RMU_FRST3_CMP34 (0x00000200UL) +#define RMU_FRST3_SMC_POS (16U) +#define RMU_FRST3_SMC (0x00010000UL) +#define RMU_FRST3_USART1_POS (20U) +#define RMU_FRST3_USART1 (0x00100000UL) +#define RMU_FRST3_USART2_POS (21U) +#define RMU_FRST3_USART2 (0x00200000UL) +#define RMU_FRST3_USART3_POS (22U) +#define RMU_FRST3_USART3 (0x00400000UL) +#define RMU_FRST3_USART4_POS (23U) +#define RMU_FRST3_USART4 (0x00800000UL) +#define RMU_FRST3_USART5_POS (24U) +#define RMU_FRST3_USART5 (0x01000000UL) +#define RMU_FRST3_USART6_POS (25U) +#define RMU_FRST3_USART6 (0x02000000UL) + +/* Bit definition for RMU_PRSTCR0 register */ +#define RMU_PRSTCR0_LKUPREN_POS (5U) +#define RMU_PRSTCR0_LKUPREN (0x20U) + +/* Bit definition for RMU_RSTF0 register */ +#define RMU_RSTF0_PORF_POS (0U) +#define RMU_RSTF0_PORF (0x00000001UL) +#define RMU_RSTF0_PINRF_POS (1U) +#define RMU_RSTF0_PINRF (0x00000002UL) +#define RMU_RSTF0_BORF_POS (2U) +#define RMU_RSTF0_BORF (0x00000004UL) +#define RMU_RSTF0_PVD1RF_POS (3U) +#define RMU_RSTF0_PVD1RF (0x00000008UL) +#define RMU_RSTF0_PVD2RF_POS (4U) +#define RMU_RSTF0_PVD2RF (0x00000010UL) +#define RMU_RSTF0_WDRF_POS (5U) +#define RMU_RSTF0_WDRF (0x00000020UL) +#define RMU_RSTF0_SWDRF_POS (6U) +#define RMU_RSTF0_SWDRF (0x00000040UL) +#define RMU_RSTF0_PDRF_POS (7U) +#define RMU_RSTF0_PDRF (0x00000080UL) +#define RMU_RSTF0_SWRF_POS (8U) +#define RMU_RSTF0_SWRF (0x00000100UL) +#define RMU_RSTF0_MPUERF_POS (9U) +#define RMU_RSTF0_MPUERF (0x00000200UL) +#define RMU_RSTF0_RAPERF_POS (10U) +#define RMU_RSTF0_RAPERF (0x00000400UL) +#define RMU_RSTF0_RAECRF_POS (11U) +#define RMU_RSTF0_RAECRF (0x00000800UL) +#define RMU_RSTF0_CKFERF_POS (12U) +#define RMU_RSTF0_CKFERF (0x00001000UL) +#define RMU_RSTF0_XTALERF_POS (13U) +#define RMU_RSTF0_XTALERF (0x00002000UL) +#define RMU_RSTF0_LKUPRF_POS (14U) +#define RMU_RSTF0_LKUPRF (0x00004000UL) +#define RMU_RSTF0_MULTIRF_POS (30U) +#define RMU_RSTF0_MULTIRF (0x40000000UL) +#define RMU_RSTF0_CLRF_POS (31U) +#define RMU_RSTF0_CLRF (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral RTC +*******************************************************************************/ +/* Bit definition for RTC_CR0 register */ +#define RTC_CR0_RESET (0x01U) + +/* Bit definition for RTC_CR1 register */ +#define RTC_CR1_PRDS_POS (0U) +#define RTC_CR1_PRDS (0x07U) +#define RTC_CR1_AMPM_POS (3U) +#define RTC_CR1_AMPM (0x08U) +#define RTC_CR1_ONEHZOE_POS (5U) +#define RTC_CR1_ONEHZOE (0x20U) +#define RTC_CR1_ONEHZSEL_POS (6U) +#define RTC_CR1_ONEHZSEL (0x40U) +#define RTC_CR1_START_POS (7U) +#define RTC_CR1_START (0x80U) + +/* Bit definition for RTC_CR2 register */ +#define RTC_CR2_RWREQ_POS (0U) +#define RTC_CR2_RWREQ (0x01U) +#define RTC_CR2_RWEN_POS (1U) +#define RTC_CR2_RWEN (0x02U) +#define RTC_CR2_PRDF_POS (2U) +#define RTC_CR2_PRDF (0x04U) +#define RTC_CR2_ALMF_POS (3U) +#define RTC_CR2_ALMF (0x08U) +#define RTC_CR2_PRDIE_POS (5U) +#define RTC_CR2_PRDIE (0x20U) +#define RTC_CR2_ALMIE_POS (6U) +#define RTC_CR2_ALMIE (0x40U) +#define RTC_CR2_ALME_POS (7U) +#define RTC_CR2_ALME (0x80U) + +/* Bit definition for RTC_CR3 register */ +#define RTC_CR3_LRCEN_POS (4U) +#define RTC_CR3_LRCEN (0x10U) +#define RTC_CR3_RCKSEL_POS (7U) +#define RTC_CR3_RCKSEL (0x80U) + +/* Bit definition for RTC_SEC register */ +#define RTC_SEC_SECU_POS (0U) +#define RTC_SEC_SECU (0x0FU) +#define RTC_SEC_SECD_POS (4U) +#define RTC_SEC_SECD (0x70U) + +/* Bit definition for RTC_MIN register */ +#define RTC_MIN_MINU_POS (0U) +#define RTC_MIN_MINU (0x0FU) +#define RTC_MIN_MIND_POS (4U) +#define RTC_MIN_MIND (0x70U) + +/* Bit definition for RTC_HOUR register */ +#define RTC_HOUR_HOURU_POS (0U) +#define RTC_HOUR_HOURU (0x0FU) +#define RTC_HOUR_HOURD_POS (4U) +#define RTC_HOUR_HOURD (0x30U) +#define RTC_HOUR_HOURD_0 (0x10U) +#define RTC_HOUR_HOURD_1 (0x20U) + +/* Bit definition for RTC_WEEK register */ +#define RTC_WEEK_WEEK (0x07U) + +/* Bit definition for RTC_DAY register */ +#define RTC_DAY_DAYU_POS (0U) +#define RTC_DAY_DAYU (0x0FU) +#define RTC_DAY_DAYD_POS (4U) +#define RTC_DAY_DAYD (0x30U) +#define RTC_DAY_DAYD_0 (0x10U) +#define RTC_DAY_DAYD_1 (0x20U) + +/* Bit definition for RTC_MON register */ +#define RTC_MON_MON (0x1FU) + +/* Bit definition for RTC_YEAR register */ +#define RTC_YEAR_YEARU_POS (0U) +#define RTC_YEAR_YEARU (0x0FU) +#define RTC_YEAR_YEARD_POS (4U) +#define RTC_YEAR_YEARD (0xF0U) + +/* Bit definition for RTC_ALMMIN register */ +#define RTC_ALMMIN_ALMMINU_POS (0U) +#define RTC_ALMMIN_ALMMINU (0x0FU) +#define RTC_ALMMIN_ALMMIND_POS (4U) +#define RTC_ALMMIN_ALMMIND (0x70U) + +/* Bit definition for RTC_ALMHOUR register */ +#define RTC_ALMHOUR_ALMHOURU_POS (0U) +#define RTC_ALMHOUR_ALMHOURU (0x0FU) +#define RTC_ALMHOUR_ALMHOURD_POS (4U) +#define RTC_ALMHOUR_ALMHOURD (0x30U) +#define RTC_ALMHOUR_ALMHOURD_0 (0x10U) +#define RTC_ALMHOUR_ALMHOURD_1 (0x20U) + +/* Bit definition for RTC_ALMWEEK register */ +#define RTC_ALMWEEK_ALMWEEK (0x7FU) + +/* Bit definition for RTC_ERRCRH register */ +#define RTC_ERRCRH_COMP8_POS (0U) +#define RTC_ERRCRH_COMP8 (0x01U) +#define RTC_ERRCRH_COMPEN_POS (7U) +#define RTC_ERRCRH_COMPEN (0x80U) + +/* Bit definition for RTC_ERRCRL register */ +#define RTC_ERRCRL (0xFFU) + +/******************************************************************************* + Bit definition for Peripheral SMC +*******************************************************************************/ +/* Bit definition for SMC_STSR register */ +#define SMC_STSR_STATUS (0x00000001UL) + +/* Bit definition for SMC_STCR0 register */ +#define SMC_STCR0_LPWIR_POS (2U) +#define SMC_STCR0_LPWIR (0x00000004UL) + +/* Bit definition for SMC_STCR1 register */ +#define SMC_STCR1_LPWOR_POS (2U) +#define SMC_STCR1_LPWOR (0x00000004UL) + +/* Bit definition for SMC_CMDR register */ +#define SMC_CMDR_CMDADD_POS (0U) +#define SMC_CMDR_CMDADD (0x000FFFFFUL) +#define SMC_CMDR_CRES_POS (20U) +#define SMC_CMDR_CRES (0x00100000UL) +#define SMC_CMDR_CMD_POS (21U) +#define SMC_CMDR_CMD (0x00600000UL) +#define SMC_CMDR_CMD_0 (0x00200000UL) +#define SMC_CMDR_CMD_1 (0x00400000UL) +#define SMC_CMDR_CMDCHIP_POS (23U) +#define SMC_CMDR_CMDCHIP (0x03800000UL) + +/* Bit definition for SMC_TMCR register */ +#define SMC_TMCR_T_RC_POS (0U) +#define SMC_TMCR_T_RC (0x0000000FUL) +#define SMC_TMCR_T_WC_POS (4U) +#define SMC_TMCR_T_WC (0x000000F0UL) +#define SMC_TMCR_T_CEOE_POS (8U) +#define SMC_TMCR_T_CEOE (0x00000700UL) +#define SMC_TMCR_T_WP_POS (12U) +#define SMC_TMCR_T_WP (0x00007000UL) +#define SMC_TMCR_T_TR_POS (20U) +#define SMC_TMCR_T_TR (0x00700000UL) +#define SMC_TMCR_T_ADV_POS (24U) +#define SMC_TMCR_T_ADV (0x07000000UL) + +/* Bit definition for SMC_CPCR register */ +#define SMC_CPCR_RSYN_POS (0U) +#define SMC_CPCR_RSYN (0x00000001UL) +#define SMC_CPCR_WSYN_POS (4U) +#define SMC_CPCR_WSYN (0x00000010UL) +#define SMC_CPCR_MW_POS (8U) +#define SMC_CPCR_MW (0x00000300UL) +#define SMC_CPCR_MW_0 (0x00000100UL) +#define SMC_CPCR_MW_1 (0x00000200UL) +#define SMC_CPCR_BAAS_POS (10U) +#define SMC_CPCR_BAAS (0x00000400UL) +#define SMC_CPCR_ADVS_POS (11U) +#define SMC_CPCR_ADVS (0x00000800UL) +#define SMC_CPCR_BLSS_POS (12U) +#define SMC_CPCR_BLSS (0x00001000UL) + +/* Bit definition for SMC_RFTR register */ +#define SMC_RFTR_REFPRD (0x0000000FUL) + +/* Bit definition for SMC_TMSR register */ +#define SMC_TMSR_T_RC_POS (0U) +#define SMC_TMSR_T_RC (0x0000000FUL) +#define SMC_TMSR_T_WC_POS (4U) +#define SMC_TMSR_T_WC (0x000000F0UL) +#define SMC_TMSR_T_CEOE_POS (8U) +#define SMC_TMSR_T_CEOE (0x00000700UL) +#define SMC_TMSR_T_WP_POS (12U) +#define SMC_TMSR_T_WP (0x00007000UL) +#define SMC_TMSR_T_TR_POS (20U) +#define SMC_TMSR_T_TR (0x00700000UL) +#define SMC_TMSR_T_ADV_POS (24U) +#define SMC_TMSR_T_ADV (0x07000000UL) + +/* Bit definition for SMC_CPSR register */ +#define SMC_CPSR_RSYN_POS (0U) +#define SMC_CPSR_RSYN (0x00000001UL) +#define SMC_CPSR_WSYN_POS (4U) +#define SMC_CPSR_WSYN (0x00000010UL) +#define SMC_CPSR_MW_POS (8U) +#define SMC_CPSR_MW (0x00000300UL) +#define SMC_CPSR_BAAS_POS (10U) +#define SMC_CPSR_BAAS (0x00000400UL) +#define SMC_CPSR_ADVS_POS (11U) +#define SMC_CPSR_ADVS (0x00000800UL) +#define SMC_CPSR_BLSS_POS (12U) +#define SMC_CPSR_BLSS (0x00001000UL) +#define SMC_CPSR_ADDMSK_POS (16U) +#define SMC_CPSR_ADDMSK (0x00FF0000UL) +#define SMC_CPSR_ADDMAT_POS (24U) +#define SMC_CPSR_ADDMAT (0xFF000000UL) + +/* Bit definition for SMC_BACR register */ +#define SMC_BACR_MUXMD_POS (4U) +#define SMC_BACR_MUXMD (0x00000010UL) +#define SMC_BACR_CKSEL_POS (14U) +#define SMC_BACR_CKSEL (0x0000C000UL) +#define SMC_BACR_CKSEL_0 (0x00004000UL) +#define SMC_BACR_CKSEL_1 (0x00008000UL) + +/* Bit definition for SMC_CSCR0 register */ +#define SMC_CSCR0_ADDMSK0 (0x000000FFUL) + +/* Bit definition for SMC_CSCR1 register */ +#define SMC_CSCR1_ADDMAT0 (0x000000FFUL) + +/******************************************************************************* + Bit definition for Peripheral SPI +*******************************************************************************/ +/* Bit definition for SPI_DR register */ +#define SPI_DR (0xFFFFFFFFUL) + +/* Bit definition for SPI_CR register */ +#define SPI_CR_SPIMDS_POS (0U) +#define SPI_CR_SPIMDS (0x00000001UL) +#define SPI_CR_TXMDS_POS (1U) +#define SPI_CR_TXMDS (0x00000002UL) +#define SPI_CR_MSTR_POS (3U) +#define SPI_CR_MSTR (0x00000008UL) +#define SPI_CR_SPLPBK_POS (4U) +#define SPI_CR_SPLPBK (0x00000010UL) +#define SPI_CR_SPLPBK2_POS (5U) +#define SPI_CR_SPLPBK2 (0x00000020UL) +#define SPI_CR_SPE_POS (6U) +#define SPI_CR_SPE (0x00000040UL) +#define SPI_CR_CSUSPE_POS (7U) +#define SPI_CR_CSUSPE (0x00000080UL) +#define SPI_CR_EIE_POS (8U) +#define SPI_CR_EIE (0x00000100UL) +#define SPI_CR_TXIE_POS (9U) +#define SPI_CR_TXIE (0x00000200UL) +#define SPI_CR_RXIE_POS (10U) +#define SPI_CR_RXIE (0x00000400UL) +#define SPI_CR_IDIE_POS (11U) +#define SPI_CR_IDIE (0x00000800UL) +#define SPI_CR_MODFE_POS (12U) +#define SPI_CR_MODFE (0x00001000UL) +#define SPI_CR_PATE_POS (13U) +#define SPI_CR_PATE (0x00002000UL) +#define SPI_CR_PAOE_POS (14U) +#define SPI_CR_PAOE (0x00004000UL) +#define SPI_CR_PAE_POS (15U) +#define SPI_CR_PAE (0x00008000UL) + +/* Bit definition for SPI_CFG1 register */ +#define SPI_CFG1_FTHLV_POS (0U) +#define SPI_CFG1_FTHLV (0x00000003UL) +#define SPI_CFG1_FTHLV_0 (0x00000001UL) +#define SPI_CFG1_FTHLV_1 (0x00000002UL) +#define SPI_CFG1_CTMDS_POS (2U) +#define SPI_CFG1_CTMDS (0x00000004UL) +#define SPI_CFG1_SPRDTD_POS (6U) +#define SPI_CFG1_SPRDTD (0x00000040UL) +#define SPI_CFG1_SS0PV_POS (8U) +#define SPI_CFG1_SS0PV (0x00000100UL) +#define SPI_CFG1_SS1PV_POS (9U) +#define SPI_CFG1_SS1PV (0x00000200UL) +#define SPI_CFG1_SS2PV_POS (10U) +#define SPI_CFG1_SS2PV (0x00000400UL) +#define SPI_CFG1_SS3PV_POS (11U) +#define SPI_CFG1_SS3PV (0x00000800UL) +#define SPI_CFG1_CLKDIV_POS (12U) +#define SPI_CFG1_CLKDIV (0x0000F000UL) +#define SPI_CFG1_CLKDIV_0 (0x00001000UL) +#define SPI_CFG1_CLKDIV_1 (0x00002000UL) +#define SPI_CFG1_CLKDIV_2 (0x00004000UL) +#define SPI_CFG1_CLKDIV_3 (0x00008000UL) +#define SPI_CFG1_MSSI_POS (20U) +#define SPI_CFG1_MSSI (0x00700000UL) +#define SPI_CFG1_MSSI_0 (0x00100000UL) +#define SPI_CFG1_MSSI_1 (0x00200000UL) +#define SPI_CFG1_MSSI_2 (0x00400000UL) +#define SPI_CFG1_MSSDL_POS (24U) +#define SPI_CFG1_MSSDL (0x07000000UL) +#define SPI_CFG1_MSSDL_0 (0x01000000UL) +#define SPI_CFG1_MSSDL_1 (0x02000000UL) +#define SPI_CFG1_MSSDL_2 (0x04000000UL) +#define SPI_CFG1_MIDI_POS (28U) +#define SPI_CFG1_MIDI (0x70000000UL) +#define SPI_CFG1_MIDI_0 (0x10000000UL) +#define SPI_CFG1_MIDI_1 (0x20000000UL) +#define SPI_CFG1_MIDI_2 (0x40000000UL) + +/* Bit definition for SPI_SR register */ +#define SPI_SR_OVRERF_POS (0U) +#define SPI_SR_OVRERF (0x00000001UL) +#define SPI_SR_IDLNF_POS (1U) +#define SPI_SR_IDLNF (0x00000002UL) +#define SPI_SR_MODFERF_POS (2U) +#define SPI_SR_MODFERF (0x00000004UL) +#define SPI_SR_PERF_POS (3U) +#define SPI_SR_PERF (0x00000008UL) +#define SPI_SR_UDRERF_POS (4U) +#define SPI_SR_UDRERF (0x00000010UL) +#define SPI_SR_TDEF_POS (5U) +#define SPI_SR_TDEF (0x00000020UL) +#define SPI_SR_RDFF_POS (7U) +#define SPI_SR_RDFF (0x00000080UL) + +/* Bit definition for SPI_CFG2 register */ +#define SPI_CFG2_CPHA_POS (0U) +#define SPI_CFG2_CPHA (0x00000001UL) +#define SPI_CFG2_CPOL_POS (1U) +#define SPI_CFG2_CPOL (0x00000002UL) +#define SPI_CFG2_MBR_POS (2U) +#define SPI_CFG2_MBR (0x0000000CUL) +#define SPI_CFG2_MBR_0 (0x00000004UL) +#define SPI_CFG2_MBR_1 (0x00000008UL) +#define SPI_CFG2_SSA_POS (5U) +#define SPI_CFG2_SSA (0x000000E0UL) +#define SPI_CFG2_SSA_0 (0x00000020UL) +#define SPI_CFG2_SSA_1 (0x00000040UL) +#define SPI_CFG2_SSA_2 (0x00000080UL) +#define SPI_CFG2_DSIZE_POS (8U) +#define SPI_CFG2_DSIZE (0x00000F00UL) +#define SPI_CFG2_DSIZE_0 (0x00000100UL) +#define SPI_CFG2_DSIZE_1 (0x00000200UL) +#define SPI_CFG2_DSIZE_2 (0x00000400UL) +#define SPI_CFG2_DSIZE_3 (0x00000800UL) +#define SPI_CFG2_LSBF_POS (12U) +#define SPI_CFG2_LSBF (0x00001000UL) +#define SPI_CFG2_MIDIE_POS (13U) +#define SPI_CFG2_MIDIE (0x00002000UL) +#define SPI_CFG2_MSSDLE_POS (14U) +#define SPI_CFG2_MSSDLE (0x00004000UL) +#define SPI_CFG2_MSSIE_POS (15U) +#define SPI_CFG2_MSSIE (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral SRAMC +*******************************************************************************/ +/* Bit definition for SRAMC_WTCR register */ +#define SRAMC_WTCR_SRAM0RWT_POS (0U) +#define SRAMC_WTCR_SRAM0RWT (0x00000007UL) +#define SRAMC_WTCR_SRAM0WWT_POS (4U) +#define SRAMC_WTCR_SRAM0WWT (0x00000070UL) +#define SRAMC_WTCR_SRAMHRWT_POS (16U) +#define SRAMC_WTCR_SRAMHRWT (0x00070000UL) +#define SRAMC_WTCR_SRAMHWWT_POS (20U) +#define SRAMC_WTCR_SRAMHWWT (0x00700000UL) +#define SRAMC_WTCR_SRAMBRWT_POS (24U) +#define SRAMC_WTCR_SRAMBRWT (0x07000000UL) +#define SRAMC_WTCR_SRAMBWWT_POS (28U) +#define SRAMC_WTCR_SRAMBWWT (0x70000000UL) + +/* Bit definition for SRAMC_WTPR register */ +#define SRAMC_WTPR_WTPRC_POS (0U) +#define SRAMC_WTPR_WTPRC (0x00000001UL) +#define SRAMC_WTPR_WTPRKW_POS (1U) +#define SRAMC_WTPR_WTPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKCR register */ +#define SRAMC_CKCR_PYOAD_POS (0U) +#define SRAMC_CKCR_PYOAD (0x00000001UL) +#define SRAMC_CKCR_ECCOAD_POS (16U) +#define SRAMC_CKCR_ECCOAD (0x00010000UL) +#define SRAMC_CKCR_BECCOAD_POS (17U) +#define SRAMC_CKCR_BECCOAD (0x00020000UL) +#define SRAMC_CKCR_ECCMOD_POS (24U) +#define SRAMC_CKCR_ECCMOD (0x03000000UL) +#define SRAMC_CKCR_ECCMOD_0 (0x01000000UL) +#define SRAMC_CKCR_ECCMOD_1 (0x02000000UL) +#define SRAMC_CKCR_BECCMOD_POS (26U) +#define SRAMC_CKCR_BECCMOD (0x0C000000UL) +#define SRAMC_CKCR_BECCMOD_0 (0x04000000UL) +#define SRAMC_CKCR_BECCMOD_1 (0x08000000UL) + +/* Bit definition for SRAMC_CKPR register */ +#define SRAMC_CKPR_CKPRC_POS (0U) +#define SRAMC_CKPR_CKPRC (0x00000001UL) +#define SRAMC_CKPR_CKPRKW_POS (1U) +#define SRAMC_CKPR_CKPRKW (0x000000FEUL) + +/* Bit definition for SRAMC_CKSR register */ +#define SRAMC_CKSR_SRAMH_PYERR_POS (3U) +#define SRAMC_CKSR_SRAMH_PYERR (0x00000008UL) +#define SRAMC_CKSR_SRAM0_1ERR_POS (4U) +#define SRAMC_CKSR_SRAM0_1ERR (0x00000010UL) +#define SRAMC_CKSR_SRAM0_2ERR_POS (5U) +#define SRAMC_CKSR_SRAM0_2ERR (0x00000020UL) +#define SRAMC_CKSR_SRAMB_1ERR_POS (6U) +#define SRAMC_CKSR_SRAMB_1ERR (0x00000040UL) +#define SRAMC_CKSR_SRAMB_2ERR_POS (7U) +#define SRAMC_CKSR_SRAMB_2ERR (0x00000080UL) +#define SRAMC_CKSR_CACHE_PYERR_POS (8U) +#define SRAMC_CKSR_CACHE_PYERR (0x00000100UL) + +/* Bit definition for SRAMC_SRAM0_EIEN register */ +#define SRAMC_SRAM0_EIEN_EIEN (0x00000001UL) + +/* Bit definition for SRAMC_SRAM0_EIBIT0 register */ +#define SRAMC_SRAM0_EIBIT0 (0xFFFFFFFFUL) + +/* Bit definition for SRAMC_SRAM0_EIBIT1 register */ +#define SRAMC_SRAM0_EIBIT1_EIBIT (0x0000007FUL) + +/* Bit definition for SRAMC_SRAM0_ECCERRADDR register */ +#define SRAMC_SRAM0_ECCERRADDR_ECCERRADDR (0x00007FFFUL) + +/* Bit definition for SRAMC_SRAMB_EIEN register */ +#define SRAMC_SRAMB_EIEN_EIEN (0x00000001UL) + +/* Bit definition for SRAMC_SRAMB_EIBIT0 register */ +#define SRAMC_SRAMB_EIBIT0 (0xFFFFFFFFUL) + +/* Bit definition for SRAMC_SRAMB_EIBIT1 register */ +#define SRAMC_SRAMB_EIBIT1_EIBIT (0x0000007FUL) + +/* Bit definition for SRAMC_SRAMB_ECCERRADDR register */ +#define SRAMC_SRAMB_ECCERRADDR_ECCERRADDR (0x00000FFFUL) + +/******************************************************************************* + Bit definition for Peripheral SWDT +*******************************************************************************/ +/* Bit definition for SWDT_CR register */ +#define SWDT_CR_PERI_POS (0U) +#define SWDT_CR_PERI (0x00000003UL) +#define SWDT_CR_PERI_0 (0x00000001UL) +#define SWDT_CR_PERI_1 (0x00000002UL) +#define SWDT_CR_CKS_POS (4U) +#define SWDT_CR_CKS (0x000000F0UL) +#define SWDT_CR_WDPT_POS (8U) +#define SWDT_CR_WDPT (0x00000F00UL) +#define SWDT_CR_SLPOFF_POS (16U) +#define SWDT_CR_SLPOFF (0x00010000UL) +#define SWDT_CR_ITS_POS (31U) +#define SWDT_CR_ITS (0x80000000UL) + +/* Bit definition for SWDT_SR register */ +#define SWDT_SR_CNT_POS (0U) +#define SWDT_SR_CNT (0x0000FFFFUL) +#define SWDT_SR_UDF_POS (16U) +#define SWDT_SR_UDF (0x00010000UL) +#define SWDT_SR_REF_POS (17U) +#define SWDT_SR_REF (0x00020000UL) + +/* Bit definition for SWDT_RR register */ +#define SWDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral TMR0 +*******************************************************************************/ +/* Bit definition for TMR0_CNTAR register */ +#define TMR0_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR0_CNTBR register */ +#define TMR0_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPAR register */ +#define TMR0_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPBR register */ +#define TMR0_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR0_BCONR register */ +#define TMR0_BCONR_CSTA_POS (0U) +#define TMR0_BCONR_CSTA (0x00000001UL) +#define TMR0_BCONR_CAPMDA_POS (1U) +#define TMR0_BCONR_CAPMDA (0x00000002UL) +#define TMR0_BCONR_CMENA_POS (2U) +#define TMR0_BCONR_CMENA (0x00000004UL) +#define TMR0_BCONR_OVENA_POS (3U) +#define TMR0_BCONR_OVENA (0x00000008UL) +#define TMR0_BCONR_CKDIVA_POS (4U) +#define TMR0_BCONR_CKDIVA (0x000000F0UL) +#define TMR0_BCONR_SYNSA_POS (8U) +#define TMR0_BCONR_SYNSA (0x00000100UL) +#define TMR0_BCONR_SYNCLKA_POS (9U) +#define TMR0_BCONR_SYNCLKA (0x00000200UL) +#define TMR0_BCONR_ASYNCLKA_POS (10U) +#define TMR0_BCONR_ASYNCLKA (0x00000400UL) +#define TMR0_BCONR_HSTAA_POS (12U) +#define TMR0_BCONR_HSTAA (0x00001000UL) +#define TMR0_BCONR_HSTPA_POS (13U) +#define TMR0_BCONR_HSTPA (0x00002000UL) +#define TMR0_BCONR_HCLEA_POS (14U) +#define TMR0_BCONR_HCLEA (0x00004000UL) +#define TMR0_BCONR_HICPA_POS (15U) +#define TMR0_BCONR_HICPA (0x00008000UL) +#define TMR0_BCONR_CSTB_POS (16U) +#define TMR0_BCONR_CSTB (0x00010000UL) +#define TMR0_BCONR_CAPMDB_POS (17U) +#define TMR0_BCONR_CAPMDB (0x00020000UL) +#define TMR0_BCONR_CMENB_POS (18U) +#define TMR0_BCONR_CMENB (0x00040000UL) +#define TMR0_BCONR_OVENB_POS (19U) +#define TMR0_BCONR_OVENB (0x00080000UL) +#define TMR0_BCONR_CKDIVB_POS (20U) +#define TMR0_BCONR_CKDIVB (0x00F00000UL) +#define TMR0_BCONR_SYNSB_POS (24U) +#define TMR0_BCONR_SYNSB (0x01000000UL) +#define TMR0_BCONR_SYNCLKB_POS (25U) +#define TMR0_BCONR_SYNCLKB (0x02000000UL) +#define TMR0_BCONR_ASYNCLKB_POS (26U) +#define TMR0_BCONR_ASYNCLKB (0x04000000UL) +#define TMR0_BCONR_HSTAB_POS (28U) +#define TMR0_BCONR_HSTAB (0x10000000UL) +#define TMR0_BCONR_HSTPB_POS (29U) +#define TMR0_BCONR_HSTPB (0x20000000UL) +#define TMR0_BCONR_HCLEB_POS (30U) +#define TMR0_BCONR_HCLEB (0x40000000UL) +#define TMR0_BCONR_HICPB_POS (31U) +#define TMR0_BCONR_HICPB (0x80000000UL) + +/* Bit definition for TMR0_STFLR register */ +#define TMR0_STFLR_CMFA_POS (0U) +#define TMR0_STFLR_CMFA (0x00000001UL) +#define TMR0_STFLR_OVFA_POS (1U) +#define TMR0_STFLR_OVFA (0x00000002UL) +#define TMR0_STFLR_ICPA_POS (2U) +#define TMR0_STFLR_ICPA (0x00000004UL) +#define TMR0_STFLR_CMFB_POS (16U) +#define TMR0_STFLR_CMFB (0x00010000UL) +#define TMR0_STFLR_OVFB_POS (17U) +#define TMR0_STFLR_OVFB (0x00020000UL) +#define TMR0_STFLR_ICPB_POS (18U) +#define TMR0_STFLR_ICPB (0x00040000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR4 +*******************************************************************************/ +/* Bit definition for TMR4_OCCRUH register */ +#define TMR4_OCCRUH (0xFFFFU) + +/* Bit definition for TMR4_OCCRUL register */ +#define TMR4_OCCRUL (0xFFFFU) + +/* Bit definition for TMR4_OCCRVH register */ +#define TMR4_OCCRVH (0xFFFFU) + +/* Bit definition for TMR4_OCCRVL register */ +#define TMR4_OCCRVL (0xFFFFU) + +/* Bit definition for TMR4_OCCRWH register */ +#define TMR4_OCCRWH (0xFFFFU) + +/* Bit definition for TMR4_OCCRWL register */ +#define TMR4_OCCRWL (0xFFFFU) + +/* Bit definition for TMR4_OCCRXH register */ +#define TMR4_OCCRXH (0xFFFFU) + +/* Bit definition for TMR4_OCCRXL register */ +#define TMR4_OCCRXL (0xFFFFU) + +/* Bit definition for TMR4_OCSR register */ +#define TMR4_OCSR_OCEH_POS (0U) +#define TMR4_OCSR_OCEH (0x0001U) +#define TMR4_OCSR_OCEL_POS (1U) +#define TMR4_OCSR_OCEL (0x0002U) +#define TMR4_OCSR_OCPH_POS (2U) +#define TMR4_OCSR_OCPH (0x0004U) +#define TMR4_OCSR_OCPL_POS (3U) +#define TMR4_OCSR_OCPL (0x0008U) +#define TMR4_OCSR_OCIEH_POS (4U) +#define TMR4_OCSR_OCIEH (0x0010U) +#define TMR4_OCSR_OCIEL_POS (5U) +#define TMR4_OCSR_OCIEL (0x0020U) +#define TMR4_OCSR_OCFH_POS (6U) +#define TMR4_OCSR_OCFH (0x0040U) +#define TMR4_OCSR_OCFL_POS (7U) +#define TMR4_OCSR_OCFL (0x0080U) + +/* Bit definition for TMR4_OCER register */ +#define TMR4_OCER_CHBUFEN_POS (0U) +#define TMR4_OCER_CHBUFEN (0x0003U) +#define TMR4_OCER_CHBUFEN_0 (0x0001U) +#define TMR4_OCER_CHBUFEN_1 (0x0002U) +#define TMR4_OCER_CLBUFEN_POS (2U) +#define TMR4_OCER_CLBUFEN (0x000CU) +#define TMR4_OCER_CLBUFEN_0 (0x0004U) +#define TMR4_OCER_CLBUFEN_1 (0x0008U) +#define TMR4_OCER_MHBUFEN_POS (4U) +#define TMR4_OCER_MHBUFEN (0x0030U) +#define TMR4_OCER_MHBUFEN_0 (0x0010U) +#define TMR4_OCER_MHBUFEN_1 (0x0020U) +#define TMR4_OCER_MLBUFEN_POS (6U) +#define TMR4_OCER_MLBUFEN (0x00C0U) +#define TMR4_OCER_MLBUFEN_0 (0x0040U) +#define TMR4_OCER_MLBUFEN_1 (0x0080U) +#define TMR4_OCER_LMCH_POS (8U) +#define TMR4_OCER_LMCH (0x0100U) +#define TMR4_OCER_LMCL_POS (9U) +#define TMR4_OCER_LMCL (0x0200U) +#define TMR4_OCER_LMMH_POS (10U) +#define TMR4_OCER_LMMH (0x0400U) +#define TMR4_OCER_LMML_POS (11U) +#define TMR4_OCER_LMML (0x0800U) +#define TMR4_OCER_MCECH_POS (12U) +#define TMR4_OCER_MCECH (0x1000U) +#define TMR4_OCER_MCECL_POS (13U) +#define TMR4_OCER_MCECL (0x2000U) + +/* Bit definition for TMR4_OCMRH register */ +#define TMR4_OCMRH_OCFDCH_POS (0U) +#define TMR4_OCMRH_OCFDCH (0x0001U) +#define TMR4_OCMRH_OCFPKH_POS (1U) +#define TMR4_OCMRH_OCFPKH (0x0002U) +#define TMR4_OCMRH_OCFUCH_POS (2U) +#define TMR4_OCMRH_OCFUCH (0x0004U) +#define TMR4_OCMRH_OCFZRH_POS (3U) +#define TMR4_OCMRH_OCFZRH (0x0008U) +#define TMR4_OCMRH_OPDCH_POS (4U) +#define TMR4_OCMRH_OPDCH (0x0030U) +#define TMR4_OCMRH_OPDCH_0 (0x0010U) +#define TMR4_OCMRH_OPDCH_1 (0x0020U) +#define TMR4_OCMRH_OPPKH_POS (6U) +#define TMR4_OCMRH_OPPKH (0x00C0U) +#define TMR4_OCMRH_OPPKH_0 (0x0040U) +#define TMR4_OCMRH_OPPKH_1 (0x0080U) +#define TMR4_OCMRH_OPUCH_POS (8U) +#define TMR4_OCMRH_OPUCH (0x0300U) +#define TMR4_OCMRH_OPUCH_0 (0x0100U) +#define TMR4_OCMRH_OPUCH_1 (0x0200U) +#define TMR4_OCMRH_OPZRH_POS (10U) +#define TMR4_OCMRH_OPZRH (0x0C00U) +#define TMR4_OCMRH_OPZRH_0 (0x0400U) +#define TMR4_OCMRH_OPZRH_1 (0x0800U) +#define TMR4_OCMRH_OPNPKH_POS (12U) +#define TMR4_OCMRH_OPNPKH (0x3000U) +#define TMR4_OCMRH_OPNPKH_0 (0x1000U) +#define TMR4_OCMRH_OPNPKH_1 (0x2000U) +#define TMR4_OCMRH_OPNZRH_POS (14U) +#define TMR4_OCMRH_OPNZRH (0xC000U) +#define TMR4_OCMRH_OPNZRH_0 (0x4000U) +#define TMR4_OCMRH_OPNZRH_1 (0x8000U) + +/* Bit definition for TMR4_OCMRL register */ +#define TMR4_OCMRL_OCFDCL_POS (0U) +#define TMR4_OCMRL_OCFDCL (0x00000001UL) +#define TMR4_OCMRL_OCFPKL_POS (1U) +#define TMR4_OCMRL_OCFPKL (0x00000002UL) +#define TMR4_OCMRL_OCFUCL_POS (2U) +#define TMR4_OCMRL_OCFUCL (0x00000004UL) +#define TMR4_OCMRL_OCFZRL_POS (3U) +#define TMR4_OCMRL_OCFZRL (0x00000008UL) +#define TMR4_OCMRL_OPDCL_POS (4U) +#define TMR4_OCMRL_OPDCL (0x00000030UL) +#define TMR4_OCMRL_OPDCL_0 (0x00000010UL) +#define TMR4_OCMRL_OPDCL_1 (0x00000020UL) +#define TMR4_OCMRL_OPPKL_POS (6U) +#define TMR4_OCMRL_OPPKL (0x000000C0UL) +#define TMR4_OCMRL_OPPKL_0 (0x00000040UL) +#define TMR4_OCMRL_OPPKL_1 (0x00000080UL) +#define TMR4_OCMRL_OPUCL_POS (8U) +#define TMR4_OCMRL_OPUCL (0x00000300UL) +#define TMR4_OCMRL_OPUCL_0 (0x00000100UL) +#define TMR4_OCMRL_OPUCL_1 (0x00000200UL) +#define TMR4_OCMRL_OPZRL_POS (10U) +#define TMR4_OCMRL_OPZRL (0x00000C00UL) +#define TMR4_OCMRL_OPZRL_0 (0x00000400UL) +#define TMR4_OCMRL_OPZRL_1 (0x00000800UL) +#define TMR4_OCMRL_OPNPKL_POS (12U) +#define TMR4_OCMRL_OPNPKL (0x00003000UL) +#define TMR4_OCMRL_OPNPKL_0 (0x00001000UL) +#define TMR4_OCMRL_OPNPKL_1 (0x00002000UL) +#define TMR4_OCMRL_OPNZRL_POS (14U) +#define TMR4_OCMRL_OPNZRL (0x0000C000UL) +#define TMR4_OCMRL_OPNZRL_0 (0x00004000UL) +#define TMR4_OCMRL_OPNZRL_1 (0x00008000UL) +#define TMR4_OCMRL_EOPNDCL_POS (16U) +#define TMR4_OCMRL_EOPNDCL (0x00030000UL) +#define TMR4_OCMRL_EOPNDCL_0 (0x00010000UL) +#define TMR4_OCMRL_EOPNDCL_1 (0x00020000UL) +#define TMR4_OCMRL_EOPNUCL_POS (18U) +#define TMR4_OCMRL_EOPNUCL (0x000C0000UL) +#define TMR4_OCMRL_EOPNUCL_0 (0x00040000UL) +#define TMR4_OCMRL_EOPNUCL_1 (0x00080000UL) +#define TMR4_OCMRL_EOPDCL_POS (20U) +#define TMR4_OCMRL_EOPDCL (0x00300000UL) +#define TMR4_OCMRL_EOPDCL_0 (0x00100000UL) +#define TMR4_OCMRL_EOPDCL_1 (0x00200000UL) +#define TMR4_OCMRL_EOPPKL_POS (22U) +#define TMR4_OCMRL_EOPPKL (0x00C00000UL) +#define TMR4_OCMRL_EOPPKL_0 (0x00400000UL) +#define TMR4_OCMRL_EOPPKL_1 (0x00800000UL) +#define TMR4_OCMRL_EOPUCL_POS (24U) +#define TMR4_OCMRL_EOPUCL (0x03000000UL) +#define TMR4_OCMRL_EOPUCL_0 (0x01000000UL) +#define TMR4_OCMRL_EOPUCL_1 (0x02000000UL) +#define TMR4_OCMRL_EOPZRL_POS (26U) +#define TMR4_OCMRL_EOPZRL (0x0C000000UL) +#define TMR4_OCMRL_EOPZRL_0 (0x04000000UL) +#define TMR4_OCMRL_EOPZRL_1 (0x08000000UL) +#define TMR4_OCMRL_EOPNPKL_POS (28U) +#define TMR4_OCMRL_EOPNPKL (0x30000000UL) +#define TMR4_OCMRL_EOPNPKL_0 (0x10000000UL) +#define TMR4_OCMRL_EOPNPKL_1 (0x20000000UL) +#define TMR4_OCMRL_EOPNZRL_POS (30U) +#define TMR4_OCMRL_EOPNZRL (0xC0000000UL) +#define TMR4_OCMRL_EOPNZRL_0 (0x40000000UL) +#define TMR4_OCMRL_EOPNZRL_1 (0x80000000UL) + +/* Bit definition for TMR4_CPSR register */ +#define TMR4_CPSR (0xFFFFU) + +/* Bit definition for TMR4_CNTR register */ +#define TMR4_CNTR (0xFFFFU) + +/* Bit definition for TMR4_CCSR register */ +#define TMR4_CCSR_CKDIV_POS (0U) +#define TMR4_CCSR_CKDIV (0x000FU) +#define TMR4_CCSR_CLEAR_POS (4U) +#define TMR4_CCSR_CLEAR (0x0010U) +#define TMR4_CCSR_MODE_POS (5U) +#define TMR4_CCSR_MODE (0x0020U) +#define TMR4_CCSR_STOP_POS (6U) +#define TMR4_CCSR_STOP (0x0040U) +#define TMR4_CCSR_BUFEN_POS (7U) +#define TMR4_CCSR_BUFEN (0x0080U) +#define TMR4_CCSR_IRQPEN_POS (8U) +#define TMR4_CCSR_IRQPEN (0x0100U) +#define TMR4_CCSR_IRQPF_POS (9U) +#define TMR4_CCSR_IRQPF (0x0200U) +#define TMR4_CCSR_IRQZEN_POS (10U) +#define TMR4_CCSR_IRQZEN (0x0400U) +#define TMR4_CCSR_IRQZF_POS (11U) +#define TMR4_CCSR_IRQZF (0x0800U) +#define TMR4_CCSR_SYNST_POS (12U) +#define TMR4_CCSR_SYNST (0x1000U) +#define TMR4_CCSR_HST_POS (13U) +#define TMR4_CCSR_HST (0x2000U) +#define TMR4_CCSR_ECKEN_POS (15U) +#define TMR4_CCSR_ECKEN (0x8000U) + +/* Bit definition for TMR4_CVPR register */ +#define TMR4_CVPR_ZIM_POS (0U) +#define TMR4_CVPR_ZIM (0x000FU) +#define TMR4_CVPR_PIM_POS (4U) +#define TMR4_CVPR_PIM (0x00F0U) +#define TMR4_CVPR_ZIC_POS (8U) +#define TMR4_CVPR_ZIC (0x0F00U) +#define TMR4_CVPR_PIC_POS (12U) +#define TMR4_CVPR_PIC (0xF000U) + +/* Bit definition for TMR4_PSCR register */ +#define TMR4_PSCR_OEUH_POS (0U) +#define TMR4_PSCR_OEUH (0x00000001UL) +#define TMR4_PSCR_OEUL_POS (1U) +#define TMR4_PSCR_OEUL (0x00000002UL) +#define TMR4_PSCR_OEVH_POS (2U) +#define TMR4_PSCR_OEVH (0x00000004UL) +#define TMR4_PSCR_OEVL_POS (3U) +#define TMR4_PSCR_OEVL (0x00000008UL) +#define TMR4_PSCR_OEWH_POS (4U) +#define TMR4_PSCR_OEWH (0x00000010UL) +#define TMR4_PSCR_OEWL_POS (5U) +#define TMR4_PSCR_OEWL (0x00000020UL) +#define TMR4_PSCR_OEXH_POS (6U) +#define TMR4_PSCR_OEXH (0x00000040UL) +#define TMR4_PSCR_OEXL_POS (7U) +#define TMR4_PSCR_OEXL (0x00000080UL) +#define TMR4_PSCR_MOE_POS (8U) +#define TMR4_PSCR_MOE (0x00000100UL) +#define TMR4_PSCR_AOE_POS (9U) +#define TMR4_PSCR_AOE (0x00000200UL) +#define TMR4_PSCR_ODT_POS (10U) +#define TMR4_PSCR_ODT (0x00000C00UL) +#define TMR4_PSCR_ODT_0 (0x00000400UL) +#define TMR4_PSCR_ODT_1 (0x00000800UL) +#define TMR4_PSCR_OSUH_POS (16U) +#define TMR4_PSCR_OSUH (0x00030000UL) +#define TMR4_PSCR_OSUH_0 (0x00010000UL) +#define TMR4_PSCR_OSUH_1 (0x00020000UL) +#define TMR4_PSCR_OSUL_POS (18U) +#define TMR4_PSCR_OSUL (0x000C0000UL) +#define TMR4_PSCR_OSUL_0 (0x00040000UL) +#define TMR4_PSCR_OSUL_1 (0x00080000UL) +#define TMR4_PSCR_OSVH_POS (20U) +#define TMR4_PSCR_OSVH (0x00300000UL) +#define TMR4_PSCR_OSVH_0 (0x00100000UL) +#define TMR4_PSCR_OSVH_1 (0x00200000UL) +#define TMR4_PSCR_OSVL_POS (22U) +#define TMR4_PSCR_OSVL (0x00C00000UL) +#define TMR4_PSCR_OSVL_0 (0x00400000UL) +#define TMR4_PSCR_OSVL_1 (0x00800000UL) +#define TMR4_PSCR_OSWH_POS (24U) +#define TMR4_PSCR_OSWH (0x03000000UL) +#define TMR4_PSCR_OSWH_0 (0x01000000UL) +#define TMR4_PSCR_OSWH_1 (0x02000000UL) +#define TMR4_PSCR_OSWL_POS (26U) +#define TMR4_PSCR_OSWL (0x0C000000UL) +#define TMR4_PSCR_OSWL_0 (0x04000000UL) +#define TMR4_PSCR_OSWL_1 (0x08000000UL) +#define TMR4_PSCR_OSXH_POS (28U) +#define TMR4_PSCR_OSXH (0x30000000UL) +#define TMR4_PSCR_OSXH_0 (0x10000000UL) +#define TMR4_PSCR_OSXH_1 (0x20000000UL) +#define TMR4_PSCR_OSXL_POS (30U) +#define TMR4_PSCR_OSXL (0xC0000000UL) +#define TMR4_PSCR_OSXL_0 (0x40000000UL) +#define TMR4_PSCR_OSXL_1 (0x80000000UL) + +/* Bit definition for TMR4_PFSRU register */ +#define TMR4_PFSRU (0xFFFFU) + +/* Bit definition for TMR4_PDARU register */ +#define TMR4_PDARU (0xFFFFU) + +/* Bit definition for TMR4_PDBRU register */ +#define TMR4_PDBRU (0xFFFFU) + +/* Bit definition for TMR4_PFSRV register */ +#define TMR4_PFSRV (0xFFFFU) + +/* Bit definition for TMR4_PDARV register */ +#define TMR4_PDARV (0xFFFFU) + +/* Bit definition for TMR4_PDBRV register */ +#define TMR4_PDBRV (0xFFFFU) + +/* Bit definition for TMR4_PFSRW register */ +#define TMR4_PFSRW (0xFFFFU) + +/* Bit definition for TMR4_PDARW register */ +#define TMR4_PDARW (0xFFFFU) + +/* Bit definition for TMR4_PDBRW register */ +#define TMR4_PDBRW (0xFFFFU) + +/* Bit definition for TMR4_PFSRX register */ +#define TMR4_PFSRX (0xFFFFU) + +/* Bit definition for TMR4_PDARX register */ +#define TMR4_PDARX (0xFFFFU) + +/* Bit definition for TMR4_PDBRX register */ +#define TMR4_PDBRX (0xFFFFU) + +/* Bit definition for TMR4_POCR register */ +#define TMR4_POCR_DIVCK_POS (0U) +#define TMR4_POCR_DIVCK (0x0007U) +#define TMR4_POCR_PWMMD_POS (4U) +#define TMR4_POCR_PWMMD (0x0030U) +#define TMR4_POCR_PWMMD_0 (0x0010U) +#define TMR4_POCR_PWMMD_1 (0x0020U) +#define TMR4_POCR_LVLS_POS (6U) +#define TMR4_POCR_LVLS (0x00C0U) +#define TMR4_POCR_LVLS_0 (0x0040U) +#define TMR4_POCR_LVLS_1 (0x0080U) + +/* Bit definition for TMR4_SCCRUH register */ +#define TMR4_SCCRUH (0xFFFFU) + +/* Bit definition for TMR4_SCCRUL register */ +#define TMR4_SCCRUL (0xFFFFU) + +/* Bit definition for TMR4_SCCRVH register */ +#define TMR4_SCCRVH (0xFFFFU) + +/* Bit definition for TMR4_SCCRVL register */ +#define TMR4_SCCRVL (0xFFFFU) + +/* Bit definition for TMR4_SCCRWH register */ +#define TMR4_SCCRWH (0xFFFFU) + +/* Bit definition for TMR4_SCCRWL register */ +#define TMR4_SCCRWL (0xFFFFU) + +/* Bit definition for TMR4_SCCRXH register */ +#define TMR4_SCCRXH (0xFFFFU) + +/* Bit definition for TMR4_SCCRXL register */ +#define TMR4_SCCRXL (0xFFFFU) + +/* Bit definition for TMR4_SCSR register */ +#define TMR4_SCSR_BUFEN_POS (0U) +#define TMR4_SCSR_BUFEN (0x0003U) +#define TMR4_SCSR_BUFEN_0 (0x0001U) +#define TMR4_SCSR_BUFEN_1 (0x0002U) +#define TMR4_SCSR_EVTOS_POS (2U) +#define TMR4_SCSR_EVTOS (0x001CU) +#define TMR4_SCSR_LMC_POS (5U) +#define TMR4_SCSR_LMC (0x0020U) +#define TMR4_SCSR_EVTMS_POS (8U) +#define TMR4_SCSR_EVTMS (0x0100U) +#define TMR4_SCSR_EVTDS_POS (9U) +#define TMR4_SCSR_EVTDS (0x0200U) +#define TMR4_SCSR_DEN_POS (12U) +#define TMR4_SCSR_DEN (0x1000U) +#define TMR4_SCSR_PEN_POS (13U) +#define TMR4_SCSR_PEN (0x2000U) +#define TMR4_SCSR_UEN_POS (14U) +#define TMR4_SCSR_UEN (0x4000U) +#define TMR4_SCSR_ZEN_POS (15U) +#define TMR4_SCSR_ZEN (0x8000U) + +/* Bit definition for TMR4_SCMR register */ +#define TMR4_SCMR_AMC_POS (0U) +#define TMR4_SCMR_AMC (0x000FU) +#define TMR4_SCMR_MZCE_POS (6U) +#define TMR4_SCMR_MZCE (0x0040U) +#define TMR4_SCMR_MPCE_POS (7U) +#define TMR4_SCMR_MPCE (0x0080U) + +/* Bit definition for TMR4_SCER register */ +#define TMR4_SCER_EVTRS_POS (0U) +#define TMR4_SCER_EVTRS (0x000FU) +#define TMR4_SCER_PCTS_POS (8U) +#define TMR4_SCER_PCTS (0x0100U) + +/* Bit definition for TMR4_RCSR register */ +#define TMR4_RCSR_RTIDU_POS (0U) +#define TMR4_RCSR_RTIDU (0x00000001UL) +#define TMR4_RCSR_RTIDV_POS (1U) +#define TMR4_RCSR_RTIDV (0x00000002UL) +#define TMR4_RCSR_RTIDW_POS (2U) +#define TMR4_RCSR_RTIDW (0x00000004UL) +#define TMR4_RCSR_RTIDX_POS (3U) +#define TMR4_RCSR_RTIDX (0x00000008UL) +#define TMR4_RCSR_RTIFU_POS (4U) +#define TMR4_RCSR_RTIFU (0x00000010UL) +#define TMR4_RCSR_RTICU_POS (5U) +#define TMR4_RCSR_RTICU (0x00000020UL) +#define TMR4_RCSR_RTEU_POS (6U) +#define TMR4_RCSR_RTEU (0x00000040UL) +#define TMR4_RCSR_RTSU_POS (7U) +#define TMR4_RCSR_RTSU (0x00000080UL) +#define TMR4_RCSR_RTIFV_POS (8U) +#define TMR4_RCSR_RTIFV (0x00000100UL) +#define TMR4_RCSR_RTICV_POS (9U) +#define TMR4_RCSR_RTICV (0x00000200UL) +#define TMR4_RCSR_RTEV_POS (10U) +#define TMR4_RCSR_RTEV (0x00000400UL) +#define TMR4_RCSR_RTSV_POS (11U) +#define TMR4_RCSR_RTSV (0x00000800UL) +#define TMR4_RCSR_RTIFW_POS (12U) +#define TMR4_RCSR_RTIFW (0x00001000UL) +#define TMR4_RCSR_RTICW_POS (13U) +#define TMR4_RCSR_RTICW (0x00002000UL) +#define TMR4_RCSR_RTEW_POS (14U) +#define TMR4_RCSR_RTEW (0x00004000UL) +#define TMR4_RCSR_RTSW_POS (15U) +#define TMR4_RCSR_RTSW (0x00008000UL) +#define TMR4_RCSR_RTIFX_POS (16U) +#define TMR4_RCSR_RTIFX (0x00010000UL) +#define TMR4_RCSR_RTICX_POS (17U) +#define TMR4_RCSR_RTICX (0x00020000UL) +#define TMR4_RCSR_RTEX_POS (18U) +#define TMR4_RCSR_RTEX (0x00040000UL) +#define TMR4_RCSR_RTSX_POS (19U) +#define TMR4_RCSR_RTSX (0x00080000UL) + +/* Bit definition for TMR4_SCIR register */ +#define TMR4_SCIR_ITEN0_POS (0U) +#define TMR4_SCIR_ITEN0 (0x0001U) +#define TMR4_SCIR_ITEN1_POS (1U) +#define TMR4_SCIR_ITEN1 (0x0002U) +#define TMR4_SCIR_ITEN2_POS (2U) +#define TMR4_SCIR_ITEN2 (0x0004U) +#define TMR4_SCIR_ITEN3_POS (3U) +#define TMR4_SCIR_ITEN3 (0x0008U) +#define TMR4_SCIR_ITEN4_POS (4U) +#define TMR4_SCIR_ITEN4 (0x0010U) +#define TMR4_SCIR_ITEN5_POS (5U) +#define TMR4_SCIR_ITEN5 (0x0020U) +#define TMR4_SCIR_ITEN6_POS (6U) +#define TMR4_SCIR_ITEN6 (0x0040U) +#define TMR4_SCIR_ITEN7_POS (7U) +#define TMR4_SCIR_ITEN7 (0x0080U) + +/* Bit definition for TMR4_SCFR register */ +#define TMR4_SCFR_SF0_POS (0U) +#define TMR4_SCFR_SF0 (0x0001U) +#define TMR4_SCFR_SF1_POS (1U) +#define TMR4_SCFR_SF1 (0x0002U) +#define TMR4_SCFR_SF2_POS (2U) +#define TMR4_SCFR_SF2 (0x0004U) +#define TMR4_SCFR_SF3_POS (3U) +#define TMR4_SCFR_SF3 (0x0008U) +#define TMR4_SCFR_SF4_POS (4U) +#define TMR4_SCFR_SF4 (0x0010U) +#define TMR4_SCFR_SF5_POS (5U) +#define TMR4_SCFR_SF5 (0x0020U) +#define TMR4_SCFR_SF6_POS (6U) +#define TMR4_SCFR_SF6 (0x0040U) +#define TMR4_SCFR_SF7_POS (7U) +#define TMR4_SCFR_SF7 (0x0080U) + +/******************************************************************************* + Bit definition for Peripheral TMR6 +*******************************************************************************/ +/* Bit definition for TMR6_CNTER register */ +#define TMR6_CNTER_CNT (0x0000FFFFUL) + +/* Bit definition for TMR6_UPDAR register */ +#define TMR6_UPDAR_UPDA (0x0000FFFFUL) + +/* Bit definition for TMR6_PERAR register */ +#define TMR6_PERAR_PERA (0x0000FFFFUL) + +/* Bit definition for TMR6_PERBR register */ +#define TMR6_PERBR_PERB (0x0000FFFFUL) + +/* Bit definition for TMR6_PERCR register */ +#define TMR6_PERCR_PERC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMAR register */ +#define TMR6_GCMAR_GCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMBR register */ +#define TMR6_GCMBR_GCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMCR register */ +#define TMR6_GCMCR_GCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMDR register */ +#define TMR6_GCMDR_GCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMER register */ +#define TMR6_GCMER_GCME (0x0000FFFFUL) + +/* Bit definition for TMR6_GCMFR register */ +#define TMR6_GCMFR_GCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMAR register */ +#define TMR6_SCMAR_SCMA (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMBR register */ +#define TMR6_SCMBR_SCMB (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMCR register */ +#define TMR6_SCMCR_SCMC (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMDR register */ +#define TMR6_SCMDR_SCMD (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMER register */ +#define TMR6_SCMER_SCME (0x0000FFFFUL) + +/* Bit definition for TMR6_SCMFR register */ +#define TMR6_SCMFR_SCMF (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUAR register */ +#define TMR6_DTUAR_DTUA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDAR register */ +#define TMR6_DTDAR_DTDA (0x0000FFFFUL) + +/* Bit definition for TMR6_DTUBR register */ +#define TMR6_DTUBR_DTUB (0x0000FFFFUL) + +/* Bit definition for TMR6_DTDBR register */ +#define TMR6_DTDBR_DTDB (0x0000FFFFUL) + +/* Bit definition for TMR6_GCONR register */ +#define TMR6_GCONR_START_POS (0U) +#define TMR6_GCONR_START (0x00000001UL) +#define TMR6_GCONR_DIR_POS (1U) +#define TMR6_GCONR_DIR (0x00000002UL) +#define TMR6_GCONR_MODE_POS (2U) +#define TMR6_GCONR_MODE (0x00000004UL) +#define TMR6_GCONR_CKDIV_POS (4U) +#define TMR6_GCONR_CKDIV (0x000000F0UL) +#define TMR6_GCONR_OVSTP_POS (8U) +#define TMR6_GCONR_OVSTP (0x00000100UL) +#define TMR6_GCONR_ZMSKREV_POS (16U) +#define TMR6_GCONR_ZMSKREV (0x00010000UL) +#define TMR6_GCONR_ZMSKPOS_POS (17U) +#define TMR6_GCONR_ZMSKPOS (0x00020000UL) +#define TMR6_GCONR_ZMSKVAL_POS (18U) +#define TMR6_GCONR_ZMSKVAL (0x000C0000UL) +#define TMR6_GCONR_ZMSKVAL_0 (0x00040000UL) +#define TMR6_GCONR_ZMSKVAL_1 (0x00080000UL) + +/* Bit definition for TMR6_ICONR register */ +#define TMR6_ICONR_INTENA_POS (0U) +#define TMR6_ICONR_INTENA (0x00000001UL) +#define TMR6_ICONR_INTENB_POS (1U) +#define TMR6_ICONR_INTENB (0x00000002UL) +#define TMR6_ICONR_INTENC_POS (2U) +#define TMR6_ICONR_INTENC (0x00000004UL) +#define TMR6_ICONR_INTEND_POS (3U) +#define TMR6_ICONR_INTEND (0x00000008UL) +#define TMR6_ICONR_INTENE_POS (4U) +#define TMR6_ICONR_INTENE (0x00000010UL) +#define TMR6_ICONR_INTENF_POS (5U) +#define TMR6_ICONR_INTENF (0x00000020UL) +#define TMR6_ICONR_INTENOVF_POS (6U) +#define TMR6_ICONR_INTENOVF (0x00000040UL) +#define TMR6_ICONR_INTENUDF_POS (7U) +#define TMR6_ICONR_INTENUDF (0x00000080UL) +#define TMR6_ICONR_INTENDTE_POS (8U) +#define TMR6_ICONR_INTENDTE (0x00000100UL) +#define TMR6_ICONR_INTENSAU_POS (16U) +#define TMR6_ICONR_INTENSAU (0x00010000UL) +#define TMR6_ICONR_INTENSAD_POS (17U) +#define TMR6_ICONR_INTENSAD (0x00020000UL) +#define TMR6_ICONR_INTENSBU_POS (18U) +#define TMR6_ICONR_INTENSBU (0x00040000UL) +#define TMR6_ICONR_INTENSBD_POS (19U) +#define TMR6_ICONR_INTENSBD (0x00080000UL) + +/* Bit definition for TMR6_BCONR register */ +#define TMR6_BCONR_BENA_POS (0U) +#define TMR6_BCONR_BENA (0x00000001UL) +#define TMR6_BCONR_BSEA_POS (1U) +#define TMR6_BCONR_BSEA (0x00000002UL) +#define TMR6_BCONR_BTRUA_POS (2U) +#define TMR6_BCONR_BTRUA (0x00000004UL) +#define TMR6_BCONR_BTRDA_POS (3U) +#define TMR6_BCONR_BTRDA (0x00000008UL) +#define TMR6_BCONR_BENB_POS (4U) +#define TMR6_BCONR_BENB (0x00000010UL) +#define TMR6_BCONR_BSEB_POS (5U) +#define TMR6_BCONR_BSEB (0x00000020UL) +#define TMR6_BCONR_BTRUB_POS (6U) +#define TMR6_BCONR_BTRUB (0x00000040UL) +#define TMR6_BCONR_BTRDB_POS (7U) +#define TMR6_BCONR_BTRDB (0x00000080UL) +#define TMR6_BCONR_BENP_POS (8U) +#define TMR6_BCONR_BENP (0x00000100UL) +#define TMR6_BCONR_BSEP_POS (9U) +#define TMR6_BCONR_BSEP (0x00000200UL) +#define TMR6_BCONR_BTRUP_POS (10U) +#define TMR6_BCONR_BTRUP (0x00000400UL) +#define TMR6_BCONR_BTRDP_POS (11U) +#define TMR6_BCONR_BTRDP (0x00000800UL) +#define TMR6_BCONR_BENSPA_POS (16U) +#define TMR6_BCONR_BENSPA (0x00010000UL) +#define TMR6_BCONR_BSESPA_POS (17U) +#define TMR6_BCONR_BSESPA (0x00020000UL) +#define TMR6_BCONR_BTRUSPA_POS (18U) +#define TMR6_BCONR_BTRUSPA (0x00040000UL) +#define TMR6_BCONR_BTRDSPA_POS (19U) +#define TMR6_BCONR_BTRDSPA (0x00080000UL) +#define TMR6_BCONR_BENSPB_POS (20U) +#define TMR6_BCONR_BENSPB (0x00100000UL) +#define TMR6_BCONR_BSESPB_POS (21U) +#define TMR6_BCONR_BSESPB (0x00200000UL) +#define TMR6_BCONR_BTRUSPB_POS (22U) +#define TMR6_BCONR_BTRUSPB (0x00400000UL) +#define TMR6_BCONR_BTRDSPB_POS (23U) +#define TMR6_BCONR_BTRDSPB (0x00800000UL) + +/* Bit definition for TMR6_DCONR register */ +#define TMR6_DCONR_DTCEN_POS (0U) +#define TMR6_DCONR_DTCEN (0x00000001UL) +#define TMR6_DCONR_SEPA_POS (1U) +#define TMR6_DCONR_SEPA (0x00000002UL) +#define TMR6_DCONR_DTBENU_POS (4U) +#define TMR6_DCONR_DTBENU (0x00000010UL) +#define TMR6_DCONR_DTBEND_POS (5U) +#define TMR6_DCONR_DTBEND (0x00000020UL) +#define TMR6_DCONR_DTBTRU_POS (6U) +#define TMR6_DCONR_DTBTRU (0x00000040UL) +#define TMR6_DCONR_DTBTRD_POS (7U) +#define TMR6_DCONR_DTBTRD (0x00000080UL) + +/* Bit definition for TMR6_PCNAR register */ +#define TMR6_PCNAR_STACA_POS (0U) +#define TMR6_PCNAR_STACA (0x00000003UL) +#define TMR6_PCNAR_STACA_0 (0x00000001UL) +#define TMR6_PCNAR_STACA_1 (0x00000002UL) +#define TMR6_PCNAR_STPCA_POS (2U) +#define TMR6_PCNAR_STPCA (0x0000000CUL) +#define TMR6_PCNAR_STPCA_0 (0x00000004UL) +#define TMR6_PCNAR_STPCA_1 (0x00000008UL) +#define TMR6_PCNAR_OVFCA_POS (4U) +#define TMR6_PCNAR_OVFCA (0x00000030UL) +#define TMR6_PCNAR_OVFCA_0 (0x00000010UL) +#define TMR6_PCNAR_OVFCA_1 (0x00000020UL) +#define TMR6_PCNAR_UDFCA_POS (6U) +#define TMR6_PCNAR_UDFCA (0x000000C0UL) +#define TMR6_PCNAR_UDFCA_0 (0x00000040UL) +#define TMR6_PCNAR_UDFCA_1 (0x00000080UL) +#define TMR6_PCNAR_CMAUCA_POS (8U) +#define TMR6_PCNAR_CMAUCA (0x00000300UL) +#define TMR6_PCNAR_CMAUCA_0 (0x00000100UL) +#define TMR6_PCNAR_CMAUCA_1 (0x00000200UL) +#define TMR6_PCNAR_CMADCA_POS (10U) +#define TMR6_PCNAR_CMADCA (0x00000C00UL) +#define TMR6_PCNAR_CMADCA_0 (0x00000400UL) +#define TMR6_PCNAR_CMADCA_1 (0x00000800UL) +#define TMR6_PCNAR_CMBUCA_POS (12U) +#define TMR6_PCNAR_CMBUCA (0x00003000UL) +#define TMR6_PCNAR_CMBUCA_0 (0x00001000UL) +#define TMR6_PCNAR_CMBUCA_1 (0x00002000UL) +#define TMR6_PCNAR_CMBDCA_POS (14U) +#define TMR6_PCNAR_CMBDCA (0x0000C000UL) +#define TMR6_PCNAR_CMBDCA_0 (0x00004000UL) +#define TMR6_PCNAR_CMBDCA_1 (0x00008000UL) +#define TMR6_PCNAR_FORCA_POS (16U) +#define TMR6_PCNAR_FORCA (0x00030000UL) +#define TMR6_PCNAR_FORCA_0 (0x00010000UL) +#define TMR6_PCNAR_FORCA_1 (0x00020000UL) +#define TMR6_PCNAR_EMBCA_POS (20U) +#define TMR6_PCNAR_EMBCA (0x00300000UL) +#define TMR6_PCNAR_EMBCA_0 (0x00100000UL) +#define TMR6_PCNAR_EMBCA_1 (0x00200000UL) +#define TMR6_PCNAR_EMBRA_POS (22U) +#define TMR6_PCNAR_EMBRA (0x00C00000UL) +#define TMR6_PCNAR_EMBRA_0 (0x00400000UL) +#define TMR6_PCNAR_EMBRA_1 (0x00800000UL) +#define TMR6_PCNAR_EMBSA_POS (24U) +#define TMR6_PCNAR_EMBSA (0x03000000UL) +#define TMR6_PCNAR_EMBSA_0 (0x01000000UL) +#define TMR6_PCNAR_EMBSA_1 (0x02000000UL) +#define TMR6_PCNAR_OUTENA_POS (28U) +#define TMR6_PCNAR_OUTENA (0x10000000UL) +#define TMR6_PCNAR_CAPMDA_POS (31U) +#define TMR6_PCNAR_CAPMDA (0x80000000UL) + +/* Bit definition for TMR6_PCNBR register */ +#define TMR6_PCNBR_STACB_POS (0U) +#define TMR6_PCNBR_STACB (0x00000003UL) +#define TMR6_PCNBR_STACB_0 (0x00000001UL) +#define TMR6_PCNBR_STACB_1 (0x00000002UL) +#define TMR6_PCNBR_STPCB_POS (2U) +#define TMR6_PCNBR_STPCB (0x0000000CUL) +#define TMR6_PCNBR_STPCB_0 (0x00000004UL) +#define TMR6_PCNBR_STPCB_1 (0x00000008UL) +#define TMR6_PCNBR_OVFCB_POS (4U) +#define TMR6_PCNBR_OVFCB (0x00000030UL) +#define TMR6_PCNBR_OVFCB_0 (0x00000010UL) +#define TMR6_PCNBR_OVFCB_1 (0x00000020UL) +#define TMR6_PCNBR_UDFCB_POS (6U) +#define TMR6_PCNBR_UDFCB (0x000000C0UL) +#define TMR6_PCNBR_UDFCB_0 (0x00000040UL) +#define TMR6_PCNBR_UDFCB_1 (0x00000080UL) +#define TMR6_PCNBR_CMAUCB_POS (8U) +#define TMR6_PCNBR_CMAUCB (0x00000300UL) +#define TMR6_PCNBR_CMAUCB_0 (0x00000100UL) +#define TMR6_PCNBR_CMAUCB_1 (0x00000200UL) +#define TMR6_PCNBR_CMADCB_POS (10U) +#define TMR6_PCNBR_CMADCB (0x00000C00UL) +#define TMR6_PCNBR_CMADCB_0 (0x00000400UL) +#define TMR6_PCNBR_CMADCB_1 (0x00000800UL) +#define TMR6_PCNBR_CMBUCB_POS (12U) +#define TMR6_PCNBR_CMBUCB (0x00003000UL) +#define TMR6_PCNBR_CMBUCB_0 (0x00001000UL) +#define TMR6_PCNBR_CMBUCB_1 (0x00002000UL) +#define TMR6_PCNBR_CMBDCB_POS (14U) +#define TMR6_PCNBR_CMBDCB (0x0000C000UL) +#define TMR6_PCNBR_CMBDCB_0 (0x00004000UL) +#define TMR6_PCNBR_CMBDCB_1 (0x00008000UL) +#define TMR6_PCNBR_FORCB_POS (16U) +#define TMR6_PCNBR_FORCB (0x00030000UL) +#define TMR6_PCNBR_FORCB_0 (0x00010000UL) +#define TMR6_PCNBR_FORCB_1 (0x00020000UL) +#define TMR6_PCNBR_EMBCB_POS (20U) +#define TMR6_PCNBR_EMBCB (0x00300000UL) +#define TMR6_PCNBR_EMBCB_0 (0x00100000UL) +#define TMR6_PCNBR_EMBCB_1 (0x00200000UL) +#define TMR6_PCNBR_EMBRB_POS (22U) +#define TMR6_PCNBR_EMBRB (0x00C00000UL) +#define TMR6_PCNBR_EMBRB_0 (0x00400000UL) +#define TMR6_PCNBR_EMBRB_1 (0x00800000UL) +#define TMR6_PCNBR_EMBSB_POS (24U) +#define TMR6_PCNBR_EMBSB (0x03000000UL) +#define TMR6_PCNBR_EMBSB_0 (0x01000000UL) +#define TMR6_PCNBR_EMBSB_1 (0x02000000UL) +#define TMR6_PCNBR_OUTENB_POS (28U) +#define TMR6_PCNBR_OUTENB (0x10000000UL) +#define TMR6_PCNBR_CAPMDB_POS (31U) +#define TMR6_PCNBR_CAPMDB (0x80000000UL) + +/* Bit definition for TMR6_FCNGR register */ +#define TMR6_FCNGR_NOFIENGA_POS (0U) +#define TMR6_FCNGR_NOFIENGA (0x00000001UL) +#define TMR6_FCNGR_NOFICKGA_POS (1U) +#define TMR6_FCNGR_NOFICKGA (0x00000006UL) +#define TMR6_FCNGR_NOFICKGA_0 (0x00000002UL) +#define TMR6_FCNGR_NOFICKGA_1 (0x00000004UL) +#define TMR6_FCNGR_NOFIENGB_POS (4U) +#define TMR6_FCNGR_NOFIENGB (0x00000010UL) +#define TMR6_FCNGR_NOFICKGB_POS (5U) +#define TMR6_FCNGR_NOFICKGB (0x00000060UL) +#define TMR6_FCNGR_NOFICKGB_0 (0x00000020UL) +#define TMR6_FCNGR_NOFICKGB_1 (0x00000040UL) + +/* Bit definition for TMR6_VPERR register */ +#define TMR6_VPERR_SPPERIA_POS (8U) +#define TMR6_VPERR_SPPERIA (0x00000100UL) +#define TMR6_VPERR_SPPERIB_POS (9U) +#define TMR6_VPERR_SPPERIB (0x00000200UL) +#define TMR6_VPERR_PCNTE_POS (16U) +#define TMR6_VPERR_PCNTE (0x00030000UL) +#define TMR6_VPERR_PCNTE_0 (0x00010000UL) +#define TMR6_VPERR_PCNTE_1 (0x00020000UL) +#define TMR6_VPERR_PCNTS_POS (18U) +#define TMR6_VPERR_PCNTS (0x001C0000UL) + +/* Bit definition for TMR6_STFLR register */ +#define TMR6_STFLR_CMAF_POS (0U) +#define TMR6_STFLR_CMAF (0x00000001UL) +#define TMR6_STFLR_CMBF_POS (1U) +#define TMR6_STFLR_CMBF (0x00000002UL) +#define TMR6_STFLR_CMCF_POS (2U) +#define TMR6_STFLR_CMCF (0x00000004UL) +#define TMR6_STFLR_CMDF_POS (3U) +#define TMR6_STFLR_CMDF (0x00000008UL) +#define TMR6_STFLR_CMEF_POS (4U) +#define TMR6_STFLR_CMEF (0x00000010UL) +#define TMR6_STFLR_CMFF_POS (5U) +#define TMR6_STFLR_CMFF (0x00000020UL) +#define TMR6_STFLR_OVFF_POS (6U) +#define TMR6_STFLR_OVFF (0x00000040UL) +#define TMR6_STFLR_UDFF_POS (7U) +#define TMR6_STFLR_UDFF (0x00000080UL) +#define TMR6_STFLR_DTEF_POS (8U) +#define TMR6_STFLR_DTEF (0x00000100UL) +#define TMR6_STFLR_CMSAUF_POS (9U) +#define TMR6_STFLR_CMSAUF (0x00000200UL) +#define TMR6_STFLR_CMSADF_POS (10U) +#define TMR6_STFLR_CMSADF (0x00000400UL) +#define TMR6_STFLR_CMSBUF_POS (11U) +#define TMR6_STFLR_CMSBUF (0x00000800UL) +#define TMR6_STFLR_CMSBDF_POS (12U) +#define TMR6_STFLR_CMSBDF (0x00001000UL) +#define TMR6_STFLR_VPERNUM_POS (21U) +#define TMR6_STFLR_VPERNUM (0x00E00000UL) +#define TMR6_STFLR_CMAF2_POS (26U) +#define TMR6_STFLR_CMAF2 (0x04000000UL) +#define TMR6_STFLR_CMBF2_POS (27U) +#define TMR6_STFLR_CMBF2 (0x08000000UL) +#define TMR6_STFLR_DIRF_POS (31U) +#define TMR6_STFLR_DIRF (0x80000000UL) + +/* Bit definition for TMR6_HSTAR register */ +#define TMR6_HSTAR_HSTA0_POS (0U) +#define TMR6_HSTAR_HSTA0 (0x00000001UL) +#define TMR6_HSTAR_HSTA1_POS (1U) +#define TMR6_HSTAR_HSTA1 (0x00000002UL) +#define TMR6_HSTAR_HSTA2_POS (2U) +#define TMR6_HSTAR_HSTA2 (0x00000004UL) +#define TMR6_HSTAR_HSTA3_POS (3U) +#define TMR6_HSTAR_HSTA3 (0x00000008UL) +#define TMR6_HSTAR_STAS_POS (7U) +#define TMR6_HSTAR_STAS (0x00000080UL) +#define TMR6_HSTAR_HSTA8_POS (8U) +#define TMR6_HSTAR_HSTA8 (0x00000100UL) +#define TMR6_HSTAR_HSTA9_POS (9U) +#define TMR6_HSTAR_HSTA9 (0x00000200UL) +#define TMR6_HSTAR_HSTA16_POS (16U) +#define TMR6_HSTAR_HSTA16 (0x00010000UL) +#define TMR6_HSTAR_HSTA17_POS (17U) +#define TMR6_HSTAR_HSTA17 (0x00020000UL) +#define TMR6_HSTAR_HSTA18_POS (18U) +#define TMR6_HSTAR_HSTA18 (0x00040000UL) +#define TMR6_HSTAR_HSTA19_POS (19U) +#define TMR6_HSTAR_HSTA19 (0x00080000UL) + +/* Bit definition for TMR6_HSTPR register */ +#define TMR6_HSTPR_HSTP0_POS (0U) +#define TMR6_HSTPR_HSTP0 (0x00000001UL) +#define TMR6_HSTPR_HSTP1_POS (1U) +#define TMR6_HSTPR_HSTP1 (0x00000002UL) +#define TMR6_HSTPR_HSTP2_POS (2U) +#define TMR6_HSTPR_HSTP2 (0x00000004UL) +#define TMR6_HSTPR_HSTP3_POS (3U) +#define TMR6_HSTPR_HSTP3 (0x00000008UL) +#define TMR6_HSTPR_STPS_POS (7U) +#define TMR6_HSTPR_STPS (0x00000080UL) +#define TMR6_HSTPR_HSTP8_POS (8U) +#define TMR6_HSTPR_HSTP8 (0x00000100UL) +#define TMR6_HSTPR_HSTP9_POS (9U) +#define TMR6_HSTPR_HSTP9 (0x00000200UL) +#define TMR6_HSTPR_HSTP16_POS (16U) +#define TMR6_HSTPR_HSTP16 (0x00010000UL) +#define TMR6_HSTPR_HSTP17_POS (17U) +#define TMR6_HSTPR_HSTP17 (0x00020000UL) +#define TMR6_HSTPR_HSTP18_POS (18U) +#define TMR6_HSTPR_HSTP18 (0x00040000UL) +#define TMR6_HSTPR_HSTP19_POS (19U) +#define TMR6_HSTPR_HSTP19 (0x00080000UL) + +/* Bit definition for TMR6_HCLRR register */ +#define TMR6_HCLRR_HCLE0_POS (0U) +#define TMR6_HCLRR_HCLE0 (0x00000001UL) +#define TMR6_HCLRR_HCLE1_POS (1U) +#define TMR6_HCLRR_HCLE1 (0x00000002UL) +#define TMR6_HCLRR_HCLE2_POS (2U) +#define TMR6_HCLRR_HCLE2 (0x00000004UL) +#define TMR6_HCLRR_HCLE3_POS (3U) +#define TMR6_HCLRR_HCLE3 (0x00000008UL) +#define TMR6_HCLRR_CLES_POS (7U) +#define TMR6_HCLRR_CLES (0x00000080UL) +#define TMR6_HCLRR_HCLE8_POS (8U) +#define TMR6_HCLRR_HCLE8 (0x00000100UL) +#define TMR6_HCLRR_HCLE9_POS (9U) +#define TMR6_HCLRR_HCLE9 (0x00000200UL) +#define TMR6_HCLRR_HCLE16_POS (16U) +#define TMR6_HCLRR_HCLE16 (0x00010000UL) +#define TMR6_HCLRR_HCLE17_POS (17U) +#define TMR6_HCLRR_HCLE17 (0x00020000UL) +#define TMR6_HCLRR_HCLE18_POS (18U) +#define TMR6_HCLRR_HCLE18 (0x00040000UL) +#define TMR6_HCLRR_HCLE19_POS (19U) +#define TMR6_HCLRR_HCLE19 (0x00080000UL) + +/* Bit definition for TMR6_HUPDR register */ +#define TMR6_HUPDR_HUPD0_POS (0U) +#define TMR6_HUPDR_HUPD0 (0x00000001UL) +#define TMR6_HUPDR_HUPD1_POS (1U) +#define TMR6_HUPDR_HUPD1 (0x00000002UL) +#define TMR6_HUPDR_HUPD2_POS (2U) +#define TMR6_HUPDR_HUPD2 (0x00000004UL) +#define TMR6_HUPDR_HUPD3_POS (3U) +#define TMR6_HUPDR_HUPD3 (0x00000008UL) +#define TMR6_HUPDR_UPDS_POS (7U) +#define TMR6_HUPDR_UPDS (0x00000080UL) +#define TMR6_HUPDR_HUPD8_POS (8U) +#define TMR6_HUPDR_HUPD8 (0x00000100UL) +#define TMR6_HUPDR_HUPD9_POS (9U) +#define TMR6_HUPDR_HUPD9 (0x00000200UL) +#define TMR6_HUPDR_HUPD16_POS (16U) +#define TMR6_HUPDR_HUPD16 (0x00010000UL) +#define TMR6_HUPDR_HUPD17_POS (17U) +#define TMR6_HUPDR_HUPD17 (0x00020000UL) +#define TMR6_HUPDR_HUPD18_POS (18U) +#define TMR6_HUPDR_HUPD18 (0x00040000UL) +#define TMR6_HUPDR_HUPD19_POS (19U) +#define TMR6_HUPDR_HUPD19 (0x00080000UL) + +/* Bit definition for TMR6_HCPAR register */ +#define TMR6_HCPAR_HCPA0_POS (0U) +#define TMR6_HCPAR_HCPA0 (0x00000001UL) +#define TMR6_HCPAR_HCPA1_POS (1U) +#define TMR6_HCPAR_HCPA1 (0x00000002UL) +#define TMR6_HCPAR_HCPA2_POS (2U) +#define TMR6_HCPAR_HCPA2 (0x00000004UL) +#define TMR6_HCPAR_HCPA3_POS (3U) +#define TMR6_HCPAR_HCPA3 (0x00000008UL) +#define TMR6_HCPAR_HCPA8_POS (8U) +#define TMR6_HCPAR_HCPA8 (0x00000100UL) +#define TMR6_HCPAR_HCPA9_POS (9U) +#define TMR6_HCPAR_HCPA9 (0x00000200UL) +#define TMR6_HCPAR_HCPA16_POS (16U) +#define TMR6_HCPAR_HCPA16 (0x00010000UL) +#define TMR6_HCPAR_HCPA17_POS (17U) +#define TMR6_HCPAR_HCPA17 (0x00020000UL) +#define TMR6_HCPAR_HCPA18_POS (18U) +#define TMR6_HCPAR_HCPA18 (0x00040000UL) +#define TMR6_HCPAR_HCPA19_POS (19U) +#define TMR6_HCPAR_HCPA19 (0x00080000UL) +#define TMR6_HCPAR_HCPA24_POS (24U) +#define TMR6_HCPAR_HCPA24 (0x01000000UL) +#define TMR6_HCPAR_HCPA25_POS (25U) +#define TMR6_HCPAR_HCPA25 (0x02000000UL) + +/* Bit definition for TMR6_HCPBR register */ +#define TMR6_HCPBR_HCPB0_POS (0U) +#define TMR6_HCPBR_HCPB0 (0x00000001UL) +#define TMR6_HCPBR_HCPB1_POS (1U) +#define TMR6_HCPBR_HCPB1 (0x00000002UL) +#define TMR6_HCPBR_HCPB2_POS (2U) +#define TMR6_HCPBR_HCPB2 (0x00000004UL) +#define TMR6_HCPBR_HCPB3_POS (3U) +#define TMR6_HCPBR_HCPB3 (0x00000008UL) +#define TMR6_HCPBR_HCPB8_POS (8U) +#define TMR6_HCPBR_HCPB8 (0x00000100UL) +#define TMR6_HCPBR_HCPB9_POS (9U) +#define TMR6_HCPBR_HCPB9 (0x00000200UL) +#define TMR6_HCPBR_HCPB16_POS (16U) +#define TMR6_HCPBR_HCPB16 (0x00010000UL) +#define TMR6_HCPBR_HCPB17_POS (17U) +#define TMR6_HCPBR_HCPB17 (0x00020000UL) +#define TMR6_HCPBR_HCPB18_POS (18U) +#define TMR6_HCPBR_HCPB18 (0x00040000UL) +#define TMR6_HCPBR_HCPB19_POS (19U) +#define TMR6_HCPBR_HCPB19 (0x00080000UL) +#define TMR6_HCPBR_HCPB24_POS (24U) +#define TMR6_HCPBR_HCPB24 (0x01000000UL) +#define TMR6_HCPBR_HCPB25_POS (25U) +#define TMR6_HCPBR_HCPB25 (0x02000000UL) + +/* Bit definition for TMR6_HCUPR register */ +#define TMR6_HCUPR_HCUP0_POS (0U) +#define TMR6_HCUPR_HCUP0 (0x00000001UL) +#define TMR6_HCUPR_HCUP1_POS (1U) +#define TMR6_HCUPR_HCUP1 (0x00000002UL) +#define TMR6_HCUPR_HCUP2_POS (2U) +#define TMR6_HCUPR_HCUP2 (0x00000004UL) +#define TMR6_HCUPR_HCUP3_POS (3U) +#define TMR6_HCUPR_HCUP3 (0x00000008UL) +#define TMR6_HCUPR_HCUP4_POS (4U) +#define TMR6_HCUPR_HCUP4 (0x00000010UL) +#define TMR6_HCUPR_HCUP5_POS (5U) +#define TMR6_HCUPR_HCUP5 (0x00000020UL) +#define TMR6_HCUPR_HCUP6_POS (6U) +#define TMR6_HCUPR_HCUP6 (0x00000040UL) +#define TMR6_HCUPR_HCUP7_POS (7U) +#define TMR6_HCUPR_HCUP7 (0x00000080UL) +#define TMR6_HCUPR_HCUP8_POS (8U) +#define TMR6_HCUPR_HCUP8 (0x00000100UL) +#define TMR6_HCUPR_HCUP9_POS (9U) +#define TMR6_HCUPR_HCUP9 (0x00000200UL) +#define TMR6_HCUPR_HCUP16_POS (16U) +#define TMR6_HCUPR_HCUP16 (0x00010000UL) +#define TMR6_HCUPR_HCUP17_POS (17U) +#define TMR6_HCUPR_HCUP17 (0x00020000UL) +#define TMR6_HCUPR_HCUP18_POS (18U) +#define TMR6_HCUPR_HCUP18 (0x00040000UL) +#define TMR6_HCUPR_HCUP19_POS (19U) +#define TMR6_HCUPR_HCUP19 (0x00080000UL) + +/* Bit definition for TMR6_HCDOR register */ +#define TMR6_HCDOR_HCDO0_POS (0U) +#define TMR6_HCDOR_HCDO0 (0x00000001UL) +#define TMR6_HCDOR_HCDO1_POS (1U) +#define TMR6_HCDOR_HCDO1 (0x00000002UL) +#define TMR6_HCDOR_HCDO2_POS (2U) +#define TMR6_HCDOR_HCDO2 (0x00000004UL) +#define TMR6_HCDOR_HCDO3_POS (3U) +#define TMR6_HCDOR_HCDO3 (0x00000008UL) +#define TMR6_HCDOR_HCDO4_POS (4U) +#define TMR6_HCDOR_HCDO4 (0x00000010UL) +#define TMR6_HCDOR_HCDO5_POS (5U) +#define TMR6_HCDOR_HCDO5 (0x00000020UL) +#define TMR6_HCDOR_HCDO6_POS (6U) +#define TMR6_HCDOR_HCDO6 (0x00000040UL) +#define TMR6_HCDOR_HCDO7_POS (7U) +#define TMR6_HCDOR_HCDO7 (0x00000080UL) +#define TMR6_HCDOR_HCDO8_POS (8U) +#define TMR6_HCDOR_HCDO8 (0x00000100UL) +#define TMR6_HCDOR_HCDO9_POS (9U) +#define TMR6_HCDOR_HCDO9 (0x00000200UL) +#define TMR6_HCDOR_HCDO16_POS (16U) +#define TMR6_HCDOR_HCDO16 (0x00010000UL) +#define TMR6_HCDOR_HCDO17_POS (17U) +#define TMR6_HCDOR_HCDO17 (0x00020000UL) +#define TMR6_HCDOR_HCDO18_POS (18U) +#define TMR6_HCDOR_HCDO18 (0x00040000UL) +#define TMR6_HCDOR_HCDO19_POS (19U) +#define TMR6_HCDOR_HCDO19 (0x00080000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR6_COMMON +*******************************************************************************/ +/* Bit definition for TMR6_COMMON_FCNTR register */ +#define TMR6_COMMON_FCNTR_NOFIENTA_POS (0U) +#define TMR6_COMMON_FCNTR_NOFIENTA (0x00000001UL) +#define TMR6_COMMON_FCNTR_NOFICKTA_POS (1U) +#define TMR6_COMMON_FCNTR_NOFICKTA (0x00000006UL) +#define TMR6_COMMON_FCNTR_NOFICKTA_0 (0x00000002UL) +#define TMR6_COMMON_FCNTR_NOFICKTA_1 (0x00000004UL) +#define TMR6_COMMON_FCNTR_NOFIENTB_POS (4U) +#define TMR6_COMMON_FCNTR_NOFIENTB (0x00000010UL) +#define TMR6_COMMON_FCNTR_NOFICKTB_POS (5U) +#define TMR6_COMMON_FCNTR_NOFICKTB (0x00000060UL) +#define TMR6_COMMON_FCNTR_NOFICKTB_0 (0x00000020UL) +#define TMR6_COMMON_FCNTR_NOFICKTB_1 (0x00000040UL) + +/* Bit definition for TMR6_COMMON_SSTAR register */ +#define TMR6_COMMON_SSTAR_SSTA1_POS (0U) +#define TMR6_COMMON_SSTAR_SSTA1 (0x00000001UL) +#define TMR6_COMMON_SSTAR_SSTA2_POS (1U) +#define TMR6_COMMON_SSTAR_SSTA2 (0x00000002UL) + +/* Bit definition for TMR6_COMMON_SSTPR register */ +#define TMR6_COMMON_SSTPR_SSTP1_POS (0U) +#define TMR6_COMMON_SSTPR_SSTP1 (0x00000001UL) +#define TMR6_COMMON_SSTPR_SSTP2_POS (1U) +#define TMR6_COMMON_SSTPR_SSTP2 (0x00000002UL) + +/* Bit definition for TMR6_COMMON_SCLRR register */ +#define TMR6_COMMON_SCLRR_SCLE1_POS (0U) +#define TMR6_COMMON_SCLRR_SCLE1 (0x00000001UL) +#define TMR6_COMMON_SCLRR_SCLE2_POS (1U) +#define TMR6_COMMON_SCLRR_SCLE2 (0x00000002UL) + +/* Bit definition for TMR6_COMMON_SUPDR register */ +#define TMR6_COMMON_SUPDR_SUPD1_POS (0U) +#define TMR6_COMMON_SUPDR_SUPD1 (0x00000001UL) +#define TMR6_COMMON_SUPDR_SUPD2_POS (1U) +#define TMR6_COMMON_SUPDR_SUPD2 (0x00000002UL) + +/******************************************************************************* + Bit definition for Peripheral TMRA +*******************************************************************************/ +/* Bit definition for TMRA_CNTER register */ +#define TMRA_CNTER_CNT (0xFFFFFFFFUL) + +/* Bit definition for TMRA_PERAR register */ +#define TMRA_PERAR_PER (0xFFFFFFFFUL) + +/* Bit definition for TMRA_CMPAR register */ +#define TMRA_CMPAR_CMP (0xFFFFFFFFUL) + +/* Bit definition for TMRA_BCSTRL register */ +#define TMRA_BCSTRL_START_POS (0U) +#define TMRA_BCSTRL_START (0x01U) +#define TMRA_BCSTRL_DIR_POS (1U) +#define TMRA_BCSTRL_DIR (0x02U) +#define TMRA_BCSTRL_MODE_POS (2U) +#define TMRA_BCSTRL_MODE (0x04U) +#define TMRA_BCSTRL_SYNST_POS (3U) +#define TMRA_BCSTRL_SYNST (0x08U) +#define TMRA_BCSTRL_CKDIV_POS (4U) +#define TMRA_BCSTRL_CKDIV (0xF0U) + +/* Bit definition for TMRA_BCSTRH register */ +#define TMRA_BCSTRH_OVSTP_POS (0U) +#define TMRA_BCSTRH_OVSTP (0x01U) +#define TMRA_BCSTRH_ITENOVF_POS (4U) +#define TMRA_BCSTRH_ITENOVF (0x10U) +#define TMRA_BCSTRH_ITENUDF_POS (5U) +#define TMRA_BCSTRH_ITENUDF (0x20U) +#define TMRA_BCSTRH_OVFF_POS (6U) +#define TMRA_BCSTRH_OVFF (0x40U) +#define TMRA_BCSTRH_UDFF_POS (7U) +#define TMRA_BCSTRH_UDFF (0x80U) + +/* Bit definition for TMRA_HCONR register */ +#define TMRA_HCONR_HSTA0_POS (0U) +#define TMRA_HCONR_HSTA0 (0x0001U) +#define TMRA_HCONR_HSTA1_POS (1U) +#define TMRA_HCONR_HSTA1 (0x0002U) +#define TMRA_HCONR_HSTA2_POS (2U) +#define TMRA_HCONR_HSTA2 (0x0004U) +#define TMRA_HCONR_HSTP0_POS (4U) +#define TMRA_HCONR_HSTP0 (0x0010U) +#define TMRA_HCONR_HSTP1_POS (5U) +#define TMRA_HCONR_HSTP1 (0x0020U) +#define TMRA_HCONR_HSTP2_POS (6U) +#define TMRA_HCONR_HSTP2 (0x0040U) +#define TMRA_HCONR_HCLE0_POS (8U) +#define TMRA_HCONR_HCLE0 (0x0100U) +#define TMRA_HCONR_HCLE1_POS (9U) +#define TMRA_HCONR_HCLE1 (0x0200U) +#define TMRA_HCONR_HCLE2_POS (10U) +#define TMRA_HCONR_HCLE2 (0x0400U) +#define TMRA_HCONR_HCLE3_POS (12U) +#define TMRA_HCONR_HCLE3 (0x1000U) +#define TMRA_HCONR_HCLE4_POS (13U) +#define TMRA_HCONR_HCLE4 (0x2000U) +#define TMRA_HCONR_HCLE5_POS (14U) +#define TMRA_HCONR_HCLE5 (0x4000U) +#define TMRA_HCONR_HCLE6_POS (15U) +#define TMRA_HCONR_HCLE6 (0x8000U) + +/* Bit definition for TMRA_HCUPR register */ +#define TMRA_HCUPR_HCUP0_POS (0U) +#define TMRA_HCUPR_HCUP0 (0x0001U) +#define TMRA_HCUPR_HCUP1_POS (1U) +#define TMRA_HCUPR_HCUP1 (0x0002U) +#define TMRA_HCUPR_HCUP2_POS (2U) +#define TMRA_HCUPR_HCUP2 (0x0004U) +#define TMRA_HCUPR_HCUP3_POS (3U) +#define TMRA_HCUPR_HCUP3 (0x0008U) +#define TMRA_HCUPR_HCUP4_POS (4U) +#define TMRA_HCUPR_HCUP4 (0x0010U) +#define TMRA_HCUPR_HCUP5_POS (5U) +#define TMRA_HCUPR_HCUP5 (0x0020U) +#define TMRA_HCUPR_HCUP6_POS (6U) +#define TMRA_HCUPR_HCUP6 (0x0040U) +#define TMRA_HCUPR_HCUP7_POS (7U) +#define TMRA_HCUPR_HCUP7 (0x0080U) +#define TMRA_HCUPR_HCUP8_POS (8U) +#define TMRA_HCUPR_HCUP8 (0x0100U) +#define TMRA_HCUPR_HCUP9_POS (9U) +#define TMRA_HCUPR_HCUP9 (0x0200U) +#define TMRA_HCUPR_HCUP10_POS (10U) +#define TMRA_HCUPR_HCUP10 (0x0400U) +#define TMRA_HCUPR_HCUP11_POS (11U) +#define TMRA_HCUPR_HCUP11 (0x0800U) +#define TMRA_HCUPR_HCUP12_POS (12U) +#define TMRA_HCUPR_HCUP12 (0x1000U) + +/* Bit definition for TMRA_HCDOR register */ +#define TMRA_HCDOR_HCDO0_POS (0U) +#define TMRA_HCDOR_HCDO0 (0x0001U) +#define TMRA_HCDOR_HCDO1_POS (1U) +#define TMRA_HCDOR_HCDO1 (0x0002U) +#define TMRA_HCDOR_HCDO2_POS (2U) +#define TMRA_HCDOR_HCDO2 (0x0004U) +#define TMRA_HCDOR_HCDO3_POS (3U) +#define TMRA_HCDOR_HCDO3 (0x0008U) +#define TMRA_HCDOR_HCDO4_POS (4U) +#define TMRA_HCDOR_HCDO4 (0x0010U) +#define TMRA_HCDOR_HCDO5_POS (5U) +#define TMRA_HCDOR_HCDO5 (0x0020U) +#define TMRA_HCDOR_HCDO6_POS (6U) +#define TMRA_HCDOR_HCDO6 (0x0040U) +#define TMRA_HCDOR_HCDO7_POS (7U) +#define TMRA_HCDOR_HCDO7 (0x0080U) +#define TMRA_HCDOR_HCDO8_POS (8U) +#define TMRA_HCDOR_HCDO8 (0x0100U) +#define TMRA_HCDOR_HCDO9_POS (9U) +#define TMRA_HCDOR_HCDO9 (0x0200U) +#define TMRA_HCDOR_HCDO10_POS (10U) +#define TMRA_HCDOR_HCDO10 (0x0400U) +#define TMRA_HCDOR_HCDO11_POS (11U) +#define TMRA_HCDOR_HCDO11 (0x0800U) +#define TMRA_HCDOR_HCDO12_POS (12U) +#define TMRA_HCDOR_HCDO12 (0x1000U) + +/* Bit definition for TMRA_ICONR register */ +#define TMRA_ICONR_ITEN1_POS (0U) +#define TMRA_ICONR_ITEN1 (0x0001U) +#define TMRA_ICONR_ITEN2_POS (1U) +#define TMRA_ICONR_ITEN2 (0x0002U) +#define TMRA_ICONR_ITEN3_POS (2U) +#define TMRA_ICONR_ITEN3 (0x0004U) +#define TMRA_ICONR_ITEN4_POS (3U) +#define TMRA_ICONR_ITEN4 (0x0008U) +#define TMRA_ICONR_ITEN5_POS (4U) +#define TMRA_ICONR_ITEN5 (0x0010U) +#define TMRA_ICONR_ITEN6_POS (5U) +#define TMRA_ICONR_ITEN6 (0x0020U) +#define TMRA_ICONR_ITEN7_POS (6U) +#define TMRA_ICONR_ITEN7 (0x0040U) +#define TMRA_ICONR_ITEN8_POS (7U) +#define TMRA_ICONR_ITEN8 (0x0080U) + +/* Bit definition for TMRA_ECONR register */ +#define TMRA_ECONR_ETEN1_POS (0U) +#define TMRA_ECONR_ETEN1 (0x0001U) +#define TMRA_ECONR_ETEN2_POS (1U) +#define TMRA_ECONR_ETEN2 (0x0002U) +#define TMRA_ECONR_ETEN3_POS (2U) +#define TMRA_ECONR_ETEN3 (0x0004U) +#define TMRA_ECONR_ETEN4_POS (3U) +#define TMRA_ECONR_ETEN4 (0x0008U) +#define TMRA_ECONR_ETEN5_POS (4U) +#define TMRA_ECONR_ETEN5 (0x0010U) +#define TMRA_ECONR_ETEN6_POS (5U) +#define TMRA_ECONR_ETEN6 (0x0020U) +#define TMRA_ECONR_ETEN7_POS (6U) +#define TMRA_ECONR_ETEN7 (0x0040U) +#define TMRA_ECONR_ETEN8_POS (7U) +#define TMRA_ECONR_ETEN8 (0x0080U) + +/* Bit definition for TMRA_FCONR register */ +#define TMRA_FCONR_NOFIENTG_POS (0U) +#define TMRA_FCONR_NOFIENTG (0x0001U) +#define TMRA_FCONR_NOFICKTG_POS (1U) +#define TMRA_FCONR_NOFICKTG (0x0006U) +#define TMRA_FCONR_NOFIENCA_POS (8U) +#define TMRA_FCONR_NOFIENCA (0x0100U) +#define TMRA_FCONR_NOFICKCA_POS (9U) +#define TMRA_FCONR_NOFICKCA (0x0600U) +#define TMRA_FCONR_NOFIENCB_POS (12U) +#define TMRA_FCONR_NOFIENCB (0x1000U) +#define TMRA_FCONR_NOFICKCB_POS (13U) +#define TMRA_FCONR_NOFICKCB (0x6000U) + +/* Bit definition for TMRA_STFLR register */ +#define TMRA_STFLR_CMPF1_POS (0U) +#define TMRA_STFLR_CMPF1 (0x0001U) +#define TMRA_STFLR_CMPF2_POS (1U) +#define TMRA_STFLR_CMPF2 (0x0002U) +#define TMRA_STFLR_CMPF3_POS (2U) +#define TMRA_STFLR_CMPF3 (0x0004U) +#define TMRA_STFLR_CMPF4_POS (3U) +#define TMRA_STFLR_CMPF4 (0x0008U) +#define TMRA_STFLR_CMPF5_POS (4U) +#define TMRA_STFLR_CMPF5 (0x0010U) +#define TMRA_STFLR_CMPF6_POS (5U) +#define TMRA_STFLR_CMPF6 (0x0020U) +#define TMRA_STFLR_CMPF7_POS (6U) +#define TMRA_STFLR_CMPF7 (0x0040U) +#define TMRA_STFLR_CMPF8_POS (7U) +#define TMRA_STFLR_CMPF8 (0x0080U) +#define TMRA_STFLR_ICPF1_POS (8U) +#define TMRA_STFLR_ICPF1 (0x0100U) +#define TMRA_STFLR_ICPF2_POS (9U) +#define TMRA_STFLR_ICPF2 (0x0200U) +#define TMRA_STFLR_ICPF3_POS (10U) +#define TMRA_STFLR_ICPF3 (0x0400U) +#define TMRA_STFLR_ICPF4_POS (11U) +#define TMRA_STFLR_ICPF4 (0x0800U) +#define TMRA_STFLR_ICPF5_POS (12U) +#define TMRA_STFLR_ICPF5 (0x1000U) +#define TMRA_STFLR_ICPF6_POS (13U) +#define TMRA_STFLR_ICPF6 (0x2000U) +#define TMRA_STFLR_ICPF7_POS (14U) +#define TMRA_STFLR_ICPF7 (0x4000U) +#define TMRA_STFLR_ICPF8_POS (15U) +#define TMRA_STFLR_ICPF8 (0x8000U) + +/* Bit definition for TMRA_BCONR register */ +#define TMRA_BCONR_BEN_POS (0U) +#define TMRA_BCONR_BEN (0x0001U) +#define TMRA_BCONR_BSE0_POS (1U) +#define TMRA_BCONR_BSE0 (0x0002U) +#define TMRA_BCONR_BSE1_POS (2U) +#define TMRA_BCONR_BSE1 (0x0004U) +#define TMRA_BCONR_BSEN_POS (3U) +#define TMRA_BCONR_BSEN (0x0008U) + +/* Bit definition for TMRA_CCONR register */ +#define TMRA_CCONR_CAPMD_POS (0U) +#define TMRA_CCONR_CAPMD (0x0001U) +#define TMRA_CCONR_HICP0_POS (4U) +#define TMRA_CCONR_HICP0 (0x0010U) +#define TMRA_CCONR_HICP1_POS (5U) +#define TMRA_CCONR_HICP1 (0x0020U) +#define TMRA_CCONR_HICP2_POS (6U) +#define TMRA_CCONR_HICP2 (0x0040U) +#define TMRA_CCONR_HICP3_POS (8U) +#define TMRA_CCONR_HICP3 (0x0100U) +#define TMRA_CCONR_HICP4_POS (9U) +#define TMRA_CCONR_HICP4 (0x0200U) +#define TMRA_CCONR_HICP5_POS (10U) +#define TMRA_CCONR_HICP5 (0x0400U) +#define TMRA_CCONR_HICP6_POS (11U) +#define TMRA_CCONR_HICP6 (0x0800U) +#define TMRA_CCONR_NOFIENCP_POS (12U) +#define TMRA_CCONR_NOFIENCP (0x1000U) +#define TMRA_CCONR_NOFICKCP_POS (13U) +#define TMRA_CCONR_NOFICKCP (0x6000U) +#define TMRA_CCONR_NOFICKCP_0 (0x2000U) +#define TMRA_CCONR_NOFICKCP_1 (0x4000U) + +/* Bit definition for TMRA_PCONR register */ +#define TMRA_PCONR_STAC_POS (0U) +#define TMRA_PCONR_STAC (0x0003U) +#define TMRA_PCONR_STAC_0 (0x0001U) +#define TMRA_PCONR_STAC_1 (0x0002U) +#define TMRA_PCONR_STPC_POS (2U) +#define TMRA_PCONR_STPC (0x000CU) +#define TMRA_PCONR_STPC_0 (0x0004U) +#define TMRA_PCONR_STPC_1 (0x0008U) +#define TMRA_PCONR_CMPC_POS (4U) +#define TMRA_PCONR_CMPC (0x0030U) +#define TMRA_PCONR_CMPC_0 (0x0010U) +#define TMRA_PCONR_CMPC_1 (0x0020U) +#define TMRA_PCONR_PERC_POS (6U) +#define TMRA_PCONR_PERC (0x00C0U) +#define TMRA_PCONR_PERC_0 (0x0040U) +#define TMRA_PCONR_PERC_1 (0x0080U) +#define TMRA_PCONR_FORC_POS (8U) +#define TMRA_PCONR_FORC (0x0300U) +#define TMRA_PCONR_FORC_0 (0x0100U) +#define TMRA_PCONR_FORC_1 (0x0200U) +#define TMRA_PCONR_OUTEN_POS (12U) +#define TMRA_PCONR_OUTEN (0x1000U) + +/******************************************************************************* + Bit definition for Peripheral TRNG +*******************************************************************************/ +/* Bit definition for TRNG_CR register */ +#define TRNG_CR_EN_POS (0U) +#define TRNG_CR_EN (0x00000001UL) +#define TRNG_CR_RUN_POS (1U) +#define TRNG_CR_RUN (0x00000002UL) + +/* Bit definition for TRNG_MR register */ +#define TRNG_MR_LOAD_POS (0U) +#define TRNG_MR_LOAD (0x00000001UL) +#define TRNG_MR_CNT_POS (2U) +#define TRNG_MR_CNT (0x0000001CUL) + +/* Bit definition for TRNG_DR0 register */ +#define TRNG_DR0 (0xFFFFFFFFUL) + +/* Bit definition for TRNG_DR1 register */ +#define TRNG_DR1 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USART +*******************************************************************************/ +/* Bit definition for USART_SR register */ +#define USART_SR_PE_POS (0U) +#define USART_SR_PE (0x00000001UL) +#define USART_SR_FE_POS (1U) +#define USART_SR_FE (0x00000002UL) +#define USART_SR_ORE_POS (3U) +#define USART_SR_ORE (0x00000008UL) +#define USART_SR_BE_POS (4U) +#define USART_SR_BE (0x00000010UL) +#define USART_SR_RXNE_POS (5U) +#define USART_SR_RXNE (0x00000020UL) +#define USART_SR_TC_POS (6U) +#define USART_SR_TC (0x00000040UL) +#define USART_SR_TXE_POS (7U) +#define USART_SR_TXE (0x00000080UL) +#define USART_SR_RTOF_POS (8U) +#define USART_SR_RTOF (0x00000100UL) +#define USART_SR_WKUP_POS (9U) +#define USART_SR_WKUP (0x00000200UL) +#define USART_SR_LBD_POS (10U) +#define USART_SR_LBD (0x00000400UL) +#define USART_SR_TEND_POS (11U) +#define USART_SR_TEND (0x00000800UL) +#define USART_SR_MPB_POS (16U) +#define USART_SR_MPB (0x00010000UL) + +/* Bit definition for USART_TDR register */ +#define USART_TDR_TDR_POS (0U) +#define USART_TDR_TDR (0x01FFU) +#define USART_TDR_MPID_POS (9U) +#define USART_TDR_MPID (0x0200U) + +/* Bit definition for USART_RDR register */ +#define USART_RDR_RDR (0x01FFU) + +/* Bit definition for USART_BRR register */ +#define USART_BRR_DIV_FRACTION_POS (0U) +#define USART_BRR_DIV_FRACTION (0x0000007FUL) +#define USART_BRR_DIV_INTEGER_POS (8U) +#define USART_BRR_DIV_INTEGER (0x0000FF00UL) + +/* Bit definition for USART_CR1 register */ +#define USART_CR1_RTOE_POS (0U) +#define USART_CR1_RTOE (0x00000001UL) +#define USART_CR1_RTOIE_POS (1U) +#define USART_CR1_RTOIE (0x00000002UL) +#define USART_CR1_RE_POS (2U) +#define USART_CR1_RE (0x00000004UL) +#define USART_CR1_TE_POS (3U) +#define USART_CR1_TE (0x00000008UL) +#define USART_CR1_SLME_POS (4U) +#define USART_CR1_SLME (0x00000010UL) +#define USART_CR1_RIE_POS (5U) +#define USART_CR1_RIE (0x00000020UL) +#define USART_CR1_TCIE_POS (6U) +#define USART_CR1_TCIE (0x00000040UL) +#define USART_CR1_TXEIE_POS (7U) +#define USART_CR1_TXEIE (0x00000080UL) +#define USART_CR1_TENDIE_POS (8U) +#define USART_CR1_TENDIE (0x00000100UL) +#define USART_CR1_PS_POS (9U) +#define USART_CR1_PS (0x00000200UL) +#define USART_CR1_PCE_POS (10U) +#define USART_CR1_PCE (0x00000400UL) +#define USART_CR1_M_POS (12U) +#define USART_CR1_M (0x00001000UL) +#define USART_CR1_OVER8_POS (15U) +#define USART_CR1_OVER8 (0x00008000UL) +#define USART_CR1_CPE_POS (16U) +#define USART_CR1_CPE (0x00010000UL) +#define USART_CR1_CFE_POS (17U) +#define USART_CR1_CFE (0x00020000UL) +#define USART_CR1_CORE_POS (19U) +#define USART_CR1_CORE (0x00080000UL) +#define USART_CR1_CRTOF_POS (20U) +#define USART_CR1_CRTOF (0x00100000UL) +#define USART_CR1_CBE_POS (21U) +#define USART_CR1_CBE (0x00200000UL) +#define USART_CR1_CWKUP_POS (22U) +#define USART_CR1_CWKUP (0x00400000UL) +#define USART_CR1_CLBD_POS (23U) +#define USART_CR1_CLBD (0x00800000UL) +#define USART_CR1_MS_POS (24U) +#define USART_CR1_MS (0x01000000UL) +#define USART_CR1_CTEND_POS (25U) +#define USART_CR1_CTEND (0x02000000UL) +#define USART_CR1_ML_POS (28U) +#define USART_CR1_ML (0x10000000UL) +#define USART_CR1_FBME_POS (29U) +#define USART_CR1_FBME (0x20000000UL) +#define USART_CR1_NFE_POS (30U) +#define USART_CR1_NFE (0x40000000UL) +#define USART_CR1_SBS_POS (31U) +#define USART_CR1_SBS (0x80000000UL) + +/* Bit definition for USART_CR2 register */ +#define USART_CR2_MPE_POS (0U) +#define USART_CR2_MPE (0x00000001UL) +#define USART_CR2_WKUPIE_POS (1U) +#define USART_CR2_WKUPIE (0x00000002UL) +#define USART_CR2_BEIE_POS (2U) +#define USART_CR2_BEIE (0x00000004UL) +#define USART_CR2_BEE_POS (3U) +#define USART_CR2_BEE (0x00000008UL) +#define USART_CR2_LBDIE_POS (4U) +#define USART_CR2_LBDIE (0x00000010UL) +#define USART_CR2_LBDL_POS (5U) +#define USART_CR2_LBDL (0x00000020UL) +#define USART_CR2_SBKL_POS (6U) +#define USART_CR2_SBKL (0x000000C0UL) +#define USART_CR2_SBKL_0 (0x00000040UL) +#define USART_CR2_SBKL_1 (0x00000080UL) +#define USART_CR2_WKUPE_POS (8U) +#define USART_CR2_WKUPE (0x00000100UL) +#define USART_CR2_CLKC_POS (11U) +#define USART_CR2_CLKC (0x00001800UL) +#define USART_CR2_CLKC_0 (0x00000800UL) +#define USART_CR2_CLKC_1 (0x00001000UL) +#define USART_CR2_STOP_POS (13U) +#define USART_CR2_STOP (0x00002000UL) +#define USART_CR2_LINEN_POS (14U) +#define USART_CR2_LINEN (0x00004000UL) +#define USART_CR2_SBK_POS (16U) +#define USART_CR2_SBK (0x00010000UL) +#define USART_CR2_SBKM_POS (17U) +#define USART_CR2_SBKM (0x00020000UL) + +/* Bit definition for USART_CR3 register */ +#define USART_CR3_HDSEL_POS (3U) +#define USART_CR3_HDSEL (0x00000008UL) +#define USART_CR3_LOOP_POS (4U) +#define USART_CR3_LOOP (0x00000010UL) +#define USART_CR3_SCEN_POS (5U) +#define USART_CR3_SCEN (0x00000020UL) +#define USART_CR3_RTSE_POS (8U) +#define USART_CR3_RTSE (0x00000100UL) +#define USART_CR3_CTSE_POS (9U) +#define USART_CR3_CTSE (0x00000200UL) +#define USART_CR3_BCN_POS (21U) +#define USART_CR3_BCN (0x00E00000UL) + +/* Bit definition for USART_PR register */ +#define USART_PR_PSC_POS (0U) +#define USART_PR_PSC (0x00000003UL) +#define USART_PR_PSC_0 (0x00000001UL) +#define USART_PR_PSC_1 (0x00000002UL) +#define USART_PR_LBMPSC_POS (2U) +#define USART_PR_LBMPSC (0x0000000CUL) +#define USART_PR_LBMPSC_0 (0x00000004UL) +#define USART_PR_LBMPSC_1 (0x00000008UL) +#define USART_PR_ULBREN_POS (4U) +#define USART_PR_ULBREN (0x00000010UL) + +/* Bit definition for USART_LBMC register */ +#define USART_LBMC_LBMC (0x0000FFFFUL) +#define USART_LBMC_LBMC_0 (0x00000001UL) +#define USART_LBMC_LBMC_1 (0x00000002UL) +#define USART_LBMC_LBMC_2 (0x00000004UL) +#define USART_LBMC_LBMC_3 (0x00000008UL) +#define USART_LBMC_LBMC_4 (0x00000010UL) +#define USART_LBMC_LBMC_5 (0x00000020UL) +#define USART_LBMC_LBMC_6 (0x00000040UL) +#define USART_LBMC_LBMC_7 (0x00000080UL) +#define USART_LBMC_LBMC_8 (0x00000100UL) +#define USART_LBMC_LBMC_9 (0x00000200UL) +#define USART_LBMC_LBMC_10 (0x00000400UL) +#define USART_LBMC_LBMC_11 (0x00000800UL) +#define USART_LBMC_LBMC_12 (0x00001000UL) +#define USART_LBMC_LBMC_13 (0x00002000UL) +#define USART_LBMC_LBMC_14 (0x00004000UL) +#define USART_LBMC_LBMC_15 (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral WDT +*******************************************************************************/ +/* Bit definition for WDT_CR register */ +#define WDT_CR_PERI_POS (0U) +#define WDT_CR_PERI (0x00000003UL) +#define WDT_CR_PERI_0 (0x00000001UL) +#define WDT_CR_PERI_1 (0x00000002UL) +#define WDT_CR_CKS_POS (4U) +#define WDT_CR_CKS (0x000000F0UL) +#define WDT_CR_WDPT_POS (8U) +#define WDT_CR_WDPT (0x00000F00UL) +#define WDT_CR_SLPOFF_POS (16U) +#define WDT_CR_SLPOFF (0x00010000UL) +#define WDT_CR_ITS_POS (31U) +#define WDT_CR_ITS (0x80000000UL) + +/* Bit definition for WDT_SR register */ +#define WDT_SR_CNT_POS (0U) +#define WDT_SR_CNT (0x0000FFFFUL) +#define WDT_SR_UDF_POS (16U) +#define WDT_SR_UDF (0x00010000UL) +#define WDT_SR_REF_POS (17U) +#define WDT_SR_REF (0x00020000UL) + +/* Bit definition for WDT_RR register */ +#define WDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************/ +/* Device Specific Registers bit_band structure */ +/******************************************************************************/ + +typedef struct { + __IO uint32_t STRT; + uint32_t RESERVED0[7]; +} stc_adc_str_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t CLREN; + __IO uint32_t DFMT; + uint32_t RESERVED1[8]; +} stc_adc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t RSCHSEL; + uint32_t RESERVED1[13]; +} stc_adc_cr1_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t OVSMOD; + uint32_t RESERVED1[3]; +} stc_adc_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t TRGENA; + uint32_t RESERVED1[7]; + __IO uint32_t TRGENB; +} stc_adc_trgsr_bit_t; + +typedef struct { + __IO uint32_t EXCHSEL; + uint32_t RESERVED0[7]; +} stc_adc_exchselr_bit_t; + +typedef struct { + __I uint32_t EOCAF; + __I uint32_t EOCBF; + uint32_t RESERVED0[2]; + __I uint32_t SASTPDF; + uint32_t RESERVED1[3]; +} stc_adc_isr_bit_t; + +typedef struct { + __IO uint32_t EOCAIEN; + __IO uint32_t EOCBIEN; + uint32_t RESERVED0[6]; +} stc_adc_icr_bit_t; + +typedef struct { + __O uint32_t CLREOCAF; + __O uint32_t CLREOCBF; + uint32_t RESERVED0[2]; + __O uint32_t CLRSASTPDF; + uint32_t RESERVED1[3]; +} stc_adc_isclrr_bit_t; + +typedef struct { + __IO uint32_t SYNCEN; + uint32_t RESERVED0[15]; +} stc_adc_synccr_bit_t; + +typedef struct { + __IO uint32_t AWD0EN; + __IO uint32_t AWD0IEN; + __IO uint32_t AWD0MD; + uint32_t RESERVED0[1]; + __IO uint32_t AWD1EN; + __IO uint32_t AWD1IEN; + __IO uint32_t AWD1MD; + uint32_t RESERVED1[9]; +} stc_adc_awdcr_bit_t; + +typedef struct { + __I uint32_t AWD0F; + __I uint32_t AWD1F; + uint32_t RESERVED0[2]; + __I uint32_t AWDCMF; + uint32_t RESERVED1[3]; +} stc_adc_awdsr_bit_t; + +typedef struct { + __O uint32_t CLRAWD0F; + __O uint32_t CLRAWD1F; + uint32_t RESERVED0[2]; + __O uint32_t CLRAWDCMF; + uint32_t RESERVED1[3]; +} stc_adc_awdsclrr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t MODE; + uint32_t RESERVED0[30]; +} stc_aes_cr_bit_t; + +typedef struct { + __O uint32_t STRG; + uint32_t RESERVED0[31]; +} stc_aos_intsfttrg_bit_t; + +typedef struct { + __IO uint32_t NFEN1; + uint32_t RESERVED0[7]; + __IO uint32_t NFEN2; + uint32_t RESERVED1[7]; + __IO uint32_t NFEN3; + uint32_t RESERVED2[7]; + __IO uint32_t NFEN4; + uint32_t RESERVED3[7]; +} stc_aos_pevntnfcr_bit_t; + +typedef struct { + __IO uint32_t CENA; + __IO uint32_t CWDE; + uint32_t RESERVED0[2]; + __IO uint32_t CSST; + uint32_t RESERVED1[2]; + __I uint32_t CMON; +} stc_cmp_mdr_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t CIEN; + uint32_t RESERVED1[2]; + __IO uint32_t CFF; + __IO uint32_t CRF; +} stc_cmp_fir_bit_t; + +typedef struct { + __IO uint32_t COEN; + __IO uint32_t COPS; + __IO uint32_t CPOE; + uint32_t RESERVED0[1]; + __IO uint32_t BWEN; + __IO uint32_t BWMD; + uint32_t RESERVED1[2]; +} stc_cmp_ocr_bit_t; + +typedef struct { + __IO uint32_t CTWS0; + __IO uint32_t CTWS1; + __IO uint32_t CTWS2; + __IO uint32_t CTWS3; + __IO uint32_t CTWS4; + __IO uint32_t CTWS5; + __IO uint32_t CTWS6; + __IO uint32_t CTWS7; + __IO uint32_t CTWS8; + __IO uint32_t CTWS9; + __IO uint32_t CTWS10; + __IO uint32_t CTWS11; + __IO uint32_t CTWS12; + __IO uint32_t CTWS13; + __IO uint32_t CTWS14; + __IO uint32_t CTWS15; + __IO uint32_t CTWP0; + __IO uint32_t CTWP1; + __IO uint32_t CTWP2; + __IO uint32_t CTWP3; + __IO uint32_t CTWP4; + __IO uint32_t CTWP5; + __IO uint32_t CTWP6; + __IO uint32_t CTWP7; + __IO uint32_t CTWP8; + __IO uint32_t CTWP9; + __IO uint32_t CTWP10; + __IO uint32_t CTWP11; + __IO uint32_t CTWP12; + __IO uint32_t CTWP13; + __IO uint32_t CTWP14; + __IO uint32_t CTWP15; +} stc_cmp_bwsr1_bit_t; + +typedef struct { + __IO uint32_t FRADIVEN; + uint32_t RESERVED0[31]; +} stc_cmu_xtaldivcr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t XTALMS; + uint32_t RESERVED1[1]; +} stc_cmu_xtalcfgr_bit_t; + +typedef struct { + __IO uint32_t XTAL32STP; + uint32_t RESERVED0[7]; +} stc_cmu_xtal32cr_bit_t; + +typedef struct { + __IO uint32_t LRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_lrccr_bit_t; + +typedef struct { + __IO uint32_t PLLHOFF; + uint32_t RESERVED0[7]; +} stc_cmu_pllhcr_bit_t; + +typedef struct { + __IO uint32_t XTALSTP; + uint32_t RESERVED0[7]; +} stc_cmu_xtalcr_bit_t; + +typedef struct { + __IO uint32_t HRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_hrccr_bit_t; + +typedef struct { + __IO uint32_t MRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_mrccr_bit_t; + +typedef struct { + __IO uint32_t HRCSTBF; + uint32_t RESERVED0[2]; + __IO uint32_t XTALSTBF; + uint32_t RESERVED1[1]; + __IO uint32_t PLLHSTBF; + uint32_t RESERVED2[2]; +} stc_cmu_oscstbsr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t MCOEN; +} stc_cmu_mcocfgr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t TPIUCKOE; +} stc_cmu_tpiuckcfgr_bit_t; + +typedef struct { + __IO uint32_t XTALSTDIE; + __IO uint32_t XTALSTDRE; + __IO uint32_t XTALSTDRIS; + uint32_t RESERVED0[4]; + __IO uint32_t XTALSTDE; +} stc_cmu_xtalstdcr_bit_t; + +typedef struct { + __IO uint32_t XTALSTDF; + uint32_t RESERVED0[7]; +} stc_cmu_xtalstdsr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t PLLSRC; + uint32_t RESERVED1[24]; +} stc_cmu_pllhcfgr_bit_t; + +typedef struct { + __IO uint32_t CR; + __I uint32_t FLAG; + uint32_t RESERVED0[30]; +} stc_crc_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t ERRIE; + __IO uint32_t CTCEN; + uint32_t RESERVED1[24]; +} stc_ctc_cr1_bit_t; + +typedef struct { + __I uint32_t TRIMOK; + __I uint32_t TRMOVF; + __I uint32_t TRMUDF; + __I uint32_t CTCBSY; + uint32_t RESERVED0[28]; +} stc_ctc_str_bit_t; + +typedef struct { + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DL0R4; + __IO uint32_t DL1R5; + __IO uint32_t DL2R6; + __IO uint32_t DL3R7; + __IO uint32_t DL4R8; + __IO uint32_t DL5R9; + __IO uint32_t DL6R10; + __IO uint32_t DL7R11; + __IO uint32_t DL8; + __IO uint32_t DL9; + __IO uint32_t DL10; + __IO uint32_t DL11; +} stc_dac_dadr1_bit_t; + +typedef struct { + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DL0R4; + __IO uint32_t DL1R5; + __IO uint32_t DL2R6; + __IO uint32_t DL3R7; + __IO uint32_t DL4R8; + __IO uint32_t DL5R9; + __IO uint32_t DL6R10; + __IO uint32_t DL7R11; + __IO uint32_t DL8; + __IO uint32_t DL9; + __IO uint32_t DL10; + __IO uint32_t DL11; +} stc_dac_dadr2_bit_t; + +typedef struct { + __IO uint32_t DAE; + __IO uint32_t DA1E; + __IO uint32_t DA2E; + uint32_t RESERVED0[5]; + __IO uint32_t DPSEL; + __IO uint32_t DAAMP1; + __IO uint32_t DAAMP2; + __IO uint32_t EXTDSL1; + __IO uint32_t EXTDSL2; + uint32_t RESERVED1[3]; +} stc_dac_dacr_bit_t; + +typedef struct { + __IO uint32_t ADCSL1; + __IO uint32_t ADCSL2; + __IO uint32_t ADCSL3; + uint32_t RESERVED0[5]; + __I uint32_t DA1SF; + __I uint32_t DA2SF; + uint32_t RESERVED1[5]; + __IO uint32_t ADPEN; +} stc_dac_daadpcr_bit_t; + +typedef struct { + uint32_t RESERVED0[14]; + __IO uint32_t DAODIS1; + __IO uint32_t DAODIS2; +} stc_dac_daocr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t COMPTRG; + uint32_t RESERVED1[22]; + __IO uint32_t INTEN; +} stc_dcu_ctl_bit_t; + +typedef struct { + __I uint32_t FLAG_OP; + __I uint32_t FLAG_LS2; + __I uint32_t FLAG_EQ2; + __I uint32_t FLAG_GT2; + __I uint32_t FLAG_LS1; + __I uint32_t FLAG_EQ1; + __I uint32_t FLAG_GT1; + uint32_t RESERVED0[2]; + __I uint32_t FLAG_RLD; + __I uint32_t FLAG_BTM; + __I uint32_t FLAG_TOP; + uint32_t RESERVED1[20]; +} stc_dcu_flag_bit_t; + +typedef struct { + __O uint32_t CLR_OP; + __O uint32_t CLR_LS2; + __O uint32_t CLR_EQ2; + __O uint32_t CLR_GT2; + __O uint32_t CLR_LS1; + __O uint32_t CLR_EQ1; + __O uint32_t CLR_GT1; + uint32_t RESERVED0[2]; + __O uint32_t CLR_RLD; + __O uint32_t CLR_BTM; + __O uint32_t CLR_TOP; + uint32_t RESERVED1[20]; +} stc_dcu_flagclr_bit_t; + +typedef struct { + __IO uint32_t SEL_OP; + __IO uint32_t SEL_LS2; + __IO uint32_t SEL_EQ2; + __IO uint32_t SEL_GT2; + __IO uint32_t SEL_LS1; + __IO uint32_t SEL_EQ1; + __IO uint32_t SEL_GT1; + uint32_t RESERVED0[3]; + __IO uint32_t SEL_BTM; + __IO uint32_t SEL_TOP; + uint32_t RESERVED1[20]; +} stc_dcu_intevtsel_bit_t; + +typedef struct { + __IO uint32_t EN; + uint32_t RESERVED0[31]; +} stc_dma_en_bit_t; + +typedef struct { + __I uint32_t TRNERR0; + __I uint32_t TRNERR1; + __I uint32_t TRNERR2; + __I uint32_t TRNERR3; + __I uint32_t TRNERR4; + __I uint32_t TRNERR5; + uint32_t RESERVED0[10]; + __I uint32_t REQERR0; + __I uint32_t REQERR1; + __I uint32_t REQERR2; + __I uint32_t REQERR3; + __I uint32_t REQERR4; + __I uint32_t REQERR5; + uint32_t RESERVED1[10]; +} stc_dma_intstat0_bit_t; + +typedef struct { + __I uint32_t TC0; + __I uint32_t TC1; + __I uint32_t TC2; + __I uint32_t TC3; + __I uint32_t TC4; + __I uint32_t TC5; + uint32_t RESERVED0[10]; + __I uint32_t BTC0; + __I uint32_t BTC1; + __I uint32_t BTC2; + __I uint32_t BTC3; + __I uint32_t BTC4; + __I uint32_t BTC5; + uint32_t RESERVED1[10]; +} stc_dma_intstat1_bit_t; + +typedef struct { + __IO uint32_t MSKTRNERR0; + __IO uint32_t MSKTRNERR1; + __IO uint32_t MSKTRNERR2; + __IO uint32_t MSKTRNERR3; + __IO uint32_t MSKTRNERR4; + __IO uint32_t MSKTRNERR5; + uint32_t RESERVED0[10]; + __IO uint32_t MSKREQERR0; + __IO uint32_t MSKREQERR1; + __IO uint32_t MSKREQERR2; + __IO uint32_t MSKREQERR3; + __IO uint32_t MSKREQERR4; + __IO uint32_t MSKREQERR5; + uint32_t RESERVED1[10]; +} stc_dma_intmask0_bit_t; + +typedef struct { + __IO uint32_t MSKTC0; + __IO uint32_t MSKTC1; + __IO uint32_t MSKTC2; + __IO uint32_t MSKTC3; + __IO uint32_t MSKTC4; + __IO uint32_t MSKTC5; + uint32_t RESERVED0[10]; + __IO uint32_t MSKBTC0; + __IO uint32_t MSKBTC1; + __IO uint32_t MSKBTC2; + __IO uint32_t MSKBTC3; + __IO uint32_t MSKBTC4; + __IO uint32_t MSKBTC5; + uint32_t RESERVED1[10]; +} stc_dma_intmask1_bit_t; + +typedef struct { + __O uint32_t CLRTRNERR0; + __O uint32_t CLRTRNERR1; + __O uint32_t CLRTRNERR2; + __O uint32_t CLRTRNERR3; + __O uint32_t CLRTRNERR4; + __O uint32_t CLRTRNERR5; + uint32_t RESERVED0[10]; + __O uint32_t CLRREQERR0; + __O uint32_t CLRREQERR1; + __O uint32_t CLRREQERR2; + __O uint32_t CLRREQERR3; + __O uint32_t CLRREQERR4; + __O uint32_t CLRREQERR5; + uint32_t RESERVED1[10]; +} stc_dma_intclr0_bit_t; + +typedef struct { + __O uint32_t CLRTC0; + __O uint32_t CLRTC1; + __O uint32_t CLRTC2; + __O uint32_t CLRTC3; + __O uint32_t CLRTC4; + __O uint32_t CLRTC5; + uint32_t RESERVED0[10]; + __O uint32_t CLRBTC0; + __O uint32_t CLRBTC1; + __O uint32_t CLRBTC2; + __O uint32_t CLRBTC3; + __O uint32_t CLRBTC4; + __O uint32_t CLRBTC5; + uint32_t RESERVED1[10]; +} stc_dma_intclr1_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t RCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_reqstat_bit_t; + +typedef struct { + __I uint32_t DMAACT; + __I uint32_t RCFGACT; + uint32_t RESERVED0[30]; +} stc_dma_chstat_bit_t; + +typedef struct { + __IO uint32_t RCFGEN; + __IO uint32_t RCFGLLP; + uint32_t RESERVED0[30]; +} stc_dma_rcfgctl_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t SRPTEN; + __IO uint32_t DRPTEN; + __IO uint32_t SNSEQEN; + __IO uint32_t DNSEQEN; + uint32_t RESERVED1[2]; + __IO uint32_t LLPEN; + __IO uint32_t LLPRUN; + __IO uint32_t IE; + uint32_t RESERVED2[19]; +} stc_dma_chctl_bit_t; + +typedef struct { + __IO uint32_t FSTP; + uint32_t RESERVED0[31]; +} stc_efm_fstp_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t LVM; + uint32_t RESERVED1[7]; + __IO uint32_t ICACHE; + __IO uint32_t DCACHE; + __IO uint32_t PREFETE; + __IO uint32_t CRST; + uint32_t RESERVED2[12]; +} stc_efm_frmc_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t BUSHLDCTL; + uint32_t RESERVED1[7]; + __IO uint32_t KEY1LOCK; + __IO uint32_t KEY2LOCK; + uint32_t RESERVED2[14]; +} stc_efm_fwmc_bit_t; + +typedef struct { + __I uint32_t OTPWERR; + __I uint32_t PRTWERR; + __I uint32_t PGSZERR; + __I uint32_t MISMTCH; + __I uint32_t OPTEND; + __I uint32_t COLERR; + uint32_t RESERVED0[2]; + __I uint32_t RDY; + uint32_t RESERVED1[23]; +} stc_efm_fsr_bit_t; + +typedef struct { + __IO uint32_t OTPWERRCLR; + __IO uint32_t PRTWERRCLR; + __IO uint32_t PGSZERRCLR; + __IO uint32_t MISMTCHCLR; + __IO uint32_t OPTENDCLR; + __IO uint32_t COLERRCLR; + uint32_t RESERVED0[26]; +} stc_efm_fsclr_bit_t; + +typedef struct { + __IO uint32_t PEERRITE; + __IO uint32_t OPTENDITE; + __IO uint32_t COLERRITE; + uint32_t RESERVED0[29]; +} stc_efm_fite_bit_t; + +typedef struct { + __I uint32_t FSWP; + uint32_t RESERVED0[31]; +} stc_efm_fswp_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t EN; +} stc_efm_mmf_remcr_bit_t; + +typedef struct { + __IO uint32_t WLOCK0; + uint32_t RESERVED0[31]; +} stc_efm_wlock_bit_t; + +typedef struct { + __IO uint32_t F0NWPRT0; + __IO uint32_t F0NWPRT1; + __IO uint32_t F0NWPRT2; + __IO uint32_t F0NWPRT3; + __IO uint32_t F0NWPRT4; + __IO uint32_t F0NWPRT5; + __IO uint32_t F0NWPRT6; + __IO uint32_t F0NWPRT7; + __IO uint32_t F0NWPRT8; + __IO uint32_t F0NWPRT9; + __IO uint32_t F0NWPRT10; + __IO uint32_t F0NWPRT11; + __IO uint32_t F0NWPRT12; + __IO uint32_t F0NWPRT13; + __IO uint32_t F0NWPRT14; + __IO uint32_t F0NWPRT15; + __IO uint32_t F0NWPRT16; + __IO uint32_t F0NWPRT17; + __IO uint32_t F0NWPRT18; + __IO uint32_t F0NWPRT19; + __IO uint32_t F0NWPRT20; + __IO uint32_t F0NWPRT21; + __IO uint32_t F0NWPRT22; + __IO uint32_t F0NWPRT23; + __IO uint32_t F0NWPRT24; + __IO uint32_t F0NWPRT25; + __IO uint32_t F0NWPRT26; + __IO uint32_t F0NWPRT27; + __IO uint32_t F0NWPRT28; + __IO uint32_t F0NWPRT29; + __IO uint32_t F0NWPRT30; + __IO uint32_t F0NWPRT31; +} stc_efm_f0nwprt_bit_t; + +typedef struct { + __IO uint32_t CMPEN1; + __IO uint32_t CMPEN2; + __IO uint32_t CMPEN3; + __IO uint32_t CMPEN4; + __IO uint32_t SYSEN; + __IO uint32_t PWMSEN0; + __IO uint32_t PWMSEN1; + __IO uint32_t PWMSEN2; + __IO uint32_t PWMSEN3; + uint32_t RESERVED0[7]; + __IO uint32_t PORTINEN1; + __IO uint32_t PORTINEN2; + __IO uint32_t PORTINEN3; + __IO uint32_t PORTINEN4; + uint32_t RESERVED1[2]; + __IO uint32_t INVSEL1; + __IO uint32_t INVSEL2; + __IO uint32_t INVSEL3; + __IO uint32_t INVSEL4; + uint32_t RESERVED2[1]; + __IO uint32_t OSCSTPEN; + __IO uint32_t SRAMECCERREN; + __IO uint32_t SRAMPYERREN; + __IO uint32_t LOCKUPEN; + __IO uint32_t PVDEN; +} stc_emb_ctl1_bit_t; + +typedef struct { + __IO uint32_t PWMLV0; + __IO uint32_t PWMLV1; + __IO uint32_t PWMLV2; + __IO uint32_t PWMLV3; + uint32_t RESERVED0[14]; + __IO uint32_t NFEN1; + uint32_t RESERVED1[2]; + __IO uint32_t NFEN2; + uint32_t RESERVED2[2]; + __IO uint32_t NFEN3; + uint32_t RESERVED3[2]; + __IO uint32_t NFEN4; + uint32_t RESERVED4[4]; +} stc_emb_ctl2_bit_t; + +typedef struct { + __IO uint32_t SOE; + uint32_t RESERVED0[31]; +} stc_emb_soe_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t PWMSF; + __I uint32_t CMPF; + __I uint32_t SYSF; + uint32_t RESERVED1[1]; + __I uint32_t PWMST; + __I uint32_t CMPST; + __I uint32_t SYSST; + __I uint32_t PORTINF1; + __I uint32_t PORTINF2; + __I uint32_t PORTINF3; + __I uint32_t PORTINF4; + uint32_t RESERVED2[2]; + __I uint32_t PORTINST1; + __I uint32_t PORTINST2; + __I uint32_t PORTINST3; + __I uint32_t PORTINST4; + uint32_t RESERVED3[14]; +} stc_emb_stat_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __O uint32_t PWMSFCLR; + __O uint32_t CMPFCLR; + __O uint32_t SYSFCLR; + uint32_t RESERVED1[4]; + __O uint32_t PORTINFCLR1; + __O uint32_t PORTINFCLR2; + __O uint32_t PORTINFCLR3; + __O uint32_t PORTINFCLR4; + uint32_t RESERVED2[20]; +} stc_emb_statclr_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t PWMSINTEN; + __IO uint32_t CMPINTEN; + __IO uint32_t SYSINTEN; + uint32_t RESERVED1[4]; + __IO uint32_t PORTININTEN1; + __IO uint32_t PORTININTEN2; + __IO uint32_t PORTININTEN3; + __IO uint32_t PORTININTEN4; + uint32_t RESERVED2[20]; +} stc_emb_inten_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t PWMRSEL; + __IO uint32_t CMPRSEL; + __IO uint32_t SYSRSEL; + uint32_t RESERVED1[4]; + __IO uint32_t PORTINRSEL1; + __IO uint32_t PORTINRSEL2; + __IO uint32_t PORTINRSEL3; + __IO uint32_t PORTINRSEL4; + uint32_t RESERVED2[20]; +} stc_emb_rlssel_bit_t; + +typedef struct { + __IO uint32_t START; + uint32_t RESERVED0[31]; +} stc_fcm_str_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t INEXS; + uint32_t RESERVED1[7]; + __IO uint32_t EXREFE; + uint32_t RESERVED2[16]; +} stc_fcm_rccr_bit_t; + +typedef struct { + __IO uint32_t ERRIE; + __IO uint32_t MENDIE; + __IO uint32_t OVFIE; + uint32_t RESERVED0[1]; + __IO uint32_t ERRINTRS; + uint32_t RESERVED1[2]; + __IO uint32_t ERRE; + uint32_t RESERVED2[24]; +} stc_fcm_rier_bit_t; + +typedef struct { + __I uint32_t ERRF; + __I uint32_t MENDF; + __I uint32_t OVF; + uint32_t RESERVED0[29]; +} stc_fcm_sr_bit_t; + +typedef struct { + __O uint32_t ERRFCLR; + __O uint32_t MENDFCLR; + __O uint32_t OVFCLR; + uint32_t RESERVED0[29]; +} stc_fcm_clr_bit_t; + +typedef struct { + __I uint32_t PIN00; + __I uint32_t PIN01; + __I uint32_t PIN02; + __I uint32_t PIN03; + __I uint32_t PIN04; + __I uint32_t PIN05; + __I uint32_t PIN06; + __I uint32_t PIN07; + __I uint32_t PIN08; + __I uint32_t PIN09; + __I uint32_t PIN10; + __I uint32_t PIN11; + __I uint32_t PIN12; + __I uint32_t PIN13; + __I uint32_t PIN14; + __I uint32_t PIN15; +} stc_gpio_pidr_bit_t; + +typedef struct { + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podr_bit_t; + +typedef struct { + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poer_bit_t; + +typedef struct { + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posr_bit_t; + +typedef struct { + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porr_bit_t; + +typedef struct { + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potr_bit_t; + +typedef struct { + __IO uint32_t WE; + uint32_t RESERVED0[15]; +} stc_gpio_pwpr_bit_t; + +typedef struct { + __IO uint32_t POUT; + __IO uint32_t POUTE; + __IO uint32_t NOD; + uint32_t RESERVED0[3]; + __IO uint32_t PUU; + __IO uint32_t PUD; + __I uint32_t PIN; + __IO uint32_t INVE; + __IO uint32_t CINSEL; + uint32_t RESERVED1[1]; + __IO uint32_t INTE; + __IO uint32_t PINAE; + __IO uint32_t LTE; + __IO uint32_t DDIS; +} stc_gpio_pcr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t BFE; + uint32_t RESERVED1[7]; +} stc_gpio_pfsr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t FST_GRP; + uint32_t RESERVED0[30]; +} stc_hash_cr_bit_t; + +typedef struct { + __IO uint32_t PE; + __IO uint32_t SMBUS; + __IO uint32_t SMBALRTEN; + __IO uint32_t SMBDEFAULTEN; + __IO uint32_t SMBHOSTEN; + uint32_t RESERVED0[1]; + __IO uint32_t ENGC; + __IO uint32_t RESTART; + __IO uint32_t START; + __IO uint32_t STOP; + __IO uint32_t ACK; + uint32_t RESERVED1[4]; + __IO uint32_t SWRST; + uint32_t RESERVED2[16]; +} stc_i2c_cr1_bit_t; + +typedef struct { + __IO uint32_t STARTIE; + __IO uint32_t SLADDR0IE; + __IO uint32_t SLADDR1IE; + __IO uint32_t TENDIE; + __IO uint32_t STOPIE; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLIE; + __IO uint32_t TEMPTYIE; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOIE; + uint32_t RESERVED2[1]; + __IO uint32_t RFREQIE; + __IO uint32_t NACKIE; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTIE; + uint32_t RESERVED4[5]; + __IO uint32_t GENCALLIE; + __IO uint32_t SMBDEFAULTIE; + __IO uint32_t SMBHOSTIE; + __IO uint32_t SMBALRTIE; + uint32_t RESERVED5[8]; +} stc_i2c_cr2_bit_t; + +typedef struct { + __IO uint32_t TMOUTEN; + __IO uint32_t LTMOUT; + __IO uint32_t HTMOUT; + uint32_t RESERVED0[4]; + __IO uint32_t FACKEN; + uint32_t RESERVED1[24]; +} stc_i2c_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[10]; + __IO uint32_t BUSWAIT; + uint32_t RESERVED1[1]; + __IO uint32_t BUSFREECLREN; + uint32_t RESERVED2[19]; +} stc_i2c_cr4_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR0EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD0; + uint32_t RESERVED2[10]; + __IO uint32_t MASKEN0; + uint32_t RESERVED3[5]; +} stc_i2c_slr0_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR1EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD1; + uint32_t RESERVED2[10]; + __IO uint32_t MASKEN1; + uint32_t RESERVED3[5]; +} stc_i2c_slr1_bit_t; + +typedef struct { + __IO uint32_t STARTF; + __IO uint32_t SLADDR0F; + __IO uint32_t SLADDR1F; + __IO uint32_t TENDF; + __IO uint32_t STOPF; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLF; + __IO uint32_t TEMPTYF; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOF; + __IO uint32_t ACKRF; + uint32_t RESERVED2[1]; + __IO uint32_t NACKF; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTF; + uint32_t RESERVED4[1]; + __IO uint32_t MSL; + __IO uint32_t BUSY; + __IO uint32_t TRA; + uint32_t RESERVED5[1]; + __IO uint32_t GENCALLF; + __IO uint32_t SMBDEFAULTF; + __IO uint32_t SMBHOSTF; + __IO uint32_t SMBALRTF; + __IO uint32_t TFEMPTY; + __IO uint32_t TFFULL; + __IO uint32_t RFEMPTY; + __IO uint32_t RFFULL; + uint32_t RESERVED6[3]; + __IO uint32_t RFREQ; +} stc_i2c_sr_bit_t; + +typedef struct { + __O uint32_t STARTFCLR; + __O uint32_t SLADDR0FCLR; + __O uint32_t SLADDR1FCLR; + __O uint32_t TENDFCLR; + __O uint32_t STOPFCLR; + uint32_t RESERVED0[1]; + __O uint32_t RFULLFCLR; + __O uint32_t TEMPTYFCLR; + uint32_t RESERVED1[1]; + __O uint32_t ARLOFCLR; + __O uint32_t RFREQCLR; + uint32_t RESERVED2[1]; + __O uint32_t NACKFCLR; + uint32_t RESERVED3[1]; + __O uint32_t TMOUTFCLR; + uint32_t RESERVED4[5]; + __O uint32_t GENCALLFCLR; + __O uint32_t SMBDEFAULTFCLR; + __O uint32_t SMBHOSTFCLR; + __O uint32_t SMBALRTFCLR; + uint32_t RESERVED5[8]; +} stc_i2c_clr_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t DNFEN; + __IO uint32_t ANFEN; + uint32_t RESERVED1[26]; +} stc_i2c_fltr_bit_t; + +typedef struct { + __IO uint32_t FEN; + __IO uint32_t TFFLUSH; + __IO uint32_t RFFLUSH; + __IO uint32_t NACKTFFLUSH; + uint32_t RESERVED0[28]; +} stc_i2c_fstr_bit_t; + +typedef struct { + __I uint32_t SWDTAUTS; + __I uint32_t SWDTITS; + uint32_t RESERVED0[10]; + __I uint32_t SWDTSLPOFF; + uint32_t RESERVED1[3]; + __I uint32_t WDTAUTS; + __I uint32_t WDTITS; + uint32_t RESERVED2[10]; + __I uint32_t WDTSLPOFF; + uint32_t RESERVED3[3]; +} stc_icg_icg0_bit_t; + +typedef struct { + __I uint32_t HRCFREQSEL; + uint32_t RESERVED0[7]; + __I uint32_t HRCSTOP; + uint32_t RESERVED1[9]; + __I uint32_t BORDIS; + uint32_t RESERVED2[13]; +} stc_icg_icg1_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SWDTEN; + __IO uint32_t PVD1EN; + __IO uint32_t PVD2EN; + uint32_t RESERVED1[1]; + __IO uint32_t XTALSTPEN; + uint32_t RESERVED2[2]; + __IO uint32_t RPARERREN; + __IO uint32_t RECCERREN; + __IO uint32_t BUSERREN; + __IO uint32_t WDTEN; + uint32_t RESERVED3[20]; +} stc_intc_nmier_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SWDTF; + __IO uint32_t PVD1F; + __IO uint32_t PVD2F; + uint32_t RESERVED1[1]; + __IO uint32_t XTALSTPF; + uint32_t RESERVED2[2]; + __IO uint32_t RPARERRF; + __IO uint32_t RECCERRF; + __IO uint32_t BUSERRF; + __IO uint32_t WDTF; + uint32_t RESERVED3[20]; +} stc_intc_nmifr_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SWDTFCLR; + __IO uint32_t PVD1FCLR; + __IO uint32_t PVD2FCLR; + uint32_t RESERVED1[1]; + __IO uint32_t XTALSTPFCLR; + uint32_t RESERVED2[2]; + __IO uint32_t RPARERRFCLR; + __IO uint32_t RECCERRFCLR; + __IO uint32_t BUSERRFCLR; + __IO uint32_t WDTFCLR; + uint32_t RESERVED3[20]; +} stc_intc_nmifcr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t EFEN; + uint32_t RESERVED1[7]; + __IO uint32_t NOCEN; + uint32_t RESERVED2[16]; +} stc_intc_eirqcr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t SWDTWKEN; + uint32_t RESERVED1[2]; + __IO uint32_t CMP1WKEN; + __IO uint32_t WKTMWKEN; + __IO uint32_t RTCALMWKEN; + __IO uint32_t RTCPRDWKEN; + __IO uint32_t TMR0CMPWKEN; + uint32_t RESERVED2[2]; + __IO uint32_t RXWKEN; + uint32_t RESERVED3[2]; + __IO uint32_t CMP2WKEN; + __IO uint32_t CMP3WKEN; + __IO uint32_t CMP4WKEN; +} stc_intc_wken_bit_t; + +typedef struct { + __IO uint32_t EIF0; + __IO uint32_t EIF1; + __IO uint32_t EIF2; + __IO uint32_t EIF3; + __IO uint32_t EIF4; + __IO uint32_t EIF5; + __IO uint32_t EIF6; + __IO uint32_t EIF7; + __IO uint32_t EIF8; + __IO uint32_t EIF9; + __IO uint32_t EIF10; + __IO uint32_t EIF11; + __IO uint32_t EIF12; + __IO uint32_t EIF13; + __IO uint32_t EIF14; + __IO uint32_t EIF15; + uint32_t RESERVED0[16]; +} stc_intc_eifr_bit_t; + +typedef struct { + __IO uint32_t EIFCLR0; + __IO uint32_t EIFCLR1; + __IO uint32_t EIFCLR2; + __IO uint32_t EIFCLR3; + __IO uint32_t EIFCLR4; + __IO uint32_t EIFCLR5; + __IO uint32_t EIFCLR6; + __IO uint32_t EIFCLR7; + __IO uint32_t EIFCLR8; + __IO uint32_t EIFCLR9; + __IO uint32_t EIFCLR10; + __IO uint32_t EIFCLR11; + __IO uint32_t EIFCLR12; + __IO uint32_t EIFCLR13; + __IO uint32_t EIFCLR14; + __IO uint32_t EIFCLR15; + uint32_t RESERVED0[16]; +} stc_intc_eifcr_bit_t; + +typedef struct { + __IO uint32_t SWIE0; + __IO uint32_t SWIE1; + __IO uint32_t SWIE2; + __IO uint32_t SWIE3; + __IO uint32_t SWIE4; + __IO uint32_t SWIE5; + __IO uint32_t SWIE6; + __IO uint32_t SWIE7; + __IO uint32_t SWIE8; + __IO uint32_t SWIE9; + __IO uint32_t SWIE10; + __IO uint32_t SWIE11; + __IO uint32_t SWIE12; + __IO uint32_t SWIE13; + __IO uint32_t SWIE14; + __IO uint32_t SWIE15; + __IO uint32_t SWIE16; + __IO uint32_t SWIE17; + __IO uint32_t SWIE18; + __IO uint32_t SWIE19; + __IO uint32_t SWIE20; + __IO uint32_t SWIE21; + __IO uint32_t SWIE22; + __IO uint32_t SWIE23; + __IO uint32_t SWIE24; + __IO uint32_t SWIE25; + __IO uint32_t SWIE26; + __IO uint32_t SWIE27; + __IO uint32_t SWIE28; + __IO uint32_t SWIE29; + __IO uint32_t SWIE30; + __IO uint32_t SWIE31; +} stc_intc_swier_bit_t; + +typedef struct { + __IO uint32_t EVTE0; + __IO uint32_t EVTE1; + __IO uint32_t EVTE2; + __IO uint32_t EVTE3; + __IO uint32_t EVTE4; + __IO uint32_t EVTE5; + __IO uint32_t EVTE6; + __IO uint32_t EVTE7; + __IO uint32_t EVTE8; + __IO uint32_t EVTE9; + __IO uint32_t EVTE10; + __IO uint32_t EVTE11; + __IO uint32_t EVTE12; + __IO uint32_t EVTE13; + __IO uint32_t EVTE14; + __IO uint32_t EVTE15; + __IO uint32_t EVTE16; + __IO uint32_t EVTE17; + __IO uint32_t EVTE18; + __IO uint32_t EVTE19; + __IO uint32_t EVTE20; + __IO uint32_t EVTE21; + __IO uint32_t EVTE22; + __IO uint32_t EVTE23; + __IO uint32_t EVTE24; + __IO uint32_t EVTE25; + __IO uint32_t EVTE26; + __IO uint32_t EVTE27; + __IO uint32_t EVTE28; + __IO uint32_t EVTE29; + __IO uint32_t EVTE30; + __IO uint32_t EVTE31; +} stc_intc_evter_bit_t; + +typedef struct { + __IO uint32_t IEN0; + __IO uint32_t IEN1; + __IO uint32_t IEN2; + __IO uint32_t IEN3; + __IO uint32_t IEN4; + __IO uint32_t IEN5; + __IO uint32_t IEN6; + __IO uint32_t IEN7; + __IO uint32_t IEN8; + __IO uint32_t IEN9; + __IO uint32_t IEN10; + __IO uint32_t IEN11; + __IO uint32_t IEN12; + __IO uint32_t IEN13; + __IO uint32_t IEN14; + __IO uint32_t IEN15; + __IO uint32_t IEN16; + __IO uint32_t IEN17; + __IO uint32_t IEN18; + __IO uint32_t IEN19; + __IO uint32_t IEN20; + __IO uint32_t IEN21; + __IO uint32_t IEN22; + __IO uint32_t IEN23; + __IO uint32_t IEN24; + __IO uint32_t IEN25; + __IO uint32_t IEN26; + __IO uint32_t IEN27; + __IO uint32_t IEN28; + __IO uint32_t IEN29; + __IO uint32_t IEN30; + __IO uint32_t IEN31; +} stc_intc_ier_bit_t; + +typedef struct { + __IO uint32_t SEN; + uint32_t RESERVED0[31]; +} stc_keyscan_ser_bit_t; + +typedef struct { + uint32_t RESERVED0[23]; + __IO uint32_t TDC; + uint32_t RESERVED1[8]; +} stc_mcan_dbtp_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t LBCK; + uint32_t RESERVED1[2]; + __I uint32_t RX; + uint32_t RESERVED2[5]; + __I uint32_t PVAL; + uint32_t RESERVED3[7]; + __I uint32_t SVAL; + uint32_t RESERVED4[10]; +} stc_mcan_test_bit_t; + +typedef struct { + __IO uint32_t INIT; + __IO uint32_t CCE; + __IO uint32_t ASM; + __I uint32_t CSA; + __IO uint32_t CSR; + __IO uint32_t MON; + __IO uint32_t DAR; + __IO uint32_t TEST; + __IO uint32_t FDOE; + __IO uint32_t BRSE; + __IO uint32_t UTSU; + __IO uint32_t WMM; + __IO uint32_t PXHD; + __IO uint32_t EFBI; + __IO uint32_t TXP; + __IO uint32_t NISO; + uint32_t RESERVED0[16]; +} stc_mcan_cccr_bit_t; + +typedef struct { + __IO uint32_t ETOC; + uint32_t RESERVED0[31]; +} stc_mcan_tocc_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t RP; + uint32_t RESERVED1[16]; +} stc_mcan_ecr_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __I uint32_t EP; + __I uint32_t EW; + __I uint32_t BO; + uint32_t RESERVED1[3]; + __I uint32_t RESI; + __I uint32_t RBRS; + __I uint32_t RFDF; + __I uint32_t PXE; + uint32_t RESERVED2[17]; +} stc_mcan_psr_bit_t; + +typedef struct { + __IO uint32_t RF0N; + __IO uint32_t RF0W; + __IO uint32_t RF0F; + __IO uint32_t RF0L; + __IO uint32_t RF1N; + __IO uint32_t RF1W; + __IO uint32_t RF1F; + __IO uint32_t RF1L; + __IO uint32_t HPM; + __IO uint32_t TC; + __IO uint32_t TCF; + __IO uint32_t TFE; + __IO uint32_t TEFN; + __IO uint32_t TEFW; + __IO uint32_t TEFF; + __IO uint32_t TEFL; + __IO uint32_t TSW; + __IO uint32_t MRAF; + __IO uint32_t TOO; + __IO uint32_t DRX; + __IO uint32_t BEC; + __IO uint32_t BEU; + __IO uint32_t ELO; + __IO uint32_t EP; + __IO uint32_t EW; + __IO uint32_t BO; + __IO uint32_t WDI; + __IO uint32_t PEA; + __IO uint32_t PED; + __IO uint32_t ARA; + uint32_t RESERVED0[2]; +} stc_mcan_ir_bit_t; + +typedef struct { + __IO uint32_t RF0NE; + __IO uint32_t RF0WE; + __IO uint32_t RF0FE; + __IO uint32_t RF0LE; + __IO uint32_t RF1NE; + __IO uint32_t RF1WE; + __IO uint32_t RF1FE; + __IO uint32_t RF1LE; + __IO uint32_t HPME; + __IO uint32_t TCE; + __IO uint32_t TCFE; + __IO uint32_t TFEE; + __IO uint32_t TEFNE; + __IO uint32_t TEFWE; + __IO uint32_t TEFFE; + __IO uint32_t TEFLE; + __IO uint32_t TSWE; + __IO uint32_t MRAFE; + __IO uint32_t TOOE; + __IO uint32_t DRXE; + __IO uint32_t BECE; + __IO uint32_t BEUE; + __IO uint32_t ELOE; + __IO uint32_t EPE; + __IO uint32_t EWE; + __IO uint32_t BOE; + __IO uint32_t WDIE; + __IO uint32_t PEAE; + __IO uint32_t PEDE; + __IO uint32_t ARAE; + uint32_t RESERVED0[2]; +} stc_mcan_ie_bit_t; + +typedef struct { + __IO uint32_t RF0NL; + __IO uint32_t RF0WL; + __IO uint32_t RF0FL; + __IO uint32_t RF0LL; + __IO uint32_t RF1NL; + __IO uint32_t RF1WL; + __IO uint32_t RF1FL; + __IO uint32_t RF1LL; + __IO uint32_t HPML; + __IO uint32_t TCL; + __IO uint32_t TCFL; + __IO uint32_t TFEL; + __IO uint32_t TEFNL; + __IO uint32_t TEFWL; + __IO uint32_t TEFFL; + __IO uint32_t TEFLL; + __IO uint32_t TSWL; + __IO uint32_t MRAFL; + __IO uint32_t TOOL; + __IO uint32_t DRXL; + __IO uint32_t BECL; + __IO uint32_t BEUL; + __IO uint32_t ELOL; + __IO uint32_t EPL; + __IO uint32_t EWL; + __IO uint32_t BOL; + __IO uint32_t WDIL; + __IO uint32_t PEAL; + __IO uint32_t PEDL; + __IO uint32_t ARAL; + uint32_t RESERVED0[2]; +} stc_mcan_ils_bit_t; + +typedef struct { + __IO uint32_t EINT0; + __IO uint32_t EINT1; + uint32_t RESERVED0[30]; +} stc_mcan_ile_bit_t; + +typedef struct { + __IO uint32_t RRFE; + __IO uint32_t RRFS; + uint32_t RESERVED0[30]; +} stc_mcan_gfc_bit_t; + +typedef struct { + uint32_t RESERVED0[15]; + __I uint32_t FLST; + uint32_t RESERVED1[16]; +} stc_mcan_hpms_bit_t; + +typedef struct { + __IO uint32_t ND0; + __IO uint32_t ND1; + __IO uint32_t ND2; + __IO uint32_t ND3; + __IO uint32_t ND4; + __IO uint32_t ND5; + __IO uint32_t ND6; + __IO uint32_t ND7; + __IO uint32_t ND8; + __IO uint32_t ND9; + __IO uint32_t ND10; + __IO uint32_t ND11; + __IO uint32_t ND12; + __IO uint32_t ND13; + __IO uint32_t ND14; + __IO uint32_t ND15; + __IO uint32_t ND16; + __IO uint32_t ND17; + __IO uint32_t ND18; + __IO uint32_t ND19; + __IO uint32_t ND20; + __IO uint32_t ND21; + __IO uint32_t ND22; + __IO uint32_t ND23; + __IO uint32_t ND24; + __IO uint32_t ND25; + __IO uint32_t ND26; + __IO uint32_t ND27; + __IO uint32_t ND28; + __IO uint32_t ND29; + __IO uint32_t ND30; + __IO uint32_t ND31; +} stc_mcan_ndat1_bit_t; + +typedef struct { + __IO uint32_t ND32; + __IO uint32_t ND33; + __IO uint32_t ND34; + __IO uint32_t ND35; + __IO uint32_t ND36; + __IO uint32_t ND37; + __IO uint32_t ND38; + __IO uint32_t ND39; + __IO uint32_t ND40; + __IO uint32_t ND41; + __IO uint32_t ND42; + __IO uint32_t ND43; + __IO uint32_t ND44; + __IO uint32_t ND45; + __IO uint32_t ND46; + __IO uint32_t ND47; + __IO uint32_t ND48; + __IO uint32_t ND49; + __IO uint32_t ND50; + __IO uint32_t ND51; + __IO uint32_t ND52; + __IO uint32_t ND53; + __IO uint32_t ND54; + __IO uint32_t ND55; + __IO uint32_t ND56; + __IO uint32_t ND57; + __IO uint32_t ND58; + __IO uint32_t ND59; + __IO uint32_t ND60; + __IO uint32_t ND61; + __IO uint32_t ND62; + __IO uint32_t ND63; +} stc_mcan_ndat2_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t F0OM; +} stc_mcan_rxf0c_bit_t; + +typedef struct { + uint32_t RESERVED0[24]; + __I uint32_t F0F; + __I uint32_t RF0L; + uint32_t RESERVED1[6]; +} stc_mcan_rxf0s_bit_t; + +typedef struct { + uint32_t RESERVED0[31]; + __IO uint32_t F1OM; +} stc_mcan_rxf1c_bit_t; + +typedef struct { + uint32_t RESERVED0[24]; + __I uint32_t F1F; + __I uint32_t RF1L; + uint32_t RESERVED1[6]; +} stc_mcan_rxf1s_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t TFQM; + uint32_t RESERVED1[1]; +} stc_mcan_txbc_bit_t; + +typedef struct { + uint32_t RESERVED0[21]; + __I uint32_t TFQF; + uint32_t RESERVED1[10]; +} stc_mcan_txfqs_bit_t; + +typedef struct { + __I uint32_t TRP0; + __I uint32_t TRP1; + __I uint32_t TRP2; + __I uint32_t TRP3; + __I uint32_t TRP4; + __I uint32_t TRP5; + __I uint32_t TRP6; + __I uint32_t TRP7; + __I uint32_t TRP8; + __I uint32_t TRP9; + __I uint32_t TRP10; + __I uint32_t TRP11; + __I uint32_t TRP12; + __I uint32_t TRP13; + __I uint32_t TRP14; + __I uint32_t TRP15; + __I uint32_t TRP16; + __I uint32_t TRP17; + __I uint32_t TRP18; + __I uint32_t TRP19; + __I uint32_t TRP20; + __I uint32_t TRP21; + __I uint32_t TRP22; + __I uint32_t TRP23; + __I uint32_t TRP24; + __I uint32_t TRP25; + __I uint32_t TRP26; + __I uint32_t TRP27; + __I uint32_t TRP28; + __I uint32_t TRP29; + __I uint32_t TRP30; + __I uint32_t TRP31; +} stc_mcan_txbrp_bit_t; + +typedef struct { + __IO uint32_t AR0; + __IO uint32_t AR1; + __IO uint32_t AR2; + __IO uint32_t AR3; + __IO uint32_t AR4; + __IO uint32_t AR5; + __IO uint32_t AR6; + __IO uint32_t AR7; + __IO uint32_t AR8; + __IO uint32_t AR9; + __IO uint32_t AR10; + __IO uint32_t AR11; + __IO uint32_t AR12; + __IO uint32_t AR13; + __IO uint32_t AR14; + __IO uint32_t AR15; + __IO uint32_t AR16; + __IO uint32_t AR17; + __IO uint32_t AR18; + __IO uint32_t AR19; + __IO uint32_t AR20; + __IO uint32_t AR21; + __IO uint32_t AR22; + __IO uint32_t AR23; + __IO uint32_t AR24; + __IO uint32_t AR25; + __IO uint32_t AR26; + __IO uint32_t AR27; + __IO uint32_t AR28; + __IO uint32_t AR29; + __IO uint32_t AR30; + __IO uint32_t AR31; +} stc_mcan_txbar_bit_t; + +typedef struct { + __IO uint32_t CR0; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t CR5; + __IO uint32_t CR6; + __IO uint32_t CR7; + __IO uint32_t CR8; + __IO uint32_t CR9; + __IO uint32_t CR10; + __IO uint32_t CR11; + __IO uint32_t CR12; + __IO uint32_t CR13; + __IO uint32_t CR14; + __IO uint32_t CR15; + __IO uint32_t CR16; + __IO uint32_t CR17; + __IO uint32_t CR18; + __IO uint32_t CR19; + __IO uint32_t CR20; + __IO uint32_t CR21; + __IO uint32_t CR22; + __IO uint32_t CR23; + __IO uint32_t CR24; + __IO uint32_t CR25; + __IO uint32_t CR26; + __IO uint32_t CR27; + __IO uint32_t CR28; + __IO uint32_t CR29; + __IO uint32_t CR30; + __IO uint32_t CR31; +} stc_mcan_txbcr_bit_t; + +typedef struct { + __I uint32_t TO0; + __I uint32_t TO1; + __I uint32_t TO2; + __I uint32_t TO3; + __I uint32_t TO4; + __I uint32_t TO5; + __I uint32_t TO6; + __I uint32_t TO7; + __I uint32_t TO8; + __I uint32_t TO9; + __I uint32_t TO10; + __I uint32_t TO11; + __I uint32_t TO12; + __I uint32_t TO13; + __I uint32_t TO14; + __I uint32_t TO15; + __I uint32_t TO16; + __I uint32_t TO17; + __I uint32_t TO18; + __I uint32_t TO19; + __I uint32_t TO20; + __I uint32_t TO21; + __I uint32_t TO22; + __I uint32_t TO23; + __I uint32_t TO24; + __I uint32_t TO25; + __I uint32_t TO26; + __I uint32_t TO27; + __I uint32_t TO28; + __I uint32_t TO29; + __I uint32_t TO30; + __I uint32_t TO31; +} stc_mcan_txbto_bit_t; + +typedef struct { + __I uint32_t CF0; + __I uint32_t CF1; + __I uint32_t CF2; + __I uint32_t CF3; + __I uint32_t CF4; + __I uint32_t CF5; + __I uint32_t CF6; + __I uint32_t CF7; + __I uint32_t CF8; + __I uint32_t CF9; + __I uint32_t CF10; + __I uint32_t CF11; + __I uint32_t CF12; + __I uint32_t CF13; + __I uint32_t CF14; + __I uint32_t CF15; + __I uint32_t CF16; + __I uint32_t CF17; + __I uint32_t CF18; + __I uint32_t CF19; + __I uint32_t CF20; + __I uint32_t CF21; + __I uint32_t CF22; + __I uint32_t CF23; + __I uint32_t CF24; + __I uint32_t CF25; + __I uint32_t CF26; + __I uint32_t CF27; + __I uint32_t CF28; + __I uint32_t CF29; + __I uint32_t CF30; + __I uint32_t CF31; +} stc_mcan_txbcf_bit_t; + +typedef struct { + __IO uint32_t TIE0; + __IO uint32_t TIE1; + __IO uint32_t TIE2; + __IO uint32_t TIE3; + __IO uint32_t TIE4; + __IO uint32_t TIE5; + __IO uint32_t TIE6; + __IO uint32_t TIE7; + __IO uint32_t TIE8; + __IO uint32_t TIE9; + __IO uint32_t TIE10; + __IO uint32_t TIE11; + __IO uint32_t TIE12; + __IO uint32_t TIE13; + __IO uint32_t TIE14; + __IO uint32_t TIE15; + __IO uint32_t TIE16; + __IO uint32_t TIE17; + __IO uint32_t TIE18; + __IO uint32_t TIE19; + __IO uint32_t TIE20; + __IO uint32_t TIE21; + __IO uint32_t TIE22; + __IO uint32_t TIE23; + __IO uint32_t TIE24; + __IO uint32_t TIE25; + __IO uint32_t TIE26; + __IO uint32_t TIE27; + __IO uint32_t TIE28; + __IO uint32_t TIE29; + __IO uint32_t TIE30; + __IO uint32_t TIE31; +} stc_mcan_txbtie_bit_t; + +typedef struct { + __IO uint32_t CFIE0; + __IO uint32_t CFIE1; + __IO uint32_t CFIE2; + __IO uint32_t CFIE3; + __IO uint32_t CFIE4; + __IO uint32_t CFIE5; + __IO uint32_t CFIE6; + __IO uint32_t CFIE7; + __IO uint32_t CFIE8; + __IO uint32_t CFIE9; + __IO uint32_t CFIE10; + __IO uint32_t CFIE11; + __IO uint32_t CFIE12; + __IO uint32_t CFIE13; + __IO uint32_t CFIE14; + __IO uint32_t CFIE15; + __IO uint32_t CFIE16; + __IO uint32_t CFIE17; + __IO uint32_t CFIE18; + __IO uint32_t CFIE19; + __IO uint32_t CFIE20; + __IO uint32_t CFIE21; + __IO uint32_t CFIE22; + __IO uint32_t CFIE23; + __IO uint32_t CFIE24; + __IO uint32_t CFIE25; + __IO uint32_t CFIE26; + __IO uint32_t CFIE27; + __IO uint32_t CFIE28; + __IO uint32_t CFIE29; + __IO uint32_t CFIE30; + __IO uint32_t CFIE31; +} stc_mcan_txbcie_bit_t; + +typedef struct { + uint32_t RESERVED0[24]; + __I uint32_t EFF; + __I uint32_t TEFL; + uint32_t RESERVED1[6]; +} stc_mcan_txefs_bit_t; + +typedef struct { + __I uint32_t SMPU1EAF; + __I uint32_t SMPU2EAF; + __I uint32_t PSPEF; + __I uint32_t MSPEF; + uint32_t RESERVED0[28]; +} stc_mpu_sr_bit_t; + +typedef struct { + __O uint32_t SMPU1ECLR; + __O uint32_t SMPU2ECLR; + __O uint32_t PSPECLR; + __O uint32_t MSPECLR; + uint32_t RESERVED0[28]; +} stc_mpu_eclr_bit_t; + +typedef struct { + __IO uint32_t MPUWE; + uint32_t RESERVED0[31]; +} stc_mpu_wp_bit_t; + +typedef struct { + __IO uint32_t AESRDP; + __IO uint32_t AESWRP; + __IO uint32_t HASHRDP; + __IO uint32_t HASHWRP; + __IO uint32_t TRNGRDP; + __IO uint32_t TRNGWRP; + __IO uint32_t CRCRDP; + __IO uint32_t CRCWRP; + __IO uint32_t EFMRDP; + __IO uint32_t EFMWRP; + uint32_t RESERVED0[2]; + __IO uint32_t WDTRDP; + __IO uint32_t WDTWRP; + __IO uint32_t SWDTRDP; + __IO uint32_t SWDTWRP; + __IO uint32_t BKSRAMRDP; + __IO uint32_t BKSRAMWRP; + __IO uint32_t RTCRDP; + __IO uint32_t RTCWRP; + __IO uint32_t DMPURDP; + __IO uint32_t DMPUWRP; + __IO uint32_t SRAMCRDP; + __IO uint32_t SRAMCWRP; + __IO uint32_t INTCRDP; + __IO uint32_t INTCWRP; + __IO uint32_t SYSCRDP; + __IO uint32_t SYSCWRP; + __IO uint32_t MSTPRDP; + __IO uint32_t MSPTWRP; + uint32_t RESERVED1[1]; + __IO uint32_t BUSERRE; +} stc_mpu_ippr_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t MSPPACT; + __IO uint32_t MSPPE; +} stc_mpu_msppctl_bit_t; + +typedef struct { + uint32_t RESERVED0[30]; + __IO uint32_t PSPPACT; + __IO uint32_t PSPPE; +} stc_mpu_psppctl_bit_t; + +typedef struct { + __IO uint32_t RG0E; + __IO uint32_t RG1E; + __IO uint32_t RG2E; + __IO uint32_t RG3E; + __IO uint32_t RG4E; + __IO uint32_t RG5E; + __IO uint32_t RG6E; + __IO uint32_t RG7E; + __IO uint32_t RG8E; + __IO uint32_t RG9E; + __IO uint32_t RG10E; + __IO uint32_t RG11E; + __IO uint32_t RG12E; + __IO uint32_t RG13E; + __IO uint32_t RG14E; + __IO uint32_t RG15E; + uint32_t RESERVED0[16]; +} stc_mpu_srge_bit_t; + +typedef struct { + __IO uint32_t RG0WP; + __IO uint32_t RG1WP; + __IO uint32_t RG2WP; + __IO uint32_t RG3WP; + __IO uint32_t RG4WP; + __IO uint32_t RG5WP; + __IO uint32_t RG6WP; + __IO uint32_t RG7WP; + __IO uint32_t RG8WP; + __IO uint32_t RG9WP; + __IO uint32_t RG10WP; + __IO uint32_t RG11WP; + __IO uint32_t RG12WP; + __IO uint32_t RG13WP; + __IO uint32_t RG14WP; + __IO uint32_t RG15WP; + uint32_t RESERVED0[16]; +} stc_mpu_srgwp_bit_t; + +typedef struct { + __IO uint32_t RG0RP; + __IO uint32_t RG1RP; + __IO uint32_t RG2RP; + __IO uint32_t RG3RP; + __IO uint32_t RG4RP; + __IO uint32_t RG5RP; + __IO uint32_t RG6RP; + __IO uint32_t RG7RP; + __IO uint32_t RG8RP; + __IO uint32_t RG9RP; + __IO uint32_t RG10RP; + __IO uint32_t RG11RP; + __IO uint32_t RG12RP; + __IO uint32_t RG13RP; + __IO uint32_t RG14RP; + __IO uint32_t RG15RP; + uint32_t RESERVED0[16]; +} stc_mpu_srgrp_bit_t; + +typedef struct { + __IO uint32_t SMPUBRP; + __IO uint32_t SMPUBWP; + uint32_t RESERVED0[5]; + __IO uint32_t SMPUE; + uint32_t RESERVED1[24]; +} stc_mpu_scr_bit_t; + +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t SMCEN; + uint32_t RESERVED1[30]; +} stc_peric_smc_enar_bit_t; + +typedef struct { + __IO uint32_t TMR0U1A; + __IO uint32_t TMR0U1B; + __IO uint32_t TMR0U2A; + __IO uint32_t TMR0U2B; + __IO uint32_t TMR4U1; + __IO uint32_t TMR4U2; + __IO uint32_t TMR4U3; + uint32_t RESERVED0[1]; + __IO uint32_t TMR6U1; + __IO uint32_t TMR6U2; + __IO uint32_t TMRAU1; + __IO uint32_t TMRAU2; + __IO uint32_t TMRAU3; + __IO uint32_t TMRAU4; + __IO uint32_t TMRAU5; + uint32_t RESERVED1[17]; +} stc_peric_tmr_synenr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t USART1_NFE; + uint32_t RESERVED1[29]; +} stc_peric_usart1_nfc_bit_t; + +typedef struct { + __IO uint32_t SRAMH; + uint32_t RESERVED0[3]; + __IO uint32_t SRAM0; + uint32_t RESERVED1[5]; + __IO uint32_t SRAMB; + uint32_t RESERVED2[2]; + __IO uint32_t KEY; + __IO uint32_t DMA1; + __IO uint32_t DMA2; + __IO uint32_t FCM; + __IO uint32_t AOS; + __IO uint32_t CTC; + uint32_t RESERVED3[1]; + __IO uint32_t AES; + __IO uint32_t HASH; + __IO uint32_t TRNG; + __IO uint32_t CRC; + __IO uint32_t DCU1; + __IO uint32_t DCU2; + __IO uint32_t DCU3; + __IO uint32_t DCU4; + uint32_t RESERVED4[4]; +} stc_pwc_fcg0_bit_t; + +typedef struct { + __IO uint32_t MCAN1; + __IO uint32_t MCAN2; + uint32_t RESERVED0[1]; + __IO uint32_t QSPI; + __IO uint32_t I2C1; + __IO uint32_t I2C2; + uint32_t RESERVED1[10]; + __IO uint32_t SPI1; + __IO uint32_t SPI2; + __IO uint32_t SPI3; + uint32_t RESERVED2[13]; +} stc_pwc_fcg1_bit_t; + +typedef struct { + __IO uint32_t TMR6_1; + __IO uint32_t TMR6_2; + uint32_t RESERVED0[7]; + __IO uint32_t TMR4_1; + __IO uint32_t TMR4_2; + __IO uint32_t TMR4_3; + __IO uint32_t TMR0_1; + __IO uint32_t TMR0_2; + uint32_t RESERVED1[1]; + __IO uint32_t EMB; + uint32_t RESERVED2[4]; + __IO uint32_t TMRA_1; + __IO uint32_t TMRA_2; + __IO uint32_t TMRA_3; + __IO uint32_t TMRA_4; + __IO uint32_t TMRA_5; + uint32_t RESERVED3[7]; +} stc_pwc_fcg2_bit_t; + +typedef struct { + __IO uint32_t ADC1; + __IO uint32_t ADC2; + __IO uint32_t ADC3; + uint32_t RESERVED0[1]; + __IO uint32_t DAC; + uint32_t RESERVED1[3]; + __IO uint32_t CMP12; + __IO uint32_t CMP34; + uint32_t RESERVED2[6]; + __IO uint32_t SMC; + uint32_t RESERVED3[3]; + __IO uint32_t USART1; + __IO uint32_t USART2; + __IO uint32_t USART3; + __IO uint32_t USART4; + __IO uint32_t USART5; + __IO uint32_t USART6; + uint32_t RESERVED4[6]; +} stc_pwc_fcg3_bit_t; + +typedef struct { + __IO uint32_t PRT0; + uint32_t RESERVED0[31]; +} stc_pwc_fcg0pc_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t WKOVF; + uint32_t RESERVED1[2]; + __IO uint32_t WKTCE; +} stc_pwc_wktcr_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t PWDN; +} stc_pwc_pwrc0_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t VHRCSD; + __IO uint32_t PDTS; + uint32_t RESERVED1[4]; +} stc_pwc_pwrc1_bit_t; + +typedef struct { + uint32_t RESERVED0[7]; + __IO uint32_t ADBUFE; +} stc_pwc_pwrc4_bit_t; + +typedef struct { + __IO uint32_t EXVCCINEN; + uint32_t RESERVED0[4]; + __IO uint32_t PVD1EN; + __IO uint32_t PVD2EN; + uint32_t RESERVED1[1]; +} stc_pwc_pvdcr0_bit_t; + +typedef struct { + __IO uint32_t PVD1IRE; + __IO uint32_t PVD1IRS; + __IO uint32_t PVD1CMPOE; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2IRE; + __IO uint32_t PVD2IRS; + __IO uint32_t PVD2CMPOE; + uint32_t RESERVED1[1]; +} stc_pwc_pvdcr1_bit_t; + +typedef struct { + __IO uint32_t PVD1NFDIS; + uint32_t RESERVED0[3]; + __IO uint32_t PVD2NFDIS; + uint32_t RESERVED1[3]; +} stc_pwc_pvdfcr_bit_t; + +typedef struct { + __IO uint32_t WKE00; + __IO uint32_t WKE01; + __IO uint32_t WKE02; + __IO uint32_t WKE03; + __IO uint32_t WKE10; + __IO uint32_t WKE11; + __IO uint32_t WKE12; + __IO uint32_t WKE13; +} stc_pwc_pdwke0_bit_t; + +typedef struct { + __IO uint32_t WKE20; + __IO uint32_t WKE21; + __IO uint32_t WKE22; + __IO uint32_t WKE23; + __IO uint32_t WKE30; + __IO uint32_t WKE31; + __IO uint32_t WKE32; + __IO uint32_t WKE33; +} stc_pwc_pdwke1_bit_t; + +typedef struct { + __IO uint32_t VD1WKE; + __IO uint32_t VD2WKE; + uint32_t RESERVED0[2]; + __IO uint32_t RTCPRDWKE; + __IO uint32_t RTCALMWKE; + uint32_t RESERVED1[1]; + __IO uint32_t WKTMWKE; +} stc_pwc_pdwke2_bit_t; + +typedef struct { + __IO uint32_t WK0EGS; + __IO uint32_t WK1EGS; + __IO uint32_t WK2EGS; + __IO uint32_t WK3EGS; + __IO uint32_t VD1EGS; + __IO uint32_t VD2EGS; + uint32_t RESERVED0[2]; +} stc_pwc_pdwkes_bit_t; + +typedef struct { + __IO uint32_t PTWK0F; + __IO uint32_t PTWK1F; + __IO uint32_t PTWK2F; + __IO uint32_t PTWK3F; + __IO uint32_t VD1WKF; + __IO uint32_t VD2WKF; + uint32_t RESERVED0[2]; +} stc_pwc_pdwkf0_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t RXD0WKF; + __IO uint32_t RTCPRDWKF; + __IO uint32_t RTCALMWKF; + uint32_t RESERVED1[1]; + __IO uint32_t WKTMWKF; +} stc_pwc_pdwkf1_bit_t; + +typedef struct { + __IO uint32_t VVDRSD; + __IO uint32_t SRAMBSD; + uint32_t RESERVED0[5]; + __IO uint32_t CSDIS; +} stc_pwc_pwrc5_bit_t; + +typedef struct { + __IO uint32_t PVD1MON; + __IO uint32_t PVD1DETFLG; + uint32_t RESERVED0[2]; + __IO uint32_t PVD2MON; + __IO uint32_t PVD2DETFLG; + uint32_t RESERVED1[2]; +} stc_pwc_pvddsr_bit_t; + +typedef struct { + __IO uint32_t RAMPDC0; + uint32_t RESERVED0[9]; + __IO uint32_t RAMPDC10; + uint32_t RESERVED1[21]; +} stc_pwc_rampc0_bit_t; + +typedef struct { + __IO uint32_t PRAMPDC0; + uint32_t RESERVED0[1]; + __IO uint32_t PRAMPDC2; + uint32_t RESERVED1[29]; +} stc_pwc_pramlpc_bit_t; + +typedef struct { + __IO uint32_t FLNWT; + __IO uint32_t CKSMRC; + uint32_t RESERVED0[12]; + __IO uint32_t EXBUSOE; + __IO uint32_t STOP; +} stc_pwc_stpmcr_bit_t; + +typedef struct { + __IO uint32_t FPRCB0; + __IO uint32_t FPRCB1; + uint32_t RESERVED0[1]; + __IO uint32_t FPRCB3; + uint32_t RESERVED1[12]; +} stc_pwc_fprc_bit_t; + +typedef struct { + uint32_t RESERVED0[13]; + __IO uint32_t KEY; + __IO uint32_t DMA1; + __IO uint32_t DMA2; + __IO uint32_t FCM; + __IO uint32_t AOS; + __IO uint32_t CTC; + uint32_t RESERVED1[1]; + __IO uint32_t AES; + __IO uint32_t HASH; + __IO uint32_t TRNG; + __IO uint32_t CRC; + __IO uint32_t DCU1; + __IO uint32_t DCU2; + __IO uint32_t DCU3; + __IO uint32_t DCU4; + uint32_t RESERVED2[4]; +} stc_rmu_frst0_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t QSPI; + uint32_t RESERVED1[12]; + __IO uint32_t SPI1; + __IO uint32_t SPI2; + __IO uint32_t SPI3; + uint32_t RESERVED2[13]; +} stc_rmu_frst1_bit_t; + +typedef struct { + __IO uint32_t TMR6; + uint32_t RESERVED0[9]; + __IO uint32_t TMR4; + uint32_t RESERVED1[1]; + __IO uint32_t TMR0; + uint32_t RESERVED2[2]; + __IO uint32_t EMB; + uint32_t RESERVED3[4]; + __IO uint32_t TMRA; + uint32_t RESERVED4[11]; +} stc_rmu_frst2_bit_t; + +typedef struct { + __IO uint32_t ADC1; + __IO uint32_t ADC2; + __IO uint32_t ADC3; + uint32_t RESERVED0[1]; + __IO uint32_t DAC; + uint32_t RESERVED1[3]; + __IO uint32_t CMP12; + __IO uint32_t CMP34; + uint32_t RESERVED2[6]; + __IO uint32_t SMC; + uint32_t RESERVED3[3]; + __IO uint32_t USART1; + __IO uint32_t USART2; + __IO uint32_t USART3; + __IO uint32_t USART4; + __IO uint32_t USART5; + __IO uint32_t USART6; + uint32_t RESERVED4[6]; +} stc_rmu_frst3_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t LKUPREN; + uint32_t RESERVED1[2]; +} stc_rmu_prstcr0_bit_t; + +typedef struct { + __IO uint32_t PORF; + __IO uint32_t PINRF; + __IO uint32_t BORF; + __IO uint32_t PVD1RF; + __IO uint32_t PVD2RF; + __IO uint32_t WDRF; + __IO uint32_t SWDRF; + __IO uint32_t PDRF; + __IO uint32_t SWRF; + __IO uint32_t MPUERF; + __IO uint32_t RAPERF; + __IO uint32_t RAECRF; + __IO uint32_t CKFERF; + __IO uint32_t XTALERF; + __IO uint32_t LKUPRF; + uint32_t RESERVED0[15]; + __IO uint32_t MULTIRF; + __IO uint32_t CLRF; +} stc_rmu_rstf0_bit_t; + +typedef struct { + __IO uint32_t RESET; + uint32_t RESERVED0[7]; +} stc_rtc_cr0_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t AMPM; + uint32_t RESERVED1[1]; + __IO uint32_t ONEHZOE; + __IO uint32_t ONEHZSEL; + __IO uint32_t START; +} stc_rtc_cr1_bit_t; + +typedef struct { + __IO uint32_t RWREQ; + __IO uint32_t RWEN; + __IO uint32_t PRDF; + __IO uint32_t ALMF; + uint32_t RESERVED0[1]; + __IO uint32_t PRDIE; + __IO uint32_t ALMIE; + __IO uint32_t ALME; +} stc_rtc_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t LRCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RCKSEL; +} stc_rtc_cr3_bit_t; + +typedef struct { + __IO uint32_t COMP8; + uint32_t RESERVED0[6]; + __IO uint32_t COMPEN; +} stc_rtc_errcrh_bit_t; + +typedef struct { + __IO uint32_t SPIMDS; + __IO uint32_t TXMDS; + uint32_t RESERVED0[1]; + __IO uint32_t MSTR; + __IO uint32_t SPLPBK; + __IO uint32_t SPLPBK2; + __IO uint32_t SPE; + __IO uint32_t CSUSPE; + __IO uint32_t EIE; + __IO uint32_t TXIE; + __IO uint32_t RXIE; + __IO uint32_t IDIE; + __IO uint32_t MODFE; + __IO uint32_t PATE; + __IO uint32_t PAOE; + __IO uint32_t PAE; + uint32_t RESERVED1[16]; +} stc_spi_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[2]; + __IO uint32_t CTMDS; + uint32_t RESERVED1[3]; + __IO uint32_t SPRDTD; + uint32_t RESERVED2[1]; + __IO uint32_t SS0PV; + __IO uint32_t SS1PV; + __IO uint32_t SS2PV; + __IO uint32_t SS3PV; + uint32_t RESERVED3[20]; +} stc_spi_cfg1_bit_t; + +typedef struct { + __IO uint32_t OVRERF; + __I uint32_t IDLNF; + __IO uint32_t MODFERF; + __IO uint32_t PERF; + __IO uint32_t UDRERF; + __I uint32_t TDEF; + uint32_t RESERVED0[1]; + __I uint32_t RDFF; + uint32_t RESERVED1[24]; +} stc_spi_sr_bit_t; + +typedef struct { + __IO uint32_t CPHA; + __IO uint32_t CPOL; + uint32_t RESERVED0[10]; + __IO uint32_t LSBF; + __IO uint32_t MIDIE; + __IO uint32_t MSSDLE; + __IO uint32_t MSSIE; + uint32_t RESERVED1[16]; +} stc_spi_cfg2_bit_t; + +typedef struct { + __IO uint32_t WTPRC; + uint32_t RESERVED0[31]; +} stc_sramc_wtpr_bit_t; + +typedef struct { + __IO uint32_t PYOAD; + uint32_t RESERVED0[15]; + __IO uint32_t ECCOAD; + __IO uint32_t BECCOAD; + uint32_t RESERVED1[14]; +} stc_sramc_ckcr_bit_t; + +typedef struct { + __IO uint32_t CKPRC; + uint32_t RESERVED0[31]; +} stc_sramc_ckpr_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t SRAMH_PYERR; + __IO uint32_t SRAM0_1ERR; + __IO uint32_t SRAM0_2ERR; + __IO uint32_t SRAMB_1ERR; + __IO uint32_t SRAMB_2ERR; + __IO uint32_t CACHE_PYERR; + uint32_t RESERVED1[23]; +} stc_sramc_cksr_bit_t; + +typedef struct { + __IO uint32_t EIEN; + uint32_t RESERVED0[31]; +} stc_sramc_sram0_eien_bit_t; + +typedef struct { + __IO uint32_t EIEN; + uint32_t RESERVED0[31]; +} stc_sramc_sramb_eien_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t SLPOFF; + uint32_t RESERVED1[14]; + __IO uint32_t ITS; +} stc_swdt_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_swdt_sr_bit_t; + +typedef struct { + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + __IO uint32_t CMENA; + __IO uint32_t OVENA; + uint32_t RESERVED0[4]; + __IO uint32_t SYNSA; + __IO uint32_t SYNCLKA; + __IO uint32_t ASYNCLKA; + uint32_t RESERVED1[1]; + __IO uint32_t HSTAA; + __IO uint32_t HSTPA; + __IO uint32_t HCLEA; + __IO uint32_t HICPA; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + __IO uint32_t CMENB; + __IO uint32_t OVENB; + uint32_t RESERVED2[4]; + __IO uint32_t SYNSB; + __IO uint32_t SYNCLKB; + __IO uint32_t ASYNCLKB; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB; + __IO uint32_t HSTPB; + __IO uint32_t HCLEB; + __IO uint32_t HICPB; +} stc_tmr0_bconr_bit_t; + +typedef struct { + __IO uint32_t CMFA; + __IO uint32_t OVFA; + __IO uint32_t ICPA; + uint32_t RESERVED0[13]; + __IO uint32_t CMFB; + __IO uint32_t OVFB; + __IO uint32_t ICPB; + uint32_t RESERVED1[13]; +} stc_tmr0_stflr_bit_t; + +typedef struct { + __IO uint32_t OCEH; + __IO uint32_t OCEL; + __IO uint32_t OCPH; + __IO uint32_t OCPL; + __IO uint32_t OCIEH; + __IO uint32_t OCIEL; + __IO uint32_t OCFH; + __IO uint32_t OCFL; + uint32_t RESERVED0[8]; +} stc_tmr4_ocsr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t LMCH; + __IO uint32_t LMCL; + __IO uint32_t LMMH; + __IO uint32_t LMML; + __IO uint32_t MCECH; + __IO uint32_t MCECL; + uint32_t RESERVED1[2]; +} stc_tmr4_ocer_bit_t; + +typedef struct { + __IO uint32_t OCFDCH; + __IO uint32_t OCFPKH; + __IO uint32_t OCFUCH; + __IO uint32_t OCFZRH; + uint32_t RESERVED0[12]; +} stc_tmr4_ocmrh_bit_t; + +typedef struct { + __IO uint32_t OCFDCL; + __IO uint32_t OCFPKL; + __IO uint32_t OCFUCL; + __IO uint32_t OCFZRL; + uint32_t RESERVED0[28]; +} stc_tmr4_ocmrl_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t CLEAR; + __IO uint32_t MODE; + __IO uint32_t STOP; + __IO uint32_t BUFEN; + __IO uint32_t IRQPEN; + __IO uint32_t IRQPF; + __IO uint32_t IRQZEN; + __IO uint32_t IRQZF; + __IO uint32_t SYNST; + __IO uint32_t HST; + uint32_t RESERVED1[1]; + __IO uint32_t ECKEN; +} stc_tmr4_ccsr_bit_t; + +typedef struct { + __IO uint32_t OEUH; + __IO uint32_t OEUL; + __IO uint32_t OEVH; + __IO uint32_t OEVL; + __IO uint32_t OEWH; + __IO uint32_t OEWL; + __IO uint32_t OEXH; + __IO uint32_t OEXL; + __IO uint32_t MOE; + __IO uint32_t AOE; + uint32_t RESERVED0[22]; +} stc_tmr4_pscr_bit_t; + +typedef struct { + uint32_t RESERVED0[5]; + __IO uint32_t LMC; + uint32_t RESERVED1[2]; + __IO uint32_t EVTMS; + __IO uint32_t EVTDS; + uint32_t RESERVED2[2]; + __IO uint32_t DEN; + __IO uint32_t PEN; + __IO uint32_t UEN; + __IO uint32_t ZEN; +} stc_tmr4_scsr_bit_t; + +typedef struct { + uint32_t RESERVED0[6]; + __IO uint32_t MZCE; + __IO uint32_t MPCE; + uint32_t RESERVED1[8]; +} stc_tmr4_scmr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t PCTS; + uint32_t RESERVED1[7]; +} stc_tmr4_scer_bit_t; + +typedef struct { + __IO uint32_t RTIDU; + __IO uint32_t RTIDV; + __IO uint32_t RTIDW; + __IO uint32_t RTIDX; + __I uint32_t RTIFU; + __IO uint32_t RTICU; + __IO uint32_t RTEU; + __IO uint32_t RTSU; + __I uint32_t RTIFV; + __IO uint32_t RTICV; + __IO uint32_t RTEV; + __IO uint32_t RTSV; + __I uint32_t RTIFW; + __IO uint32_t RTICW; + __IO uint32_t RTEW; + __IO uint32_t RTSW; + __I uint32_t RTIFX; + __IO uint32_t RTICX; + __IO uint32_t RTEX; + __IO uint32_t RTSX; + uint32_t RESERVED0[12]; +} stc_tmr4_rcsr_bit_t; + +typedef struct { + __IO uint32_t ITEN0; + __IO uint32_t ITEN1; + __IO uint32_t ITEN2; + __IO uint32_t ITEN3; + __IO uint32_t ITEN4; + __IO uint32_t ITEN5; + __IO uint32_t ITEN6; + __IO uint32_t ITEN7; + uint32_t RESERVED0[8]; +} stc_tmr4_scir_bit_t; + +typedef struct { + __IO uint32_t SF0; + __IO uint32_t SF1; + __IO uint32_t SF2; + __IO uint32_t SF3; + __IO uint32_t SF4; + __IO uint32_t SF5; + __IO uint32_t SF6; + __IO uint32_t SF7; + uint32_t RESERVED0[8]; +} stc_tmr4_scfr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + uint32_t RESERVED0[5]; + __IO uint32_t OVSTP; + uint32_t RESERVED1[7]; + __IO uint32_t ZMSKREV; + __IO uint32_t ZMSKPOS; + uint32_t RESERVED2[14]; +} stc_tmr6_gconr_bit_t; + +typedef struct { + __IO uint32_t INTENA; + __IO uint32_t INTENB; + __IO uint32_t INTENC; + __IO uint32_t INTEND; + __IO uint32_t INTENE; + __IO uint32_t INTENF; + __IO uint32_t INTENOVF; + __IO uint32_t INTENUDF; + __IO uint32_t INTENDTE; + uint32_t RESERVED0[7]; + __IO uint32_t INTENSAU; + __IO uint32_t INTENSAD; + __IO uint32_t INTENSBU; + __IO uint32_t INTENSBD; + uint32_t RESERVED1[12]; +} stc_tmr6_iconr_bit_t; + +typedef struct { + __IO uint32_t BENA; + __IO uint32_t BSEA; + __IO uint32_t BTRUA; + __IO uint32_t BTRDA; + __IO uint32_t BENB; + __IO uint32_t BSEB; + __IO uint32_t BTRUB; + __IO uint32_t BTRDB; + __IO uint32_t BENP; + __IO uint32_t BSEP; + __IO uint32_t BTRUP; + __IO uint32_t BTRDP; + uint32_t RESERVED0[4]; + __IO uint32_t BENSPA; + __IO uint32_t BSESPA; + __IO uint32_t BTRUSPA; + __IO uint32_t BTRDSPA; + __IO uint32_t BENSPB; + __IO uint32_t BSESPB; + __IO uint32_t BTRUSPB; + __IO uint32_t BTRDSPB; + uint32_t RESERVED1[8]; +} stc_tmr6_bconr_bit_t; + +typedef struct { + __IO uint32_t DTCEN; + __IO uint32_t SEPA; + uint32_t RESERVED0[2]; + __IO uint32_t DTBENU; + __IO uint32_t DTBEND; + __IO uint32_t DTBTRU; + __IO uint32_t DTBTRD; + uint32_t RESERVED1[24]; +} stc_tmr6_dconr_bit_t; + +typedef struct { + uint32_t RESERVED0[28]; + __IO uint32_t OUTENA; + uint32_t RESERVED1[2]; + __IO uint32_t CAPMDA; +} stc_tmr6_pcnar_bit_t; + +typedef struct { + uint32_t RESERVED0[28]; + __IO uint32_t OUTENB; + uint32_t RESERVED1[2]; + __IO uint32_t CAPMDB; +} stc_tmr6_pcnbr_bit_t; + +typedef struct { + __IO uint32_t NOFIENGA; + uint32_t RESERVED0[3]; + __IO uint32_t NOFIENGB; + uint32_t RESERVED1[27]; +} stc_tmr6_fcngr_bit_t; + +typedef struct { + uint32_t RESERVED0[8]; + __IO uint32_t SPPERIA; + __IO uint32_t SPPERIB; + uint32_t RESERVED1[22]; +} stc_tmr6_vperr_bit_t; + +typedef struct { + __IO uint32_t CMAF; + __IO uint32_t CMBF; + __IO uint32_t CMCF; + __IO uint32_t CMDF; + __IO uint32_t CMEF; + __IO uint32_t CMFF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; + __I uint32_t DTEF; + __IO uint32_t CMSAUF; + __IO uint32_t CMSADF; + __IO uint32_t CMSBUF; + __IO uint32_t CMSBDF; + uint32_t RESERVED0[13]; + __IO uint32_t CMAF2; + __IO uint32_t CMBF2; + uint32_t RESERVED1[3]; + __I uint32_t DIRF; +} stc_tmr6_stflr_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + __IO uint32_t HSTA3; + uint32_t RESERVED0[3]; + __IO uint32_t STAS; + __IO uint32_t HSTA8; + __IO uint32_t HSTA9; + uint32_t RESERVED1[6]; + __IO uint32_t HSTA16; + __IO uint32_t HSTA17; + __IO uint32_t HSTA18; + __IO uint32_t HSTA19; + uint32_t RESERVED2[12]; +} stc_tmr6_hstar_bit_t; + +typedef struct { + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + __IO uint32_t HSTP3; + uint32_t RESERVED0[3]; + __IO uint32_t STPS; + __IO uint32_t HSTP8; + __IO uint32_t HSTP9; + uint32_t RESERVED1[6]; + __IO uint32_t HSTP16; + __IO uint32_t HSTP17; + __IO uint32_t HSTP18; + __IO uint32_t HSTP19; + uint32_t RESERVED2[12]; +} stc_tmr6_hstpr_bit_t; + +typedef struct { + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + __IO uint32_t HCLE3; + uint32_t RESERVED0[3]; + __IO uint32_t CLES; + __IO uint32_t HCLE8; + __IO uint32_t HCLE9; + uint32_t RESERVED1[6]; + __IO uint32_t HCLE16; + __IO uint32_t HCLE17; + __IO uint32_t HCLE18; + __IO uint32_t HCLE19; + uint32_t RESERVED2[12]; +} stc_tmr6_hclrr_bit_t; + +typedef struct { + __IO uint32_t HUPD0; + __IO uint32_t HUPD1; + __IO uint32_t HUPD2; + __IO uint32_t HUPD3; + uint32_t RESERVED0[3]; + __IO uint32_t UPDS; + __IO uint32_t HUPD8; + __IO uint32_t HUPD9; + uint32_t RESERVED1[6]; + __IO uint32_t HUPD16; + __IO uint32_t HUPD17; + __IO uint32_t HUPD18; + __IO uint32_t HUPD19; + uint32_t RESERVED2[12]; +} stc_tmr6_hupdr_bit_t; + +typedef struct { + __IO uint32_t HCPA0; + __IO uint32_t HCPA1; + __IO uint32_t HCPA2; + __IO uint32_t HCPA3; + uint32_t RESERVED0[4]; + __IO uint32_t HCPA8; + __IO uint32_t HCPA9; + uint32_t RESERVED1[6]; + __IO uint32_t HCPA16; + __IO uint32_t HCPA17; + __IO uint32_t HCPA18; + __IO uint32_t HCPA19; + uint32_t RESERVED2[4]; + __IO uint32_t HCPA24; + __IO uint32_t HCPA25; + uint32_t RESERVED3[6]; +} stc_tmr6_hcpar_bit_t; + +typedef struct { + __IO uint32_t HCPB0; + __IO uint32_t HCPB1; + __IO uint32_t HCPB2; + __IO uint32_t HCPB3; + uint32_t RESERVED0[4]; + __IO uint32_t HCPB8; + __IO uint32_t HCPB9; + uint32_t RESERVED1[6]; + __IO uint32_t HCPB16; + __IO uint32_t HCPB17; + __IO uint32_t HCPB18; + __IO uint32_t HCPB19; + uint32_t RESERVED2[4]; + __IO uint32_t HCPB24; + __IO uint32_t HCPB25; + uint32_t RESERVED3[6]; +} stc_tmr6_hcpbr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + uint32_t RESERVED0[6]; + __IO uint32_t HCUP16; + __IO uint32_t HCUP17; + __IO uint32_t HCUP18; + __IO uint32_t HCUP19; + uint32_t RESERVED1[12]; +} stc_tmr6_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + uint32_t RESERVED0[6]; + __IO uint32_t HCDO16; + __IO uint32_t HCDO17; + __IO uint32_t HCDO18; + __IO uint32_t HCDO19; + uint32_t RESERVED1[12]; +} stc_tmr6_hcdor_bit_t; + +typedef struct { + __IO uint32_t NOFIENTA; + uint32_t RESERVED0[3]; + __IO uint32_t NOFIENTB; + uint32_t RESERVED1[27]; +} stc_tmr6_common_fcntr_bit_t; + +typedef struct { + __IO uint32_t SSTA1; + __IO uint32_t SSTA2; + uint32_t RESERVED0[30]; +} stc_tmr6_common_sstar_bit_t; + +typedef struct { + __IO uint32_t SSTP1; + __IO uint32_t SSTP2; + uint32_t RESERVED0[30]; +} stc_tmr6_common_sstpr_bit_t; + +typedef struct { + __IO uint32_t SCLE1; + __IO uint32_t SCLE2; + uint32_t RESERVED0[30]; +} stc_tmr6_common_sclrr_bit_t; + +typedef struct { + __IO uint32_t SUPD1; + __IO uint32_t SUPD2; + uint32_t RESERVED0[30]; +} stc_tmr6_common_supdr_bit_t; + +typedef struct { + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + __IO uint32_t SYNST; + uint32_t RESERVED0[4]; +} stc_tmra_bcstrl_bit_t; + +typedef struct { + __IO uint32_t OVSTP; + uint32_t RESERVED0[3]; + __IO uint32_t ITENOVF; + __IO uint32_t ITENUDF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; +} stc_tmra_bcstrh_bit_t; + +typedef struct { + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + uint32_t RESERVED2[1]; + __IO uint32_t HCLE3; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; +} stc_tmra_hconr_bit_t; + +typedef struct { + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + __IO uint32_t HCUP12; + uint32_t RESERVED0[3]; +} stc_tmra_hcupr_bit_t; + +typedef struct { + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + __IO uint32_t HCDO12; + uint32_t RESERVED0[3]; +} stc_tmra_hcdor_bit_t; + +typedef struct { + __IO uint32_t ITEN1; + __IO uint32_t ITEN2; + __IO uint32_t ITEN3; + __IO uint32_t ITEN4; + __IO uint32_t ITEN5; + __IO uint32_t ITEN6; + __IO uint32_t ITEN7; + __IO uint32_t ITEN8; + uint32_t RESERVED0[8]; +} stc_tmra_iconr_bit_t; + +typedef struct { + __IO uint32_t ETEN1; + __IO uint32_t ETEN2; + __IO uint32_t ETEN3; + __IO uint32_t ETEN4; + __IO uint32_t ETEN5; + __IO uint32_t ETEN6; + __IO uint32_t ETEN7; + __IO uint32_t ETEN8; + uint32_t RESERVED0[8]; +} stc_tmra_econr_bit_t; + +typedef struct { + __IO uint32_t NOFIENTG; + uint32_t RESERVED0[7]; + __IO uint32_t NOFIENCA; + uint32_t RESERVED1[3]; + __IO uint32_t NOFIENCB; + uint32_t RESERVED2[3]; +} stc_tmra_fconr_bit_t; + +typedef struct { + __IO uint32_t CMPF1; + __IO uint32_t CMPF2; + __IO uint32_t CMPF3; + __IO uint32_t CMPF4; + __IO uint32_t CMPF5; + __IO uint32_t CMPF6; + __IO uint32_t CMPF7; + __IO uint32_t CMPF8; + __IO uint32_t ICPF1; + __IO uint32_t ICPF2; + __IO uint32_t ICPF3; + __IO uint32_t ICPF4; + __IO uint32_t ICPF5; + __IO uint32_t ICPF6; + __IO uint32_t ICPF7; + __IO uint32_t ICPF8; +} stc_tmra_stflr_bit_t; + +typedef struct { + __IO uint32_t BEN; + __IO uint32_t BSE0; + __IO uint32_t BSE1; + __IO uint32_t BSEN; + uint32_t RESERVED0[12]; +} stc_tmra_bconr_bit_t; + +typedef struct { + __IO uint32_t CAPMD; + uint32_t RESERVED0[3]; + __IO uint32_t HICP0; + __IO uint32_t HICP1; + __IO uint32_t HICP2; + uint32_t RESERVED1[1]; + __IO uint32_t HICP3; + __IO uint32_t HICP4; + __IO uint32_t HICP5; + __IO uint32_t HICP6; + __IO uint32_t NOFIENCP; + uint32_t RESERVED2[3]; +} stc_tmra_cconr_bit_t; + +typedef struct { + uint32_t RESERVED0[12]; + __IO uint32_t OUTEN; + uint32_t RESERVED1[3]; +} stc_tmra_pconr_bit_t; + +typedef struct { + __IO uint32_t EN; + __IO uint32_t RUN; + uint32_t RESERVED0[30]; +} stc_trng_cr_bit_t; + +typedef struct { + __IO uint32_t LOAD; + uint32_t RESERVED0[31]; +} stc_trng_mr_bit_t; + +typedef struct { + __I uint32_t PE; + __I uint32_t FE; + uint32_t RESERVED0[1]; + __I uint32_t ORE; + __I uint32_t BE; + __I uint32_t RXNE; + __I uint32_t TC; + __I uint32_t TXE; + __I uint32_t RTOF; + __I uint32_t WKUP; + __I uint32_t LBD; + __I uint32_t TEND; + uint32_t RESERVED1[4]; + __I uint32_t MPB; + uint32_t RESERVED2[15]; +} stc_usart_sr_bit_t; + +typedef struct { + uint32_t RESERVED0[9]; + __IO uint32_t MPID; + uint32_t RESERVED1[6]; +} stc_usart_tdr_bit_t; + +typedef struct { + __IO uint32_t RTOE; + __IO uint32_t RTOIE; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t SLME; + __IO uint32_t RIE; + __IO uint32_t TCIE; + __IO uint32_t TXEIE; + __IO uint32_t TENDIE; + __IO uint32_t PS; + __IO uint32_t PCE; + uint32_t RESERVED0[1]; + __IO uint32_t M; + uint32_t RESERVED1[2]; + __IO uint32_t OVER8; + __IO uint32_t CPE; + __IO uint32_t CFE; + uint32_t RESERVED2[1]; + __IO uint32_t CORE; + __IO uint32_t CRTOF; + __IO uint32_t CBE; + __IO uint32_t CWKUP; + __IO uint32_t CLBD; + __IO uint32_t MS; + __IO uint32_t CTEND; + uint32_t RESERVED3[2]; + __IO uint32_t ML; + __IO uint32_t FBME; + __IO uint32_t NFE; + __IO uint32_t SBS; +} stc_usart_cr1_bit_t; + +typedef struct { + __IO uint32_t MPE; + __IO uint32_t WKUPIE; + __IO uint32_t BEIE; + __IO uint32_t BEE; + __IO uint32_t LBDIE; + __IO uint32_t LBDL; + uint32_t RESERVED0[2]; + __IO uint32_t WKUPE; + uint32_t RESERVED1[4]; + __IO uint32_t STOP; + __IO uint32_t LINEN; + uint32_t RESERVED2[1]; + __IO uint32_t SBK; + __IO uint32_t SBKM; + uint32_t RESERVED3[14]; +} stc_usart_cr2_bit_t; + +typedef struct { + uint32_t RESERVED0[3]; + __IO uint32_t HDSEL; + __IO uint32_t LOOP; + __IO uint32_t SCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RTSE; + __IO uint32_t CTSE; + uint32_t RESERVED2[22]; +} stc_usart_cr3_bit_t; + +typedef struct { + uint32_t RESERVED0[4]; + __IO uint32_t ULBREN; + uint32_t RESERVED1[27]; +} stc_usart_pr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t SLPOFF; + uint32_t RESERVED1[14]; + __IO uint32_t ITS; +} stc_wdt_cr_bit_t; + +typedef struct { + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_wdt_sr_bit_t; + + +typedef struct { + stc_adc_str_bit_t STR_b; + uint32_t RESERVED0[8]; + stc_adc_cr0_bit_t CR0_b; + stc_adc_cr1_bit_t CR1_b; + stc_adc_cr2_bit_t CR2_b; + uint32_t RESERVED1[16]; + stc_adc_trgsr_bit_t TRGSR_b; + uint32_t RESERVED2[96]; + stc_adc_exchselr_bit_t EXCHSELR_b; + uint32_t RESERVED3[344]; + stc_adc_isr_bit_t ISR_b; + stc_adc_icr_bit_t ICR_b; + stc_adc_isclrr_bit_t ISCLRR_b; + uint32_t RESERVED4[40]; + stc_adc_synccr_bit_t SYNCCR_b; + uint32_t RESERVED5[656]; + stc_adc_awdcr_bit_t AWDCR_b; + stc_adc_awdsr_bit_t AWDSR_b; + stc_adc_awdsclrr_bit_t AWDSCLRR_b; +} bCM_ADC_TypeDef; + +typedef struct { + stc_aes_cr_bit_t CR_b; +} bCM_AES_TypeDef; + +typedef struct { + stc_aos_intsfttrg_bit_t INTSFTTRG_b; + uint32_t RESERVED0[2912]; + stc_aos_pevntnfcr_bit_t PEVNTNFCR_b; +} bCM_AOS_TypeDef; + +typedef struct { + stc_cmp_mdr_bit_t MDR_b; + stc_cmp_fir_bit_t FIR_b; + stc_cmp_ocr_bit_t OCR_b; + uint32_t RESERVED0[104]; + stc_cmp_bwsr1_bit_t BWSR1_b; +} bCM_CMP_TypeDef; + +typedef struct { + uint32_t RESERVED0[224]; + stc_cmu_xtaldivcr_bit_t XTALDIVCR_b; + uint32_t RESERVED1[156032]; + stc_cmu_xtalcfgr_bit_t XTALCFGR_b; + uint32_t RESERVED2[24]; + stc_cmu_xtal32cr_bit_t XTAL32CR_b; + uint32_t RESERVED3[184]; + stc_cmu_lrccr_bit_t LRCCR_b; + uint32_t RESERVED4[237032]; + stc_cmu_pllhcr_bit_t PLLHCR_b; + uint32_t RESERVED5[56]; + stc_cmu_xtalcr_bit_t XTALCR_b; + uint32_t RESERVED6[24]; + stc_cmu_hrccr_bit_t HRCCR_b; + uint32_t RESERVED7[8]; + stc_cmu_mrccr_bit_t MRCCR_b; + uint32_t RESERVED8[24]; + stc_cmu_oscstbsr_bit_t OSCSTBSR_b; + stc_cmu_mcocfgr_bit_t MCO1CFGR_b; + stc_cmu_mcocfgr_bit_t MCO2CFGR_b; + stc_cmu_tpiuckcfgr_bit_t TPIUCKCFGR_b; + stc_cmu_xtalstdcr_bit_t XTALSTDCR_b; + stc_cmu_xtalstdsr_bit_t XTALSTDSR_b; + uint32_t RESERVED9[1520]; + stc_cmu_pllhcfgr_bit_t PLLHCFGR_b; +} bCM_CMU_TypeDef; + +typedef struct { + stc_crc_cr_bit_t CR_b; +} bCM_CRC_TypeDef; + +typedef struct { + stc_ctc_cr1_bit_t CR1_b; + uint32_t RESERVED0[32]; + stc_ctc_str_bit_t STR_b; +} bCM_CTC_TypeDef; + +typedef struct { + stc_dac_dadr1_bit_t DADR1_b; + stc_dac_dadr2_bit_t DADR2_b; + stc_dac_dacr_bit_t DACR_b; + stc_dac_daadpcr_bit_t DAADPCR_b; + uint32_t RESERVED0[160]; + stc_dac_daocr_bit_t DAOCR_b; +} bCM_DAC_TypeDef; + +typedef struct { + stc_dcu_ctl_bit_t CTL_b; + stc_dcu_flag_bit_t FLAG_b; + uint32_t RESERVED0[96]; + stc_dcu_flagclr_bit_t FLAGCLR_b; + stc_dcu_intevtsel_bit_t INTEVTSEL_b; +} bCM_DCU_TypeDef; + +typedef struct { + stc_dma_en_bit_t EN_b; + stc_dma_intstat0_bit_t INTSTAT0_b; + stc_dma_intstat1_bit_t INTSTAT1_b; + stc_dma_intmask0_bit_t INTMASK0_b; + stc_dma_intmask1_bit_t INTMASK1_b; + stc_dma_intclr0_bit_t INTCLR0_b; + stc_dma_intclr1_bit_t INTCLR1_b; + uint32_t RESERVED0[32]; + stc_dma_reqstat_bit_t REQSTAT_b; + stc_dma_chstat_bit_t CHSTAT_b; + uint32_t RESERVED1[32]; + stc_dma_rcfgctl_bit_t RCFGCTL_b; + uint32_t RESERVED2[352]; + stc_dma_chctl_bit_t CHCTL0_b; + uint32_t RESERVED3[480]; + stc_dma_chctl_bit_t CHCTL1_b; + uint32_t RESERVED4[480]; + stc_dma_chctl_bit_t CHCTL2_b; + uint32_t RESERVED5[480]; + stc_dma_chctl_bit_t CHCTL3_b; + uint32_t RESERVED6[480]; + stc_dma_chctl_bit_t CHCTL4_b; + uint32_t RESERVED7[480]; + stc_dma_chctl_bit_t CHCTL5_b; +} bCM_DMA_TypeDef; + +typedef struct { + uint32_t RESERVED0[160]; + stc_efm_fstp_bit_t FSTP_b; + stc_efm_frmc_bit_t FRMC_b; + stc_efm_fwmc_bit_t FWMC_b; + stc_efm_fsr_bit_t FSR_b; + stc_efm_fsclr_bit_t FSCLR_b; + stc_efm_fite_bit_t FITE_b; + stc_efm_fswp_bit_t FSWP_b; + uint32_t RESERVED1[1696]; + stc_efm_mmf_remcr_bit_t MMF_REMCR0_b; + stc_efm_mmf_remcr_bit_t MMF_REMCR1_b; + uint32_t RESERVED2[928]; + stc_efm_wlock_bit_t WLOCK_b; + uint32_t RESERVED3[96]; + stc_efm_f0nwprt_bit_t F0NWPRT_b; +} bCM_EFM_TypeDef; + +typedef struct { + stc_emb_ctl1_bit_t CTL1_b; + stc_emb_ctl2_bit_t CTL2_b; + stc_emb_soe_bit_t SOE_b; + stc_emb_stat_bit_t STAT_b; + stc_emb_statclr_bit_t STATCLR_b; + stc_emb_inten_bit_t INTEN_b; + stc_emb_rlssel_bit_t RLSSEL_b; +} bCM_EMB_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_fcm_str_bit_t STR_b; + uint32_t RESERVED1[32]; + stc_fcm_rccr_bit_t RCCR_b; + stc_fcm_rier_bit_t RIER_b; + stc_fcm_sr_bit_t SR_b; + stc_fcm_clr_bit_t CLR_b; +} bCM_FCM_TypeDef; + +typedef struct { + stc_gpio_pidr_bit_t PIDRA_b; + uint32_t RESERVED0[16]; + stc_gpio_podr_bit_t PODRA_b; + stc_gpio_poer_bit_t POERA_b; + stc_gpio_posr_bit_t POSRA_b; + stc_gpio_porr_bit_t PORRA_b; + stc_gpio_potr_bit_t POTRA_b; + uint32_t RESERVED1[16]; + stc_gpio_pidr_bit_t PIDRB_b; + uint32_t RESERVED2[16]; + stc_gpio_podr_bit_t PODRB_b; + stc_gpio_poer_bit_t POERB_b; + stc_gpio_posr_bit_t POSRB_b; + stc_gpio_porr_bit_t PORRB_b; + stc_gpio_potr_bit_t POTRB_b; + uint32_t RESERVED3[16]; + stc_gpio_pidr_bit_t PIDRC_b; + uint32_t RESERVED4[16]; + stc_gpio_podr_bit_t PODRC_b; + stc_gpio_poer_bit_t POERC_b; + stc_gpio_posr_bit_t POSRC_b; + stc_gpio_porr_bit_t PORRC_b; + stc_gpio_potr_bit_t POTRC_b; + uint32_t RESERVED5[16]; + stc_gpio_pidr_bit_t PIDRD_b; + uint32_t RESERVED6[16]; + stc_gpio_podr_bit_t PODRD_b; + stc_gpio_poer_bit_t POERD_b; + stc_gpio_posr_bit_t POSRD_b; + stc_gpio_porr_bit_t PORRD_b; + stc_gpio_potr_bit_t POTRD_b; + uint32_t RESERVED7[16]; + stc_gpio_pidr_bit_t PIDRE_b; + uint32_t RESERVED8[16]; + stc_gpio_podr_bit_t PODRE_b; + stc_gpio_poer_bit_t POERE_b; + stc_gpio_posr_bit_t POSRE_b; + stc_gpio_porr_bit_t PORRE_b; + stc_gpio_potr_bit_t POTRE_b; + uint32_t RESERVED9[16]; + stc_gpio_pidr_bit_t PIDRH_b; + uint32_t RESERVED10[16]; + stc_gpio_podr_bit_t PODRH_b; + stc_gpio_poer_bit_t POERH_b; + stc_gpio_posr_bit_t POSRH_b; + stc_gpio_porr_bit_t PORRH_b; + stc_gpio_potr_bit_t POTRH_b; + uint32_t RESERVED11[7408]; + stc_gpio_pwpr_bit_t PWPR_b; + uint32_t RESERVED12[16]; + stc_gpio_pcr_bit_t PCRA0_b; + stc_gpio_pfsr_bit_t PFSRA0_b; + stc_gpio_pcr_bit_t PCRA1_b; + stc_gpio_pfsr_bit_t PFSRA1_b; + stc_gpio_pcr_bit_t PCRA2_b; + stc_gpio_pfsr_bit_t PFSRA2_b; + stc_gpio_pcr_bit_t PCRA3_b; + stc_gpio_pfsr_bit_t PFSRA3_b; + stc_gpio_pcr_bit_t PCRA4_b; + stc_gpio_pfsr_bit_t PFSRA4_b; + stc_gpio_pcr_bit_t PCRA5_b; + stc_gpio_pfsr_bit_t PFSRA5_b; + stc_gpio_pcr_bit_t PCRA6_b; + stc_gpio_pfsr_bit_t PFSRA6_b; + stc_gpio_pcr_bit_t PCRA7_b; + stc_gpio_pfsr_bit_t PFSRA7_b; + stc_gpio_pcr_bit_t PCRA8_b; + stc_gpio_pfsr_bit_t PFSRA8_b; + stc_gpio_pcr_bit_t PCRA9_b; + stc_gpio_pfsr_bit_t PFSRA9_b; + stc_gpio_pcr_bit_t PCRA10_b; + stc_gpio_pfsr_bit_t PFSRA10_b; + stc_gpio_pcr_bit_t PCRA11_b; + stc_gpio_pfsr_bit_t PFSRA11_b; + stc_gpio_pcr_bit_t PCRA12_b; + stc_gpio_pfsr_bit_t PFSRA12_b; + stc_gpio_pcr_bit_t PCRA13_b; + stc_gpio_pfsr_bit_t PFSRA13_b; + stc_gpio_pcr_bit_t PCRA14_b; + stc_gpio_pfsr_bit_t PFSRA14_b; + stc_gpio_pcr_bit_t PCRA15_b; + stc_gpio_pfsr_bit_t PFSRA15_b; + stc_gpio_pcr_bit_t PCRB0_b; + stc_gpio_pfsr_bit_t PFSRB0_b; + stc_gpio_pcr_bit_t PCRB1_b; + stc_gpio_pfsr_bit_t PFSRB1_b; + stc_gpio_pcr_bit_t PCRB2_b; + stc_gpio_pfsr_bit_t PFSRB2_b; + stc_gpio_pcr_bit_t PCRB3_b; + stc_gpio_pfsr_bit_t PFSRB3_b; + stc_gpio_pcr_bit_t PCRB4_b; + stc_gpio_pfsr_bit_t PFSRB4_b; + stc_gpio_pcr_bit_t PCRB5_b; + stc_gpio_pfsr_bit_t PFSRB5_b; + stc_gpio_pcr_bit_t PCRB6_b; + stc_gpio_pfsr_bit_t PFSRB6_b; + stc_gpio_pcr_bit_t PCRB7_b; + stc_gpio_pfsr_bit_t PFSRB7_b; + stc_gpio_pcr_bit_t PCRB8_b; + stc_gpio_pfsr_bit_t PFSRB8_b; + stc_gpio_pcr_bit_t PCRB9_b; + stc_gpio_pfsr_bit_t PFSRB9_b; + stc_gpio_pcr_bit_t PCRB10_b; + stc_gpio_pfsr_bit_t PFSRB10_b; + stc_gpio_pcr_bit_t PCRB11_b; + stc_gpio_pfsr_bit_t PFSRB11_b; + stc_gpio_pcr_bit_t PCRB12_b; + stc_gpio_pfsr_bit_t PFSRB12_b; + stc_gpio_pcr_bit_t PCRB13_b; + stc_gpio_pfsr_bit_t PFSRB13_b; + stc_gpio_pcr_bit_t PCRB14_b; + stc_gpio_pfsr_bit_t PFSRB14_b; + stc_gpio_pcr_bit_t PCRB15_b; + stc_gpio_pfsr_bit_t PFSRB15_b; + stc_gpio_pcr_bit_t PCRC0_b; + stc_gpio_pfsr_bit_t PFSRC0_b; + stc_gpio_pcr_bit_t PCRC1_b; + stc_gpio_pfsr_bit_t PFSRC1_b; + stc_gpio_pcr_bit_t PCRC2_b; + stc_gpio_pfsr_bit_t PFSRC2_b; + stc_gpio_pcr_bit_t PCRC3_b; + stc_gpio_pfsr_bit_t PFSRC3_b; + stc_gpio_pcr_bit_t PCRC4_b; + stc_gpio_pfsr_bit_t PFSRC4_b; + stc_gpio_pcr_bit_t PCRC5_b; + stc_gpio_pfsr_bit_t PFSRC5_b; + stc_gpio_pcr_bit_t PCRC6_b; + stc_gpio_pfsr_bit_t PFSRC6_b; + stc_gpio_pcr_bit_t PCRC7_b; + stc_gpio_pfsr_bit_t PFSRC7_b; + stc_gpio_pcr_bit_t PCRC8_b; + stc_gpio_pfsr_bit_t PFSRC8_b; + stc_gpio_pcr_bit_t PCRC9_b; + stc_gpio_pfsr_bit_t PFSRC9_b; + stc_gpio_pcr_bit_t PCRC10_b; + stc_gpio_pfsr_bit_t PFSRC10_b; + stc_gpio_pcr_bit_t PCRC11_b; + stc_gpio_pfsr_bit_t PFSRC11_b; + stc_gpio_pcr_bit_t PCRC12_b; + stc_gpio_pfsr_bit_t PFSRC12_b; + stc_gpio_pcr_bit_t PCRC13_b; + stc_gpio_pfsr_bit_t PFSRC13_b; + stc_gpio_pcr_bit_t PCRC14_b; + stc_gpio_pfsr_bit_t PFSRC14_b; + stc_gpio_pcr_bit_t PCRC15_b; + stc_gpio_pfsr_bit_t PFSRC15_b; + stc_gpio_pcr_bit_t PCRD0_b; + stc_gpio_pfsr_bit_t PFSRD0_b; + stc_gpio_pcr_bit_t PCRD1_b; + stc_gpio_pfsr_bit_t PFSRD1_b; + stc_gpio_pcr_bit_t PCRD2_b; + stc_gpio_pfsr_bit_t PFSRD2_b; + uint32_t RESERVED13[160]; + stc_gpio_pcr_bit_t PCRD8_b; + stc_gpio_pfsr_bit_t PFSRD8_b; + stc_gpio_pcr_bit_t PCRD9_b; + stc_gpio_pfsr_bit_t PFSRD9_b; + stc_gpio_pcr_bit_t PCRD10_b; + stc_gpio_pfsr_bit_t PFSRD10_b; + stc_gpio_pcr_bit_t PCRD11_b; + stc_gpio_pfsr_bit_t PFSRD11_b; + uint32_t RESERVED14[128]; + stc_gpio_pcr_bit_t PCRE0_b; + stc_gpio_pfsr_bit_t PFSRE0_b; + stc_gpio_pcr_bit_t PCRE1_b; + stc_gpio_pfsr_bit_t PFSRE1_b; + stc_gpio_pcr_bit_t PCRE2_b; + stc_gpio_pfsr_bit_t PFSRE2_b; + stc_gpio_pcr_bit_t PCRE3_b; + stc_gpio_pfsr_bit_t PFSRE3_b; + stc_gpio_pcr_bit_t PCRE4_b; + stc_gpio_pfsr_bit_t PFSRE4_b; + uint32_t RESERVED15[224]; + stc_gpio_pcr_bit_t PCRE12_b; + stc_gpio_pfsr_bit_t PFSRE12_b; + stc_gpio_pcr_bit_t PCRE13_b; + stc_gpio_pfsr_bit_t PFSRE13_b; + stc_gpio_pcr_bit_t PCRE14_b; + stc_gpio_pfsr_bit_t PFSRE14_b; + stc_gpio_pcr_bit_t PCRE15_b; + stc_gpio_pfsr_bit_t PFSRE15_b; + stc_gpio_pcr_bit_t PCRH0_b; + stc_gpio_pfsr_bit_t PFSRH0_b; + stc_gpio_pcr_bit_t PCRH1_b; + stc_gpio_pfsr_bit_t PFSRH1_b; + stc_gpio_pcr_bit_t PCRH2_b; + stc_gpio_pfsr_bit_t PFSRH2_b; +} bCM_GPIO_TypeDef; + +typedef struct { + stc_hash_cr_bit_t CR_b; +} bCM_HASH_TypeDef; + +typedef struct { + stc_i2c_cr1_bit_t CR1_b; + stc_i2c_cr2_bit_t CR2_b; + stc_i2c_cr3_bit_t CR3_b; + stc_i2c_cr4_bit_t CR4_b; + stc_i2c_slr0_bit_t SLR0_b; + stc_i2c_slr1_bit_t SLR1_b; + uint32_t RESERVED0[32]; + stc_i2c_sr_bit_t SR_b; + stc_i2c_clr_bit_t CLR_b; + uint32_t RESERVED1[96]; + stc_i2c_fltr_bit_t FLTR_b; + stc_i2c_fstr_bit_t FSTR_b; +} bCM_I2C_TypeDef; + +typedef struct { + stc_icg_icg0_bit_t ICG0_b; + stc_icg_icg1_bit_t ICG1_b; +} bCM_ICG_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_intc_nmier_bit_t NMIER_b; + stc_intc_nmifr_bit_t NMIFR_b; + stc_intc_nmifcr_bit_t NMIFCR_b; + stc_intc_eirqcr_bit_t EIRQCR0_b; + stc_intc_eirqcr_bit_t EIRQCR1_b; + stc_intc_eirqcr_bit_t EIRQCR2_b; + stc_intc_eirqcr_bit_t EIRQCR3_b; + stc_intc_eirqcr_bit_t EIRQCR4_b; + stc_intc_eirqcr_bit_t EIRQCR5_b; + stc_intc_eirqcr_bit_t EIRQCR6_b; + stc_intc_eirqcr_bit_t EIRQCR7_b; + stc_intc_eirqcr_bit_t EIRQCR8_b; + stc_intc_eirqcr_bit_t EIRQCR9_b; + stc_intc_eirqcr_bit_t EIRQCR10_b; + stc_intc_eirqcr_bit_t EIRQCR11_b; + stc_intc_eirqcr_bit_t EIRQCR12_b; + stc_intc_eirqcr_bit_t EIRQCR13_b; + stc_intc_eirqcr_bit_t EIRQCR14_b; + stc_intc_eirqcr_bit_t EIRQCR15_b; + stc_intc_wken_bit_t WKEN_b; + stc_intc_eifr_bit_t EIFR_b; + stc_intc_eifcr_bit_t EIFCR_b; + uint32_t RESERVED1[1024]; + stc_intc_swier_bit_t SWIER_b; + stc_intc_evter_bit_t EVTER_b; + stc_intc_ier_bit_t IER_b; +} bCM_INTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_keyscan_ser_bit_t SER_b; +} bCM_KEYSCAN_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_mcan_dbtp_bit_t DBTP_b; + stc_mcan_test_bit_t TEST_b; + uint32_t RESERVED1[32]; + stc_mcan_cccr_bit_t CCCR_b; + uint32_t RESERVED2[96]; + stc_mcan_tocc_bit_t TOCC_b; + uint32_t RESERVED3[160]; + stc_mcan_ecr_bit_t ECR_b; + stc_mcan_psr_bit_t PSR_b; + uint32_t RESERVED4[64]; + stc_mcan_ir_bit_t IR_b; + stc_mcan_ie_bit_t IE_b; + stc_mcan_ils_bit_t ILS_b; + stc_mcan_ile_bit_t ILE_b; + uint32_t RESERVED5[256]; + stc_mcan_gfc_bit_t GFC_b; + uint32_t RESERVED6[128]; + stc_mcan_hpms_bit_t HPMS_b; + stc_mcan_ndat1_bit_t NDAT1_b; + stc_mcan_ndat2_bit_t NDAT2_b; + stc_mcan_rxf0c_bit_t RXF0C_b; + stc_mcan_rxf0s_bit_t RXF0S_b; + uint32_t RESERVED7[64]; + stc_mcan_rxf1c_bit_t RXF1C_b; + stc_mcan_rxf1s_bit_t RXF1S_b; + uint32_t RESERVED8[64]; + stc_mcan_txbc_bit_t TXBC_b; + stc_mcan_txfqs_bit_t TXFQS_b; + uint32_t RESERVED9[32]; + stc_mcan_txbrp_bit_t TXBRP_b; + stc_mcan_txbar_bit_t TXBAR_b; + stc_mcan_txbcr_bit_t TXBCR_b; + stc_mcan_txbto_bit_t TXBTO_b; + stc_mcan_txbcf_bit_t TXBCF_b; + stc_mcan_txbtie_bit_t TXBTIE_b; + stc_mcan_txbcie_bit_t TXBCIE_b; + uint32_t RESERVED10[96]; + stc_mcan_txefs_bit_t TXEFS_b; +} bCM_MCAN_TypeDef; + +typedef struct { + uint32_t RESERVED0[512]; + stc_mpu_sr_bit_t SR_b; + stc_mpu_eclr_bit_t ECLR_b; + stc_mpu_wp_bit_t WP_b; + stc_mpu_ippr_bit_t IPPR_b; + uint32_t RESERVED1[32]; + stc_mpu_msppctl_bit_t MSPPCTL_b; + uint32_t RESERVED2[32]; + stc_mpu_psppctl_bit_t PSPPCTL_b; + stc_mpu_srge_bit_t S1RGE_b; + stc_mpu_srgwp_bit_t S1RGWP_b; + stc_mpu_srgrp_bit_t S1RGRP_b; + stc_mpu_scr_bit_t S1CR_b; + stc_mpu_srge_bit_t S2RGE_b; + stc_mpu_srgwp_bit_t S2RGWP_b; + stc_mpu_srgrp_bit_t S2RGRP_b; + stc_mpu_scr_bit_t S2CR_b; +} bCM_MPU_TypeDef; + +typedef struct { + uint32_t RESERVED0[96]; + stc_peric_smc_enar_bit_t SMC_ENAR_b; + uint32_t RESERVED1[32]; + stc_peric_tmr_synenr_bit_t TMR_SYNENR_b; + uint32_t RESERVED2[32]; + stc_peric_usart1_nfc_bit_t USART1_NFC_b; +} bCM_PERIC_TypeDef; + +typedef struct { + stc_pwc_fcg0_bit_t FCG0_b; + stc_pwc_fcg1_bit_t FCG1_b; + stc_pwc_fcg2_bit_t FCG2_b; + stc_pwc_fcg3_bit_t FCG3_b; + stc_pwc_fcg0pc_bit_t FCG0PC_b; + uint32_t RESERVED0[139104]; + stc_pwc_wktcr_bit_t WKTCR_b; + uint32_t RESERVED1[16368]; + stc_pwc_pwrc0_bit_t PWRC0_b; + uint32_t RESERVED2[24]; + stc_pwc_pwrc1_bit_t PWRC1_b; + uint32_t RESERVED3[88]; + stc_pwc_pwrc4_bit_t PWRC4_b; + uint32_t RESERVED4[24]; + stc_pwc_pvdcr0_bit_t PVDCR0_b; + uint32_t RESERVED5[24]; + stc_pwc_pvdcr1_bit_t PVDCR1_b; + uint32_t RESERVED6[24]; + stc_pwc_pvdfcr_bit_t PVDFCR_b; + uint32_t RESERVED7[88]; + stc_pwc_pdwke0_bit_t PDWKE0_b; + uint32_t RESERVED8[24]; + stc_pwc_pdwke1_bit_t PDWKE1_b; + uint32_t RESERVED9[24]; + stc_pwc_pdwke2_bit_t PDWKE2_b; + uint32_t RESERVED10[24]; + stc_pwc_pdwkes_bit_t PDWKES_b; + uint32_t RESERVED11[24]; + stc_pwc_pdwkf0_bit_t PDWKF0_b; + uint32_t RESERVED12[24]; + stc_pwc_pdwkf1_bit_t PDWKF1_b; + uint32_t RESERVED13[24]; + stc_pwc_pwrc5_bit_t PWRC5_b; + uint32_t RESERVED14[1048]; + stc_pwc_pvddsr_bit_t PVDDSR_b; + uint32_t RESERVED15[24]; + stc_pwc_rampc0_bit_t RAMPC0_b; + uint32_t RESERVED16[32]; + stc_pwc_pramlpc_bit_t PRAMLPC_b; + uint32_t RESERVED17[235968]; + stc_pwc_stpmcr_bit_t STPMCR_b; + uint32_t RESERVED18[8064]; + stc_pwc_fprc_bit_t FPRC_b; +} bCM_PWC_TypeDef; + +typedef struct { + stc_rmu_frst0_bit_t FRST0_b; + stc_rmu_frst1_bit_t FRST1_b; + stc_rmu_frst2_bit_t FRST2_b; + stc_rmu_frst3_bit_t FRST3_b; + stc_rmu_prstcr0_bit_t PRSTCR0_b; + uint32_t RESERVED0[24]; + stc_rmu_rstf0_bit_t RSTF0_b; +} bCM_RMU_TypeDef; + +typedef struct { + stc_rtc_cr0_bit_t CR0_b; + uint32_t RESERVED0[24]; + stc_rtc_cr1_bit_t CR1_b; + uint32_t RESERVED1[24]; + stc_rtc_cr2_bit_t CR2_b; + uint32_t RESERVED2[24]; + stc_rtc_cr3_bit_t CR3_b; + uint32_t RESERVED3[344]; + stc_rtc_errcrh_bit_t ERRCRH_b; +} bCM_RTC_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_spi_cr_bit_t CR_b; + uint32_t RESERVED1[32]; + stc_spi_cfg1_bit_t CFG1_b; + uint32_t RESERVED2[32]; + stc_spi_sr_bit_t SR_b; + stc_spi_cfg2_bit_t CFG2_b; +} bCM_SPI_TypeDef; + +typedef struct { + uint32_t RESERVED0[32]; + stc_sramc_wtpr_bit_t WTPR_b; + stc_sramc_ckcr_bit_t CKCR_b; + stc_sramc_ckpr_bit_t CKPR_b; + stc_sramc_cksr_bit_t CKSR_b; + stc_sramc_sram0_eien_bit_t SRAM0_EIEN_b; + uint32_t RESERVED1[96]; + stc_sramc_sramb_eien_bit_t SRAMB_EIEN_b; +} bCM_SRAMC_TypeDef; + +typedef struct { + stc_swdt_cr_bit_t CR_b; + stc_swdt_sr_bit_t SR_b; +} bCM_SWDT_TypeDef; + +typedef struct { + uint32_t RESERVED0[128]; + stc_tmr0_bconr_bit_t BCONR_b; + stc_tmr0_stflr_bit_t STFLR_b; +} bCM_TMR0_TypeDef; + +typedef struct { + uint32_t RESERVED0[256]; + stc_tmr4_ocsr_bit_t OCSRU_b; + stc_tmr4_ocer_bit_t OCERU_b; + stc_tmr4_ocsr_bit_t OCSRV_b; + stc_tmr4_ocer_bit_t OCERV_b; + stc_tmr4_ocsr_bit_t OCSRW_b; + stc_tmr4_ocer_bit_t OCERW_b; + stc_tmr4_ocsr_bit_t OCSRX_b; + stc_tmr4_ocer_bit_t OCERX_b; + stc_tmr4_ocmrh_bit_t OCMRUH_b; + uint32_t RESERVED1[16]; + stc_tmr4_ocmrl_bit_t OCMRUL_b; + stc_tmr4_ocmrh_bit_t OCMRVH_b; + uint32_t RESERVED2[16]; + stc_tmr4_ocmrl_bit_t OCMRVL_b; + stc_tmr4_ocmrh_bit_t OCMRWH_b; + uint32_t RESERVED3[16]; + stc_tmr4_ocmrl_bit_t OCMRWL_b; + stc_tmr4_ocmrh_bit_t OCMRXH_b; + uint32_t RESERVED4[16]; + stc_tmr4_ocmrl_bit_t OCMRXL_b; + uint32_t RESERVED5[64]; + stc_tmr4_ccsr_bit_t CCSR_b; + uint32_t RESERVED6[16]; + stc_tmr4_pscr_bit_t PSCR_b; + uint32_t RESERVED7[896]; + stc_tmr4_scsr_bit_t SCSRUH_b; + stc_tmr4_scmr_bit_t SCMRUH_b; + stc_tmr4_scsr_bit_t SCSRUL_b; + stc_tmr4_scmr_bit_t SCMRUL_b; + stc_tmr4_scsr_bit_t SCSRVH_b; + stc_tmr4_scmr_bit_t SCMRVH_b; + stc_tmr4_scsr_bit_t SCSRVL_b; + stc_tmr4_scmr_bit_t SCMRVL_b; + stc_tmr4_scsr_bit_t SCSRWH_b; + stc_tmr4_scmr_bit_t SCMRWH_b; + stc_tmr4_scsr_bit_t SCSRWL_b; + stc_tmr4_scmr_bit_t SCMRWL_b; + stc_tmr4_scsr_bit_t SCSRXH_b; + stc_tmr4_scmr_bit_t SCMRXH_b; + stc_tmr4_scsr_bit_t SCSRXL_b; + stc_tmr4_scmr_bit_t SCMRXL_b; + stc_tmr4_scer_bit_t SCER_b; + uint32_t RESERVED8[16]; + stc_tmr4_rcsr_bit_t RCSR_b; + stc_tmr4_scir_bit_t SCIR_b; + uint32_t RESERVED9[16]; + stc_tmr4_scfr_bit_t SCFR_b; +} bCM_TMR4_TypeDef; + +typedef struct { + uint32_t RESERVED0[2560]; + stc_tmr6_gconr_bit_t GCONR_b; + stc_tmr6_iconr_bit_t ICONR_b; + stc_tmr6_bconr_bit_t BCONR_b; + stc_tmr6_dconr_bit_t DCONR_b; + uint32_t RESERVED1[32]; + stc_tmr6_pcnar_bit_t PCNAR_b; + stc_tmr6_pcnbr_bit_t PCNBR_b; + stc_tmr6_fcngr_bit_t FCNGR_b; + stc_tmr6_vperr_bit_t VPERR_b; + stc_tmr6_stflr_bit_t STFLR_b; + uint32_t RESERVED2[192]; + stc_tmr6_hstar_bit_t HSTAR_b; + stc_tmr6_hstpr_bit_t HSTPR_b; + stc_tmr6_hclrr_bit_t HCLRR_b; + stc_tmr6_hupdr_bit_t HUPDR_b; + stc_tmr6_hcpar_bit_t HCPAR_b; + stc_tmr6_hcpbr_bit_t HCPBR_b; + stc_tmr6_hcupr_bit_t HCUPR_b; + stc_tmr6_hcdor_bit_t HCDOR_b; +} bCM_TMR6_TypeDef; + +typedef struct { + uint32_t RESERVED0[1888]; + stc_tmr6_common_fcntr_bit_t FCNTR_b; + stc_tmr6_common_sstar_bit_t SSTAR_b; + stc_tmr6_common_sstpr_bit_t SSTPR_b; + stc_tmr6_common_sclrr_bit_t SCLRR_b; + stc_tmr6_common_supdr_bit_t SUPDR_b; +} bCM_TMR6_COMMON_TypeDef; + +typedef struct { + uint32_t RESERVED0[1024]; + stc_tmra_bcstrl_bit_t BCSTRL_b; + stc_tmra_bcstrh_bit_t BCSTRH_b; + uint32_t RESERVED1[16]; + stc_tmra_hconr_bit_t HCONR_b; + uint32_t RESERVED2[16]; + stc_tmra_hcupr_bit_t HCUPR_b; + uint32_t RESERVED3[16]; + stc_tmra_hcdor_bit_t HCDOR_b; + uint32_t RESERVED4[16]; + stc_tmra_iconr_bit_t ICONR_b; + uint32_t RESERVED5[16]; + stc_tmra_econr_bit_t ECONR_b; + uint32_t RESERVED6[16]; + stc_tmra_fconr_bit_t FCONR_b; + uint32_t RESERVED7[16]; + stc_tmra_stflr_bit_t STFLR_b; + uint32_t RESERVED8[272]; + stc_tmra_bconr_bit_t BCONR1_b; + uint32_t RESERVED9[48]; + stc_tmra_bconr_bit_t BCONR2_b; + uint32_t RESERVED10[48]; + stc_tmra_bconr_bit_t BCONR3_b; + uint32_t RESERVED11[48]; + stc_tmra_bconr_bit_t BCONR4_b; + uint32_t RESERVED12[304]; + stc_tmra_cconr_bit_t CCONR1_b; + uint32_t RESERVED13[16]; + stc_tmra_cconr_bit_t CCONR2_b; + uint32_t RESERVED14[16]; + stc_tmra_cconr_bit_t CCONR3_b; + uint32_t RESERVED15[16]; + stc_tmra_cconr_bit_t CCONR4_b; + uint32_t RESERVED16[16]; + stc_tmra_cconr_bit_t CCONR5_b; + uint32_t RESERVED17[16]; + stc_tmra_cconr_bit_t CCONR6_b; + uint32_t RESERVED18[16]; + stc_tmra_cconr_bit_t CCONR7_b; + uint32_t RESERVED19[16]; + stc_tmra_cconr_bit_t CCONR8_b; + uint32_t RESERVED20[272]; + stc_tmra_pconr_bit_t PCONR1_b; + uint32_t RESERVED21[16]; + stc_tmra_pconr_bit_t PCONR2_b; + uint32_t RESERVED22[16]; + stc_tmra_pconr_bit_t PCONR3_b; + uint32_t RESERVED23[16]; + stc_tmra_pconr_bit_t PCONR4_b; + uint32_t RESERVED24[16]; + stc_tmra_pconr_bit_t PCONR5_b; + uint32_t RESERVED25[16]; + stc_tmra_pconr_bit_t PCONR6_b; + uint32_t RESERVED26[16]; + stc_tmra_pconr_bit_t PCONR7_b; + uint32_t RESERVED27[16]; + stc_tmra_pconr_bit_t PCONR8_b; +} bCM_TMRA_TypeDef; + +typedef struct { + stc_trng_cr_bit_t CR_b; + stc_trng_mr_bit_t MR_b; +} bCM_TRNG_TypeDef; + +typedef struct { + stc_usart_sr_bit_t SR_b; + stc_usart_tdr_bit_t TDR_b; + uint32_t RESERVED0[48]; + stc_usart_cr1_bit_t CR1_b; + stc_usart_cr2_bit_t CR2_b; + stc_usart_cr3_bit_t CR3_b; + stc_usart_pr_bit_t PR_b; +} bCM_USART_TypeDef; + +typedef struct { + stc_wdt_cr_bit_t CR_b; + stc_wdt_sr_bit_t SR_b; +} bCM_WDT_TypeDef; + + +/******************************************************************************/ +/* Device Specific Peripheral bit_band declaration & memory map */ +/******************************************************************************/ +#define bCM_ADC1 ((bCM_ADC_TypeDef *)0x42800000UL) +#define bCM_ADC2 ((bCM_ADC_TypeDef *)0x42808000UL) +#define bCM_ADC3 ((bCM_ADC_TypeDef *)0x42810000UL) +#define bCM_AES ((bCM_AES_TypeDef *)0x42100000UL) +#define bCM_AOS ((bCM_AOS_TypeDef *)0x42210000UL) +#define bCM_CMP1 ((bCM_CMP_TypeDef *)0x42710000UL) +#define bCM_CMP2 ((bCM_CMP_TypeDef *)0x42712000UL) +#define bCM_CMP3 ((bCM_CMP_TypeDef *)0x42718000UL) +#define bCM_CMP4 ((bCM_CMP_TypeDef *)0x4271A000UL) +#define bCM_CMU ((bCM_CMU_TypeDef *)0x42900000UL) +#define bCM_CRC ((bCM_CRC_TypeDef *)0x42118000UL) +#define bCM_CTC ((bCM_CTC_TypeDef *)0x42938000UL) +#define bCM_DAC ((bCM_DAC_TypeDef *)0x42820000UL) +#define bCM_DCU1 ((bCM_DCU_TypeDef *)0x42AC0000UL) +#define bCM_DCU2 ((bCM_DCU_TypeDef *)0x42AC8000UL) +#define bCM_DCU3 ((bCM_DCU_TypeDef *)0x42AD0000UL) +#define bCM_DCU4 ((bCM_DCU_TypeDef *)0x42AD8000UL) +#define bCM_DMA1 ((bCM_DMA_TypeDef *)0x42A60000UL) +#define bCM_DMA2 ((bCM_DMA_TypeDef *)0x42A68000UL) +#define bCM_EFM ((bCM_EFM_TypeDef *)0x42208000UL) +#define bCM_EMB0 ((bCM_EMB_TypeDef *)0x422F8000UL) +#define bCM_EMB1 ((bCM_EMB_TypeDef *)0x422F8400UL) +#define bCM_EMB2 ((bCM_EMB_TypeDef *)0x422F8800UL) +#define bCM_EMB3 ((bCM_EMB_TypeDef *)0x422F8C00UL) +#define bCM_FCM ((bCM_FCM_TypeDef *)0x42908000UL) +#define bCM_GPIO ((bCM_GPIO_TypeDef *)0x42A70000UL) +#define bCM_HASH ((bCM_HASH_TypeDef *)0x42108000UL) +#define bCM_I2C1 ((bCM_I2C_TypeDef *)0x42768000UL) +#define bCM_I2C2 ((bCM_I2C_TypeDef *)0x42770000UL) +#define bCM_INTC ((bCM_INTC_TypeDef *)0x42A20000UL) +#define bCM_KEYSCAN ((bCM_KEYSCAN_TypeDef *)0x42A18000UL) +#define bCM_MCAN1 ((bCM_MCAN_TypeDef *)0x42520000UL) +#define bCM_MCAN2 ((bCM_MCAN_TypeDef *)0x42528000UL) +#define bCM_MPU ((bCM_MPU_TypeDef *)0x42A00000UL) +#define bCM_PERIC ((bCM_PERIC_TypeDef *)0x42AA8000UL) +#define bCM_PWC ((bCM_PWC_TypeDef *)0x42900000UL) +#define bCM_RMU ((bCM_RMU_TypeDef *)0x42999C00UL) +#define bCM_RTC ((bCM_RTC_TypeDef *)0x42980000UL) +#define bCM_SPI1 ((bCM_SPI_TypeDef *)0x42380000UL) +#define bCM_SPI2 ((bCM_SPI_TypeDef *)0x42388000UL) +#define bCM_SPI3 ((bCM_SPI_TypeDef *)0x42400000UL) +#define bCM_SRAMC ((bCM_SRAMC_TypeDef *)0x42A10000UL) +#define bCM_SWDT ((bCM_SWDT_TypeDef *)0x42928000UL) +#define bCM_TMR0_1 ((bCM_TMR0_TypeDef *)0x42480000UL) +#define bCM_TMR0_2 ((bCM_TMR0_TypeDef *)0x42488000UL) +#define bCM_TMR4_1 ((bCM_TMR4_TypeDef *)0x42700000UL) +#define bCM_TMR4_2 ((bCM_TMR4_TypeDef *)0x42708000UL) +#define bCM_TMR4_3 ((bCM_TMR4_TypeDef *)0x4271C000UL) +#define bCM_TMR6_1 ((bCM_TMR6_TypeDef *)0x42780000UL) +#define bCM_TMR6_2 ((bCM_TMR6_TypeDef *)0x42788000UL) +#define bCM_TMR6_COMMON ((bCM_TMR6_COMMON_TypeDef *)0x42786000UL) +#define bCM_TMRA_1 ((bCM_TMRA_TypeDef *)0x42740000UL) +#define bCM_TMRA_2 ((bCM_TMRA_TypeDef *)0x42748000UL) +#define bCM_TMRA_3 ((bCM_TMRA_TypeDef *)0x42750000UL) +#define bCM_TMRA_4 ((bCM_TMRA_TypeDef *)0x42758000UL) +#define bCM_TMRA_5 ((bCM_TMRA_TypeDef *)0x424C0000UL) +#define bCM_TRNG ((bCM_TRNG_TypeDef *)0x42840000UL) +#define bCM_USART1 ((bCM_USART_TypeDef *)0x42398000UL) +#define bCM_USART2 ((bCM_USART_TypeDef *)0x423A0000UL) +#define bCM_USART3 ((bCM_USART_TypeDef *)0x423A8000UL) +#define bCM_USART4 ((bCM_USART_TypeDef *)0x42418000UL) +#define bCM_USART5 ((bCM_USART_TypeDef *)0x42420000UL) +#define bCM_USART6 ((bCM_USART_TypeDef *)0x42428000UL) +#define bCM_WDT ((bCM_WDT_TypeDef *)0x42920000UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F448_H__ */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h new file mode 100644 index 0000000000..d9ea25ddb8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/hc32f4xx.h @@ -0,0 +1,66 @@ +/** + ******************************************************************************* + * @file hc32f4xx.h + * @brief This file contains the common part of the HC32 series. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_H__ +#define __HC32F4XX_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +/** + * @brief HC32F4xx Device Include + */ +#if defined(HC32F448) +#include "hc32f448.h" +#include "system_hc32f448.h" +#else +#error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f448.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f448.h new file mode 100644 index 0000000000..103ba2ddab --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Include/system_hc32f448.h @@ -0,0 +1,140 @@ +/** + ******************************************************************************* + * @file system_hc32f448.h + * @brief This file contains all the functions prototypes of the HC32 System. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __SYSTEM_HC32F448_H__ +#define __SYSTEM_HC32F448_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F448_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @addtogroup HC32F448_System_Global_Macros + * @{ + */ + +/** + * @addtogroup HC32F448_System_Clock_Source + * @{ + */ +#if !defined (MRC_VALUE) +#define MRC_VALUE (8000000UL) /*!< Internal middle speed RC freq. */ +#endif + +#if !defined (LRC_VALUE) +#define LRC_VALUE (32768UL) /*!< Internal low speed RC freq. */ +#endif + +#if !defined (SWDTLRC_VALUE) +#define SWDTLRC_VALUE (10000UL) /*!< Internal SWDT low speed RC freq. */ +#endif + +#if !defined (XTAL_VALUE) +#define XTAL_VALUE (8000000UL) /*!< External high speed OSC freq. */ +#endif + +#if !defined (XTAL32_VALUE) +#define XTAL32_VALUE (32768UL) /*!< External low speed OSC freq. */ +#endif + +#if !defined (HCLK_VALUE) +#define HCLK_VALUE (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +/** + * @addtogroup HC32F448_System_Exported_Variable + * @{ + */ + +extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */ +extern uint32_t HRC_VALUE; /*!< HRC frequency */ + +/** + * @} + */ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HC32F448_System_Global_Functions + * @{ + */ + +extern void SystemInit(void); /*!< Initialize the system */ +extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */ + +#if defined (ROM_EXT_QSPI) +void SystemInit_QspiMem(void); +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F448_H__ */ + +/******************************************************************************* + * EOF (not truncated) + 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zCXnx=WAlK^1oC}!Y#wl#K)#QT%>ynI$oJ8)dB7k{FP?S1_~_U?;4*<;d~|FcFbLC& zXNz8ZbZj1Ifa_j-bZj1Ifa_j-bZj1|hudC!bZj1|hudC!bZj1|hudC!bZj1|hudC! zbZj0d;kJf~UVLu>v}Tz=YnBPLW|=^1mI<_GnLulHM0K*? z&Cb*p9Cq^s2aT;lkz#C<#+Gok2ftWv>#SOU_*p*&H{08yI3uZUE$-Y*Y_Vt`8^o0u z?gHNE;A#m)IqYy3O_3b6E8^-Gx)?Pc(n;6!)aj?w|7Fm>= z7}mLwVB|)EksF2!|0p+QbXI%4t>pEr@j8aJ*ABK`V^SfnV_17F!SGsw;Wfj?YfQ-S zx{S_gueX=Ho-g}$}2K`HhA{{x~3= + +Stack_Size EQU 0x00000C00 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Peripheral Interrupts + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD EXTINT00_SWINT16_Handler + DCD EXTINT01_SWINT17_Handler + DCD EXTINT02_SWINT18_Handler + DCD EXTINT03_SWINT19_Handler + DCD EXTINT04_SWINT20_Handler + DCD EXTINT05_SWINT21_Handler + DCD EXTINT06_SWINT22_Handler + DCD EXTINT07_SWINT23_Handler + DCD EXTINT08_SWINT24_Handler + DCD EXTINT09_SWINT25_Handler + DCD EXTINT10_SWINT26_Handler + DCD EXTINT11_SWINT27_Handler + DCD EXTINT12_SWINT28_Handler + DCD EXTINT13_SWINT29_Handler + DCD EXTINT14_SWINT30_Handler + DCD EXTINT15_SWINT31_Handler + DCD DMA1_Error_Handler + DCD DMA1_TC0_BTC0_Handler + DCD DMA1_TC1_BTC1_Handler + DCD DMA1_TC2_BTC2_Handler + DCD DMA1_TC3_BTC3_Handler + DCD DMA1_TC4_BTC4_Handler + DCD DMA1_TC5_BTC5_Handler + DCD EFM_PEError_ReadCol_Handler + DCD EFM_OpEnd_Handler + DCD QSPI_Handler + DCD DCU1_Handler + DCD DCU2_Handler + DCD DCU3_Handler + DCD DCU4_Handler + DCD DMA2_Error_Handler + DCD DMA2_TC0_BTC0_Handler + DCD DMA2_TC1_BTC1_Handler + DCD DMA2_TC2_BTC2_Handler + DCD DMA2_TC3_BTC3_Handler + DCD DMA2_TC4_BTC4_Handler + DCD DMA2_TC5_BTC5_Handler + DCD TMR0_1_Handler + DCD TMR0_2_Handler + DCD RTC_Handler + DCD CLK_XtalStop_Handler + DCD PWC_WKTM_Handler + DCD SWDT_Handler + DCD TMR6_1_GCmp_Handler + DCD TMR6_1_Ovf_Udf_Handler + DCD TMR6_1_Dte_Handler + DCD TMR6_1_SCmp_Handler + DCD TMRA_1_Ovf_Udf_Handler + DCD TMRA_1_Cmp_Handler + DCD TMR6_2_GCmp_Handler + DCD TMR6_2_Ovf_Udf_Handler + DCD TMR6_2_Dte_Handler + DCD TMR6_2_SCmp_Handler + DCD TMRA_2_Ovf_Udf_Handler + DCD TMRA_2_Cmp_Handler + DCD TMRA_3_Ovf_Udf_Handler + DCD TMRA_3_Cmp_Handler + DCD TMRA_4_Ovf_Udf_Handler + DCD TMRA_4_Cmp_Handler + DCD TMR4_1_GCmp_Handler + DCD TMR4_1_Ovf_Udf_Handler + DCD TMR4_1_Reload_Handler + DCD TMR4_1_SCmp_Handler + DCD TMR4_2_GCmp_Handler + DCD TMR4_2_Ovf_Udf_Handler + DCD TMR4_2_Reload_Handler + DCD TMR4_2_SCmp_Handler + DCD TMR4_3_GCmp_Handler + DCD TMR4_3_Ovf_Udf_Handler + DCD TMR4_3_Reload_Handler + DCD TMR4_3_SCmp_Handler + DCD I2C1_Handler + DCD I2C2_Handler + DCD CMP1_Handler + DCD CMP2_Handler + DCD CMP3_Handler + DCD CMP4_Handler + DCD USART1_Handler + DCD USART1_TxComplete_Handler + DCD USART2_Handler + DCD USART2_TxComplete_Handler + DCD SPI1_Handler + DCD TMRA_5_Ovf_Udf_Handler + DCD TMRA_5_Cmp_Handler + DCD EVENT_PORT1_Handler + DCD EVENT_PORT2_Handler + DCD EVENT_PORT3_Handler + DCD EVENT_PORT4_Handler + DCD USART3_Handler + DCD USART3_TxComplete_Handler + DCD USART4_Handler + DCD USART4_TxComplete_Handler + DCD SPI2_Handler + DCD SPI3_Handler + DCD EMB_GR0_Handler + DCD EMB_GR1_Handler + DCD EMB_GR2_Handler + DCD EMB_GR3_Handler + DCD USART5_Handler + DCD USART5_TxComplete_Handler + DCD USART6_Handler + DCD USART6_TxComplete_Handler + DCD MCAN1_INT0_Handler + DCD MCAN1_INT1_Handler + DCD MCAN2_INT0_Handler + DCD MCAN2_INT1_Handler + DCD USART1_WKUP_Handler + DCD PWC_LVD1_Handler + DCD PWC_LVD2_Handler + DCD FCM_Handler + DCD WDT_Handler + DCD CTC_Handler + DCD ADC1_Handler + DCD ADC2_Handler + DCD ADC3_Handler + DCD TRNG_Handler + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT EXTINT00_SWINT16_Handler [WEAK] + EXPORT EXTINT01_SWINT17_Handler [WEAK] + EXPORT EXTINT02_SWINT18_Handler [WEAK] + EXPORT EXTINT03_SWINT19_Handler [WEAK] + EXPORT EXTINT04_SWINT20_Handler [WEAK] + EXPORT EXTINT05_SWINT21_Handler [WEAK] + EXPORT EXTINT06_SWINT22_Handler [WEAK] + EXPORT EXTINT07_SWINT23_Handler [WEAK] + EXPORT EXTINT08_SWINT24_Handler [WEAK] + EXPORT EXTINT09_SWINT25_Handler [WEAK] + EXPORT EXTINT10_SWINT26_Handler [WEAK] + EXPORT EXTINT11_SWINT27_Handler [WEAK] + EXPORT EXTINT12_SWINT28_Handler [WEAK] + EXPORT EXTINT13_SWINT29_Handler [WEAK] + EXPORT EXTINT14_SWINT30_Handler [WEAK] + EXPORT EXTINT15_SWINT31_Handler [WEAK] + EXPORT DMA1_Error_Handler [WEAK] + EXPORT DMA1_TC0_BTC0_Handler [WEAK] + EXPORT DMA1_TC1_BTC1_Handler [WEAK] + EXPORT DMA1_TC2_BTC2_Handler [WEAK] + EXPORT DMA1_TC3_BTC3_Handler [WEAK] + EXPORT DMA1_TC4_BTC4_Handler [WEAK] + EXPORT DMA1_TC5_BTC5_Handler [WEAK] + EXPORT EFM_PEError_ReadCol_Handler [WEAK] + EXPORT EFM_OpEnd_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT DCU1_Handler [WEAK] + EXPORT DCU2_Handler [WEAK] + EXPORT DCU3_Handler [WEAK] + EXPORT DCU4_Handler [WEAK] + EXPORT DMA2_Error_Handler [WEAK] + EXPORT DMA2_TC0_BTC0_Handler [WEAK] + EXPORT DMA2_TC1_BTC1_Handler [WEAK] + EXPORT DMA2_TC2_BTC2_Handler [WEAK] + EXPORT DMA2_TC3_BTC3_Handler [WEAK] + EXPORT DMA2_TC4_BTC4_Handler [WEAK] + EXPORT DMA2_TC5_BTC5_Handler [WEAK] + EXPORT TMR0_1_Handler [WEAK] + EXPORT TMR0_2_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT CLK_XtalStop_Handler [WEAK] + EXPORT PWC_WKTM_Handler [WEAK] + EXPORT SWDT_Handler [WEAK] + EXPORT TMR6_1_GCmp_Handler [WEAK] + EXPORT TMR6_1_Ovf_Udf_Handler [WEAK] + EXPORT TMR6_1_Dte_Handler [WEAK] + EXPORT TMR6_1_SCmp_Handler [WEAK] + EXPORT TMRA_1_Ovf_Udf_Handler [WEAK] + EXPORT TMRA_1_Cmp_Handler [WEAK] + EXPORT TMR6_2_GCmp_Handler [WEAK] + EXPORT TMR6_2_Ovf_Udf_Handler [WEAK] + EXPORT TMR6_2_Dte_Handler [WEAK] + EXPORT TMR6_2_SCmp_Handler [WEAK] + EXPORT TMRA_2_Ovf_Udf_Handler [WEAK] + EXPORT TMRA_2_Cmp_Handler [WEAK] + EXPORT TMRA_3_Ovf_Udf_Handler [WEAK] + EXPORT TMRA_3_Cmp_Handler [WEAK] + EXPORT TMRA_4_Ovf_Udf_Handler [WEAK] + EXPORT TMRA_4_Cmp_Handler [WEAK] + EXPORT TMR4_1_GCmp_Handler [WEAK] + EXPORT TMR4_1_Ovf_Udf_Handler [WEAK] + EXPORT TMR4_1_Reload_Handler [WEAK] + EXPORT TMR4_1_SCmp_Handler [WEAK] + EXPORT TMR4_2_GCmp_Handler [WEAK] + EXPORT TMR4_2_Ovf_Udf_Handler [WEAK] + EXPORT TMR4_2_Reload_Handler [WEAK] + EXPORT TMR4_2_SCmp_Handler [WEAK] + EXPORT TMR4_3_GCmp_Handler [WEAK] + EXPORT TMR4_3_Ovf_Udf_Handler [WEAK] + EXPORT TMR4_3_Reload_Handler [WEAK] + EXPORT TMR4_3_SCmp_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT I2C2_Handler [WEAK] + EXPORT CMP1_Handler [WEAK] + EXPORT CMP2_Handler [WEAK] + EXPORT CMP3_Handler [WEAK] + EXPORT CMP4_Handler [WEAK] + EXPORT USART1_Handler [WEAK] + EXPORT USART1_TxComplete_Handler [WEAK] + EXPORT USART2_Handler [WEAK] + EXPORT USART2_TxComplete_Handler [WEAK] + EXPORT SPI1_Handler [WEAK] + EXPORT TMRA_5_Ovf_Udf_Handler [WEAK] + EXPORT TMRA_5_Cmp_Handler [WEAK] + EXPORT EVENT_PORT1_Handler [WEAK] + EXPORT EVENT_PORT2_Handler [WEAK] + EXPORT EVENT_PORT3_Handler [WEAK] + EXPORT EVENT_PORT4_Handler [WEAK] + EXPORT USART3_Handler [WEAK] + EXPORT USART3_TxComplete_Handler [WEAK] + EXPORT USART4_Handler [WEAK] + EXPORT USART4_TxComplete_Handler [WEAK] + EXPORT SPI2_Handler [WEAK] + EXPORT SPI3_Handler [WEAK] + EXPORT EMB_GR0_Handler [WEAK] + EXPORT EMB_GR1_Handler [WEAK] + EXPORT EMB_GR2_Handler [WEAK] + EXPORT EMB_GR3_Handler [WEAK] + EXPORT USART5_Handler [WEAK] + EXPORT USART5_TxComplete_Handler [WEAK] + EXPORT USART6_Handler [WEAK] + EXPORT USART6_TxComplete_Handler [WEAK] + EXPORT MCAN1_INT0_Handler [WEAK] + EXPORT MCAN1_INT1_Handler [WEAK] + EXPORT MCAN2_INT0_Handler [WEAK] + EXPORT MCAN2_INT1_Handler [WEAK] + EXPORT USART1_WKUP_Handler [WEAK] + EXPORT PWC_LVD1_Handler [WEAK] + EXPORT PWC_LVD2_Handler [WEAK] + EXPORT FCM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT CTC_Handler [WEAK] + EXPORT ADC1_Handler [WEAK] + EXPORT ADC2_Handler [WEAK] + EXPORT ADC3_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +EXTINT00_SWINT16_Handler +EXTINT01_SWINT17_Handler +EXTINT02_SWINT18_Handler +EXTINT03_SWINT19_Handler +EXTINT04_SWINT20_Handler +EXTINT05_SWINT21_Handler +EXTINT06_SWINT22_Handler +EXTINT07_SWINT23_Handler +EXTINT08_SWINT24_Handler +EXTINT09_SWINT25_Handler +EXTINT10_SWINT26_Handler +EXTINT11_SWINT27_Handler +EXTINT12_SWINT28_Handler +EXTINT13_SWINT29_Handler +EXTINT14_SWINT30_Handler +EXTINT15_SWINT31_Handler +DMA1_Error_Handler +DMA1_TC0_BTC0_Handler +DMA1_TC1_BTC1_Handler +DMA1_TC2_BTC2_Handler +DMA1_TC3_BTC3_Handler +DMA1_TC4_BTC4_Handler +DMA1_TC5_BTC5_Handler +EFM_PEError_ReadCol_Handler +EFM_OpEnd_Handler +QSPI_Handler +DCU1_Handler +DCU2_Handler +DCU3_Handler +DCU4_Handler +DMA2_Error_Handler +DMA2_TC0_BTC0_Handler +DMA2_TC1_BTC1_Handler +DMA2_TC2_BTC2_Handler +DMA2_TC3_BTC3_Handler +DMA2_TC4_BTC4_Handler +DMA2_TC5_BTC5_Handler +TMR0_1_Handler +TMR0_2_Handler +RTC_Handler +CLK_XtalStop_Handler +PWC_WKTM_Handler +SWDT_Handler +TMR6_1_GCmp_Handler +TMR6_1_Ovf_Udf_Handler +TMR6_1_Dte_Handler +TMR6_1_SCmp_Handler +TMRA_1_Ovf_Udf_Handler +TMRA_1_Cmp_Handler +TMR6_2_GCmp_Handler +TMR6_2_Ovf_Udf_Handler +TMR6_2_Dte_Handler +TMR6_2_SCmp_Handler +TMRA_2_Ovf_Udf_Handler +TMRA_2_Cmp_Handler +TMRA_3_Ovf_Udf_Handler +TMRA_3_Cmp_Handler +TMRA_4_Ovf_Udf_Handler +TMRA_4_Cmp_Handler +TMR4_1_GCmp_Handler +TMR4_1_Ovf_Udf_Handler +TMR4_1_Reload_Handler +TMR4_1_SCmp_Handler +TMR4_2_GCmp_Handler +TMR4_2_Ovf_Udf_Handler +TMR4_2_Reload_Handler +TMR4_2_SCmp_Handler +TMR4_3_GCmp_Handler +TMR4_3_Ovf_Udf_Handler +TMR4_3_Reload_Handler +TMR4_3_SCmp_Handler +I2C1_Handler +I2C2_Handler +CMP1_Handler +CMP2_Handler +CMP3_Handler +CMP4_Handler +USART1_Handler +USART1_TxComplete_Handler +USART2_Handler +USART2_TxComplete_Handler +SPI1_Handler +TMRA_5_Ovf_Udf_Handler +TMRA_5_Cmp_Handler +EVENT_PORT1_Handler +EVENT_PORT2_Handler +EVENT_PORT3_Handler +EVENT_PORT4_Handler +USART3_Handler +USART3_TxComplete_Handler +USART4_Handler +USART4_TxComplete_Handler +SPI2_Handler +SPI3_Handler +EMB_GR0_Handler +EMB_GR1_Handler +EMB_GR2_Handler +EMB_GR3_Handler +USART5_Handler +USART5_TxComplete_Handler +USART6_Handler +USART6_TxComplete_Handler +MCAN1_INT0_Handler +MCAN1_INT1_Handler +MCAN2_INT0_Handler +MCAN2_INT1_Handler +USART1_WKUP_Handler +PWC_LVD1_Handler +PWC_LVD2_Handler +FCM_Handler +WDT_Handler +CTC_Handler +ADC1_Handler +ADC2_Handler +ADC3_Handler +TRNG_Handler + + B . + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F448xA.ld b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F448xA.ld new file mode 100644 index 0000000000..6328cfaad0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F448xA.ld @@ -0,0 +1,216 @@ +/****************************************************************************** + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F448xA.ld */ +/* Abstract Linker script for HC32F448 Device with */ +/* 128KByte FLASH, 68KByte RAM */ +/* Version V1.0 */ +/* Date 2023-05-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 16 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 1024; +__OTP_LOCK_START = 0x03000A80; +__OTP_LOCK_SIZE = 128; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 128K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 64K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K + QSPI_ROM (rx): ORIGIN = 0x98000000, LENGTH = 8M +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .ex_rom : + { + . = ALIGN(4); + KEEP(*(.ex_rom)) + . = ALIGN(4); + } >QSPI_ROM + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F448xC.ld b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F448xC.ld new file mode 100644 index 0000000000..cb95657651 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/linker/HC32F448xC.ld @@ -0,0 +1,216 @@ +/****************************************************************************** + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F448xC.ld */ +/* Abstract Linker script for HC32F448 Device with */ +/* 256KByte FLASH, 68KByte RAM */ +/* Version V1.0 */ +/* Date 2023-05-31 */ +/*****************************************************************************/ + +/* Custom defines, according to section 7.7 of the user manual. + Take OTP sector 16 for example. */ +__OTP_DATA_START = 0x03000C00; +__OTP_DATA_SIZE = 1024; +__OTP_LOCK_START = 0x03000A80; +__OTP_LOCK_SIZE = 128; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 256K + OTP_DATA (rx): ORIGIN = __OTP_DATA_START, LENGTH = __OTP_DATA_SIZE + OTP_LOCK (rx): ORIGIN = __OTP_LOCK_START, LENGTH = __OTP_LOCK_SIZE + RAM (rwx): ORIGIN = 0x1FFF8000, LENGTH = 64K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K + QSPI_ROM (rx): ORIGIN = 0x98000000, LENGTH = 8M +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .ex_rom : + { + . = ALIGN(4); + KEEP(*(.ex_rom)) + . = ALIGN(4); + } >QSPI_ROM + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data_sec : + { + KEEP(*(.otp_data_sec)) + } >OTP_DATA + + .otp_lock_sec : + { + KEEP(*(.otp_lock_sec)) + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S new file mode 100644 index 0000000000..0e8b36831b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/startup_hc32f448.S @@ -0,0 +1,510 @@ +;/** +; ****************************************************************************** +; @file startup_hc32f448.S +; @brief Startup for GCC. +; verbatim +; Change Logs: +; Date Author Notes +; 2023-05-31 CDT First version +; endverbatim +; ***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; ****************************************************************************** +; */ + +/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + .syntax unified + .arch armv7e-m + .cpu cortex-m4 + .fpu softvfp + .thumb + +/* +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Stack_Size, 0x00000C00 + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Heap_Size, 0x00000400 + + .if Heap_Size != 0 /* Heap is provided */ + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .endif + +/* +; Interrupt vector table start. +*/ + .section .vectors, "a", %progbits + .align 2 + .type __Vectors, %object + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long IRQ000_Handler + .long IRQ001_Handler + .long IRQ002_Handler + .long IRQ003_Handler + .long IRQ004_Handler + .long IRQ005_Handler + .long IRQ006_Handler + .long IRQ007_Handler + .long IRQ008_Handler + .long IRQ009_Handler + .long IRQ010_Handler + .long IRQ011_Handler + .long IRQ012_Handler + .long IRQ013_Handler + .long IRQ014_Handler + .long IRQ015_Handler + .long EXTINT00_SWINT16_Handler + .long EXTINT01_SWINT17_Handler + .long EXTINT02_SWINT18_Handler + .long EXTINT03_SWINT19_Handler + .long EXTINT04_SWINT20_Handler + .long EXTINT05_SWINT21_Handler + .long EXTINT06_SWINT22_Handler + .long EXTINT07_SWINT23_Handler + .long EXTINT08_SWINT24_Handler + .long EXTINT09_SWINT25_Handler + .long EXTINT10_SWINT26_Handler + .long EXTINT11_SWINT27_Handler + .long EXTINT12_SWINT28_Handler + .long EXTINT13_SWINT29_Handler + .long EXTINT14_SWINT30_Handler + .long EXTINT15_SWINT31_Handler + .long DMA1_Error_Handler + .long DMA1_TC0_BTC0_Handler + .long DMA1_TC1_BTC1_Handler + .long DMA1_TC2_BTC2_Handler + .long DMA1_TC3_BTC3_Handler + .long DMA1_TC4_BTC4_Handler + .long DMA1_TC5_BTC5_Handler + .long EFM_PEError_ReadCol_Handler + .long EFM_OpEnd_Handler + .long QSPI_Handler + .long DCU1_Handler + .long DCU2_Handler + .long DCU3_Handler + .long DCU4_Handler + .long DMA2_Error_Handler + .long DMA2_TC0_BTC0_Handler + .long DMA2_TC1_BTC1_Handler + .long DMA2_TC2_BTC2_Handler + .long DMA2_TC3_BTC3_Handler + .long DMA2_TC4_BTC4_Handler + .long DMA2_TC5_BTC5_Handler + .long TMR0_1_Handler + .long TMR0_2_Handler + .long RTC_Handler + .long CLK_XtalStop_Handler + .long PWC_WKTM_Handler + .long SWDT_Handler + .long TMR6_1_GCmp_Handler + .long TMR6_1_Ovf_Udf_Handler + .long TMR6_1_Dte_Handler + .long TMR6_1_SCmp_Handler + .long TMRA_1_Ovf_Udf_Handler + .long TMRA_1_Cmp_Handler + .long TMR6_2_GCmp_Handler + .long TMR6_2_Ovf_Udf_Handler + .long TMR6_2_Dte_Handler + .long TMR6_2_SCmp_Handler + .long TMRA_2_Ovf_Udf_Handler + .long TMRA_2_Cmp_Handler + .long TMRA_3_Ovf_Udf_Handler + .long TMRA_3_Cmp_Handler + .long TMRA_4_Ovf_Udf_Handler + .long TMRA_4_Cmp_Handler + .long TMR4_1_GCmp_Handler + .long TMR4_1_Ovf_Udf_Handler + .long TMR4_1_Reload_Handler + .long TMR4_1_SCmp_Handler + .long TMR4_2_GCmp_Handler + .long TMR4_2_Ovf_Udf_Handler + .long TMR4_2_Reload_Handler + .long TMR4_2_SCmp_Handler + .long TMR4_3_GCmp_Handler + .long TMR4_3_Ovf_Udf_Handler + .long TMR4_3_Reload_Handler + .long TMR4_3_SCmp_Handler + .long I2C1_Handler + .long I2C2_Handler + .long CMP1_Handler + .long CMP2_Handler + .long CMP3_Handler + .long CMP4_Handler + .long USART1_Handler + .long USART1_TxComplete_Handler + .long USART2_Handler + .long USART2_TxComplete_Handler + .long SPI1_Handler + .long TMRA_5_Ovf_Udf_Handler + .long TMRA_5_Cmp_Handler + .long EVENT_PORT1_Handler + .long EVENT_PORT2_Handler + .long EVENT_PORT3_Handler + .long EVENT_PORT4_Handler + .long USART3_Handler + .long USART3_TxComplete_Handler + .long USART4_Handler + .long USART4_TxComplete_Handler + .long SPI2_Handler + .long SPI3_Handler + .long EMB_GR0_Handler + .long EMB_GR1_Handler + .long EMB_GR2_Handler + .long EMB_GR3_Handler + .long USART5_Handler + .long USART5_TxComplete_Handler + .long USART6_Handler + .long USART6_TxComplete_Handler + .long MCAN1_INT0_Handler + .long MCAN1_INT1_Handler + .long MCAN2_INT0_Handler + .long MCAN2_INT1_Handler + .long USART1_WKUP_Handler + .long PWC_LVD1_Handler + .long PWC_LVD2_Handler + .long FCM_Handler + .long WDT_Handler + .long CTC_Handler + .long ADC1_Handler + .long ADC2_Handler + .long ADC3_Handler + .long TRNG_Handler + +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors +/* +; Interrupt vector table end. +*/ + +/* +; Reset handler start. +*/ + .section .text.Reset_Handler + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + .globl Reset_Handler +Reset_Handler: +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ +StackInit: + ldr r1, =__StackLimit + ldr r2, =__StackTop + + movs r0, 0 +StackInitLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt StackInitLoop + +ClrSramSR: + ldr r0, =0x40050810 + movw r1, #0x1FF + str r1, [r0] + + /* Copy data from read only memory to RAM. */ +CopyData: + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +CopyLoop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop + +CopyData1: + ldr r1, =__etext_ramb + ldr r2, =__data_start_ramb__ + ldr r3, =__data_end_ramb__ +CopyLoop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop1 + +/* This part of work usually is done in C library startup code. + * Otherwise, define this macro to enable it in this startup. + * + * There are two schemes too. + * One can clear multiple BSS sections. Another can only clear one section. + * The former is more size expensive than the latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + /* Clear BSS section. */ +ClearBss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +ClearLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop + +ClearBss1: + ldr r1, =__bss_start_ramb__ + ldr r2, =__bss_end_ramb__ + + movs r0, 0 +ClearLoop1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop1 + + /* Call the clock system initialization function. */ + bl SystemInit + /* Call the application's entry point. */ + bl main + bx lr + .size Reset_Handler, . - Reset_Handler +/* +; Reset handler end. +*/ + +/* +; Default handler start. +*/ + .section .text.Default_Handler, "ax", %progbits + .align 2 +Default_Handler: + b . + .size Default_Handler, . - Default_Handler +/* +; Default handler end. +*/ + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler IRQ000_Handler + Set_Default_Handler IRQ001_Handler + Set_Default_Handler IRQ002_Handler + Set_Default_Handler IRQ003_Handler + Set_Default_Handler IRQ004_Handler + Set_Default_Handler IRQ005_Handler + Set_Default_Handler IRQ006_Handler + Set_Default_Handler IRQ007_Handler + Set_Default_Handler IRQ008_Handler + Set_Default_Handler IRQ009_Handler + Set_Default_Handler IRQ010_Handler + Set_Default_Handler IRQ011_Handler + Set_Default_Handler IRQ012_Handler + Set_Default_Handler IRQ013_Handler + Set_Default_Handler IRQ014_Handler + Set_Default_Handler IRQ015_Handler + Set_Default_Handler EXTINT00_SWINT16_Handler + Set_Default_Handler EXTINT01_SWINT17_Handler + Set_Default_Handler EXTINT02_SWINT18_Handler + Set_Default_Handler EXTINT03_SWINT19_Handler + Set_Default_Handler EXTINT04_SWINT20_Handler + Set_Default_Handler EXTINT05_SWINT21_Handler + Set_Default_Handler EXTINT06_SWINT22_Handler + Set_Default_Handler EXTINT07_SWINT23_Handler + Set_Default_Handler EXTINT08_SWINT24_Handler + Set_Default_Handler EXTINT09_SWINT25_Handler + Set_Default_Handler EXTINT10_SWINT26_Handler + Set_Default_Handler EXTINT11_SWINT27_Handler + Set_Default_Handler EXTINT12_SWINT28_Handler + Set_Default_Handler EXTINT13_SWINT29_Handler + Set_Default_Handler EXTINT14_SWINT30_Handler + Set_Default_Handler EXTINT15_SWINT31_Handler + Set_Default_Handler DMA1_Error_Handler + Set_Default_Handler DMA1_TC0_BTC0_Handler + Set_Default_Handler DMA1_TC1_BTC1_Handler + Set_Default_Handler DMA1_TC2_BTC2_Handler + Set_Default_Handler DMA1_TC3_BTC3_Handler + Set_Default_Handler DMA1_TC4_BTC4_Handler + Set_Default_Handler DMA1_TC5_BTC5_Handler + Set_Default_Handler EFM_PEError_ReadCol_Handler + Set_Default_Handler EFM_OpEnd_Handler + Set_Default_Handler QSPI_Handler + Set_Default_Handler DCU1_Handler + Set_Default_Handler DCU2_Handler + Set_Default_Handler DCU3_Handler + Set_Default_Handler DCU4_Handler + Set_Default_Handler DMA2_Error_Handler + Set_Default_Handler DMA2_TC0_BTC0_Handler + Set_Default_Handler DMA2_TC1_BTC1_Handler + Set_Default_Handler DMA2_TC2_BTC2_Handler + Set_Default_Handler DMA2_TC3_BTC3_Handler + Set_Default_Handler DMA2_TC4_BTC4_Handler + Set_Default_Handler DMA2_TC5_BTC5_Handler + Set_Default_Handler TMR0_1_Handler + Set_Default_Handler TMR0_2_Handler + Set_Default_Handler RTC_Handler + Set_Default_Handler CLK_XtalStop_Handler + Set_Default_Handler PWC_WKTM_Handler + Set_Default_Handler SWDT_Handler + Set_Default_Handler TMR6_1_GCmp_Handler + Set_Default_Handler TMR6_1_Ovf_Udf_Handler + Set_Default_Handler TMR6_1_Dte_Handler + Set_Default_Handler TMR6_1_SCmp_Handler + Set_Default_Handler TMRA_1_Ovf_Udf_Handler + Set_Default_Handler TMRA_1_Cmp_Handler + Set_Default_Handler TMR6_2_GCmp_Handler + Set_Default_Handler TMR6_2_Ovf_Udf_Handler + Set_Default_Handler TMR6_2_Dte_Handler + Set_Default_Handler TMR6_2_SCmp_Handler + Set_Default_Handler TMRA_2_Ovf_Udf_Handler + Set_Default_Handler TMRA_2_Cmp_Handler + Set_Default_Handler TMRA_3_Ovf_Udf_Handler + Set_Default_Handler TMRA_3_Cmp_Handler + Set_Default_Handler TMRA_4_Ovf_Udf_Handler + Set_Default_Handler TMRA_4_Cmp_Handler + Set_Default_Handler TMR4_1_GCmp_Handler + Set_Default_Handler TMR4_1_Ovf_Udf_Handler + Set_Default_Handler TMR4_1_Reload_Handler + Set_Default_Handler TMR4_1_SCmp_Handler + Set_Default_Handler TMR4_2_GCmp_Handler + Set_Default_Handler TMR4_2_Ovf_Udf_Handler + Set_Default_Handler TMR4_2_Reload_Handler + Set_Default_Handler TMR4_2_SCmp_Handler + Set_Default_Handler TMR4_3_GCmp_Handler + Set_Default_Handler TMR4_3_Ovf_Udf_Handler + Set_Default_Handler TMR4_3_Reload_Handler + Set_Default_Handler TMR4_3_SCmp_Handler + Set_Default_Handler I2C1_Handler + Set_Default_Handler I2C2_Handler + Set_Default_Handler CMP1_Handler + Set_Default_Handler CMP2_Handler + Set_Default_Handler CMP3_Handler + Set_Default_Handler CMP4_Handler + Set_Default_Handler USART1_Handler + Set_Default_Handler USART1_TxComplete_Handler + Set_Default_Handler USART2_Handler + Set_Default_Handler USART2_TxComplete_Handler + Set_Default_Handler SPI1_Handler + Set_Default_Handler TMRA_5_Ovf_Udf_Handler + Set_Default_Handler TMRA_5_Cmp_Handler + Set_Default_Handler EVENT_PORT1_Handler + Set_Default_Handler EVENT_PORT2_Handler + Set_Default_Handler EVENT_PORT3_Handler + Set_Default_Handler EVENT_PORT4_Handler + Set_Default_Handler USART3_Handler + Set_Default_Handler USART3_TxComplete_Handler + Set_Default_Handler USART4_Handler + Set_Default_Handler USART4_TxComplete_Handler + Set_Default_Handler SPI2_Handler + Set_Default_Handler SPI3_Handler + Set_Default_Handler EMB_GR0_Handler + Set_Default_Handler EMB_GR1_Handler + Set_Default_Handler EMB_GR2_Handler + Set_Default_Handler EMB_GR3_Handler + Set_Default_Handler USART5_Handler + Set_Default_Handler USART5_TxComplete_Handler + Set_Default_Handler USART6_Handler + Set_Default_Handler USART6_TxComplete_Handler + Set_Default_Handler MCAN1_INT0_Handler + Set_Default_Handler MCAN1_INT1_Handler + Set_Default_Handler MCAN2_INT0_Handler + Set_Default_Handler MCAN2_INT1_Handler + Set_Default_Handler USART1_WKUP_Handler + Set_Default_Handler PWC_LVD1_Handler + Set_Default_Handler PWC_LVD2_Handler + Set_Default_Handler FCM_Handler + Set_Default_Handler WDT_Handler + Set_Default_Handler CTC_Handler + Set_Default_Handler ADC1_Handler + Set_Default_Handler ADC2_Handler + Set_Default_Handler ADC3_Handler + Set_Default_Handler TRNG_Handler + + .end diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd new file mode 100644 index 0000000000..5ab6c67971 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/GCC/svd/HC32F448.svd @@ -0,0 +1,56794 @@ + + + HC32F448 + 1.0 + HC32F448 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + 0x0 + 0xFFFFFFFF + + + ADC1 + desc ADC1 + 0x40040000 + + 0x0 + 0xB1 + registers + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F7 + + + MS + desc MS + 2 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + CR2 + desc CR2 + 0x6 + 16 + read-write + 0x0 + 0x1F00 + + + OVSS + desc OVSS + 11 + 8 + read-write + + + OVSMOD + desc OVSMOD + 12 + 12 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + CHSELA + desc CHSELA + 15 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFF + + + CHSELB + desc CHSELB + 15 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + AVCHSEL + desc AVCHSEL + 15 + 0 + read-write + + + + + EXCHSELR + desc EXCHSELR + 0x18 + 8 + read-write + 0x0 + 0x1 + + + EXCHSEL + desc EXCHSEL + 0 + 0 + read-write + + + + + SSTR0 + desc SSTR0 + 0x20 + 8 + read-write + 0xB + 0xFF + + + SSTR1 + desc SSTR1 + 0x21 + 8 + read-write + 0xB + 0xFF + + + SSTR2 + desc SSTR2 + 0x22 + 8 + read-write + 0xB + 0xFF + + + SSTR3 + desc SSTR3 + 0x23 + 8 + read-write + 0xB + 0xFF + + + SSTR4 + desc SSTR4 + 0x24 + 8 + read-write + 0xB + 0xFF + + + SSTR5 + desc SSTR5 + 0x25 + 8 + read-write + 0xB + 0xFF + + + SSTR6 + desc SSTR6 + 0x26 + 8 + read-write + 0xB + 0xFF + + + SSTR7 + desc SSTR7 + 0x27 + 8 + read-write + 0xB + 0xFF + + + SSTR8 + desc SSTR8 + 0x28 + 8 + read-write + 0xB + 0xFF + + + SSTR9 + desc SSTR9 + 0x29 + 8 + read-write + 0xB + 0xFF + + + SSTR10 + desc SSTR10 + 0x2A + 8 + read-write + 0xB + 0xFF + + + SSTR11 + desc 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+ + TMRA4 + desc TMRA + 0x4003AC00 + + 0x0 + 0x15E + registers + + + + TMRA5 + desc TMRA + 0x40026000 + + 0x0 + 0x15E + registers + + + + TRNG + desc TRNG + 0x40042000 + + 0x0 + 0x14 + registers + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + 0x3 + + + EN + desc EN + 0 + 0 + read-write + + + RUN + desc RUN + 1 + 1 + read-write + + + + + MR + desc MR + 0x4 + 32 + read-write + 0x12 + 0x1D + + + LOAD + desc LOAD + 0 + 0 + read-write + + + CNT + desc CNT + 4 + 2 + read-write + + + + + DR0 + desc DR0 + 0xC + 32 + read-only + 0x0 + 0xFFFFFFFF + + + DR1 + desc DR1 + 0x10 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + + + USART1 + desc USART + 0x4001CC00 + + 0x0 + 0x1C + registers + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x109EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + TEND + desc TEND + 11 + 11 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + TDR + desc TDR + 0x4 + 16 + read-write + 0x1FF + 0x3FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + + + RDR + desc RDR + 0x6 + 16 + read-only + 0x0 + 0x1FF + + + RDR + desc RDR + 8 + 0 + read-only + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF31B97FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + TENDIE + desc TENDIE + 8 + 8 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CRTOF + desc CRTOF + 20 + 20 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + CTEND + desc CTEND + 25 + 25 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x13 + + + PSC + desc PSC + 1 + 0 + read-write + + + ULBREN + desc ULBREN + 4 + 4 + read-write + + + + + + + USART2 + desc USART + 0x4001D000 + + 0x0 + 0x1C + registers + + + + USART3 + desc USART + 0x4001D400 + + 0x0 + 0x20 + registers + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x10EFB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + BE + desc BE + 4 + 4 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + WKUP + desc WKUP + 9 + 9 + read-only + + + LBD + desc LBD + 10 + 10 + read-only + + + TEND + desc TEND + 11 + 11 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + TDR + desc TDR + 0x4 + 16 + read-write + 0x1FF + 0x3FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + + + RDR + desc RDR + 0x6 + 16 + read-only + 0x0 + 0x1FF + + + RDR + desc RDR + 8 + 0 + read-only + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFFFF + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xF3EB97FC + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + TENDIE + desc TENDIE + 8 + 8 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CBE + desc CBE + 21 + 21 + read-write + + + CWKUP + desc CWKUP + 22 + 22 + read-write + + + CLBD + desc CLBD + 23 + 23 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + CTEND + desc CTEND + 25 + 25 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + FBME + desc FBME + 29 + 29 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x379FF + + + MPE + desc MPE + 0 + 0 + read-write + + + WKUPIE + desc WKUPIE + 1 + 1 + read-write + + + BEIE + desc BEIE + 2 + 2 + read-write + + + BEE + desc BEE + 3 + 3 + read-write + + + LBDIE + desc LBDIE + 4 + 4 + read-write + + + LBDL + desc LBDL + 5 + 5 + read-write + + + SBKL + desc SBKL + 7 + 6 + read-write + + + WKUPE + desc WKUPE + 8 + 8 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + LINEN + desc LINEN + 14 + 14 + read-write + + + SBK + desc SBK + 16 + 16 + read-write + + + SBKM + desc SBKM + 17 + 17 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0x318 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + LOOP + desc LOOP + 4 + 4 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x1F + + + PSC + desc PSC + 1 + 0 + read-write + + + LBMPSC + desc LBMPSC + 3 + 2 + read-write + + + ULBREN + desc ULBREN + 4 + 4 + read-write + + + + + LBMC + desc LBMC + 0x1C + 32 + read-only + 0x0 + 0xFFFF + + + LBMC + desc LBMC + 15 + 0 + read-only + + + + + + + USART4 + desc USART + 0x40020C00 + + 0x0 + 0x1C + registers + + + + USART5 + desc USART5 + 0x40021000 + + 0x0 + 0x1C + registers + + + + SR + desc SR + 0x0 + 32 + read-only + 0xC0 + 0x109EB + + + PE + desc PE + 0 + 0 + read-only + + + FE + desc FE + 1 + 1 + read-only + + + ORE + desc ORE + 3 + 3 + read-only + + + RXNE + desc RXNE + 5 + 5 + read-only + + + TC + desc TC + 6 + 6 + read-only + + + TXE + desc TXE + 7 + 7 + read-only + + + RTOF + desc RTOF + 8 + 8 + read-only + + + TEND + desc TEND + 11 + 11 + read-only + + + MPB + desc MPB + 16 + 16 + read-only + + + + + TDR + desc TDR + 0x4 + 16 + read-write + 0x1FF + 0x3FF + + + TDR + desc TDR + 8 + 0 + read-write + + + MPID + desc MPID + 9 + 9 + read-write + + + + + RDR + desc RDR + 0x6 + 16 + read-only + 0x0 + 0x1FF + + + RDR + desc RDR + 8 + 0 + read-only + + + + + BRR + desc BRR + 0x8 + 32 + read-write + 0xFF00 + 0xFF7F + + + DIV_FRACTION + desc DIV_FRACTION + 6 + 0 + read-write + + + DIV_INTEGER + desc DIV_INTEGER + 15 + 8 + read-write + + + + + CR1 + desc CR1 + 0xC + 32 + read-write + 0x80000000 + 0xD31B97FF + + + RTOE + desc RTOE + 0 + 0 + read-write + + + RTOIE + desc RTOIE + 1 + 1 + read-write + + + RE + desc RE + 2 + 2 + read-write + + + TE + desc TE + 3 + 3 + read-write + + + SLME + desc SLME + 4 + 4 + read-write + + + RIE + desc RIE + 5 + 5 + read-write + + + TCIE + desc TCIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + TENDIE + desc TENDIE + 8 + 8 + read-write + + + PS + desc PS + 9 + 9 + read-write + + + PCE + desc PCE + 10 + 10 + read-write + + + M + desc M + 12 + 12 + read-write + + + OVER8 + desc OVER8 + 15 + 15 + read-write + + + CPE + desc CPE + 16 + 16 + read-write + + + CFE + desc CFE + 17 + 17 + read-write + + + CORE + desc CORE + 19 + 19 + read-write + + + CRTOF + desc CRTOF + 20 + 20 + read-write + + + MS + desc MS + 24 + 24 + read-write + + + CTEND + desc CTEND + 25 + 25 + read-write + + + ML + desc ML + 28 + 28 + read-write + + + NFE + desc NFE + 30 + 30 + read-write + + + SBS + desc SBS + 31 + 31 + read-write + + + + + CR2 + desc CR2 + 0x10 + 32 + read-write + 0x600 + 0x3801 + + + MPE + desc MPE + 0 + 0 + read-write + + + CLKC + desc CLKC + 12 + 11 + read-write + + + STOP + desc STOP + 13 + 13 + read-write + + + + + CR3 + desc CR3 + 0x14 + 32 + read-write + 0x0 + 0xE00328 + + + HDSEL + desc HDSEL + 3 + 3 + read-write + + + SCEN + desc SCEN + 5 + 5 + read-write + + + RTSE + desc RTSE + 8 + 8 + read-write + + + CTSE + desc CTSE + 9 + 9 + read-write + + + BCN + desc BCN + 23 + 21 + read-write + + + + + PR + desc PR + 0x18 + 32 + read-write + 0x0 + 0x13 + + + PSC + desc PSC + 1 + 0 + read-write + + + ULBREN + desc ULBREN + 4 + 4 + read-write + + + + + + + USART6 + desc USART + 0x40021400 + + 0x0 + 0x20 + registers + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + registers + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-write + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-write + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-write + + + + + + + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f448.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f448.c new file mode 100644 index 0000000000..d5cffa14b7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Device/HDSC/hc32f4xx/Source/system_hc32f448.c @@ -0,0 +1,205 @@ +/** + ******************************************************************************* + * @file system_hc32f448.c + * @brief This file provides two functions and two global variables to be called + * from user application. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "system_hc32f448.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F448_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @defgroup HC32F448_System_Local_Macros HC32F448 System Local Macros + * @{ + */ +#define HRC_16MHz_VALUE (16000000UL) /*!< Internal high speed RC freq. */ +#define HRC_20MHz_VALUE (20000000UL) /*!< Internal high speed RC freq. */ +/* HRC select */ +#define HRC_FREQ_MON() (*((volatile uint32_t *)(0x40010684UL))) + +/* Vector Table base offset field */ +#ifndef VECT_TAB_OFFSET +#define VECT_TAB_OFFSET (0x0UL) /*!< This value must be a multiple of 0x400. */ +#endif +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @addtogroup HC32F448_System_Global_Variable + * @{ + */ + +/*!< System clock frequency (Core clock) */ +__NO_INIT uint32_t SystemCoreClock; +/*!< High speed RC frequency (HCR clock) */ +__NO_INIT uint32_t HRC_VALUE; + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup HC32F448_System_Global_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. Initialize the System and update + * the SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20) | (3UL << 22)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); +#if defined (ROM_EXT_QSPI) + SystemInit_QspiMem(); +#endif /* ROM_EXT_QSPI */ + /* Configure the Vector Table relocation */ + SCB->VTOR = VECT_TAB_OFFSET; /* Vector Table Relocation */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t u8SysClkSrc; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t u32PllSrcFreq; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + if (1UL == (HRC_FREQ_MON() & 1UL)) { + HRC_VALUE = HRC_16MHz_VALUE; + } else { + HRC_VALUE = HRC_20MHz_VALUE; + } + u8SysClkSrc = CM_CMU->CKSWR & CMU_CKSWR_CKSW; + switch (u8SysClkSrc) { + case 0x00U: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01U: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02U: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03U: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04U: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05U: /* use PLLH */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + plln = (CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS; + pllp = (CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS; + pllm = (CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS; + if (0UL == bCM_CMU->PLLHCFGR_b.PLLSRC) { /* use external high speed OSC as PLL source */ + u32PllSrcFreq = XTAL_VALUE; + } else { /* use internal high RC as PLL source */ + u32PllSrcFreq = HRC_VALUE; + } + SystemCoreClock = u32PllSrcFreq / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + break; + default: + break; + } +} + +#if defined (ROM_EXT_QSPI) +/** + * @brief Initialize the QSPI memory. + * @param None + * @retval None + */ +__WEAKDEF void SystemInit_QspiMem(void) +{ + /* QSPI configure */ + CM_GPIO->PWPR = 0xA501U; + /* High driver */ + CM_GPIO->PCRC7 = 0x0120U; + CM_GPIO->PCRB14 = 0x0120U; + CM_GPIO->PCRB13 = 0x0120U; + CM_GPIO->PCRD9 = 0x0120U; + CM_GPIO->PCRD10 = 0x0120U; + CM_GPIO->PCRD11 = 0x0120U; + /* Set function */ + CM_GPIO->PFSRC7 = 0x07U; + CM_GPIO->PFSRB14 = 0x07U; + CM_GPIO->PFSRB13 = 0x07U; + CM_GPIO->PFSRD9 = 0x07U; + CM_GPIO->PFSRD10 = 0x07U; + CM_GPIO->PFSRD11 = 0x07U; + /* qspi configure */ + CM_PWC->FCG1 &= ~0x00000008UL; + CM_QSPI->CR = 0x0002000D; + CM_QSPI->CSCR = 0x00000001; + CM_QSPI->FCR = 0x00008332; +} +#endif /* ROM_EXT_QSPI */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_common_tables.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_common_tables.h new file mode 100644 index 0000000000..721b18dd2d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_common_tables.h @@ -0,0 +1,517 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_common_tables.h + * Description: Extern declaration for common tables + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + /* Double Precision Float CFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024) + extern const uint16_t armBitRevTable[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16) + extern const uint64_t twiddleCoefF64_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32) + extern const uint64_t twiddleCoefF64_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64) + extern const uint64_t twiddleCoefF64_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128) + extern const uint64_t twiddleCoefF64_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256) + extern const uint64_t twiddleCoefF64_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512) + extern const uint64_t twiddleCoefF64_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024) + extern const uint64_t twiddleCoefF64_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048) + extern const uint64_t twiddleCoefF64_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096) + extern const uint64_t twiddleCoefF64_4096[8192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) + extern const float32_t twiddleCoef_16[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + extern const float32_t twiddleCoef_32[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) + extern const float32_t twiddleCoef_64[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + extern const float32_t twiddleCoef_128[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) + extern const float32_t twiddleCoef_256[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + extern const float32_t twiddleCoef_512[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) + extern const float32_t twiddleCoef_1024[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + extern const float32_t twiddleCoef_2048[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) + extern const float32_t twiddleCoef_4096[8192]; + #define twiddleCoef twiddleCoef_4096 + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) + extern const q31_t twiddleCoef_16_q31[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + extern const q31_t twiddleCoef_32_q31[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) + extern const q31_t twiddleCoef_64_q31[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + extern const q31_t twiddleCoef_128_q31[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) + extern const q31_t twiddleCoef_256_q31[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + extern const q31_t twiddleCoef_512_q31[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) + extern const q31_t twiddleCoef_1024_q31[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + extern const q31_t twiddleCoef_2048_q31[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) + extern const q31_t twiddleCoef_4096_q31[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) + extern const q15_t twiddleCoef_16_q15[24]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + extern const q15_t twiddleCoef_32_q15[48]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) + extern const q15_t twiddleCoef_64_q15[96]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + extern const q15_t twiddleCoef_128_q15[192]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) + extern const q15_t twiddleCoef_256_q15[384]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + extern const q15_t twiddleCoef_512_q15[768]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) + extern const q15_t twiddleCoef_1024_q15[1536]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + extern const q15_t twiddleCoef_2048_q15[3072]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) + extern const q15_t twiddleCoef_4096_q15[6144]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + /* Double Precision Float RFFT twiddles */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32) + extern const uint64_t twiddleCoefF64_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64) + extern const uint64_t twiddleCoefF64_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128) + extern const uint64_t twiddleCoefF64_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256) + extern const uint64_t twiddleCoefF64_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512) + extern const uint64_t twiddleCoefF64_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024) + extern const uint64_t twiddleCoefF64_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048) + extern const uint64_t twiddleCoefF64_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096) + extern const uint64_t twiddleCoefF64_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32) + extern const float32_t twiddleCoef_rfft_32[32]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64) + extern const float32_t twiddleCoef_rfft_64[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128) + extern const float32_t twiddleCoef_rfft_128[128]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256) + extern const float32_t twiddleCoef_rfft_256[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512) + extern const float32_t twiddleCoef_rfft_512[512]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024) + extern const float32_t twiddleCoef_rfft_1024[1024]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048) + extern const float32_t twiddleCoef_rfft_2048[2048]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096) + extern const float32_t twiddleCoef_rfft_4096[4096]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* Double precision floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16) + #define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32) + #define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64) + #define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128) + #define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256) + #define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512) + #define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024) + #define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048) + #define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096) + #define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + /* floating-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16) + #define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) + extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32) + #define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) + extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64) + #define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128) + #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) + extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256) + #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) + extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512) + #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) + extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024) + #define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) + extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048) + #define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) + extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096) + #define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + + /* fixed-point bit reversal tables */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16) + #define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) + extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32) + #define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) + extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64) + #define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) + extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128) + #define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) + extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256) + #define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) + extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512) + #define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) + extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024) + #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) + extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048) + #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) + extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096) + #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) + extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32) + extern const float32_t realCoefA[8192]; + extern const float32_t realCoefB[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31) + extern const q31_t realCoefAQ31[8192]; + extern const q31_t realCoefBQ31[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15) + extern const q15_t realCoefAQ15[8192]; + extern const q15_t realCoefBQ15[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128) + extern const float32_t Weights_128[256]; + extern const float32_t cos_factors_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512) + extern const float32_t Weights_512[1024]; + extern const float32_t cos_factors_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048) + extern const float32_t Weights_2048[4096]; + extern const float32_t cos_factors_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192) + extern const float32_t Weights_8192[16384]; + extern const float32_t cos_factors_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128) + extern const q15_t WeightsQ15_128[256]; + extern const q15_t cos_factorsQ15_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512) + extern const q15_t WeightsQ15_512[1024]; + extern const q15_t cos_factorsQ15_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048) + extern const q15_t WeightsQ15_2048[4096]; + extern const q15_t cos_factorsQ15_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192) + extern const q15_t WeightsQ15_8192[16384]; + extern const q15_t cos_factorsQ15_8192[8192]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128) + extern const q31_t WeightsQ31_128[256]; + extern const q31_t cos_factorsQ31_128[128]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512) + extern const q31_t WeightsQ31_512[1024]; + extern const q31_t cos_factorsQ31_512[512]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048) + extern const q31_t WeightsQ31_2048[4096]; + extern const q31_t cos_factorsQ31_2048[2048]; + #endif + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192) + extern const q31_t WeightsQ31_8192[16384]; + extern const q31_t cos_factorsQ31_8192[8192]; + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */ + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES) + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15) + extern const q15_t armRecipTableQ15[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31) + extern const q31_t armRecipTableQ31[64]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + /* Tables for Fast Math Sine and Cosine */ + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32) + extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31) + extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15) + extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) + extern const q31_t sqrtTable_Q31[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + + #if defined(ARM_MATH_MVEI) + #if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) + extern const q15_t sqrtTable_Q15[256]; + #endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */ + #endif + +#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */ + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + extern const float32_t exp_tab[8]; + extern const float32_t __logf_lut_f32[8]; +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +extern const unsigned char hwLUT[256]; +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#endif /* ARM_COMMON_TABLES_H */ + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_const_structs.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_const_structs.h new file mode 100644 index 0000000000..83984c40cd --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_const_structs.h @@ -0,0 +1,76 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_const_structs.h + * Description: Constant structs that are initialized for user convenience. + * For example, some can be given as arguments to the arm_cfft_f32() function. + * + * $Date: 27. January 2017 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048; + extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096; + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; + extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; + + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; + extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; + +#endif diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_helium_utils.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_helium_utils.h new file mode 100644 index 0000000000..7609d329f0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_helium_utils.h @@ -0,0 +1,348 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_helium_utils.h + * Description: Utility functions for Helium development + * + * $Date: 09. September 2019 + * $Revision: V.1.5.1 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2019 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_UTILS_HELIUM_H_ +#define _ARM_UTILS_HELIUM_H_ + +/*************************************** + +Definitions available for MVEF and MVEI + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) + +#define INACTIVELANE 0 /* inactive lane content */ + + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */ + +/*************************************** + +Definitions available for MVEF only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) + +__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in) +{ + float32_t acc; + + acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) + + vgetq_lane(in, 2) + vgetq_lane(in, 3); + + return acc; +} + +/* newton initial guess */ +#define INVSQRT_MAGIC_F32 0x5f3759df + +#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\ +{ \ + float32x4_t tmp; \ + \ + /* tmp = xhalf * x * x */ \ + tmp = vmulq(xStart, xStart); \ + tmp = vmulq(tmp, xHalf); \ + /* (1.5f - xhalf * x * x) */ \ + tmp = vsubq(vdupq_n_f32(1.5f), tmp); \ + /* x = x*(1.5f-xhalf*x*x); */ \ + invSqrt = vmulq(tmp, xStart); \ +} +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */ + +/*************************************** + +Definitions available for MVEI only + +***************************************/ +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) + + +#include "arm_common_tables.h" + +/* Following functions are used to transpose matrix in f32 and q31 cases */ +__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + static const uint32x4_t vecOffs = { 0, 2, 1, 3 }; + /* + * + * | 0 1 | => | 0 2 | + * | 2 3 | | 1 3 | + * + */ + uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn); + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve( + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + const uint32x4_t vecOffs1 = { 0, 3, 6, 1}; + const uint32x4_t vecOffs2 = { 4, 7, 2, 5}; + /* + * + * | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 | + * | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 | + * | 6 7 8 | | 2 5 8 | (row major) | 8 . . . | + * + */ + uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc); + uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]); + + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1); + vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2); + + pDataDest[8] = pDataSrc[8]; + + return (ARM_MATH_SUCCESS); +} + +__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest) +{ + /* + * 4x4 Matrix transposition + * is 4 x de-interleave operation + * + * 0 1 2 3 0 4 8 12 + * 4 5 6 7 1 5 9 13 + * 8 9 10 11 2 6 10 14 + * 12 13 14 15 3 7 11 15 + */ + + uint32x4x4_t vecIn; + + vecIn = vld4q((uint32_t const *) pDataSrc); + vstrwq(pDataDest, vecIn.val[0]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[1]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[2]); + pDataDest += 4; + vstrwq(pDataDest, vecIn.val[3]); + + return (ARM_MATH_SUCCESS); +} + + +__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve( + uint16_t srcRows, + uint16_t srcCols, + uint32_t * pDataSrc, + uint32_t * pDataDest) +{ + uint32x4_t vecOffs; + uint32_t i; + uint32_t blkCnt; + uint32_t const *pDataC; + uint32_t *pDataDestR; + uint32x4_t vecIn; + + vecOffs = vidupq_u32((uint32_t)0, 1); + vecOffs = vecOffs * srcCols; + + i = srcCols; + do + { + pDataC = (uint32_t const *) pDataSrc; + pDataDestR = pDataDest; + + blkCnt = srcRows >> 2; + while (blkCnt > 0U) + { + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq(pDataDestR, vecIn); + pDataDestR += 4; + pDataC = pDataC + srcCols * 4; + /* + * Decrement the blockSize loop counter + */ + blkCnt--; + } + + /* + * tail + */ + blkCnt = srcRows & 3; + if (blkCnt > 0U) + { + mve_pred16_t p0 = vctp32q(blkCnt); + vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs); + vstrwq_p(pDataDestR, vecIn, p0); + } + + pDataSrc += 1; + pDataDest += srcRows; + } + while (--i); + + return (ARM_MATH_SUCCESS); +} + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE) +__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn) +{ + q63x2_t vecTmpLL; + q31x4_t vecTmp0, vecTmp1; + q31_t scale; + q63_t tmp64; + q31x4_t vecNrm, vecDst, vecIdx, vecSignBits; + + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + /* + * index = in >> 24; + */ + vecIdx = vecNrm >> 24; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + vecTmpLL = vmullbq_int(vecNrm, vecTmp0); + + /* + * scale elements 0, 2 + */ + scale = 26 + (vecSignBits[0] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[0] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[2] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[2] = (q31_t) tmp64; + + vecTmpLL = vmulltq_int(vecNrm, vecTmp0); + + /* + * scale elements 1, 3 + */ + scale = 26 + (vecSignBits[1] >> 1); + tmp64 = asrl(vecTmpLL[0], scale); + vecDst[1] = (q31_t) tmp64; + + scale = 26 + (vecSignBits[3] >> 1); + tmp64 = asrl(vecTmpLL[1], scale); + vecDst[3] = (q31_t) tmp64; + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0)); + + return vecDst; +} +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE) +__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn) +{ + q31x4_t vecTmpLev, vecTmpLodd, vecSignL; + q15x8_t vecTmp0, vecTmp1; + q15x8_t vecNrm, vecDst, vecIdx, vecSignBits; + + vecDst = vuninitializedq_s16(); + + vecSignBits = vclsq(vecIn); + vecSignBits = vbicq(vecSignBits, 1); + /* + * in = in << no_of_sign_bits; + */ + vecNrm = vshlq(vecIn, vecSignBits); + + vecIdx = vecNrm >> 8; + vecIdx = vecIdx << 1; + + vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecIdx = vecIdx + 1; + + vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, vecIdx); + + vecTmp1 = vqrdmulhq(vecTmp1, vecNrm); + vecTmp0 = vecTmp0 - vecTmp1; + vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0); + vecTmp1 = vqrdmulhq(vecNrm, vecTmp1); + vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1; + vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1); + + vecSignBits = vecSignBits >> 1; + + vecTmpLev = vmullbq_int(vecNrm, vecTmp0); + vecTmpLodd = vmulltq_int(vecNrm, vecTmp0); + + vecTmp0 = vecSignBits + 10; + /* + * negate sign to apply register based vshl + */ + vecTmp0 = -vecTmp0; + + /* + * shift even elements + */ + vecSignL = vmovlbq(vecTmp0); + vecTmpLev = vshlq(vecTmpLev, vecSignL); + /* + * shift odd elements + */ + vecSignL = vmovltq(vecTmp0); + vecTmpLodd = vshlq(vecTmpLodd, vecSignL); + /* + * merge and narrow odd and even parts + */ + vecDst = vmovnbq_s32(vecDst, vecTmpLev); + vecDst = vmovntq_s32(vecDst, vecTmpLodd); + /* + * set negative values to 0 + */ + vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0)); + + return vecDst; +} +#endif + +#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */ + +#endif diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_math.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_math.h new file mode 100644 index 0000000000..48bee62cd9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_math.h @@ -0,0 +1,8970 @@ +/****************************************************************************** + * @file arm_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 18. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * ------------ + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M and Cortex-A processor + * based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filtering functions + * - Matrix functions + * - Transform functions + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * - Support Vector Machine functions (SVM) + * - Bayes classifier functions + * - Distance functions + * + * The library has generally separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * ------------ + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * + * Here is the list of pre-built libraries : + * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) + * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) + * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) + * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) + * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) + * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) + * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) + * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) + * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) + * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) + * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) + * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) + * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) + * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) + * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) + * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) + * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) + * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) + * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * + * + * Examples + * -------- + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * ------------ + * + * The library is now tested on Fast Models building with cmake. + * Core M0, M7, A5 are tested. + * + * + * + * Building the Library + * ------------ + * + * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP\\Projects\\ARM folder. + * - arm_cortexM_math.uvprojx + * + * + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. + * + * There is also a work in progress cmake build. The README file is giving more details. + * + * Preprocessor Macros + * ------------ + * + * Each library project have different preprocessor macros. + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_LOOPUNROLL: + * + * Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions + * + * - ARM_MATH_NEON: + * + * Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions. + * It is not enabled by default when Neon is available because performances are + * dependent on the compiler and target architecture. + * + * - ARM_MATH_NEON_EXPERIMENTAL: + * + * Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of + * of some DSP functions. Experimental Neon versions currently do not have better + * performances than the scalar versions. + * + * - ARM_MATH_HELIUM: + * + * It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_FLOAT16. + * + * - ARM_MATH_MVEF: + * + * Select Helium versions of the f32 algorithms. + * It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI. + * + * - ARM_MATH_MVEI: + * + * Select Helium versions of the int and fixed point algorithms. + * + * - ARM_MATH_FLOAT16: + * + * Float16 implementations of some algorithms (Requires MVE extension). + * + *
    + * CMSIS-DSP in ARM::CMSIS Pack + * ----------------------------- + * + * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: + * |File/Folder |Content | + * |---------------------------------|------------------------------------------------------------------------| + * |\b CMSIS\\Documentation\\DSP | This documentation | + * |\b CMSIS\\DSP\\DSP_Lib_TestSuite | DSP_Lib test suite | + * |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions | + * |\b CMSIS\\DSP\\Include | DSP_Lib include files | + * |\b CMSIS\\DSP\\Lib | DSP_Lib binaries | + * |\b CMSIS\\DSP\\Projects | Projects to rebuild DSP_Lib binaries | + * |\b CMSIS\\DSP\\Source | DSP_Lib source files | + * + *
    + * Revision History of CMSIS-DSP + * ------------ + * Please refer to \ref ChangeLog_pg. + */ + + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
    + * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
    + *     pData[i*numCols + j]
+ *
    + * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to \ref arm_mat_init_f32(), \ref arm_mat_init_q31() and \ref arm_mat_init_q15() + * for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
    + * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
    + *     ARM_MATH_SIZE_MISMATCH
+ *
    + * Otherwise the functions return + * 
    + *     ARM_MATH_SUCCESS
+ *
    + * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
    + *     ARM_MATH_MATRIX_CHECK
+ *
    + * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ + +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ + +/** + * @defgroup groupSVM SVM Functions + * This set of functions is implementing SVM classification on 2 classes. + * The training must be done from scikit-learn. The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/SVM.py + * + * If more than 2 classes are needed, the functions in this folder + * will have to be used, as building blocks, to do multi-class classification. + * + * No multi-class classification is provided in this SVM folder. + * + */ + + +/** + * @defgroup groupBayes Bayesian estimators + * + * Implement the naive gaussian Bayes estimator. + * The training must be done from scikit-learn. + * + * The parameters can be easily + * generated from the scikit-learn object. Some examples are given in + * DSP/Testing/PatternGeneration/Bayes.py + */ + +/** + * @defgroup groupDistance Distance functions + * + * Distance functions for use with clustering algorithms. + * There are distance functions for float vectors and boolean vectors. + * + */ + + +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wsign-conversion" + #pragma GCC diagnostic ignored "-Wconversion" + #pragma GCC diagnostic ignored "-Wunused-parameter" + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + + +/* Included for instrinsics definitions */ +#if defined (_MSC_VER ) +#include +#define __STATIC_FORCEINLINE static __forceinline +#define __STATIC_INLINE static __inline +#define __ALIGNED(x) __declspec(align(x)) + +#elif defined (__GNUC_PYTHON__) +#include +#define __ALIGNED(x) __attribute__((aligned(x))) +#define __STATIC_FORCEINLINE static __attribute__((inline)) +#define __STATIC_INLINE static __attribute__((inline)) +#pragma GCC diagnostic ignored "-Wunused-function" +#pragma GCC diagnostic ignored "-Wattributes" + +#else +#include "cmsis_compiler.h" +#endif + + + +#include +#include +#include +#include + + +#define F64_MAX ((float64_t)DBL_MAX) +#define F32_MAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MAX ((float16_t)FLT_MAX) +#endif + +#define F64_MIN (-DBL_MAX) +#define F32_MIN (-FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_MIN (-(float16_t)FLT_MAX) +#endif + +#define F64_ABSMAX ((float64_t)DBL_MAX) +#define F32_ABSMAX ((float32_t)FLT_MAX) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMAX ((float16_t)FLT_MAX) +#endif + +#define F64_ABSMIN ((float64_t)0.0) +#define F32_ABSMIN ((float32_t)0.0) + +#if defined(ARM_MATH_FLOAT16) +#define F16_ABSMIN ((float16_t)0.0) +#endif + +#define Q31_MAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_MAX ((q15_t)(0x7FFF)) +#define Q7_MAX ((q7_t)(0x7F)) +#define Q31_MIN ((q31_t)(0x80000000L)) +#define Q15_MIN ((q15_t)(0x8000)) +#define Q7_MIN ((q7_t)(0x80)) + +#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL)) +#define Q15_ABSMAX ((q15_t)(0x7FFF)) +#define Q7_ABSMAX ((q7_t)(0x7F)) +#define Q31_ABSMIN ((q31_t)0) +#define Q15_ABSMIN ((q15_t)0) +#define Q7_ABSMIN ((q7_t)0) + +/* evaluate ARM DSP feature */ +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + #define ARM_MATH_DSP 1 +#endif + +#if defined(ARM_MATH_NEON) +#include +#endif + +#if defined (ARM_MATH_HELIUM) + #define ARM_MATH_MVEF + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_MVEF) + #define ARM_MATH_MVEI + #define ARM_MATH_FLOAT16 +#endif + +#if defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) +#include +#endif + + + /** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 ((q31_t)(0x100)) +#define DELTA_Q15 ((q15_t)0x5) +#define INDEX_MASK 0x0000003F +#ifndef PI + #define PI 3.14159265358979f +#endif + + /** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define FAST_MATH_TABLE_SIZE 512 +#define FAST_MATH_Q31_SHIFT (32 - 10) +#define FAST_MATH_Q15_SHIFT (16 - 10) +#define CONTROLLER_Q31_SHIFT (32 - 9) +#define TABLE_SPACING_Q31 0x400000 +#define TABLE_SPACING_Q15 0x80 + + /** + * @brief Macros required for SINE and COSINE Controller functions + */ + /* 1.31(q31) Fixed value of 2/360 */ + /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + + /** + * @brief Macros for complex numbers + */ + + /* Dimension C vector space */ + #define CMPLX_DIM 2 + + /** + * @brief Error status returned by some functions in the library. + */ + + typedef enum + { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ + } arm_status; + + /** + * @brief 8-bit fractional data type in 1.7 format. + */ + typedef int8_t q7_t; + + /** + * @brief 16-bit fractional data type in 1.15 format. + */ + typedef int16_t q15_t; + + /** + * @brief 32-bit fractional data type in 1.31 format. + */ + typedef int32_t q31_t; + + /** + * @brief 64-bit fractional data type in 1.63 format. + */ + typedef int64_t q63_t; + + /** + * @brief 32-bit floating-point type definition. + */ + typedef float float32_t; + + /** + * @brief 64-bit floating-point type definition. + */ + typedef double float64_t; + + /** + * @brief vector types + */ +#if defined(ARM_MATH_NEON) || defined (ARM_MATH_MVEI) + /** + * @brief 64-bit fractional 128-bit vector data type in 1.63 format + */ + typedef int64x2_t q63x2_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 1.31 format. + */ + typedef int32x4_t q31x4_t; + + /** + * @brief 16-bit fractional 128-bit vector data type with 16-bit alignement in 1.15 format. + */ + typedef __ALIGNED(2) int16x8_t q15x8_t; + + /** + * @brief 8-bit fractional 128-bit vector data type with 8-bit alignement in 1.7 format. + */ + typedef __ALIGNED(1) int8x16_t q7x16_t; + + /** + * @brief 32-bit fractional 128-bit vector pair data type in 1.31 format. + */ + typedef int32x4x2_t q31x4x2_t; + + /** + * @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format. + */ + typedef int32x4x4_t q31x4x4_t; + + /** + * @brief 16-bit fractional 128-bit vector pair data type in 1.15 format. + */ + typedef int16x8x2_t q15x8x2_t; + + /** + * @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format. + */ + typedef int16x8x4_t q15x8x4_t; + + /** + * @brief 8-bit fractional 128-bit vector pair data type in 1.7 format. + */ + typedef int8x16x2_t q7x16x2_t; + + /** + * @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format. + */ + typedef int8x16x4_t q7x16x4_t; + + /** + * @brief 32-bit fractional data type in 9.23 format. + */ + typedef int32_t q23_t; + + /** + * @brief 32-bit fractional 128-bit vector data type in 9.23 format. + */ + typedef int32x4_t q23x4_t; + + /** + * @brief 64-bit status 128-bit vector data type. + */ + typedef int64x2_t status64x2_t; + + /** + * @brief 32-bit status 128-bit vector data type. + */ + typedef int32x4_t status32x4_t; + + /** + * @brief 16-bit status 128-bit vector data type. + */ + typedef int16x8_t status16x8_t; + + /** + * @brief 8-bit status 128-bit vector data type. + */ + typedef int8x16_t status8x16_t; + + +#endif + +#if defined(ARM_MATH_NEON) || defined(ARM_MATH_MVEF) /* floating point vector*/ + /** + * @brief 32-bit floating-point 128-bit vector type + */ + typedef float32x4_t f32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector data type + */ + typedef __ALIGNED(2) float16x8_t f16x8_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector pair data type + */ + typedef float32x4x2_t f32x4x2_t; + + /** + * @brief 32-bit floating-point 128-bit vector quadruplet data type + */ + typedef float32x4x4_t f32x4x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector pair data type + */ + typedef float16x8x2_t f16x8x2_t; + + /** + * @brief 16-bit floating-point 128-bit vector quadruplet data type + */ + typedef float16x8x4_t f16x8x4_t; +#endif + + /** + * @brief 32-bit ubiquitous 128-bit vector data type + */ + typedef union _any32x4_t + { + float32x4_t f; + int32x4_t i; + } any32x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 128-bit vector data type + */ + typedef union _any16x8_t + { + float16x8_t f; + int16x8_t i; + } any16x8_t; +#endif + +#endif + +#if defined(ARM_MATH_NEON) + /** + * @brief 32-bit fractional 64-bit vector data type in 1.31 format. + */ + typedef int32x2_t q31x2_t; + + /** + * @brief 16-bit fractional 64-bit vector data type in 1.15 format. + */ + typedef __ALIGNED(2) int16x4_t q15x4_t; + + /** + * @brief 8-bit fractional 64-bit vector data type in 1.7 format. + */ + typedef __ALIGNED(1) int8x8_t q7x8_t; + + /** + * @brief 32-bit float 64-bit vector data type. + */ + typedef float32x2_t f32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit float 64-bit vector data type. + */ + typedef __ALIGNED(2) float16x4_t f16x4_t; +#endif + + /** + * @brief 32-bit floating-point 128-bit vector triplet data type + */ + typedef float32x4x3_t f32x4x3_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 128-bit vector triplet data type + */ + typedef float16x8x3_t f16x8x3_t; +#endif + + /** + * @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format + */ + typedef int32x4x3_t q31x4x3_t; + + /** + * @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format + */ + typedef int16x8x3_t q15x8x3_t; + + /** + * @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format + */ + typedef int8x16x3_t q7x16x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector pair data type + */ + typedef float32x2x2_t f32x2x2_t; + + /** + * @brief 32-bit floating-point 64-bit vector triplet data type + */ + typedef float32x2x3_t f32x2x3_t; + + /** + * @brief 32-bit floating-point 64-bit vector quadruplet data type + */ + typedef float32x2x4_t f32x2x4_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit floating-point 64-bit vector pair data type + */ + typedef float16x4x2_t f16x4x2_t; + + /** + * @brief 16-bit floating-point 64-bit vector triplet data type + */ + typedef float16x4x3_t f16x4x3_t; + + /** + * @brief 16-bit floating-point 64-bit vector quadruplet data type + */ + typedef float16x4x4_t f16x4x4_t; +#endif + + /** + * @brief 32-bit fractional 64-bit vector pair data type in 1.31 format + */ + typedef int32x2x2_t q31x2x2_t; + + /** + * @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format + */ + typedef int32x2x3_t q31x2x3_t; + + /** + * @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format + */ + typedef int32x4x3_t q31x2x4_t; + + /** + * @brief 16-bit fractional 64-bit vector pair data type in 1.15 format + */ + typedef int16x4x2_t q15x4x2_t; + + /** + * @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format + */ + typedef int16x4x2_t q15x4x3_t; + + /** + * @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format + */ + typedef int16x4x3_t q15x4x4_t; + + /** + * @brief 8-bit fractional 64-bit vector pair data type in 1.7 format + */ + typedef int8x8x2_t q7x8x2_t; + + /** + * @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format + */ + typedef int8x8x3_t q7x8x3_t; + + /** + * @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format + */ + typedef int8x8x4_t q7x8x4_t; + + /** + * @brief 32-bit ubiquitous 64-bit vector data type + */ + typedef union _any32x2_t + { + float32x2_t f; + int32x2_t i; + } any32x2_t; + +#if defined(ARM_MATH_FLOAT16) + /** + * @brief 16-bit ubiquitous 64-bit vector data type + */ + typedef union _any16x4_t + { + float16x4_t f; + int16x4_t i; + } any16x4_t; +#endif + + /** + * @brief 32-bit status 64-bit vector data type. + */ + typedef int32x4_t status32x2_t; + + /** + * @brief 16-bit status 64-bit vector data type. + */ + typedef int16x8_t status16x4_t; + + /** + * @brief 8-bit status 64-bit vector data type. + */ + typedef int8x16_t status8x8_t; + +#endif + + + +/** + @brief definition to read/write two 16 bit values. + @deprecated + */ +#if defined ( __CC_ARM ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define __SIMD32_TYPE int32_t +#elif defined ( __GNUC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __ICCARM__ ) + #define __SIMD32_TYPE int32_t __packed +#elif defined ( __TI_ARM__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __CSMC__ ) + #define __SIMD32_TYPE int32_t +#elif defined ( __TASKING__ ) + #define __SIMD32_TYPE __un(aligned) int32_t +#elif defined(_MSC_VER ) + #define __SIMD32_TYPE int32_t +#else + #error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr)) +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr)) +#define __SIMD64(addr) (*( int64_t **) & (addr)) + +#define STEP(x) (x) <= 0 ? 0 : 1 +#define SQ(x) ((x) * (x)) + +/* SIMD replacement */ + + +/** + @brief Read 2 Q15 from Q15 pointer. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2 ( + q15_t * pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, pQ15, 4); +#else + val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ; +#endif + + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_ia ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 += 2; + return (val); +} + +/** + @brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards. + @param[in] pQ15 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q15x2_da ( + q15_t ** pQ15) +{ + q31_t val; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ15, 4); +#else + val = ((*pQ15)[1] << 16) | ((*pQ15)[0] & 0x0FFFF); +#endif + + *pQ15 -= 2; + return (val); +} + +/** + @brief Write 2 Q15 to Q15 pointer and increment pointer afterwards. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2_ia ( + q15_t ** pQ15, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ15, &val, 4); +#else + (*pQ15)[0] = (val & 0x0FFFF); + (*pQ15)[1] = (val >> 16) & 0x0FFFF; +#endif + + *pQ15 += 2; +} + +/** + @brief Write 2 Q15 to Q15 pointer. + @param[in] pQ15 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q15x2 ( + q15_t * pQ15, + q31_t value) +{ + q31_t val = value; + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (pQ15, &val, 4); +#else + pQ15[0] = val & 0x0FFFF; + pQ15[1] = val >> 16; +#endif +} + + +/** + @brief Read 4 Q7 from Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_ia ( + q7_t ** pQ7) +{ + q31_t val; + + +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val =(((*pQ7)[3] & 0x0FF) << 24) | (((*pQ7)[2] & 0x0FF) << 16) | (((*pQ7)[1] & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + + *pQ7 += 4; + + return (val); +} + +/** + @brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards. + @param[in] pQ7 points to input value + @return Q31 value + */ +__STATIC_FORCEINLINE q31_t read_q7x4_da ( + q7_t ** pQ7) +{ + q31_t val; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (&val, *pQ7, 4); +#else + val = ((((*pQ7)[3]) & 0x0FF) << 24) | ((((*pQ7)[2]) & 0x0FF) << 16) | ((((*pQ7)[1]) & 0x0FF) << 8) | ((*pQ7)[0] & 0x0FF); +#endif + *pQ7 -= 4; + + return (val); +} + +/** + @brief Write 4 Q7 to Q7 pointer and increment pointer afterwards. + @param[in] pQ7 points to input value + @param[in] value Q31 value + @return none + */ +__STATIC_FORCEINLINE void write_q7x4_ia ( + q7_t ** pQ7, + q31_t value) +{ + q31_t val = value; +#ifdef __ARM_FEATURE_UNALIGNED + memcpy (*pQ7, &val, 4); +#else + (*pQ7)[0] = val & 0x0FF; + (*pQ7)[1] = (val >> 8) & 0x0FF; + (*pQ7)[2] = (val >> 16) & 0x0FF; + (*pQ7)[3] = (val >> 24) & 0x0FF; + +#endif + *pQ7 += 4; +} + +/* + +Normally those kind of definitions are in a compiler file +in Core or Core_A. + +But for MSVC compiler it is a bit special. The goal is very specific +to CMSIS-DSP and only to allow the use of this library from other +systems like Python or Matlab. + +MSVC is not going to be used to cross-compile to ARM. So, having a MSVC +compiler file in Core or Core_A would not make sense. + +*/ +#if defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#ifndef ARM_MATH_DSP + /** + * @brief definition to pack two 16 bit values. + */ + #define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) + #define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) +#endif + + /** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) +#endif + + + /** + * @brief Clips Q63 to Q31 values. + */ + __STATIC_FORCEINLINE q31_t clip_q63_to_q31( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; + } + + /** + * @brief Clips Q63 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q63_to_q15( + q63_t x) + { + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); + } + + /** + * @brief Clips Q31 to Q7 values. + */ + __STATIC_FORCEINLINE q7_t clip_q31_to_q7( + q31_t x) + { + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; + } + + /** + * @brief Clips Q31 to Q15 values. + */ + __STATIC_FORCEINLINE q15_t clip_q31_to_q15( + q31_t x) + { + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; + } + + /** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + __STATIC_FORCEINLINE q63_t mult32x64( + q63_t x, + q31_t y) + { + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y) ) ); + } + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q31( + q31_t in, + q31_t * dst, + const q31_t * pRecipTable) + { + q31_t out; + uint32_t tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) + { + signBits = ((uint32_t) (__CLZ( in) - 1)); + } + else + { + signBits = ((uint32_t) (__CLZ(-in) - 1)); + } + + /* Convert input sample to 1.31 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q63_t) in * out) >> 31); + tempVal = 0x7FFFFFFFu - tempVal; + /* 1.31 with exp 1 */ + /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ + out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1U); + } + + + /** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ + __STATIC_FORCEINLINE uint32_t arm_recip_q15( + q15_t in, + q15_t * dst, + const q15_t * pRecipTable) + { + q15_t out = 0; + uint32_t tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) + { + signBits = ((uint32_t)(__CLZ( in) - 17)); + } + else + { + signBits = ((uint32_t)(__CLZ(-in) - 17)); + } + + /* Convert input sample to 1.15 format */ + in = (in << signBits); + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 8); + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0U; i < 2U; i++) + { + tempVal = (uint32_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFFu - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); + } + +/** + * @brief Integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32_t arm_exponent_f32(float32_t x, int32_t nb) +{ + float32_t r = x; + nb --; + while(nb > 0) + { + r = r * x; + nb--; + } + return(r); +} + +/** + * @brief 64-bit to 32-bit unsigned normalization + * @param[in] in is input unsigned long long value + * @param[out] normalized is the 32-bit normalized value + * @param[out] norm is norm scale + */ +__STATIC_INLINE void arm_norm_64_to_32u(uint64_t in, int32_t * normalized, int32_t *norm) +{ + int32_t n1; + int32_t hi = (int32_t) (in >> 32); + int32_t lo = (int32_t) ((in << 32) >> 32); + + n1 = __CLZ(hi) - 32; + if (!n1) + { + /* + * input fits in 32-bit + */ + n1 = __CLZ(lo); + if (!n1) + { + /* + * MSB set, need to scale down by 1 + */ + *norm = -1; + *normalized = (((uint32_t) lo) >> 1); + } else + { + if (n1 == 32) + { + /* + * input is zero + */ + *norm = 0; + *normalized = 0; + } else + { + /* + * 32-bit normalization + */ + *norm = n1 - 1; + *normalized = lo << *norm; + } + } + } else + { + /* + * input fits in 64-bit + */ + n1 = 1 - n1; + *norm = -n1; + /* + * 64 bit normalization + */ + *normalized = (((uint32_t) lo) >> n1) | (hi << (32 - n1)); + } +} + +__STATIC_INLINE q31_t arm_div_q63_to_q31(q63_t num, q31_t den) +{ + q31_t result; + uint64_t absNum; + int32_t normalized; + int32_t norm; + + /* + * if sum fits in 32bits + * avoid costly 64-bit division + */ + absNum = num > 0 ? num : -num; + arm_norm_64_to_32u(absNum, &normalized, &norm); + if (norm > 0) + /* + * 32-bit division + */ + result = (q31_t) num / den; + else + /* + * 64-bit division + */ + result = (q31_t) (num / den); + + return result; +} + + +/* + * @brief C custom defined intrinsic functions + */ +#if !defined (ARM_MATH_DSP) + + /* + * @brief C custom defined QADD8 + */ + __STATIC_FORCEINLINE uint32_t __QADD8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QSUB8 + */ + __STATIC_FORCEINLINE uint32_t __QSUB8( + uint32_t x, + uint32_t y) + { + q31_t r, s, t, u; + + r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; + s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; + t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; + u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; + + return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); + } + + + /* + * @brief C custom defined QADD16 + */ + __STATIC_FORCEINLINE uint32_t __QADD16( + uint32_t x, + uint32_t y) + { +/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ + q31_t r = 0, s = 0; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHADD16 + */ + __STATIC_FORCEINLINE uint32_t __SHADD16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSUB16 + */ + __STATIC_FORCEINLINE uint32_t __QSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSUB16 + */ + __STATIC_FORCEINLINE uint32_t __SHSUB16( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QASX + */ + __STATIC_FORCEINLINE uint32_t __QASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHASX + */ + __STATIC_FORCEINLINE uint32_t __SHASX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined QSAX + */ + __STATIC_FORCEINLINE uint32_t __QSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; + s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SHSAX + */ + __STATIC_FORCEINLINE uint32_t __SHSAX( + uint32_t x, + uint32_t y) + { + q31_t r, s; + + r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; + s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; + + return ((uint32_t)((s << 16) | (r ))); + } + + + /* + * @brief C custom defined SMUSDX + */ + __STATIC_FORCEINLINE uint32_t __SMUSDX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + /* + * @brief C custom defined SMUADX + */ + __STATIC_FORCEINLINE uint32_t __SMUADX( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); + } + + + /* + * @brief C custom defined QADD + */ + __STATIC_FORCEINLINE int32_t __QADD( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); + } + + + /* + * @brief C custom defined QSUB + */ + __STATIC_FORCEINLINE int32_t __QSUB( + int32_t x, + int32_t y) + { + return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); + } + + + /* + * @brief C custom defined SMLAD + */ + __STATIC_FORCEINLINE uint32_t __SMLAD( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLADX + */ + __STATIC_FORCEINLINE uint32_t __SMLADX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLSDX + */ + __STATIC_FORCEINLINE uint32_t __SMLSDX( + uint32_t x, + uint32_t y, + uint32_t sum) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q31_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALD + */ + __STATIC_FORCEINLINE uint64_t __SMLALD( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMLALDX + */ + __STATIC_FORCEINLINE uint64_t __SMLALDX( + uint32_t x, + uint32_t y, + uint64_t sum) + { +/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ + return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + + ( ((q63_t)sum ) ) )); + } + + + /* + * @brief C custom defined SMUAD + */ + __STATIC_FORCEINLINE uint32_t __SMUAD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SMUSD + */ + __STATIC_FORCEINLINE uint32_t __SMUSD( + uint32_t x, + uint32_t y) + { + return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - + ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); + } + + + /* + * @brief C custom defined SXTB16 + */ + __STATIC_FORCEINLINE uint32_t __SXTB16( + uint32_t x) + { + return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | + ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); + } + + /* + * @brief C custom defined SMMLA + */ + __STATIC_FORCEINLINE int32_t __SMMLA( + int32_t x, + int32_t y, + int32_t sum) + { + return (sum + (int32_t) (((int64_t) x * y) >> 32)); + } + +#endif /* !defined (ARM_MATH_DSP) */ + + + /** + * @brief Instance structure for the Q7 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q7; + + /** + * @brief Instance structure for the Q15 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + } arm_fir_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + } arm_fir_instance_f32; + + /** + * @brief Processing function for the Q7 FIR filter. + * @param[in] S points to an instance of the Q7 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q7( + const arm_fir_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + */ + void arm_fir_init_q7( + arm_fir_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q15 FIR filter. + * @param[in] S points to an instance of the Q15 FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q15 FIR filter (fast version). + * @param[in] S points to an instance of the Q15 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q15( + const arm_fir_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns either + * ARM_MATH_SUCCESS if initialization was successful or + * ARM_MATH_ARGUMENT_ERROR if numTaps is not a supported value. + */ + arm_status arm_fir_init_q15( + arm_fir_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR filter. + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the fast Q31 FIR filter (fast version). + * @param[in] S points to an instance of the Q31 FIR filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_fast_q31( + const arm_fir_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_q31( + arm_fir_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + /** + * @brief Processing function for the floating-point FIR filter. + * @param[in] S points to an instance of the floating-point FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_f32( + const arm_fir_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + */ + void arm_fir_init_f32( + arm_fir_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + /** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ + typedef struct + { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q15; + + /** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + } arm_biquad_casd_df1_inst_q31; + + /** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ + typedef struct + { + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_casd_df1_inst_f32; + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + /** + * @brief Instance structure for the modified Biquad coefs required by vectorized code. + */ + typedef struct + { + float32_t coeffs[8][4]; /**< Points to the array of modified coefficients. The array is of length 32. There is one per stage */ + } arm_biquad_mod_coef_f32; +#endif + + /** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15 * S, + uint8_t numStages, + const q15_t * pCoeffs, + q15_t * pState, + int8_t postShift); + + /** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q31_t * pState, + int8_t postShift); + + /** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pCoeffsMod points to the modified filter coefficients (only MVE version). + * @param[in] pState points to the state buffer. + */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + void arm_biquad_cascade_df1_mve_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + arm_biquad_mod_coef_f32 * pCoeffsMod, + float32_t * pState); +#endif + + void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise AND of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_and_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise OR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_or_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u16( + const uint16_t * pSrc, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u32( + const uint32_t * pSrc, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise NOT of a fixed-point vector. + * @param[in] pSrc points to input vector + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_not_u8( + const uint8_t * pSrc, + uint8_t * pDst, + uint32_t blockSize); + +/** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u16( + const uint16_t * pSrcA, + const uint16_t * pSrcB, + uint16_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u32( + const uint32_t * pSrcA, + const uint32_t * pSrcB, + uint32_t * pDst, + uint32_t blockSize); + + /** + * @brief Compute the logical bitwise XOR of two fixed-point vectors. + * @param[in] pSrcA points to input vector A + * @param[in] pSrcB points to input vector B + * @param[out] pDst points to output vector + * @param[in] blockSize number of samples in each vector + * @return none + */ + void arm_xor_u8( + const uint8_t * pSrcA, + const uint8_t * pSrcB, + uint8_t * pDst, + uint32_t blockSize); + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_BITONIC = 0, + /**< Bitonic sort */ + ARM_SORT_BUBBLE = 1, + /**< Bubble sort */ + ARM_SORT_HEAP = 2, + /**< Heap sort */ + ARM_SORT_INSERTION = 3, + /**< Insertion sort */ + ARM_SORT_QUICK = 4, + /**< Quick sort */ + ARM_SORT_SELECTION = 5 + /**< Selection sort */ + } arm_sort_alg; + + /** + * @brief Struct for specifying sorting algorithm + */ + typedef enum + { + ARM_SORT_DESCENDING = 0, + /**< Descending order (9 to 0) */ + ARM_SORT_ASCENDING = 1 + /**< Ascending order (0 to 9) */ + } arm_sort_dir; + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_alg alg; /**< Sorting algorithm selected */ + arm_sort_dir dir; /**< Sorting order (direction) */ + } arm_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_sort_f32( + const arm_sort_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] alg Selected algorithm. + * @param[in] dir Sorting order. + */ + void arm_sort_init_f32( + arm_sort_instance_f32 * S, + arm_sort_alg alg, + arm_sort_dir dir); + + /** + * @brief Instance structure for the sorting algorithms. + */ + typedef struct + { + arm_sort_dir dir; /**< Sorting order (direction) */ + float32_t * buffer; /**< Working buffer */ + } arm_merge_sort_instance_f32; + + /** + * @param[in] S points to an instance of the sorting structure. + * @param[in,out] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_merge_sort_f32( + const arm_merge_sort_instance_f32 * S, + float32_t *pSrc, + float32_t *pDst, + uint32_t blockSize); + + /** + * @param[in,out] S points to an instance of the sorting structure. + * @param[in] dir Sorting order. + * @param[in] buffer Working buffer. + */ + void arm_merge_sort_init_f32( + arm_merge_sort_instance_f32 * S, + arm_sort_dir dir, + float32_t * buffer); + + /** + * @brief Struct for specifying cubic spline type + */ + typedef enum + { + ARM_SPLINE_NATURAL = 0, /**< Natural spline */ + ARM_SPLINE_PARABOLIC_RUNOUT = 1 /**< Parabolic runout spline */ + } arm_spline_type; + + /** + * @brief Instance structure for the floating-point cubic spline interpolation. + */ + typedef struct + { + arm_spline_type type; /**< Type (boundary conditions) */ + const float32_t * x; /**< x values */ + const float32_t * y; /**< y values */ + uint32_t n_x; /**< Number of known data points */ + float32_t * coeffs; /**< Coefficients buffer (b,c, and d) */ + } arm_spline_instance_f32; + + /** + * @brief Processing function for the floating-point cubic spline interpolation. + * @param[in] S points to an instance of the floating-point spline structure. + * @param[in] xq points to the x values ot the interpolated data points. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples of output data. + */ + void arm_spline_f32( + arm_spline_instance_f32 * S, + const float32_t * xq, + float32_t * pDst, + uint32_t blockSize); + + /** + * @brief Initialization function for the floating-point cubic spline interpolation. + * @param[in,out] S points to an instance of the floating-point spline structure. + * @param[in] type type of cubic spline interpolation (boundary conditions) + * @param[in] x points to the x values of the known data points. + * @param[in] y points to the y values of the known data points. + * @param[in] n number of known data points. + * @param[in] coeffs coefficients array for b, c, and d + * @param[in] tempBuffer buffer array for internal computations + */ + void arm_spline_init_f32( + arm_spline_instance_f32 * S, + arm_spline_type type, + const float32_t * x, + const float32_t * y, + uint32_t n, + float32_t * coeffs, + float32_t * tempBuffer); + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f32; + + /** + * @brief Instance structure for the floating-point matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float64_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_f64; + + /** + * @brief Instance structure for the Q15 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q15; + + /** + * @brief Instance structure for the Q31 matrix structure. + */ + typedef struct + { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + } arm_matrix_instance_q31; + + /** + * @brief Floating-point matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix addition. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pScratch); + + /** + * @brief Q31, complex, matrix multiplication. + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_cmplx_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32 * pSrc, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15 * pSrc, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix transpose. + * @param[in] pSrc points to the input matrix + * @param[out] pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31 * pSrc, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @param[in] pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst, + q15_t * pState); + + /** + * @brief Q31 matrix multiplication + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32 * pSrcA, + const arm_matrix_instance_f32 * pSrcB, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15 * pSrcA, + const arm_matrix_instance_q15 * pSrcB, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix subtraction + * @param[in] pSrcA points to the first input matrix structure + * @param[in] pSrcB points to the second input matrix structure + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31 * pSrcA, + const arm_matrix_instance_q31 * pSrcB, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Floating-point matrix scaling. + * @param[in] pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32 * pSrc, + float32_t scale, + arm_matrix_instance_f32 * pDst); + + /** + * @brief Q15 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15 * pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15 * pDst); + + /** + * @brief Q31 matrix scaling. + * @param[in] pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31 * pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31 * pDst); + + /** + * @brief Q31 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q31( + arm_matrix_instance_q31 * S, + uint16_t nRows, + uint16_t nColumns, + q31_t * pData); + + /** + * @brief Q15 matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_q15( + arm_matrix_instance_q15 * S, + uint16_t nRows, + uint16_t nColumns, + q15_t * pData); + + /** + * @brief Floating-point matrix initialization. + * @param[in,out] S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] pData points to the matrix data array. + */ +void arm_mat_init_f32( + arm_matrix_instance_f32 * S, + uint16_t nRows, + uint16_t nColumns, + float32_t * pData); + + + /** + * @brief Instance structure for the Q15 PID Control. + */ + typedef struct + { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#if !defined (ARM_MATH_DSP) + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q15; + + /** + * @brief Instance structure for the Q31 PID Control. + */ + typedef struct + { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + } arm_pid_instance_q31; + + /** + * @brief Instance structure for the floating-point PID Control. + */ + typedef struct + { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ + } arm_pid_instance_f32; + + + + /** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_f32( + arm_pid_instance_f32 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + */ + void arm_pid_reset_f32( + arm_pid_instance_f32 * S); + + + /** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q31( + arm_pid_instance_q31 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] S points to an instance of the Q31 PID Control structure + */ + + void arm_pid_reset_q31( + arm_pid_instance_q31 * S); + + + /** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + */ + void arm_pid_init_q15( + arm_pid_instance_q15 * S, + int32_t resetStateFlag); + + + /** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] S points to an instance of the q15 PID Control structure + */ + void arm_pid_reset_q15( + arm_pid_instance_q15 * S); + + + /** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ + typedef struct + { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ + } arm_linear_interp_instance_f32; + + /** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_f32; + + /** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q31; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q15; + + /** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + typedef struct + { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ + } arm_bilinear_interp_instance_q7; + + + /** + * @brief Q7 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector multiplication. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_mult_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15 * S, + q15_t * pSrc); + + + /** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q15; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15 * S, + q15_t * pSrc); + + /** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix2_instance_q31; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31 * S, + q31_t * pSrc); + + /** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + } arm_cfft_radix4_instance_q31; + +/* Deprecated */ + void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31 * S, + q31_t * pSrc); + +/* Deprecated */ + arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix2_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ + } arm_cfft_radix4_instance_f32; + +/* Deprecated */ + arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32 * S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ + void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32 * S, + float32_t * pSrc); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q15_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q15_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q15_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q15; + +arm_status arm_cfft_init_q15( + arm_cfft_instance_q15 * S, + uint16_t fftLen); + +void arm_cfft_q15( + const arm_cfft_instance_q15 * S, + q15_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the fixed-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEI) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const q31_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const q31_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const q31_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_q31; + +arm_status arm_cfft_init_q31( + arm_cfft_instance_q31 * S, + uint16_t fftLen); + +void arm_cfft_q31( + const arm_cfft_instance_q31 * S, + q31_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + const uint32_t *rearranged_twiddle_tab_stride1_arr; /**< Per stage reordered twiddle pointer (offset 1) */ \ + const uint32_t *rearranged_twiddle_tab_stride2_arr; /**< Per stage reordered twiddle pointer (offset 2) */ \ + const uint32_t *rearranged_twiddle_tab_stride3_arr; /**< Per stage reordered twiddle pointer (offset 3) */ \ + const float32_t *rearranged_twiddle_stride1; /**< reordered twiddle offset 1 storage */ \ + const float32_t *rearranged_twiddle_stride2; /**< reordered twiddle offset 2 storage */ \ + const float32_t *rearranged_twiddle_stride3; +#endif + } arm_cfft_instance_f32; + + + arm_status arm_cfft_init_f32( + arm_cfft_instance_f32 * S, + uint16_t fftLen); + + void arm_cfft_f32( + const arm_cfft_instance_f32 * S, + float32_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + + /** + * @brief Instance structure for the Double Precision Floating-point CFFT/CIFFT function. + */ + typedef struct + { + uint16_t fftLen; /**< length of the FFT. */ + const float64_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ + } arm_cfft_instance_f64; + + void arm_cfft_f64( + const arm_cfft_instance_f64 * S, + float64_t * p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + + /** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q15 cfftInst; +#else + const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q15; + + arm_status arm_rfft_init_q15( + arm_rfft_instance_q15 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q15( + const arm_rfft_instance_q15 * S, + q15_t * pSrc, + q15_t * pDst); + + /** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ +#if defined(ARM_MATH_MVEI) + arm_cfft_instance_q31 cfftInst; +#else + const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +#endif + } arm_rfft_instance_q31; + + arm_status arm_rfft_init_q31( + arm_rfft_instance_q31 * S, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_q31( + const arm_rfft_instance_q31 * S, + q31_t * pSrc, + q31_t * pDst); + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + typedef struct + { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + const float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + const float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_rfft_instance_f32; + + arm_status arm_rfft_init_f32( + arm_rfft_instance_f32 * S, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + + void arm_rfft_f32( + const arm_rfft_instance_f32 * S, + float32_t * pSrc, + float32_t * pDst); + + /** + * @brief Instance structure for the Double Precision Floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f64 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float64_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f64 ; + +arm_status arm_rfft_fast_init_f64 ( + arm_rfft_fast_instance_f64 * S, + uint16_t fftLen); + + +void arm_rfft_fast_f64( + arm_rfft_fast_instance_f64 * S, + float64_t * p, float64_t * pOut, + uint8_t ifftFlag); + + + /** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ +typedef struct + { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + const float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ + } arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32 * S, + uint16_t fftLen); + + + void arm_rfft_fast_f32( + const arm_rfft_fast_instance_f32 * S, + float32_t * p, float32_t * pOut, + uint8_t ifftFlag); + + /** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + const float32_t *pTwiddle; /**< points to the twiddle factor table. */ + const float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_f32; + + + /** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + arm_status arm_dct4_init_f32( + arm_dct4_instance_f32 * S, + arm_rfft_instance_f32 * S_RFFT, + arm_cfft_radix4_instance_f32 * S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + + + /** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_f32( + const arm_dct4_instance_f32 * S, + float32_t * pState, + float32_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + const q31_t *pTwiddle; /**< points to the twiddle factor table. */ + const q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q31; + + + /** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q31( + arm_dct4_instance_q31 * S, + arm_rfft_instance_q31 * S_RFFT, + arm_cfft_radix4_instance_q31 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + + + /** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] S points to an instance of the Q31 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q31( + const arm_dct4_instance_q31 * S, + q31_t * pState, + q31_t * pInlineBuffer); + + + /** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + typedef struct + { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + const q15_t *pTwiddle; /**< points to the twiddle factor table. */ + const q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ + } arm_dct4_instance_q15; + + + /** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + arm_status arm_dct4_init_q15( + arm_dct4_instance_q15 * S, + arm_rfft_instance_q15 * S_RFFT, + arm_cfft_radix4_instance_q15 * S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + + + /** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] S points to an instance of the Q15 DCT4 structure. + * @param[in] pState points to state buffer. + * @param[in,out] pInlineBuffer points to the in-place input and output buffer. + */ + void arm_dct4_q15( + const arm_dct4_instance_q15 * S, + q15_t * pState, + q15_t * pInlineBuffer); + + + /** + * @brief Floating-point vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector addition. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_add_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector subtraction. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in each vector + */ + void arm_sub_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_f32( + const float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q7( + const q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q15( + const q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_scale_q31( + const q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q7 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Floating-point vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q15 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Q31 vector absolute value. + * @param[in] pSrc points to the input buffer + * @param[out] pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + */ + void arm_abs_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Dot product of floating-point vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t * result); + + + /** + * @brief Dot product of Q7 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q7( + const q7_t * pSrcA, + const q7_t * pSrcB, + uint32_t blockSize, + q31_t * result); + + + /** + * @brief Dot product of Q15 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Dot product of Q31 vectors. + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] result output result returned here + */ + void arm_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t blockSize, + q63_t * result); + + + /** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q7( + const q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q15( + const q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_shift_q31( + const q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_f32( + const float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q7( + const q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q15( + const q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_offset_q31( + const q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a floating-point vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q7 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q15 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Negates the elements of a Q31 vector. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] blockSize number of samples in the vector + */ + void arm_negate_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a floating-point vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q7 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q7( + const q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Copies the elements of a Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_copy_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_f32( + float32_t value, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q7( + q7_t value, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q15( + q15_t value, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_fill_q31( + q31_t value, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + + /** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + */ + void arm_conv_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + + /** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + */ + void arm_conv_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_conv_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. + */ + void arm_conv_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Partial convolution of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q15 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Partial convolution of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Partial convolution of Q7 sequences + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t * pScratch1, + q15_t * pScratch2); + + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + arm_status arm_conv_partial_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + /** + * @brief Instance structure for the Q15 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR decimator. + */ + typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for floating-point FIR decimator. + */ +typedef struct + { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + } arm_fir_decimate_instance_f32; + + +/** + @brief Processing function for floating-point FIR decimator. + @param[in] S points to an instance of the floating-point FIR decimator structure + @param[in] pSrc points to the block of input data + @param[out] pDst points to the block of output data + @param[in] blockSize number of samples to process + */ +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] S points to an instance of the floating-point FIR decimator structure + @param[in] numTaps number of coefficients in the filter + @param[in] M decimation factor + @param[in] pCoeffs points to the filter coefficients + @param[in] pState points to the state buffer + @param[in] blockSize number of input samples to process per call + @return execution status + - \ref ARM_MATH_SUCCESS : Operation successful + - \ref ARM_MATH_LENGTH_ERROR : blockSize is not a multiple of M + */ +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32 * S, + uint16_t numTaps, + uint8_t M, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q15 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15 * S, + uint16_t numTaps, + uint8_t M, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + /** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] S points to an instance of the Q31 FIR decimator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_decimate_fast_q31( + const arm_fir_decimate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31 * S, + uint16_t numTaps, + uint8_t M, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ + } arm_fir_interpolate_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR interpolator. + */ + typedef struct + { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ + } arm_fir_interpolate_instance_f32; + + + /** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15 * S, + uint8_t L, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] S points to an instance of the Q15 FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31 * S, + uint8_t L, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] pCoeffs points to the filter coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32 * S, + uint8_t L, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + } arm_biquad_cas_df1_32x64_ins_q31; + + + /** + * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + */ + void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31 * S, + uint8_t numStages, + const q31_t * pCoeffs, + q63_t * pState, + uint8_t postShift); + + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + const float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_stereo_df2T_instance_f32; + + /** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + typedef struct + { + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + const float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + } arm_biquad_cascade_df2T_instance_f64; + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_stereo_df2T_f32( + const arm_biquad_cascade_stereo_df2T_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] S points to an instance of the filter data structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_biquad_cascade_df2T_f64( + const arm_biquad_cascade_df2T_instance_f64 * S, + const float64_t * pSrc, + float64_t * pDst, + uint32_t blockSize); + + +#if defined(ARM_MATH_NEON) +void arm_biquad_cascade_df2T_compute_coefs_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + float32_t * pCoeffs); +#endif + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_stereo_df2T_init_f32( + arm_biquad_cascade_stereo_df2T_instance_f32 * S, + uint8_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] pCoeffs points to the filter coefficients. + * @param[in] pState points to the state buffer. + */ + void arm_biquad_cascade_df2T_init_f64( + arm_biquad_cascade_df2T_instance_f64 * S, + uint8_t numStages, + const float64_t * pCoeffs, + float64_t * pState); + + + /** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ + } arm_fir_lattice_instance_f32; + + + /** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15 * S, + uint16_t numStages, + const q15_t * pCoeffs, + q15_t * pState); + + + /** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] S points to an instance of the Q15 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31 * S, + uint16_t numStages, + const q31_t * pCoeffs, + q31_t * pState); + + + /** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] S points to an instance of the Q31 FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] pState points to the state buffer. The array is of length numStages. + */ + void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32 * S, + uint16_t numStages, + const float32_t * pCoeffs, + float32_t * pState); + + + /** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] S points to an instance of the floating-point FIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] blockSize number of samples to process. + */ + void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q15; + + /** + * @brief Instance structure for the Q31 IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_q31; + + /** + * @brief Instance structure for the floating-point IIR lattice filter. + */ + typedef struct + { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ + } arm_iir_lattice_instance_f32; + + + /** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32 * S, + uint16_t numStages, + float32_t * pkCoeffs, + float32_t * pvCoeffs, + float32_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31 * S, + uint16_t numStages, + q31_t * pkCoeffs, + q31_t * pvCoeffs, + q31_t * pState, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the Q15 IIR lattice structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + */ + void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + */ + void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15 * S, + uint16_t numStages, + q15_t * pkCoeffs, + q15_t * pvCoeffs, + q15_t * pState, + uint32_t blockSize); + + + /** + * @brief Instance structure for the floating-point LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ + } arm_lms_instance_f32; + + + /** + * @brief Processing function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_f32( + const arm_lms_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_init_f32( + arm_lms_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q15 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q15; + + + /** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to the coefficient buffer. + * @param[in] pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q15( + arm_lms_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Processing function for Q15 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q15( + const arm_lms_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + } arm_lms_instance_q31; + + + /** + * @brief Processing function for Q31 LMS filter. + * @param[in] S points to an instance of the Q15 LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_q31( + const arm_lms_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 LMS filter. + * @param[in] S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_init_q31( + arm_lms_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + + + /** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_f32; + + + /** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_f32( + arm_lms_norm_instance_f32 * S, + const float32_t * pSrc, + float32_t * pRef, + float32_t * pOut, + float32_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32 * S, + uint16_t numTaps, + float32_t * pCoeffs, + float32_t * pState, + float32_t mu, + uint32_t blockSize); + + + /** + * @brief Instance structure for the Q31 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q31; + + + /** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q31( + arm_lms_norm_instance_q31 * S, + const q31_t * pSrc, + q31_t * pRef, + q31_t * pOut, + q31_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31 * S, + uint16_t numTaps, + q31_t * pCoeffs, + q31_t * pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + typedef struct + { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + const q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ + } arm_lms_norm_instance_q15; + + + /** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] pSrc points to the block of input data. + * @param[in] pRef points to the block of reference data. + * @param[out] pOut points to the block of output data. + * @param[out] pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + */ + void arm_lms_norm_q15( + arm_lms_norm_instance_q15 * S, + const q15_t * pSrc, + q15_t * pRef, + q15_t * pOut, + q15_t * pErr, + uint32_t blockSize); + + + /** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] pCoeffs points to coefficient buffer. + * @param[in] pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + */ + void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15 * S, + uint16_t numTaps, + q15_t * pCoeffs, + q15_t * pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + + + /** + * @brief Correlation of floating-point sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_f32( + const float32_t * pSrcA, + uint32_t srcALen, + const float32_t * pSrcB, + uint32_t srcBLen, + float32_t * pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. +*/ +void arm_correlate_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1. + @return none + */ +void arm_correlate_fast_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst); + + +/** + @brief Correlation of Q15 sequences (fast version). + @param[in] pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + */ +void arm_correlate_fast_opt_q15( + const q15_t * pSrcA, + uint32_t srcALen, + const q15_t * pSrcB, + uint32_t srcBLen, + q15_t * pDst, + q15_t * pScratch); + + + /** + * @brief Correlation of Q31 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + +/** + @brief Correlation of Q31 sequences (fast version). + @param[in] pSrcA points to the first input sequence + @param[in] srcALen length of the first input sequence + @param[in] pSrcB points to the second input sequence + @param[in] srcBLen length of the second input sequence + @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ +void arm_correlate_fast_q31( + const q31_t * pSrcA, + uint32_t srcALen, + const q31_t * pSrcB, + uint32_t srcBLen, + q31_t * pDst); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + */ + void arm_correlate_opt_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst, + q15_t * pScratch1, + q15_t * pScratch2); + + + /** + * @brief Correlation of Q7 sequences. + * @param[in] pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + */ + void arm_correlate_q7( + const q7_t * pSrcA, + uint32_t srcALen, + const q7_t * pSrcB, + uint32_t srcBLen, + q7_t * pDst); + + + /** + * @brief Instance structure for the floating-point sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_f32; + + /** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q31; + + /** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q15; + + /** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + typedef struct + { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + const q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ + } arm_fir_sparse_instance_q7; + + + /** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] S points to an instance of the floating-point sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32 * S, + const float32_t * pSrc, + float32_t * pDst, + float32_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32 * S, + uint16_t numTaps, + const float32_t * pCoeffs, + float32_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] S points to an instance of the Q31 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31 * S, + const q31_t * pSrc, + q31_t * pDst, + q31_t * pScratchIn, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31 * S, + uint16_t numTaps, + const q31_t * pCoeffs, + q31_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] S points to an instance of the Q15 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15 * S, + const q15_t * pSrc, + q15_t * pDst, + q15_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15 * S, + uint16_t numTaps, + const q15_t * pCoeffs, + q15_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] S points to an instance of the Q7 sparse FIR structure. + * @param[in] pSrc points to the block of input data. + * @param[out] pDst points to the block of output data + * @param[in] pScratchIn points to a temporary buffer of size blockSize. + * @param[in] pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + */ + void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7 * S, + const q7_t * pSrc, + q7_t * pDst, + q7_t * pScratchIn, + q31_t * pScratchOut, + uint32_t blockSize); + + + /** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] pCoeffs points to the array of filter coefficients. + * @param[in] pState points to the state buffer. + * @param[in] pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + */ + void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7 * S, + uint16_t numTaps, + const q7_t * pCoeffs, + q7_t * pState, + int32_t * pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + + /** + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cos output. + */ + void arm_sin_cos_f32( + float32_t theta, + float32_t * pSinVal, + float32_t * pCosVal); + + + /** + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] pSinVal points to the processed sine output. + * @param[out] pCosVal points to the processed cosine output. + */ + void arm_sin_cos_q31( + q31_t theta, + q31_t * pSinVal, + q31_t * pCosVal); + + + /** + * @brief Floating-point complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + /** + * @brief Q31 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex conjugate. + * @param[in] pSrc points to the input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_conj_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude squared + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_squared_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @ingroup groupController + */ + + /** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+   *
    + * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup PID + * @{ + */ + + /** + * @brief Process function for the floating-point PID Control. + * @param[in,out] S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return processed output sample. + */ + __STATIC_FORCEINLINE float32_t arm_pid_f32( + arm_pid_instance_f32 * S, + float32_t in) + { + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + + } + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ +__STATIC_FORCEINLINE q31_t arm_pid_q31( + arm_pid_instance_q31 * S, + q31_t in) + { + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31U); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return processed output sample. + + \par Scaling and Overflow Behavior + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ +__STATIC_FORCEINLINE q15_t arm_pid_q15( + arm_pid_instance_q15 * S, + q15_t in) + { + q63_t acc; + q15_t out; + +#if defined (ARM_MATH_DSP) + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)read_q15x2 (S->state), (uint64_t)acc); +#else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; +#endif + + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + + /* saturate the output */ + out = (q15_t) (__SSAT((q31_t)(acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); + } + + /** + * @} end of PID group + */ + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32 * src, + arm_matrix_instance_f32 * dst); + + + /** + * @brief Floating-point matrix inverse. + * @param[in] src points to the instance of the input floating-point matrix structure. + * @param[out] dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + arm_status arm_mat_inverse_f64( + const arm_matrix_instance_f64 * src, + arm_matrix_instance_f64 * dst); + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup clarke + * @{ + */ + + /** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @return none + */ + __STATIC_FORCEINLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t * pIalpha, + float32_t * pIbeta) + { + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); + } + + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t * pIalpha, + q31_t * pIbeta) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); + } + + /** + * @} end of clarke group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_clarke + * @{ + */ + + /** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] pIa points to output three-phase coordinate a + * @param[out] pIb points to output three-phase coordinate b + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pIa, + float32_t * pIb) + { + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; + } + + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] pIa points to output three-phase coordinate a + @param[out] pIb points to output three-phase coordinate b + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pIa, + q31_t * pIb) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); + } + + /** + * @} end of inv_clarke group + */ + + + + /** + * @ingroup groupController + */ + + /** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup park + * @{ + */ + + /** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] pId points to output rotor reference frame d + * @param[out] pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + * + * The function implements the forward Park transform. + * + */ + __STATIC_FORCEINLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t * pId, + float32_t * pIq, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; + } + + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] pId points to output rotor reference frame d + @param[out] pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + \par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t * pId, + q31_t * pIq, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); + } + + /** + * @} end of park group + */ + + + /** + * @ingroup groupController + */ + + /** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + + /** + * @addtogroup inv_park + * @{ + */ + + /** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none + */ + __STATIC_FORCEINLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t * pIalpha, + float32_t * pIbeta, + float32_t sinVal, + float32_t cosVal) + { + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; + } + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none + + @par Scaling and Overflow Behavior + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. + */ +__STATIC_FORCEINLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t * pIalpha, + q31_t * pIbeta, + q31_t sinVal, + q31_t cosVal) + { + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); + } + + /** + * @} end of Inverse park group + */ + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
    + * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + + /** + * @addtogroup LinearInterpolate + * @{ + */ + + /** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + __STATIC_FORCEINLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32 * S, + float32_t x) + { + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if (i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if ((uint32_t)i >= (S->nValues - 1)) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + + } + + /* returns output value */ + return (y); + } + + + /** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q31_t arm_linear_interp_q31( + q31_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (q31_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1U); + } + } + + + /** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + __STATIC_FORCEINLINE q15_t arm_linear_interp_q15( + q15_t * pYData, + q31_t x, + uint32_t nValues) + { + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & (int32_t)0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if (index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + + /* convert y to 1.15 format */ + return (q15_t) (y >> 20); + } + } + + + /** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + __STATIC_FORCEINLINE q7_t arm_linear_interp_q7( + q7_t * pYData, + q31_t x, + uint32_t nValues) + { + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (q7_t) (y >> 20); + } + } + + /** + * @} end of LinearInterpolate group + */ + + /** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + float32_t arm_sin_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q31_t arm_sin_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + q15_t arm_sin_q15( + q15_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + float32_t arm_cos_f32( + float32_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q31_t arm_cos_q31( + q31_t x); + + + /** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + q15_t arm_cos_q15( + q15_t x); + + +/** + @brief Floating-point vector of log values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vlog_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector of exp values. + @param[in] pSrc points to the input vector + @param[out] pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none + */ + void arm_vexp_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + /** + * @ingroup groupFastMath + */ + + + /** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   *
    + * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
    + */ + + + /** + * @addtogroup SQRT + * @{ + */ + +/** + @brief Floating-point square root function. + @param[in] in input value + @param[out] pOut square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +__STATIC_FORCEINLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t * pOut) + { + if (in >= 0.0f) + { +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); + #else + *pOut = sqrtf(in); + #endif + +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } + } + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q31( + q31_t in, + q31_t * pOut); + + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF + @param[out] pOut points to square root of input value + @return execution status + - \ref ARM_MATH_SUCCESS : input value is positive + - \ref ARM_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0 + */ +arm_status arm_sqrt_q15( + q15_t in, + q15_t * pOut); + + /** + * @brief Vector Floating-point square root function. + * @param[in] pIn input vector. + * @param[out] pOut vector of square roots of input elements. + * @param[in] len length of input vector. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + void arm_vsqrt_f32( + float32_t * pIn, + float32_t * pOut, + uint16_t len); + + void arm_vsqrt_q31( + q31_t * pIn, + q31_t * pOut, + uint16_t len); + + void arm_vsqrt_q15( + q15_t * pIn, + q15_t * pOut, + uint16_t len); + + /** + * @} end of SQRT group + */ + + + /** + * @brief floating-point Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_f32( + int32_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const int32_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + + /** + * @brief floating-point Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_f32( + int32_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + int32_t * dst, + int32_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t rOffset; + int32_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q15 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q15( + q15_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q15_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q15 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q15( + q15_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q15_t * dst, + q15_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q15_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Q7 Circular write function. + */ + __STATIC_FORCEINLINE void arm_circularWrite_q7( + q7_t * circBuffer, + int32_t L, + uint16_t * writeOffset, + int32_t bufferInc, + const q7_t * src, + int32_t srcInc, + uint32_t blockSize) + { + uint32_t i = 0U; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = (uint16_t)wOffset; + } + + + /** + * @brief Q7 Circular Read function. + */ + __STATIC_FORCEINLINE void arm_circularRead_q7( + q7_t * circBuffer, + int32_t L, + int32_t * readOffset, + int32_t bufferInc, + q7_t * dst, + q7_t * dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) + { + uint32_t i = 0; + int32_t rOffset; + q7_t* dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = dst_base + dst_length; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0U) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; + } + + + /** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q31( + const q31_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q15( + const q15_t * pSrc, + uint32_t blockSize, + q63_t * pResult); + + + /** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_power_q7( + const q7_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult); + + + /** + * @brief Mean value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Mean value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Mean value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_mean_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Variance of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Variance of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_var_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_rms_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult); + + + /** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output value. + */ + void arm_std_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult); + + + /** + * @brief Floating-point complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_f32( + const float32_t * pSrc, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q31( + const q31_t * pSrc, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex magnitude + * @param[in] pSrc points to the complex input vector + * @param[out] pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + */ + void arm_cmplx_mag_q15( + const q15_t * pSrc, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q15 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + uint32_t numSamples, + q31_t * realResult, + q31_t * imagResult); + + + /** + * @brief Q31 complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + uint32_t numSamples, + q63_t * realResult, + q63_t * imagResult); + + + /** + * @brief Floating-point complex dot product + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] realResult real part of the result returned here + * @param[out] imagResult imaginary part of the result returned here + */ + void arm_cmplx_dot_prod_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t numSamples, + float32_t * realResult, + float32_t * imagResult); + + + /** + * @brief Q15 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q15( + const q15_t * pSrcCmplx, + const q15_t * pSrcReal, + q15_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_q31( + const q31_t * pSrcCmplx, + const q31_t * pSrcReal, + q31_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-real multiplication + * @param[in] pSrcCmplx points to the complex input vector + * @param[in] pSrcReal points to the real input vector + * @param[out] pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + */ + void arm_cmplx_mult_real_f32( + const float32_t * pSrcCmplx, + const float32_t * pSrcReal, + float32_t * pCmplxDst, + uint32_t numSamples); + + + /** + * @brief Minimum value of a Q7 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + */ + void arm_min_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * result, + uint32_t * index); + + + /** + * @brief Minimum value of a Q15 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[in] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a Q31 vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + + /** + * @brief Minimum value of a floating-point vector. + * @param[in] pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] pResult is output pointer + * @param[out] pIndex is the array index of the minimum value in the input buffer. + */ + void arm_min_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q7( + const q7_t * pSrc, + uint32_t blockSize, + q7_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q15( + const q15_t * pSrc, + uint32_t blockSize, + q15_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_q31( + const q31_t * pSrc, + uint32_t blockSize, + q31_t * pResult, + uint32_t * pIndex); + + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] pResult maximum value returned here + * @param[out] pIndex index of maximum value returned here + */ + void arm_max_f32( + const float32_t * pSrc, + uint32_t blockSize, + float32_t * pResult, + uint32_t * pIndex); + + /** + @brief Maximum value of a floating-point vector. + @param[in] pSrc points to the input vector + @param[in] blockSize number of samples in input vector + @param[out] pResult maximum value returned here + @return none + */ + void arm_max_no_idx_f32( + const float32_t *pSrc, + uint32_t blockSize, + float32_t *pResult); + + /** + * @brief Q15 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q15( + const q15_t * pSrcA, + const q15_t * pSrcB, + q15_t * pDst, + uint32_t numSamples); + + + /** + * @brief Q31 complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_q31( + const q31_t * pSrcA, + const q31_t * pSrcB, + q31_t * pDst, + uint32_t numSamples); + + + /** + * @brief Floating-point complex-by-complex multiplication + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[out] pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + */ + void arm_cmplx_mult_cmplx_f32( + const float32_t * pSrcA, + const float32_t * pSrcB, + float32_t * pDst, + uint32_t numSamples); + + + /** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q31( + const float32_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q15( + const float32_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] pSrc points to the floating-point input vector + * @param[out] pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + */ + void arm_float_to_q7( + const float32_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_float( + const q31_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q15( + const q31_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q31_to_q7( + const q31_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_float( + const q15_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q31( + const q15_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q15_to_q7( + const q15_t * pSrc, + q7_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] pSrc is input pointer + * @param[out] pDst is output pointer + * @param[in] blockSize is the number of samples to process + */ + void arm_q7_to_float( + const q7_t * pSrc, + float32_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q31( + const q7_t * pSrc, + q31_t * pDst, + uint32_t blockSize); + + + /** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] pSrc input pointer + * @param[out] pDst output pointer + * @param[in] blockSize number of samples to process + */ + void arm_q7_to_q15( + const q7_t * pSrc, + q15_t * pDst, + uint32_t blockSize); + +/** + * @brief Struct for specifying SVM Kernel + */ +typedef enum +{ + ARM_ML_KERNEL_LINEAR = 0, + /**< Linear kernel */ + ARM_ML_KERNEL_POLYNOMIAL = 1, + /**< Polynomial kernel */ + ARM_ML_KERNEL_RBF = 2, + /**< Radial Basis Function kernel */ + ARM_ML_KERNEL_SIGMOID = 3 + /**< Sigmoid kernel */ +} arm_ml_kernel_type; + + +/** + * @brief Instance structure for linear SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ +} arm_svm_linear_instance_f32; + + +/** + * @brief Instance structure for polynomial SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + int32_t degree; /**< Polynomial degree */ + float32_t coef0; /**< Polynomial constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_polynomial_instance_f32; + +/** + * @brief Instance structure for rbf SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_rbf_instance_f32; + +/** + * @brief Instance structure for sigmoid SVM prediction function. + */ +typedef struct +{ + uint32_t nbOfSupportVectors; /**< Number of support vectors */ + uint32_t vectorDimension; /**< Dimension of vector space */ + float32_t intercept; /**< Intercept */ + const float32_t *dualCoefficients; /**< Dual coefficients */ + const float32_t *supportVectors; /**< Support vectors */ + const int32_t *classes; /**< The two SVM classes */ + float32_t coef0; /**< Independant constant */ + float32_t gamma; /**< Gamma factor */ +} arm_svm_sigmoid_instance_f32; + +/** + * @brief SVM linear instance init function + * @param[in] S Parameters for SVM functions + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @return none. + * + */ + + +void arm_svm_linear_init_f32(arm_svm_linear_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes); + +/** + * @brief SVM linear prediction + * @param[in] S Pointer to an instance of the linear SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ + +void arm_svm_linear_predict_f32(const arm_svm_linear_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM polynomial instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] degree Polynomial degree + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + + +void arm_svm_polynomial_init_f32(arm_svm_polynomial_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + int32_t degree, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM polynomial prediction + * @param[in] S Pointer to an instance of the polynomial SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_polynomial_predict_f32(const arm_svm_polynomial_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + +/** + * @brief SVM radial basis function instance init function + * @param[in] S points to an instance of the polynomial SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_rbf_init_f32(arm_svm_rbf_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t gamma + ); + +/** + * @brief SVM rbf prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult decision value + * @return none. + * + */ +void arm_svm_rbf_predict_f32(const arm_svm_rbf_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + +/** + * @brief SVM sigmoid instance init function + * @param[in] S points to an instance of the rbf SVM structure. + * @param[in] nbOfSupportVectors Number of support vectors + * @param[in] vectorDimension Dimension of vector space + * @param[in] intercept Intercept + * @param[in] dualCoefficients Array of dual coefficients + * @param[in] supportVectors Array of support vectors + * @param[in] classes Array of 2 classes ID + * @param[in] coef0 coeff0 (scikit-learn terminology) + * @param[in] gamma gamma (scikit-learn terminology) + * @return none. + * + */ + +void arm_svm_sigmoid_init_f32(arm_svm_sigmoid_instance_f32 *S, + uint32_t nbOfSupportVectors, + uint32_t vectorDimension, + float32_t intercept, + const float32_t *dualCoefficients, + const float32_t *supportVectors, + const int32_t *classes, + float32_t coef0, + float32_t gamma + ); + +/** + * @brief SVM sigmoid prediction + * @param[in] S Pointer to an instance of the rbf SVM structure. + * @param[in] in Pointer to input vector + * @param[out] pResult Decision value + * @return none. + * + */ +void arm_svm_sigmoid_predict_f32(const arm_svm_sigmoid_instance_f32 *S, + const float32_t * in, + int32_t * pResult); + + + +/** + * @brief Instance structure for Naive Gaussian Bayesian estimator. + */ +typedef struct +{ + uint32_t vectorDimension; /**< Dimension of vector space */ + uint32_t numberOfClasses; /**< Number of different classes */ + const float32_t *theta; /**< Mean values for the Gaussians */ + const float32_t *sigma; /**< Variances for the Gaussians */ + const float32_t *classPriors; /**< Class prior probabilities */ + float32_t epsilon; /**< Additive value to variances */ +} arm_gaussian_naive_bayes_instance_f32; + +/** + * @brief Naive Gaussian Bayesian Estimator + * + * @param[in] S points to a naive bayes instance structure + * @param[in] in points to the elements of the input vector. + * @param[in] pBuffer points to a buffer of length numberOfClasses + * @return The predicted class + * + */ + + +uint32_t arm_gaussian_naive_bayes_predict_f32(const arm_gaussian_naive_bayes_instance_f32 *S, + const float32_t * in, + float32_t *pBuffer); + +/** + * @brief Computation of the LogSumExp + * + * In probabilistic computations, the dynamic of the probability values can be very + * wide because they come from gaussian functions. + * To avoid underflow and overflow issues, the values are represented by their log. + * In this representation, multiplying the original exp values is easy : their logs are added. + * But adding the original exp values is requiring some special handling and it is the + * goal of the LogSumExp function. + * + * If the values are x1...xn, the function is computing: + * + * ln(exp(x1) + ... + exp(xn)) and the computation is done in such a way that + * rounding issues are minimised. + * + * The max xm of the values is extracted and the function is computing: + * xm + ln(exp(x1 - xm) + ... + exp(xn - xm)) + * + * @param[in] *in Pointer to an array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return LogSumExp + * + */ + + +float32_t arm_logsumexp_f32(const float32_t *in, uint32_t blockSize); + +/** + * @brief Dot product with log arithmetic + * + * Vectors are containing the log of the samples + * + * @param[in] pSrcA points to the first input vector + * @param[in] pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[in] pTmpBuffer temporary buffer of length blockSize + * @return The log of the dot product . + * + */ + + +float32_t arm_logsumexp_dot_prod_f32(const float32_t * pSrcA, + const float32_t * pSrcB, + uint32_t blockSize, + float32_t *pTmpBuffer); + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float32_t arm_entropy_f32(const float32_t * pSrcA,uint32_t blockSize); + + +/** + * @brief Entropy + * + * @param[in] pSrcA Array of input values. + * @param[in] blockSize Number of samples in the input array. + * @return Entropy -Sum(p ln p) + * + */ + + +float64_t arm_entropy_f64(const float64_t * pSrcA, uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float32_t arm_kullback_leibler_f32(const float32_t * pSrcA + ,const float32_t * pSrcB + ,uint32_t blockSize); + + +/** + * @brief Kullback-Leibler + * + * @param[in] pSrcA Pointer to an array of input values for probability distribution A. + * @param[in] pSrcB Pointer to an array of input values for probability distribution B. + * @param[in] blockSize Number of samples in the input array. + * @return Kullback-Leibler Divergence D(A || B) + * + */ +float64_t arm_kullback_leibler_f64(const float64_t * pSrcA, + const float64_t * pSrcB, + uint32_t blockSize); + + +/** + * @brief Weighted sum + * + * + * @param[in] *in Array of input values. + * @param[in] *weigths Weights + * @param[in] blockSize Number of samples in the input array. + * @return Weighted sum + * + */ +float32_t arm_weighted_sum_f32(const float32_t *in + , const float32_t *weigths + , uint32_t blockSize); + + +/** + * @brief Barycenter + * + * + * @param[in] in List of vectors + * @param[in] weights Weights of the vectors + * @param[out] out Barycenter + * @param[in] nbVectors Number of vectors + * @param[in] vecDim Dimension of space (vector dimension) + * @return None + * + */ +void arm_barycenter_f32(const float32_t *in + , const float32_t *weights + , float32_t *out + , uint32_t nbVectors + , uint32_t vecDim); + +/** + * @brief Euclidean distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_euclidean_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Bray-Curtis distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_braycurtis_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Canberra distance between two vectors + * + * This function may divide by zero when samples pA[i] and pB[i] are both zero. + * The result of the computation will be correct. So the division per zero may be + * ignored. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_canberra_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Chebyshev distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_chebyshev_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + + +/** + * @brief Cityblock (Manhattan) distance between two vectors + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_cityblock_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Correlation distance between two vectors + * + * The input vectors are modified in place ! + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ +float32_t arm_correlation_distance_f32(float32_t *pA,float32_t *pB, uint32_t blockSize); + +/** + * @brief Cosine distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_cosine_distance_f32(const float32_t *pA,const float32_t *pB, uint32_t blockSize); + +/** + * @brief Jensen-Shannon distance between two vectors + * + * This function is assuming that elements of second vector are > 0 + * and 0 only when the corresponding element of first vector is 0. + * Otherwise the result of the computation does not make sense + * and for speed reasons, the cases returning NaN or Infinity are not + * managed. + * + * When the function is computing x log (x / y) with x 0 and y 0, + * it will compute the right value (0) but a division per zero will occur + * and shoudl be ignored in client code. + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] blockSize vector length + * @return distance + * + */ + +float32_t arm_jensenshannon_distance_f32(const float32_t *pA,const float32_t *pB,uint32_t blockSize); + +/** + * @brief Minkowski distance between two vectors + * + * @param[in] pA First vector + * @param[in] pB Second vector + * @param[in] n Norm order (>= 2) + * @param[in] blockSize vector length + * @return distance + * + */ + + + +float32_t arm_minkowski_distance_f32(const float32_t *pA,const float32_t *pB, int32_t order, uint32_t blockSize); + +/** + * @brief Dice distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] order Distance order + * @param[in] blockSize Number of samples + * @return distance + * + */ + + +float32_t arm_dice_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Hamming distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_hamming_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Jaccard distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_jaccard_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Kulsinski distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_kulsinski_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Roger Stanimoto distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_rogerstanimoto_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Russell-Rao distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_russellrao_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Michener distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalmichener_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Sokal-Sneath distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_sokalsneath_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + +/** + * @brief Yule distance between two vectors + * + * @param[in] pA First vector of packed booleans + * @param[in] pB Second vector of packed booleans + * @param[in] numberOfBools Number of booleans + * @return distance + * + */ + +float32_t arm_yule_distance(const uint32_t *pA, const uint32_t *pB, uint32_t numberOfBools); + + + /** + * @ingroup groupInterpolation + */ + + /** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
    + * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   *
    + * \par + * The interpolated output point is computed as: + * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
    + * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + + + /** + * @addtogroup BilinearInterpolate + * @{ + */ + + /** + * @brief Floating-point bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32 * S, + float32_t X, + float32_t Y) + { + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numCols - 2) || yIndex < 0 || yIndex > (S->numRows - 2)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex ) + (yIndex ) * S->numCols; + + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex ) + (yIndex+1) * S->numCols; + + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); + } + + + /** + * @brief Q31 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31 * S, + q31_t X, + q31_t Y) + { + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; + x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11U; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; + y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return ((q31_t)(acc << 2)); + } + + + /** + * @brief Q15 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0x0FFFFF - xfract)) >> 4U); + acc = ((q63_t) out * (0x0FFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0x0FFFFF - yfract)) >> 4U); + acc += ((q63_t) out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0x0FFFFF - xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); + acc += ((q63_t) out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return ((q15_t)(acc >> 36)); + } + + + /** + * @brief Q7 bilinear interpolation. + * @param[in,out] S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + __STATIC_FORCEINLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7 * S, + q31_t X, + q31_t Y) + { + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & (q31_t)0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & (q31_t)0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numCols - 2) || cI < 0 || cI > (S->numRows - 2)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; + x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & (q31_t)0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; + y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return ((q7_t)(acc >> 40)); + } + + /** + * @} end of BilinearInterpolate group + */ + + +/* SMMLAR */ +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMLSR */ +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +/* SMMULR */ +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +/* SMMLA */ +#define multAcc_32x32_keep32(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +/* SMMLS */ +#define multSub_32x32_keep32(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +/* SMMUL */ +#define mult_32x32_keep32(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + + +#if defined ( __CC_ARM ) + /* Enter low optimization region - place directly above function definition */ + #if defined( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + #else + #define LOW_OPTIMIZATION_EXIT + #endif + + /* Enter low optimization region - place directly above function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __GNUC__ ) + #define LOW_OPTIMIZATION_ENTER \ + __attribute__(( optimize("-O1") )) + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __ICCARM__ ) + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define LOW_OPTIMIZATION_EXIT + + /* Enter low optimization region - place directly above function definition */ + #if defined ( __ARM_ARCH_7EM__ ) + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + #else + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #endif + + /* Exit low optimization region - place directly after end of function definition */ + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TI_ARM__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __CSMC__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( __TASKING__ ) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__) + #define LOW_OPTIMIZATION_ENTER + #define LOW_OPTIMIZATION_EXIT + #define IAR_ONLY_LOW_OPTIMIZATION_ENTER + #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#endif + + + +/* Compiler specific diagnostic adjustment */ +#if defined ( __CC_ARM ) + +#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) + +#elif defined ( __GNUC__ ) +#pragma GCC diagnostic pop + +#elif defined ( __ICCARM__ ) + +#elif defined ( __TI_ARM__ ) + +#elif defined ( __CSMC__ ) + +#elif defined ( __TASKING__ ) + +#elif defined ( _MSC_VER ) + +#else + #error Unknown compiler +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_mve_tables.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_mve_tables.h new file mode 100644 index 0000000000..4d2c135ac6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_mve_tables.h @@ -0,0 +1,235 @@ +/* ---------------------------------------------------------------------- + * Project: CMSIS DSP Library + * Title: arm_mve_tables.h + * Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc + * used for MVE implementation only + * + * $Date: 08. January 2020 + * $Revision: V1.7.0 + * + * Target Processor: Cortex-M cores + * -------------------------------------------------------------------- */ +/* + * Copyright (C) 2010-2020 ARM Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + #ifndef _ARM_MVE_TABLES_H + #define _ARM_MVE_TABLES_H + + #include "arm_math.h" + + + + + + +#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2]; +extern float32_t rearranged_twiddle_stride1_16_f32[8]; +extern float32_t rearranged_twiddle_stride2_16_f32[8]; +extern float32_t rearranged_twiddle_stride3_16_f32[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3]; +extern float32_t rearranged_twiddle_stride1_64_f32[40]; +extern float32_t rearranged_twiddle_stride2_64_f32[40]; +extern float32_t rearranged_twiddle_stride3_64_f32[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4]; +extern float32_t rearranged_twiddle_stride1_256_f32[168]; +extern float32_t rearranged_twiddle_stride2_256_f32[168]; +extern float32_t rearranged_twiddle_stride3_256_f32[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5]; +extern float32_t rearranged_twiddle_stride1_1024_f32[680]; +extern float32_t rearranged_twiddle_stride2_1024_f32[680]; +extern float32_t rearranged_twiddle_stride3_1024_f32[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6]; +extern float32_t rearranged_twiddle_stride1_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride2_4096_f32[2728]; +extern float32_t rearranged_twiddle_stride3_4096_f32[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2]; +extern q31_t rearranged_twiddle_stride1_16_q31[8]; +extern q31_t rearranged_twiddle_stride2_16_q31[8]; +extern q31_t rearranged_twiddle_stride3_16_q31[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3]; +extern q31_t rearranged_twiddle_stride1_64_q31[40]; +extern q31_t rearranged_twiddle_stride2_64_q31[40]; +extern q31_t rearranged_twiddle_stride3_64_q31[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4]; +extern q31_t rearranged_twiddle_stride1_256_q31[168]; +extern q31_t rearranged_twiddle_stride2_256_q31[168]; +extern q31_t rearranged_twiddle_stride3_256_q31[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5]; +extern q31_t rearranged_twiddle_stride1_1024_q31[680]; +extern q31_t rearranged_twiddle_stride2_1024_q31[680]; +extern q31_t rearranged_twiddle_stride3_1024_q31[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6]; +extern q31_t rearranged_twiddle_stride1_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride2_4096_q31[2728]; +extern q31_t rearranged_twiddle_stride3_4096_q31[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2]; +extern q15_t rearranged_twiddle_stride1_16_q15[8]; +extern q15_t rearranged_twiddle_stride2_16_q15[8]; +extern q15_t rearranged_twiddle_stride3_16_q15[8]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3]; +extern q15_t rearranged_twiddle_stride1_64_q15[40]; +extern q15_t rearranged_twiddle_stride2_64_q15[40]; +extern q15_t rearranged_twiddle_stride3_64_q15[40]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4]; +extern q15_t rearranged_twiddle_stride1_256_q15[168]; +extern q15_t rearranged_twiddle_stride2_256_q15[168]; +extern q15_t rearranged_twiddle_stride3_256_q15[168]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5]; +extern q15_t rearranged_twiddle_stride1_1024_q15[680]; +extern q15_t rearranged_twiddle_stride2_1024_q15[680]; +extern q15_t rearranged_twiddle_stride3_1024_q15[680]; +#endif + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192) + +extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6]; +extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6]; +extern q15_t rearranged_twiddle_stride1_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride2_4096_q15[2728]; +extern q15_t rearranged_twiddle_stride3_4096_q15[2728]; +#endif + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#if defined(ARM_MATH_MVEI) + +#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) + + +#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */ + +#endif /* defined(ARM_MATH_MVEI) */ + + + +#endif /*_ARM_MVE_TABLES_H*/ + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_vec_math.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_vec_math.h new file mode 100644 index 0000000000..0ce9464bcb --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/arm_vec_math.h @@ -0,0 +1,372 @@ +/****************************************************************************** + * @file arm_vec_math.h + * @brief Public header file for CMSIS DSP Library + * @version V1.7.0 + * @date 15. October 2019 + ******************************************************************************/ +/* + * Copyright (c) 2010-2019 Arm Limited or its affiliates. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _ARM_VEC_MATH_H +#define _ARM_VEC_MATH_H + +#include "arm_math.h" +#include "arm_common_tables.h" +#include "arm_helium_utils.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#define INV_NEWTON_INIT_F32 0x7EF127EA + +static const float32_t __logf_rng_f32=0.693147180f; + + +/* fast inverse approximation (3x newton) */ +__STATIC_INLINE f32x4_t vrecip_medprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +/* fast inverse approximation (4x newton) */ +__STATIC_INLINE f32x4_t vrecip_hiprec_f32( + f32x4_t x) +{ + q31x4_t m; + f32x4_t b; + any32x4_t xinv; + f32x4_t ax = vabsq(x); + + xinv.f = ax; + + m = 0x3F800000 - (xinv.i & 0x7F800000); + xinv.i = xinv.i + m; + xinv.f = 1.41176471f - 0.47058824f * xinv.f; + xinv.i = xinv.i + m; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + b = 2.0f - xinv.f * ax; + xinv.f = xinv.f * b; + + xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f)); + /* + * restore sign + */ + xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f)); + + return xinv.f; +} + +__STATIC_INLINE f32x4_t vdiv_f32( + f32x4_t num, f32x4_t den) +{ + return vmulq(num, vrecip_hiprec_f32(den)); +} + +/** + @brief Single-precision taylor dev. + @param[in] x f32 quad vector input + @param[in] coeffs f32 quad vector coeffs + @return destination f32 quad vector + */ + +__STATIC_INLINE f32x4_t vtaylor_polyq_f32( + f32x4_t x, + const float32_t * coeffs) +{ + f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]); + f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]); + f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]); + f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]); + f32x4_t x2 = vmulq(x, x); + f32x4_t x4 = vmulq(x2, x2); + f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4); + + return res; +} + +__STATIC_INLINE f32x4_t vmant_exp_f32( + f32x4_t x, + int32x4_t * e) +{ + any32x4_t r; + int32x4_t n; + + r.f = x; + n = r.i >> 23; + n = n - 127; + r.i = r.i - (n << 23); + + *e = n; + return r.f; +} + + +__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn) +{ + q31x4_t vecExpUnBiased; + f32x4_t vecTmpFlt0, vecTmpFlt1; + f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3; + f32x4_t vecExpUnBiasedFlt; + + /* + * extract exponent + */ + vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased); + + vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1; + /* + * a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]); + */ + vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]); + vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]); + /* + * b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]); + */ + vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]); + vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]); + /* + * c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]); + */ + vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]); + vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]); + /* + * d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]); + */ + vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]); + vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]); + /* + * a = a + b * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0); + /* + * c = c + d * xx; + */ + vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0); + /* + * xx = xx * xx; + */ + vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0; + vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased); + /* + * r.f = a + c * xx; + */ + vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0); + /* + * add exponent + * r.f = r.f + ((float32_t) m) * __logf_rng_f32; + */ + vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32); + // set log0 down to -inf + vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f)); + return vecAcc0; +} + +__STATIC_INLINE f32x4_t vexpq_f32( + f32x4_t x) +{ + // Perform range reduction [-log(2),log(2)] + int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f)); + f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f)); + + // Polynomial Approximation + f32x4_t poly = vtaylor_polyq_f32(val, exp_tab); + + // Reconstruct + poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23))); + + poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126)); + return poly; +} + +__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb) +{ + f32x4_t r = x; + nb--; + while (nb > 0) { + r = vmulq(r, x); + nb--; + } + return (r); +} + +__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn) +{ + f32x4_t vecSx, vecW, vecTmp; + any32x4_t v; + + vecSx = vabsq(vecIn); + + v.f = vecIn; + v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i); + + vecW = vmulq(vecSx, v.f); + + // v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w))))))); + vecTmp = vsubq(vdupq_n_f32(8.0f), vecW); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -70.0f); + vecTmp = vfmasq(vecW, vecTmp, 56.0f); + vecTmp = vfmasq(vecW, vecTmp, -28.0f); + vecTmp = vfmasq(vecW, vecTmp, 8.0f); + v.f = vmulq(v.f, vecTmp); + + v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f)); + /* + * restore sign + */ + v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f)); + return v.f; +} + +__STATIC_INLINE f32x4_t vtanhq_f32( + f32x4_t val) +{ + f32x4_t x = + vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f)); + f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f)); + f32x4_t num = vsubq_n_f32(exp2x, 1.f); + f32x4_t den = vaddq_n_f32(exp2x, 1.f); + f32x4_t tanh = vmulq_f32(num, vrecip_f32(den)); + return tanh; +} + +__STATIC_INLINE f32x4_t vpowq_f32( + f32x4_t val, + f32x4_t n) +{ + return vexpq_f32(vmulq_f32(n, vlogq_f32(val))); +} + +#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/ + +#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) +#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */ + +#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) + +#include "NEMath.h" +/** + * @brief Vectorized integer exponentiation + * @param[in] x value + * @param[in] nb integer exponent >= 1 + * @return x^nb + * + */ +__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb) +{ + float32x4_t r = x; + nb --; + while(nb > 0) + { + r = vmulq_f32(r , x); + nb--; + } + return(r); +} + + +__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x) +{ + float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN)); + float32x4_t e = vrsqrteq_f32(x1); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e); + return vmulq_f32(x, e); +} + +__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec) +{ + float32x4_t tempF; + int32x4_t tempHI,tempLO; + + tempLO = vmovl_s16(vget_low_s16(vec)); + tempF = vcvtq_n_f32_s32(tempLO,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempLO = vcvtq_n_s32_f32(tempF,15); + + tempHI = vmovl_s16(vget_high_s16(vec)); + tempF = vcvtq_n_f32_s32(tempHI,15); + tempF = __arm_vec_sqrt_f32_neon(tempF); + tempHI = vcvtq_n_s32_f32(tempF,15); + + return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI))); +} + +__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec) +{ + float32x4_t temp; + + temp = vcvtq_n_f32_s32(vec,31); + temp = __arm_vec_sqrt_f32_neon(temp); + return(vcvtq_n_s32_f32(temp,31)); +} + +#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_VEC_MATH_H */ + +/** + * + * End of file. + */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cachel1_armv7.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cachel1_armv7.h new file mode 100644 index 0000000000..d2c3e2291f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.0 + * @date 03. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armcc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armcc.h new file mode 100644 index 0000000000..237ff6ec3e --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armcc.h @@ -0,0 +1,885 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.2.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armclang.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armclang.h new file mode 100644 index 0000000000..90de9dbf8f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armclang.h @@ -0,0 +1,1467 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.3.1 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000..0e5c7349d3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1893 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_compiler.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_compiler.h new file mode 100644 index 0000000000..adbf296f15 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_gcc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_gcc.h new file mode 100644 index 0000000000..a2778f58e8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_gcc.h @@ -0,0 +1,2177 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.3.0 + * @date 26. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_iccarm.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_iccarm.h new file mode 100644 index 0000000000..7eeffca5c7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_iccarm.h @@ -0,0 +1,968 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.2.0 + * @date 28. January 2020 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_version.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_version.h new file mode 100644 index 0000000000..2f048e4552 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.4 + * @date 23. July 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv81mml.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv81mml.h new file mode 100644 index 0000000000..1ad19e215a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv81mml.h @@ -0,0 +1,4191 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.3.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv8mbl.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv8mbl.h new file mode 100644 index 0000000000..932d3d188b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv8mml.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv8mml.h new file mode 100644 index 0000000000..71f000bcad --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_armv8mml.h @@ -0,0 +1,3196 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm0.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm0.h new file mode 100644 index 0000000000..6441ff3419 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm0plus.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm0plus.h new file mode 100644 index 0000000000..4e7179a614 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm0plus.h @@ -0,0 +1,1087 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 21. August 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ +#endif + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +#else + uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ + return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ +#endif +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm1.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm1.h new file mode 100644 index 0000000000..76b4569743 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm23.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm23.h new file mode 100644 index 0000000000..55fff99509 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm23.h @@ -0,0 +1,2297 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 11. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm3.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm3.h new file mode 100644 index 0000000000..24453a8863 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm3.h @@ -0,0 +1,1943 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm33.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm33.h new file mode 100644 index 0000000000..13359be3ed --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm33.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.2.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm35p.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm35p.h new file mode 100644 index 0000000000..6a5f6ad147 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm35p.h @@ -0,0 +1,3264 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm4.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm4.h new file mode 100644 index 0000000000..4e0e886697 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm55.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm55.h new file mode 100644 index 0000000000..6efaa3f842 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm55.h @@ -0,0 +1,4215 @@ +/**************************************************************************//** + * @file core_cm55.h + * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2018-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CM55_H_GENERIC +#define __CORE_CM55_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_CM55 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM55 definitions */ +#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ + __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (55U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM55_H_DEPENDANT +#define __CORE_CM55_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM55_REV + #define __CM55_REV 0x0000U + #warning "__CM55_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 8U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M55 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[4]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 3 */ + uint32_t RESERVED14[3]; + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (16UL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (16UL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (8UL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (6UL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +/** + \brief Cortex-M55 PMU events + \note Architectural PMU events can be found in pmu_armv8.h +*/ + +#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ +#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ +#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ +#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ +#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ +#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ +#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ +#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ +#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ +#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ +#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ +#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ +#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM55_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm7.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm7.h new file mode 100644 index 0000000000..e1c31c275d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_cm7.h @@ -0,0 +1,2362 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_sc000.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_sc000.h new file mode 100644 index 0000000000..dbc755fff3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_sc000.h @@ -0,0 +1,1030 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_sc300.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_sc300.h new file mode 100644 index 0000000000..e8914ba601 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/core_sc300.h @@ -0,0 +1,1917 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.9 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
    + Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    + Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
    + Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/mpu_armv7.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/mpu_armv7.h new file mode 100644 index 0000000000..791a8dae65 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/mpu_armv7.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.1 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/mpu_armv8.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/mpu_armv8.h new file mode 100644 index 0000000000..ef44ad01df --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.2 + * @date 10. February 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/pmu_armv8.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/pmu_armv8.h new file mode 100644 index 0000000000..dbd39d20c7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.0 + * @date 24. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/tz_context.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/tz_context.h new file mode 100644 index 0000000000..0d09749f3a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/cmsis/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h new file mode 100644 index 0000000000..6b84660d63 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll.h @@ -0,0 +1,337 @@ +/** + ******************************************************************************* + * @file hc32_ll.h + * @brief This file contains HC32 Series Device Driver Library file call + * management. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_H__ +#define __HC32_LL_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_Global + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Global_Macros LL Global Macros + * @{ + */ + +/** + * @defgroup Peripheral_Register_WP_Global_Macros Peripheral Register Write Protection Global Macros + * @{ + */ +#define LL_PERIPH_EFM (1UL << 0U) +#define LL_PERIPH_FCG (1UL << 1U) +#define LL_PERIPH_GPIO (1UL << 2U) +#define LL_PERIPH_INTC (1UL << 3U) +#define LL_PERIPH_LVD (1UL << 4U) +#define LL_PERIPH_MPU (1UL << 5U) +#define LL_PERIPH_PWC_CLK_RMU (1UL << 6U) +#define LL_PERIPH_SRAM (1UL << 7U) +#define LL_PERIPH_ALL (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_GPIO | LL_PERIPH_INTC | \ + LL_PERIPH_LVD | LL_PERIPH_MPU | LL_PERIPH_SRAM | LL_PERIPH_PWC_CLK_RMU) +/** + * @} + */ + +/** + * @defgroup Timer_SW_Sync_Start_Global_Macros Timer Software Sync Start Global Macros + * @{ + */ +#define LL_SW_SYNC_START_TMR0_1_CH_A PERIC_TMR_SYNENR_TMR0U1A +#define LL_SW_SYNC_START_TMR0_1_CH_B PERIC_TMR_SYNENR_TMR0U1B +#define LL_SW_SYNC_START_TMR0_2_CH_A PERIC_TMR_SYNENR_TMR0U2A +#define LL_SW_SYNC_START_TMR0_2_CH_B PERIC_TMR_SYNENR_TMR0U2B +#define LL_SW_SYNC_START_TMR4_1 PERIC_TMR_SYNENR_TMR4U1 +#define LL_SW_SYNC_START_TMR4_2 PERIC_TMR_SYNENR_TMR4U2 +#define LL_SW_SYNC_START_TMR4_3 PERIC_TMR_SYNENR_TMR4U3 +#define LL_SW_SYNC_START_TMR6_1 PERIC_TMR_SYNENR_TMR6U1 +#define LL_SW_SYNC_START_TMR6_2 PERIC_TMR_SYNENR_TMR6U2 +#define LL_SW_SYNC_START_TMRA_1 PERIC_TMR_SYNENR_TMRAU1 +#define LL_SW_SYNC_START_TMRA_2 PERIC_TMR_SYNENR_TMRAU2 +#define LL_SW_SYNC_START_TMRA_3 PERIC_TMR_SYNENR_TMRAU3 +#define LL_SW_SYNC_START_TMRA_4 PERIC_TMR_SYNENR_TMRAU4 +#define LL_SW_SYNC_START_TMRA_5 PERIC_TMR_SYNENR_TMRAU5 +#define LL_SW_SYNC_START_TMR_ALL (LL_SW_SYNC_START_TMR0_1_CH_A | LL_SW_SYNC_START_TMR0_1_CH_B | \ + LL_SW_SYNC_START_TMR0_2_CH_A | LL_SW_SYNC_START_TMR0_2_CH_B | \ + LL_SW_SYNC_START_TMR4_1 | LL_SW_SYNC_START_TMR4_2 | \ + LL_SW_SYNC_START_TMR4_3 | LL_SW_SYNC_START_TMR6_1 | \ + LL_SW_SYNC_START_TMR6_2 | LL_SW_SYNC_START_TMRA_1 | \ + LL_SW_SYNC_START_TMRA_2 | LL_SW_SYNC_START_TMRA_3 | \ + LL_SW_SYNC_START_TMRA_4 | LL_SW_SYNC_START_TMRA_5) +/** + * @} + */ + +/* Defined use Device Driver Library */ +#if !defined (USE_DDL_DRIVER) +/** + * @brief Comment the line below if you will not use the Device Driver Library. + * In this case, the application code will be based on direct access to + * peripherals registers. + */ +/* #define USE_DDL_DRIVER */ +#endif /* USE_DDL_DRIVER */ + +/** +* @defgroup HC32_Series_DDL_Release_Version HC32 Series DDL Release Version +* @{ +*/ +#define HC32_DDL_REV_MAIN 0x01U /*!< [31:24] main version */ +#define HC32_DDL_REV_SUB1 0x01U /*!< [23:16] sub1 version */ +#define HC32_DDL_REV_SUB2 0x00U /*!< [15:8] sub2 version */ +#define HC32_DDL_REV_PATCH 0x00U /*!< [7:0] patch version */ +#define HC32_DDL_REV ((HC32_DDL_REV_MAIN << 24) | (HC32_DDL_REV_SUB1 << 16) | \ + (HC32_DDL_REV_SUB2 << 8 ) | (HC32_DDL_REV_PATCH)) +/** + * @} + */ + +/** + * @} + */ + +/* Use Device Driver Library */ +#if defined (USE_DDL_DRIVER) + +/** + * @brief Include peripheral module's header file + */ +#if (LL_ADC_ENABLE == DDL_ON) +#include "hc32_ll_adc.h" +#endif /* LL_ADC_ENABLE */ + +#if (LL_AES_ENABLE == DDL_ON) +#include "hc32_ll_aes.h" +#endif /* LL_AES_ENABLE */ + +#if (LL_AOS_ENABLE == DDL_ON) +#include "hc32_ll_aos.h" +#endif /* LL_AOS_ENABLE */ + +#if (LL_CLK_ENABLE == DDL_ON) +#include "hc32_ll_clk.h" +#endif /* LL_CLK_ENABLE */ + +#if (LL_CMP_ENABLE == DDL_ON) +#include "hc32_ll_cmp.h" +#endif /* LL_CMP_ENABLE */ + +#if (LL_CRC_ENABLE == DDL_ON) +#include "hc32_ll_crc.h" +#endif /* LL_CRC_ENABLE */ + +#if (LL_CTC_ENABLE == DDL_ON) +#include "hc32_ll_ctc.h" +#endif /* LL_CTC_ENABLE */ + +#if (LL_DAC_ENABLE == DDL_ON) +#include "hc32_ll_dac.h" +#endif /* LL_DAC_ENABLE */ + +#if (LL_DBGC_ENABLE == DDL_ON) +#include "hc32_ll_dbgc.h" +#endif /* LL_DBGC_ENABLE */ + +#if (LL_DCU_ENABLE == DDL_ON) +#include "hc32_ll_dcu.h" +#endif /* LL_DCU_ENABLE */ + +#if (LL_DMA_ENABLE == DDL_ON) +#include "hc32_ll_dma.h" +#endif /* LL_DMA_ENABLE */ + +#if (LL_EFM_ENABLE == DDL_ON) +#include "hc32_ll_efm.h" +#endif /* LL_EFM_ENABLE */ + +#if (LL_EMB_ENABLE == DDL_ON) +#include "hc32_ll_emb.h" +#endif /* LL_EMB_ENABLE */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +#include "hc32_ll_event_port.h" +#endif /* LL_EVENT_PORT_ENABLE */ + +#if (LL_FCG_ENABLE == DDL_ON) +#include "hc32_ll_fcg.h" +#endif /* LL_FCG_ENABLE */ + +#if (LL_FCM_ENABLE == DDL_ON) +#include "hc32_ll_fcm.h" +#endif /* LL_FCM_ENABLE */ + +#if (LL_GPIO_ENABLE == DDL_ON) +#include "hc32_ll_gpio.h" +#endif /* LL_GPIO_ENABLE */ + +#if (LL_HASH_ENABLE == DDL_ON) +#include "hc32_ll_hash.h" +#endif /* LL_HASH_ENABLE */ + +#if (LL_I2C_ENABLE == DDL_ON) +#include "hc32_ll_i2c.h" +#endif /* LL_I2C_ENABLE */ + +#if (LL_ICG_ENABLE == DDL_ON) +#include "hc32_ll_icg.h" +#endif /* LL_ICG_ENABLE */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) +#include "hc32_ll_interrupts.h" +#endif /* LL_INTERRUPTS_ENABLE */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) +#include "hc32_ll_keyscan.h" +#endif /* LL_KEYSCAN_ENABLE */ + +#if (LL_MCAN_ENABLE == DDL_ON) +#include "hc32_ll_mcan.h" +#endif /* LL_MCAN_ENABLE */ + +#if (LL_MPU_ENABLE == DDL_ON) +#include "hc32_ll_mpu.h" +#endif /* LL_MPU_ENABLE */ + +#if (LL_PWC_ENABLE == DDL_ON) +#include "hc32_ll_pwc.h" +#endif /* LL_PWC_ENABLE */ + +#if (LL_QSPI_ENABLE == DDL_ON) +#include "hc32_ll_qspi.h" +#endif /* LL_QSPI_ENABLE */ + +#if (LL_RMU_ENABLE == DDL_ON) +#include "hc32_ll_rmu.h" +#endif /* LL_RMU_ENABLE */ + +#if (LL_RTC_ENABLE == DDL_ON) +#include "hc32_ll_rtc.h" +#endif /* LL_RTC_ENABLE */ + +#if (LL_SMC_ENABLE == DDL_ON) +#include "hc32_ll_smc.h" +#endif /* LL_SMC_ENABLE */ + +#if (LL_SPI_ENABLE == DDL_ON) +#include "hc32_ll_spi.h" +#endif /* LL_SPI_ENABLE */ + +#if (LL_SRAM_ENABLE == DDL_ON) +#include "hc32_ll_sram.h" +#endif /* LL_SRAM_ENABLE */ + +#if (LL_SWDT_ENABLE == DDL_ON) +#include "hc32_ll_swdt.h" +#endif /* LL_SWDT_ENABLE */ + +#if (LL_TMR0_ENABLE == DDL_ON) +#include "hc32_ll_tmr0.h" +#endif /* LL_TMR0_ENABLE */ + +#if (LL_TMR4_ENABLE == DDL_ON) +#include "hc32_ll_tmr4.h" +#endif /* LL_TMR4_ENABLE */ + +#if (LL_TMR6_ENABLE == DDL_ON) +#include "hc32_ll_tmr6.h" +#endif /* LL_TMR6_ENABLE */ + +#if (LL_TMRA_ENABLE == DDL_ON) +#include "hc32_ll_tmra.h" +#endif /* LL_TMRA_ENABLE */ + +#if (LL_TRNG_ENABLE == DDL_ON) +#include "hc32_ll_trng.h" +#endif /* LL_TRNG_ENABLE */ + +#if (LL_USART_ENABLE == DDL_ON) +#include "hc32_ll_usart.h" +#endif /* LL_USART_ENABLE */ + +#if (LL_UTILITY_ENABLE == DDL_ON) +#include "hc32_ll_utility.h" +#endif /* LL_UTILITY_ENABLE */ + +#if (LL_WDT_ENABLE == DDL_ON) +#include "hc32_ll_wdt.h" +#endif /* LL_WDT_ENABLE */ + +#endif /* USE_DDL_DRIVER */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup LL_Global_Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral); +void LL_PERIPH_WP(uint32_t u32Peripheral); +void LL_TMR_SWSyncStart(uint32_t u32Tmr); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h new file mode 100644 index 0000000000..5a287bd016 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_adc.h @@ -0,0 +1,524 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.h + * @brief This file contains all the functions prototypes of the ADC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + API fixed: ADC_DeInit() + 2023-12-15 CDT Add declaration of API ADC_MxChCmd(), ADC_ConvDataAverageMxChCmd(), and add defgroup ADC_Mx_Channel + Add declaration of API ADC_GetResolution() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ADC_H__ +#define __HC32_LL_ADC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ADC + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Types ADC Global Types + * @{ + */ +/** + * @brief Structure definition of analog watchdog(AWD) configuration. + */ +typedef struct { + uint16_t u16WatchdogMode; /*!< Specifies the ADC analog watchdog mode. + This parameter can be a value of @ref ADC_AWD_Mode */ + uint16_t u16LowThreshold; /*!< Specifies the ADC analog watchdog Low threshold value. */ + uint16_t u16HighThreshold; /*!< Specifies the ADC analog watchdog High threshold value. */ +} stc_adc_awd_config_t; + +/** + * @brief Structure definition of ADC initialization. + */ +typedef struct { + uint16_t u16ScanMode; /*!< Specifies the ADC scan convert mode. + This parameter can be a value of @ref ADC_Scan_Mode */ + uint16_t u16Resolution; /*!< Specifies the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint16_t u16DataAlign; /*!< Specifies ADC data alignment. + This parameter can be a value of @ref ADC_Data_Align */ +} stc_adc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Macros ADC Global Macros + * @{ + */ + +/** + * @defgroup ADC_Sequence ADC Sequence + * @{ + */ +#define ADC_SEQ_A (0U) /*!< ADC sequence A. */ +#define ADC_SEQ_B (1U) /*!< ADC sequence B. */ +/** + * @} + */ + +/** + * @defgroup ADC_Channel ADC Channel + * @{ + */ +#define ADC_CH0 (0U) /*!< Default input pin: PA0 for ADC1, PA4 for ADC2, PE2 for ADC3. */ +#define ADC_CH1 (1U) /*!< Default input pin: PA1 for ADC1, PA5 for ADC2, PE3 for ADC3. */ +#define ADC_CH2 (2U) /*!< Default input pin: PA2 for ADC1, PA6 for ADC2, PE4 for ADC3. */ +#define ADC_CH3 (3U) /*!< Default input pin: PA3 for ADC1, PA7 for ADC2, PE12 for ADC3. */ +#define ADC_CH4 (4U) /*!< Default input pin: PA4 for ADC1, PB0 for ADC2, PE13 for ADC3. */ +#define ADC_CH5 (5U) /*!< Default input pin: PA5 for ADC1, PB1 for ADC2, PE14 for ADC3. */ +#define ADC_CH6 (6U) /*!< Default input pin: PA6 for ADC1, PC0 for ADC2, PA6 for ADC3. */ +#define ADC_CH7 (7U) /*!< Default input pin: PA7 for ADC1, PC1 for ADC2, PA7 for ADC3. */ +#define ADC_CH8 (8U) /*!< Default input pin: PB0 for ADC1, ADC2 not supported, PB0 for ADC3. */ +#define ADC_CH9 (9U) /*!< Default input pin: PB1 for ADC1, ADC2 not supported, PB1 for ADC3. */ +#define ADC_CH10 (10U) /*!< Default input pin: PC0 for ADC1, ADC2 not supported, PE15 for ADC3. */ +#define ADC_CH11 (11U) /*!< Default input pin: PC1 for ADC1, ADC2 not supported, PB10 for ADC3. */ +#define ADC_CH12 (12U) /*!< Default input pin: PC2 for ADC1, ADC2 and ADC3 not supported. */ +#define ADC_CH13 (13U) /*!< Default input pin: PC3 for ADC1, ADC2 and ADC3 not supported. */ +#define ADC_CH14 (14U) /*!< Default input pin: PC4 for ADC1, ADC2 and ADC3 not supported. */ +#define ADC_CH15 (15U) /*!< Default input pin: PC5 for ADC1, ADC2 and ADC3 not supported. */ + +#define ADC1_EXT_CH (ADC_CH15) /*!< ADC1 extended channel, internal reference voltage. */ +#define ADC2_EXT_CH (ADC_CH7) /*!< ADC2 extended channel, internal reference voltage. */ +#define ADC3_EXT_CH (ADC_CH11) /*!< ADC3 extended channel, internal reference voltage. */ +/** + * @} + */ + +/** + * @defgroup ADC_Mx_Channel ADC Channel + * @{ + */ +#define ADC_MX_CH0 (1U << 0U) /*!< ADC channel 0 position */ +#define ADC_MX_CH1 (1U << 1U) /*!< ADC channel 1 position */ +#define ADC_MX_CH2 (1U << 2U) /*!< ADC channel 2 position */ +#define ADC_MX_CH3 (1U << 3U) /*!< ADC channel 3 position */ +#define ADC_MX_CH4 (1U << 4U) /*!< ADC channel 4 position */ +#define ADC_MX_CH5 (1U << 5U) /*!< ADC channel 5 position */ +#define ADC_MX_CH6 (1U << 6U) /*!< ADC channel 6 position */ +#define ADC_MX_CH7 (1U << 7U) /*!< ADC channel 7 position */ +#define ADC_MX_CH8 (1U << 8U) /*!< ADC channel 8 position */ +#define ADC_MX_CH9 (1U << 9U) /*!< ADC channel 9 position */ +#define ADC_MX_CH10 (1U << 10U) /*!< ADC channel 10 position */ +#define ADC_MX_CH11 (1U << 11U) /*!< ADC channel 11 position */ +#define ADC_MX_CH12 (1U << 12U) /*!< ADC channel 12 position */ +#define ADC_MX_CH13 (1U << 13U) /*!< ADC channel 13 position */ +#define ADC_MX_CH14 (1U << 14U) /*!< ADC channel 14 position */ +#define ADC_MX_CH15 (1U << 15U) /*!< ADC channel 15 position */ + +#define ADC1_MX_CH_ALL (0xFFFFUL) /*!< ADC1 Channel mask position */ +#define ADC2_MX_CH_ALL (0xFFUL) /*!< ADC2 Channel mask position */ +#define ADC3_MX_CH_ALL (0xFFFUL) /*!< ADC3 Channel mask position */ +/** + * @} + */ + +/** + * @defgroup ADC_Scan_Mode ADC Scan Convert Mode + * @{ + */ +#define ADC_MD_SEQA_SINGLESHOT (0x0U) /*!< Sequence A single shot. Sequence B is disabled. */ +#define ADC_MD_SEQA_CONT (0x1U << ADC_CR0_MS_POS) /*!< Sequence A continuous. Sequence B is disabled. */ +#define ADC_MD_SEQA_SEQB_SINGLESHOT (0x2U << ADC_CR0_MS_POS) /*!< Sequence A and B both single shot. */ +#define ADC_MD_SEQA_CONT_SEQB_SINGLESHOT (0x3U << ADC_CR0_MS_POS) /*!< Sequence A continuous and sequence B single shot. */ +#define ADC_MD_SEQA_BUF (0x4U << ADC_CR0_MS_POS) /*!< Sequence A data buffer. Sequence B is disabled. */ +#define ADC_MD_SEQA_BUF_SEQB_SINGLESHOT (0x6U << ADC_CR0_MS_POS) /*!< Sequence A data buffer and sequence B single shot. */ +/** + * @} + */ + +/** + * @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */ +#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */ +#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */ +/** + * @} + */ + +/** + * @defgroup ADC_Data_Align ADC Data Align + * @{ + */ +#define ADC_DATAALIGN_RIGHT (0x0U) /*!< Right alignment of converted data. */ +#define ADC_DATAALIGN_LEFT (ADC_CR0_DFMT) /*!< Left alignment of converted data. */ +/** + * @} + */ + +/** + * @defgroup ADC_Average_Count ADC Average Count + * @{ + */ +#define ADC_AVG_CNT2 (0x0U) /*!< 2 consecutive average conversions. */ +#define ADC_AVG_CNT4 (0x1U << ADC_CR0_AVCNT_POS) /*!< 4 consecutive average conversions. */ +#define ADC_AVG_CNT8 (0x2U << ADC_CR0_AVCNT_POS) /*!< 8 consecutive average conversions. */ +#define ADC_AVG_CNT16 (0x3U << ADC_CR0_AVCNT_POS) /*!< 16 consecutive average conversions. */ +#define ADC_AVG_CNT32 (0x4U << ADC_CR0_AVCNT_POS) /*!< 32 consecutive average conversions. */ +#define ADC_AVG_CNT64 (0x5U << ADC_CR0_AVCNT_POS) /*!< 64 consecutive average conversions. */ +#define ADC_AVG_CNT128 (0x6U << ADC_CR0_AVCNT_POS) /*!< 128 consecutive average conversions. */ +#define ADC_AVG_CNT256 (0x7U << ADC_CR0_AVCNT_POS) /*!< 256 consecutive average conversions. */ +/** + * @} + */ + +/** + * @defgroup ADC_SeqA_Resume_Mode ADC Sequence A Resume Mode + * @brief After interrupted by sequence B, sequence A continues to scan from the interrupt channel or the first channel. + * @{ + */ +#define ADC_SEQA_RESUME_SCAN_CONT (0U) /*!< Scanning will continue from the interrupted channel. */ +#define ADC_SEQA_RESUME_SCAN_RESTART (ADC_CR1_RSCHSEL) /*!< Scanning will start from the first channel. */ +/** + * @} + */ + +/** + * @defgroup ADC_Sample_Mode ADC Sample Mode + * @{ + */ +#define ADC_SAMPLE_MD_NORMAL (0U) /*!< ADC normal sampling mode. */ +#define ADC_SAMPLE_MD_OVER (ADC_CR2_OVSMOD) /*!< ADC over sampling mode. */ +/** + * @} + */ + +/** + * @defgroup ADC_Over_Sample_Shift ADC Over Sample Shift + * @{ + */ +#define ADC_OVER_SAMPLE_SHIFT_0BIT (0U) /*!< Right shift 0 bit when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_1BIT (1U << ADC_CR2_OVSS_POS) /*!< Right shift 1 bit when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_2BIT (2U << ADC_CR2_OVSS_POS) /*!< Right shift 2 bits when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_3BIT (3U << ADC_CR2_OVSS_POS) /*!< Right shift 3 bits when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_4BIT (4U << ADC_CR2_OVSS_POS) /*!< Right shift 4 bits when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_5BIT (5U << ADC_CR2_OVSS_POS) /*!< Right shift 5 bits when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_6BIT (6U << ADC_CR2_OVSS_POS) /*!< Right shift 6 bits when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_7BIT (7U << ADC_CR2_OVSS_POS) /*!< Right shift 7 bits when use over sampling mode. */ +#define ADC_OVER_SAMPLE_SHIFT_8BIT (8U << ADC_CR2_OVSS_POS) /*!< Right shift 8 bits when use over sampling mode. */ +/** + * @} + */ + +/** + * @defgroup ADC_Hard_Trigger_Sel ADC Hard Trigger Selection + * @{ + */ +#define ADC_HARDTRIG_ADTRG_PIN (0x0U) /*!< Selects the following edge of pin ADTRG as the trigger of ADC sequence. */ +#define ADC_HARDTRIG_EVT0 (ADC_TRGSR_TRGSELA_0) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL0(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT1 (ADC_TRGSR_TRGSELA_1) /*!< Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL1(x=(null), 1, 2, 3). */ +#define ADC_HARDTRIG_EVT0_EVT1 (ADC_TRGSR_TRGSELA) /*!< Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_TRGSEL0 and register ADCx_TRGSEL1. */ +/** + * @} + */ + +/** + * @defgroup ADC_Int_Type ADC Interrupt Type + * @{ + */ +#define ADC_INT_EOCA (ADC_ICR_EOCAIEN) /*!< Interrupt of the end of conversion of sequence A. */ +#define ADC_INT_EOCB (ADC_ICR_EOCBIEN) /*!< Interrupt of the end of conversion of sequence B. */ +#define ADC_INT_ALL (ADC_INT_EOCA | ADC_INT_EOCB) +/** + * @} + */ + +/** + * @defgroup ADC_Ext_Ch_Analog_Src ADC Extended Channel Analog Source + * @{ + */ +#define ADC_EXTCH_EXTERN_ANALOG_PIN (0x0U) /*!< The analog source of extended channel is external analog input pin. */ +#define ADC_EXTCH_INTERN_ANALOG_SRC (ADC_EXCHSELR_EXCHSEL) /*!< The analog source of extended channel is internal analog signal. */ +/** + * @} + */ + +/** + * @defgroup ADC_Status_Flag ADC Status Flag + * @{ + */ +#define ADC_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */ +#define ADC_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */ +#define ADC_FLAG_NESTED (ADC_ISR_SASTPDF) /*!< Status flag of sequence A was interrupted by sequence B. */ +#define ADC_FLAG_ALL (ADC_FLAG_EOCA | ADC_FLAG_EOCB | ADC_FLAG_NESTED) +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Unit ADC Synchronous Unit + * @{ + */ +#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */ +#define ADC_SYNC_ADC1_ADC2_ADC3 (0x1U << ADC_SYNCCR_SYNCMD_POS) /*!< ADC1, ADC2 and ADC3 work synchronously. */ +/** + * @} + */ + +/** + * @defgroup ADC_Sync_Mode ADC Synchronous Mode + * @{ + */ +#define ADC_SYNC_SINGLE_DELAY_TRIG (0U) /*!< Single shot delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan once. */ +#define ADC_SYNC_SINGLE_PARALLEL_TRIG (0x2U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan once. */ +#define ADC_SYNC_CYCLIC_DELAY_TRIG (0x4U << ADC_SYNCCR_SYNCMD_POS) /*!< Cyclic delayed trigger mode. + When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + All ADCs scan cyclicly(keep scanning till you stop them). */ +#define ADC_SYNC_CYCLIC_PARALLEL_TRIG (0x6U << ADC_SYNCCR_SYNCMD_POS) /*!< Single shot parallel trigger mode. + When the trigger condition occurs, all ADCs start at the same time. + All ADCs scan cyclicly(keep scanning till you stop them). */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit + * @{ + */ +#define ADC_AWD0 (0U) /*!< ADC analog watchdog 0. */ +#define ADC_AWD1 (1U) /*!< ADC analog watchdog 1. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Int_Type ADC AWD Interrupt Type + * @{ + */ +#define ADC_AWD_INT_AWD0 (ADC_AWDCR_AWD0IEN) /*!< Interrupt of AWD0. */ +#define ADC_AWD_INT_AWD1 (ADC_AWDCR_AWD1IEN) /*!< Interrupt of AWD1. */ +#define ADC_AWD_INT_ALL (ADC_AWD_INT_AWD0 | ADC_AWD_INT_AWD1) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Mode ADC Analog Watchdog Mode + * @{ + */ +#define ADC_AWD_MD_CMP_OUT (0x0U) /*!< ADCValue > HighThreshold or ADCValue < LowThreshold */ +#define ADC_AWD_MD_CMP_IN (0x1U) /*!< LowThreshold < ADCValue < HighThreshold */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Comb_Mode ADC AWD(Analog Watchdog) Combination Mode + * @note If combination mode is valid(ADC_AWD_COMB_OR/ADC_AWD_COMB_AND/ADC_AWD_COMB_XOR) and + * the Channels selected by the AWD0 and AWD1 are deferent, make sure that the channel + * of AWD1 is converted after the channel conversion of AWD0 ends. + * @{ + */ +#define ADC_AWD_COMB_INVD (0U) /*!< Combination mode is invalid. */ +#define ADC_AWD_COMB_OR (ADC_AWDCR_AWDCM_0) /*!< The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. */ +#define ADC_AWD_COMB_AND (ADC_AWDCR_AWDCM_1) /*!< The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. */ +#define ADC_AWD_COMB_XOR (ADC_AWDCR_AWDCM) /*!< Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag + * @{ + */ +#define ADC_AWD_FLAG_AWD0 (ADC_AWDSR_AWD0F) /*!< Flag of AWD0. */ +#define ADC_AWD_FLAG_AWD1 (ADC_AWDSR_AWD1F) /*!< Flag of AWD1. */ +#define ADC_AWD_FLAG_COMB (ADC_AWDSR_AWDCMF) /*!< Flag of combination of mode. */ +#define ADC_AWD_FLAG_ALL (ADC_AWD_FLAG_AWD0 | ADC_AWD_FLAG_AWD1 | ADC_AWD_FLAG_COMB) +/** + * @} + */ + +/** + * @defgroup ADC_Remap_Pin ADC Remap Pin + * @{ + */ +#define ADC1_PIN_PA0 (0U) /*!< ADC1_IN0(PA0): default channel is ADC_CH0 of ADC1 */ +#define ADC1_PIN_PA1 (1U) /*!< ADC1_IN1(PA1): default channel is ADC_CH1 of ADC1 */ +#define ADC1_PIN_PA2 (2U) /*!< ADC1_IN2(PA2): default channel is ADC_CH2 of ADC1 */ +#define ADC1_PIN_PA3 (3U) /*!< ADC1_IN3(PA3): default channel is ADC_CH3 of ADC1 */ +#define ADC1_PIN_PA4 (4U) /*!< ADC12_IN4(PA4): default channel is ADC_CH4 of ADC1 */ +#define ADC1_PIN_PA5 (5U) /*!< ADC12_IN5(PA5): default channel is ADC_CH5 of ADC1 */ +#define ADC1_PIN_PA6 (6U) /*!< ADC123_IN6(PA6): default channel is ADC_CH6 of ADC1 */ +#define ADC1_PIN_PA7 (7U) /*!< ADC123_IN7(PA7): default channel is ADC_CH7 of ADC1 */ +#define ADC1_PIN_PB0 (8U) /*!< ADC123_IN8(PB0): default channel is ADC_CH8 of ADC1 */ +#define ADC1_PIN_PB1 (9U) /*!< ADC123_IN9(PB1): default channel is ADC_CH9 of ADC1 */ +#define ADC1_PIN_PC0 (10U) /*!< ADC12_IN10(PC0): default channel is ADC_CH10 of ADC1 */ +#define ADC1_PIN_PC1 (11U) /*!< ADC12_IN11(PC1): default channel is ADC_CH11 of ADC1 */ +#define ADC1_PIN_PC2 (12U) /*!< ADC1_IN12(PC2): default channel is ADC_CH12 of ADC1 */ +#define ADC1_PIN_PC3 (13U) /*!< ADC1_IN13(PC3): default channel is ADC_CH13 of ADC1 */ +#define ADC1_PIN_PC4 (14U) /*!< ADC1_IN14(PC4): default channel is ADC_CH14 of ADC1 */ +#define ADC1_PIN_PC5 (15U) /*!< ADC1_IN15(PC5): default channel is ADC_CH15 of ADC1 */ + +#define ADC2_PIN_PA4 (0U) /*!< ADC12_IN4(PA4): default channel is ADC_CH0 ADC2 */ +#define ADC2_PIN_PA5 (1U) /*!< ADC12_IN5(PA5): default channel is ADC_CH1 ADC2 */ +#define ADC2_PIN_PA6 (2U) /*!< ADC123_IN6(PA6): default channel is ADC_CH2 ADC2 */ +#define ADC2_PIN_PA7 (3U) /*!< ADC123_IN7(PA7): default channel is ADC_CH3 ADC2 */ +#define ADC2_PIN_PB0 (4U) /*!< ADC123_IN8(PB0): default channel is ADC_CH4 ADC2 */ +#define ADC2_PIN_PB1 (5U) /*!< ADC123_IN9(PB1): default channel is ADC_CH5 ADC2 */ +#define ADC2_PIN_PC0 (6U) /*!< ADC12_IN10(PC0): default channel is ADC_CH6 ADC2 */ +#define ADC2_PIN_PC1 (7U) /*!< ADC12_IN11(PC1): default channel is ADC_CH7 ADC2 */ + +#define ADC3_PIN_PE2 (0U) /*!< ADC3_IN0(PE2): default channel is ADC_CH0 of ADC3 */ +#define ADC3_PIN_PE3 (1U) /*!< ADC3_IN1(PE3): default channel is ADC_CH1 of ADC3 */ +#define ADC3_PIN_PE4 (2U) /*!< ADC3_IN2(PE4): default channel is ADC_CH2 of ADC3 */ +#define ADC3_PIN_PE12 (3U) /*!< ADC3_IN3(PE12): default channel is ADC_CH3 of ADC3 */ +#define ADC3_PIN_PE13 (4U) /*!< ADC3_IN4(PE13): default channel is ADC_CH4 of ADC3 */ +#define ADC3_PIN_PE14 (5U) /*!< ADC3_IN5(PE14): default channel is ADC_CH5 of ADC3 */ +#define ADC3_PIN_PA6 (6U) /*!< ADC123_IN6(PA6): default channel is ADC_CH6 of ADC3 */ +#define ADC3_PIN_PA7 (7U) /*!< ADC123_IN7(PA7): default channel is ADC_CH7 of ADC3 */ +#define ADC3_PIN_PB0 (8U) /*!< ADC123_IN8(PB0): default channel is ADC_CH8 of ADC3 */ +#define ADC3_PIN_PB1 (9U) /*!< ADC123_IN9(PB1): default channel is ADC_CH9 of ADC3 */ +#define ADC3_PIN_PE15 (10U) /*!< ADC3_IN10(PE15): default channel is ADC_CH10 of ADC3 */ +#define ADC3_PIN_PB10 (11U) /*!< ADC3_IN11(PB10): default channel is ADC_CH11 of ADC3 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup ADC_Global_Functions + * @{ + */ +/******************************************************************************* + Basic features + ******************************************************************************/ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit); +int32_t ADC_DeInit(CM_ADC_TypeDef *ADCx); +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit); +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState); +void ADC_MxChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint32_t u32MxCh, en_functional_state_t enNewState); +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime); + +/* Conversion data average calculation function. */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount); +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState); +void ADC_ConvDataAverageMxChCmd(CM_ADC_TypeDef *ADCx, uint32_t u32MxCh, en_functional_state_t enNewState); +/* Extended channel. */ +void ADC_SetExtChSrc(CM_ADC_TypeDef *ADCx, uint8_t u8ExtChSrc); +void ADC_SetSampleMode(CM_ADC_TypeDef *ADCx, uint16_t u16Mode); +void ADC_SetOverSampleShift(CM_ADC_TypeDef *ADCx, uint16_t u16ShiftValue); + +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel); +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState); +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState); +int32_t ADC_Start(CM_ADC_TypeDef *ADCx); +void ADC_Stop(CM_ADC_TypeDef *ADCx); +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); +uint16_t ADC_GetResolution(const CM_ADC_TypeDef *ADCx); +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag); +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag); +/******************************************************************************* + Advanced features + ******************************************************************************/ +/* Channel remap. */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin); +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch); +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx); + +/* Sync mode. */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay); +void ADC_SyncModeCmd(en_functional_state_t enNewState); + +/* Analog watchdog */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd); +/* Combination mode. */ +void ADC_AWD_SetCombMode(CM_ADC_TypeDef *ADCx, uint16_t u16CombMode); +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode); +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit); +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold); +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch); +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState); +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState); +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag); +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag); + +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState); +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode); +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h new file mode 100644 index 0000000000..5fb30a7f9b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aes.h @@ -0,0 +1,117 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.h + * @brief This file contains all the functions prototypes of the AES driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AES_H__ +#define __HC32_LL_AES_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AES + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Global_Macros AES Global Macros + * @{ + */ + +/** + * @defgroup AES_Key_Size AES Key Size + * @{ + */ +#define AES_KEY_SIZE_16BYTE (16U) +#define AES_KEY_SIZE_24BYTE (24U) +#define AES_KEY_SIZE_32BYTE (32U) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AES_Global_Functions + * @{ + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext); + +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext); + +int32_t AES_DeInit(void); +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h new file mode 100644 index 0000000000..505df2e1dc --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_aos.h @@ -0,0 +1,247 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.h + * @brief This file contains all the functions prototypes of the AOS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_AOS_H__ +#define __HC32_LL_AOS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_AOS + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Macros AOS Global Macros + * @{ + */ + +/** + * @defgroup AOS_Target_Select AOS Target Select + * @{ + */ +#define AOS_DCU1 (uint32_t)(&CM_AOS->DCU_TRGSEL1) +#define AOS_DCU2 (uint32_t)(&CM_AOS->DCU_TRGSEL2) +#define AOS_DCU3 (uint32_t)(&CM_AOS->DCU_TRGSEL3) +#define AOS_DCU4 (uint32_t)(&CM_AOS->DCU_TRGSEL4) +#define AOS_DMA1_0 (uint32_t)(&CM_AOS->DMA1_TRGSEL0) +#define AOS_DMA1_1 (uint32_t)(&CM_AOS->DMA1_TRGSEL1) +#define AOS_DMA1_2 (uint32_t)(&CM_AOS->DMA1_TRGSEL2) +#define AOS_DMA1_3 (uint32_t)(&CM_AOS->DMA1_TRGSEL3) +#define AOS_DMA1_4 (uint32_t)(&CM_AOS->DMA1_TRGSEL4) +#define AOS_DMA1_5 (uint32_t)(&CM_AOS->DMA1_TRGSEL5) +#define AOS_DMA2_0 (uint32_t)(&CM_AOS->DMA2_TRGSEL0) +#define AOS_DMA2_1 (uint32_t)(&CM_AOS->DMA2_TRGSEL1) +#define AOS_DMA2_2 (uint32_t)(&CM_AOS->DMA2_TRGSEL2) +#define AOS_DMA2_3 (uint32_t)(&CM_AOS->DMA2_TRGSEL3) +#define AOS_DMA2_4 (uint32_t)(&CM_AOS->DMA2_TRGSEL4) +#define AOS_DMA2_5 (uint32_t)(&CM_AOS->DMA2_TRGSEL5) +#define AOS_DMA_RC (uint32_t)(&CM_AOS->DMA_RC_TRGSEL) +#define AOS_TMR6_0 (uint32_t)(&CM_AOS->TMR6_TRGSEL0) +#define AOS_TMR6_1 (uint32_t)(&CM_AOS->TMR6_TRGSEL1) +#define AOS_TMR4_0 (uint32_t)(&CM_AOS->TMR4_TRGSEL0) +#define AOS_TMR4_1 (uint32_t)(&CM_AOS->TMR4_TRGSEL1) +#define AOS_TMR4_2 (uint32_t)(&CM_AOS->TMR4_TRGSEL2) +#define AOS_EVTPORT12 (uint32_t)(&CM_AOS->PEVNT_TRGSEL12) +#define AOS_EVTPORT34 (uint32_t)(&CM_AOS->PEVNT_TRGSEL34) +#define AOS_TMR0 (uint32_t)(&CM_AOS->TMR0_TRGSEL) +#define AOS_TMRA_0 (uint32_t)(&CM_AOS->TMRA_TRGSEL0) +#define AOS_TMRA_1 (uint32_t)(&CM_AOS->TMRA_TRGSEL1) +#define AOS_TMRA_2 (uint32_t)(&CM_AOS->TMRA_TRGSEL2) +#define AOS_TMRA_3 (uint32_t)(&CM_AOS->TMRA_TRGSEL3) +#define AOS_ADC1_0 (uint32_t)(&CM_AOS->ADC1_TRGSEL0) +#define AOS_ADC1_1 (uint32_t)(&CM_AOS->ADC1_TRGSEL1) +#define AOS_ADC2_0 (uint32_t)(&CM_AOS->ADC2_TRGSEL0) +#define AOS_ADC2_1 (uint32_t)(&CM_AOS->ADC2_TRGSEL1) +#define AOS_ADC3_0 (uint32_t)(&CM_AOS->ADC3_TRGSEL0) +#define AOS_ADC3_1 (uint32_t)(&CM_AOS->ADC3_TRGSEL1) +#define AOS_COMM_1 (uint32_t)(&CM_AOS->COMTRGSEL1) +#define AOS_COMM_2 (uint32_t)(&CM_AOS->COMTRGSEL2) + +/** + * @} + */ + +/** + * @defgroup AOS_Common_Trigger_ID AOS Common Trigger ID + * @{ + */ +#define AOS_COMM_TRIG1 (1UL << 30U) +#define AOS_COMM_TRIG2 (1UL << 31U) +#define AOS_COMM_TRIG_MASK (AOS_COMM_TRIG1 | AOS_COMM_TRIG2) + +/** + * @} + */ + +/** + * @defgroup AOS_Trigger_Select_Mask AOS Trigger Select Mask + * @{ + */ +#define AOS_TRIG_SEL_MASK (0x1FFUL) + +/** + * @} + */ + +/** + * @defgroup AOS_PLU_ID AOS PL Unit ID + * @{ + */ +#define AOS_PLU_ID0 (0UL) +#define AOS_PLU_ID1 (1UL) +#define AOS_PLU_ID2 (2UL) +#define AOS_PLU_ID3 (3UL) +/** + * @} + */ + +/** + * @defgroup AOS_PLU_SEL AOS PL Unit Selection + * @note AOS_PLU_SEL_NONE means selecting AOS source event to trigger AOS target. + * otherwise selecting ouput of selected PLU to trigger AOS target + * @{ + */ +#define AOS_PLU_SEL_UNIT0 (AOS_PLU_ID0) +#define AOS_PLU_SEL_UNIT1 (AOS_PLU_ID1) +#define AOS_PLU_SEL_UNIT2 (AOS_PLU_ID2) +#define AOS_PLU_SEL_UNIT3 (AOS_PLU_ID3) +#define AOS_PLU_SEL_NONE (0xFFFFUL) +/** + * @} + */ + +/** + * @defgroup AOS_PLU_PLInput_ID AOS PLU PL Input ID + * @{ + */ +#define AOS_PLU_PLIN_ID_A (0UL) +#define AOS_PLU_PLIN_ID_B (1UL) +#define AOS_PLU_PLIN_ID_C (2UL) +#define AOS_PLU_PLIN_ID_D (3UL) +/** + * @} + */ + +/** + * @defgroup AOS_PLU_PLInput_Src AOS PL Input Source + * @{ + */ +#define AOS_PLU_PLIN_SRC_NUM0 (0UL) +#define AOS_PLU_PLIN_SRC_NUM1 (1UL) +#define AOS_PLU_PLIN_SRC_TRIG_EVT (2UL) +#define AOS_PLU_PLIN_SRC_PORT_IN (3UL) +/** + * @} + */ + +/** + * @defgroup AOS_PLU_Mode AOS PLU logic Operation Mode + * @{ + */ +#define AOS_PLU_MODE_OR_OR (0UL) /*!< (PLINA | PLINB) | (PLINC | PLIND) */ +#define AOS_PLU_MODE_AND_OR (1UL) /*!< (PLINA & PLINB) | (PLINC & PLIND) */ +#define AOS_PLU_MODE_OR_XOR (2UL) /*!< (PLINA | PLINB) ^ (PLINC | PLIND) */ +#define AOS_PLU_MODE_AND_AND (3UL) /*!< (PLINA & PLINB) & (PLINC & PLIND) */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AOS_Global_Functions + * @{ + */ + +/** + * @brief AOS software trigger. + * @param None + * @retval None + */ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + WRITE_REG32(bCM_AOS->INTSFTTRG_b.STRG, SET); +} + +int32_t AOS_DeInit(void); +void AOS_CommonTriggerCmd(uint32_t u32Target, uint32_t u32CommonTrigger, en_functional_state_t enNewState); +void AOS_SetTriggerEventSrc(uint32_t u32Target, en_event_src_t enSource); +void AOS_PLU_SetPlinTriggerEventSrc(uint32_t u32PluId, uint32_t u32PlinId, en_event_src_t enSource); +void AOS_PLU_SetPlinSrc(uint32_t u32PluId, uint32_t u32PlinId, uint32_t u32Source); +void AOS_PLU_SetLogicOperationMode(uint32_t u32PluId, uint32_t u32Mode); +void AOS_SelectPLU(uint32_t u32Target, uint32_t u32PluSel); +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_AOS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h new file mode 100644 index 0000000000..751f021b1a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_clk.h @@ -0,0 +1,681 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.h + * @brief This file contains all the functions prototypes of the CLK driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Modify comment + Refine API CLK_XtalStdInit. and add API CLK_XtalStdCmd, CLK_SetXtalStdExceptionType + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CLK_H__ +#define __HC32_LL_CLK_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CLK + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Types CLK Global Types + * @{ + */ +/** + * @brief CLK XTAL configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< The new state of the XTAL. + This parameter can be a value of @ref CLK_XTAL_State */ + uint8_t u8Drv; /*!< The XTAL drive ability. + This parameter can be a value of @ref CLK_XTAL_Driver */ + uint8_t u8Mode; /*!< The XTAL mode selection osc or exclk. + This parameter can be a value of @ref CLK_XTAL_Mode_Selection */ + uint8_t u8StableTime; /*!< The XTAL stable time selection. + This parameter can be a value of @ref CLK_XTAL_Stable_Time_Selection */ +} stc_clock_xtal_init_t; + +/** + * @brief CLK XTAL fault detect configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< Specifies the new state of XTALSTD. + This parameter can be a value of @ref CLK_XTALSTD_State */ + uint8_t u8ExceptionType; /*!< Specifies the XTALSTD exception type. + This parameter can be a value of @ref CLK_XTALSTD_Exception_type */ +} stc_clock_xtalstd_init_t; + +/** + * @brief CLK XTAL divide structure definition + */ +typedef struct { + uint32_t u32State; /*!< The new state of the XTAL divide. + This parameter can be a value of @ref CLK_XTALDIV_State */ + uint32_t u32Num; /*!< The numerator of XTAL divide. */ + uint32_t u32Den; /*!< The denominator of XTAL divide. */ +} stc_clock_xtaldiv_init_t; + +/** + * @brief CLK XTAL32 configuration structure definition + */ +typedef struct { + uint8_t u8State; /*!< The new state of the XTAL32 divide. + This parameter can be a value of @ref CLK_XTAL32_State */ + uint8_t u8Drv; /*!< The Xtal32 drive ability setting, + This parameter can be a value of @ref CLK_XTAL32_Drive */ + uint8_t u8Filter; /*!< Xtal32 noise filter setting, + This parameter can be a value of@ref CLK_XTAL32_Filter_Selection */ +} stc_clock_xtal32_init_t; + +/** + * @brief CLK clock frequency configuration structure definition + */ +typedef struct { + union { + uint32_t SCFGR; /*!< clock frequency config register */ + struct { + uint32_t PCLK0S : 3; /*!< PCLK0 */ + uint32_t resvd0 : 1; /*!< reserved */ + uint32_t PCLK1S : 3; /*!< PCLK1 */ + uint32_t resvd1 : 1; /*!< reserved */ + uint32_t PCLK2S : 3; /*!< PCLK2 */ + uint32_t resvd2 : 1; /*!< reserved */ + uint32_t PCLK3S : 3; /*!< PCLK3 */ + uint32_t resvd3 : 1; /*!< reserved */ + uint32_t PCLK4S : 3; /*!< PCLK4 */ + uint32_t resvd4 : 1; /*!< reserved */ + uint32_t EXCKS : 3; /*!< EXCLK */ + uint32_t resvd5 : 1; /*!< reserved */ + uint32_t HCLKS : 3; /*!< HCLK */ + uint32_t resvd6 : 5; /*!< reserved */ + } SCFGR_f; + }; +} stc_clock_scale_t; + +/** + * @brief CLK PLL configuration structure definition + */ +typedef struct { + uint8_t u8PLLState; /*!< PLL new state, @ref CLK_PLL_State for details */ + union { + uint32_t PLLCFGR; /*!< PLL config register */ + struct { + uint32_t PLLM : 2; /*!< PLL M divide */ + uint32_t resvd0 : 5; /*!< reserved */ + uint32_t PLLSRC : 1; /*!< PLL/PLLA source clock select */ + uint32_t PLLN : 9; /*!< PLL N multi */ + uint32_t resvd1 : 3; /*!< reserved */ + uint32_t PLLR : 4; /*!< PLL R divide */ + uint32_t PLLQ : 4; /*!< PLL Q divide */ + uint32_t PLLP : 4; /*!< PLL P divide */ + } PLLCFGR_f; + }; +} stc_clock_pll_init_t; + +/** + * @brief CLK bus frequency structure definition + */ +typedef struct { + uint32_t u32SysclkFreq; /*!< System clock frequency. */ + uint32_t u32HclkFreq; /*!< Hclk frequency. */ + uint32_t u32Pclk0Freq; /*!< Pclk0 frequency. */ + uint32_t u32Pclk1Freq; /*!< Pclk1 frequency. */ + uint32_t u32Pclk2Freq; /*!< Pclk2 frequency. */ + uint32_t u32Pclk3Freq; /*!< Pclk3 frequency. */ + uint32_t u32Pclk4Freq; /*!< Pclk4 frequency. */ + uint32_t u32ExclkFreq; /*!< Exclk frequency. */ +} stc_clock_freq_t; + +/** + * @brief CLK PLL clock frequency structure definition + */ +typedef struct { + uint32_t u32PllVcin; /*!< PLL vcin clock frequency. */ + uint32_t u32PllVco; /*!< PLL vco clock frequency. */ + uint32_t u32PllP; /*!< PLLp clock frequency. */ + uint32_t u32PllQ; /*!< PLLq clock frequency. */ + uint32_t u32PllR; /*!< PLLr clock frequency. */ +} stc_pll_clock_freq_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Macros CLK Global Macros + * @{ + */ + +/** + * @defgroup CLK_PLL_State PLL state on or off + * @{ + */ +#define CLK_PLL_OFF (0x01U) +#define CLK_PLL_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_PLL_Source_Clock PLL source clock selection + * @{ + */ +#define CLK_PLL_SRC_XTAL (0x00UL) +#define CLK_PLL_SRC_HRC (0x01UL) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_State XTAL function config + * @{ + */ +#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP) +#define CLK_XTAL_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_Driver XTAL drive ability + * @note + * @verbatim + * High | Mid | Low | ULow | + * [20~25] | [16~20) | (8~16) | [4~8] | + * @endverbatim + * @{ + */ +#define CLK_XTAL_DRV_HIGH (0x00U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_MID (0x01U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_LOW (0x02U << CMU_XTALCFGR_XTALDRV_POS) +#define CLK_XTAL_DRV_ULOW (0x03U << CMU_XTALCFGR_XTALDRV_POS) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_Mode_Selection XTAL mode selection osc or exclk + * @{ + */ +#define CLK_XTAL_MD_OSC (0x00U) +#define CLK_XTAL_MD_EXCLK (CMU_XTALCFGR_XTALMS) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_Stable_Time_Selection XTAL stable time selection + * @note a cycle of stable counter = a cycle of LRC divide by 8 + * @{ + */ +#define CLK_XTAL_STB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */ +#define CLK_XTAL_STB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */ +#define CLK_XTAL_STB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */ +#define CLK_XTAL_STB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */ +#define CLK_XTAL_STB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */ +#define CLK_XTAL_STB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */ +#define CLK_XTAL_STB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */ +#define CLK_XTAL_STB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */ +#define CLK_XTAL_STB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */ +/** + * @} + */ + +/** + * @defgroup CLK_XTALDIV_State XTAL divide state Config + * @{ + */ +#define CLK_XTALDIV_OFF (0x00UL) +#define CLK_XTALDIV_ON (CMU_XTALDIVCR_FRADIVEN) +/** + * @} + */ + +/** + * @defgroup CLK_XTALSTD_State XTAL error detection on or off + * @{ + */ +#define CLK_XTALSTD_OFF (0x00U) +#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE) +/** + * @} + */ + +/** + * @defgroup CLK_XTALSTD_Exception_type XTALSTD exception type + * @{ + */ +#define CLK_XTALSTD_EXP_TYPE_NONE (0x00U) +#define CLK_XTALSTD_EXP_TYPE_RST (CMU_XTALSTDCR_XTALSTDRIS | CMU_XTALSTDCR_XTALSTDRE) +#define CLK_XTALSTD_EXP_TYPE_INT (CMU_XTALSTDCR_XTALSTDIE) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL32_State XTAL32 state on or off + * @{ + */ +#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP) +#define CLK_XTAL32_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL32_Drive XTAL32 drive ability + * @{ + */ +#define CLK_XTAL32_DRV_MID (0x00U) +#define CLK_XTAL32_DRV_HIGH (0x01U) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL32_Filter_Selection XTAL32 filtering selection. + * @{ + */ +#define CLK_XTAL32_FILTER_ALL_MD (0x00U) /*!< Valid in run,stop,power down mode. */ +#define CLK_XTAL32_FILTER_RUN_MD (0x01U) /*!< Valid in run mode. */ +#define CLK_XTAL32_FILTER_OFF (0x03U) /*!< Invalid in run,stop,power down mode. */ +/** + * @} + */ + +/** + * @defgroup CLK_HRC_Config HRC Config + * @{ + */ +#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP) +#define CLK_HRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_STB_Flag CLK Stable Flags + * @{ + */ +#define CLK_STB_FLAG_HRC (CMU_OSCSTBSR_HRCSTBF) +#define CLK_STB_FLAG_XTAL (CMU_OSCSTBSR_XTALSTBF) +#define CLK_STB_FLAG_PLL (CMU_OSCSTBSR_PLLHSTBF) +#define CLK_STB_FLAG_MASK (CMU_OSCSTBSR_HRCSTBF | CMU_OSCSTBSR_XTALSTBF | CMU_OSCSTBSR_PLLHSTBF) +/** + * @} + */ + +/** + * @defgroup CLK_System_Clock_Source System Clock Source + * @{ + */ +#define CLK_SYSCLK_SRC_HRC (0x00U) +#define CLK_SYSCLK_SRC_MRC (0x01U) +#define CLK_SYSCLK_SRC_LRC (0x02U) +#define CLK_SYSCLK_SRC_XTAL (0x03U) +#define CLK_SYSCLK_SRC_XTAL32 (0x04U) +#define CLK_SYSCLK_SRC_PLL (0x05U) +/** + * @} + */ + +/** + * @defgroup CLK_Bus_Clock_Sel Clock Bus Clock Category Selection + * @{ + */ +#define CLK_BUS_PCLK0 (CMU_SCFGR_PCLK0S) +#define CLK_BUS_PCLK1 (CMU_SCFGR_PCLK1S) +#define CLK_BUS_PCLK2 (CMU_SCFGR_PCLK2S) +#define CLK_BUS_PCLK3 (CMU_SCFGR_PCLK3S) +#define CLK_BUS_PCLK4 (CMU_SCFGR_PCLK4S) +#define CLK_BUS_EXCLK (CMU_SCFGR_EXCKS) +#define CLK_BUS_HCLK (CMU_SCFGR_HCLKS) +#define CLK_BUS_CLK_ALL (CLK_BUS_PCLK0 | CLK_BUS_PCLK1 | CLK_BUS_PCLK2 | CLK_BUS_PCLK3 | \ + CLK_BUS_PCLK4 | CLK_BUS_EXCLK | CLK_BUS_HCLK) +/** + * @} + */ + +/** + * @defgroup CLK_Clock_Divider Clock Divider + * @{ + */ + +/** + * @defgroup CLK_System_Clock_Divider System Clock Divider + * @{ + */ +#define CLK_SYSCLK_DIV1 (0x00U) +#define CLK_SYSCLK_DIV2 (0x01U) +#define CLK_SYSCLK_DIV4 (0x02U) +#define CLK_SYSCLK_DIV8 (0x03U) +#define CLK_SYSCLK_DIV16 (0x04U) +#define CLK_SYSCLK_DIV32 (0x05U) +#define CLK_SYSCLK_DIV64 (0x06U) +/** + * @} + */ + +/** + * @defgroup CLK_HCLK_Divider CLK HCLK Divider + * @{ + */ +#define CLK_HCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_HCLKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK1_Divider CLK PCLK1 Divider + * @{ + */ +#define CLK_PCLK1_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK1S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK4_Divider CLK PCLK4 Divider + * @{ + */ +#define CLK_PCLK4_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK4S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK3_Divider CLK PCLK3 Divider + * @{ + */ +#define CLK_PCLK3_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK3S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_EXCLK_Divider CLK EXCLK Divider + * @{ + */ +#define CLK_EXCLK_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_EXCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK2_Divider CLK PCLK2 Divider + * @{ + */ +#define CLK_PCLK2_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK2S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK0_Divider CLK PCLK0 Divider + * @{ + */ +#define CLK_PCLK0_DIV1 (CLK_SYSCLK_DIV1 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV2 (CLK_SYSCLK_DIV2 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV4 (CLK_SYSCLK_DIV4 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV8 (CLK_SYSCLK_DIV8 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV16 (CLK_SYSCLK_DIV16 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV32 (CLK_SYSCLK_DIV32 << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV64 (CLK_SYSCLK_DIV64 << CMU_SCFGR_PCLK0S_POS) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup CLK_CANCLK_Sel CLK CAN Clock Selection + * @{ + */ +#define CLK_MCANCLK_SYSCLK_DIV2 (0x01U) +#define CLK_MCANCLK_SYSCLK_DIV3 (0x02U) +#define CLK_MCANCLK_SYSCLK_DIV4 (0x03U) +#define CLK_MCANCLK_SYSCLK_DIV5 (0x04U) +#define CLK_MCANCLK_SYSCLK_DIV6 (0x05U) +#define CLK_MCANCLK_SYSCLK_DIV7 (0x06U) +#define CLK_MCANCLK_SYSCLK_DIV8 (0x07U) +#define CLK_MCANCLK_PLLQ (0x08U) +#define CLK_MCANCLK_PLLR (0x09U) +#define CLK_MCANCLK_XTAL (0x0DU) +/** + * @} + */ + +/** + * @defgroup CLK_CAN_Sel CLK CAN Channel Selection + * @{ + */ +#define CLK_MCAN1 (0x01U) +#define CLK_MCAN2 (0x02U) +/** + * @} + */ + +/** + * @defgroup CLK_PERIPH_Sel CLK Peripheral Clock Selection + * @note ADC,I2S,DAC,TRNG + * @{ + */ +/* PCLK2 is used for ADC clock, PCLK4 is used for DAC/TRNG clock */ +#define CLK_PERIPHCLK_PCLK (0x0000U) +#define CLK_PERIPHCLK_PLLQ (0x0008U) +#define CLK_PERIPHCLK_PLLR (0x0009U) +/** + * @} + */ + +/** + * @defgroup CLK_TPIU_Divider TPIU clock divider + * @{ + */ +#define CLK_TPIUCLK_DIV1 (0x00U) +#define CLK_TPIUCLK_DIV2 (0x01U) +#define CLK_TPIUCLK_DIV4 (0x02U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Channel_Sel CLK MCO Channel Select + * @{ + */ +#define CLK_MCO1 (0x00U) +#define CLK_MCO2 (0x01U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source + * @{ + */ +#define CLK_MCO_SRC_HRC (0x00U) +#define CLK_MCO_SRC_MRC (0x01U) +#define CLK_MCO_SRC_LRC (0x02U) +#define CLK_MCO_SRC_XTAL (0x03U) +#define CLK_MCO_SRC_XTAL32 (0x04U) +#define CLK_MCO_SRC_PLLP (0x06U) +#define CLK_MCO_SRC_PLLQ (0x08U) +#define CLK_MCO_SRC_HCLK (0x0BU) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler + * @{ + */ +#define CLK_MCO_DIV1 (0x00U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV2 (0x01U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV4 (0x02U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV8 (0x03U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV16 (0x04U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV32 (0x05U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV64 (0x06U << CMU_MCOCFGR_MCODIV_POS) +#define CLK_MCO_DIV128 (0x07U << CMU_MCOCFGR_MCODIV_POS) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CLK_Global_Functions + * @{ + */ +int32_t CLK_HrcCmd(en_functional_state_t enNewState); +int32_t CLK_MrcCmd(en_functional_state_t enNewState); +int32_t CLK_LrcCmd(en_functional_state_t enNewState); + +void CLK_HrcTrim(int8_t i8TrimVal); +void CLK_MrcTrim(int8_t i8TrimVal); +void CLK_LrcTrim(int8_t i8TrimVal); + +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit); +int32_t CLK_XtalCmd(en_functional_state_t enNewState); + +void CLK_XtalDivCmd(en_functional_state_t enNewState); +int32_t CLK_XtalDivStructInit(stc_clock_xtaldiv_init_t *pstcXtalDivInit); +int32_t CLK_XtalDivInit(const stc_clock_xtaldiv_init_t *pstcXtalDivInit); + +void CLK_XtalStdCmd(en_functional_state_t enNewState); +int32_t CLK_XtalStdInit(uint8_t u8State, uint8_t u8ExceptionType); +int32_t CLK_SetXtalStdExceptionType(uint8_t u8ExceptionType); +void CLK_ClearXtalStdStatus(void); +en_flag_status_t CLK_GetXtalStdStatus(void); + +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init); +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState); + +void CLK_SetPLLSrc(uint32_t u32PllSrc); +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit); +int32_t CLK_PLLCmd(en_functional_state_t enNewState); +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq); + +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div); +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag); +void CLK_SetSysClockSrc(uint8_t u8Src); +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div); +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq); +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock); + +void CLK_SetPeriClockSrc(uint16_t u16Src); +void CLK_SetCANClockSrc(uint8_t u8Unit, uint8_t u8Src); + +void CLK_TpiuClockCmd(en_functional_state_t enNewState); +void CLK_SetTpiuClockDiv(uint8_t u8Div); +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h new file mode 100644 index 0000000000..7858cbb7b9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_cmp.h @@ -0,0 +1,484 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.h + * @brief This file contains all the functions prototypes of the CMP driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CMP_H__ +#define __HC32_LL_CMP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CMP + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CMP_Global_Types CMP Global Types + * @{ + */ + +/** + * @brief CMP normal mode configuration structure + */ +typedef struct { + uint16_t u16PositiveInput; /*!< Positive(compare voltage) input @ref CMP_Positive_Input_Select */ + uint16_t u16NegativeInput; /*!< Negative(Reference voltage) input @ref CMP_Negative_Input_Select */ + uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */ + uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */ + uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */ +} stc_cmp_init_t; + +/** + * @brief CMP window mode configuration structure + */ +typedef struct { + uint16_t u16PositiveInput; /*!< Window mode Positive(compare voltage) input @ref CMP_Window_Positive_Select */ + uint16_t u16WinVolLow; /*!< CMP reference low voltage for window mode @ref CMP_Window_Low_Select */ + uint16_t u16WinVolHigh; /*!< CMP reference high voltage for window mode @ref CMP_Window_High_Select */ + uint16_t u16OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */ + uint16_t u16OutDetectEdge; /*!< Output detect edge, @ref CMP_Out_Detect_Edge_Select */ + uint16_t u16OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */ +} stc_cmp_window_init_t; + +/** + * @brief CMP blank window function configuration structure + */ +typedef struct { + uint8_t u8Mode; /*!< blank window mode select, @ref CMP_BlankWindow_Mode */ + uint16_t u16Src; /*!< blank window source select, + can be any combination of @ref CMP_BlankWindow_Src */ + uint16_t u16ValidLevelEdge; /*!< Valid level for blank window level mode @ref CMP_BlankWindow_Valid_Level + Valid edge for blank window edge mode @ref CMP_BlankWindow_Valid_Edge */ + uint16_t u16MaskWidth; /*!< Mask width when valid edge occurs for blank window edge mode, which range + from 0~255 */ + uint8_t u8OutLevel; /*!< CMP output level when blank window valid @ref CMP_BlankWindow_output_Level */ +} stc_cmp_blankwindow_t; + +/** + * @brief CMP input scan mode configuration structure + */ +typedef struct { + uint16_t u16Mode; /*!< Scan mode @ref CMP_Scan_Mode */ + uint16_t u16Src; /*!< Scan input source @ref CMP_Scan_Inm_Inp_Src */ + uint16_t u16Stable; /*!< Scan stable time value, range [0x00U ~ 0x3FU], + The CMP stable time = T(CMP clock) x u16Stable, + The stable time is recommended greater than 100nS */ + uint16_t u16Period; /*!< Scan period value, range [0x08 ~ 0xFF], + u16Period > (u16Stable + u16OutFilter * 4 + CMP_SCAN_PERIOD_IMME) + u16OutFilter is configured in CMP_NormalModeInit() function. */ +} stc_cmp_scan_config_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup CMP_Global_Macros CMP Global Macros + * @{ + */ + +#define VISR_OFFSET (8U) + +/** + * @defgroup CMP_Window_Mode_Unit CMP Window Mode Unit + * @{ + */ +#define CMP_WIN_CMP12 (0x01U) +#define CMP_WIN_CMP34 (0x02U) + +/** + * @} + */ + +/** + * @defgroup CMP_Positive_Input_Select CMP Positive(Compare) Voltage Input + * @{ + */ +#define CMP_POSITIVE_NONE (0x0U) +/* Positive input select table + CMP1 CMP2 CMP3 CMP4 +------------------------------------- +INP1 PA0 PA4 PB0 PA9 +INP2 PA1 PA5 PB1 PB1 +INP3 PA2 PA6 PC0 PC0 +INP4 PA3 PA3 PA4 PA10 +*/ +#define CMP_POSITIVE_INP1 (CMP_PMSR_CVSL_0 >> CMP_PMSR_CVSL_POS) +#define CMP_POSITIVE_INP2 (CMP_PMSR_CVSL_1 >> CMP_PMSR_CVSL_POS) +#define CMP_POSITIVE_INP3 (CMP_PMSR_CVSL_2 >> CMP_PMSR_CVSL_POS) +#define CMP_POSITIVE_INP4 (CMP_PMSR_CVSL_3 >> CMP_PMSR_CVSL_POS) +/** + * @} + */ + +/** + * @defgroup CMP_Window_Positive_Select CMP Window Mode positive(compare) Voltage + * @{ + */ +#define CMP_WIN_POSITIVE_NONE (0x0U) +/* Positive input select table for window mode + WIN_CMP12 WIN_CMP34 +---------------------------------------------- +INP1 -- -- +INP2 -- PB1 +INP3 -- PC0 +INP4 PA3 -- +*/ +#define CMP_WIN_POSITIVE_INP2 (CMP_PMSR_CVSL_1 >> CMP_PMSR_CVSL_POS) +#define CMP_WIN_POSITIVE_INP3 (CMP_PMSR_CVSL_2 >> CMP_PMSR_CVSL_POS) +#define CMP_WIN_POSITIVE_INP4 (CMP_PMSR_CVSL_3 >> CMP_PMSR_CVSL_POS) +/** + * @} + */ + +/** + * @defgroup CMP_Scan_Inp_Status CMP Scan Function Positive In INP Source + * @{ + */ +#define CMP_SCAN_STAT_INP_NONE (0U) +#define CMP_SCAN_STAT_INP1 (1U << CMP_SCMR_CVST_POS) +#define CMP_SCAN_STAT_INP2 (2U << CMP_SCMR_CVST_POS) +#define CMP_SCAN_STAT_INP3 (4U << CMP_SCMR_CVST_POS) +#define CMP_SCAN_STAT_INP4 (8U << CMP_SCMR_CVST_POS) +/** + * @} + */ + +/** + * @defgroup CMP_Scan_Inm_Status CMP Scan Function Positive In INM Source + * @{ + */ +#define CMP_SCAN_STAT_INM_NONE (0U) +#define CMP_SCAN_STAT_INM1 (1U << CMP_SCMR_RVST_POS) +#define CMP_SCAN_STAT_INM2 (2U << CMP_SCMR_RVST_POS) +#define CMP_SCAN_STAT_INM3 (4U << CMP_SCMR_RVST_POS) +#define CMP_SCAN_STAT_INM4 (8U << CMP_SCMR_RVST_POS) +/** + * @} + */ + +/** + * @defgroup CMP_Scan_Inm_Inp_Src CMP Scan Inm or Inp Source + * @{ + */ +#define CMP_SCAN_SRC_INP1_INM1 (1U) +#define CMP_SCAN_SRC_INP2_INM2 (2U) +#define CMP_SCAN_SRC_INP3_INM3 (4U) +#define CMP_SCAN_SRC_INP4_INM4 (8U) +/** + * @} + */ + +/** + * @defgroup CMP_Scan_Mode CMP Scan Mode + * @{ + */ +#define CMP_SCAN_NONE (0U) +#define CMP_SCAN_INP (CMP_MDR_CSMD_1) +#define CMP_SCAN_INM (CMP_MDR_CSMD) +/** + * @} + */ + +/** + * @defgroup CMP_Negative_Input_Select CMP Negative(Reference) Voltage Input + * @{ + */ +#define CMP_NEGATIVE_NONE (0x0U) +/* Negative input select table + CMP1 CMP2 CMP3 CMP4 +---------------------------------------------------- +INM1 PA7 PA7 PA7 PA7 +INM2 PC3 PC4 PC5 PA8 +INM3 DAO1 DAO1 DAO1 DAO1 +INM4 DAO2 DAO2 DAO2 DAO2 +*/ +#define CMP_NEGATIVE_INM1 (CMP_PMSR_RVSL_0) +#define CMP_NEGATIVE_INM2 (CMP_PMSR_RVSL_1) +#define CMP_NEGATIVE_INM3 (CMP_PMSR_RVSL_2) +#define CMP_NEGATIVE_INM4 (CMP_PMSR_RVSL_3) +/** + * @} + */ + +/** + * @defgroup CMP_Window_Low_Select CMP Window Mode Window Low Voltage + * @{ + */ +#define CMP_WIN_LOW_NONE (0x0U) +/* Window mode low voltage select table + WIN_CMP12 IN_CMP34 +------------------------------------- +INM1 PA7 PA7 +INM2 PC3 PC5 +INM3 DAO1 DAO1 +INM4 DAO2 DAO2 +*/ +#define CMP_WIN_LOW_INM1 (CMP_PMSR_RVSL_0) +#define CMP_WIN_LOW_INM2 (CMP_PMSR_RVSL_1) +#define CMP_WIN_LOW_INM3 (CMP_PMSR_RVSL_2) +#define CMP_WIN_LOW_INM4 (CMP_PMSR_RVSL_3) +/** + * @} + */ + +/** + * @defgroup CMP_Window_High_Select CMP Window Mode Window High Voltage + * @{ + */ +#define CMP_WIN_HIGH_NONE (0x0U) +/* Window mode high voltage select table + WIN_CMP12 WIN_CMP34 +------------------------------------------ +INM1 PA7 PA7 +INM2 PC4 PA8 +INM3 DAO1 DAO1 +INM4 DAO2 DAO2 +*/ +#define CMP_WIN_HIGH_INM1 (CMP_PMSR_RVSL_0) +#define CMP_WIN_HIGH_INM2 (CMP_PMSR_RVSL_1) +#define CMP_WIN_HIGH_INM3 (CMP_PMSR_RVSL_2) +#define CMP_WIN_HIGH_INM4 (CMP_PMSR_RVSL_3) +/** + * @} + */ + +/** + * @defgroup CMP_Out_Polarity_Select CMP Output Polarity + * @{ + */ +#define CMP_OUT_INVT_OFF (0x0U) /*!< CMP output don't reverse */ +#define CMP_OUT_INVT_ON (CMP_OCR_COPS) /*!< CMP output level reverse */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Detect_Edge_Select CMP Output Detect Edge + * @{ + */ +#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */ +#define CMP_DETECT_EDGS_RISING (1U << CMP_FIR_EDGS_POS) /*!< Detect rising edge */ +#define CMP_DETECT_EDGS_FALLING (2U << CMP_FIR_EDGS_POS) /*!< Detect falling edge */ +#define CMP_DETECT_EDGS_BOTH (3U << CMP_FIR_EDGS_POS) /*!< Detect rising and falling edges */ +/** + * @} + */ + +/** + * @defgroup CMP_Out_Filter CMP Output Filter Configuration + * @{ + */ +#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */ +#define CMP_OUT_FILTER_CLK (1U << CMP_FIR_FCKS_POS) +#define CMP_OUT_FILTER_CLK_DIV2 (2U << CMP_FIR_FCKS_POS) +#define CMP_OUT_FILTER_CLK_DIV4 (3U << CMP_FIR_FCKS_POS) +#define CMP_OUT_FILTER_CLK_DIV8 (4U << CMP_FIR_FCKS_POS) +#define CMP_OUT_FILTER_CLK_DIV16 (5U << CMP_FIR_FCKS_POS) +#define CMP_OUT_FILTER_CLK_DIV32 (6U << CMP_FIR_FCKS_POS) +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_Src CMP Output blank window Function Control Signal + * @{ + */ +/* Blank window PWM source select table + CMP1 CMP2 CMP3 CMP4 +------------------------------------------------------------------------ +SRC1 TIMA_1_PWM1 TIMA_3_PWM1 TIMA_1_PWM1 TIMA_2_PWM1 +SRC2 TIMA_1_PWM2 TIMA_3_PWM2 TIMA_1_PWM2 TIMA_2_PWM2 +SRC3 TIMA_1_PWM3 TIMA_3_PWM3 TIMA_1_PWM3 TIMA_2_PWM3 +SRC4 TIMA_2_PWM1 TIMA_4_PWM1 TIMA_3_PWM1 TIMA_4_PWM1 +SRC5 TIMA_2_PWM2 TIMA_4_PWM2 TIMA_3_PWM2 TIMA_4_PWM2 +SRC6 TIMA_2_PWM3 TIMA_4_PWM3 TIMA_3_PWM3 TIMA_4_PWM3 +SRC7 TIM6_1_PWMA TIM6_1_PWMA TIM6_1_PWMB TIM6_1_PWMB +SRC8 TIM6_2_PWMA TIM6_2_PWMA TIM6_2_PWMB TIM6_2_PWMB +SRC9 TIM4_1_OUH TIM4_1_OUH TIM4_2_OUH TIM4_2_OUH +SRC10 TIM4_1_OUL TIM4_1_OUL TIM4_2_OUL TIM4_2_OUL +SRC11 TIM4_1_OVH TIM4_1_OVH TIM4_2_OVH TIM4_2_OVH +SRC12 TIM4_1_OVL TIM4_1_OVL TIM4_2_OVL TIM4_2_OVL +SRC13 TIM4_1_OWH TIM4_1_OWH TIM4_2_OWH TIM4_2_OWH +SRC14 TIM4_1_OWL TIM4_1_OWL TIM4_2_OWL TIM4_2_OWL +SRC15 TIM4_1_OXH TIM4_1_OXH TIM4_2_OXH TIM4_2_OXH +SRC16 TIM4_1_OXL TIM4_1_OXL TIM4_2_OXL TIM4_2_OXL +*/ +#define CMP_BLANKWIN_SRC1 (CMP_BWSR1_CTWS0) +#define CMP_BLANKWIN_SRC2 (CMP_BWSR1_CTWS1) +#define CMP_BLANKWIN_SRC3 (CMP_BWSR1_CTWS2) +#define CMP_BLANKWIN_SRC4 (CMP_BWSR1_CTWS3) +#define CMP_BLANKWIN_SRC5 (CMP_BWSR1_CTWS4) +#define CMP_BLANKWIN_SRC6 (CMP_BWSR1_CTWS5) +#define CMP_BLANKWIN_SRC7 (CMP_BWSR1_CTWS6) +#define CMP_BLANKWIN_SRC8 (CMP_BWSR1_CTWS7) +#define CMP_BLANKWIN_SRC9 (CMP_BWSR1_CTWS8) +#define CMP_BLANKWIN_SRC10 (CMP_BWSR1_CTWS9) +#define CMP_BLANKWIN_SRC11 (CMP_BWSR1_CTWS10) +#define CMP_BLANKWIN_SRC12 (CMP_BWSR1_CTWS11) +#define CMP_BLANKWIN_SRC13 (CMP_BWSR1_CTWS12) +#define CMP_BLANKWIN_SRC14 (CMP_BWSR1_CTWS13) +#define CMP_BLANKWIN_SRC15 (CMP_BWSR1_CTWS14) +#define CMP_BLANKWIN_SRC16 (CMP_BWSR1_CTWS15) +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_Valid_Level CMP Blank Window Valid Level + * @{ + */ +#define CMP_BLANKWIN_VALID_LVL_LOW (0U) /*!< Blank window valid level is low */ +#define CMP_BLANKWIN_VALID_LVL_HIGH (1U) /*!< Blank window valid level is high */ +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_output_Level CMP Output Level When Blank Windows Valid + * @{ + */ +#define CMP_BLANKWIN_OUTPUT_LVL_LOW (0U) /*!< Output low when blank windows valid */ +#define CMP_BLANKWIN_OUTPUT_LVL_HIGH (1U << CMP_OCR_BWOL_POS) /*!< Output high when blank windows valid */ +#define CMP_BLANKWIN_OUTPUT_LVL_HOLD (2U << CMP_OCR_BWOL_POS) /*!< Output level hold when blank windows valid */ +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_Mode CMP Blank Windows Mode + * @{ + */ +#define CMP_BLANKWIN_MD_LVL (0U) +#define CMP_BLANKWIN_MD_EDGE (CMP_OCR_BWMD) +/** + * @} + */ + +/** + * @defgroup CMP_BlankWindow_Valid_Edge CMP Blank Windows valid edge for edge mode + * @{ + */ +#define CMP_BLANKWIN_VALID_EDGE_NONE (0U) /*!< Blank window valid edge none */ +#define CMP_BLANKWIN_VALID_EDGE_RISING (CMP_BWSR2_TWEG_0) /*!< Blank window rising edge valid */ +#define CMP_BLANKWIN_VALID_EDGE_FALLING (CMP_BWSR2_TWEG_1) /*!< Blank window falling edge valid */ +#define CMP_BLANKWIN_VALID_EDGE_ALL (CMP_BWSR2_TWEG_0 | CMP_BWSR2_TWEG_1) /*!< Blank window all edge valid */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CMP_Global_Functions + * @{ + */ + +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit); +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit); +void CMP_DeInit(CM_CMP_TypeDef *CMPx); + +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx); +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges); +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter); +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity); +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput); +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput); +void CMP_ClearOutDetectFlag(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges); +en_flag_status_t CMP_GetOutDetectFlag(const CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges); + +int32_t CMP_WindowModeInit(uint8_t u8WinCMPx, const stc_cmp_window_init_t *pstcCmpWindowInit); +int32_t CMP_WindowStructInit(stc_cmp_window_init_t *pstcCmpWindowInit); + +void CMP_BlankWindowSrcDisable(CM_CMP_TypeDef *CMPx, uint16_t u16BlankWindowSrc); +int32_t CMP_BlankWindowConfig(CM_CMP_TypeDef *CMPx, const stc_cmp_blankwindow_t *pstcBlankWindowConfig); +int32_t CMP_BlankWindowStructInit(stc_cmp_blankwindow_t *pstcBlankWindowConfig); +void CMP_BlankWindowCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); +void CMP_BlankWindowMode(CM_CMP_TypeDef *CMPx, uint8_t u8Mode); + +uint32_t CMP_GetScanInpSrc(CM_CMP_TypeDef *CMPx); +uint32_t CMP_GetScanInmSrc(CM_CMP_TypeDef *CMPx); +void CMP_ScanSetSrc(CM_CMP_TypeDef *CMPx, uint16_t u16Src); +void CMP_ScanSetMode(CM_CMP_TypeDef *CMPx, uint16_t u16Mode); +int32_t CMP_ScanConfig(CM_CMP_TypeDef *CMPx, stc_cmp_scan_config_t *pstcCmpScanConfig); +int32_t CMP_ScanStructInit(stc_cmp_scan_config_t *pstcCmpScanConfig); +int32_t CMP_ScanTimeConfig(CM_CMP_TypeDef *CMPx, uint16_t u16Stable, uint16_t u16Period); +void CMP_ScanCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h new file mode 100644 index 0000000000..1f5b1797d6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_crc.h @@ -0,0 +1,163 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.h + * @brief This file contains all the functions prototypes of the CRC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CRC_H__ +#define __HC32_LL_CRC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CRC + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Types CRC Global Types + * @{ + */ + +/** + * @brief CRC initialization structure definition + */ +typedef struct { + uint32_t u32Protocol; /*!< Specifies CRC Protocol. + This parameter can be a value of @ref CRC_Protocol_Control_Bit */ + uint32_t u32InitValue; /*!< Specifies initial CRC value. + This parameter can be CRC_INIT_VALUE_DEFAULT @ref CRC_Init_Value_Default */ +} stc_crc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Macros CRC Global Macros + * @{ + */ + +/** + * @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit + * @{ + */ +#define CRC_CRC16 (0x0UL) +#define CRC_CRC32 (CRC_CR_CR) +/** + * @} + */ + +/** + * @defgroup CRC_DATA_Bit_Width CRC Data Bit Width + * @{ + */ +#define CRC_DATA_WIDTH_8BIT (1U) +#define CRC_DATA_WIDTH_16BIT (2U) +#define CRC_DATA_WIDTH_32BIT (4U) +/** + * @} + */ + +/** + * @defgroup CRC_Init_Value_Default CRC Default Computation Initialization Value + * @{ + */ +#define CRC_INIT_VALUE_DEFAULT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CRC_Global_Functions + * @{ + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit); +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit); +int32_t CRC_DeInit(void); + +en_flag_status_t CRC_GetResultStatus(void); + +uint16_t CRC_CRC16_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +uint16_t CRC_CRC16_Calculate(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +en_flag_status_t CRC_CRC16_CheckData(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint16_t u16ExpectValue); +en_flag_status_t CRC_CRC16_GetCheckResult(uint16_t u16ExpectValue); + +uint32_t CRC_CRC32_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +uint32_t CRC_CRC32_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len); +en_flag_status_t CRC_CRC32_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue); +en_flag_status_t CRC_CRC32_GetCheckResult(uint32_t u32ExpectValue); + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ctc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ctc.h new file mode 100644 index 0000000000..694dd1ac04 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_ctc.h @@ -0,0 +1,249 @@ +/** + ******************************************************************************* + * @file hc32_ll_ctc.h + * @brief This file contains all the functions prototypes of the Clock Trimming + * Controller(CTC) driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_CTC_H__ +#define __HC32_LL_CTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_CTC + * @{ + */ + +#if (LL_CTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CTC_Global_Types CTC Global Types + * @{ + */ + +/** + * @brief CTC continuous trim initialization structure definition + */ +typedef struct { + uint32_t u32HrcClockDiv; /*!< HRC clock division + This parameter can be a value of @ref CTC_HRC_Clock_Division */ + uint32_t u32RefClockFreq; /*!< Reference clock frequency + This parameter should refer user manual recommended values */ + uint32_t u32RefClockSrc; /*!< Reference clock source selection + This parameter can be a value of @ref CTC_Continuous_Trim_Reference_Clock_Source */ + uint32_t u32RefClockDiv; /*!< Reference clock division + This parameter can be a value of @ref CTC_Reference_Clock_Division */ + float32_t f32TolerantErrRate; /*!< CTC tolerance deviation + This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */ + uint8_t u8TrimValue; /*!< CTC TRMVAL value + This parameter can be a value between Min_Data=0 and Max_Data=0x3F */ +} stc_ctc_ct_init_t; + +/** + * @brief CTC single trim initialization structure definition + */ +typedef struct { + uint32_t u32HrcClockDiv; /*!< HRC clock division + This parameter can be a value of @ref CTC_HRC_Clock_Division */ + uint32_t u32CtcRefEdge; /*!< CTCREF edge + This parameter can be a value of @ref CTC_Single_Trim_CTCREF_Edge */ + float32_t f32CtcRefEdgeTime; /*!< CTCREF edge time(unit:S) + This parameter should refer user actual CTCREF edge time */ + float32_t f32TolerantErrRate; /*!< CTC tolerance deviation + This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */ + uint8_t u8TrimValue; /*!< CTC TRMVAL value + This parameter can be a value between Min_Data=0 and Max_Data=0x3F */ +} stc_ctc_st_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CTC_Global_Macros CTC Global Macros + * @{ + */ + +/** + * @defgroup CTC_Continuous_Trim_Reference_Clock_Source CTC Continuous Trim Reference Clock Source + * @{ + */ +#define CTC_REF_CLK_SRC_CTCREF (0UL) /*!< Clock source: CTCREF */ +#define CTC_REF_CLK_SRC_XTAL (CTC_CR1_REFCKS) /*!< Clock source: XTAL */ +#define CTC_REF_CLK_SRC_XTAL32 (CTC_CR1_REFCKS_1) /*!< Clock source: XTAL32 */ +/** + * @} + */ + +/** + * @defgroup CTC_Flag CTC Flag + * @{ + */ +#define CTC_FLAG_TRIM_OK (CTC_STR_TRIMOK) /*!< Trimming OK flag */ +#define CTC_FLAG_TRIM_OVF (CTC_STR_TRMOVF) /*!< Trimming overflow flag */ +#define CTC_FLAG_TRIM_UDF (CTC_STR_TRMUDF) /*!< Trimming underflow flag */ +#define CTC_FLAG_BUSY (CTC_STR_CTCBSY) /*!< CTC busy flag */ +#define CTC_FLAG_ALL (CTC_FLAG_TRIM_OVF | CTC_FLAG_TRIM_UDF | \ + CTC_FLAG_TRIM_OK | CTC_FLAG_BUSY) +/** + * @} + */ + +/** + * @defgroup CTC_Reference_Clock_Division CTC Reference Clock Division + * @{ + */ +#define CTC_REF_CLK_DIV2 (0UL) /*!< REFCLK/2 */ +#define CTC_REF_CLK_DIV4 (1UL) /*!< REFCLK/4 */ +#define CTC_REF_CLK_DIV8 (2UL) /*!< REFCLK/8 */ +#define CTC_REF_CLK_DIV16 (3UL) /*!< REFCLK/16 */ +#define CTC_REF_CLK_DIV64 (4UL) /*!< REFCLK/64 */ +#define CTC_REF_CLK_DIV256 (5UL) /*!< REFCLK/256 */ +#define CTC_REF_CLK_DIV1024 (6UL) /*!< REFCLK/1024 */ +#define CTC_REF_CLK_DIV4096 (7UL) /*!< REFCLK/4096 */ +/** + * @} + */ + +/** + * @defgroup CTC_HRC_Clock_Division CTC HRC Clock Division + * @{ + */ +#define CTC_HRC_CLK_DIV1 (0UL) /*!< HRCCLK/1 */ +#define CTC_HRC_CLK_DIV2 (1UL) /*!< HRCCLK/2 */ +#define CTC_HRC_CLK_DIV4 (2UL) /*!< HRCCLK/4 */ +#define CTC_HRC_CLK_DIV8 (3UL) /*!< HRCCLK/8 */ +#define CTC_HRC_CLK_DIV32 (4UL) /*!< HRCCLK/32 */ +#define CTC_HRC_CLK_DIV128 (5UL) /*!< HRCCLK/128 */ +#define CTC_HRC_CLK_DIV512 (6UL) /*!< HRCCLK/512 */ +#define CTC_HRC_CLK_DIV2048 (7UL) /*!< HRCCLK/2048 */ +/** + * @} + */ + +/** + * @defgroup CTC_Single_Trim_CTCREF_Edge CTC Single Trim CTCREF Edge + * @{ + */ +#define CTC_CTCREF_RISING_RISING (0UL) /*!< CTC trim between CTCREF rising and CTCREF rising */ +#define CTC_CTCREF_RISING_FALLING (CTC_CR1_REFEDG_0) /*!< CTC trim between CTCREF rising and CTCREF failing */ +#define CTC_CTCREF_FALLING_RISING (CTC_CR1_REFEDG_1) /*!< CTC trim between CTCREF failing and CTCREF rising */ +#define CTC_CTCREF_FALLING_FALLING (CTC_CR1_REFEDG) /*!< CTC trim between CTCREF failing and CTCREF failing */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CTC_Global_Functions + * @{ + */ + +/** + * @brief Start CTC trimming. + * @param None + * @retval None + */ +__STATIC_INLINE void CTC_Start(void) +{ + SET_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN); +} + +/** + * @brief Stop CTC trimming. + * @param None + * @retval None + */ +__STATIC_INLINE void CTC_Stop(void) +{ + CLR_REG32_BIT(CM_CTC->CR1, CTC_CR1_CTCEN); +} + +int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit); +int32_t CTC_CT_Init(const stc_ctc_ct_init_t *pstcCtcInit); + +int32_t CTC_ST_StructInit(stc_ctc_st_init_t *pstcCtcInit); +int32_t CTC_ST_Init(const stc_ctc_st_init_t *pstcCtcInit); + +int32_t CTC_DeInit(void); +void CTC_IntCmd(en_functional_state_t enNewState); +en_flag_status_t CTC_GetStatus(uint32_t u32Flag); +void CTC_SetTrimValue(uint8_t u8TrimValue); +uint8_t CTC_GetTrimValue(void); +void CTC_SetReloadValue(uint16_t u16ReloadValue); +uint16_t CTC_GetReloadValue(void); +void CTC_SetOffsetValue(uint8_t u8OffsetValue); +uint8_t CTC_GetOffsetValue(void); + +uint16_t CTC_GetCountValue(void); + +/** + * @} + */ + +#endif /* LL_CTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_CTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dac.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dac.h new file mode 100644 index 0000000000..2dd8263747 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dac.h @@ -0,0 +1,190 @@ +/** + ******************************************************************************* + * @file hc32_ll_dac.h + * @brief This file contains all the functions prototypes of the DAC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DAC_H__ +#define __HC32_LL_DAC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DAC + * @{ + */ + +#if (LL_DAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DAC_Global_Types DAC Global Types + * @{ + */ + +/** + * @brief Structure definition of DAC initialization. + */ +typedef struct { + uint16_t u16Src; /*!< Data source to be converted + This parameter can be a value of @ref DAC_DATA_SRC */ + en_functional_state_t enOutput; /*!< Enable or disable analog output + This parameter can be a value of @ref en_functional_state_t */ +} stc_dac_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup DAC_Global_Macros DAC Global Macros + * @{ + */ + +/** + * @defgroup DAC_CH DAC channel + * @{ + */ +#define DAC_CH1 (0U) +#define DAC_CH2 (1U) +/** + * @} + */ + +/** + * @defgroup DAC_DATA_SRC DAC data source + * @{ + */ +#define DAC_DATA_SRC_DATAREG (0U) +#define DAC_DATA_SRC_DCU (DAC_DACR_EXTDSL1) +/** + * @} + */ + +/** + * @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern + * @{ + */ +#define DAC_DATA_ALIGN_LEFT (DAC_DACR_DPSEL) +#define DAC_DATA_ALIGN_RIGHT (0U) +/** + * @} + */ + +/** + * @defgroup DAC_RESOLUTION DAC resolution + * @{ + */ +#define DAC_RESOLUTION_12BIT (12U) +/** + * @} + */ + +/** + * @defgroup DAC_ADP_SELECT DAC ADCx priority select + * @{ + */ +#define DAC_ADP_SEL_ADC1 (DAC_DAADPCR_ADCSL1) +#define DAC_ADP_SEL_ADC2 (DAC_DAADPCR_ADCSL2) +#define DAC_ADP_SEL_ADC3 (DAC_DAADPCR_ADCSL3) +#define DAC_ADP_SEL_ALL (DAC_DAADPCR_ADCSL1 | DAC_DAADPCR_ADCSL2 | DAC_DAADPCR_ADCSL3) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DAC_Global_Functions + * @{ + */ + +int32_t DAC_StructInit(stc_dac_init_t *pstcDacInit); +int32_t DAC_Init(CM_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcDacInit); +int32_t DAC_DeInit(CM_DAC_TypeDef *DACx); + +void DAC_SetDataSrc(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src); +void DAC_DataRegAlignConfig(CM_DAC_TypeDef *DACx, uint16_t u16Align); +void DAC_OutputCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState); +void DAC_AMPCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState); +void DAC_ADCPrioCmd(CM_DAC_TypeDef *DACx, en_functional_state_t enNewState); +void DAC_ADCPrioConfig(CM_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState); + +int32_t DAC_Start(CM_DAC_TypeDef *DACx, uint16_t u16Ch); +int32_t DAC_Stop(CM_DAC_TypeDef *DACx, uint16_t u16Ch); +void DAC_StartDualCh(CM_DAC_TypeDef *DACx); +void DAC_StopDualCh(CM_DAC_TypeDef *DACx); + +void DAC_SetChData(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Data); +void DAC_SetDualChData(CM_DAC_TypeDef *DACx, uint16_t u16Data1, uint16_t u16Data2); +int32_t DAC_GetChConvertState(const CM_DAC_TypeDef *DACx, uint16_t u16Ch); + +/** + * @} + */ + +#endif /* LL_DAC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DAC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dbgc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dbgc.h new file mode 100644 index 0000000000..c90795d341 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dbgc.h @@ -0,0 +1,148 @@ +/** + ******************************************************************************* + * @file hc32_ll_dbgc.h + * @brief This file contains all the functions prototypes of the DBGC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Remove API DBGC_GetChipID() + Add macro definition DBGC_Trace_Mode + Add declaration of API DBGC_TraceIoCmd,DBGC_TraceModeConfig + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DBGC_H__ +#define __HC32_LL_DBGC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DBGC + * @{ + */ + +#if (LL_DBGC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DBGC_Global_Macros DBGC Global Macros + * @{ + */ + +/** + * @defgroup DBGC_Periph_Sel DBGC Periph Selection + * @{ + */ +#define DBGC_PERIPH_SWDT (DBGC_MCUSTPCTL_SWDTSTP) +#define DBGC_PERIPH_WDT (DBGC_MCUSTPCTL_WDTSTP ) +#define DBGC_PERIPH_RTC (DBGC_MCUSTPCTL_RTCSTP ) +#define DBGC_PERIPH_TMR0_1 (DBGC_MCUSTPCTL_M06STP) +#define DBGC_PERIPH_TMR0_2 (DBGC_MCUSTPCTL_M07STP) +#define DBGC_PERIPH_TMR4_1 (DBGC_MCUSTPCTL_M12STP) +#define DBGC_PERIPH_TMR4_2 (DBGC_MCUSTPCTL_M13STP) +#define DBGC_PERIPH_TMR4_3 (DBGC_MCUSTPCTL_M14STP) +#define DBGC_PERIPH_TMR6_1 (DBGC_MCUSTPCTL_M15STP) +#define DBGC_PERIPH_TMR6_2 (DBGC_MCUSTPCTL_M16STP) +/** + * @} + */ + +/** + * @defgroup DBGC_Periph2_Sel DBGC Periph2 Selection + * @{ + */ +#define DBGC_PERIPH_TMRA_1 (DBGC_MCUSTPCTL2_M32STP) +#define DBGC_PERIPH_TMRA_2 (DBGC_MCUSTPCTL2_M33STP) +#define DBGC_PERIPH_TMRA_3 (DBGC_MCUSTPCTL2_M34STP) +#define DBGC_PERIPH_TMRA_4 (DBGC_MCUSTPCTL2_M35STP) +#define DBGC_PERIPH_TMRA_5 (DBGC_MCUSTPCTL2_M36STP) +/** + * @} + */ + +/** + * @defgroup DBGC_Trace_Mode DBGC trace mode + * @{ + */ +#define DBGC_TRACE_ASYNC (0UL) +#define DBGC_TRACE_SYNC_1BIT (DBGC_MCUTRACECTL_TRACEMODE_0) +#define DBGC_TRACE_SYNC_2BIT (DBGC_MCUTRACECTL_TRACEMODE_1) +#define DBGC_TRACE_SYNC_4BIT (DBGC_MCUTRACECTL_TRACEMODE) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DBGC_Global_Functions + * @{ + */ +void DBGC_PeriphCmd(uint32_t u32Periph, en_functional_state_t enNewState); +void DBGC_Periph2Cmd(uint32_t u32Periph, en_functional_state_t enNewState); +void DBGC_TraceIoCmd(en_functional_state_t enNewState); +void DBGC_TraceModeConfig(uint32_t u32TraceMode); +/** + * @} + */ + +#endif /* LL_DBGC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DBGC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h new file mode 100644 index 0000000000..22f3fa6c79 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dcu.h @@ -0,0 +1,298 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.h + * @brief This file contains all the functions prototypes of the DCU(Data + * Computing Unit) driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DCU_H__ +#define __HC32_LL_DCU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DCU + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Types DCU Global Types + * @{ + */ + +/** + * @brief DCU initialization structure definition + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies DCU operation. + This parameter can be a value of @ref DCU_Mode */ + uint32_t u32DataWidth; /*!< Specifies DCU data width. + This parameter can be a value of @ref DCU_Data_Width */ +} stc_dcu_init_t; + +/** + * @brief DCU wave output configure structure definition + */ +typedef struct { + uint32_t u32LowerLimit; /*!< Defines the wave lower limit of the wave amplitude. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ + uint32_t u32UpperLimit; /*!< Defines the upper limit of the wave amplitude. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ + uint32_t u32Step; /*!< Defines the increasing/decreasing step. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ +} stc_dcu_wave_config_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Macros DCU Global Macros + * @{ + */ + +/** + * @defgroup DCU_Data_Width DCU Data Width + * @{ + */ +#define DCU_DATA_WIDTH_8BIT (0UL) /*!< DCU data width: 8 bit */ +#define DCU_DATA_WIDTH_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data width: 16 bit */ +#define DCU_DATA_WIDTH_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data width: 32 bit */ +/** + * @} + */ + +/** + * @defgroup DCU_Compare_Trigger_Condition DCU Compare Trigger Condition + * @{ + */ +#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */ +#define DCU_CMP_TRIG_DATA0_DATA1_DATA2 (DCU_CTL_COMPTRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */ +/** + * @} + */ + +/** + * @defgroup DCU_Mode DCU Mode + * @{ + */ +#define DCU_MD_INVD (0UL) /*!< DCU invalid */ +#define DCU_MD_ADD (1UL) /*!< DCU add operation */ +#define DCU_MD_SUB (2UL) /*!< DCU sub operation */ +#define DCU_MD_HW_ADD (3UL) /*!< DCU hardware trigger add */ +#define DCU_MD_HW_SUB (4UL) /*!< DCU hardware trigger sub */ +#define DCU_MD_CMP (5UL) /*!< DCU compare */ +#define DCU_MD_TRIANGLE_WAVE (8UL) /*!< DCU triangle wave output mode */ +#define DCU_MD_SAWTOOTH_WAVE_INC (9UL) /*!< DCU increasing sawtooth wave output mode */ +#define DCU_MD_SAWTOOTH_WAVE_DEC (10UL) /*!< DCU decreasing sawtooth wave output mode */ +/** + * @} + */ + +/** + * @defgroup DCU_Flag DCU Flag + * @{ + */ +#define DCU_FLAG_CARRY (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */ +#define DCU_FLAG_DATA0_LT_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */ +#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */ +#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */ +#define DCU_FLAG_DATA0_LT_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */ +#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */ +#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */ +#define DCU_FLAG_SAWTOOTH_WAVE_RELOAD (DCU_FLAG_FLAG_RLD) /*!< DCU sawtooth wave mode reload interrupt */ +#define DCU_FLAG_TRIANGLE_WAVE_BOTTOM (DCU_FLAG_FLAG_BTM) /*!< DCU triangle wave mode bottom interrupt */ +#define DCU_FLAG_TRIANGLE_WAVE_TOP (DCU_FLAG_FLAG_TOP) /*!< DCU triangle wave mode top interrupt */ + +#define DCU_FLAG_ALL (0x00000E7FUL) +/** + * @} + */ + +/** + * @defgroup DCU_Category DCU Category + * @{ + */ +#define DCU_CATEGORY_OP (0UL) /*!< DCU operation result(overflow/underflow) */ +#define DCU_CATEGORY_CMP_WIN (1UL) /*!< DCU comparison(window) */ +#define DCU_CATEGORY_CMP_NON_WIN (2UL) /*!< DCU comparison(non-window) */ +#define DCU_CATEGORY_WAVE (3UL) /*!< DCU wave mode(sawtooth/triangle wave) */ +/** + * @} + */ + +/** + * @defgroup DCU_Interrupt_Type DCU Interrupt Type + * @{ + */ +/** + * @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt + * @note Interrupt type DCU_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_NON_WIN + * @{ + */ +#define DCU_INT_CMP_DATA0_LT_DATA2 (DCU_INTEVTSEL_SEL_LS2) /*!< DCU DATA0 < DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTEVTSEL_SEL_EQ2) /*!< DCU DATA0 = DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTEVTSEL_SEL_GT2) /*!< DCU DATA0 > DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_LT_DATA1 (DCU_INTEVTSEL_SEL_LS1) /*!< DCU DATA0 < DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTEVTSEL_SEL_EQ1) /*!< DCU DATA0 = DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTEVTSEL_SEL_GT1) /*!< DCU DATA0 > DATA1 interrupt */ +#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LT_DATA2 | \ + DCU_INT_CMP_DATA0_EQ_DATA2 | \ + DCU_INT_CMP_DATA0_GT_DATA2 | \ + DCU_INT_CMP_DATA0_LT_DATA1 | \ + DCU_INT_CMP_DATA0_EQ_DATA1 | \ + DCU_INT_CMP_DATA0_GT_DATA1) +/** + * @} + */ + +/** + * @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt + * @note Interrupt type DCU_Window_Compare_Interrupt is valid when only select DCU_CATEGORY_CMP_WIN + * @{ + */ +#define DCU_INT_CMP_WIN_INSIDE (DCU_INTEVTSEL_SEL_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */ +#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTEVTSEL_SEL_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */ +#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | DCU_INT_CMP_WIN_OUTSIDE) +/** + * @} + */ + +/** + * @defgroup DCU_Operation_Interrupt DCU Operation Interrupt + * @note DCU_Window_Compare_Interrupt selection is valid when only select DCU_CATEGORY_OP + * @{ + */ +#define DCU_INT_OP_CARRY (DCU_INTEVTSEL_SEL_OP) /*!< DCU addition overflow or subtraction underflow interrupt */ +/** + * @} + */ + +/** + * @defgroup DCU_Wave_Mode_Interrupt DCU Wave Mode Interrupt + * @note Interrupt type DCU_Wave_Mode_Interrupt is valid when only select DCU_CATEGORY_WAVE + * @{ + */ +#define DCU_INT_TRIANGLE_WAVE_BOTTOM (DCU_INTEVTSEL_SEL_BTM) /*!< DCU triangle wave mode bottom interrupt */ +#define DCU_INT_TRIANGLE_WAVE_TOP (DCU_INTEVTSEL_SEL_TOP) /*!< DCU triangle wave mode top interrupt */ +#define DCU_INT_WAVE_MD_ALL (DCU_INT_TRIANGLE_WAVE_TOP | \ + DCU_INT_TRIANGLE_WAVE_BOTTOM) +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup DCU_Data_Register_Index DCU Data Register Index + * @{ + */ +#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */ +#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */ +#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DCU_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit); +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit); +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx); + +int32_t DCU_WaveConfig(CM_DCU_TypeDef *DCUx, const stc_dcu_wave_config_t *pstcWaveConfig); + +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode); +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth); +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond); + +/* Interrupt and flag management functions */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState); +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState); + +/* Read and write functions */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data); +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data); +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data); + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h new file mode 100644 index 0000000000..c829f00e65 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_def.h @@ -0,0 +1,390 @@ +/** + ******************************************************************************* + * @file hc32_ll_def.h + * @brief This file contains LL common definitions: enumeration, macros and + * structures definitions. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DEF_H__ +#define __HC32_LL_DEF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + +/** + * @addtogroup LL_Common + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Types LL Common Global Types + * @{ + */ + +/** + * @brief Single precision floating point number (4 byte) + */ +typedef float float32_t; + +/** + * @brief Double precision floating point number (8 byte) + */ +typedef double float64_t; + +/** + * @brief Function pointer type to void/void function + */ +typedef void (*func_ptr_t)(void); + +/** + * @brief Functional state + */ +typedef enum { + DISABLE = 0U, + ENABLE = 1U, +} en_functional_state_t; + +/** + * @brief Flag status + */ +typedef enum { + RESET = 0U, + SET = 1U, +} en_flag_status_t, en_int_status_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup LL_Common_Global_Macros LL Common Global Macros + * @{ + */ + +/** + * @defgroup Compiler_Macros Compiler Macros + * @{ + */ +#ifndef __UNUSED +#define __UNUSED __attribute__((unused)) +#endif /* __UNUSED */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned(4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((section("RAMCODE"))) +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"))) +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE __attribute__((optnone)) +#endif /* __NO_OPTIMIZE */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __attribute__((aligned (4))) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) +/* Usage: __RAM_FUNC void foo(void) */ +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".noinit"))) +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE __attribute__((optimize("O0"))) +#endif /* __NO_OPTIMIZE */ +#elif defined (__ICCARM__) /*!< IAR Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __weak +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN _Pragma("data_alignment=4") +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE _Pragma("optimize = no_inline") +#endif /* __NOINLINE */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __ramfunc +#endif /* __RAM_FUNC */ +#ifndef __NO_INIT +#define __NO_INIT __no_init +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE _Pragma("optimize=none") +#endif /* __NO_OPTIMIZE */ +#elif defined (__CC_ARM) /*!< ARM Compiler */ +#ifndef __WEAKDEF +#define __WEAKDEF __attribute__((weak)) +#endif /* __WEAKDEF */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN __align(4) +#endif /* __ALIGN_BEGIN */ +#ifndef __NOINLINE +#define __NOINLINE __attribute__((noinline)) +#endif /* __NOINLINE */ +#ifndef __NO_INIT +#define __NO_INIT __attribute__((section(".bss.noinit"), zero_init)) +#endif /* __NO_INIT */ +#ifndef __NO_OPTIMIZE +#define __NO_OPTIMIZE +#endif /* __NO_OPTIMIZE */ +/* RAM functions are defined using the toolchain options. +Functions that are executed in RAM should reside in a separate source module. +Using the 'Options for File' dialog you can simply change the 'Code / Const' +area of a module to a memory space in physical RAM. */ +#ifndef __RAM_FUNC +#define __RAM_FUNC __attribute__((section("RAMCODE"))) +#endif /* __RAM_FUNC */ +/* Suppress warning message: extended constant initializer used */ +#pragma diag_suppress 1296 +#else +#error "unsupported compiler!!" +#endif +/** + * @} + */ + +/** + * @defgroup Extend_Macros Extend Macros + * @{ + */ +/* Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U)) + +/* BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU)) + +/* Returns the dimension of an array */ +#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0]))) + +/* Returns the minimum value out of two values */ +#define LL_MIN(x, y) ((x) < (y) ? (x) : (y)) + +/* Returns the maximum value out of two values */ +#define LL_MAX(x, y) ((x) > (y) ? (x) : (y)) +/** + * @} + */ + +/** + * @defgroup Check_Parameters_Validity Check Parameters Validity + * @{ + */ + +/* Check Functional State */ +#define IS_FUNCTIONAL_STATE(state) (((state) == DISABLE) || ((state) == ENABLE)) + +/** + * @defgroup Check_Address_Align_Validity Check Address Align Validity + * @{ + */ +#define IS_ADDR_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL))) +#define IS_ADDR_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL)) +#define IS_ADDR_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup Peripheral_Bit_Band Peripheral Bit Band + * @{ + */ +#define __PERIPH_BIT_BAND_BASE (0x42000000UL) +#define __PERIPH_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIPH_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __PERIPH_BIT_BAND_BASE) +#define PERIPH_BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup Generic_Error_Codes Generic Error Codes + * @{ + */ +#define LL_OK (0) /*!< No error */ +#define LL_ERR (-1) /*!< Non-specific error code */ +#define LL_ERR_UNINIT (-2) /*!< Module (or part of it) was not initialized properly */ +#define LL_ERR_INVD_PARAM (-3) /*!< Provided parameter is not valid */ +#define LL_ERR_INVD_MD (-4) /*!< Operation not allowed in current mode */ +#define LL_ERR_NOT_RDY (-5) /*!< A requested final state is not reached */ +#define LL_ERR_BUSY (-6) /*!< A conflicting or requested operation is still in progress */ +#define LL_ERR_ADDR_ALIGN (-7) /*!< Address alignment does not match */ +#define LL_ERR_TIMEOUT (-8) /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */ +#define LL_ERR_BUF_EMPTY (-9) /*!< Circular buffer can not be read because the buffer is empty */ +#define LL_ERR_BUF_FULL (-10) /*!< Circular buffer can not be written because the buffer is full */ +/** + * @} + */ + +/** + * @defgroup Chip_Module_Switch Chip Module Switch + * @{ + */ +#define DDL_ON (1U) +#define DDL_OFF (0U) +/** + * @} + */ + +/** + * @defgroup Bit_Mask_Macros Bit Mask Macros + * @{ + */ +#define BIT_MASK_00 (1UL << 0U) +#define BIT_MASK_01 (1UL << 1U) +#define BIT_MASK_02 (1UL << 2U) +#define BIT_MASK_03 (1UL << 3U) +#define BIT_MASK_04 (1UL << 4U) +#define BIT_MASK_05 (1UL << 5U) +#define BIT_MASK_06 (1UL << 6U) +#define BIT_MASK_07 (1UL << 7U) +#define BIT_MASK_08 (1UL << 8U) +#define BIT_MASK_09 (1UL << 9U) +#define BIT_MASK_10 (1UL << 10U) +#define BIT_MASK_11 (1UL << 11U) +#define BIT_MASK_12 (1UL << 12U) +#define BIT_MASK_13 (1UL << 13U) +#define BIT_MASK_14 (1UL << 14U) +#define BIT_MASK_15 (1UL << 15U) +#define BIT_MASK_16 (1UL << 16U) +#define BIT_MASK_17 (1UL << 17U) +#define BIT_MASK_18 (1UL << 18U) +#define BIT_MASK_19 (1UL << 19U) +#define BIT_MASK_20 (1UL << 20U) +#define BIT_MASK_21 (1UL << 21U) +#define BIT_MASK_22 (1UL << 22U) +#define BIT_MASK_23 (1UL << 23U) +#define BIT_MASK_24 (1UL << 24U) +#define BIT_MASK_25 (1UL << 25U) +#define BIT_MASK_26 (1UL << 26U) +#define BIT_MASK_27 (1UL << 27U) +#define BIT_MASK_28 (1UL << 28U) +#define BIT_MASK_29 (1UL << 29U) +#define BIT_MASK_30 (1UL << 30U) +#define BIT_MASK_31 (1UL << 31U) +/** + * @} + */ + +/** + * @defgroup Register_Macros Register Macros + * @{ + */ +#define RW_MEM8(addr) (*(volatile uint8_t *)(addr)) +#define RW_MEM16(addr) (*(volatile uint16_t *)(addr)) +#define RW_MEM32(addr) (*(volatile uint32_t *)(addr)) + +#define SET_REG_BIT(REG, BIT) ((REG) |= (BIT)) +#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT))) +#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT))) +#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT))) + +#define CLR_REG_BIT(REG, BIT) ((REG) &= (~(BIT))) +#define CLR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT))))) +#define CLR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT))))) +#define CLR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT))))) + +#define READ_REG_BIT(REG, BIT) ((REG) & (BIT)) +#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT))) +#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT))) +#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT))) + +#define CLR_REG(REG) ((REG) = (0U)) +#define CLR_REG8(REG) ((REG) = ((uint8_t)(0U))) +#define CLR_REG16(REG) ((REG) = ((uint16_t)(0U))) +#define CLR_REG32(REG) ((REG) = ((uint32_t)(0UL))) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL))) +#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL))) +#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL))) + +#define READ_REG(REG) (REG) +#define READ_REG8(REG) (REG) +#define READ_REG16(REG) (REG) +#define READ_REG32(REG) (REG) + +#define MODIFY_REG(REGS, CLRMASK, SETMASK) (WRITE_REG((REGS), (((READ_REG(REGS)) & (~(CLRMASK))) | ((SETMASK) & (CLRMASK))))) +#define MODIFY_REG8(REGS, CLRMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLRMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLRMASK))))) +#define MODIFY_REG16(REGS, CLRMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLRMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLRMASK))))) +#define MODIFY_REG32(REGS, CLRMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLRMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLRMASK))))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DEF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h new file mode 100644 index 0000000000..00e35ee50c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_dma.h @@ -0,0 +1,587 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.h + * @brief This file contains all the functions prototypes of the DMA driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Add API DMA_SetDataWidth() + Delete group DMA_AHB_HPROT_Config + Delete API DMA_AHB_HProtPrivilegeCmd() + 2023-12-15 CDT Modify API input param type:u16->u32 + Add structure stc_dma_rc_nonseq_init_t + Add API DMA_ReconfigNonSeqStructInit() & DMA_ReconfigNonSeqInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_DMA_H__ +#define __HC32_LL_DMA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_DMA + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Types DMA Global Types + * @{ + */ + +/** + * @brief DMA basic configuration + */ +typedef struct { + uint32_t u32IntEn; /*!< Specifies the DMA interrupt function. + This parameter can be a value of @ref DMA_Int_Config */ + uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */ + uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */ + uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width. + This parameter can be a value of @ref DMA_DataWidth_Sel */ + uint32_t u32BlockSize; /*!< Specifies the DMA block size. */ + uint32_t u32TransCount; /*!< Specifies the DMA transfer count. */ + uint32_t u32SrcAddrInc; /*!< Specifies the source address increment mode. + This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */ + uint32_t u32DestAddrInc; /*!< Specifies the destination address increment mode. + This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */ +} stc_dma_init_t; + +/** + * @brief DMA repeat mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source repeat function. + This parameter can be a value of @ref DMA_Repeat_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source repeat size. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination repeat size. */ +} stc_dma_repeat_init_t; + +/** + * @brief DMA non-sequence mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function. + This parameter can be a value of @ref DMA_NonSeq_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */ + uint32_t u32SrcOffset; /*!< Specifies the DMA source non-sequence function offset. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */ + uint32_t u32DestOffset; /*!< Specifies the DMA destination non-sequence function offset. */ +} stc_dma_nonseq_init_t; + +/** + * @brief DMA Link List Pointer (LLP) mode configuration + */ +typedef struct { + uint32_t u32State; /*!< Specifies the DMA LLP function. + This parameter can be a value of @ref DMA_Llp_En */ + uint32_t u32Mode; /*!< Specifies the DMA LLP auto or wait REQ. + This parameter can be a value of @ref DMA_Llp_Mode */ + uint32_t u32Addr; /*!< Specifies the DMA list pointer address for LLP function. */ +} stc_dma_llp_init_t; + +/** + * @brief DMA re-config function configuration + */ +typedef struct { + uint32_t u32CountMode; /*!< Specifies the DMA reconfig function count mode. + This parameter can be a value of @ref DMA_Reconfig_Count_Sel */ + uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode. + This parameter can be a value of @ref DMA_Reconfig_DestAddr_Sel */ + uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode. + This parameter can be a value of @ref DMA_Reconfig_SrcAddr_Sel */ +} stc_dma_reconfig_init_t; + +/** + * @brief DMA re-config non-sequence mode configuration + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies the DMA source non-sequence function. + This parameter can be a value of @ref DMA_NonSeq_Config */ + uint32_t u32SrcCount; /*!< Specifies the DMA source non-sequence function count. */ + uint32_t u32SrcDist; /*!< Specifies the DMA source non-sequence function distance. */ + uint32_t u32DestCount; /*!< Specifies the DMA destination non-sequence function count. */ + uint32_t u32DestDist; /*!< Specifies the DMA destination non-sequence function distance. */ +} stc_dma_rc_nonseq_init_t; + +/** + * @brief Dma LLP(linked list pointer) descriptor structure definition + */ +typedef struct { + uint32_t SARx; /*!< LLP source address */ + uint32_t DARx; /*!< LLP destination address */ + uint32_t DTCTLx; /*!< LLP transfer count and block size */ + uint32_t RPTx; /*!< LLP source & destination repeat size */ + uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */ + uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */ + uint32_t LLPx; /*!< LLP next list pointer */ + uint32_t CHCTLx; /*!< LLP channel control */ +} stc_dma_llp_descriptor_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Macros DMA Global Macros + * @{ + */ + +/** + * @defgroup DMA_Channel_selection DMA Channel Position selection + * @{ + */ +#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */ +#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */ +#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */ +#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */ +#define DMA_CH4 (0x04U) /*!< DMA Channel 4 */ +#define DMA_CH5 (0x05U) /*!< DMA Channel 5 */ + +/** + * @} + */ + +/** + * @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection + * @{ + */ +#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */ +#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */ +#define DMA_MX_CH_ALL (DMA_CHEN_CHEN) /*!< DMA Channel mask position */ +#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */ +#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */ +#define DMA_MX_CH4 (0x10UL) /*!< DMA Channel 4 position */ +#define DMA_MX_CH5 (0x20UL) /*!< DMA Channel 5 position */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Request_Err_Sel DMA request error flag selection + * @{ + */ +#define DMA_FLAG_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error flag CH.0 */ +#define DMA_FLAG_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error flag CH.1 */ +#define DMA_FLAG_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error flag CH.2 */ +#define DMA_FLAG_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error flag CH.3 */ +#define DMA_FLAG_REQ_ERR_CH4 (DMA_INTSTAT0_REQERR_4) /*!< DMA request error flag CH.4 */ +#define DMA_FLAG_REQ_ERR_CH5 (DMA_INTSTAT0_REQERR_5) /*!< DMA request error flag CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Trans_Err_Sel DMA transfer error flag selection + * @{ + */ +#define DMA_FLAG_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error flag CH.0 */ +#define DMA_FLAG_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error flag CH.1 */ +#define DMA_FLAG_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error flag CH.2 */ +#define DMA_FLAG_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error flag CH.3 */ +#define DMA_FLAG_TRANS_ERR_CH4 (DMA_INTSTAT0_TRNERR_4) /*!< DMA transfer error flag CH.4 */ +#define DMA_FLAG_TRANS_ERR_CH5 (DMA_INTSTAT0_TRNERR_5) /*!< DMA transfer error flag CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Btc_Sel DMA block transfer completed flag selection + * @{ + */ +#define DMA_FLAG_BTC_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed flag CH.0 */ +#define DMA_FLAG_BTC_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed flag CH.1 */ +#define DMA_FLAG_BTC_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed flag CH.2 */ +#define DMA_FLAG_BTC_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed flag CH.3 */ +#define DMA_FLAG_BTC_CH4 (DMA_INTSTAT1_BTC_4) /*!< DMA block transfer completed flag CH.4 */ +#define DMA_FLAG_BTC_CH5 (DMA_INTSTAT1_BTC_5) /*!< DMA block transfer completed flag CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_Flag_Tc_Sel DMA transfer completed flag selection + * @{ + */ +#define DMA_FLAG_TC_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed flag CH.0 */ +#define DMA_FLAG_TC_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed flag CH.1 */ +#define DMA_FLAG_TC_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed flag CH.2 */ +#define DMA_FLAG_TC_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed flag CH.3 */ +#define DMA_FLAG_TC_CH4 (DMA_INTSTAT1_TC_4) /*!< DMA transfer completed flag CH.4 */ +#define DMA_FLAG_TC_CH5 (DMA_INTSTAT1_TC_5) /*!< DMA transfer completed flag CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Request_Err_Sel DMA request error interrupt selection + * @{ + */ +#define DMA_INT_REQ_ERR_CH0 (DMA_INTMASK0_MSKREQERR_0) /*!< DMA request error interrupt CH.0 */ +#define DMA_INT_REQ_ERR_CH1 (DMA_INTMASK0_MSKREQERR_1) /*!< DMA request error interrupt CH.1 */ +#define DMA_INT_REQ_ERR_CH2 (DMA_INTMASK0_MSKREQERR_2) /*!< DMA request error interrupt CH.2 */ +#define DMA_INT_REQ_ERR_CH3 (DMA_INTMASK0_MSKREQERR_3) /*!< DMA request error interrupt CH.3 */ +#define DMA_INT_REQ_ERR_CH4 (DMA_INTMASK0_MSKREQERR_4) /*!< DMA request error interrupt CH.4 */ +#define DMA_INT_REQ_ERR_CH5 (DMA_INTMASK0_MSKREQERR_5) /*!< DMA request error interrupt CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Trans_Err_Sel DMA transfer error interrupt selection + * @{ + */ +#define DMA_INT_TRANS_ERR_CH0 (DMA_INTMASK0_MSKTRNERR_0) /*!< DMA transfer error interrupt CH.0 */ +#define DMA_INT_TRANS_ERR_CH1 (DMA_INTMASK0_MSKTRNERR_1) /*!< DMA transfer error interrupt CH.1 */ +#define DMA_INT_TRANS_ERR_CH2 (DMA_INTMASK0_MSKTRNERR_2) /*!< DMA transfer error interrupt CH.2 */ +#define DMA_INT_TRANS_ERR_CH3 (DMA_INTMASK0_MSKTRNERR_3) /*!< DMA transfer error interrupt CH.3 */ +#define DMA_INT_TRANS_ERR_CH4 (DMA_INTMASK0_MSKTRNERR_4) /*!< DMA transfer error interrupt CH.4 */ +#define DMA_INT_TRANS_ERR_CH5 (DMA_INTMASK0_MSKTRNERR_5) /*!< DMA transfer error interrupt CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Btc_Sel DMA block transfer completed interrupt selection + * @{ + */ +#define DMA_INT_BTC_CH0 (DMA_INTMASK1_MSKBTC_0) /*!< DMA block transfer completed interrupt CH.0 */ +#define DMA_INT_BTC_CH1 (DMA_INTMASK1_MSKBTC_1) /*!< DMA block transfer completed interrupt CH.1 */ +#define DMA_INT_BTC_CH2 (DMA_INTMASK1_MSKBTC_2) /*!< DMA block transfer completed interrupt CH.2 */ +#define DMA_INT_BTC_CH3 (DMA_INTMASK1_MSKBTC_3) /*!< DMA block transfer completed interrupt CH.3 */ +#define DMA_INT_BTC_CH4 (DMA_INTMASK1_MSKBTC_4) /*!< DMA block transfer completed interrupt CH.4 */ +#define DMA_INT_BTC_CH5 (DMA_INTMASK1_MSKBTC_5) /*!< DMA block transfer completed interrupt CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Tc_Sel DMA transfer completed interrupt selection + * @{ + */ +#define DMA_INT_TC_CH0 (DMA_INTMASK1_MSKTC_0) /*!< DMA transfer completed interrupt CH.0 */ +#define DMA_INT_TC_CH1 (DMA_INTMASK1_MSKTC_1) /*!< DMA transfer completed interrupt CH.1 */ +#define DMA_INT_TC_CH2 (DMA_INTMASK1_MSKTC_2) /*!< DMA transfer completed interrupt CH.2 */ +#define DMA_INT_TC_CH3 (DMA_INTMASK1_MSKTC_3) /*!< DMA transfer completed interrupt CH.3 */ +#define DMA_INT_TC_CH4 (DMA_INTMASK1_MSKTC_4) /*!< DMA transfer completed interrupt CH.4 */ +#define DMA_INT_TC_CH5 (DMA_INTMASK1_MSKTC_5) /*!< DMA transfer completed interrupt CH.5 */ +/** + * @} + */ + +/** + * @defgroup DMA_FlagMsk_Sel DMA flag mask selection + * @{ + */ +#define DMA_FLAG_ERR_MASK (DMA_INTSTAT0_TRNERR | DMA_INTSTAT0_REQERR) /*!< DMA error flag mask */ +#define DMA_FLAG_TRANS_MASK (DMA_INTSTAT1_TC | DMA_INTSTAT1_BTC) /*!< DMA transfer flag mask */ +/** + * @} + */ + +/** + * @defgroup DMA_IntMsk_Sel DMA interrupt mask selection + * @{ + */ +#define DMA_INT_ERR_MASK (DMA_INTMASK0_MSKREQERR | DMA_INTMASK0_MSKTRNERR) /*!< DMA error interrupt mask */ +#define DMA_INT_TRANS_MASK (DMA_INTMASK1_MSKTC | DMA_INTMASK1_MSKBTC) /*!< DMA transfer interrupt mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Req_Status_Sel DMA request status + * @{ + */ +#define DMA_STAT_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */ +#define DMA_STAT_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */ +#define DMA_STAT_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */ +#define DMA_STAT_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */ +#define DMA_STAT_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */ +#define DMA_STAT_REQ_CH4 (DMA_REQSTAT_CHREQ_4) /*!< DMA request from CH.4 */ +#define DMA_STAT_REQ_CH5 (DMA_REQSTAT_CHREQ_5) /*!< DMA request from CH.5 */ + +#define DMA_STAT_REQ_MASK (DMA_REQSTAT_CHREQ | DMA_REQSTAT_RCFGREQ) /*!< DMA request mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Trans_Status_Sel DMA transfer status + * @{ + */ +#define DMA_STAT_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */ +#define DMA_STAT_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */ +#define DMA_STAT_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */ +#define DMA_STAT_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */ +#define DMA_STAT_TRANS_CH4 (DMA_CHSTAT_CHACT_4) /*!< DMA transfer status of CH.4 */ +#define DMA_STAT_TRANS_CH5 (DMA_CHSTAT_CHACT_5) /*!< DMA transfer status of CH.5 */ +#define DMA_STAT_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */ +#define DMA_STAT_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */ + +#define DMA_STAT_TRANS_MASK (DMA_CHSTAT_DMAACT | DMA_CHSTAT_CHACT | DMA_CHSTAT_RCFGACT) +/** + * @} + */ + +/** + * @defgroup DMA_DataWidth_Sel DMA transfer data width + * @{ + */ +#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */ +#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */ +#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */ + +/** + * @} + */ + +/** + * @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable + * @{ + */ +#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA linked list pinter disable */ +#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA linked list pinter enable */ +/** + * @} + */ + +/** + * @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete + * @{ + */ +#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transferring complete */ +#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transferring complete */ +/** + * @} + */ + +/** + * @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode + * @{ + */ +#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */ +#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */ +#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */ +/** + * @} + */ + +/** + * @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode + * @{ + */ +#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */ +#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */ +#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Config DMA interrupt function config + * @{ + */ +#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */ +#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */ +/** + * @} + */ + +/** + * @defgroup DMA_Repeat_Config DMA repeat mode function config + * @{ + */ +#define DMA_RPT_NONE (0x00000000UL) /*!< DMA repeat disable */ +#define DMA_RPT_SRC (DMA_CHCTL_SRPTEN) /*!< DMA source repeat enable */ +#define DMA_RPT_DEST (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */ +#define DMA_RPT_BOTH (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN) /*!< DMA source & destination repeat enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_NonSeq_Config DMA non-sequence mode function config + * @{ + */ +#define DMA_NON_SEQ_NONE (0x00000000UL) /*!< DMA non-sequence disable */ +#define DMA_NON_SEQ_SRC (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */ +#define DMA_NON_SEQ_DEST (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */ +#define DMA_NON_SEQ_BOTH (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN) /*!< DMA source & destination non-sequence enable */ + +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_Count_Sel DMA reconfig count mode selection + * @{ + */ +#define DMA_RC_CNT_KEEP (0x00000000UL) /*!< Keep the original counting method */ +#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */ +#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_DestAddr_Sel DMA reconfig destination address mode selection + * @{ + */ +#define DMA_RC_DEST_ADDR_KEEP (0x00000000UL) /*!< Destination address Keep the original mode */ +#define DMA_RC_DEST_ADDR_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */ +#define DMA_RC_DEST_ADDR_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */ +/** + * @} + */ + +/** + * @defgroup DMA_Reconfig_SrcAddr_Sel DMA reconfig source address mode selection + * @{ + */ +#define DMA_RC_SRC_ADDR_KEEP (0x00000000UL) /*!< Source address Keep the original mode */ +#define DMA_RC_SRC_ADDR_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */ +#define DMA_RC_SRC_ADDR_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DMA_Global_Functions + * @{ + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); + +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag); +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag); + +void DMA_MxChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState); +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status); + +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count); +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +int32_t DMA_SetDataWidth(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32DataWidth); + +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size); +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size); +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count); +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset); + +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); + +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit); +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit); +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +int32_t DMA_UnitDeInit(CM_DMA_TypeDef *DMAx); + +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit); +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit); + +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit); +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit); + +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit); +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit); + +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit); +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit); +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState); +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); +int32_t DMA_ReconfigNonSeqStructInit(stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit); +int32_t DMA_ReconfigNonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit); + +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch); +void DMA_AHB_HProtBufCacheCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_DMA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h new file mode 100644 index 0000000000..892ae5be0f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_efm.h @@ -0,0 +1,511 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.h + * @brief This file contains all the functions prototypes of the EFM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Rename EFM_DataCacheResetCmd() as EFM_CacheRamReset() and modify comment + Optimized macro group EFM_Remap_Size definitions + Add structure of stc_efm_location_t and declaration of API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EFM_H__ +#define __HC32_LL_EFM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EFM + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Types EFM Global Types + * @{ + */ +/** + * @brief EFM unique ID definition + */ +typedef struct { + uint32_t u32UniqueID0; /*!< unique ID 0. */ + uint32_t u32UniqueID1; /*!< unique ID 1. */ + uint32_t u32UniqueID2; /*!< unique ID 2. */ +} stc_efm_unique_id_t; + +typedef struct { + uint32_t u32State; + uint32_t u32Addr; + uint32_t u32Size; +} stc_efm_remap_init_t; + +/** + * @brief EFM location definition + */ +typedef struct { + uint8_t u8X_Location; /*!< X location. */ + uint8_t u8Y_Location; /*!< Y location. */ +} stc_efm_location_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Macros EFM Global Macros + * @{ + */ +/** + * @defgroup EFM_Address EFM Address Area + * @{ + */ +#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */ + +#define EFM_END_ADDR (0x0003FFFFUL) /*!< Flash end address */ +#define EFM_OTP_END_ADDR1 (0x00001FFFUL) /*!< OTP end address1 */ +#define EFM_OTP_START_ADDR1 (0x00000000UL) /*!< OTP start address1 */ +#define EFM_OTP_START_ADDR (0x03000C00UL) /*!< OTP start address */ +#define EFM_OTP_END_ADDR (0x03000FFFUL) /*!< OTP end address */ +#define EFM_OTP_LOCK_ADDR_START (0x03000A80UL) /*!< OTP lock address */ +#define EFM_OTP_LOCK_ADDR_START1 (0x03000AC0UL) /*!< OTP lock address 1 */ +#define EFM_OTP_LOCK_ADDR_END (0x03000AFFUL) /*!< OTP lock address */ +#define EFM_OTP_ENABLE_ADDR (0x03000A00UL) /*!< OTP Enable address */ +#define EFM_SECURITY_START_ADDR (0x03002040UL) /*!< Flash security start address */ +#define EFM_SECURITY_END_ADDR (0x0300204BUL) /*!< Flash security end address */ +/** + * @} + */ + +/** + * @defgroup EFM_Chip_Sel EFM Chip Selection + * @{ + */ +#define EFM_CHIP_ALL (EFM_FSTP_FSTP) +/** + * @} + */ + +/** + * @defgroup EFM_Bus_Status EFM Bus Status + * @{ + */ +#define EFM_BUS_HOLD (0x0UL) /*!< Bus busy while flash program or erase */ +#define EFM_BUS_RELEASE (0x1UL) /*!< Bus release while flash program or erase */ +/** + * @} + */ + +/** + * @defgroup EFM_Wait_Cycle EFM Wait Cycle + * @{ + */ + +#define EFM_WAIT_CYCLE0 (0U << EFM_FRMC_FLWT_POS) /*!< Don't insert read wait cycle */ +#define EFM_WAIT_CYCLE1 (1U << EFM_FRMC_FLWT_POS) /*!< Insert 1 read wait cycle */ + +#define EFM_WAIT_CYCLE2 (2U << EFM_FRMC_FLWT_POS) /*!< Insert 2 read wait cycles */ +#define EFM_WAIT_CYCLE3 (3U << EFM_FRMC_FLWT_POS) /*!< Insert 3 read wait cycles */ +#define EFM_WAIT_CYCLE4 (4U << EFM_FRMC_FLWT_POS) /*!< Insert 4 read wait cycles */ +#define EFM_WAIT_CYCLE5 (5U << EFM_FRMC_FLWT_POS) /*!< Insert 5 read wait cycles */ +#define EFM_WAIT_CYCLE6 (6U << EFM_FRMC_FLWT_POS) /*!< Insert 6 read wait cycles */ +#define EFM_WAIT_CYCLE7 (7U << EFM_FRMC_FLWT_POS) /*!< Insert 7 read wait cycles */ +#define EFM_WAIT_CYCLE8 (8U << EFM_FRMC_FLWT_POS) /*!< Insert 8 read wait cycles */ +#define EFM_WAIT_CYCLE9 (9U << EFM_FRMC_FLWT_POS) /*!< Insert 9 read wait cycles */ +#define EFM_WAIT_CYCLE10 (10U << EFM_FRMC_FLWT_POS) /*!< Insert 10 read wait cycles */ +#define EFM_WAIT_CYCLE11 (11U << EFM_FRMC_FLWT_POS) /*!< Insert 11 read wait cycles */ +#define EFM_WAIT_CYCLE12 (12U << EFM_FRMC_FLWT_POS) /*!< Insert 12 read wait cycles */ +#define EFM_WAIT_CYCLE13 (13U << EFM_FRMC_FLWT_POS) /*!< Insert 13 read wait cycles */ +#define EFM_WAIT_CYCLE14 (14U << EFM_FRMC_FLWT_POS) /*!< Insert 14 read wait cycles */ +#define EFM_WAIT_CYCLE15 (15U << EFM_FRMC_FLWT_POS) /*!< Insert 15 read wait cycles */ +/** + * @} + */ + +/** + * @defgroup EFM_Swap_Address EFM Swap Address + * @{ + */ +#define EFM_SWAP_ADDR (0x03002000UL) +#define EFM_SWAP_DATA (0x005A5A5AUL) +/** + * @} + */ + +/** + * @defgroup EFM_OperateMode_Sel EFM Operate Mode Selection + * @{ + */ +#define EFM_MD_READONLY (0x0UL << EFM_FWMC_PEMOD_POS) /*!< Read only mode */ +#define EFM_MD_PGM_SINGLE (0x1UL << EFM_FWMC_PEMOD_POS) /*!< Program single mode */ +#define EFM_MD_PGM_READBACK (0x2UL << EFM_FWMC_PEMOD_POS) /*!< Program and read back mode */ +#define EFM_MD_PGM_SEQ (0x3UL << EFM_FWMC_PEMOD_POS) /*!< Program sequence mode */ +#define EFM_MD_ERASE_SECTOR (0x4UL << EFM_FWMC_PEMOD_POS) /*!< Sector erase mode */ + +#define EFM_MD_ERASE_ALL_CHIP (0x5UL << EFM_FWMC_PEMOD_POS) /*!< Chip erase mode */ +/** + * @} + */ + +/** + * @defgroup EFM_Flag_Sel EFM Flag Selection + * @{ + */ +#define EFM_FLAG_OTPWERR (EFM_FSR_OTPWERR) /*!< EFM Flash otp Programming/erase error flag. */ +#define EFM_FLAG_PEPRTERR (EFM_FSR_PRTWERR) /*!< EFM Flash write protect address error flag. */ +#define EFM_FLAG_PGSZERR (EFM_FSR_PGSZERR) /*!< EFM Flash programming size error flag. */ +#define EFM_FLAG_PGMISMTCH (EFM_FSR_MISMTCH) /*!< EFM Flash programming missing match error flag. */ +#define EFM_FLAG_OPTEND (EFM_FSR_OPTEND) /*!< EFM Flash end of operation flag. */ +#define EFM_FLAG_COLERR (EFM_FSR_COLERR) /*!< EFM Flash read collide error flag. */ +#define EFM_FLAG_RDY (EFM_FSR_RDY) /*!< EFM Flash ready flag. */ + +#define EFM_FLAG_ALL (EFM_FLAG_OTPWERR | EFM_FLAG_PEPRTERR | EFM_FLAG_PGSZERR | EFM_FLAG_PGMISMTCH | \ + EFM_FLAG_OPTEND | EFM_FLAG_COLERR | EFM_FLAG_RDY) + +/** + * @} + */ + +/** + * @defgroup EFM_Interrupt_Sel EFM Interrupt Selection + * @{ + */ +#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */ +#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */ +#define EFM_INT_COLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */ + +#define EFM_INT_ALL (EFM_FITE_PEERRITE | EFM_FITE_OPTENDITE | EFM_FITE_COLERRITE) +/** + * @} + */ + +/** + * @defgroup EFM_Keys EFM Keys + * @{ + */ +#define EFM_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REG_UNLOCK_KEY2 (0x3210UL) +#define EFM_REG_LOCK_KEY (0x0000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Size EFM Sector Size + * @{ + */ +#define SECTOR_SIZE (0x2000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Address EFM Sector Address + * @{ + */ +#define EFM_SECTOR_ADDR(x) (uint32_t)(SECTOR_SIZE * (x)) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Base_Address EFM Otp Base Address + * @{ + */ +#define EFM_OTP_BASE1_ADDR (0x00000000UL) +#define EFM_OTP_BASE1_SIZE (0x2000UL) +#define EFM_OTP_BASE2_ADDR (0x03000C00UL) +#define EFM_OTP_BASE2_SIZE (0x40UL) +#define EFM_OTP_LOCK_ADDR0 (0x03000A80UL) +#define EFM_OTP_LOCK_ADDR1 (0x03000AC0UL) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Address EFM Otp Address + * @{ + */ +#define EFM_OTP_BLOCK0 (EFM_OTP_BASE1_ADDR) + +#define EFM_OTP_BLOCK1 (EFM_OTP_BASE2_ADDR + (0UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK2 (EFM_OTP_BASE2_ADDR + (1UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK3 (EFM_OTP_BASE2_ADDR + (2UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK4 (EFM_OTP_BASE2_ADDR + (3UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK5 (EFM_OTP_BASE2_ADDR + (4UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK6 (EFM_OTP_BASE2_ADDR + (5UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK7 (EFM_OTP_BASE2_ADDR + (6UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK8 (EFM_OTP_BASE2_ADDR + (7UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK9 (EFM_OTP_BASE2_ADDR + (8UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK10 (EFM_OTP_BASE2_ADDR + (9UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK11 (EFM_OTP_BASE2_ADDR + (10UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK12 (EFM_OTP_BASE2_ADDR + (11UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK13 (EFM_OTP_BASE2_ADDR + (12UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK14 (EFM_OTP_BASE2_ADDR + (13UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK15 (EFM_OTP_BASE2_ADDR + (14UL * EFM_OTP_BASE2_SIZE)) +#define EFM_OTP_BLOCK16 (EFM_OTP_BASE2_ADDR + (15UL * EFM_OTP_BASE2_SIZE)) +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Lock_Address EFM Otp Lock_address + * x at range of 0~16 + * @{ + */ +#define EFM_OTP_BLOCK_LOCKADDR(x) ((x == 0UL) ? EFM_OTP_LOCK_ADDR0 : (EFM_OTP_LOCK_ADDR1 + (x - 1UL) * 0x04UL)) +/** + * @} + */ + +#define EFM_REMAP_REG_LOCK_KEY (0x0000UL) +#define EFM_REMAP_REG_UNLOCK_KEY1 (0x0123UL) +#define EFM_REMAP_REG_UNLOCK_KEY2 (0x3210UL) + +/** + * @defgroup EFM_Remap_State EFM remap function state + * @{ + */ +#define EFM_REMAP_OFF (0UL) +#define EFM_REMAP_ON (EFM_MMF_REMCR_EN) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Size EFM remap size definition + * @note refer to chip user manual for details size spec. + * @{ + */ +#define EFM_REMAP_4K (12UL) +#define EFM_REMAP_8K (13UL) +#define EFM_REMAP_16K (14UL) +#define EFM_REMAP_32K (15UL) +#define EFM_REMAP_64K (16UL) +#define EFM_REMAP_128K (17UL) +#define EFM_REMAP_256K (18UL) +#define EFM_REMAP_SIZE_MAX EFM_REMAP_256K +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Index EFM remap index + * @{ + */ +#define EFM_REMAP_IDX0 (0U) +#define EFM_REMAP_IDX1 (1U) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_BaseAddr EFM remap base address + * @{ + */ +#define EFM_REMAP_BASE_ADDR0 (0x2000000UL) +#define EFM_REMAP_BASE_ADDR1 (0x2080000UL) +/** + * @} + */ + +/** + * @defgroup EFM_Remap_Region EFM remap ROM/RAM region + * @{ + */ +#define EFM_REMAP_ROM_END_ADDR EFM_END_ADDR + +#define EFM_REMAP_RAM_START_ADDR (0x1FFF8000UL) +#define EFM_REMAP_RAM_END_ADDR (0x1FFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EFM_Protect_Level EFM protect level + * @{ + */ +#define EFM_PROTECT_LEVEL1 (1U) +#define EFM_PROTECT_LEVEL2 (2U) +#define EFM_PROTECT_LEVEL3 (4U) +/** + * @} + */ + +/** + * @defgroup EFM_MCU_Status EFM protect level + * @{ + */ +#define EFM_MCU_PROTECT1_FREE (0U) +#define EFM_MCU_PROTECT1_LOCK (1U) +#define EFM_MCU_PROTECT1_UNLOCK (2U) +#define EFM_MCU_PROTECT2_LOCK (4U) +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EFM_Global_Functions + * @{ + */ + +/** + * @brief EFM Protect Unlock. + * @param None + * @retval None + */ + +__STATIC_INLINE void EFM_REG_Unlock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM Protect Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REG_Lock(void) +{ + WRITE_REG32(CM_EFM->FAPRT, EFM_REG_LOCK_KEY); +} + +/** + * @brief EFM remap Unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Unlock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_UNLOCK_KEY2); +} + +/** + * @brief EFM remap Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_REMAP_Lock(void) +{ + WRITE_REG32(CM_EFM->MMF_REMPRT, EFM_REMAP_REG_LOCK_KEY); +} + +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState); +void EFM_FWMC_Cmd(en_functional_state_t enNewState); +void EFM_SetBusStatus(uint32_t u32Status); +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState); +void EFM_ClearStatus(uint32_t u32Flag); +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle); +int32_t EFM_SetOperateMode(uint32_t u32Mode); +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen); +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data); +int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len); +int32_t EFM_SectorErase(uint32_t u32Addr); +int32_t EFM_ChipErase(uint8_t u8Chip); + +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag); +en_flag_status_t EFM_GetStatus(uint32_t u32Flag); +void EFM_GetUID(stc_efm_unique_id_t *pstcUID); +uint8_t EFM_GetWaferID(void); +void EFM_GetLocation(stc_efm_location_t *pstcLocation); +uint64_t EFM_GetLotID(void); + +void EFM_CacheRamReset(en_functional_state_t enNewState); +void EFM_PrefetchCmd(en_functional_state_t enNewState); +void EFM_DCacheCmd(en_functional_state_t enNewState); +void EFM_ICacheCmd(en_functional_state_t enNewState); + +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState); +int32_t EFM_SwapCmd(en_functional_state_t enNewState); +en_flag_status_t EFM_GetSwapStatus(void); +int32_t EFM_OTP_Lock(uint32_t u32Addr); + +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit); +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit); +void EFM_REMAP_DeInit(void); +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState); +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr); +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size); + +uint32_t EFM_GetCID(void); +void EFM_OTP_WP_Unlock(void); +void EFM_OTP_WP_Lock(void); +int32_t EFM_OTP_Enable(void); +void EFM_SectorProtectRegLock(uint32_t u32RegLock); +void EFM_SingleSectorOperateCmd(uint8_t u8SectorNum, en_functional_state_t enNewState); +void EFM_SequenceSectorOperateCmd(uint32_t u32StartSectorNum, uint16_t u16Count, en_functional_state_t enNewState); + +void EFM_Protect_Enable(uint8_t u8Level); +int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len); + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h new file mode 100644 index 0000000000..361509bd1b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_emb.h @@ -0,0 +1,528 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.h + * @brief This file contains all the functions prototypes of the EMB + * (Emergency Brake) driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Update EMB_CTL1_CMPEN0~3 to EMB_CTL1_CMPEN1~4 + 2023-12-15 CDT Add stc_emb_monitor_sys_t to combine osc, sram, lockup, lvd + Replace macro: EMB_CTL1_SRAMERREN -> EMB_CTL1_SRAMECCERREN + Add marco EMB_FLAG_CLR_ALL + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EMB_H__ +#define __HC32_LL_EMB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EMB + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Types EMB Global Types + * @{ + */ + +/** + * @brief EMB monitor system exception configuration + */ +typedef struct { + uint32_t u32Osc; /*!< Enable or disable EMB detect OSC failure function + This parameter can be a value of @ref EMB_OSC_Selection */ + uint32_t u32SramEccError; /*!< EMB detect SRAM ECC error function + This parameter can be a value of @ref EMB_SRAM_ECC_Error_Selection */ + uint32_t u32SramParityError; /*!< EMB detect SRAM parity error function + This parameter can be a value of @ref EMB_SRAM_Parity_Error_Selection */ + uint32_t u32Lockup; /*!< EMB detect lockup function + This parameter can be a value of @ref EMB_Lockup_Selection */ + uint32_t u32Lvd; /*!< EMB detect LVD function + This parameter can be a value of @ref EMB_LVD_Selection */ +} stc_emb_monitor_sys_t; + +/** + * @brief EMB monitor EMB port configuration + */ +typedef struct { + uint32_t u32PortState; /*!< Enable or disable EMB detect port in control function + This parameter can be a value of @ref EMB_Port_Selection */ + uint32_t u32PortLevel; /*!< EMB detect port level + This parameter can be a value of @ref EMB_Detect_Port_Level */ + uint32_t u32PortFilterDiv; /*!< EMB port filter division + This parameter can be a value of @ref EMB_Port_Filter_Clock_Division */ + uint32_t u32PortFilterState; /*!< Enable or disable EMB detect port filter in control function + This parameter can be a value of @ref EMB_Port_Filter_Selection */ +} stc_emb_monitor_port_config_t; + +/** + * @brief EMB monitor PWM configuration + */ +typedef struct { + uint32_t u32PwmState; /*!< Enable or disable EMB detect timer same phase function + This parameter can be a value of @ref EMB_Detect_PWM state. */ + uint32_t u32PwmLevel; /*!< Detect timer polarity level + This parameter can be a value of @ref EMB_Detect_PWM level */ +} stc_emb_monitor_tmr_pwm_t; + +/** + * @brief EMB monitor port in configuration + */ +typedef struct { + stc_emb_monitor_port_config_t stcPort1; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ + stc_emb_monitor_port_config_t stcPort2; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ + stc_emb_monitor_port_config_t stcPort3; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ + stc_emb_monitor_port_config_t stcPort4; /*!< EMB detect EMB port in function + This parameter details refer @ref stc_emb_monitor_port_config_t structure */ +} stc_emb_monitor_port_t; + +/** + * @brief EMB monitor CMP configuration + */ +typedef struct { + uint32_t u32Cmp1State; /*!< Enable or disable EMB detect CMP1 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp2State; /*!< Enable or disable EMB detect CMP2 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp3State; /*!< Enable or disable EMB detect CMP3 result function + This parameter can be a value of @ref EMB_CMP_Selection */ + uint32_t u32Cmp4State; /*!< Enable or disable EMB detect CMP4 result function + This parameter can be a value of @ref EMB_CMP_Selection */ +} stc_emb_monitor_cmp_t; + +/** + * @brief EMB monitor TMR4 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr4PwmX; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr4_t; + +/** + * @brief EMB control TMR4 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr4_t stcTmr4; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr4_t structure */ + stc_emb_monitor_sys_t stcSys; /*!< EMB detect System function + This parameter details refer @ref stc_emb_monitor_sys_t structure */ +} stc_emb_tmr4_init_t; + +/** + * @brief EMB monitor TMR6 configuration + */ +typedef struct { + stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_monitor_tmr6_t; + +/** + * @brief EMB control TMR6 initialization configuration + */ +typedef struct { + stc_emb_monitor_cmp_t stcCmp; /*!< EMB detect CMP function + This parameter details refer @ref stc_emb_monitor_cmp_t structure */ + stc_emb_monitor_port_t stcPort; /*!< EMB detect EMB port function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + stc_emb_monitor_tmr6_t stcTmr6; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr6_t structure */ + stc_emb_monitor_sys_t stcSys; /*!< EMB detect System function + This parameter details refer @ref stc_emb_monitor_sys_t structure */ +} stc_emb_tmr6_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Macros EMB Global Macros + * @{ + */ + +/** + * @defgroup EMB_CMP_Selection EMB CMP Selection + * @{ + */ +#define EMB_CMP1_DISABLE (0UL) +#define EMB_CMP2_DISABLE (0UL) +#define EMB_CMP3_DISABLE (0UL) +#define EMB_CMP4_DISABLE (0UL) + +#define EMB_CMP1_ENABLE (EMB_CTL1_CMPEN1) +#define EMB_CMP2_ENABLE (EMB_CTL1_CMPEN2) +#define EMB_CMP3_ENABLE (EMB_CTL1_CMPEN3) +#define EMB_CMP4_ENABLE (EMB_CTL1_CMPEN4) +/** + * @} + */ + +/** + * @defgroup EMB_OSC_Selection EMB OSC Selection + * @{ + */ +#define EMB_OSC_DISABLE (0UL) +#define EMB_OSC_ENABLE (EMB_CTL1_OSCSTPEN) +/** + * @} + */ + +/** + * @defgroup EMB_SRAM_ECC_Error_Selection EMB SRAM ECC Error Selection + * @{ + */ +#define EMB_SRAM_ECC_ERR_DISABLE (0UL) +#define EMB_SRAM_ECC_ERR_ENABLE (EMB_CTL1_SRAMECCERREN) +/** + * @} + */ + +/** + * @defgroup EMB_SRAM_Parity_Error_Selection EMB SRAM Parity Error Selection + * @{ + */ +#define EMB_SRAM_PARITY_ERR_DISABLE (0UL) +#define EMB_SRAM_PARITY_ERR_ENABLE (EMB_CTL1_SRAMPYERREN) +/** + * @} + */ + +/** + * @defgroup EMB_Lockup_Selection EMB Lockup Selection + * @{ + */ +#define EMB_LOCKUP_DISABLE (0UL) +#define EMB_LOCKUP_ENABLE (EMB_CTL1_LOCKUPEN) +/** + * @} + */ + +/** + * @defgroup EMB_LVD_Selection EMB LVD Selection + * @{ + */ +#define EMB_LVD_DISABLE (0UL) +#define EMB_LVD_ENABLE (EMB_CTL1_PVDEN) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_PWM EMB Detect PWM + * @{ + */ +/** + * @defgroup EMB_TMR4_PWM_Selection EMB TMR4 PWM Selection + * @{ + */ +#define EMB_TMR4_PWM_X_DISABLE (0UL) +#define EMB_TMR4_PWM_W_DISABLE (0UL) +#define EMB_TMR4_PWM_V_DISABLE (0UL) +#define EMB_TMR4_PWM_U_DISABLE (0UL) + +#define EMB_TMR4_PWM_X_ENABLE (EMB_CTL1_PWMSEN3) +#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL1_PWMSEN0) +#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL1_PWMSEN1) +#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL1_PWMSEN2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR4_PWM_Level EMB Detect TMR4 PWM Level + * @{ + */ +#define EMB_DETECT_TMR4_PWM_X_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR4_PWM_X_BOTH_HIGH (EMB_CTL2_PWMLV3) +#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_CTL2_PWMLV0) +#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_CTL2_PWMLV1) +#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_CTL2_PWMLV2) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_PWM_Selection EMB TMR6 PWM Selection + * @{ + */ +#define EMB_TMR6_1_PWM_DISABLE (0UL) +#define EMB_TMR6_2_PWM_DISABLE (0UL) + +#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL1_PWMSEN0) +#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL1_PWMSEN1) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_PWM_Level EMB Detect TMR6 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL) + +#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_CTL2_PWMLV0) +#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_CTL2_PWMLV1) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup EMB_Port_Selection EMB Port Selection + * @{ + */ +#define EMB_PORT1_DISABLE (0UL) +#define EMB_PORT2_DISABLE (0UL) +#define EMB_PORT3_DISABLE (0UL) +#define EMB_PORT4_DISABLE (0UL) + +#define EMB_PORT1_ENABLE (EMB_CTL1_PORTINEN1) +#define EMB_PORT2_ENABLE (EMB_CTL1_PORTINEN2) +#define EMB_PORT3_ENABLE (EMB_CTL1_PORTINEN3) +#define EMB_PORT4_ENABLE (EMB_CTL1_PORTINEN4) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port_Level EMB Detect Port Level + * @{ + */ +#define EMB_PORT1_DETECT_LVL_HIGH (0UL) +#define EMB_PORT2_DETECT_LVL_HIGH (0UL) +#define EMB_PORT3_DETECT_LVL_HIGH (0UL) +#define EMB_PORT4_DETECT_LVL_HIGH (0UL) + +#define EMB_PORT1_DETECT_LVL_LOW (EMB_CTL1_INVSEL1) +#define EMB_PORT2_DETECT_LVL_LOW (EMB_CTL1_INVSEL2) +#define EMB_PORT3_DETECT_LVL_LOW (EMB_CTL1_INVSEL3) +#define EMB_PORT4_DETECT_LVL_LOW (EMB_CTL1_INVSEL4) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Selection EMB Port Filter Selection + * @{ + */ +#define EMB_PORT1_FILTER_DISABLE (0UL) +#define EMB_PORT2_FILTER_DISABLE (0UL) +#define EMB_PORT3_FILTER_DISABLE (0UL) +#define EMB_PORT4_FILTER_DISABLE (0UL) + +#define EMB_PORT1_FILTER_ENABLE (EMB_CTL2_NFEN1) +#define EMB_PORT2_FILTER_ENABLE (EMB_CTL2_NFEN2) +#define EMB_PORT3_FILTER_ENABLE (EMB_CTL2_NFEN3) +#define EMB_PORT4_FILTER_ENABLE (EMB_CTL2_NFEN4) +/** + * @} + */ + +/** + * @defgroup EMB_Port_Filter_Clock_Division EMB Port Filter Clock Division + * @{ + */ +#define EMB_PORT1_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL1_POS) +#define EMB_PORT1_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL1_POS) +#define EMB_PORT1_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL1_POS) +#define EMB_PORT1_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL1_POS) + +#define EMB_PORT2_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL2_POS) +#define EMB_PORT2_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL2_POS) +#define EMB_PORT2_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL2_POS) +#define EMB_PORT2_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL2_POS) + +#define EMB_PORT3_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL3_POS) +#define EMB_PORT3_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL3_POS) +#define EMB_PORT3_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL3_POS) +#define EMB_PORT3_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL3_POS) + +#define EMB_PORT4_FILTER_CLK_DIV1 (0UL << EMB_CTL2_NFSEL4_POS) +#define EMB_PORT4_FILTER_CLK_DIV8 (1UL << EMB_CTL2_NFSEL4_POS) +#define EMB_PORT4_FILTER_CLK_DIV32 (2UL << EMB_CTL2_NFSEL4_POS) +#define EMB_PORT4_FILTER_CLK_DIV128 (3UL << EMB_CTL2_NFSEL4_POS) +/** + * @} + */ + +/** + * @defgroup EMB_Flag_State EMB Flag State + * @{ + */ +#define EMB_FLAG_PWMS (EMB_STAT_PWMSF) +#define EMB_FLAG_CMP (EMB_STAT_CMPF) +#define EMB_FLAG_SYS (EMB_STAT_SYSF) +#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF1) +#define EMB_FLAG_PORT2 (EMB_STAT_PORTINF2) +#define EMB_FLAG_PORT3 (EMB_STAT_PORTINF3) +#define EMB_FLAG_PORT4 (EMB_STAT_PORTINF4) +#define EMB_STAT_PWMS (EMB_STAT_PWMST) +#define EMB_STAT_CMP (EMB_STAT_CMPST) +#define EMB_STAT_SYS (EMB_STAT_SYSST) +#define EMB_STAT_PORT1 (EMB_STAT_PORTINST1) +#define EMB_STAT_PORT2 (EMB_STAT_PORTINST2) +#define EMB_STAT_PORT3 (EMB_STAT_PORTINST3) +#define EMB_STAT_PORT4 (EMB_STAT_PORTINST4) +#define EMB_FLAG_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_SYS | EMB_FLAG_PORT1 | \ + EMB_FLAG_PORT2 | EMB_FLAG_PORT3 | EMB_FLAG_PORT4 | EMB_STAT_PWMS | \ + EMB_STAT_CMP | EMB_STAT_SYS | EMB_STAT_PORT1 | EMB_STAT_PORT2 | \ + EMB_STAT_PORT3 | EMB_STAT_PORT4) +#define EMB_FLAG_CLR_ALL (EMB_FLAG_PWMS | EMB_FLAG_CMP | EMB_FLAG_SYS | EMB_FLAG_PORT1 | \ + EMB_FLAG_PORT2 | EMB_FLAG_PORT3 | EMB_FLAG_PORT4) +/** + * @} + */ + +/** + * @defgroup EMB_Interrupt EMB Interrupt + * @{ + */ +#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN) +#define EMB_INT_CMP (EMB_INTEN_CMPINTEN) +#define EMB_INT_SYS (EMB_INTEN_SYSINTEN) +#define EMB_INT_PORT1 (EMB_INTEN_PORTININTEN1) +#define EMB_INT_PORT2 (EMB_INTEN_PORTININTEN2) +#define EMB_INT_PORT3 (EMB_INTEN_PORTININTEN3) +#define EMB_INT_PORT4 (EMB_INTEN_PORTININTEN4) +#define EMB_INT_ALL (EMB_INT_PWMS | EMB_INT_CMP | EMB_INT_SYS | EMB_INT_PORT1 | \ + EMB_INT_PORT2 | EMB_INT_PORT3 | EMB_INT_PORT4) +/** + * @} + */ + +/** + * @defgroup EMB_Release_TMR_PWM_Condition EMB Release TMR PWM Condition + * @{ + */ +#define EMB_RELEASE_PWM_COND_FLAG_ZERO (0UL) +#define EMB_RELEASE_PWM_COND_STAT_ZERO (1UL) +/** + * @} + */ + +/** + * @defgroup EMB_Monitor_Event EMB Monitor Event + * @{ + */ +#define EMB_EVT_PWMS (EMB_RLSSEL_PWMRSEL) +#define EMB_EVT_CMP (EMB_RLSSEL_CMPRSEL) +#define EMB_EVT_SYS (EMB_RLSSEL_SYSRSEL) +#define EMB_EVT_PORT1 (EMB_RLSSEL_PORTINRSEL1) +#define EMB_EVT_PORT2 (EMB_RLSSEL_PORTINRSEL2) +#define EMB_EVT_PORT3 (EMB_RLSSEL_PORTINRSEL3) +#define EMB_EVT_PORT4 (EMB_RLSSEL_PORTINRSEL4) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EMB_Global_Functions + * @{ + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit); +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit); + +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit); +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit); + +void EMB_DeInit(CM_EMB_TypeDef *EMBx); +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState); +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag); +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState); + +void EMB_SetReleasePwmCond(CM_EMB_TypeDef *EMBx, uint32_t u32Event, uint32_t u32Cond); + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h new file mode 100644 index 0000000000..e80861db38 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_event_port.h @@ -0,0 +1,231 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.h + * @brief This file contains all the functions prototypes of the Event Port + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_EVENT_PORT_H__ +#define __HC32_LL_EVENT_PORT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EVENT_PORT + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EP_Global_Types Event Port Global Types + * @{ + */ + +/** + * @brief Event Pin Set and Reset enumeration + */ +typedef enum { + EVT_PIN_RESET = 0U, /*!< Pin reset */ + EVT_PIN_SET = 1U /*!< Pin set */ +} en_ep_state_t; + +typedef struct { + uint32_t u32PinDir; /*!< Input/Output setting, @ref EP_PinDirection_Sel for details */ + en_ep_state_t enPinState; /*!< Corresponding pin initial state, @ref en_ep_state_t for details */ + uint32_t u32PinTriggerOps; /*!< Corresponding pin state after triggered, @ref EP_TriggerOps_Sel for details */ + uint32_t u32Edge; /*!< Event port trigger edge, @ref EP_Trigger_Sel for details */ + uint32_t u32Filter; /*!< Filter clock function setting, @ref EP_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< Filter clock, ref@ EP_FilterClock_Div for details */ +} stc_ep_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Global_Macros Event Port Global Macros + * @{ + */ + +/** + * @defgroup EP_Port_source EP Port Source + * @{ + */ +#define EVT_PORT_1 (0U) /*!< Event port 1 */ +#define EVT_PORT_2 (1U) /*!< Event port 2 */ +#define EVT_PORT_3 (2U) /*!< Event port 3 */ +#define EVT_PORT_4 (3U) /*!< Event port 4 */ +/** + * @} + */ + +/** + * @defgroup EP_pins_define EP Pin Source + * @{ + */ +#define EVT_PIN_00 (0x0001U) /*!< Event port Pin 00 */ +#define EVT_PIN_01 (0x0002U) /*!< Event port Pin 01 */ +#define EVT_PIN_02 (0x0004U) /*!< Event port Pin 02 */ +#define EVT_PIN_03 (0x0008U) /*!< Event port Pin 03 */ +#define EVT_PIN_04 (0x0010U) /*!< Event port Pin 04 */ +#define EVT_PIN_05 (0x0020U) /*!< Event port Pin 05 */ +#define EVT_PIN_06 (0x0040U) /*!< Event port Pin 06 */ +#define EVT_PIN_07 (0x0080U) /*!< Event port Pin 07 */ +#define EVT_PIN_08 (0x0100U) /*!< Event port Pin 08 */ +#define EVT_PIN_09 (0x0200U) /*!< Event port Pin 09 */ +#define EVT_PIN_10 (0x0400U) /*!< Event port Pin 10 */ +#define EVT_PIN_11 (0x0800U) /*!< Event port Pin 11 */ +#define EVT_PIN_12 (0x1000U) /*!< Event port Pin 12 */ +#define EVT_PIN_13 (0x2000U) /*!< Event port Pin 13 */ +#define EVT_PIN_14 (0x4000U) /*!< Event port Pin 14 */ +#define EVT_PIN_15 (0x8000U) /*!< Event port Pin 15 */ +#define EVT_PIN_All (0xFFFFU) /*!< All event pins are selected */ +#define EVT_PIN_MASK (0xFFFFU) /*!< Event pin mask for assert test */ +/** + * @} + */ + +/** + * @defgroup EP_PinDirection_Sel EP Pin Input/Output Direction Selection + * @{ + */ +#define EP_DIR_IN (0UL) /*!< EP input */ +#define EP_DIR_OUT (1UL) /*!< EP output */ +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Sel Event Port Filter Function Selection + * @{ + */ +#define EP_FILTER_OFF (0UL) /*!< EP filter function OFF */ + +#define EP_FILTER_ON (1UL) /*!< EP filter function ON */ + +/** + * @} + */ + +/** + * @defgroup EP_FilterClock_Div Event Port Filter Sampling Clock Division Selection + * @{ + */ +#define EP_FCLK_DIV1 (0UL) /*!< PCLK as EP filter clock source */ +#define EP_FCLK_DIV8 (1UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div8 as EP filter clock source */ +#define EP_FCLK_DIV32 (2UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div32 as EP filter clock source */ +#define EP_FCLK_DIV64 (3UL << AOS_PEVNTNFCR_DIVS1_POS) /*!< PCLK div64 as EP filter clock source */ +/** + * @} + */ + +/** + * @defgroup EP_Trigger_Sel Event Port Trigger Edge Selection + * @{ + */ +#define EP_TRIG_NONE (0UL) /*!< No Trigger by edge */ +#define EP_TRIG_FALLING (1UL) /*!< Trigger by falling edge */ +#define EP_TRIG_RISING (2UL) /*!< Trigger by rising edge */ +#define EP_TRIG_BOTH (3UL) /*!< Trigger by falling and rising edge */ +/** + * @} + */ + +/** + * @defgroup EP_TriggerOps_Sel Event Port Operation + * @{ + */ +#define EP_OPS_NONE (0UL) /*!< Pin no action after triggered */ +#define EP_OPS_LOW (1UL) /*!< Pin ouput low after triggered */ +#define EP_OPS_HIGH (2UL) /*!< Pin ouput high after triggered */ +#define EP_OPS_TOGGLE (3UL) /*!< Pin toggle after triggered */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EP_Global_Functions + * @{ + */ +void EP_DeInit(void); +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit); + +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit); +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge); +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops); +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadInputPort(uint8_t u8EventPort); +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin); +uint16_t EP_ReadOutputPort(uint8_t u8EventPort); +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin); +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir); + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_EVENT_PORT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h new file mode 100644 index 0000000000..10c948bfc7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcg.h @@ -0,0 +1,198 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.h + * @brief This file contains all the functions prototypes of the FCG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCG_H__ +#define __HC32_LL_FCG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCG + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Macros FCG Global Macros + * @{ + */ +/** + * @defgroup FCG_FCG0_Peripheral FCG FCG0 peripheral + * @{ + */ +#define FCG0_PERIPH_SRAMH (PWC_FCG0_SRAMH) +#define FCG0_PERIPH_SRAM0 (PWC_FCG0_SRAM0) +#define FCG0_PERIPH_SRAMB (PWC_FCG0_SRAMB) +#define FCG0_PERIPH_KEY (PWC_FCG0_KEY) +#define FCG0_PERIPH_DMA1 (PWC_FCG0_DMA1) +#define FCG0_PERIPH_DMA2 (PWC_FCG0_DMA2) +#define FCG0_PERIPH_FCM (PWC_FCG0_FCM) +#define FCG0_PERIPH_AOS (PWC_FCG0_AOS) +#define FCG0_PERIPH_CTC (PWC_FCG0_CTC) +#define FCG0_PERIPH_AES (PWC_FCG0_AES) +#define FCG0_PERIPH_HASH (PWC_FCG0_HASH) +#define FCG0_PERIPH_TRNG (PWC_FCG0_TRNG) +#define FCG0_PERIPH_CRC (PWC_FCG0_CRC) +#define FCG0_PERIPH_DCU1 (PWC_FCG0_DCU1) +#define FCG0_PERIPH_DCU2 (PWC_FCG0_DCU2) +#define FCG0_PERIPH_DCU3 (PWC_FCG0_DCU3) +#define FCG0_PERIPH_DCU4 (PWC_FCG0_DCU4) +/** + * @} + */ + +/** + * @defgroup FCG_FCG1_Peripheral FCG FCG1 peripheral + * @{ + */ +#define FCG1_PERIPH_MCAN1 (PWC_FCG1_MCAN1) +#define FCG1_PERIPH_MCAN2 (PWC_FCG1_MCAN2) +#define FCG1_PERIPH_QSPI (PWC_FCG1_QSPI) +#define FCG1_PERIPH_I2C1 (PWC_FCG1_I2C1) +#define FCG1_PERIPH_I2C2 (PWC_FCG1_I2C2) +#define FCG1_PERIPH_SPI1 (PWC_FCG1_SPI1) +#define FCG1_PERIPH_SPI2 (PWC_FCG1_SPI2) +#define FCG1_PERIPH_SPI3 (PWC_FCG1_SPI3) +/** + * @} + */ + +/** + * @defgroup FCG_FCG2_Peripheral FCG FCG2 peripheral + * @{ + */ +#define FCG2_PERIPH_TMR6_1 (PWC_FCG2_TMR6_1) +#define FCG2_PERIPH_TMR6_2 (PWC_FCG2_TMR6_2) +#define FCG2_PERIPH_TMR4_1 (PWC_FCG2_TMR4_1) +#define FCG2_PERIPH_TMR4_2 (PWC_FCG2_TMR4_2) +#define FCG2_PERIPH_TMR4_3 (PWC_FCG2_TMR4_3) +#define FCG2_PERIPH_TMR0_1 (PWC_FCG2_TMR0_1) +#define FCG2_PERIPH_TMR0_2 (PWC_FCG2_TMR0_2) +#define FCG2_PERIPH_EMB (PWC_FCG2_EMB) +#define FCG2_PERIPH_TMRA_1 (PWC_FCG2_TMRA_1) +#define FCG2_PERIPH_TMRA_2 (PWC_FCG2_TMRA_2) +#define FCG2_PERIPH_TMRA_3 (PWC_FCG2_TMRA_3) +#define FCG2_PERIPH_TMRA_4 (PWC_FCG2_TMRA_4) +#define FCG2_PERIPH_TMRA_5 (PWC_FCG2_TMRA_5) +/** + * @} + */ + +/** + * @defgroup FCG_FCG3_Peripheral FCG FCG3 peripheral + * @{ + */ +#define FCG3_PERIPH_ADC1 (PWC_FCG3_ADC1) +#define FCG3_PERIPH_ADC2 (PWC_FCG3_ADC2) +#define FCG3_PERIPH_ADC3 (PWC_FCG3_ADC3) +#define FCG3_PERIPH_DAC (PWC_FCG3_DAC) +#define FCG3_PERIPH_CMP1_2 (PWC_FCG3_CMP12) +#define FCG3_PERIPH_CMP3_4 (PWC_FCG3_CMP34) +#define FCG3_PERIPH_SMC (PWC_FCG3_SMC) +#define FCG3_PERIPH_USART1 (PWC_FCG3_USART1) +#define FCG3_PERIPH_USART2 (PWC_FCG3_USART2) +#define FCG3_PERIPH_USART3 (PWC_FCG3_USART3) +#define FCG3_PERIPH_USART4 (PWC_FCG3_USART4) +#define FCG3_PERIPH_USART5 (PWC_FCG3_USART5) +#define FCG3_PERIPH_USART6 (PWC_FCG3_USART6) +/** + * @} + */ + +/** + * @defgroup FCG_FCGx_Peripheral_Mask FCG FCGx Peripheral Mask + * @{ + */ +#define FCG_FCG0_PERIPH_MASK (0x0FF7E411UL) +#define FCG_FCG1_PERIPH_MASK (0x0007003BUL) +#define FCG_FCG2_PERIPH_MASK (0x01F0BE03UL) +#define FCG_FCG3_PERIPH_MASK (0x03F10317UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCG_Global_Functions + * @{ + */ + +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); + +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h new file mode 100644 index 0000000000..7664db23b4 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_fcm.h @@ -0,0 +1,290 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.h + * @brief This file contains all the functions prototypes of the FCM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_FCM_H__ +#define __HC32_LL_FCM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_FCM + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Types FCM Global Types + * @{ + */ +/** + * @brief FCM Init structure definition + */ +typedef struct { + uint16_t u16LowerLimit; /*!< FCM lower limit value */ + uint16_t u16UpperLimit; /*!< FCM upper limit value */ + uint32_t u32TargetClock; /*!< FCM target clock source selection, @ref FCM_Target_Clock_Src */ + uint32_t u32TargetClockDiv; /*!< FCM target clock source division selection, @ref FCM_Target_Clock_Div */ + uint32_t u32ExtRefClockEnable; /*!< FCM external reference clock function config, @ref FCM_Ext_Ref_Clock_Config */ + uint32_t u32RefClockEdge; /*!< FCM reference clock trigger edge selection, @ref FCM_Ref_Clock_Edge */ + uint32_t u32DigitalFilter; /*!< FCM digital filter function config, @ref FCM_Digital_Filter_Config */ + uint32_t u32RefClock; /*!< FCM reference clock source selection, @ref FCM_Ref_Clock_Src */ + uint32_t u32RefClockDiv; /*!< FCM reference clock source division selection, @ref FCM_Ref_Clock_Div */ + uint32_t u32ExceptionType; /*!< FCM exception type select, @ref FCM_Exception_Type */ +} stc_fcm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Macros FCM Global Macros + * @{ + */ + +/** + * @defgroup FCM_Target_Clock_Src FCM Target Clock Source + * @{ + */ +#define FCM_TARGET_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS) +#define FCM_TARGET_CLK_PLLHP (0x08UL << FCM_MCCR_MCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Target_Clock_Div FCM Target Clock Division + * @{ + */ +#define FCM_TARGET_CLK_DIV1 (0x00UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV4 (0x01UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV8 (0x02UL << FCM_MCCR_MDIVS_POS) +#define FCM_TARGET_CLK_DIV32 (0x03UL << FCM_MCCR_MDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Ext_Ref_Clock_Config FCM External Reference Clock Config + * @{ + */ +#define FCM_EXT_REF_OFF (0x00UL) +#define FCM_EXT_REF_ON (FCM_RCCR_EXREFE) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Edge FCM Reference Clock Edge + * @{ + */ +#define FCM_REF_CLK_RISING (0x00UL) +#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0) +#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1) +/** + * @} + */ + +/** + * @defgroup FCM_Digital_Filter_Config FCM Digital Filter Config + * @{ + */ +#define FCM_DIG_FILTER_OFF (0x00UL) +#define FCM_DIG_FILTER_DIV1 (FCM_RCCR_DNFS_0) +#define FCM_DIG_FILTER_DIV4 (FCM_RCCR_DNFS_1) +#define FCM_DIG_FILTER_DIV16 (FCM_RCCR_DNFS) +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Src FCM Reference Clock Source + * @{ + */ +#define FCM_REF_CLK_EXTCLK (0x00UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PLLHP (0x18UL << FCM_RCCR_RCKS_POS) + +/** + * @} + */ + +/** + * @defgroup FCM_Ref_Clock_Div FCM Reference Clock Division + * @{ + */ +#define FCM_REF_CLK_DIV32 (0x00UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV128 (0x01UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV1024 (0x02UL << FCM_RCCR_RDIVS_POS) +#define FCM_REF_CLK_DIV8192 (0x03UL << FCM_RCCR_RDIVS_POS) +/** + * @} + */ + +/** + * @defgroup FCM_Abnormal_Reset_Func FCM Abnormal Reset Function Config + * @{ + */ +#define FCM_ERR_RST_OFF (0x00UL) +#define FCM_ERR_RST_ON (FCM_RIER_ERRE) +/** + * @} + */ + +/** + * @defgroup FCM_Exception_Type FCM Exception Type + * @{ + */ +#define FCM_EXP_TYPE_INT (0x00UL) +#define FCM_EXP_TYPE_RST (FCM_RIER_ERRINTRS) +/** + * @} + */ + +/** + * @defgroup FCM_Int_Type FCM Interrupt Type + * @{ + */ +#define FCM_INT_OVF (FCM_RIER_OVFIE) +#define FCM_INT_END (FCM_RIER_MENDIE) +#define FCM_INT_ERR (FCM_RIER_ERRIE) +/** + * @} + */ + +/** + * @defgroup FCM_Flag_Sel FCM Status Flag Selection + * @{ + */ +#define FCM_FLAG_ERR (FCM_SR_ERRF) +#define FCM_FLAG_END (FCM_SR_MENDF) +#define FCM_FLAG_OVF (FCM_SR_OVF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCM_Global_Functions + * @{ + */ + +/** + * @brief Set FCM upper limit value. + * @param u16Limit + * @retval None. + */ +__STATIC_INLINE void FCM_SetUpperLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->UVR, u16Limit); +} + +/** + * @brief Set FCM lower limit value. + * @param u16Limit + * @retval None + */ +__STATIC_INLINE void FCM_SetLowerLimit(uint16_t u16Limit) +{ + WRITE_REG32(CM_FCM->LVR, u16Limit); +} + +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit); +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit); +int32_t FCM_DeInit(void); +uint16_t FCM_GetCountValue(void); +void FCM_SetUpperLimit(uint16_t u16Limit); +void FCM_SetLowerLimit(uint16_t u16Limit); +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div); +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div); +en_flag_status_t FCM_GetStatus(uint32_t u32Flag); +void FCM_ClearStatus(uint32_t u32Flag); +void FCM_ResetCmd(en_functional_state_t enNewState); +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +void FCM_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_FCM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h new file mode 100644 index 0000000000..586f2c5b6c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_gpio.h @@ -0,0 +1,451 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.h + * @brief This file contains all the functions prototypes of the GPIO driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_GPIO_H__ +#define __HC32_LL_GPIO_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_GPIO + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Types GPIO Global Types + * @{ + */ + +/** + * @brief GPIO Pin Set and Reset enumeration + */ +typedef enum { + PIN_RESET = 0U, /*!< Pin reset */ + PIN_SET = 1U /*!< Pin set */ +} en_pin_state_t; + +/** + * @brief GPIO Init structure definition + */ +typedef struct { + uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ + uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */ + uint16_t u16PinOutputType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */ + uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */ + uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */ + uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */ + uint16_t u16PullDown; /*!< Internal pull-down register setting, @ref GPIO_PinPD_Sel for details */ + uint16_t u16InputMos; /*!< Input MOS always on selection, @ref GPIO_PinInputMOS_Sel for details */ + uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel for details */ + uint16_t u16ExtInt; /*!< External interrupt pin setting, @ref GPIO_PinExtInt_Sel for details */ + uint16_t u16PinInputType; /*!< Input type setting, @ref GPIO_PinInType_Sel for details */ + uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */ +} stc_gpio_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Macros GPIO Global Macros + * @{ + */ + +/** + * @defgroup GPIO_Pins_Define GPIO Pin Source + * @{ + */ +#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */ +#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */ +#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */ +#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */ +#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */ +#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */ +#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */ +#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */ +#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */ +#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */ +#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */ +#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */ +#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */ +#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */ +#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */ +#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */ +/** + * @} + */ + +/** + * @defgroup GPIO_All_Pins_Define GPIO All Pin Definition for Each Product + * @{ + */ +#define GPIO_PIN_A_ALL (0xFFFFU) /*!< Pin A all*/ +#define GPIO_PIN_B_ALL (0xFFFFU) /*!< Pin B all*/ +#define GPIO_PIN_C_ALL (0xFFFFU) /*!< Pin C all*/ +#define GPIO_PIN_D_ALL (0x0F07U) /*!< Pin D all*/ +#define GPIO_PIN_E_ALL (0xF01FU) /*!< Pin E all*/ +#define GPIO_PIN_H_ALL (0x0007U) /*!< Pin H all*/ +/** + * @} + */ + +/** + * @defgroup GPIO_Port_Source GPIO Port Source + * @{ + */ +#define GPIO_PORT_A (0x00U) /*!< Port A selected */ +#define GPIO_PORT_B (0x01U) /*!< Port B selected */ +#define GPIO_PORT_C (0x02U) /*!< Port C selected */ +#define GPIO_PORT_D (0x03U) /*!< Port D selected */ +#define GPIO_PORT_E (0x04U) /*!< Port E selected */ +#define GPIO_PORT_H (0x05U) /*!< Port H selected */ +/** + * @} + */ + +/** + * @defgroup GPIO_Function_Sel GPIO Function Selection + * @{ + */ +#define GPIO_FUNC_0 (0U) +#define GPIO_FUNC_1 (1U) +#define GPIO_FUNC_2 (2U) +#define GPIO_FUNC_3 (3U) +#define GPIO_FUNC_4 (4U) +#define GPIO_FUNC_5 (5U) +#define GPIO_FUNC_6 (6U) +#define GPIO_FUNC_7 (7U) +#define GPIO_FUNC_8 (8U) +#define GPIO_FUNC_11 (11U) +#define GPIO_FUNC_12 (12U) +#define GPIO_FUNC_13 (13U) +#define GPIO_FUNC_14 (14U) +#define GPIO_FUNC_15 (15U) +#define GPIO_FUNC_21 (21U) +#define GPIO_FUNC_22 (22U) +#define GPIO_FUNC_32 (32U) +#define GPIO_FUNC_33 (33U) +#define GPIO_FUNC_34 (34U) +#define GPIO_FUNC_35 (35U) +#define GPIO_FUNC_36 (36U) +#define GPIO_FUNC_37 (37U) +#define GPIO_FUNC_38 (38U) +#define GPIO_FUNC_39 (39U) +#define GPIO_FUNC_40 (40U) +#define GPIO_FUNC_41 (41U) +#define GPIO_FUNC_42 (42U) +#define GPIO_FUNC_43 (43U) +#define GPIO_FUNC_44 (44U) +#define GPIO_FUNC_45 (45U) +#define GPIO_FUNC_46 (46U) +#define GPIO_FUNC_47 (47U) +#define GPIO_FUNC_48 (48U) +#define GPIO_FUNC_49 (49U) +#define GPIO_FUNC_50 (50U) +#define GPIO_FUNC_51 (51U) +#define GPIO_FUNC_52 (52U) +#define GPIO_FUNC_53 (53U) +#define GPIO_FUNC_54 (54U) +#define GPIO_FUNC_55 (55U) +#define GPIO_FUNC_56 (56U) +#define GPIO_FUNC_57 (57U) +/** + * @} + */ + +/** + * @defgroup GPIO_DebugPin_Sel GPIO Debug Pin Selection + * @{ + */ +#define GPIO_PIN_TCK (0x01U) +#define GPIO_PIN_TMS (0x02U) +#define GPIO_PIN_TDO (0x04U) +#define GPIO_PIN_TDI (0x08U) +#define GPIO_PIN_TRST (0x10U) +#define GPIO_PIN_DEBUG_JTAG (0x1FU) +#define GPIO_PIN_SWCLK (0x01U) +#define GPIO_PIN_SWDIO (0x02U) +#define GPIO_PIN_SWO (0x04U) +#define GPIO_PIN_DEBUG_SWD (0x07U) +#define GPIO_PIN_DEBUG (0x1FU) +/** + * @} + */ + +/** + * @defgroup GPIO_ReadCycle_Sel GPIO Pin Read Wait Cycle Selection + * @{ + */ +#define GPIO_RD_WAIT0 (0x00U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT1 (0x01U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT2 (0x02U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT3 (0x03U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT4 (0x04U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT5 (0x05U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT6 (0x06U << GPIO_PCCR_RDWT_POS) +#define GPIO_RD_WAIT7 (0x07U << GPIO_PCCR_RDWT_POS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinState_Sel GPIO Pin Output State Selection + * @{ + */ +#define PIN_STAT_RST (0U) +#define PIN_STAT_SET (GPIO_PCR_POUT) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDirection_Sel GPIO Pin Input/Output Direction Selection + * @{ + */ +#define PIN_DIR_IN (0U) +#define PIN_DIR_OUT (GPIO_PCR_POUTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinOutType_Sel GPIO Pin Output Type Selection + * @{ + */ +#define PIN_OUT_TYPE_CMOS (0U) +#define PIN_OUT_TYPE_NMOS (GPIO_PCR_NOD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDrv_Sel GPIO Pin Drive Capacity Selection + * @{ + */ +#define PIN_LOW_DRV (0U) +#define PIN_MID_DRV (GPIO_PCR_DRV_0) +#define PIN_HIGH_DRV (GPIO_PCR_DRV_1) +/** + * @} + */ + +/** + * @defgroup GPIO_PinLatch_Sel GPIO Pin Output Latch Selection + * @{ + */ +#define PIN_LATCH_OFF (0U) +#define PIN_LATCH_ON (GPIO_PCR_LTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPU_Sel GPIO Pin Internal Pull-Up Resistor Selection + * @{ + */ +#define PIN_PU_OFF (0U) +#define PIN_PU_ON (GPIO_PCR_PUU) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPD_Sel GPIO Pin Internal Pull-Down Resistor Selection + * @{ + */ +#define PIN_PD_OFF (0U) +#define PIN_PD_ON (GPIO_PCR_PUD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInputMOS_Sel GPIO Pin Input MOS Always On selection + * @{ + */ +#define PIN_IN_MOS_OFF (0U) +#define PIN_IN_MOS_ON (GPIO_PCR_PINAE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInvert_Sel GPIO Pin I/O Invert Selection + * @{ + */ +#define PIN_INVT_OFF (0U) +#define PIN_INVT_ON (GPIO_PCR_INVE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInType_Sel GPIO Pin Input Type Selection + * @{ + */ +#define PIN_IN_TYPE_SMT (0U) +#define PIN_IN_TYPE_CMOS (GPIO_PCR_CINSEL) +/** + * @} + */ + +/** + * @defgroup GPIO_PinExtInt_Sel GPIO Pin External Interrupt Selection + * @{ + */ +#define PIN_EXTINT_OFF (0U) +#define PIN_EXTINT_ON (GPIO_PCR_INTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinMode_Sel GPIO Pin Mode Selection + * @{ + */ +#define PIN_ATTR_DIGITAL (0U) +#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin Sub-function Enable or Disable + * @{ + */ +#define PIN_SUBFUNC_DISABLE (0U) +#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE) +/** + * @} + */ + +/** + * @defgroup GPIO_Register_Protect_Key GPIO Registers Protect Key + * @{ + */ +#define GPIO_REG_LOCK_KEY (0xA500U) +#define GPIO_REG_UNLOCK_KEY (0xA501U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup GPIO_Global_Functions + * @{ + */ +/** + * @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Lock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_LOCK_KEY); +} + +/** + * @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_REG_Unlock(void) +{ + WRITE_REG16(CM_GPIO->PWPR, GPIO_REG_UNLOCK_KEY); +} + +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit); +void GPIO_DeInit(void); +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit); +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState); +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func); +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +void GPIO_SetSubFunc(uint8_t u8Func); +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait); +void GPIO_InputMOSCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadInputPort(uint8_t u8Port); +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadOutputPort(uint8_t u8Port); +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal); +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_ExtIntCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +void GPIO_AnalogCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h new file mode 100644 index 0000000000..ca72429e16 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_hash.h @@ -0,0 +1,94 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.h + * @brief This file contains all the functions prototypes of the HASH driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_HASH_H__ +#define __HC32_LL_HASH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_HASH + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HASH_Global_Functions + * @{ + */ + +int32_t HASH_DeInit(void); +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest); + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h new file mode 100644 index 0000000000..70ab2f32e2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_i2c.h @@ -0,0 +1,396 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.h + * @brief This file contains all the functions prototypes of the Inter-Integrated + * Circuit(I2C) driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Move macro define I2C_SRC_CLK to head file and add marco I2C_WIDTH_MAX_IMME + 2023-12-15 CDT Rename I2C_FIFO_FLAG_xx as I2C_FLAG_xx_FIFO_xx, I2C_INT_RFREQ as I2C_INT_RX_FIFO_REQ + Adjust I2C_FLAG_ALL & I2C_FLAG_CLR_ALL & I2C_INT_ALL + Add I2C_Flag_Clear def group + Remove API I2C_FIFO_ClearRequestStatus() & I2C_FIFO_GetStatus + Fix I2C_Deinit + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_I2C_H__ +#define __HC32_LL_I2C_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_I2C + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2C_Global_Types I2C Global Types + * @{ + */ + +/** + * @brief I2c configuration structure + */ +typedef struct { + uint32_t u32ClockDiv; /*!< I2C clock division for i2c source clock */ + uint32_t u32Baudrate; /*!< I2C baudrate config */ + uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(i2c source clock after frequency divider) */ +} stc_i2c_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Macros I2C Global Macros + * @{ + */ + +#define I2C_SRC_CLK (SystemCoreClock >> ((CM_CMU->SCFGR & CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS)) + +#define I2C_WIDTH_MAX_IMME (516UL) + +/** + * @defgroup I2C_Trans_Dir I2C Transfer Direction + * @{ + */ +#define I2C_DIR_TX (0x0U) +#define I2C_DIR_RX (0x1U) +/** + * @} + */ + +/** + * @defgroup I2C_Addr_Config I2C Address Configure + * @{ + */ +#define I2C_ADDR_DISABLE (0U) +#define I2C_ADDR_7BIT (I2C_SLR0_SLADDR0EN) +#define I2C_ADDR_10BIT (I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0EN) +/** + * @} + */ + +/** + * @defgroup I2C_Clock_Division I2C Clock Division + * @{ + */ +#define I2C_CLK_DIV1 (0UL) /*!< I2c source clock/1 */ +#define I2C_CLK_DIV2 (1UL) /*!< I2c source clock/2 */ +#define I2C_CLK_DIV4 (2UL) /*!< I2c source clock/4 */ +#define I2C_CLK_DIV8 (3UL) /*!< I2c source clock/8 */ +#define I2C_CLK_DIV16 (4UL) /*!< I2c source clock/16 */ +#define I2C_CLK_DIV32 (5UL) /*!< I2c source clock/32 */ +#define I2C_CLK_DIV64 (6UL) /*!< I2c source clock/64 */ +#define I2C_CLK_DIV128 (7UL) /*!< I2c source clock/128 */ +/** + * @} + */ + +/** + * @defgroup I2C_Address_Num I2C Address Number + * @{ + */ +#define I2C_ADDR0 (0UL) +#define I2C_ADDR1 (1UL) +/** + * @} + */ + +/** + * @defgroup I2C_Ack_Config I2C ACK Configure + * @{ + */ +#define I2C_ACK (0UL) /*!< Send ACK after date receive */ +#define I2C_NACK (I2C_CR1_ACK) /*!< Send NACK after date received */ +/** + * @} + */ + +/** + * @defgroup I2C_Smbus_Match_Config I2C SMBUS Address Match Configure + * @{ + */ +#define I2C_SMBUS_MATCH_ALARM (I2C_CR1_SMBALRTEN) +#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN) +#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN) +#define I2C_SMBUS_MATCH_ALL (I2C_CR1_SMBALRTEN | I2C_CR1_SMBDEFAULTEN | I2C_CR1_SMBHOSTEN) +/** + * @} + */ + +/** + * @defgroup I2C_Digital_Filter_Clock I2C Digital Filter Clock + * @{ + */ +#define I2C_DIG_FILTER_CLK_DIV1 (0UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/1 */ +#define I2C_DIG_FILTER_CLK_DIV2 (1UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/2 */ +#define I2C_DIG_FILTER_CLK_DIV3 (2UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/3 */ +#define I2C_DIG_FILTER_CLK_DIV4 (3UL << I2C_FLTR_DNF_POS) /*!< I2C Clock/4 */ +/** + * @} + */ + +/** + * @defgroup I2C_Flag I2C Flag + * @{ + */ +#define I2C_FLAG_START (I2C_SR_STARTF) /*!< Start condition detected */ +#define I2C_FLAG_MATCH_ADDR0 (I2C_SR_SLADDR0F) /*!< Address 0 detected */ +#define I2C_FLAG_MATCH_ADDR1 (I2C_SR_SLADDR1F) /*!< Address 1 detected */ +#define I2C_FLAG_TX_CPLT (I2C_SR_TENDF) /*!< Transfer end */ +#define I2C_FLAG_STOP (I2C_SR_STOPF) /*!< Stop condition detected */ +#define I2C_FLAG_RX_FULL (I2C_SR_RFULLF) /*!< Receive buffer full */ +#define I2C_FLAG_TX_EMPTY (I2C_SR_TEMPTYF) /*!< Transfer buffer empty */ +#define I2C_FLAG_ARBITRATE_FAIL (I2C_SR_ARLOF) /*!< Arbitration fails */ +#define I2C_FLAG_ACKR (I2C_SR_ACKRF) /*!< ACK status */ +#define I2C_FLAG_NACKF (I2C_SR_NACKF) /*!< NACK detected */ +#define I2C_FLAG_TMOUTF (I2C_SR_TMOUTF) /*!< Time out detected */ +#define I2C_FLAG_MASTER (I2C_SR_MSL) /*!< Master mode flag */ +#define I2C_FLAG_BUSY (I2C_SR_BUSY) /*!< Bus busy status */ +#define I2C_FLAG_TRA (I2C_SR_TRA) /*!< Transfer mode flag */ +#define I2C_FLAG_GENERAL_CALL (I2C_SR_GENCALLF) /*!< General call detected */ +#define I2C_FLAG_SMBUS_DEFAULT_MATCH (I2C_SR_SMBDEFAULTF) /*!< SMBUS default address detected */ +#define I2C_FLAG_SMBUS_HOST_MATCH (I2C_SR_SMBHOSTF) /*!< SMBUS host address detected */ +#define I2C_FLAG_SMBUS_ALARM_MATCH (I2C_SR_SMBALRTF) /*!< SMBUS alarm address detected */ +#define I2C_FLAG_RX_FIFO_REQ (I2C_SR_RFREQ) /*!< Receive FIFO request */ +#define I2C_FLAG_RX_FIFO_FULL (I2C_SR_RFFULL) /*!< Receive FIFO full */ +#define I2C_FLAG_RX_FIFO_EMPTY (I2C_SR_RFEMPTY) /*!< Receive FIFO empty */ +#define I2C_FLAG_TX_FIFO_FULL (I2C_SR_TFFULL) /*!< Transfer FIFO full */ +#define I2C_FLAG_TX_FIFO_EMPTY (I2C_SR_TFEMPTY) /*!< Transfer FIFO empty */ + +#define I2C_FLAG_ALL (I2C_FLAG_START | I2C_FLAG_NACKF | \ + I2C_FLAG_MATCH_ADDR0 | I2C_FLAG_TMOUTF | \ + I2C_FLAG_MATCH_ADDR1 | I2C_FLAG_MASTER | \ + I2C_FLAG_TX_CPLT | I2C_FLAG_BUSY | \ + I2C_FLAG_STOP | I2C_FLAG_TRA | \ + I2C_FLAG_RX_FULL | I2C_FLAG_GENERAL_CALL | \ + I2C_FLAG_TX_EMPTY | I2C_FLAG_SMBUS_DEFAULT_MATCH | \ + I2C_FLAG_ARBITRATE_FAIL | I2C_FLAG_SMBUS_HOST_MATCH | \ + I2C_FLAG_ACKR | I2C_FLAG_SMBUS_ALARM_MATCH | \ + I2C_FLAG_RX_FIFO_REQ | I2C_FLAG_RX_FIFO_FULL | \ + I2C_FLAG_RX_FIFO_EMPTY | I2C_FLAG_TX_FIFO_FULL | \ + I2C_FLAG_TX_FIFO_EMPTY) +/** + * @} + */ + +/** + * @defgroup I2C_Flag_Clear I2C Flag to clear + * @{ + */ +#define I2C_FLAG_CLR_START (I2C_CLR_STARTFCLR) /*!< Start condition detected */ +#define I2C_FLAG_CLR_MATCH_ADDR0 (I2C_CLR_SLADDR0FCLR) /*!< Address 0 detected */ +#define I2C_FLAG_CLR_MATCH_ADDR1 (I2C_CLR_SLADDR1FCLR) /*!< Address 1 detected */ +#define I2C_FLAG_CLR_TX_CPLT (I2C_CLR_TENDFCLR) /*!< Transfer end */ +#define I2C_FLAG_CLR_STOP (I2C_CLR_STOPFCLR) /*!< Stop condition detected */ +#define I2C_FLAG_CLR_RX_FULL (I2C_CLR_RFULLFCLR) /*!< Receive buffer full */ +#define I2C_FLAG_CLR_ARBITRATE_FAIL (I2C_CLR_ARLOFCLR) /*!< Arbitration fails */ +#define I2C_FLAG_CLR_NACK (I2C_CLR_NACKFCLR) /*!< NACK detected */ +#define I2C_FLAG_CLR_TMOUTF (I2C_CLR_TMOUTFCLR) /*!< Time out detected */ +#define I2C_FLAG_CLR_GENERAL_CALL (I2C_CLR_GENCALLFCLR) /*!< General call detected */ +#define I2C_FLAG_CLR_SMBUS_DEFAULT_MATCH (I2C_CLR_SMBDEFAULTFCLR) /*!< SMBUS default address detected */ +#define I2C_FLAG_CLR_SMBUS_HOST_MATCH (I2C_CLR_SMBHOSTFCLR) /*!< SMBUS host address detected */ +#define I2C_FLAG_CLR_SMBUS_ALARM_MATCH (I2C_CLR_SMBALRTFCLR) /*!< SMBUS alarm address detected */ +#define I2C_FLAG_CLR_RX_FIFO_REQ (I2C_CLR_RFREQCLR) /*!< Receive FIFO request */ + +#define I2C_FLAG_CLR_ALL (I2C_FLAG_CLR_START | I2C_FLAG_CLR_ARBITRATE_FAIL | \ + I2C_FLAG_CLR_MATCH_ADDR0 | I2C_FLAG_CLR_NACK | \ + I2C_FLAG_CLR_MATCH_ADDR1 | I2C_FLAG_CLR_TMOUTF | \ + I2C_FLAG_CLR_TX_CPLT | I2C_FLAG_CLR_GENERAL_CALL | \ + I2C_FLAG_CLR_STOP | I2C_FLAG_CLR_SMBUS_DEFAULT_MATCH | \ + I2C_FLAG_CLR_RX_FULL | I2C_FLAG_CLR_SMBUS_HOST_MATCH | \ + I2C_FLAG_CLR_SMBUS_ALARM_MATCH | \ + I2C_FLAG_CLR_RX_FIFO_REQ) + +/** + * @} + */ + +/** + * @defgroup I2C_FIFO_Data_Status I2C FIFO status + * @{ + */ +#define I2C_FIFO_EMPTY (0U) +#define I2C_FIFO_HALFFULL (1U) +#define I2C_FIFO_FULL (2U) +/** + * @} + */ + +/** + * @defgroup I2C_Int_Flag I2C Interrupt Flag Bits + * @{ + */ +#define I2C_INT_START (I2C_CR2_STARTIE) +#define I2C_INT_MATCH_ADDR0 (I2C_CR2_SLADDR0IE) +#define I2C_INT_MATCH_ADDR1 (I2C_CR2_SLADDR1IE) +#define I2C_INT_TX_CPLT (I2C_CR2_TENDIE) +#define I2C_INT_STOP (I2C_CR2_STOPIE) +#define I2C_INT_RX_FULL (I2C_CR2_RFULLIE) +#define I2C_INT_TX_EMPTY (I2C_CR2_TEMPTYIE) +#define I2C_INT_ARBITRATE_FAIL (I2C_CR2_ARLOIE) +#define I2C_INT_NACK (I2C_CR2_NACKIE) +#define I2C_INT_TMOUTIE (I2C_CR2_TMOUTIE) +#define I2C_INT_GENERAL_CALL (I2C_CR2_GENCALLIE) +#define I2C_INT_SMBUS_DEFAULT_MATCH (I2C_CR2_SMBDEFAULTIE) +#define I2C_INT_SMBUS_HOST_MATCH (I2C_CR2_SMBHOSTIE) +#define I2C_INT_SMBUS_ALARM_MATCH (I2C_CR2_SMBALRTIE) +#define I2C_INT_RX_FIFO_REQ (I2C_CR2_RFREQIE) +#define I2C_INT_ALL (I2C_INT_START | I2C_INT_ARBITRATE_FAIL | \ + I2C_INT_MATCH_ADDR0 | I2C_INT_NACK | \ + I2C_INT_MATCH_ADDR1 | I2C_INT_TMOUTIE | \ + I2C_INT_TX_CPLT | I2C_INT_GENERAL_CALL | \ + I2C_INT_STOP | I2C_INT_SMBUS_DEFAULT_MATCH | \ + I2C_INT_RX_FULL | I2C_INT_SMBUS_HOST_MATCH | \ + I2C_INT_TX_EMPTY | I2C_INT_SMBUS_ALARM_MATCH | \ + I2C_INT_RX_FIFO_REQ) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2C_Global_Functions + * @{ + */ + +/* Initialization and Configuration **********************************/ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit); +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +int32_t I2C_DeInit(CM_I2C_TypeDef *I2Cx); +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error); +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr); +void I2C_SlaveAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState); +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState); +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock); +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState); + +void I2C_SlaveMaskAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32MaskAddr); +void I2C_SlaveMaskAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState); + +void I2C_BusFreeClearCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +/* Start/Restart/Stop ************************************************/ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx); +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx); + +/* Status management *************************************************/ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag); + +/* FIFO *************************************************************/ +void I2C_FIFO_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +uint32_t I2C_FIFO_GetTxDataNum(const CM_I2C_TypeDef *I2Cx); +uint32_t I2C_FIFO_GetRxDataStatus(const CM_I2C_TypeDef *I2Cx); +uint32_t I2C_FIFO_GetTxDataStatus(const CM_I2C_TypeDef *I2Cx); +void I2C_FIFO_NackResetFIFOCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_FIFO_TxFlush(CM_I2C_TypeDef *I2Cx); +void I2C_FIFO_RxFlush(CM_I2C_TypeDef *I2Cx); + +/* Data transfer *****************************************************/ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data); +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx); +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig); + +/* Time out function *************************************************/ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH); +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL); +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState); + +/* High level functions for reference ********************************/ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout); +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_I2C_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h new file mode 100644 index 0000000000..b244be50d2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_icg.h @@ -0,0 +1,428 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.h + * @brief This file contains all the Macro Definitions of the ICG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Modify macro define:ICG_SWDT_LPM_CNT_CONTINUE -> ICG_SWDT_LPM_CNT_CONT + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_ICG_H__ +#define __HC32_LL_ICG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_ICG + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Global_Macros ICG Global Macros + * @{ + */ + +/** + * @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State + * @{ + */ +#define ICG_SWDT_RST_START (0UL) /*!< SWDT auto start after reset */ +#define ICG_SWDT_RST_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Exception_Type ICG SWDT Exception Type + * @{ + */ +#define ICG_SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */ +#define ICG_SWDT_EXP_TYPE_RST (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Count_Period ICG SWDT Count Period + * @{ + */ +#define ICG_SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_SWDT_CNT_PERIOD4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */ +#define ICG_SWDT_CNT_PERIOD16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */ +#define ICG_SWDT_CNT_PERIOD65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division + * @{ + */ +#define ICG_SWDT_CLK_DIV1 (0UL) /*!< CLK */ +#define ICG_SWDT_CLK_DIV16 (0x04UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/16 */ +#define ICG_SWDT_CLK_DIV32 (0x05UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/32 */ +#define ICG_SWDT_CLK_DIV64 (0x06UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/64 */ +#define ICG_SWDT_CLK_DIV128 (0x07UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/128 */ +#define ICG_SWDT_CLK_DIV256 (0x08UL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/256 */ +#define ICG_SWDT_CLK_DIV2048 (0x0BUL << ICG_ICG0_SWDTCKS_POS) /*!< CLK/2048 */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range + * @{ + */ +#define ICG_SWDT_RANGE_0TO25PCT (0x01UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% */ +#define ICG_SWDT_RANGE_25TO50PCT (0x02UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% */ +#define ICG_SWDT_RANGE_0TO50PCT (0x03UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% */ +#define ICG_SWDT_RANGE_50TO75PCT (0x04UL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~75% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_SWDT_RANGE_25TO75PCT (0x06UL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~75% */ +#define ICG_SWDT_RANGE_0TO75PCT (0x07UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~75% */ +#define ICG_SWDT_RANGE_75TO100PCT (0x08UL << ICG_ICG0_SWDTWDPT_POS) /*!< 75%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_50TO100PCT (0x0CUL << ICG_ICG0_SWDTWDPT_POS) /*!< 50%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_SWDT_RANGE_25TO100PCT (0x0EUL << ICG_ICG0_SWDTWDPT_POS) /*!< 25%~100% */ +#define ICG_SWDT_RANGE_0TO100PCT (0x0FUL << ICG_ICG0_SWDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count + * @brief Counting control of SWDT in sleep/stop mode + * @{ + */ +#define ICG_SWDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep/stop mode */ +#define ICG_SWDT_LPM_CNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< Stop counting in sleep/stop mode */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Reset_State ICG WDT Reset State + * @{ + */ +#define ICG_WDT_RST_START (0UL) /*!< WDT auto start after reset */ +#define ICG_WDT_RST_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Exception_Type ICG WDT Exception Type + * @{ + */ +#define ICG_WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define ICG_WDT_EXP_TYPE_RST (ICG_ICG0_WDTITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Count_Period ICG WDT Count Period + * @{ + */ +#define REDEF_ICG_WDTPERI_POS ICG_ICG0_WDTPERI_POS + +#define ICG_WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define ICG_WDT_CNT_PERIOD4096 (0x01UL << REDEF_ICG_WDTPERI_POS) /*!< 4096 clock cycle */ +#define ICG_WDT_CNT_PERIOD16384 (0x02UL << REDEF_ICG_WDTPERI_POS) /*!< 16384 clock cycle */ +#define ICG_WDT_CNT_PERIOD65536 (0x03UL << REDEF_ICG_WDTPERI_POS) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division + * @{ + */ +#define REDEF_ICG_WDTCKS_POS ICG_ICG0_WDTCKS_POS + +#define ICG_WDT_CLK_DIV4 (0x02UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/4 */ +#define ICG_WDT_CLK_DIV64 (0x06UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/64 */ +#define ICG_WDT_CLK_DIV128 (0x07UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/128 */ +#define ICG_WDT_CLK_DIV256 (0x08UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/256 */ +#define ICG_WDT_CLK_DIV512 (0x09UL << REDEF_ICG_WDTCKS_POS) /*!< CLK/512 */ +#define ICG_WDT_CLK_DIV1024 (0x0AUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/1024 */ +#define ICG_WDT_CLK_DIV2048 (0x0BUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/2048 */ +#define ICG_WDT_CLK_DIV8192 (0x0DUL << REDEF_ICG_WDTCKS_POS) /*!< CLK/8192 */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range + * @{ + */ +#define REDEF_ICG_WDTWDPT_POS ICG_ICG0_WDTWDPT_POS + +#define ICG_WDT_RANGE_0TO25PCT (0x01UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% */ +#define ICG_WDT_RANGE_25TO50PCT (0x02UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% */ +#define ICG_WDT_RANGE_0TO50PCT (0x03UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% */ +#define ICG_WDT_RANGE_50TO75PCT (0x04UL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~75% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~75% */ +#define ICG_WDT_RANGE_25TO75PCT (0x06UL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~75% */ +#define ICG_WDT_RANGE_0TO75PCT (0x07UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~75% */ +#define ICG_WDT_RANGE_75TO100PCT (0x08UL << REDEF_ICG_WDTWDPT_POS) /*!< 75%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 75%~100% */ +#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~50% & 75%~100% */ +#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~50% & 75%~100% */ +#define ICG_WDT_RANGE_50TO100PCT (0x0CUL << REDEF_ICG_WDTWDPT_POS) /*!< 50%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~25% & 50%~100% */ +#define ICG_WDT_RANGE_25TO100PCT (0x0EUL << REDEF_ICG_WDTWDPT_POS) /*!< 25%~100% */ +#define ICG_WDT_RANGE_0TO100PCT (0x0FUL << REDEF_ICG_WDTWDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode + * @{ + */ +#define ICG_WDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep mode */ +#define ICG_WDT_LPM_CNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold + * @{ + */ +#define ICG_BOR_VOL_THRESHOLD_LVL0 (0UL) /*!< BOR voltage threshold 1.9V */ +#define ICG_BOR_VOL_THRESHOLD_LVL1 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */ +#define ICG_BOR_VOL_THRESHOLD_LVL2 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */ +#define ICG_BOR_VOL_THRESHOLD_LVL3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Reset_State ICG BOR Reset State + * @{ + */ +#define ICG_BOR_RST_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */ +#define ICG_BOR_RST_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select + * @{ + */ + +#define ICG_HRC_20M (0UL) /*!< HRC = 20MHZ */ +#define ICG_HRC_16M (ICG_ICG1_HRCFREQSEL) /*!< HRC = 16MHZ */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Reset_State ICG HRC Reset State + * @{ + */ +#define ICG_HRC_RST_OSCILLATION (0UL) /*!< HRC Oscillation after reset */ +#define ICG_HRC_RST_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State + * @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF + * @{ + */ +#define ICG_FLASH_PROTECT_RST_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */ +#define ICG_FLASH_PROTECT_RST_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Configuration ICG Register Configuration + * @{ + */ + +/** + * @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration + * @{ + */ +/* SWDT register config */ +#define ICG_RB_SWDT_AUTS (ICG_SWDT_RST_STOP) +#define ICG_RB_SWDT_ITS (ICG_SWDT_EXP_TYPE_RST) +#define ICG_RB_SWDT_PERI (ICG_SWDT_CNT_PERIOD65536) +#define ICG_RB_SWDT_CKS (ICG_SWDT_CLK_DIV2048) +#define ICG_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT) +#define ICG_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_CNT_STOP) + +/* SWDT register value */ +#define ICG_REG_SWDT_CONFIG (ICG_RB_SWDT_AUTS | ICG_RB_SWDT_ITS | ICG_RB_SWDT_PERI | \ + ICG_RB_SWDT_CKS | ICG_RB_SWDT_WDPT | ICG_RB_SWDT_SLTPOFF) +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration + * @{ + */ +/* WDT register config */ +#define ICG_RB_WDT_AUTS (ICG_WDT_RST_STOP) +#define ICG_RB_WDT_ITS (ICG_WDT_EXP_TYPE_RST) +#define ICG_RB_WDT_PERI (ICG_WDT_CNT_PERIOD65536) +#define ICG_RB_WDT_CKS (ICG_WDT_CLK_DIV8192) +#define ICG_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT) +#define ICG_RB_WDT_SLTPOFF (ICG_WDT_LPM_CNT_STOP) + +/* WDT register value */ +#define ICG_REG_WDT_CONFIG (ICG_RB_WDT_AUTS | ICG_RB_WDT_ITS | ICG_RB_WDT_PERI | \ + ICG_RB_WDT_CKS | ICG_RB_WDT_WDPT | ICG_RB_WDT_SLTPOFF) +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration + * @{ + */ +/* BOR register config */ +#define ICG_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_LVL3) +#define ICG_RB_BOR_DIS (ICG_BOR_RST_DISABLE) + +/* BOR register value */ +#define ICG_REG_BOR_CONFIG (ICG_RB_BOR_LEV | ICG_RB_BOR_DIS) +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration + * @{ + */ +/* HRC register config */ +#define ICG_RB_HRC_FREQSEL (ICG_HRC_16M) +#define ICG_RB_HRC_STOP (ICG_HRC_RST_STOP) + +/* HRC register value */ +#define ICG_REG_HRC_CONFIG (ICG_RB_HRC_FREQSEL | ICG_RB_HRC_STOP) +/** + * @} + */ + +/** + * @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration + * @{ + */ +/* FLASH Read Protect register value */ +#define ICG_REG_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RST_DISABLE) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Value ICG Register Value + * @{ + */ +/* ICG register value */ +#ifndef ICG_REG_CFG0_CONST +#define ICG_REG_CFG0_CONST (ICG_REG_WDT_CONFIG | ICG_REG_SWDT_CONFIG | 0xE000E000UL) +#endif +#ifndef ICG_REG_CFG1_CONST +#define ICG_REG_CFG1_CONST (ICG_REG_BOR_CONFIG | ICG_REG_HRC_CONFIG | 0xFFF8FEFEUL) +#endif +#ifndef ICG_REG_CFG2_CONST +#define ICG_REG_CFG2_CONST (0xFFFFFFFFUL) +#endif +#ifndef ICG_REG_CFG3_CONST +#define ICG_REG_CFG3_CONST (ICG_REG_FLASH_PROTECT_CONFIG | 0xFFFF0000UL) +#endif +#ifndef ICG_REG_CFG4_CONST +#define ICG_REG_CFG4_CONST (0xFFFFFFFFUL) +#endif +/* ICG reserved value */ +#define ICG_REG_RESV_CONST (0xFFFFFFFFUL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h new file mode 100644 index 0000000000..7b97a0f412 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_interrupts.h @@ -0,0 +1,472 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Add declaration of API INTC_GetIntSrcState() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_INTERRUPTS_H__ +#define __HC32_LL_INTERRUPTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_INTERRUPTS + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Types INTC Global Types + * @{ + */ + +/** + * @brief Interrupt registration structure definition + */ +typedef struct { + en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */ + IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be INT000_IRQn~INT127_IRQn @ref IRQn_Type */ + func_ptr_t pfnCallback; /*!< Callback function for corresponding peripheral IRQ */ +} stc_irq_signin_config_t; + +/** + * @brief NMI initialize configuration structure definition + */ +typedef struct { + uint32_t u32Src; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */ +} stc_nmi_init_t; + +/** + * @brief EXTINT initialize configuration structure definition + */ +typedef struct { + uint32_t u32Filter; /*!< ExtInt filter (A) function setting, @ref EXTINT_FilterClock_Sel for details */ + uint32_t u32FilterClock; /*!< ExtInt filter (A) clock division, @ref EXTINT_FilterClock_Div for details */ + uint32_t u32Edge; /*!< ExtInt trigger edge, @ref EXTINT_Trigger_Sel for details */ + uint32_t u32FilterB; /*!< NMI, ExtInt filter B function setting, @ref NMI_EXTINT_FilterBClock_Sel for details */ + uint32_t u32FilterBClock; /*!< NMI, ExtInt filter B time, @ref NMI_EXTINT_FilterBTim_Sel for details */ +} stc_extint_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Macros INTC Global Macros + * @{ + */ +/** + * @defgroup INTC_Priority_Sel Interrupt Priority Level 00 ~ 15 + * @{ + */ +#define DDL_IRQ_PRIO_00 (0U) +#define DDL_IRQ_PRIO_01 (1U) +#define DDL_IRQ_PRIO_02 (2U) +#define DDL_IRQ_PRIO_03 (3U) +#define DDL_IRQ_PRIO_04 (4U) +#define DDL_IRQ_PRIO_05 (5U) +#define DDL_IRQ_PRIO_06 (6U) +#define DDL_IRQ_PRIO_07 (7U) +#define DDL_IRQ_PRIO_08 (8U) +#define DDL_IRQ_PRIO_09 (9U) +#define DDL_IRQ_PRIO_10 (10U) +#define DDL_IRQ_PRIO_11 (11U) +#define DDL_IRQ_PRIO_12 (12U) +#define DDL_IRQ_PRIO_13 (13U) +#define DDL_IRQ_PRIO_14 (14U) +#define DDL_IRQ_PRIO_15 (15U) + +#define DDL_IRQ_PRIO_DEFAULT (DDL_IRQ_PRIO_15) + +/** + * @} + */ + +/** + * @defgroup NMI_TriggerSrc_Sel NMI Trigger Source Selection + * @{ + */ +#define NMI_SRC_SWDT (INTC_NMIFR_SWDTF) +#define NMI_SRC_LVD1 (INTC_NMIFR_PVD1F) +#define NMI_SRC_LVD2 (INTC_NMIFR_PVD2F) +#define NMI_SRC_XTAL (INTC_NMIFR_XTALSTPF) +#define NMI_SRC_SRAM_PARITY (INTC_NMIFR_RPARERRF) +#define NMI_SRC_SRAM_ECC (INTC_NMIFR_RECCERRF) +#define NMI_SRC_BUS_ERR (INTC_NMIFR_BUSERRF) +#define NMI_SRC_WDT (INTC_NMIFR_WDTF) +#define NMI_SRC_ALL (NMI_SRC_SWDT | NMI_SRC_LVD1 | NMI_SRC_LVD2 | \ + NMI_SRC_XTAL | NMI_SRC_BUS_ERR | NMI_SRC_SRAM_PARITY | \ + NMI_SRC_WDT | NMI_SRC_SRAM_ECC) + +/** + * @} + */ + +/** + * @defgroup EXTINT_Channel_Sel External Interrupt Channel Selection + * @{ + */ +#define EXTINT_CH00 (1UL << 0U) +#define EXTINT_CH01 (1UL << 1U) +#define EXTINT_CH02 (1UL << 2U) +#define EXTINT_CH03 (1UL << 3U) +#define EXTINT_CH04 (1UL << 4U) +#define EXTINT_CH05 (1UL << 5U) +#define EXTINT_CH06 (1UL << 6U) +#define EXTINT_CH07 (1UL << 7U) +#define EXTINT_CH08 (1UL << 8U) +#define EXTINT_CH09 (1UL << 9U) +#define EXTINT_CH10 (1UL <<10U) +#define EXTINT_CH11 (1UL <<11U) +#define EXTINT_CH12 (1UL <<12U) +#define EXTINT_CH13 (1UL <<13U) +#define EXTINT_CH14 (1UL <<14U) +#define EXTINT_CH15 (1UL <<15U) +#define EXTINT_CH_ALL (EXTINT_CH00 | EXTINT_CH01 | EXTINT_CH02 | EXTINT_CH03 | \ + EXTINT_CH04 | EXTINT_CH05 | EXTINT_CH06 | EXTINT_CH07 | \ + EXTINT_CH08 | EXTINT_CH09 | EXTINT_CH10 | EXTINT_CH11 | \ + EXTINT_CH12 | EXTINT_CH13 | EXTINT_CH14 | EXTINT_CH15) +/** + * @} + */ + +/** + * @defgroup INT_Channel_Sel Interrupt Channel Selection + * @{ + */ +#define INTC_INT0 INTC_IER_IEN0 +#define INTC_INT1 INTC_IER_IEN1 +#define INTC_INT2 INTC_IER_IEN2 +#define INTC_INT3 INTC_IER_IEN3 +#define INTC_INT4 INTC_IER_IEN4 +#define INTC_INT5 INTC_IER_IEN5 +#define INTC_INT6 INTC_IER_IEN6 +#define INTC_INT7 INTC_IER_IEN7 +#define INTC_INT8 INTC_IER_IEN8 +#define INTC_INT9 INTC_IER_IEN9 +#define INTC_INT10 INTC_IER_IEN10 +#define INTC_INT11 INTC_IER_IEN11 +#define INTC_INT12 INTC_IER_IEN12 +#define INTC_INT13 INTC_IER_IEN13 +#define INTC_INT14 INTC_IER_IEN14 +#define INTC_INT15 INTC_IER_IEN15 +#define INTC_INT16 INTC_IER_IEN16 +#define INTC_INT17 INTC_IER_IEN17 +#define INTC_INT18 INTC_IER_IEN18 +#define INTC_INT19 INTC_IER_IEN19 +#define INTC_INT20 INTC_IER_IEN20 +#define INTC_INT21 INTC_IER_IEN21 +#define INTC_INT22 INTC_IER_IEN22 +#define INTC_INT23 INTC_IER_IEN23 +#define INTC_INT24 INTC_IER_IEN24 +#define INTC_INT25 INTC_IER_IEN25 +#define INTC_INT26 INTC_IER_IEN26 +#define INTC_INT27 INTC_IER_IEN27 +#define INTC_INT28 INTC_IER_IEN28 +#define INTC_INT29 INTC_IER_IEN29 +#define INTC_INT30 INTC_IER_IEN30 +#define INTC_INT31 INTC_IER_IEN31 +#define INTC_INT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup INTC_Event_Channel_Sel Event Channel Selection + * @{ + */ +#define INTC_EVT0 INTC_EVTER_EVTE0 +#define INTC_EVT1 INTC_EVTER_EVTE1 +#define INTC_EVT2 INTC_EVTER_EVTE2 +#define INTC_EVT3 INTC_EVTER_EVTE3 +#define INTC_EVT4 INTC_EVTER_EVTE4 +#define INTC_EVT5 INTC_EVTER_EVTE5 +#define INTC_EVT6 INTC_EVTER_EVTE6 +#define INTC_EVT7 INTC_EVTER_EVTE7 +#define INTC_EVT8 INTC_EVTER_EVTE8 +#define INTC_EVT9 INTC_EVTER_EVTE9 +#define INTC_EVT10 INTC_EVTER_EVTE10 +#define INTC_EVT11 INTC_EVTER_EVTE11 +#define INTC_EVT12 INTC_EVTER_EVTE12 +#define INTC_EVT13 INTC_EVTER_EVTE13 +#define INTC_EVT14 INTC_EVTER_EVTE14 +#define INTC_EVT15 INTC_EVTER_EVTE15 +#define INTC_EVT16 INTC_EVTER_EVTE16 +#define INTC_EVT17 INTC_EVTER_EVTE17 +#define INTC_EVT18 INTC_EVTER_EVTE18 +#define INTC_EVT19 INTC_EVTER_EVTE19 +#define INTC_EVT20 INTC_EVTER_EVTE20 +#define INTC_EVT21 INTC_EVTER_EVTE21 +#define INTC_EVT22 INTC_EVTER_EVTE22 +#define INTC_EVT23 INTC_EVTER_EVTE23 +#define INTC_EVT24 INTC_EVTER_EVTE24 +#define INTC_EVT25 INTC_EVTER_EVTE25 +#define INTC_EVT26 INTC_EVTER_EVTE26 +#define INTC_EVT27 INTC_EVTER_EVTE27 +#define INTC_EVT28 INTC_EVTER_EVTE28 +#define INTC_EVT29 INTC_EVTER_EVTE29 +#define INTC_EVT30 INTC_EVTER_EVTE30 +#define INTC_EVT31 INTC_EVTER_EVTE31 +#define INTC_EVT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup SWINT_Channel_Sel Software Interrupt Channel Selection + * @{ + */ +#define SWINT_CH00 INTC_SWIER_SWIE0 +#define SWINT_CH01 INTC_SWIER_SWIE1 +#define SWINT_CH02 INTC_SWIER_SWIE2 +#define SWINT_CH03 INTC_SWIER_SWIE3 +#define SWINT_CH04 INTC_SWIER_SWIE4 +#define SWINT_CH05 INTC_SWIER_SWIE5 +#define SWINT_CH06 INTC_SWIER_SWIE6 +#define SWINT_CH07 INTC_SWIER_SWIE7 +#define SWINT_CH08 INTC_SWIER_SWIE8 +#define SWINT_CH09 INTC_SWIER_SWIE9 +#define SWINT_CH10 INTC_SWIER_SWIE10 +#define SWINT_CH11 INTC_SWIER_SWIE11 +#define SWINT_CH12 INTC_SWIER_SWIE12 +#define SWINT_CH13 INTC_SWIER_SWIE13 +#define SWINT_CH14 INTC_SWIER_SWIE14 +#define SWINT_CH15 INTC_SWIER_SWIE15 +#define SWINT_CH16 INTC_SWIER_SWIE16 +#define SWINT_CH17 INTC_SWIER_SWIE17 +#define SWINT_CH18 INTC_SWIER_SWIE18 +#define SWINT_CH19 INTC_SWIER_SWIE19 +#define SWINT_CH20 INTC_SWIER_SWIE20 +#define SWINT_CH21 INTC_SWIER_SWIE21 +#define SWINT_CH22 INTC_SWIER_SWIE22 +#define SWINT_CH23 INTC_SWIER_SWIE23 +#define SWINT_CH24 INTC_SWIER_SWIE24 +#define SWINT_CH25 INTC_SWIER_SWIE25 +#define SWINT_CH26 INTC_SWIER_SWIE26 +#define SWINT_CH27 INTC_SWIER_SWIE27 +#define SWINT_CH28 INTC_SWIER_SWIE28 +#define SWINT_CH29 INTC_SWIER_SWIE29 +#define SWINT_CH30 INTC_SWIER_SWIE30 +#define SWINT_CH31 INTC_SWIER_SWIE31 +#define SWINT_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Sel External Interrupt Filter A Function Selection + * @{ + */ +#define EXTINT_FILTER_OFF (0UL) +#define EXTINT_FILTER_ON INTC_EIRQCR_EFEN + +/** + * @} + */ + +/** + * @defgroup NMI_EXTINT_FilterBClock_Sel External Interrupt Filter B Function Selection + * @{ + */ +#define NMI_EXTINT_FILTER_B_OFF (0UL) +#define NMI_EXTINT_FILTER_B_ON INTC_EIRQCR_NOCEN +/** + * @} + */ + +/** + * @defgroup EXTINT_FilterClock_Div External Interrupt Filter A Sampling Clock Division Selection + * @{ + */ +#define EXTINT_FCLK_DIV1 (0UL) +#define EXTINT_FCLK_DIV8 (INTC_EIRQCR_EISMPCLK_0) +#define EXTINT_FCLK_DIV32 (INTC_EIRQCR_EISMPCLK_1) +#define EXTINT_FCLK_DIV64 (INTC_EIRQCR_EISMPCLK) + +/** + * @} + */ + +/** + * @defgroup NMI_EXTINT_FilterBTim_Sel External Interrupt Filter B Time Selection + * @{ + */ +#define NMI_EXTINT_FCLK_B_500NS (0UL) +#define NMI_EXTINT_FCLK_B_1US (INTC_EIRQCR_NOCSEL_0) +#define NMI_EXTINT_FCLK_B_2US (INTC_EIRQCR_NOCSEL_1) +#define NMI_EXTINT_FCLK_B_4US (INTC_EIRQCR_NOCSEL) +/** + * @} + */ + +/** + * @defgroup EXTINT_Trigger_Sel External Interrupt Trigger Edge Selection + * @{ + */ +#define EXTINT_TRIG_FALLING (0UL) +#define EXTINT_TRIG_RISING INTC_EIRQCR_EIRQTRG_0 +#define EXTINT_TRIG_BOTH INTC_EIRQCR_EIRQTRG_1 +#define EXTINT_TRIG_LOW INTC_EIRQCR_EIRQTRG + +/** + * @} + */ + +/** + * @defgroup INTC_Stop_Wakeup_Source_Sel Stop Mode Wakeup Source Selection + * @{ + */ +#define INTC_STOP_WKUP_EXTINT_CH0 INTC_WKEN_EIRQWKEN_0 +#define INTC_STOP_WKUP_EXTINT_CH1 INTC_WKEN_EIRQWKEN_1 +#define INTC_STOP_WKUP_EXTINT_CH2 INTC_WKEN_EIRQWKEN_2 +#define INTC_STOP_WKUP_EXTINT_CH3 INTC_WKEN_EIRQWKEN_3 +#define INTC_STOP_WKUP_EXTINT_CH4 INTC_WKEN_EIRQWKEN_4 +#define INTC_STOP_WKUP_EXTINT_CH5 INTC_WKEN_EIRQWKEN_5 +#define INTC_STOP_WKUP_EXTINT_CH6 INTC_WKEN_EIRQWKEN_6 +#define INTC_STOP_WKUP_EXTINT_CH7 INTC_WKEN_EIRQWKEN_7 +#define INTC_STOP_WKUP_EXTINT_CH8 INTC_WKEN_EIRQWKEN_8 +#define INTC_STOP_WKUP_EXTINT_CH9 INTC_WKEN_EIRQWKEN_9 +#define INTC_STOP_WKUP_EXTINT_CH10 INTC_WKEN_EIRQWKEN_10 +#define INTC_STOP_WKUP_EXTINT_CH11 INTC_WKEN_EIRQWKEN_11 +#define INTC_STOP_WKUP_EXTINT_CH12 INTC_WKEN_EIRQWKEN_12 +#define INTC_STOP_WKUP_EXTINT_CH13 INTC_WKEN_EIRQWKEN_13 +#define INTC_STOP_WKUP_EXTINT_CH14 INTC_WKEN_EIRQWKEN_14 +#define INTC_STOP_WKUP_EXTINT_CH15 INTC_WKEN_EIRQWKEN_15 +#define INTC_STOP_WKUP_SWDT INTC_WKEN_SWDTWKEN +#define INTC_STOP_WKUP_CMP1 INTC_WKEN_CMP1WKEN +#define INTC_STOP_WKUP_WKTM INTC_WKEN_WKTMWKEN +#define INTC_STOP_WKUP_RTC_ALM INTC_WKEN_RTCALMWKEN +#define INTC_STOP_WKUP_RTC_PRD INTC_WKEN_RTCPRDWKEN +#define INTC_STOP_WKUP_TMR0_CMP INTC_WKEN_TMR0CMPWKEN +#define INTC_STOP_WKUP_USART1_RX INTC_WKEN_RXWKEN +#define INTC_STOP_WKUP_CMP2 INTC_WKEN_CMP2WKEN +#define INTC_STOP_WKUP_CMP3 INTC_WKEN_CMP3WKEN +#define INTC_STOP_WKUP_CMP4 INTC_WKEN_CMP4WKEN +#define INTC_WUPEN_ALL (INTC_WKEN_EIRQWKEN | INTC_WKEN_SWDTWKEN | \ + INTC_WKEN_CMP1WKEN | INTC_WKEN_WKTMWKEN | \ + INTC_WKEN_RTCALMWKEN | INTC_WKEN_RTCPRDWKEN | \ + INTC_WKEN_TMR0CMPWKEN | INTC_WKEN_RXWKEN | \ + INTC_WKEN_CMP2WKEN | INTC_WKEN_CMP3WKEN | \ + INTC_WKEN_CMP4WKEN) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup INTC_Global_Functions + * @{ + */ + +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig); +int32_t INTC_IrqSignOut(IRQn_Type enIRQn); +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState); +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState); +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState); +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority); +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState); + +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit); +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit); +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src); +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState); +void NMI_ClearNmiStatus(uint32_t u32Src); + +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit); +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit); +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh); +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh); +void INTC_IntSrcCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState); +en_functional_state_t INTC_GetIntSrcState(en_int_src_t enIntSrc); + +void IRQ000_Handler(void); +void IRQ001_Handler(void); +void IRQ002_Handler(void); +void IRQ003_Handler(void); +void IRQ004_Handler(void); +void IRQ005_Handler(void); +void IRQ006_Handler(void); +void IRQ007_Handler(void); + +void IRQ008_Handler(void); +void IRQ009_Handler(void); +void IRQ010_Handler(void); +void IRQ011_Handler(void); +void IRQ012_Handler(void); +void IRQ013_Handler(void); +void IRQ014_Handler(void); +void IRQ015_Handler(void); + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_INTERRUPTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h new file mode 100644 index 0000000000..cc2026a129 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_keyscan.h @@ -0,0 +1,240 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.h + * @brief This file contains all the functions prototypes of the KEYSCAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_KEYSCAN_H__ +#define __HC32_LL_KEYSCAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_KEYSCAN + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Types KEYSCAN Global Types + * @{ + */ + +/** + * @brief KEYSCAN configuration + */ +typedef struct { + uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles. + This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */ + + uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */ + + uint32_t u32KeyClock; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Clock_Sel */ + + uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyout_Sel */ + + uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyin_Sel */ +} stc_keyscan_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection + * @{ + */ +#define KEYSCAN_HIZ_CYCLE_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */ +#define KEYSCAN_HIZ_CYCLE_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection + * @{ + */ +#define KEYSCAN_LOW_CYCLE_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */ +#define KEYSCAN_LOW_CYCLE_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */ +#define KEYSCAN_LOW_CYCLE_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */ +#define KEYSCAN_LOW_CYCLE_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */ +#define KEYSCAN_LOW_CYCLE_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */ +#define KEYSCAN_LOW_CYCLE_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */ +#define KEYSCAN_LOW_CYCLE_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */ +#define KEYSCAN_LOW_CYCLE_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */ +#define KEYSCAN_LOW_CYCLE_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */ +#define KEYSCAN_LOW_CYCLE_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */ +#define KEYSCAN_LOW_CYCLE_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */ +#define KEYSCAN_LOW_CYCLE_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */ +#define KEYSCAN_LOW_CYCLE_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */ +#define KEYSCAN_LOW_CYCLE_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */ +#define KEYSCAN_LOW_CYCLE_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */ +#define KEYSCAN_LOW_CYCLE_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */ +#define KEYSCAN_LOW_CYCLE_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */ +#define KEYSCAN_LOW_CYCLE_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */ +#define KEYSCAN_LOW_CYCLE_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */ +#define KEYSCAN_LOW_CYCLE_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */ +#define KEYSCAN_LOW_CYCLE_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */ +#define KEYSCAN_LOW_CYCLE_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */ +#define KEYSCAN_LOW_CYCLE_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection + * @{ + */ +#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */ +#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */ +#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection + * @{ + */ +#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */ +#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */ +#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */ +#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */ +#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */ +#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */ +#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection + * @{ + */ +#define KEYSCAN_IN_0 (1UL << 0U) /*!< KEYIN(EIRQ) 0 is selected */ +#define KEYSCAN_IN_1 (1UL << 1U) /*!< KEYIN(EIRQ) 1 is selected */ +#define KEYSCAN_IN_2 (1UL << 2U) /*!< KEYIN(EIRQ) 2 is selected */ +#define KEYSCAN_IN_3 (1UL << 3U) /*!< KEYIN(EIRQ) 3 is selected */ +#define KEYSCAN_IN_4 (1UL << 4U) /*!< KEYIN(EIRQ) 4 is selected */ +#define KEYSCAN_IN_5 (1UL << 5U) /*!< KEYIN(EIRQ) 5 is selected */ +#define KEYSCAN_IN_6 (1UL << 6U) /*!< KEYIN(EIRQ) 6 is selected */ +#define KEYSCAN_IN_7 (1UL << 7U) /*!< KEYIN(EIRQ) 7 is selected */ +#define KEYSCAN_IN_8 (1UL << 8U) /*!< KEYIN(EIRQ) 8 is selected */ +#define KEYSCAN_IN_9 (1UL << 9U) /*!< KEYIN(EIRQ) 9 is selected */ +#define KEYSCAN_IN_10 (1UL << 10U) /*!< KEYIN(EIRQ) 10 is selected */ +#define KEYSCAN_IN_11 (1UL << 11U) /*!< KEYIN(EIRQ) 11 is selected */ +#define KEYSCAN_IN_12 (1UL << 12U) /*!< KEYIN(EIRQ) 12 is selected */ +#define KEYSCAN_IN_13 (1UL << 13U) /*!< KEYIN(EIRQ) 13 is selected */ +#define KEYSCAN_IN_14 (1UL << 14U) /*!< KEYIN(EIRQ) 14 is selected */ +#define KEYSCAN_IN_15 (1UL << 15U) /*!< KEYIN(EIRQ) 15 is selected */ +#define KEYSCAN_IN_ALL (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup KEYSCAN_Global_Functions + * @{ + */ +/** + * @brief Get KEYOUT index. + * @param None + * @retval uint32_t: KEYOUT index 0~7. + */ +__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void) +{ + return READ_REG32_BIT(CM_KEYSCAN->SSR, KEYSCAN_SSR_INDEX); +} + +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit); +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit); +void KEYSCAN_Cmd(en_functional_state_t enNewState); +int32_t KEYSCAN_DeInit(void); + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_KEYSCAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mcan.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mcan.h new file mode 100644 index 0000000000..43e29f8478 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mcan.h @@ -0,0 +1,1126 @@ +/** + ******************************************************************************* + * @file hc32_ll_mcan.h + * @brief This file contains all the functions prototypes of the MCAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Removed definitions related to BEC and BEU. + Optimized driver: + 1. Integrated stc_mcan_classic_config_t and stc_mcan_fd_config_t into stc_mcan_bit_time_config_t + 2. Integrated u32FdIso into u32FrameFormat. + 3. Removed API MCAN_SetFdIsoOperation(), added API MCAN_SetFrameFormat(). + 4. Optimized the handling of the parameter stc_mcan_filter_t.u32FilterIndex + 5. Add 5 APIs for better get protocol status(register PSR): + MCAN_GetTdcValue(), MCAN_GetDataLastErrorCode(), MCAN_GetLastErrorCode(), + MCAN_GetComState(), MCAN_GetProtocolFlagStatus() + 6. Changed u8Activity of stc_mcan_protocol_status_t to u8ComState. + 7. Changed MCAN_Comm_State to MCAN_Com_State and optimized the macros definitions. + 8. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex. Optimized MCAN_HPM_Storage macros definitions. + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_MCAN_H__ +#define __HC32_LL_MCAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_MCAN + * @{ + */ +#if (LL_MCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup MCAN_Global_Types MCAN Global Types + * @{ + */ +/** + * @brief MCAN bit time configuration structure definition + */ +typedef struct { + /* Nominal bit time configuration, used for classic CAN frame or arbitration phase of CAN FD frame */ + uint32_t u32NominalPrescaler; /*!< Specifies the nominal bit rate prescaler. + This parameter must be a number between 1 and 512 */ + uint32_t u32NominalTimeSeg1; /*!< Specifies the nominal time segment before sample point(the sum of Sync_Seg, + Prop_Seg and Phase_Seg1). + This parameter must be a number between 3 and 257 */ + uint32_t u32NominalTimeSeg2; /*!< Specifies the nominal time segment after sample point(Phase_Seg2). + This parameter must be a number between 2 and 128 */ + uint32_t u32NominalSyncJumpWidth; /*!< Specifies the nominal (re)synchronization jump width(SJW). + This parameter must be a number between 1 and 128 */ + + /* FD bit time configuration, used for data phase of CAN FD frame */ + uint32_t u32DataPrescaler; /*!< Specifies the data bit rate prescaler. + This parameter must be a number between 1 and 32 + NOTE: when u32TDC is MCAN_FD_TDC_ENABLE, the range is limited to 1, 2 */ + uint32_t u32DataTimeSeg1; /*!< Specifies the data time segment before sample point(the sum of Sync_Seg, + Prop_Seg and Phase_Seg1). + This parameter must be a number between 2 and 33 */ + uint32_t u32DataTimeSeg2; /*!< Specifies the data time segment after sample point(Phase_Seg2). + This parameter must be a number between 1 and 16 */ + uint32_t u32DataSyncJumpWidth; /*!< Specifies the data (re)synchronization jump width(SJW). + This parameter must be a number between 1 and 16 */ + + /* FD TDC(Transmitter Delay Compensation) configuration */ + uint32_t u32TDC; /*!< Enable or disable TDC(Transmitter Delay Compensation). + This parameter can be a value of @ref MCAN_TDC_Enable */ + uint32_t u32SspOffset; /*!< Specifies the transmitter delay compensation SSP offset. + This parameter must be a number between 0 and 127(MCAN clock) */ + uint32_t u32TdcFilter; /*!< Specifies the transmitter delay compensation filter window length. + This parameter defines the minimum value for the SSP position. + The feature is enabled when this parameter is configured to a value + greater than u32SspOffset. + This parameter must be a number between 0 and 127(MCAN clock) */ +} stc_mcan_bit_time_config_t; + +/** + * @brief MCAN message RAM address blocks + */ +typedef struct { + uint32_t u32StdFilterStartAddr; /*!< Output parameter. Indicates the standard filter list start address. */ + uint32_t u32ExtFilterStartAddr; /*!< Output parameter. Indicates the extended filter list start address. */ + uint32_t u32RxFifo0StartAddr; /*!< Output parameter. Indicates the Rx FIFO 0 start address. */ + uint32_t u32RxFifo1StartAddr; /*!< Output parameter. Indicates the Rx FIFO 1 start address. */ + uint32_t u32RxBufferStartAddr; /*!< Output parameter. Indicates the Rx buffer start address. */ + uint32_t u32TxEventStartAddr; /*!< Output parameter. Indicates the Tx event FIFO start address. */ + uint32_t u32TxBufferStartAddr; /*!< Output parameter. Indicates the Tx buffers start address. */ + uint32_t u32TxFifoQueueStartAddr; /*!< Output parameter. Indicates the Tx FIFO/Queue start address. */ + uint32_t u32EndAddr; /*!< Output parameter. Indicates the end address of the allocated RAM. */ + uint32_t *pu32StdFilterAddrList; /*!< Pointer to an address that used to store each standard ID filter element address. + Set it to NULL if you do not need the element address information. */ + uint32_t *pu32ExtFilterAddrList; /*!< Pointer to an address that used to store each extended ID filter element address. + Set it to NULL if you do not need the element address information. */ + uint32_t *pu32RxFifo0AddrList; /*!< Pointer to an address that used to store each Rx FIFO0 element address. + Set it to NULL if you do not need the element address information. */ + uint32_t *pu32RxFifo1AddrList; /*!< Pointer to an address that used to store each Rx FIFO1 element address. + Set it to NULL if you do not need the element address information. */ + uint32_t *pu32RxBufferAddrList; /*!< Pointer to an address that used to store each Rx buffer element address. + Set it to NULL if you do not need the element address information. */ + uint32_t *pu32TxEventAddrList; /*!< Pointer to an address that used to store each Tx event FIFO element address. + Set it to NULL if you do not need the element address information. */ + uint32_t *pu32TxBufferAddrList; /*!< Pointer to an address that used to store each dedicated Tx buffer element address. + Set it to NULL if you do not need the element address information. */ + uint32_t *pu32TxFifoQueueAddrList; /*!< Pointer to an address that used to store each Tx FIFO/queue element address. + Set it to NULL if you do not need the element address information. */ +} stc_mcan_msg_ram_addr_t; + +/** + * @brief MCAN message RAM configuration structure definition + */ +typedef struct { + uint32_t u32AddrOffset; /*!< Specifies the message RAM start address. + NOTE: The message RAM is 2K bytes and shared by MCAN1 and MCAN2. */ + uint32_t u32StdFilterNum; /*!< Specifies the number of standard message ID filters. + This parameter is used to allocate RAM to standard ID filters. + This parameter must be a number between 0 and 128 */ + uint32_t u32ExtFilterNum; /*!< Specifies the number of extended message ID filters. + This parameter is used to allocate RAM to extended ID filters. + This parameter must be a number between 0 and 64 */ + uint32_t u32RxFifo0Num; /*!< Specifies the number of Rx FIFO0 elements. + u32RxFifo0Num and u32RxFifo0DataSize are used to allocate RAM to Rx FIFO0. + This parameter must be a number between 0 and 64 */ + uint32_t u32RxFifo0DataSize; /*!< Specifies the data field size in an Rx FIFO 0 element. + This parameter can be a value of @ref MCAN_Data_Field_Size */ + uint32_t u32RxFifo1Num; /*!< Specifies the number of Rx FIFO 1 elements. + u32RxFifo1Num and u32RxFifo1DataSize are used to allocate RAM to Rx FIFO1. + This parameter must be a number between 0 and 64 */ + uint32_t u32RxFifo1DataSize; /*!< Specifies the data field size in an Rx FIFO 1 element. + This parameter can be a value of @ref MCAN_Data_Field_Size */ + uint32_t u32RxBufferNum; /*!< Specifies the number of dedicated Rx buffer elements. + u32RxBufferNum and u32RxBufferDataSize are used to allocate RAM to Rx buffer. + This parameter must be a number between 0 and 64 */ + uint32_t u32RxBufferDataSize; /*!< Specifies the data field size in an Rx buffer element. + This parameter can be a value of @ref MCAN_Data_Field_Size */ + uint32_t u32TxEventNum; /*!< Specifies the number of Tx event FIFO elements. + This parameter is used to allocate RAM to Tx event FIFO. + This parameter must be a number between 0 and 32 */ + uint32_t u32TxBufferNum; /*!< Specifies the number of dedicated Tx buffers. + u32TxBufferNum and u32TxFifoQueueNum and u32TxDataSize are used to allocate RAM for Tx messages. + The sum of u32TxBufferNum and u32TxFifoQueueNum must be a number between 0 and 32 */ + uint32_t u32TxFifoQueueNum; /*!< Specifies the number of Tx buffers used for Tx FIFO/queue. + The sum of u32TxFifoQueueNum and u32TxBufferNum must be a number between 0 and 32 */ + uint32_t u32TxFifoQueueMode; /*!< Specifies Tx FIFO/Queue operation mode. + This parameter can be a value of @ref MCAN_Tx_FIFO_Queue_Mode */ + uint32_t u32TxDataSize; /*!< Specifies the data field size in a Tx element. + This parameter can be a value of @ref MCAN_Data_Field_Size */ + uint32_t u32AllocatedSize; /*!< Output parameter. Indicates the message RAM size that allocated to the configured MCAN. + It is also the address offset of the MCAN to be configured. */ +} stc_mcan_msg_ram_config_t; + +/** + * @brief MCAN filter structure definition + */ +typedef struct { + uint32_t u32IdType; /*!< Specifies the ID type. + This parameter can be a value of @ref MCAN_ID_Type */ + uint32_t u32FilterIndex; /*!< Specifies the filter which will be initialized. + This parameter must be a number between: + - 0 and stc_mcan_msg_ram_config_t.u32StdFilterNum-1(@ref stc_mcan_msg_ram_config_t), if u32IdType is MCAN_STD_ID. + - 0 and stc_mcan_msg_ram_config_t.u32ExtFilterNum-1(@ref stc_mcan_msg_ram_config_t), if u32IdType is MCAN_EXT_ID. + NOTE: When configuring filter elements sequence by calling API MCAN_Init(), this parameter can be ignored. The local function + will handle this parameter. + When configuring filter element one by one by calling API MCAN_FilterConfig(), it is required to specify + the index of the target filter through this parameter. */ + uint32_t u32FilterType; /*!< Specifies the filter type. + This parameter can be a value of @ref MCAN_Filter_Type + The value MCAN_FILTER_RANGE_NO_EIDM is permitted only when u32IdType is MCAN_EXT_ID. + This parameter is ignored if u32FilterConfig is set to MCAN_FILTER_TO_RX_BUF */ + uint32_t u32FilterConfig; /*!< Specifies the filter configuration. + This parameter can be a value of @ref MCAN_Filter_Config */ + uint32_t u32FilterId1; /*!< Specifies the filter ID1. + This parameter must be a number between: + - 0 and 0x7FF, if u32IdType is MCAN_STD_ID + - 0 and 0x1FFFFFFF, if u32IdType is MCAN_EXT_ID */ + uint32_t u32FilterId2; /*!< Specifies the filter ID2. + This parameter is ignored if u32FilterConfig is set to MCAN_FILTER_TO_RX_BUF. + This parameter must be a number between: + - 0 and 0x7FF, if u32IdType is MCAN_STD_ID + - 0 and 0x1FFFFFFF, if u32IdType is MCAN_EXT_ID */ + uint32_t u32RxBufferIndex; /*!< Specifies the dedicated Rx buffer in which the matching message will be stored. + This parameter must be a number between 0 and 63, and less than or equal to + u32RxBufferNum of @ref stc_mcan_msg_ram_config_t + This parameter is ignored if u32FilterConfig is different from MCAN_FILTER_TO_RX_BUF */ +} stc_mcan_filter_t; + +/** + * @brief MCAN filter initialization structure definition + */ +typedef struct { + stc_mcan_filter_t *pstcStdFilterList; /*!< Pointer to the standard ID filter elements list. + These filter elements can be configured only when: + pstcStdFilterList != NULL and + u32StdFilterConfigNum > 0 and + u32StdFilterConfigNum <= u32StdFilterNum of @ref stc_mcan_msg_ram_config_t */ + stc_mcan_filter_t *pstcExtFilterList; /*!< Pointer to the extended ID filter elements list. + These filter elements can be configured only when: + pstcExtFilterList != NULL and + u32ExtFilterConfigNum > 0 and + u32ExtFilterConfigNum <= u32ExtFilterNum of @ref stc_mcan_msg_ram_config_t */ + uint32_t u32StdFilterConfigNum; /*!< Number of the standard ID filter elements which to be configured. + This parameter must less than or equal to u32StdFilterNum + of @ref stc_mcan_msg_ram_config_t */ + uint32_t u32ExtFilterConfigNum; /*!< Number of the extended ID filter elements which to be configured. + This parameter must less than or equal to u32ExtFilterNum + of @ref stc_mcan_msg_ram_config_t */ +} stc_mcan_filter_config_t; + +/** + * @brief MCAN initialization structure + */ +typedef struct { + uint32_t u32Mode; /*!< Specifies MCAN operating mode. + This parameter can be a value of @ref MCAN_Operating_Mode */ + uint32_t u32FrameFormat; /*!< Specifies the frame format supported by MCAN hardware. + This parameter can be a value of @ref MCAN_Frame_Format */ + uint32_t u32AutoRetx; /*!< Enable or disable automatic retransmission. + This parameter can be a value of @ref MCAN_Auto_Retx_Enable */ + uint32_t u32TxPause; /*!< Enable or disable transmit pause. + If transmit pause is enabled, MCAN pauses for two CAN bit times before starting + the next transmission after itself has successfully transmitted a frame. + This parameter can be a value of @ref MCAN_Tx_Pause_Enable */ + uint32_t u32ProtocolException; /*!< Enable or disable protocol exception handling. + When this function is disabled, MCAN will transmit an error frame + when it detects a protocol exception condition. + This parameter can be a value of @ref MCAN_Protocol_Exception_Enable */ + stc_mcan_bit_time_config_t stcBitTime; /*!< MCAN bit time configuration structure */ + stc_mcan_msg_ram_config_t stcMsgRam; /*!< Message RAM configuration structure. */ + stc_mcan_filter_config_t stcFilter; /*!< Acceptance filter configuration structure. */ +} stc_mcan_init_t; + +/** + * @brief MCAN Tx message structure definition + */ +typedef struct { + uint32_t ID; /*!< Specifies the ID. + This parameter must be a number between: + - 0 and 0x7FF, if IDE is 0 + - 0 and 0x1FFFFFFF, if IDE is 1 */ + uint32_t IDE; /*!< IDentifier Extension bit. Specifies the ID type for the transmitted message. + This parameter can be a value of: + - 0: 11-bit standard ID + - 1: 29-bit extended ID */ + uint32_t RTR; /*!< Remote Transmission Request. Specifies the frame type of the transmitted message. + This parameter can be a value of: + - 0: Data frame to be transmitted + - 1: Remote frame to be transmitted */ + uint32_t DLC; /*!< Data Length Code. Specifies the length of the data field of the transmitted frame. + This parameter can be a value of @ref MCAN_Data_Length_Code */ + uint32_t ESI; /*!< Error State Indicator. Specifies the error state indicator. + This parameter can be a value of: + - 0: Transmitting node is error active + - 1: Transmitting node is error passive */ + uint32_t BRS; /*!< Bit Rate Switch. Specifies whether the Tx frame is transmitted with or without bit rate switching. + This parameter can be a value of: + - 0: Frame transmitted without bit rate switching + - 1: Frame transmitted with bit rate switching */ + uint32_t FDF; /*!< FD Format indicator. Specifies whether the Tx frame is transmitted in classic or FD format. + This parameter can be a value of: + - 0: Classical CAN frame format + - 1: CAN FD frame format (new DLC-coding and CRC) */ + uint32_t u32StoreTxEvent; /*!< Specifies the event FIFO control. + This parameter can be a value of: + - 0: DO NOT store tx event + - 1: Store tx event into TX event FIFO */ + uint32_t u32MsgMarker; /*!< Specifies the message marker to be copied into Tx event FIFO + element for identification of Tx message status. + This parameter must be a number between: + - 0 and 0xFF if 8-bit message marker used(CCCR.WMM == 0) + - 0 and 0xFFFF if 16-bit-width message marker used(CCCR.WMM == 1) */ + uint32_t u32TxBuffer; /*!< Specifies the dedicated Tx buffer that used to transmit the message. + This parameter can be a value of @ref MCAN_Tx_Location + This parameter valid when Tx via dedicated Tx buffer. */ + uint8_t au8Data[64U]; /*!< Data payload of the message that to be transmitted. */ + uint32_t u32LastTxFifoQueueRequest; /*!< Ouput parameter of Tx buffer index of last Tx FIFO/queue request. + This parameter valid when Tx via FIFO or queue. */ +} stc_mcan_tx_msg_t; + +/** + * @brief MCAN Rx message structure definition + */ +typedef struct { + uint32_t ID; /*!< Specifies the ID. + This parameter must be a number between: + - 0 and 0x7FF, if IDE is 0 + - 0 and 0x1FFFFFFF, if IDE is 1 */ + uint32_t IDE; /*!< IDentifier Extension bit. Specifies the ID type for the received message. + This parameter can be a value of: + - 0: 11-bit standard ID + - 1: 29-bit extended ID */ + uint32_t RTR; /*!< Remote Transmission Request. Specifies the frame type of the received message. + This parameter can be a value of: + - 0: Data frame received + - 1: Remote frame received */ + uint32_t DLC; /*!< Data Length Code. Specifies the length of data filed of the received frame. + This parameter can be a value of @ref MCAN_Data_Length_Code */ + uint32_t ESI; /*!< Error State Indicator. Specifies the error state indicator. + This parameter can be a value of: + - 0: Transmitting node is error active + - 1: Transmitting node is error passive */ + uint32_t BRS; /*!< Bit Rate Switch. Specifies whether the Tx frame is received with or without bit rate switching. + This parameter can be a value of: + - 0: Frame received without bit rate switching + - 1: Frame received with bit rate switching */ + uint32_t FDF; /*!< FD Format indicator. Specifies whether the Tx frame is received in classic or FD format. + This parameter can be a value of: + - 0: Classical CAN frame format + - 1: CAN FD frame format (new DLC-coding and CRC) */ + uint32_t u32RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + This parameter must be a number between 0 and 0xFFFF */ + uint32_t u32FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. + This parameter must be a number between: + - 0 and 127, if IDE is 0 + - 0 and 63, if IDE is 1 */ + uint32_t u32NmfFlag; /*!< Specifies whether the accepted frame did not match any Rx filter. + Acceptance of non-matching frames may be configured via @ref MCAN_GlobalFilterConfig() + This parameter can be: + - 0: Received frame matching filter index u32FilterIndex + - 1: Received frame did not match any Rx filter element */ + uint8_t au8Data[64U]; /*!< Data payload of the received message */ + uint32_t u32DataSize; /*!< Size of Rx data payload */ +} stc_mcan_rx_msg_t; + +/** + * @brief MCAN Tx event structure definition + */ +typedef struct { + uint32_t ID; /*!< Specifies the ID. + This parameter must be a number between: + - 0 and 0x7FF, if IDE is 0 + - 0 and 0x1FFFFFFF, if IDE is 1 */ + uint32_t IDE; /*!< IDentifier Extension bit. Specifies the ID type for the transmitted message. + This parameter can be a value of: + - 0: 11-bit standard ID + - 1: 29-bit extended ID */ + uint32_t RTR; /*!< Remote Transmission Request. Specifies the frame type of the transmitted message. + This parameter can be a value of: + - 0: Data frame transmitted + - 1: Remote frame transmitted */ + uint32_t DLC; /*!< Data Length Code. Specifies the length of the transmitted frame. + This parameter can be a value of @ref MCAN_Data_Length_Code */ + uint32_t ESI; /*!< Error State Indicator. Specifies the error state indicator. + This parameter can be a value of: + - 0: Transmitting node is error active + - 1: Transmitting node is error passive */ + uint32_t BRS; /*!< Bit Rate Switch. Specifies whether the Tx frame is transmitted with or without bit rate switching. + This parameter can be a value of: + - 0: Frame transmitted without bit rate switching + - 1: Frame transmitted with bit rate switching */ + uint32_t FDF; /*!< FD Format indicator. Specifies whether the Tx frame is transmitted in classic or FD format. + This parameter can be a value of: + - 0: Classical CAN frame format + - 1: CAN FD frame format (new DLC-coding and CRC) */ + uint32_t u32TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame transmission. + This parameter is valid only when 8-bit message marker used. + This parameter must be a number between 0 and 0xFFFF. */ + uint32_t u32MsgMarker; /*!< Specifies the message marker copied into Tx Event FIFO element for identification of Tx message status. + This parameter must be a number between: + - 0 and 0xFF if 8-bit message marker used(CCCR.WMM == 0) + - 0 and 0xFFFF if 16-bit-width message marker used(CCCR.WMM == 1) */ + uint32_t u32EventType; /*!< Specifies the event type. + This parameter can be a value of @ref MCAN_Evt_Type */ +} stc_mcan_tx_event_t; + +/** + * @brief MCAN high priority message status structure definition + */ +typedef struct { + uint8_t u8FilterListType; /*!< Specifies the filter list of the matching filter element. + This parameter can be: + - 0: Standard filter list + - 1: Extended filter list */ + uint8_t u8FilterIndex; /*!< Specifies the index of matching filter element. + This parameter can be a number between: + - 0 and 127, if u8FilterListType is 0 (Standard) + - 0 and 63, if u8FilterListType is 1 (Extended) */ + uint8_t u8MsgStorage; /*!< Specifies the high priority message storage. + This parameter can be a value of @ref MCAN_HPM_Storage */ + uint8_t u8MsgIndex; /*!< Specifies the index of Rx FIFO element to which the message was stored. + This parameter is valid only when u8MsgStorage is: + MCAN_HPM_STORED_IN_RX_FIFO0 or MCAN_HPM_STORED_IN_RX_FIFO1 */ +} stc_mcan_hpm_status_t; + +/** + * @brief MCAN protocol status structure definition + */ +typedef struct { + uint8_t u8LastErrorCode; /*!< Specifies the type of the last error that occurred on the CAN bus. + This parameter can be a value of @ref MCAN_Protocol_Error_Code */ + uint8_t u8DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format + frame with its BRS flag set. + This parameter can be a value of @ref MCAN_Protocol_Error_Code */ + uint8_t u8ComState; /*!< Specifies the CAN module communication state. + This parameter can be a value of @ref MCAN_Com_State */ + uint8_t u8ErrorPassiveFlag; /*!< Specifies the CAN module error status. + This parameter can be: + - 0: The CAN is in the Error_Active state + - 1: The CAN is in the Error_Passive state */ + uint8_t u8WarningFlag; /*!< Specifies the CAN module warning status. + This parameter can be: + - 0: Both error counters are below the Error_Warning limit of 96 + - 1: At least one of error counter has reached the Error_Warning limit of 96 */ + uint8_t u8BusOffFlag; /*!< Specifies the CAN module Bus_Off status. + This parameter can be: + - 0: The CAN is not in Bus_Off state + - 1: The CAN is in Bus_Off state */ + uint8_t u8RxESIFlag; /*!< Specifies ESI flag of last received CAN FD message. + This parameter can be: + - 0: Last received CAN FD message did not have its ESI flag set + - 1: Last received CAN FD message had its ESI flag set */ + uint8_t u8RxBRSFlag; /*!< Specifies BRS flag of last received CAN FD message. + This parameter can be: + - 0: Last received CAN FD message did not have its BRS flag set + - 1: Last received CAN FD message had its BRS flag set */ + uint8_t u8RxFDFFlag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status. + This parameter can be: + - 0: Since this bit was reset by the CPU, no CAN FD message has been received + - 1: Message in CAN FD format with FDF flag set has been received */ + uint8_t u8ProtocolExceptionFlag; /*!< Specifies the CAN module protocol exception status. + This parameter can be: + - 0: No protocol exception event occurred since last read access + - 1: Protocol exception event occurred */ + uint8_t u8TdcValue; /*!< Specifies the Transmitter Delay Compensation Value. + This parameter can be a number between 0 and 127 */ + +} stc_mcan_protocol_status_t; + +/** + * @brief MCAN error counters structure definition + */ +typedef struct { + uint8_t u8TxErrorCount; /*!< Specifies the Transmit Error Counter Value. + This parameter can be a number between 0 and 255 */ + uint8_t u8RxErrorCount; /*!< Specifies the Receive Error Counter Value. + This parameter can be a number between 0 and 127 */ + uint8_t u8RxErrorPassive; /*!< Specifies the Receive Error Passive status. + This parameter can be: + - 0: The Receive Error Counter (u8RxErrorCount) is below the error passive level of 128 + - 1: The Receive Error Counter (u8RxErrorCount) has reached the error passive level of 128 */ + uint8_t u8ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. + This parameter can be a number between 0 and 255. + This counter is incremented each time when a CAN protocol error causes the u8TxErrorCount + or the u8RxErrorCount to be incremented. The counter stops at 255; the next increment of + u8TxErrorCount or u8RxErrorCount sets interrupt flag MCAN_FLAG_ERR_LOG_OVF */ +} stc_mcan_error_counter_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MCAN_Global_Macros MCAN Global Macros + * @{ + */ +/** + * @defgroup MCAN_Operating_Mode MCAN Operating Mode + * @{ + */ +#define MCAN_MD_NORMAL (0U) /*!< Normal mode */ +#define MCAN_MD_RESTRICTED_OP (1U) /*!< Restricted operation mode */ +#define MCAN_MD_BUS_MON (2U) /*!< Bus monitoring mode */ +#define MCAN_MD_INTERN_LOOPBACK (3U) /*!< Internal loopBack mode */ +#define MCAN_MD_EXTERN_LOOPBACK (4U) /*!< External loopBack mode */ +/** + * @} + */ + +/** + * @defgroup MCAN_Msg_RAM_Info MCAN Message RAM Information + * @{ + */ +#define MCAN_MSG_RAM_BASE (0x4002B000UL) /*!< MCAN message RAM start address */ +#define MCAN_MSG_RAM_SIZE (1024UL * 2UL) /*!< MCAN message RAM size */ +#define MCAN_MSG_RAM_END (MCAN_MSG_RAM_BASE + \ + MCAN_MSG_RAM_SIZE) /*!< MCAN message RAM end address */ +/** + * @} + */ + +/** + * @defgroup MCAN_ID_Type MCAN ID Type + * @{ + */ +#define MCAN_STD_ID (0U) /*!< Standard ID */ +#define MCAN_EXT_ID (1U) /*!< Extended ID */ +/** + * @} + */ + +/** + * @defgroup MCAN_ID_Mask MCAN ID Mask + * @{ + */ +#define MCAN_STD_ID_MASK (0x7FFUL) /*!< Standard ID mask */ +#define MCAN_EXT_ID_MASK (0x1FFFFFFFUL) /*!< Extended ID mask */ +/** + * @} + */ + +/** + * @defgroup MCAN_Frame_Format MCAN Frame Format + * @{ + */ +#define MCAN_FRAME_CLASSIC (0x0U) /*!< Classic CAN mode */ +#define MCAN_FRAME_ISO_FD_NO_BRS (MCAN_CCCR_FDOE) /*!< ISO CAN FD mode without bit rate switching */ +#define MCAN_FRAME_ISO_FD_BRS (MCAN_CCCR_FDOE | \ + MCAN_CCCR_BRSE) /*!< ISO CAN FD mode with bit rate switching */ +#define MCAN_FRAME_NON_ISO_FD_NO_BRS (MCAN_CCCR_NISO | \ + MCAN_CCCR_FDOE) /*!< Non-ISO CAN FD mode without bit rate switching */ +#define MCAN_FRAME_NON_ISO_FD_BRS (MCAN_CCCR_NISO | \ + MCAN_CCCR_FDOE | \ + MCAN_CCCR_BRSE) /*!< Non-ISO CAN FD mode with bit rate switching */ +/** + * @} + */ + +/** + * @defgroup MCAN_Auto_Retx_Enable MCAN Automatic Retransmission Enable + * @{ + */ +#define MCAN_AUTO_RETX_DISABLE (MCAN_CCCR_DAR) /*!< Disable automatic retransmission */ +#define MCAN_AUTO_RETX_ENABLE (0x0U) /*!< Automatic retransmission of messages not transmitted successfully */ +/** + * @} + */ + +/** + * @defgroup MCAN_Tx_Pause_Enable MCAN Tx Pause Enable + * @{ + */ +#define MCAN_TX_PAUSE_DISABLE (0x0U) /*!< Disable transmit pause */ +#define MCAN_TX_PAUSE_ENABLE (MCAN_CCCR_TXP) /*!< Enable transmit pause */ +/** + * @} + */ + +/** + * @defgroup MCAN_Msg_Marker_Cfg MCAN Message Marker Configuration + * @{ + */ +#define MCAN_MSG_MARKER_8BIT (0U) /*!< 8-bit message marker used */ +#define MCAN_MSG_MARKER_16BIT (MCAN_CCCR_WMM) /*!< 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO */ +/** + * @} + */ + +/** + * @defgroup MCAN_Protocol_Exception_Enable MCAN Protocol Exception Enable + * @{ + */ +#define MCAN_PROTOCOL_EXP_DISABLE (MCAN_CCCR_PXHD) /*!< Disable protocol exception handling */ +#define MCAN_PROTOCOL_EXP_ENABLE (0x0U) /*!< Enable protocol exception handling */ +/** + * @} + */ + +/** + * @defgroup MCAN_TDC_Enable MCAN Transmitter Delay Compensation Enable + * @{ + */ +#define MCAN_FD_TDC_DISABLE (0x0U) /*!< Disable transmitter delay compensation. */ +#define MCAN_FD_TDC_ENABLE (MCAN_DBTP_TDC) /*!< Enable transmitter delay compensation. */ +/** + * @} + */ + +/** + * @defgroup MCAN_Tx_Pin_Ctrl MCAN Tx Pin Control + * @{ + */ +#define MCAN_TX_PIN_NORMAL (0U) /*!< Tx pin controlled by the CAN Core, updated at the end of the CAN bit time */ +#define MCAN_TX_PIN_MONITOR (MCAN_TEST_TX_0) /*!< Sample Point can be monitored at Tx pin */ +#define MCAN_TX_PIN_DOMINANT (MCAN_TEST_TX_1) /*!< Dominant ('0') level at Tx pin */ +#define MCAN_TX_PIN_RECESSIVE (MCAN_TEST_TX) /*!< Recessive ('1') level at Tx pin */ +/** + * @} + */ + +/** + * @defgroup MCAN_Data_Length_Code MCAN Data Length Code + * @{ + */ +#define MCAN_DLC0 (0x0U) /*!< Classic-CAN and FD-CAN: data field size is 0 bytes. */ +#define MCAN_DLC1 (0x1U) /*!< Classic-CAN and FD-CAN: data field size is 1 bytes. */ +#define MCAN_DLC2 (0x2U) /*!< Classic-CAN and FD-CAN: data field size is 2 bytes. */ +#define MCAN_DLC3 (0x3U) /*!< Classic-CAN and FD-CAN: data field size is 3 bytes. */ +#define MCAN_DLC4 (0x4U) /*!< Classic-CAN and FD-CAN: data field size is 4 bytes. */ +#define MCAN_DLC5 (0x5U) /*!< Classic-CAN and FD-CAN: data field size is 5 bytes. */ +#define MCAN_DLC6 (0x6U) /*!< Classic-CAN and FD-CAN: data field size is 6 bytes. */ +#define MCAN_DLC7 (0x7U) /*!< Classic-CAN and FD-CAN: data field size is 7 bytes. */ +#define MCAN_DLC8 (0x8U) /*!< Classic-CAN and FD-CAN: data field size is 8 bytes. */ +#define MCAN_DLC12 (0x9U) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 12 bytes. */ +#define MCAN_DLC16 (0xAU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 16 bytes. */ +#define MCAN_DLC20 (0xBU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 20 bytes. */ +#define MCAN_DLC24 (0xCU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 24 bytes. */ +#define MCAN_DLC32 (0xDU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 32 bytes. */ +#define MCAN_DLC48 (0xEU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 48 bytes. */ +#define MCAN_DLC64 (0xFU) /*!< Classic-CAN: data field size is 8 bytes; FD-CAN: data field size is 64 bytes. */ +/** + * @} + */ + +/** + * @defgroup MCAN_Data_Field_Size MCAN Data Field Size + * @{ + */ +#define MCAN_DATA_SIZE_8BYTE (0x0U) /*!< 8 bytes data field */ +#define MCAN_DATA_SIZE_12BYTE (0x1U) /*!< 12 bytes data field */ +#define MCAN_DATA_SIZE_16BYTE (0x2U) /*!< 16 bytes data field */ +#define MCAN_DATA_SIZE_20BYTE (0x3U) /*!< 20 bytes data field */ +#define MCAN_DATA_SIZE_24BYTE (0x4U) /*!< 24 bytes data field */ +#define MCAN_DATA_SIZE_32BYTE (0x5U) /*!< 32 bytes data field */ +#define MCAN_DATA_SIZE_48BYTE (0x6U) /*!< 48 bytes data field */ +#define MCAN_DATA_SIZE_64BYTE (0x7U) /*!< 64 bytes data field */ +/** + * @} + */ + +/** + * @defgroup MCAN_Tx_FIFO_Queue_Mode MCAN Tx FIFO/Queue Mode + * @{ + */ +#define MCAN_TX_FIFO_MD (0x0U) /*!< Tx FIFO operation mode */ +#define MCAN_TX_QUEUE_MD (MCAN_TXBC_TFQM) /*!< Tx Queue operation mode */ +/** + * @} + */ + +/** + * @defgroup MCAN_Filter_Type MCAN Filter Type + * @{ + */ +#define MCAN_FILTER_RANGE (0x0U) /*!< Range filter from filter ID1 to filter ID2 */ +#define MCAN_FILTER_DUAL (0x1U) /*!< Dual ID filter for filter ID1 or filter ID2 */ +#define MCAN_FILTER_MASK (0x2U) /*!< Classic filter: filter ID1 = filter, filter ID2 = mask */ +#define MCAN_FILTER_RANGE_NO_EIDM (0x3U) /*!< Range filter from filter ID1 to filter ID2, EIDM mask not applied */ +/** + * @} + */ + +/** + * @defgroup MCAN_Filter_Config MCAN Filter Configuration + * @{ + */ +#define MCAN_FILTER_DISABLE (0x0U) /*!< Disable filter element */ +#define MCAN_FILTER_TO_RX_FIFO0 (0x1U) /*!< Store in Rx FIFO 0 if filter matches */ +#define MCAN_FILTER_TO_RX_FIFO1 (0x2U) /*!< Store in Rx FIFO 1 if filter matches */ +#define MCAN_FILTER_REJECT (0x3U) /*!< Reject ID if filter matches */ +#define MCAN_FILTER_HP_NO_STORAGE (0x4U) /*!< Set high priority if filter matches, no storage */ +#define MCAN_FILTER_HP_TO_RX_FIFO0 (0x5U) /*!< Set high priority and store in FIFO 0 if filter matches */ +#define MCAN_FILTER_HP_TO_RX_FIFO1 (0x6U) /*!< Set high priority and store in FIFO 1 if filter matches */ +#define MCAN_FILTER_TO_RX_BUF (0x7U) /*!< Store into Rx buffer, configuration of @ref MCAN_Filter_Type ignored */ +/** + * @} + */ + +/** + * @defgroup MCAN_Tx_Location MCAN Tx Location + * @{ + */ +#define MCAN_TX_BUF0 (0x1UL << 0U) /*!< Add message to Tx buffer 0 */ +#define MCAN_TX_BUF1 (0x1UL << 1U) /*!< Add message to Tx buffer 1 */ +#define MCAN_TX_BUF2 (0x1UL << 2U) /*!< Add message to Tx buffer 2 */ +#define MCAN_TX_BUF3 (0x1UL << 3U) /*!< Add message to Tx buffer 3 */ +#define MCAN_TX_BUF4 (0x1UL << 4U) /*!< Add message to Tx buffer 4 */ +#define MCAN_TX_BUF5 (0x1UL << 5U) /*!< Add message to Tx buffer 5 */ +#define MCAN_TX_BUF6 (0x1UL << 6U) /*!< Add message to Tx buffer 6 */ +#define MCAN_TX_BUF7 (0x1UL << 7U) /*!< Add message to Tx buffer 7 */ +#define MCAN_TX_BUF8 (0x1UL << 8U) /*!< Add message to Tx buffer 8 */ +#define MCAN_TX_BUF9 (0x1UL << 9U) /*!< Add message to Tx buffer 9 */ +#define MCAN_TX_BUF10 (0x1UL << 10U) /*!< Add message to Tx buffer 10 */ +#define MCAN_TX_BUF11 (0x1UL << 11U) /*!< Add message to Tx buffer 11 */ +#define MCAN_TX_BUF12 (0x1UL << 12U) /*!< Add message to Tx buffer 12 */ +#define MCAN_TX_BUF13 (0x1UL << 13U) /*!< Add message to Tx buffer 13 */ +#define MCAN_TX_BUF14 (0x1UL << 14U) /*!< Add message to Tx buffer 14 */ +#define MCAN_TX_BUF15 (0x1UL << 15U) /*!< Add message to Tx buffer 15 */ +#define MCAN_TX_BUF16 (0x1UL << 16U) /*!< Add message to Tx buffer 16 */ +#define MCAN_TX_BUF17 (0x1UL << 17U) /*!< Add message to Tx buffer 17 */ +#define MCAN_TX_BUF18 (0x1UL << 18U) /*!< Add message to Tx buffer 18 */ +#define MCAN_TX_BUF19 (0x1UL << 19U) /*!< Add message to Tx buffer 19 */ +#define MCAN_TX_BUF20 (0x1UL << 20U) /*!< Add message to Tx buffer 20 */ +#define MCAN_TX_BUF21 (0x1UL << 21U) /*!< Add message to Tx buffer 21 */ +#define MCAN_TX_BUF22 (0x1UL << 22U) /*!< Add message to Tx buffer 22 */ +#define MCAN_TX_BUF23 (0x1UL << 23U) /*!< Add message to Tx buffer 23 */ +#define MCAN_TX_BUF24 (0x1UL << 24U) /*!< Add message to Tx buffer 24 */ +#define MCAN_TX_BUF25 (0x1UL << 25U) /*!< Add message to Tx buffer 25 */ +#define MCAN_TX_BUF26 (0x1UL << 26U) /*!< Add message to Tx buffer 26 */ +#define MCAN_TX_BUF27 (0x1UL << 27U) /*!< Add message to Tx buffer 27 */ +#define MCAN_TX_BUF28 (0x1UL << 28U) /*!< Add message to Tx buffer 28 */ +#define MCAN_TX_BUF29 (0x1UL << 29U) /*!< Add message to Tx buffer 29 */ +#define MCAN_TX_BUF30 (0x1UL << 30U) /*!< Add message to Tx buffer 30 */ +#define MCAN_TX_BUF31 (0x1UL << 31U) /*!< Add message to Tx buffer 31 */ +#define MCAN_TX_BUF_ALL (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup MCAN_Rx_Location MCAN Rx Location + * @{ + */ +#define MCAN_RX_FIFO0 (0x40U) /*!< Get received message from Rx FIFO 0 */ +#define MCAN_RX_FIFO1 (0x41U) /*!< Get received message from Rx FIFO 1 */ +#define MCAN_RX_BUF0 (0x00U) /*!< Get received message from Rx buffer 0 */ +#define MCAN_RX_BUF1 (0x01U) /*!< Get received message from Rx buffer 1 */ +#define MCAN_RX_BUF2 (0x02U) /*!< Get received message from Rx buffer 2 */ +#define MCAN_RX_BUF3 (0x03U) /*!< Get received message from Rx buffer 3 */ +#define MCAN_RX_BUF4 (0x04U) /*!< Get received message from Rx buffer 4 */ +#define MCAN_RX_BUF5 (0x05U) /*!< Get received message from Rx buffer 5 */ +#define MCAN_RX_BUF6 (0x06U) /*!< Get received message from Rx buffer 6 */ +#define MCAN_RX_BUF7 (0x07U) /*!< Get received message from Rx buffer 7 */ +#define MCAN_RX_BUF8 (0x08U) /*!< Get received message from Rx buffer 8 */ +#define MCAN_RX_BUF9 (0x09U) /*!< Get received message from Rx buffer 9 */ +#define MCAN_RX_BUF10 (0x0AU) /*!< Get received message from Rx buffer 10 */ +#define MCAN_RX_BUF11 (0x0BU) /*!< Get received message from Rx buffer 11 */ +#define MCAN_RX_BUF12 (0x0CU) /*!< Get received message from Rx buffer 12 */ +#define MCAN_RX_BUF13 (0x0DU) /*!< Get received message from Rx buffer 13 */ +#define MCAN_RX_BUF14 (0x0EU) /*!< Get received message from Rx buffer 14 */ +#define MCAN_RX_BUF15 (0x0FU) /*!< Get received message from Rx buffer 15 */ +#define MCAN_RX_BUF16 (0x10U) /*!< Get received message from Rx buffer 16 */ +#define MCAN_RX_BUF17 (0x11U) /*!< Get received message from Rx buffer 17 */ +#define MCAN_RX_BUF18 (0x12U) /*!< Get received message from Rx buffer 18 */ +#define MCAN_RX_BUF19 (0x13U) /*!< Get received message from Rx buffer 19 */ +#define MCAN_RX_BUF20 (0x14U) /*!< Get received message from Rx buffer 20 */ +#define MCAN_RX_BUF21 (0x15U) /*!< Get received message from Rx buffer 21 */ +#define MCAN_RX_BUF22 (0x16U) /*!< Get received message from Rx buffer 22 */ +#define MCAN_RX_BUF23 (0x17U) /*!< Get received message from Rx buffer 23 */ +#define MCAN_RX_BUF24 (0x18U) /*!< Get received message from Rx buffer 24 */ +#define MCAN_RX_BUF25 (0x19U) /*!< Get received message from Rx buffer 25 */ +#define MCAN_RX_BUF26 (0x1AU) /*!< Get received message from Rx buffer 26 */ +#define MCAN_RX_BUF27 (0x1BU) /*!< Get received message from Rx buffer 27 */ +#define MCAN_RX_BUF28 (0x1CU) /*!< Get received message from Rx buffer 28 */ +#define MCAN_RX_BUF29 (0x1DU) /*!< Get received message from Rx buffer 29 */ +#define MCAN_RX_BUF30 (0x1EU) /*!< Get received message from Rx buffer 30 */ +#define MCAN_RX_BUF31 (0x1FU) /*!< Get received message from Rx buffer 31 */ +#define MCAN_RX_BUF32 (0x20U) /*!< Get received message from Rx buffer 32 */ +#define MCAN_RX_BUF33 (0x21U) /*!< Get received message from Rx buffer 33 */ +#define MCAN_RX_BUF34 (0x22U) /*!< Get received message from Rx buffer 34 */ +#define MCAN_RX_BUF35 (0x23U) /*!< Get received message from Rx buffer 35 */ +#define MCAN_RX_BUF36 (0x24U) /*!< Get received message from Rx buffer 36 */ +#define MCAN_RX_BUF37 (0x25U) /*!< Get received message from Rx buffer 37 */ +#define MCAN_RX_BUF38 (0x26U) /*!< Get received message from Rx buffer 38 */ +#define MCAN_RX_BUF39 (0x27U) /*!< Get received message from Rx buffer 39 */ +#define MCAN_RX_BUF40 (0x28U) /*!< Get received message from Rx buffer 40 */ +#define MCAN_RX_BUF41 (0x29U) /*!< Get received message from Rx buffer 41 */ +#define MCAN_RX_BUF42 (0x2AU) /*!< Get received message from Rx buffer 42 */ +#define MCAN_RX_BUF43 (0x2BU) /*!< Get received message from Rx buffer 43 */ +#define MCAN_RX_BUF44 (0x2CU) /*!< Get received message from Rx buffer 44 */ +#define MCAN_RX_BUF45 (0x2DU) /*!< Get received message from Rx buffer 45 */ +#define MCAN_RX_BUF46 (0x2EU) /*!< Get received message from Rx buffer 46 */ +#define MCAN_RX_BUF47 (0x2FU) /*!< Get received message from Rx buffer 47 */ +#define MCAN_RX_BUF48 (0x30U) /*!< Get received message from Rx buffer 48 */ +#define MCAN_RX_BUF49 (0x31U) /*!< Get received message from Rx buffer 49 */ +#define MCAN_RX_BUF50 (0x32U) /*!< Get received message from Rx buffer 50 */ +#define MCAN_RX_BUF51 (0x33U) /*!< Get received message from Rx buffer 51 */ +#define MCAN_RX_BUF52 (0x34U) /*!< Get received message from Rx buffer 52 */ +#define MCAN_RX_BUF53 (0x35U) /*!< Get received message from Rx buffer 53 */ +#define MCAN_RX_BUF54 (0x36U) /*!< Get received message from Rx buffer 54 */ +#define MCAN_RX_BUF55 (0x37U) /*!< Get received message from Rx buffer 55 */ +#define MCAN_RX_BUF56 (0x38U) /*!< Get received message from Rx buffer 56 */ +#define MCAN_RX_BUF57 (0x39U) /*!< Get received message from Rx buffer 57 */ +#define MCAN_RX_BUF58 (0x3AU) /*!< Get received message from Rx buffer 58 */ +#define MCAN_RX_BUF59 (0x3BU) /*!< Get received message from Rx buffer 59 */ +#define MCAN_RX_BUF60 (0x3CU) /*!< Get received message from Rx buffer 60 */ +#define MCAN_RX_BUF61 (0x3DU) /*!< Get received message from Rx buffer 61 */ +#define MCAN_RX_BUF62 (0x3EU) /*!< Get received message from Rx buffer 62 */ +#define MCAN_RX_BUF63 (0x3FU) /*!< Get received message from Rx buffer 63 */ +#define MCAN_RX_BUF_MAX MCAN_RX_BUF63 +/** + * @} + */ + +/** + * @defgroup MCAN_HPM_Storage MCAN High Priority Message Storage + * @{ + */ +#define MCAN_HPM_NO_STORAGE (0x0U) /*!< No FIFO selected */ +#define MCAN_HPM_LOST (0x1U) /*!< FIFO message lost */ +#define MCAN_HPM_STORED_IN_RX_FIFO0 (0x2U) /*!< Message stored in FIFO 0 */ +#define MCAN_HPM_STORED_IN_RX_FIFO1 (0x3U) /*!< Message stored in FIFO 1 */ +/** + * @} + */ + +/** + * @defgroup MCAN_Protocol_Error_Code MCAN Protocol Error Code + * @{ + */ +#define MCAN_PROTOCOL_NONE_ERR (0x0U) /*!< No error occurred */ +#define MCAN_PROTOCOL_STUFF_ERR (0x1U) /*!< Stuff error */ +#define MCAN_PROTOCOL_FORM_ERR (0x2U) /*!< Form error */ +#define MCAN_PROTOCOL_ACK_ERR (0x3U) /*!< Acknowledge error */ +#define MCAN_PROTOCOL_BIT1_ERR (0x4U) /*!< Bit 1 (recessive) error */ +#define MCAN_PROTOCOL_BIT0_ERR (0x5U) /*!< Bit 0 (dominant) error */ +#define MCAN_PROTOCOL_CRC_ERR (0x6U) /*!< CRC check sum error */ +#define MCAN_PROTOCOL_ERR_NO_CHANGE (0x7U) /*!< No change since last read */ +/** + * @} + */ + +/** + * @defgroup MCAN_Com_State MCAN Communication State + * @{ + */ +#define MCAN_COM_STATE_SYNC (0x0U) /*!< Node is synchronizing on CAN communication */ +#define MCAN_COM_STATE_IDLE (0x1U) /*!< Node is neither receiver nor transmitter */ +#define MCAN_COM_STATE_RX (0x2U) /*!< Node is operating as receiver */ +#define MCAN_COM_STATE_TX (0x3U) /*!< Node is operating as transmitter */ +/** + * @} + */ + +/** + * @defgroup MCAN_Protocol_Flag MCAN Protocol Status Flag + * @{ + */ +#define MCAN_PROTOCOL_FLAG_PROTOCOL_EXCEPTION (MCAN_PSR_PXE) /*!< Protocol exception event occurred */ +#define MCAN_PROTOCOL_FLAG_RX_FDF (MCAN_PSR_RFDF) /*!< Message in CAN FD format with FDF flag set has been received */ +#define MCAN_PROTOCOL_FLAG_RX_BRS (MCAN_PSR_RBRS) /*!< Last received CAN FD message had its BRS flag set */ +#define MCAN_PROTOCOL_FLAG_RX_ESI (MCAN_PSR_RESI) /*!< Last received CAN FD message had its ESI flag set */ +#define MCAN_PROTOCOL_FLAG_BUS_OFF (MCAN_PSR_BO) /*!< The MCAN is in Bus_Off state */ +#define MCAN_PROTOCOL_FLAG_ERR_WARNING (MCAN_PSR_EW) /*!< At least one of error counter has reached the Error_Warning limit of 96 */ +#define MCAN_PROTOCOL_FLAG_ERR_PASSIVE (MCAN_PSR_EP) /*!< The MCAN is in the Error_Passive state */ +#define MCAN_PROTOCOL_FLAG_ALL (MCAN_PROTOCOL_FLAG_PROTOCOL_EXCEPTION | MCAN_PROTOCOL_FLAG_RX_FDF | \ + MCAN_PROTOCOL_FLAG_RX_BRS | MCAN_PROTOCOL_FLAG_RX_ESI | \ + MCAN_PROTOCOL_FLAG_BUS_OFF | MCAN_PROTOCOL_FLAG_ERR_WARNING | \ + MCAN_PROTOCOL_FLAG_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup MCAN_Watermark_Fifo MCAN Watermark FIFO + * @{ + */ +#define MCAN_WATERMARK_RX_FIFO0 (0x0U) /*!< Rx FIFO0 */ +#define MCAN_WATERMARK_RX_FIFO1 (0x1U) /*!< Rx FIFO1 */ +#define MCAN_WATERMARK_TX_EVT_FIFO (0x2U) /*!< Tx event FIFO */ +/** + * @} + */ + +/** + * @defgroup MCAN_Rx_Fifo_Operation_Mode MCAN FIFO Operation Mode + * @{ + */ +#define MCAN_RX_FIFO_BLOCKING (0x0U) /*!< Rx FIFO blocking mode. + New received message will be discarded. */ +#define MCAN_RX_FIFO_OVERWRITE (MCAN_RXF0C_F0OM) /*!< Rx FIFO overwrite mode. + New received message will overwrite the oldest received message. */ +/** + * @} + */ + +/** + * @defgroup MCAN_NMF_Operation MCAN Non-matching Frame Operation + * @{ + */ +#define MCAN_NMF_ACCEPT_IN_RX_FIFO0 (0x0U) /*!< Accept in Rx FIFO 0 */ +#define MCAN_NMF_ACCEPT_IN_RX_FIFO1 (0x1U) /*!< Accept in Rx FIFO 1 */ +#define MCAN_NMF_REJECT (0x2U) /*!< Reject all non-matching frames */ +/** + * @} + */ + +/** + * @defgroup MCAN_Remote_Frame_Operation MCAN Remote Frame Operation + * @{ + */ +#define MCAN_REMOTE_FRAME_FILTER (0x0U) /*!< Filter remote frames with ID */ +#define MCAN_REMOTE_FRAME_REJECT (0x1U) /*!< Reject all remote frames */ +/** + * @} + */ + +/** + * @defgroup MCAN_Interrupt_Line MCAN Interrupt Line + * @{ + */ +#define MCAN_INT_LINE0 (0x1U) /*!< Interrupt line 0 */ +#define MCAN_INT_LINE1 (0x2U) /*!< Interrupt line 1 */ +/** + * @} + */ + +/** + * @defgroup MCAN_Timeout_Select MCAN Timeout Select + * @{ + */ +#define MCAN_TIMEOUT_CONT (0x0U) /*!< Timeout continuous operation */ +#define MCAN_TIMEOUT_TX_EVT_FIFO (MCAN_TOCC_TOS_0) /*!< Timeout controlled by Tx event FIFO */ +#define MCAN_TIMEOUT_RX_FIFO0 (MCAN_TOCC_TOS_1) /*!< Timeout controlled by Rx FIFO0 */ +#define MCAN_TIMEOUT_RX_FIFO1 (MCAN_TOCC_TOS) /*!< Timeout controlled by Rx FIFO1 */ +/** + * @} + */ + +/** + * @defgroup MCAN_Interrupt MCAN Interrupt + * @{ + */ +#define MCAN_INT_RX_FIFO0_NEW_MSG (MCAN_IE_RF0NE) /*!< New message written to Rx FIFO 0 */ +#define MCAN_INT_RX_FIFO0_WATERMARK (MCAN_IE_RF0WE) /*!< Rx FIFO 0 fill level reached watermark */ +#define MCAN_INT_RX_FIFO0_FULL (MCAN_IE_RF0FE) /*!< Rx FIFO 0 full */ +#define MCAN_INT_RX_FIFO0_MSG_LOST (MCAN_IE_RF0LE) /*!< Rx FIFO 0 message lost */ +#define MCAN_INT_RX_FIFO1_NEW_MSG (MCAN_IE_RF1NE) /*!< New message written to Rx FIFO 1 */ +#define MCAN_INT_RX_FIFO1_WATERMARK (MCAN_IE_RF1WE) /*!< Rx FIFO 1 fill level reached watermark */ +#define MCAN_INT_RX_FIFO1_FULL (MCAN_IE_RF1FE) /*!< Rx FIFO 1 full */ +#define MCAN_INT_RX_FIFO1_MSG_LOST (MCAN_IE_RF1LE) /*!< Rx FIFO 1 message lost */ +#define MCAN_INT_RX_HPM (MCAN_IE_HPME) /*!< High priority message received */ +#define MCAN_INT_TX_CPLT (MCAN_IE_TCE) /*!< Transmission completed */ +#define MCAN_INT_TX_ABORT_CPLT (MCAN_IE_TCFE) /*!< Transmission cancellation finished */ +#define MCAN_INT_TX_FIFO_EMPTY (MCAN_IE_TFEE) /*!< Tx FIFO empty */ +#define MCAN_INT_TX_EVT_FIFO_NEW_DATA (MCAN_IE_TEFNE) /*!< Tx handler wrote Tx event FIFO element */ +#define MCAN_INT_TX_EVT_FIFO_WATERMARK (MCAN_IE_TEFWE) /*!< Tx event FIFO fill level reached watermark */ +#define MCAN_INT_TX_EVT_FIFO_FULL (MCAN_IE_TEFFE) /*!< Tx event FIFO full */ +#define MCAN_INT_TX_EVT_FIFO_LOST (MCAN_IE_TEFLE) /*!< Tx event FIFO element lost */ +#define MCAN_INT_TIMESTAMP_WRAPAROUND (MCAN_IE_TSWE) /*!< Timestamp counter wrapped around */ +#define MCAN_INT_RAM_ACCESS_FAILURE (MCAN_IE_MRAFE) /*!< Message RAM access failure occurred */ +#define MCAN_INT_TIMEOUT (MCAN_IE_TOOE) /*!< Timeout reached */ +#define MCAN_INT_RX_BUF_NEW_MSG (MCAN_IE_DRXE) /*!< At least one received message stored into a Rx buffer */ +#define MCAN_INT_ERR_LOG_OVF (MCAN_IE_ELOE) /*!< Overflow of CAN error logging counter occurred */ +#define MCAN_INT_ERR_PASSIVE (MCAN_IE_EPE) /*!< Error_Passive status changed */ +#define MCAN_INT_ERR_WARNING (MCAN_IE_EWE) /*!< Error_Warning status changed */ +#define MCAN_INT_BUS_OFF (MCAN_IE_BOE) /*!< Bus_Off status changed */ +#define MCAN_INT_RAM_WDT (MCAN_IE_WDIE) /*!< Message RAM Watchdog event due to missing READY */ +#define MCAN_INT_ARB_PHASE_ERROR (MCAN_IE_PEAE) /*!< Protocol error in arbitration phase detected */ +#define MCAN_INT_DATA_PHASE_ERROR (MCAN_IE_PEDE) /*!< Protocol error in data phase detected */ +#define MCAN_INT_RSVD_ADDR_ACCESS (MCAN_IE_ARAE) /*!< Access to reserved address occurred */ +#define MCAN_INT_ALL (0x3FCFFFFFUL) +/** + * @} + */ + +/** + * @defgroup MCAN_Interrupt_Flag MCAN Interrupt Flag + * @{ + */ +#define MCAN_FLAG_RX_FIFO0_NEW_MSG (MCAN_IR_RF0N) /*!< New message written to Rx FIFO 0 */ +#define MCAN_FLAG_RX_FIFO0_WATERMARK (MCAN_IR_RF0W) /*!< Rx FIFO 0 fill level reached watermark */ +#define MCAN_FLAG_RX_FIFO0_FULL (MCAN_IR_RF0F) /*!< Rx FIFO 0 full */ +#define MCAN_FLAG_RX_FIFO0_MSG_LOST (MCAN_IR_RF0L) /*!< Rx FIFO 0 message lost */ +#define MCAN_FLAG_RX_FIFO1_NEW_MSG (MCAN_IR_RF1N) /*!< New message written to Rx FIFO 1 */ +#define MCAN_FLAG_RX_FIFO1_WATERMARK (MCAN_IR_RF1W) /*!< Rx FIFO 1 fill level reached watermark */ +#define MCAN_FLAG_RX_FIFO1_FULL (MCAN_IR_RF1F) /*!< Rx FIFO 1 full */ +#define MCAN_FLAG_RX_FIFO1_MSG_LOST (MCAN_IR_RF1L) /*!< Rx FIFO 1 message lost */ +#define MCAN_FLAG_RX_HPM (MCAN_IR_HPM) /*!< High priority message received */ +#define MCAN_FLAG_TX_CPLT (MCAN_IR_TC) /*!< Transmission completed */ +#define MCAN_FLAG_TX_ABORT_CPLT (MCAN_IR_TCF) /*!< Transmission cancellation finished */ +#define MCAN_FLAG_TX_FIFO_EMPTY (MCAN_IR_TFE) /*!< Tx FIFO empty */ +#define MCAN_FLAG_TX_EVT_FIFO_NEW_DATA (MCAN_IR_TEFN) /*!< Tx handler wrote Tx event FIFO element */ +#define MCAN_FLAG_TX_EVT_FIFO_WATERMARK (MCAN_IR_TEFW) /*!< Tx event FIFO fill level reached watermark */ +#define MCAN_FLAG_TX_EVT_FIFO_FULL (MCAN_IR_TEFF) /*!< Tx event FIFO full */ +#define MCAN_FLAG_TX_EVT_FIFO_LOST (MCAN_IR_TEFL) /*!< Tx event FIFO element lost */ +#define MCAN_FLAG_TIMESTAMP_WRAPAROUND (MCAN_IR_TSW) /*!< Timestamp counter wrapped around */ +#define MCAN_FLAG_RAM_ACCESS_FAILURE (MCAN_IR_MRAF) /*!< Message RAM access failure occurred */ +#define MCAN_FLAG_TIMEOUT (MCAN_IR_TOO) /*!< Timeout reached */ +#define MCAN_FLAG_RX_BUF_NEW_MSG (MCAN_IR_DRX) /*!< At least one received message stored into a Rx buffer */ +#define MCAN_FLAG_ERR_LOG_OVF (MCAN_IR_ELO) /*!< Overflow of CAN error logging counter occurred */ +#define MCAN_FLAG_ERR_PASSIVE (MCAN_IR_EP) /*!< Error_Passive status changed */ +#define MCAN_FLAG_ERR_WARNING (MCAN_IR_EW) /*!< Error_Warning status changed */ +#define MCAN_FLAG_BUS_OFF (MCAN_IR_BO) /*!< Bus_Off status changed */ +#define MCAN_FLAG_RAM_WDT (MCAN_IR_WDI) /*!< Message RAM Watchdog event due to missing READY */ +#define MCAN_FLAG_ARB_PHASE_ERROR (MCAN_IR_PEA) /*!< Protocol error in arbitration phase detected */ +#define MCAN_FLAG_DATA_PHASE_ERROR (MCAN_IR_PED) /*!< Protocol error in data phase detected */ +#define MCAN_FLAG_RSVD_ADDR_ACCESS (MCAN_IR_ARA) /*!< Access to reserved address occurred */ +#define MCAN_FLAG_ALL (0x3FCFFFFFUL) +/** + * @} + */ + +/** + * @defgroup MCAN_Evt_Type MCAN Event Type + * @{ + */ +#define MCAN_EVT_TX_EVT (0x01U) /*!< Tx event */ +#define MCAN_EVT_TX_WHEN_ABORTED (0x02U) /*!< Transmission in spite of cancellation (always set for transmissions in DAR mode) */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup MCAN_Global_Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +int32_t MCAN_Init(CM_MCAN_TypeDef *MCANx, stc_mcan_init_t *pstcMcanInit); +int32_t MCAN_StructInit(stc_mcan_init_t *pstcMcanInit); +void MCAN_DeInit(CM_MCAN_TypeDef *MCANx); +void MCAN_Start(CM_MCAN_TypeDef *MCANx); +int32_t MCAN_Stop(CM_MCAN_TypeDef *MCANx); +int32_t MCAN_EnterSleepMode(CM_MCAN_TypeDef *MCANx); +int32_t MCAN_ExitSleepMode(CM_MCAN_TypeDef *MCANx); +int32_t MCAN_GetMsgRamAddr(const CM_MCAN_TypeDef *MCANx, stc_mcan_msg_ram_addr_t *pstcAddr); + +/* Configuration functions ****************************************************/ +int32_t MCAN_FilterConfig(const CM_MCAN_TypeDef *MCANx, const stc_mcan_filter_t *pstcFilter); +void MCAN_GlobalFilterConfig(CM_MCAN_TypeDef *MCANx, \ + uint32_t u32StdNmfOperation, uint32_t u32ExtNmfOperation, \ + uint32_t u32StdRemoteOperation, uint32_t u32ExtRemoteOperation); +void MCAN_SetExtIDMask(CM_MCAN_TypeDef *MCANx, uint32_t u32Mask); +void MCAN_RxFifoOperationModeConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32RxFifo, uint32_t u32OperationMode); +void MCAN_SetFifoWatermark(CM_MCAN_TypeDef *MCANx, uint32_t u32Fifo, uint32_t u32Watermark); +void MCAN_RamWatchdogConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32StartValue); +uint8_t MCAN_GetRamWatchdogCountValue(const CM_MCAN_TypeDef *MCANx); +void MCAN_TimestampCounterConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32TsPrescaler); +void MCAN_TimestampCounterCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState); +uint16_t MCAN_GetTimestampCounter(const CM_MCAN_TypeDef *MCANx); +void MCAN_ResetTimestampCounter(CM_MCAN_TypeDef *MCANx); +void MCAN_TimeoutCounterConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32ToSelect, uint32_t u32ToPeriod); +void MCAN_TimeoutCounterCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState); +uint16_t MCAN_GetTimeoutCounter(const CM_MCAN_TypeDef *MCANx); +void MCAN_ResetTimeoutCounter(CM_MCAN_TypeDef *MCANx); +void MCAN_TxDelayCompensationConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32SspOffset, uint32_t u32TdcFilter); +void MCAN_TxDelayCompensationCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState); +void MCAN_SetFrameFormat(CM_MCAN_TypeDef *MCANx, uint32_t u32FrameFormat); +void MCAN_EdgeFilteringCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState); +void MCAN_TxEventMsgMarkerConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32MsgMarker); + +/* Control functions **********************************************************/ +int32_t MCAN_AddMsgToTxFifoQueue(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_msg_t *pTxMsg); +int32_t MCAN_AddMsgToTxBuffer(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_msg_t *pTxMsg); +void MCAN_EnableTxBufferRequest(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer); +void MCAN_AbortTxRequest(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer); +int32_t MCAN_GetRxMsg(CM_MCAN_TypeDef *MCANx, uint32_t u32RxLocation, stc_mcan_rx_msg_t *pRxMsg); +int32_t MCAN_GetTxEvent(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_event_t *pTxEvent); +int32_t MCAN_GetHighPriorityMsgStatus(const CM_MCAN_TypeDef *MCANx, stc_mcan_hpm_status_t *pHpmStatus); + +int32_t MCAN_GetProtocolStatus(const CM_MCAN_TypeDef *MCANx, stc_mcan_protocol_status_t *pProtocolStatus); +uint8_t MCAN_GetTdcValue(const CM_MCAN_TypeDef *MCANx); +uint8_t MCAN_GetDataLastErrorCode(const CM_MCAN_TypeDef *MCANx); +uint8_t MCAN_GetLastErrorCode(const CM_MCAN_TypeDef *MCANx); +uint8_t MCAN_GetComState(const CM_MCAN_TypeDef *MCANx); +en_flag_status_t MCAN_GetProtocolFlagStatus(const CM_MCAN_TypeDef *MCANx, uint32_t u32PsFlag); +int32_t MCAN_GetErrorCounter(const CM_MCAN_TypeDef *MCANx, stc_mcan_error_counter_t *pErrorCounter); + +en_flag_status_t MCAN_GetStatus(const CM_MCAN_TypeDef *MCANx, uint32_t u32Flag); +void MCAN_ClearStatus(CM_MCAN_TypeDef *MCANx, uint32_t u32Flag); +uint32_t MCAN_GetTxOccurredList(const CM_MCAN_TypeDef *MCANx); +uint32_t MCAN_GetTxAbortedList(const CM_MCAN_TypeDef *MCANx); +int32_t MCAN_CheckTxOccurred(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer); +int32_t MCAN_CheckTxAborted(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer); + +int32_t MCAN_CheckRxBufferMsgAvailable(CM_MCAN_TypeDef *MCANx, uint32_t u32RxBufferIndex); +int32_t MCAN_CheckTxBufferPending(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer); +uint32_t MCAN_GetRxFifoFillLevel(const CM_MCAN_TypeDef *MCANx, uint32_t u32RxFifo); +uint32_t MCAN_GetTxFifoFreeLevel(const CM_MCAN_TypeDef *MCANx); +int32_t MCAN_CheckRestrictedOperationMode(const CM_MCAN_TypeDef *MCANx); +void MCAN_ExitRestrictedOperationMode(CM_MCAN_TypeDef *MCANx); + +uint8_t MCAN_GetStartedTxBufferNum(const CM_MCAN_TypeDef *MCANx); +uint8_t MCAN_GetPreparedTxBufferNum(const CM_MCAN_TypeDef *MCANx); +uint8_t MCAN_GetBusLogicalState(const CM_MCAN_TypeDef *MCANx); +void MCAN_TxPinControl(CM_MCAN_TypeDef *MCANx, uint32_t u32PinCtrl); + +/* Interrupts management ******************************************************/ +void MCAN_IntCmd(CM_MCAN_TypeDef *MCANx, uint32_t u32IntType, uint32_t u32IntLine, \ + en_functional_state_t enNewState); +void MCAN_TxBufferNotificationCmd(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer, \ + uint32_t u32Notification, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_MCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_MCAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h new file mode 100644 index 0000000000..c85f59bd2b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_mpu.h @@ -0,0 +1,451 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.h + * @brief This file contains all the functions prototypes of the MPU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Add structure stc_mpu_unit_init_t, and declaration of MPU_UnitInit(), MPU_UnitStructInit() + Refine def group MPU_Flag + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_MPU_H__ +#define __HC32_LL_MPU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_MPU + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Types MPU Global Types + * @{ + */ + +/** + * @brief MPU Unit configure structure definition + */ +typedef struct { + uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region. + This parameter can be a value of @ref MPU_Exception_Type */ + uint32_t u32BackgroundWrite; /*!< Specifies the unit's write permission for the background space. + This parameter can be a value of @ref MPU_Background_Write_Permission */ + uint32_t u32BackgroundRead; /*!< Specifies the unit's read permission for the background space + This parameter can be a value of @ref MPU_Background_Read_Permission */ +} stc_mpu_unit_config_t; + +/** + * @brief MPU Unit initialize structure definition + */ +typedef struct { + uint32_t u32MpuState; /*!< Specifies the unit's state of mpu + This parameter can be a value of @ref MPU_Unit_State */ + uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region. + This parameter can be a value of @ref MPU_Exception_Type */ + uint32_t u32BackgroundWrite; /*!< Specifies the unit's write permission for the background space. + This parameter can be a value of @ref MPU_Background_Write_Permission */ + uint32_t u32BackgroundRead; /*!< Specifies the unit's read permission for the background space + This parameter can be a value of @ref MPU_Background_Read_Permission */ +} stc_mpu_unit_init_t; + +/** + * @brief MPU Init structure definition + */ +typedef struct { + stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */ + stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */ +} stc_mpu_init_t; + +/** + * @brief MPU Region Permission structure definition + */ +typedef struct { + uint32_t u32RegionWrite; /*!< Specifies the unit's write permission for the region. + This parameter can be a value of @ref MPU_Region_Write_Permission */ + uint32_t u32RegionRead; /*!< Specifies the unit's read permission for the region. + This parameter can be a value of @ref MPU_Region_Read_Permission */ +} stc_mpu_region_permission_t; + +/** + * @brief MPU region initialization structure definition + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + */ +typedef struct { + uint32_t u32BaseAddr; /*!< Specifies the base address of the region. + This parameter can be a number between 0UL and 0xFFFFFFE0UL */ + uint32_t u32Size; /*!< Specifies the size of the region. + This parameter can be a value of @ref MPU_Region_Size */ + stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */ + stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */ +} stc_mpu_region_init_t; + +/** + * @brief MPU Stack Pointer initialization structure definition + * @note The parameters 'u32Addr' and 'u32Size' must satisfy four-byte alignment. + */ +typedef struct { + uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the SP access outside specified range. + This parameter can be a value of @ref MPU_SP_Exception_Type */ + uint32_t u32Addr; /*!< Specifies the start address that the SP is allowed to access. + This parameter can be a number between 0UL and 0xFFFFFFFCUL */ + uint32_t u32Size; /*!< Specifies the allowed access range for the SP. + This parameter can be a number between 4UL and 65536UL */ +} stc_mpu_sp_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Macros MPU Global Macros + * @{ + */ + +/** + * @defgroup MPU_Unit_Type MPU Unit Type + * @{ + */ +#define MPU_UNIT_DMA1 (0x01UL) /*!< System DMA_1 MPU */ +#define MPU_UNIT_DMA2 (0x02UL) /*!< System DMA_2 MPU */ +#define MPU_UNIT_ALL (MPU_UNIT_DMA1 | MPU_UNIT_DMA2) +/** + * @} + */ + +/** + * @defgroup MPU_Region_Number MPU Region Number + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @{ + */ +#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */ +#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */ +#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */ +#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */ +#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */ +#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */ +#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */ +#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */ +#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */ +#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */ +#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */ +#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */ +#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */ +#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */ +#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */ +#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Write_Permission MPU Background Write Permission + * @{ + */ +#define MPU_BACKGROUND_WR_DISABLE (MPU_SCR_SMPUBWP) /*!< Disable write the background space */ +#define MPU_BACKGROUND_WR_ENABLE (0UL) /*!< Enable write the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Read_Permission MPU Background Read Permission + * @{ + */ +#define MPU_BACKGROUND_RD_DISABLE (MPU_SCR_SMPUBRP) /*!< Disable read the background space */ +#define MPU_BACKGROUND_RD_ENABLE (0UL) /*!< Enable read the background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Unit_State MPU unit state + * @{ + */ +#define MPU_UNIT_ENABLE (MPU_SCR_SMPUE) +#define MPU_UNIT_DISABLE (0UL) +/** + * @} + */ + +/** + * @defgroup MPU_Exception_Type MPU Exception Type + * @{ + */ +#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */ +#define MPU_EXP_TYPE_BUS_ERR (MPU_SCR_SMPUACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */ +#define MPU_EXP_TYPE_NMI (MPU_SCR_SMPUACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */ +#define MPU_EXP_TYPE_RST (MPU_SCR_SMPUACT) /*!< The host unit access protection regions will trigger the reset */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Write_Permission MPU Region Write Permission + * @{ + */ +#define MPU_REGION_WR_DISABLE (MPU_SRGWP_RG0WP) /*!< Disable write the region */ +#define MPU_REGION_WR_ENABLE (0UL) /*!< Enable write the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Read_Permission MPU Region Read Permission + * @{ + */ +#define MPU_REGION_RD_DISABLE (MPU_SRGRP_RG0RP) /*!< Disable read the region */ +#define MPU_REGION_RD_ENABLE (0UL) /*!< Enable read the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Size MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */ +#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */ +#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */ +#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */ +#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */ +#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */ +#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */ +#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */ +#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */ +#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */ +#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */ +#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */ +#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */ +#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */ +#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */ +#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */ +#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */ +#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */ +#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */ +#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */ +#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */ +#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */ +#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */ +#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */ +#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */ +#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */ +#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */ +#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */ +/** + * @} + */ + +/** + * @defgroup MPU_SP_Exception_Type MPU SP Exception Type + * @{ + */ +#define MPU_SP_EXP_TYPE_NMI (0UL) /*!< The SP access outside specified range will trigger a NMI interrupt */ +#define MPU_SP_EXP_TYPE_RST (MPU_MSPPCTL_MSPPACT) /*!< The SP access outside specified range will trigger a reset */ +/** + * @} + */ + +/** + * @defgroup MPU_SP_Unit_Type MPU SP Unit Type + * @{ + */ +#define MPU_SP_UNIT_MSP (0x01UL) /*!< MSP */ +#define MPU_SP_UNIT_PSP (0x02UL) /*!< PSP */ +#define MPU_SP_UNIT_ALL (MPU_SP_UNIT_MSP | MPU_SP_UNIT_PSP) +/** + * @} + */ + +/** + * @defgroup MPU_Flag MPU Flag + * @{ + */ +#define MPU_FLAG_DMA1 (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */ +#define MPU_FLAG_DMA2 (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */ +#define MPU_FLAG_PSP (MPU_SR_PSPEF) /*!< PSP error flag */ +#define MPU_FLAG_MSP (MPU_SR_MSPEF) /*!< MSP error flag */ +#define MPU_FLAG_ALL (MPU_FLAG_DMA1 | MPU_FLAG_DMA2 | MPU_FLAG_PSP | MPU_FLAG_MSP) + +/** + * @} + */ + +/** + * @defgroup MPU_IP_Type MPU IP Type + * @note IP access protection is not available in privileged mode. + * @{ + */ +#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */ +#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */ +#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */ +#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */ +#define MPU_IP_EFM (MPU_IPPR_EFMRDP) /*!< EFM module */ +#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */ +#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */ +#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */ +#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */ +#define MPU_IP_MPU (MPU_IPPR_DMPURDP) /*!< MPU module */ +#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */ +#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */ +#define MPU_IP_RMU_CMU_PWC (MPU_IPPR_SYSCRDP) /*!< RMU, CMU and PWC modules */ +#define MPU_IP_FCG (MPU_IPPR_MSTPRDP) /*!< PWR_FCG0/1/2/3 and PWR_FCG0PC registers */ +#define MPU_IP_ALL (MPU_IP_AES | MPU_IP_HASH | MPU_IP_TRNG | MPU_IP_CRC | \ + MPU_IP_EFM | MPU_IP_WDT | MPU_IP_SWDT | MPU_IP_BKSRAM | \ + MPU_IP_RTC | MPU_IP_MPU | MPU_IP_SRAMC | MPU_IP_INTC | \ + MPU_IP_FCG | MPU_IP_RMU_CMU_PWC) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Exception_Type MPU IP Exception Type + * @{ + */ +#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */ +#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */ +/** + * @} + */ + +/** + * @defgroup MPU_Register_Protect_Key INTC Registers Protect Key + * @{ + */ +#define MPU_REG_LOCK_KEY (0x96A4UL) +#define MPU_REG_UNLOCK_KEY (0x96A5UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup MPU_Global_Functions + * @{ + */ + +/** + * @brief MPU write protect unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Unlock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_UNLOCK_KEY); +} + +/** + * @brief MPU write protect lock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_REG_Lock(void) +{ + WRITE_REG32(CM_MPU->WP, MPU_REG_LOCK_KEY); +} + +void MPU_REG_Unlock(void); +void MPU_REG_Lock(void); + +void MPU_DeInit(void); +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit); +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit); +int32_t MPU_UnitInit(uint32_t u32Unit, stc_mpu_unit_init_t *pstcUnitInit); +int32_t MPU_UnitStructInit(stc_mpu_unit_init_t *pstcUnitInit); +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type); +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState); +en_flag_status_t MPU_GetStatus(uint32_t u32Flag); +void MPU_ClearStatus(uint32_t u32Flag); + +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit); +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit); +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr); +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size); +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); + +int32_t MPU_SPInit(uint32_t u32Unit, const stc_mpu_sp_init_t *pstcSpInit); +int32_t MPU_SPStructInit(stc_mpu_sp_init_t *pstcSpInit); +void MPU_SetSPStartAddr(uint32_t u32Unit, uint32_t u32Addr); +void MPU_SetSPSize(uint32_t u32Unit, uint32_t u32Size); +void MPU_SetSPExceptionType(uint32_t u32Unit, uint32_t u32Type); +void MPU_SPCmd(uint32_t u32Unit, en_functional_state_t enNewState); + +void MPU_IP_SetExceptionType(uint32_t u32Type); +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState); +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h new file mode 100644 index 0000000000..78cfc9308a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_pwc.h @@ -0,0 +1,664 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.h + * @brief This file contains all the functions prototypes of the PWC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify group PWC_Stop_Type + 2023-09-30 CDT Add function PWC_LVD_DeInit + Modify the PWC_LVD_Detection_Voltage_Sel comment + 2023-12-15 CDT Modify PWC_RAM_PD_CAN1 as PWC_RAM_PD_MCAN + Refine API PWC_SLEEP_Enter() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_PWC_H__ +#define __HC32_LL_PWC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_PWC + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Types PWC Global Types + * @{ + */ +/** + * @brief PWC LVD Init + */ +typedef struct { + uint32_t u32State; /*!< LVD function setting, @ref PWC_LVD_Config for details */ + uint32_t u32CompareOutputState; /*!< LVD compare output function setting, @ref PWC_LVD_CMP_Config for details */ + uint32_t u32ExceptionType; /*!< LVD interrupt or reset selection, @ref PWC_LVD_Exception_Type_Sel for details */ + uint32_t u32Filter; /*!< LVD digital filter function setting, @ref PWC_LVD_DF_Config for details */ + uint32_t u32FilterClock; /*!< LVD digital filter clock setting, @ref PWC_LVD_DFS_Clk_Sel for details */ + uint32_t u32ThresholdVoltage; /*!< LVD detect voltage setting, @ref PWC_LVD_Detection_Voltage_Sel for details */ + uint32_t u32TriggerEdge; /*!< LVD trigger setting, @ref PWC_LVD_TRIG_Sel for details */ +} stc_pwc_lvd_init_t; + +/** + * @brief PWC power down mode innit + */ +typedef struct { + uint8_t u8Mode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */ + uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */ + uint8_t u8VcapCtrl; /*!< Power down Wakeup time control, @ref PWC_PD_VCAP_Sel for details. */ +} stc_pwc_pd_mode_config_t; + +/** + * @brief PWC Stop mode Init + */ +typedef struct { + uint16_t u16Clock; /*!< System clock setting after wake-up from stop mode, + @ref PWC_STOP_CLK_Sel for details. */ + uint8_t u8StopDrv; /*!< Stop mode drive capacity, + @ref PWC_STOP_DRV_Sel for details. */ + uint16_t u16ExBusHold; /*!< Expos status in stop mode, + @ref PWC_STOP_EXBUS_Sel for details. */ + uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode, + @ref PWC_STOP_Flash_Wait_Sel for details. */ +} stc_pwc_stop_mode_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Macros PWC Global Macros + * @{ + */ + +/** + * @defgroup PWC_PDMode_Sel Power down mode selection + * @{ + */ +#define PWC_PD_MD1 (0x00U) /*!< Power down mode 1 */ +#define PWC_PD_MD2 (0x01U) /*!< Power down mode 2 */ +#define PWC_PD_MD3 (0x02U) /*!< Power down mode 3 */ +#define PWC_PD_MD4 (0x03U) /*!< Power down mode 4 */ +/** + * @} + */ + +/** + * @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode + * @{ + */ +#define PWC_PD_IO_KEEP1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */ +#define PWC_PD_IO_KEEP2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */ +#define PWC_PD_IO_HIZ (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_VCAP_Sel Wakeup speed config in Power down mode + * @{ + */ +#define PWC_PD_VCAP_0P1UF (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */ +#define PWC_PD_VCAP_0P047UF (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode + * @{ + */ +#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */ +#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_EXBUS_Sel ExBus status while enter stop mode + * @{ + */ +#define PWC_STOP_EXBUS_HIZ (0x00U) /*!< Ex-Bus Hiz in stop mode */ +#define PWC_STOP_EXBUS_HOLD (PWC_STPMCR_EXBUSOE) /*!< Ex-Bus keep in stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode + * @{ + */ +#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */ +#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */ + +/** + * @} + */ + +/** + * @defgroup PWC_STOP_Flash_Wait_Sel Whether wait flash stable or not after wake-up from stop mode + * @{ + */ +#define PWC_STOP_FLASH_WAIT_ON (0x00U) /*!< Wait flash stable after wake-up from stop mode */ +#define PWC_STOP_FLASH_WAIT_OFF (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_Stop_Type PWC stop mode type. + * @{ + */ +#define PWC_STOP_WFI (0x00U) /*!< Enter stop mode by WFI, and wake-up by interrupt handle. */ +#define PWC_STOP_WFE_INT (0x01U) /*!< Enter stop mode by WFE, and wake-up by interrupt request. */ +#define PWC_STOP_WFE_EVT (0x02U) /*!< Enter stop mode by WFE, and wake-up by event. */ +/** + * @} + */ + +/** + * @defgroup PWC_Stop_Type PWC stop mode type. + * @{ + */ +#define PWC_SLEEP_WFI (0x00U) /*!< Enter sleep mode by WFI, and wake-up by interrupt handle. */ +#define PWC_SLEEP_WFE_INT (0x01U) /*!< Enter sleep mode by WFE, and wake-up by interrupt request. */ +#define PWC_SLEEP_WFE_EVT (0x02U) /*!< Enter sleep mode by WFE, and wake-up by event. */ +/** + * @} + */ + +/** + * @defgroup PWC_RAM_Config Operating mode for RAM Config + * @{ + */ +#define PWC_RAM_HIGH_SPEED (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */ +#define PWC_RAM_ULOW_SPEED (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */ +/** + * @} + */ + +/** + * @defgroup PWC_PD_Periph_Ram Peripheral ram to power down + * @{ + */ +#define PWC_RAM_PD_MCAN (PWC_PRAMLPC_PRAMPDC0) +#define PWC_RAM_PD_CACHE (PWC_PRAMLPC_PRAMPDC2) +#define PWC_RAM_PD_ALL (PWC_PRAMLPC_PRAMPDC0 | PWC_PRAMLPC_PRAMPDC2) +/** + * @} + */ + +/** + * @defgroup PWC_PD_Ram Peripheral ram to power down + * @{ + */ +#define PWC_RAM_PD_SRAM0 (PWC_RAMPC0_RAMPDC0) /*!< 0x20000000 ~ 0x20007FFF */ +#define PWC_RAM_PD_SRAMH (PWC_RAMPC0_RAMPDC10) /*!< 0x1FFF8000 ~ 0x1FFFFFFF */ +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Channel PWC LVD channel + * @{ + */ +#define PWC_LVD_CH1 (0x00U) +#define PWC_LVD_CH2 (0x01U) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Config PWC LVD Config + * @{ + */ +#define PWC_LVD_ON (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Exception_Type_Sel PWC LVD Exception Type Select + * @{ + */ +#define PWC_LVD_EXP_TYPE_NONE (0x00U) +#define PWC_LVD_EXP_TYPE_NMI (0x01U) +#define PWC_LVD_EXP_TYPE_RST (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_CMP_Config PWC LVD Compare Config + * @{ + */ +#define PWC_LVD_CMP_OFF (0x00U) +#define PWC_LVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DF_Config LVD digital filter ON or OFF + * @{ + */ +#define PWC_LVD_FILTER_ON (0x00U) +#define PWC_LVD_FILTER_OFF (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_LVD_DFS_Clk_Sel LVD digital filter sample ability + * @note modified this value must when PWC_LVD_FILTER_OFF + * @{ + */ +#define PWC_LVD_FILTER_LRC_DIV4 (0x00UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.25 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV2 (0x01UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 0.5 LRC cycle */ +#define PWC_LVD_FILTER_LRC_DIV1 (0x02UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 1 LRC cycle */ +#define PWC_LVD_FILTER_LRC_MUL2 (0x03UL << PWC_PVDFCR_PVD1NFCKS_POS) /*!< 2 LRC cycles */ + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Detection_Voltage_Sel PWC LVD Detection voltage + * @{ + * @note + * @verbatim + * | LVL0 | LVL1 | LVL2 | LVL3 | LVL4 | LVL5 | LVL6 | LVL7 | EXVCC | + * LVD1 | 2.00V | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | -- | + * LVD2 | 2.10V | 2.30V | 2.55V | 2.65V | 2.75V | 2.85V | 2.95V | 1.10V | EXVCC | + * @endverbatim + */ +#define PWC_LVD_THRESHOLD_LVL0 (0x00U) +#define PWC_LVD_THRESHOLD_LVL1 (0x01U) +#define PWC_LVD_THRESHOLD_LVL2 (0x02U) +#define PWC_LVD_THRESHOLD_LVL3 (0x03U) +#define PWC_LVD_THRESHOLD_LVL4 (0x04U) +#define PWC_LVD_THRESHOLD_LVL5 (0x05U) +#define PWC_LVD_THRESHOLD_LVL6 (0x06U) +#define PWC_LVD_THRESHOLD_LVL7 (0x07U) +#define PWC_LVD_EXTVCC (0x07U) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_TRIG_Sel LVD trigger setting + * @{ + */ +#define PWC_LVD_TRIG_FALLING (0x00UL << PWC_PVDICR_PVD1EDGS_POS) +#define PWC_LVD_TRIG_RISING (0x01UL << PWC_PVDICR_PVD1EDGS_POS) +#define PWC_LVD_TRIG_BOTH (0x02UL << PWC_PVDICR_PVD1EDGS_POS) + +/** + * @} + */ + +/** + * @defgroup PWC_LVD_Flag LVD flag + * @{ + */ +#define PWC_LVD1_FLAG_DETECT (PWC_PVDDSR_PVD1DETFLG) /*!< VCC across VLVD1 */ +#define PWC_LVD2_FLAG_DETECT (PWC_PVDDSR_PVD2DETFLG) /*!< VCC across VLVD2 */ +#define PWC_LVD1_FLAG_MON (PWC_PVDDSR_PVD1MON) /*!< VCC > VLVD1 */ +#define PWC_LVD2_FLAG_MON (PWC_PVDDSR_PVD2MON) /*!< VCC > VLVD2 */ + +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection + * @{ + */ +#define PWC_PD_WKUP0_POS (0U) +#define PWC_PD_WKUP1_POS (8U) +#define PWC_PD_WKUP2_POS (16U) +#define PWC_PD_WKUP_WKUP00 (PWC_PDWKE0_WKE00 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP01 (PWC_PDWKE0_WKE01 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP02 (PWC_PDWKE0_WKE02 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP03 (PWC_PDWKE0_WKE03 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP10 (PWC_PDWKE0_WKE10 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP11 (PWC_PDWKE0_WKE11 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP12 (PWC_PDWKE0_WKE12 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP13 (PWC_PDWKE0_WKE13 << PWC_PD_WKUP0_POS) +#define PWC_PD_WKUP_WKUP20 (PWC_PDWKE1_WKE20 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP21 (PWC_PDWKE1_WKE21 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP22 (PWC_PDWKE1_WKE22 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP23 (PWC_PDWKE1_WKE23 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP30 (PWC_PDWKE1_WKE30 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP31 (PWC_PDWKE1_WKE31 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP32 (PWC_PDWKE1_WKE32 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_WKUP33 (PWC_PDWKE1_WKE33 << PWC_PD_WKUP1_POS) +#define PWC_PD_WKUP_LVD1 (PWC_PDWKE2_VD1WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_LVD2 (PWC_PDWKE2_VD2WKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCPRD (PWC_PDWKE2_RTCPRDWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_RTCALM (PWC_PDWKE2_RTCALMWKE << PWC_PD_WKUP2_POS) +#define PWC_PD_WKUP_WKTM (PWC_PDWKE2_WKTMWKE << PWC_PD_WKUP2_POS) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Event_Sel Power down mode wakeup event selection to set trigger edge. + * @{ + */ +#define PWC_PD_WKUP_TRIG_LVD1 (PWC_PDWKES_VD1EGS) +#define PWC_PD_WKUP_TRIG_LVD2 (PWC_PDWKES_VD2EGS) +#define PWC_PD_WKUP_TRIG_WKUP0 (PWC_PDWKES_WK0EGS) +#define PWC_PD_WKUP_TRIG_WKUP1 (PWC_PDWKES_WK1EGS) +#define PWC_PD_WKUP_TRIG_WKUP2 (PWC_PDWKES_WK2EGS) +#define PWC_PD_WKUP_TRIG_WKUP3 (PWC_PDWKES_WK3EGS) + +#define PWC_PD_WKUP_TRIG_ALL (PWC_PD_WKUP_TRIG_LVD1 | PWC_PD_WKUP_TRIG_LVD2 | PWC_PD_WKUP_TRIG_WKUP0 | \ + PWC_PD_WKUP_TRIG_WKUP1 | PWC_PD_WKUP_TRIG_WKUP2 | PWC_PD_WKUP_TRIG_WKUP3) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection + * @{ + */ +#define PWC_PD_WKUP_TRIG_FALLING (0x00U) +#define PWC_PD_WKUP_TRIG_RISING (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Flag_Sel Power down mode wakeup Event status selection + * @{ + */ +#define PWC_PD_WKUP_FLAG0_POS (0U) +#define PWC_PD_WKUP_FLAG1_POS (8U) +#define PWC_PD_WKUP_FLAG_WKUP0 (PWC_PDWKF0_PTWK0F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP1 (PWC_PDWKF0_PTWK1F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP2 (PWC_PDWKF0_PTWK2F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_WKUP3 (PWC_PDWKF0_PTWK3F << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD1 (PWC_PDWKF0_VD1WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_LVD2 (PWC_PDWKF0_VD2WKF << PWC_PD_WKUP_FLAG0_POS) +#define PWC_PD_WKUP_FLAG_RTCPRD (PWC_PDWKF1_RTCPRDWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_RTCALM (PWC_PDWKF1_RTCALMWKF << PWC_PD_WKUP_FLAG1_POS) +#define PWC_PD_WKUP_FLAG_WKTM (PWC_PDWKF1_WKTMWKF << PWC_PD_WKUP_FLAG1_POS) + +#define PWC_PD_WKUP_FLAG_ALL (PWC_PD_WKUP_FLAG_WKUP0 | PWC_PD_WKUP_FLAG_WKUP1 | PWC_PD_WKUP_FLAG_WKUP2 | \ + PWC_PD_WKUP_FLAG_WKUP3 | PWC_PD_WKUP_FLAG_LVD1 | PWC_PD_WKUP_FLAG_LVD2 | \ + PWC_PD_WKUP_FLAG_RTCPRD | PWC_PD_WKUP_FLAG_RTCALM | PWC_PD_WKUP_FLAG_WKTM) +/** + * @} + */ + +/** + * @defgroup PWC_WKT_State PWC WKT State + * @{ + */ +#define PWC_WKT_OFF (0x00U) +#define PWC_WKT_ON (PWC_WKTCR_WKTCE) +/** + * @} + */ + +/** + * @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source + * @{ + */ +#define PWC_WKT_CLK_SRC_64HZ ((0x00U << PWC_WKTCR_WKCKS_POS)) /*!< 64Hz Clock */ +#define PWC_WKT_CLK_SRC_XTAL32 ((0x01U << PWC_WKTCR_WKCKS_POS)) /*!< XTAL32 Clock */ +#define PWC_WKT_CLK_SRC_LRC ((0x02U << PWC_WKTCR_WKCKS_POS)) /*!< LRC Clock */ + +/** + * @} + */ + +/** + * @defgroup PWC_Ldo_Sel PWC LDO Selection + * @{ + */ +#define PWC_LDO_HRC (PWC_PWRC1_VHRCSD) +#define PWC_LDO_PLL (PWC_PWRC1_VPLLSD) +#define PWC_LDO_MASK (PWC_LDO_HRC | PWC_LDO_PLL) +/** + * @} + */ + +/** + * @defgroup PWC_Rtc_Clock_Sel PWC RTC clock selection + * @{ + */ +#define PWC_RTC_CLK_LRC (0x00U) /*!< Rtc clock selects LRC */ +#define PWC_RTC_CLK_XTAL_DIV (0x01U) /*!< Rtc clock selects XTAL div as 32.768KHz */ +/** + * @} + */ + +/** + * @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code. + * @brief Lock/unlock Code for each module + * PWC_UNLOCK_CODE0: + * Below registers are locked in CLK module. + * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR, + * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR, + * SCFGR, USBCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR, + * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM. + * PWC_UNLOCK_CODE1: + * Below registers are locked in PWC module. + * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0, + * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM. + * Below registers are locked in CLK module. + * PERICKSEL, I2SCKSEL, + * Below register is locked in RMU module. + * RSTF0 + * PWC_UNLOCK_CODE2: + * Below registers are locked in PWC module. + * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR + * @{ + */ +#define PWC_WRITE_ENABLE (0xA500U) +#define PWC_UNLOCK_CODE0 (0xA501U) +#define PWC_UNLOCK_CODE1 (0xA502U) +#define PWC_UNLOCK_CODE2 (0xA508U) + +/** + * @brief PWC FCG0 Unlock/Lock code + */ +#define PWC_FCG0_REG_UNLOCK_KEY (0xA5A50001UL) +#define PWC_FCG0_REG_LOCK_KEY (0xA5A50000UL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup PWC_Global_Functions + * @{ + */ +/** + * @brief Lock PWC, CLK, RMU register. + * @param [in] u16Module Lock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Lock(uint16_t u16Module) +{ + CM_PWC->FPRC = (PWC_WRITE_ENABLE | (uint16_t)((uint16_t)(~u16Module) & (CM_PWC->FPRC))); +} + +/** + * @brief Unlock PWC, CLK, RMU register. + * @param [in] u16Module Unlock code for each module. + * @arg PWC_UNLOCK_CODE0 + * @arg PWC_UNLOCK_CODE1 + * @arg PWC_UNLOCK_CODE2 + * @retval None + */ +__STATIC_INLINE void PWC_REG_Unlock(uint16_t u16Module) +{ + SET_REG16_BIT(CM_PWC->FPRC, u16Module); +} + +/** + * @brief Lock PWC_FCG0 register . + * @param None + * @retval None + */ +__STATIC_INLINE void PWC_FCG0_REG_Lock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_LOCK_KEY); +} + +/** + * @brief Unlock PWR_FCG0 register. + * @param None + * @retval None + * @note Call this function before FCG_Fcg0PeriphClockCmd() + */ +__STATIC_INLINE void PWC_FCG0_REG_Unlock(void) +{ + WRITE_REG32(CM_PWC->FCG0PC, PWC_FCG0_REG_UNLOCK_KEY); +} + +/* PWC PD Function */ +int32_t PWC_PD_Enter(void); +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig); +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig); +void PWC_PD_SetIoState(uint8_t u8IoState); +void PWC_PD_SetMode(uint8_t u8PdMode); +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState); +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge); +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag); +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag); +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState); +void PWC_PD_RamCmd(uint32_t u32Ram, en_functional_state_t enNewState); +void PWC_PD_VdrCmd(en_functional_state_t enNewState); + +/* PWC WKTM Function */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal); +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal); +uint16_t PWC_WKT_GetCompareValue(void); +void PWC_WKT_Cmd(en_functional_state_t enNewState); +en_flag_status_t PWC_WKT_GetStatus(void); +void PWC_WKT_ClearStatus(void); + +void PWC_RamModeConfig(uint16_t u16Mode); + +/* PWC Sleep Function */ +void PWC_SLEEP_Enter(uint8_t u8SleepType); + +/* PWC Stop Function */ +void PWC_STOP_Enter(uint8_t u8StopType); +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig); +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig); +void PWC_STOP_ClockSelect(uint8_t u8Clock); +void PWC_STOP_SetDrv(uint8_t u8StopDrv); +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState); + +void PWC_STOP_ExBusHoldConfig(uint16_t u16ExBusHold); + +/* PWC Speed Switch Function */ +int32_t PWC_HighSpeedToLowSpeed(void); +int32_t PWC_LowSpeedToHighSpeed(void); + +/* PWC LDO Function */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState); + +/* PWC LVD/PVD Function */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit); +void PWC_LVD_DeInit(uint8_t u8Ch); +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit); +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState); +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState); +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock); +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage); +void PWC_LVD_ClearStatus(uint8_t u8Flag); +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag); + +/* PWC Power Monitor Function */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState); + +/* PWC RAM Function */ + +void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState); +void PWC_RetSram_PowerCmd(en_functional_state_t enNewState); + +void PWC_SetRtcClock(uint8_t u8Clock); +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h new file mode 100644 index 0000000000..b4a95e9205 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_qspi.h @@ -0,0 +1,446 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.h + * @brief This file contains all the functions prototypes of the QSPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_QSPI_H__ +#define __HC32_LL_QSPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_QSPI + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Types QSPI Global Types + * @{ + */ + +/** + * @brief QSPI initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Specifies the clock division. + This parameter can be a value of @ref QSPI_Clock_Division */ + uint32_t u32SpiMode; /*!< Specifies the SPI mode. + This parameter can be a value of @ref QSPI_SPI_Mode */ + uint32_t u32PrefetchMode; /*!< Specifies the prefetch mode. + This parameter can be a value of @ref QSPI_Prefetch_Mode */ + uint32_t u32ReadMode; /*!< Specifies the read mode. + This parameter can be a value of @ref QSPI_Read_Mode */ + uint32_t u32DummyCycle; /*!< Specifies the number of dummy cycles. + This parameter can be a value of @ref QSPI_Dummy_Cycle */ + uint32_t u32AddrWidth; /*!< Specifies the address width. + This parameter can be a value of @ref QSPI_Addr_Width */ + uint32_t u32SetupTime; /*!< Specifies the advance time of QSSN setup. + This parameter can be a value of @ref QSPI_QSSN_Setup_Time */ + uint32_t u32ReleaseTime; /*!< Specifies the delay time of QSSN release. + This parameter can be a value of @ref QSPI_QSSN_Release_Time */ + uint32_t u32IntervalTime; /*!< Specifies the minimum interval time of QSSN. + This parameter can be a value of @ref QSPI_QSSN_Interval_Time */ +} stc_qspi_init_t; + +/** + * @brief QSPI Custom read mode structure definition + */ +typedef struct { + uint32_t u32InstrProtocol; /*!< Specifies the instruction stage protocol. + This parameter can be a value of @ref QSPI_Instruction_Protocol */ + uint32_t u32AddrProtocol; /*!< Specifies the address stage protocol. + This parameter can be a value of @ref QSPI_Addr_Protocol */ + uint32_t u32DataProtocol; /*!< Specifies the data stage protocol. + This parameter can be a value of @ref QSPI_Data_Protocol */ + uint8_t u8InstrCode; /*!< Specifies the instruction code in custom read mode. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */ +} stc_qspi_custom_mode_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Macros QSPI Global Macros + * @{ + */ + +/* QSPI memory mapping base and end address */ +#define QSPI_ROM_BASE (0x98000000UL) +#define QSPI_ROM_END (0x9BFFFFFFUL) + +/** + * @defgroup QSPI_Clock_Division QSPI Clock Division + * @{ + */ +#define QSPI_CLK_DIV2 (0x01UL << QSPI_CR_DIV_POS) /*!< Clock division by 2 */ +#define QSPI_CLK_DIV3 (0x02UL << QSPI_CR_DIV_POS) /*!< Clock division by 3 */ +#define QSPI_CLK_DIV4 (0x03UL << QSPI_CR_DIV_POS) /*!< Clock division by 4 */ +#define QSPI_CLK_DIV5 (0x04UL << QSPI_CR_DIV_POS) /*!< Clock division by 5 */ +#define QSPI_CLK_DIV6 (0x05UL << QSPI_CR_DIV_POS) /*!< Clock division by 6 */ +#define QSPI_CLK_DIV7 (0x06UL << QSPI_CR_DIV_POS) /*!< Clock division by 7 */ +#define QSPI_CLK_DIV8 (0x07UL << QSPI_CR_DIV_POS) /*!< Clock division by 8 */ +#define QSPI_CLK_DIV9 (0x08UL << QSPI_CR_DIV_POS) /*!< Clock division by 9 */ +#define QSPI_CLK_DIV10 (0x09UL << QSPI_CR_DIV_POS) /*!< Clock division by 10 */ +#define QSPI_CLK_DIV11 (0x0AUL << QSPI_CR_DIV_POS) /*!< Clock division by 11 */ +#define QSPI_CLK_DIV12 (0x0BUL << QSPI_CR_DIV_POS) /*!< Clock division by 12 */ +#define QSPI_CLK_DIV13 (0x0CUL << QSPI_CR_DIV_POS) /*!< Clock division by 13 */ +#define QSPI_CLK_DIV14 (0x0DUL << QSPI_CR_DIV_POS) /*!< Clock division by 14 */ +#define QSPI_CLK_DIV15 (0x0EUL << QSPI_CR_DIV_POS) /*!< Clock division by 15 */ +#define QSPI_CLK_DIV16 (0x0FUL << QSPI_CR_DIV_POS) /*!< Clock division by 16 */ +#define QSPI_CLK_DIV17 (0x10UL << QSPI_CR_DIV_POS) /*!< Clock division by 17 */ +#define QSPI_CLK_DIV18 (0x11UL << QSPI_CR_DIV_POS) /*!< Clock division by 18 */ +#define QSPI_CLK_DIV19 (0x12UL << QSPI_CR_DIV_POS) /*!< Clock division by 19 */ +#define QSPI_CLK_DIV20 (0x13UL << QSPI_CR_DIV_POS) /*!< Clock division by 20 */ +#define QSPI_CLK_DIV21 (0x14UL << QSPI_CR_DIV_POS) /*!< Clock division by 21 */ +#define QSPI_CLK_DIV22 (0x15UL << QSPI_CR_DIV_POS) /*!< Clock division by 22 */ +#define QSPI_CLK_DIV23 (0x16UL << QSPI_CR_DIV_POS) /*!< Clock division by 23 */ +#define QSPI_CLK_DIV24 (0x17UL << QSPI_CR_DIV_POS) /*!< Clock division by 24 */ +#define QSPI_CLK_DIV25 (0x18UL << QSPI_CR_DIV_POS) /*!< Clock division by 25 */ +#define QSPI_CLK_DIV26 (0x19UL << QSPI_CR_DIV_POS) /*!< Clock division by 26 */ +#define QSPI_CLK_DIV27 (0x1AUL << QSPI_CR_DIV_POS) /*!< Clock division by 27 */ +#define QSPI_CLK_DIV28 (0x1BUL << QSPI_CR_DIV_POS) /*!< Clock division by 28 */ +#define QSPI_CLK_DIV29 (0x1CUL << QSPI_CR_DIV_POS) /*!< Clock division by 29 */ +#define QSPI_CLK_DIV30 (0x1DUL << QSPI_CR_DIV_POS) /*!< Clock division by 30 */ +#define QSPI_CLK_DIV31 (0x1EUL << QSPI_CR_DIV_POS) /*!< Clock division by 31 */ +#define QSPI_CLK_DIV32 (0x1FUL << QSPI_CR_DIV_POS) /*!< Clock division by 32 */ +#define QSPI_CLK_DIV33 (0x20UL << QSPI_CR_DIV_POS) /*!< Clock division by 33 */ +#define QSPI_CLK_DIV34 (0x21UL << QSPI_CR_DIV_POS) /*!< Clock division by 34 */ +#define QSPI_CLK_DIV35 (0x22UL << QSPI_CR_DIV_POS) /*!< Clock division by 35 */ +#define QSPI_CLK_DIV36 (0x23UL << QSPI_CR_DIV_POS) /*!< Clock division by 36 */ +#define QSPI_CLK_DIV37 (0x24UL << QSPI_CR_DIV_POS) /*!< Clock division by 37 */ +#define QSPI_CLK_DIV38 (0x25UL << QSPI_CR_DIV_POS) /*!< Clock division by 38 */ +#define QSPI_CLK_DIV39 (0x26UL << QSPI_CR_DIV_POS) /*!< Clock division by 39 */ +#define QSPI_CLK_DIV40 (0x27UL << QSPI_CR_DIV_POS) /*!< Clock division by 40 */ +#define QSPI_CLK_DIV41 (0x28UL << QSPI_CR_DIV_POS) /*!< Clock division by 41 */ +#define QSPI_CLK_DIV42 (0x29UL << QSPI_CR_DIV_POS) /*!< Clock division by 42 */ +#define QSPI_CLK_DIV43 (0x2AUL << QSPI_CR_DIV_POS) /*!< Clock division by 43 */ +#define QSPI_CLK_DIV44 (0x2BUL << QSPI_CR_DIV_POS) /*!< Clock division by 44 */ +#define QSPI_CLK_DIV45 (0x2CUL << QSPI_CR_DIV_POS) /*!< Clock division by 45 */ +#define QSPI_CLK_DIV46 (0x2DUL << QSPI_CR_DIV_POS) /*!< Clock division by 46 */ +#define QSPI_CLK_DIV47 (0x2EUL << QSPI_CR_DIV_POS) /*!< Clock division by 47 */ +#define QSPI_CLK_DIV48 (0x2FUL << QSPI_CR_DIV_POS) /*!< Clock division by 48 */ +#define QSPI_CLK_DIV49 (0x30UL << QSPI_CR_DIV_POS) /*!< Clock division by 49 */ +#define QSPI_CLK_DIV50 (0x31UL << QSPI_CR_DIV_POS) /*!< Clock division by 50 */ +#define QSPI_CLK_DIV51 (0x32UL << QSPI_CR_DIV_POS) /*!< Clock division by 51 */ +#define QSPI_CLK_DIV52 (0x33UL << QSPI_CR_DIV_POS) /*!< Clock division by 52 */ +#define QSPI_CLK_DIV53 (0x34UL << QSPI_CR_DIV_POS) /*!< Clock division by 53 */ +#define QSPI_CLK_DIV54 (0x35UL << QSPI_CR_DIV_POS) /*!< Clock division by 54 */ +#define QSPI_CLK_DIV55 (0x36UL << QSPI_CR_DIV_POS) /*!< Clock division by 55 */ +#define QSPI_CLK_DIV56 (0x37UL << QSPI_CR_DIV_POS) /*!< Clock division by 56 */ +#define QSPI_CLK_DIV57 (0x38UL << QSPI_CR_DIV_POS) /*!< Clock division by 57 */ +#define QSPI_CLK_DIV58 (0x39UL << QSPI_CR_DIV_POS) /*!< Clock division by 58 */ +#define QSPI_CLK_DIV59 (0x3AUL << QSPI_CR_DIV_POS) /*!< Clock division by 59 */ +#define QSPI_CLK_DIV60 (0x3BUL << QSPI_CR_DIV_POS) /*!< Clock division by 60 */ +#define QSPI_CLK_DIV61 (0x3CUL << QSPI_CR_DIV_POS) /*!< Clock division by 61 */ +#define QSPI_CLK_DIV62 (0x3DUL << QSPI_CR_DIV_POS) /*!< Clock division by 62 */ +#define QSPI_CLK_DIV63 (0x3EUL << QSPI_CR_DIV_POS) /*!< Clock division by 63 */ +#define QSPI_CLK_DIV64 (0x3FUL << QSPI_CR_DIV_POS) /*!< Clock division by 64 */ +/** + * @} + */ + +/** + * @defgroup QSPI_SPI_Mode QSPI SPI Mode + * @{ + */ +#define QSPI_SPI_MD0 (0UL) /*!< Selects SPI mode 0 */ +#define QSPI_SPI_MD3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Prefetch_Mode QSPI Prefetch Mode + * @{ + */ +#define QSPI_PREFETCH_MD_INVD (0UL) /*!< Disable prefetch */ +#define QSPI_PREFETCH_MD_EDGE_STOP (QSPI_CR_PFE) /*!< Stop prefetch at the edge of byte */ +#define QSPI_PREFETCH_MD_IMMED_STOP (QSPI_CR_PFE | QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately */ +/** + * @} + */ + +/** + * @defgroup QSPI_Read_Mode QSPI Read Mode + * @{ + */ +#define QSPI_RD_MD_STD_RD (0UL) /*!< Standard read mode (no dummy cycles) */ +#define QSPI_RD_MD_FAST_RD (0x01UL << QSPI_CR_MDSEL_POS) /*!< Fast read mode (dummy cycles between address and data) */ +#define QSPI_RD_MD_DUAL_OUTPUT_FAST_RD (0x02UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual output mode (data on 2 lines) */ +#define QSPI_RD_MD_DUAL_IO_FAST_RD (0x03UL << QSPI_CR_MDSEL_POS) /*!< Fast read dual I/O mode (address and data on 2 lines) */ +#define QSPI_RD_MD_QUAD_OUTPUT_FAST_RD (0x04UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad output mode (data on 4 lines) */ +#define QSPI_RD_MD_QUAD_IO_FAST_RD (0x05UL << QSPI_CR_MDSEL_POS) /*!< Fast read quad I/O mode (address and data on 4 lines) */ +#define QSPI_RD_MD_CUSTOM_STANDARD_RD (0x06UL << QSPI_CR_MDSEL_POS) /*!< Custom standard read mode */ +#define QSPI_RD_MD_CUSTOM_FAST_RD (0x07UL << QSPI_CR_MDSEL_POS) /*!< Custom fast read mode */ +/** + * @} + */ + +/** + * @defgroup QSPI_Dummy_Cycle QSPI Dummy Cycle + * @{ + */ +#define QSPI_DUMMY_CYCLE3 (0UL) /*!< Dummy cycle is 3 */ +#define QSPI_DUMMY_CYCLE4 (0x01UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 4 */ +#define QSPI_DUMMY_CYCLE5 (0x02UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 5 */ +#define QSPI_DUMMY_CYCLE6 (0x03UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 6 */ +#define QSPI_DUMMY_CYCLE7 (0x04UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 7 */ +#define QSPI_DUMMY_CYCLE8 (0x05UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 8 */ +#define QSPI_DUMMY_CYCLE9 (0x06UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 9 */ +#define QSPI_DUMMY_CYCLE10 (0x07UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 10 */ +#define QSPI_DUMMY_CYCLE11 (0x08UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 11 */ +#define QSPI_DUMMY_CYCLE12 (0x09UL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 12 */ +#define QSPI_DUMMY_CYCLE13 (0x0AUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 13 */ +#define QSPI_DUMMY_CYCLE14 (0x0BUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 14 */ +#define QSPI_DUMMY_CYCLE15 (0x0CUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE16 (0x0DUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +#define QSPI_DUMMY_CYCLE17 (0x0EUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 15 */ +#define QSPI_DUMMY_CYCLE18 (0x0FUL << QSPI_FCR_DMCYCN_POS) /*!< Dummy cycle is 16 */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Width QSPI Address Width + * @{ + */ +#define QSPI_ADDR_WIDTH_8BIT (0x0U) /*!< QSPI address width is 8 bits */ +#define QSPI_ADDR_WIDTH_16BIT (QSPI_FCR_AWSL_0) /*!< QSPI address width is 16 bits */ +#define QSPI_ADDR_WIDTH_24BIT (QSPI_FCR_AWSL_1) /*!< QSPI address width is 24 bits */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT (QSPI_FCR_AWSL) /*!< QSPI address width is 32 bits and don't use 4-byte address read instruction code */ +#define QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT (QSPI_FCR_AWSL | QSPI_FCR_FOUR_BIC) /*!< QSPI address width is 32 bits and use 4-byte address read instruction code */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Setup_Time QSPI QSSN Setup Time + * @{ + */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK0P5 (0UL) /*!< Output QSSN signal 0.5 QSCK before the first rising edge of QSCK */ +#define QSPI_QSSN_SETUP_ADVANCE_QSCK1P5 (QSPI_FCR_SSNLD) /*!< Output QSSN signal 1.5 QSCK before the first rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Release_Time QSPI QSSN Release Time + * @{ + */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK0P5 (0UL) /*!< Release QSSN signal 0.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK1P5 (QSPI_FCR_SSNHD) /*!< Release QSSN signal 1.5 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK32 (QSPI_CSCR_SSNW_0 << 8U) /*!< Release QSSN signal 32 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_QSCK128 (QSPI_CSCR_SSNW_1 << 8U) /*!< Release QSSN signal 128 QSCK after the last rising edge of QSCK */ +#define QSPI_QSSN_RELEASE_DELAY_INFINITE (QSPI_CSCR_SSNW << 8U) /*!< Never release QSSN signal after the last rising edge of QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSSN_Interval_Time QSPI QSSN Interval Time + * @{ + */ +#define QSPI_QSSN_INTERVAL_QSCK1 (0UL) /*!< Minimum interval time is 1 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK2 (0x01UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 2 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK3 (0x02UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 3 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK4 (0x03UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 4 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK5 (0x04UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 5 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK6 (0x05UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 6 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK7 (0x06UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 7 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK8 (0x07UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 8 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK9 (0x08UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 9 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK10 (0x09UL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 10 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK11 (0x0AUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 11 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK12 (0x0BUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 12 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK13 (0x0CUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 13 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK14 (0x0DUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 14 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK15 (0x0EUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 15 QSCK */ +#define QSPI_QSSN_INTERVAL_QSCK16 (0x0FUL << QSPI_CSCR_SSHW_POS) /*!< Minimum interval time is 16 QSCK */ +/** + * @} + */ + +/** + * @defgroup QSPI_Instruction_Protocol QSPI Instruction Protocol + * @{ + */ +#define QSPI_INSTR_PROTOCOL_1LINE (0x0U) /*!< Instruction on 1 line */ +#define QSPI_INSTR_PROTOCOL_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines */ +#define QSPI_INSTR_PROTOCOL_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Protocol QSPI Address Protocol + * @{ + */ +#define QSPI_ADDR_PROTOCOL_1LINE (0x0U) /*!< Address on 1 line */ +#define QSPI_ADDR_PROTOCOL_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines */ +#define QSPI_ADDR_PROTOCOL_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Data_Protocol QSPI Data Protocol + * @{ + */ +#define QSPI_DATA_PROTOCOL_1LINE (0x0U) /*!< Data on 1 line */ +#define QSPI_DATA_PROTOCOL_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines */ +#define QSPI_DATA_PROTOCOL_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_WP_Pin_Level QSPI WP Pin Level + * @{ + */ +#define QSPI_WP_PIN_LOW (0x0U) /*!< WP(QSIO2) pin output low */ +#define QSPI_WP_PIN_HIGH (QSPI_FCR_WPOL) /*!< WP(QSIO2) pin output high */ +/** + * @} + */ + +/** + * @defgroup QSPI_Direct_Comm_Protocol QSPI Direct Communication Protocol + * @{ + */ +#define QSPI_DIRECT_COMM_PROTOCOL_1LINE (0x0U) /*!< Direct communication protocol on 1 line */ +#define QSPI_DIRECT_COMM_PROTOCOL_2LINE (QSPI_DCOM_DCOMPRSL_0) /*!< Direct communication protocol on 2 lines */ +#define QSPI_DIRECT_COMM_PROTOCOL_4LINE (QSPI_DCOM_DCOMPRSL_1) /*!< Direct communication protocol on 4 lines */ +/** + * @} + */ + +/** + * @defgroup QSPI_Status_Flag QSPI Status Flag + * @{ + */ +#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed */ +#define QSPI_FLAG_XIP_MD (QSPI_SR_XIPF) /*!< XIP mode */ +#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode */ +#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full */ +#define QSPI_FLAG_PREFETCH_STOP (QSPI_SR_PFAN) /*!< Prefetch function operating */ + +#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | QSPI_FLAG_XIP_MD | \ + QSPI_FLAG_ROM_ACCESS_ERR | QSPI_FLAG_PREFETCH_BUF_FULL | \ + QSPI_FLAG_PREFETCH_STOP) +#define QSPI_FLAG_CLR_ALL (QSPI_FLAG_ROM_ACCESS_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup QSPI_Global_Functions + * @{ + */ + +/** + * @brief Read data in direct communication mode. + * @param None + * @retval uint8_t Byte data. + */ +__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void) +{ + return (uint8_t)CM_QSPI->DCOM; +} + +/* Initialization and configuration functions */ +int32_t QSPI_DeInit(void); +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit); +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit); +void QSPI_SetWpPinLevel(uint32_t u32Level); +void QSPI_SetPrefetchMode(uint32_t u32Mode); +void QSPI_SelectMemoryBlock(uint8_t u8Block); +void QSPI_SetReadMode(uint32_t u32Mode); +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode); +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void QSPI_EnterDirectCommMode(void); +void QSPI_ExitDirectCommMode(void); +void QSPI_WriteDirectCommValue(uint32_t u32Protocol, uint8_t u8Value); +uint8_t QSPI_ReadDirectCommValue(void); + +/* Interrupt and flag management functions */ +uint8_t QSPI_GetPrefetchBufSize(void); +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag); +void QSPI_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h new file mode 100644 index 0000000000..1f254473dd --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rmu.h @@ -0,0 +1,208 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.h + * @brief This file contains all the functions prototypes of the RMU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RMU_H__ +#define __HC32_LL_RMU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RMU + * @{ + */ +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Macros RMU Global Macros + * @{ + */ + +/** + * @defgroup RMU_ResetCause Rmu reset cause + * @{ + */ +#define RMU_FLAG_PWR_ON (RMU_RSTF0_PORF) /*!< Power on reset */ +#define RMU_FLAG_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */ +#define RMU_FLAG_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */ +#define RMU_FLAG_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */ +#define RMU_FLAG_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */ +#define RMU_FLAG_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */ +#define RMU_FLAG_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */ +#define RMU_FLAG_PWR_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */ +#define RMU_FLAG_SW (RMU_RSTF0_SWRF) /*!< Software reset */ +#define RMU_FLAG_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */ +#define RMU_FLAG_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */ +#define RMU_FLAG_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */ +#define RMU_FLAG_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequency error reset */ +#define RMU_FLAG_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */ +#define RMU_FLAG_CPU_LOCKUP (RMU_RSTF0_LKUPRF) /*!< M4 Lockup reset */ +#define RMU_FLAG_MX (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */ +#define RMU_FLAG_ALL (RMU_FLAG_PWR_ON | RMU_FLAG_PIN | RMU_FLAG_BROWN_OUT | RMU_FLAG_PVD1 | \ + RMU_FLAG_PVD2 | RMU_FLAG_WDT | RMU_FLAG_SWDT | RMU_FLAG_PWR_DOWN | \ + RMU_FLAG_SW | RMU_FLAG_MPU_ERR | RMU_FLAG_RAM_PARITY_ERR | RMU_FLAG_RAM_ECC | \ + RMU_FLAG_CLK_ERR | RMU_FLAG_XTAL_ERR | RMU_FLAG_CPU_LOCKUP | RMU_FLAG_MX) + +/** + * @} + */ + +/** + * @defgroup RMU_FRST0_Peripheral RMU FRST0 peripheral + * @{ + */ +#define RMU_FRST0_PERIPH_KEY (RMU_FRST0_KEY) +#define RMU_FRST0_PERIPH_DMA1 (RMU_FRST0_DMA1) +#define RMU_FRST0_PERIPH_DMA2 (RMU_FRST0_DMA2) +#define RMU_FRST0_PERIPH_FCM (RMU_FRST0_FCM) +#define RMU_FRST0_PERIPH_AOS (RMU_FRST0_AOS) +#define RMU_FRST0_PERIPH_CTC (RMU_FRST0_CTC) +#define RMU_FRST0_PERIPH_AES (RMU_FRST0_AES) +#define RMU_FRST0_PERIPH_HASH (RMU_FRST0_HASH) +#define RMU_FRST0_PERIPH_TRNG (RMU_FRST0_TRNG) +#define RMU_FRST0_PERIPH_CRC (RMU_FRST0_CRC) +#define RMU_FRST0_PERIPH_DCU1 (RMU_FRST0_DCU1) +#define RMU_FRST0_PERIPH_DCU2 (RMU_FRST0_DCU2) +#define RMU_FRST0_PERIPH_DCU3 (RMU_FRST0_DCU3) +#define RMU_FRST0_PERIPH_DCU4 (RMU_FRST0_DCU4) +#define RMU_FRST0_PERIPH_ALL (0x0FF7E000UL) +/** + * @} + */ + +/** + * @defgroup RMU_FRST1_Peripheral RMU FRST1 peripheral + * @{ + */ +#define RMU_FRST1_PERIPH_QSPI (RMU_FRST1_QSPI) +#define RMU_FRST1_PERIPH_SPI1 (RMU_FRST1_SPI1) +#define RMU_FRST1_PERIPH_SPI2 (RMU_FRST1_SPI2) +#define RMU_FRST1_PERIPH_SPI3 (RMU_FRST1_SPI3) +#define RMU_FRST1_PERIPH_ALL (0x00070008UL) +/** + * @} + */ + +/** + * @defgroup RMU_FRST2_Peripheral RMU FRST2 peripheral + * @{ + */ +#define RMU_FRST2_PERIPH_TMR6 (RMU_FRST2_TMR6) +#define RMU_FRST2_PERIPH_TMR4 (RMU_FRST2_TMR4) +#define RMU_FRST2_PERIPH_TMR0 (RMU_FRST2_TMR0) +#define RMU_FRST2_PERIPH_EMB (RMU_FRST2_EMB) +#define RMU_FRST2_PERIPH_TMRA (RMU_FRST2_TMRA) +#define RMU_FRST2_PERIPH_ALL (0x00109401UL) +/** + * @} + */ + +/** + * @defgroup RMU_FRST3_Peripheral RMU FRST3 peripheral + * @{ + */ +#define RMU_FRST3_PERIPH_ADC1 (RMU_FRST3_ADC1) +#define RMU_FRST3_PERIPH_ADC2 (RMU_FRST3_ADC2) +#define RMU_FRST3_PERIPH_ADC3 (RMU_FRST3_ADC3) +#define RMU_FRST3_PERIPH_DAC (RMU_FRST3_DAC) +#define RMU_FRST3_PERIPH_CMP1_2 (RMU_FRST3_CMP12) +#define RMU_FRST3_PERIPH_CMP3_4 (RMU_FRST3_CMP34) +#define RMU_FRST3_PERIPH_SMC (RMU_FRST3_SMC) +#define RMU_FRST3_PERIPH_USART1 (RMU_FRST3_USART1) +#define RMU_FRST3_PERIPH_USART2 (RMU_FRST3_USART2) +#define RMU_FRST3_PERIPH_USART3 (RMU_FRST3_USART3) +#define RMU_FRST3_PERIPH_USART4 (RMU_FRST3_USART4) +#define RMU_FRST3_PERIPH_USART5 (RMU_FRST3_USART5) +#define RMU_FRST3_PERIPH_USART6 (RMU_FRST3_USART6) +#define RMU_FRST3_PERIPH_ALL (0x03F10317UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RMU_Global_Functions + * @{ + */ + +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause); +void RMU_ClearStatus(void); + +void RMU_CPULockUpCmd(en_functional_state_t enNewState); + +int32_t RMU_Frst0PeriphReset(uint32_t u32Frst0Periph); +int32_t RMU_Frst1PeriphReset(uint32_t u32Frst1Periph); +int32_t RMU_Frst2PeriphReset(uint32_t u32Frst2Periph); +int32_t RMU_Frst3PeriphReset(uint32_t u32Frst3Periph); + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h new file mode 100644 index 0000000000..3862c137c7 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_rtc.h @@ -0,0 +1,366 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.h + * @brief This file contains all the functions prototypes of the RTC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_RTC_H__ +#define __HC32_LL_RTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_RTC + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Types RTC Global Types + * @{ + */ + +/** + * @brief RTC Init structure definition + */ +typedef struct { + uint8_t u8ClockSrc; /*!< Specifies the RTC clock source. + This parameter can be a value of @ref RTC_Clock_Source */ + uint8_t u8HourFormat; /*!< Specifies the RTC hour format. + This parameter can be a value of @ref RTC_Hour_Format */ + uint8_t u8IntPeriod; /*!< Specifies the RTC interrupt period. + This parameter can be a value of @ref RTC_Interrupt_Period */ + uint8_t u8ClockCompen; /*!< Specifies the validity of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation */ + uint8_t u8CompenMode; /*!< Specifies the mode of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation_Mode */ + uint16_t u16CompenValue; /*!< Specifies the value of RTC clock compensation. + This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */ +} stc_rtc_init_t; + +/** + * @brief RTC Date structure definition + */ +typedef struct { + uint8_t u8Year; /*!< Specifies the RTC Year. + This parameter can be a number between Min_Data = 0 and Max_Data = 99 */ + uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format). + This parameter can be a value of @ref RTC_Month */ + uint8_t u8Day; /*!< Specifies the RTC Day. + This parameter can be a number between Min_Data = 1 and Max_Data = 31 */ + uint8_t u8Weekday; /*!< Specifies the RTC Weekday. + This parameter can be a value of @ref RTC_Weekday */ +} stc_rtc_date_t; + +/** + * @brief RTC Time structure definition + */ +typedef struct { + uint8_t u8Hour; /*!< Specifies the RTC Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8Minute; /*!< Specifies the RTC Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8Second; /*!< Specifies the RTC Second. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_time_t; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct { + uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FMT_12H is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FMT_24H is selected */ + uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday. + This parameter can be a value of @ref RTC_Alarm_Weekday */ + uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FMT_12H mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_alarm_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Macros RTC Global Macros + * @{ + */ + +/** + * @defgroup RTC_Data_Format RTC Data Format + * @{ + */ +#define RTC_DATA_FMT_DEC (0x00U) /*!< Decimal data format */ +#define RTC_DATA_FMT_BCD (0x01U) /*!< BCD data format */ +/** + * @} + */ + +/** + * @defgroup RTC_Decimal_BCD_Conversion RTC Decimal BCD Conversion + * @{ + */ +#define RTC_DEC2BCD(__DATA__) ((((__DATA__) / 10U) << 4U) + ((__DATA__) % 10U)) +#define RTC_BCD2DEC(__DATA__) ((((__DATA__) >> 4U) * 10U) + ((__DATA__) & 0x0FU)) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RTC_CLK_SRC_XTAL32 (0U) /*!< XTAL32 Clock */ +#define RTC_CLK_SRC_LRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */ +#define RTC_CLK_SRC_XTAL_DIV (RTC_CR3_RCKSEL | PWC_PWRC6_RTCCKSEL_0) /*!< XTAL Fractional Divider */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour_Format RTC Hour Format + * @{ + */ +#define RTC_HOUR_FMT_12H (0U) /*!< 12 hour time system */ +#define RTC_HOUR_FMT_24H (RTC_CR1_AMPM) /*!< 24 hour time system */ +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt_Period RTC Interrupt Period + * @{ + */ +#define RTC_INT_PERIOD_INVD (0U) /*!< Interrupt period invalid */ +#define RTC_INT_PERIOD_PER_HALF_SEC (0x01U << RTC_CR1_PRDS_POS) /*!< Interrupt period per half second */ +#define RTC_INT_PERIOD_PER_SEC (0x02U << RTC_CR1_PRDS_POS) /*!< Interrupt period per second */ +#define RTC_INT_PERIOD_PER_MINUTE (0x03U << RTC_CR1_PRDS_POS) /*!< Interrupt period per minute */ +#define RTC_INT_PERIOD_PER_HOUR (0x04U << RTC_CR1_PRDS_POS) /*!< Interrupt period per hour */ +#define RTC_INT_PERIOD_PER_DAY (0x05U << RTC_CR1_PRDS_POS) /*!< Interrupt period per day */ +#define RTC_INT_PERIOD_PER_MONTH (0x06U << RTC_CR1_PRDS_POS) /*!< Interrupt period per month */ +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation RTC Clock Compensation + * @{ + */ +#define RTC_CLK_COMPEN_DISABLE (0U) +#define RTC_CLK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN) +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation_Mode RTC Clock Compensation Mode + * @{ + */ +#define RTC_CLK_COMPEN_MD_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */ +#define RTC_CLK_COMPEN_MD_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM + * @{ + */ +#define RTC_HOUR_24H (0U) /*!< 24-hour format */ +#define RTC_HOUR_12H_AM (0U) /*!< AM in 12-hour */ +#define RTC_HOUR_12H_PM (RTC_HOUR_HOURD_1) /*!< PM in 12-hour */ +/** + * @} + */ + +/** + * @defgroup RTC_Month RTC Month + * @{ + */ +#define RTC_MONTH_JANUARY (0x01U) +#define RTC_MONTH_FEBRUARY (0x02U) +#define RTC_MONTH_MARCH (0x03U) +#define RTC_MONTH_APRIL (0x04U) +#define RTC_MONTH_MAY (0x05U) +#define RTC_MONTH_JUNE (0x06U) +#define RTC_MONTH_JULY (0x07U) +#define RTC_MONTH_AUGUST (0x08U) +#define RTC_MONTH_SEPTEMBER (0x09U) +#define RTC_MONTH_OCTOBER (0x0AU) +#define RTC_MONTH_NOVEMBER (0x0BU) +#define RTC_MONTH_DECEMBER (0x0CU) +/** + * @} + */ + +/** + * @defgroup RTC_Weekday RTC Weekday + * @{ + */ +#define RTC_WEEKDAY_SUNDAY (0x00U) +#define RTC_WEEKDAY_MONDAY (0x01U) +#define RTC_WEEKDAY_TUESDAY (0x02U) +#define RTC_WEEKDAY_WEDNESDAY (0x03U) +#define RTC_WEEKDAY_THURSDAY (0x04U) +#define RTC_WEEKDAY_FRIDAY (0x05U) +#define RTC_WEEKDAY_SATURDAY (0x06U) +/** + * @} + */ + +/** + * @defgroup RTC_Alarm_Weekday RTC Alarm Weekday + * @{ + */ +#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U) +#define RTC_ALARM_WEEKDAY_MONDAY (0x02U) +#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U) +#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U) +#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U) +#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U) +#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U) +#define RTC_ALARM_WEEKDAY_EVERYDAY (0x7FU) +/** + * @} + */ + +/** + * @defgroup RTC_Flag RTC Flag + * @{ + */ +#define RTC_FLAG_RD_WR (RTC_CR2_RWEN) /*!< Read and write permission flag */ +#define RTC_FLAG_ALARM (RTC_CR2_ALMF) /*!< Alarm flag */ +#define RTC_FLAG_PERIOD (RTC_CR2_PRDF) /*!< Period flag */ +#define RTC_FLAG_ALL (RTC_FLAG_RD_WR | RTC_FLAG_ALARM | RTC_FLAG_PERIOD) +#define RTC_FLAG_CLR_ALL (RTC_FLAG_ALARM | RTC_FLAG_PERIOD) +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt RTC Interrupt + * @{ + */ +#define RTC_INT_PERIOD (RTC_CR2_PRDIE) /*!< Period interrupt */ +#define RTC_INT_ALARM (RTC_CR2_ALMIE) /*!< Alarm interrupt */ +#define RTC_INT_ALL (RTC_INT_PERIOD | RTC_INT_ALARM) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RTC_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +int32_t RTC_DeInit(void); +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit); +int32_t RTC_EnterRwMode(void); +int32_t RTC_ExitRwMode(void); + +/* Control configuration */ +int32_t RTC_ConfirmLPMCond(void); +void RTC_SetIntPeriod(uint8_t u8Period); +void RTC_SetClockSrc(uint8_t u8Src); +void RTC_SetClockCompenValue(uint16_t u16Value); +en_functional_state_t RTC_GetCounterState(void); +void RTC_Cmd(en_functional_state_t enNewState); +void RTC_LrcCmd(en_functional_state_t enNewState); +void RTC_OneHzOutputCmd(en_functional_state_t enNewState); +void RTC_ClockCompenCmd(en_functional_state_t enNewState); + +/* Date and time functions */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); + +/* Alarm configuration functions */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +void RTC_AlarmCmd(en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t RTC_GetStatus(uint32_t u32Flag); +void RTC_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_smc.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_smc.h new file mode 100644 index 0000000000..0e5d477528 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_smc.h @@ -0,0 +1,361 @@ +/** + ******************************************************************************* + * @file hc32_ll_smc.h + * @brief This file contains all the functions prototypes of the EXMC_SMC + * (External Memory Controller: Static Memory Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SMC_H__ +#define __HC32_LL_SMC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_EXMC + * @{ + */ + +/** + * @addtogroup LL_SMC + * @{ + */ + +#if (LL_SMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Types EXMC_SMC Global Types + * @{ + */ + +/** + * @brief EXMC_SMC Chip Configuration Structure definition + */ +typedef struct { + uint32_t u32ReadMode; /*!< Defines the read sync enable. + This parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode */ + uint32_t u32WriteMode; /*!< Defines the write sync enable. + This parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode */ + uint32_t u32MemoryWidth; /*!< Defines the SMC memory width. + This parameter can be a value of @ref EXMC_SMC_Memory_Width. */ + uint32_t u32BAA; /*!< Defines the SMC BAA signal enable. + This parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection. */ + uint32_t u32ADV; /*!< Defines the SMC ADVS signal enable. + This parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection. */ + uint32_t u32BLS; /*!< Defines the SMC BLS signal selection. + This parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection. */ + uint32_t u32AddrMatch; /*!< Defines the address match. + This parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F */ + uint32_t u32AddrMask; /*!< Defines the address mask. + This parameter can be a value of @ref EXMC_SMC_Mask_Address. */ +} stc_exmc_smc_chip_config_t; + +/** + * @brief EXMC_SMC Timing Configuration Structure definition + */ +typedef struct { + uint8_t u8RC; /*!< Defines the RC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint8_t u8WC; /*!< Defines the WC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint8_t u8CEOE; /*!< Defines the CEOE in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8WP; /*!< Defines the WP in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8TR; /*!< Defines the TR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint8_t u8ADV; /*!< Defines the ADV in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ +} stc_exmc_smc_timing_config_t; + +/** + * @brief EXMC_SMC Initialization Structure definition + */ +typedef struct { + stc_exmc_smc_chip_config_t stcChipConfig; /*!< SMC memory chip configure. + This structure details refer @ref stc_exmc_smc_chip_config_t. */ + stc_exmc_smc_timing_config_t stcTimingConfig; /*!< SMC memory timing configure. + This structure details refer @ref stc_exmc_smc_timing_config_t. */ +} stc_exmc_smc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Macros EXMC_SMC Global Macros + * @{ + */ + +/** + * @defgroup EXMC_SMC_Chip EXMC_SMC Chip + * @{ + */ +#define EXMC_SMC_CHIP0 (0UL) /*!< Chip 0 */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Read_Mode EXMC_SMC Memory Read Mode + * @{ + */ +#define EXMC_SMC_READ_ASYNC (0UL) +#define EXMC_SMC_READ_SYNC (SMC_CPCR_RSYN) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Write_Mode EXMC_SMC Memory Write Mode + * @{ + */ +#define EXMC_SMC_WRITE_ASYNC (0UL) +#define EXMC_SMC_WRITE_SYNC (SMC_CPCR_WSYN) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Width EXMC_SMC Memory Width + * @{ + */ +#define EXMC_SMC_MEMORY_WIDTH_8BIT (0UL) +#define EXMC_SMC_MEMORY_WIDTH_16BIT (SMC_CPCR_MW_0) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_BAA_Port_Selection EXMC_SMC BAA Port Selection + * @{ + */ +#define EXMC_SMC_BAA_PORT_DISABLE (0UL) +#define EXMC_SMC_BAA_PORT_ENABLE (SMC_CPCR_BAAS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_ADV_Port_Selection EXMC_SMC ADV Port Selection + * @{ + */ +#define EXMC_SMC_ADV_PORT_DISABLE (0UL) +#define EXMC_SMC_ADV_PORT_ENABLE (SMC_CPCR_ADVS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_BLS_Synchronization_Selection EXMC_SMC BLS Synchronization Selection + * @{ + */ +#define EXMC_SMC_BLS_SYNC_CS (0UL) +#define EXMC_SMC_BLS_SYNC_WE (SMC_CPCR_BLSS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Command EXMC_SMC Command + * @{ + */ +#define EXMC_SMC_CMD_MDREGCONFIG (SMC_CMDR_CMD_0) /*!< Command: MdRetConfig */ +#define EXMC_SMC_CMD_UPDATEREGS (SMC_CMDR_CMD_1) /*!< Command: UpdateRegs */ +#define EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS (SMC_CMDR_CMD) /*!< Command: MdRetConfig & UpdateRegs */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_CRE_Polarity EXMC_SMC CRE Polarity + * @{ + */ +#define EXMC_SMC_CRE_POLARITY_LOW (0UL) /*!< CRE is LOW */ +#define EXMC_SMC_CRE_POLARITY_HIGH (SMC_CMDR_CRES) /*!< CRE is HIGH when ModeReg write occurs */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Status EXMC_SMC Status + * @{ + */ +#define EXMC_SMC_READY (0UL) /*!< SMC is ready */ +#define EXMC_SMC_LOWPOWER (SMC_STSR_STATUS) /*!< SMC is low power */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Sample_Clock EXMC_SMC Sample Clock + * @{ + */ +#define EXMC_SMC_SAMPLE_CLK_INTERNCLK (0UL) /*!< Internal EXCLK */ +#define EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT (SMC_BACR_CKSEL_0) /*!< Invert internal EXCLK */ +#define EXMC_SMC_SAMPLE_CLK_EXTCLK (SMC_BACR_CKSEL_1) /*!< External clock from EXMC_CLK port */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Mask_Address EXMC_SMC Mask Address + * @{ + */ +#define EXMC_SMC_ADDR_MASK_16MB (0xFFUL) +#define EXMC_SMC_ADDR_MASK_32MB (0xFEUL) +#define EXMC_SMC_ADDR_MASK_64MB (0xFCUL) +#define EXMC_SMC_ADDR_MASK_128MB (0xF8UL) +#define EXMC_SMC_ADDR_MASK_256MB (0xF0UL) +#define EXMC_SMC_ADDR_MASK_512MB (0xE0UL) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Address_Space EXMC_SMC Address Space + * @{ + */ +#define EXMC_SMC_ADDR_MIN (0x60000000UL) +#define EXMC_SMC_ADDR_MAX (0x7FFFFFFFUL) +/** + * @} + */ + +/** + * @brief SMC device memory address shifting. + * @param [in] mem_base_addr SMC base address + * @param [in] mem_width SMC memory width + * @param [in] addr SMC device memory address + * @retval SMC device shifted address value + */ +#define SMC_ADDR_SHIFT(mem_base_addr, mem_width, addr) \ +( ((EXMC_SMC_MEMORY_WIDTH_16BIT == (mem_width))? (((mem_base_addr) + ((addr) << 1U))) : \ + (((mem_base_addr) + ((addr) << 2U))))) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EXMC_SMC_Global_Functions + * @{ + */ + +/** + * @brief SMC entry low power state + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_SMC_EntryLowPower(void) +{ + WRITE_REG32(CM_SMC->STCR0, SMC_STCR0_LPWIR); +} + +/** + * @brief SMC exit low power state + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_SMC_ExitLowPower(void) +{ + WRITE_REG32(CM_SMC->STCR1, SMC_STCR1_LPWOR); +} + +/** + * @brief Get SMC status + * @param None + * @retval Returned value can be one of the macros group @ref EXMC_SMC_Status + * - EXMC_SMC_READY: SMC is ready + * - EXMC_SMC_LOWPOWER: SMC is low power + */ +__STATIC_INLINE uint32_t EXMC_SMC_GetStatus(void) +{ + return READ_REG32_BIT(CM_SMC->STSR, SMC_STSR_STATUS); +} + +/* Initialization and configuration EXMC_SMC functions */ +int32_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcSmcInit); +int32_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcSmcInit); +int32_t EXMC_SMC_DeInit(void); + +void EXMC_SMC_Cmd(en_functional_state_t enNewState); +void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState); +void EXMC_SMC_SetSampleClock(uint32_t u32SampleClock); +void EXMC_SMC_SetRefreshPeriod(uint8_t u8PeriodVal); + +void EXMC_SMC_SetCommand(uint32_t u32Chip, uint32_t u32Cmd, uint32_t u32CrePolarity, uint32_t u32Addr); +uint32_t EXMC_SMC_GetChipStartAddr(uint32_t u32Chip); +uint32_t EXMC_SMC_GetChipEndAddr(uint32_t u32Chip); +int32_t EXMC_SMC_GetChipConfig(uint32_t u32Chip, stc_exmc_smc_chip_config_t *pstcChipConfig); +int32_t EXMC_SMC_GetTimingConfig(uint32_t u32Chip, stc_exmc_smc_timing_config_t *pstcTimingConfig); + +/** + * @} + */ + +#endif /* LL_SMC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SMC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h new file mode 100644 index 0000000000..a0ec506398 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_spi.h @@ -0,0 +1,509 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.h + * @brief This file contains all the functions prototypes of the SPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Rename SPI_FLAG_OVERLOAD as SPI_FLAG_OVERRUN, SPI_FLAG_UNDERLOAD as SPI_FLAG_UNDERRUN + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SPI_H__ +#define __HC32_LL_SPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SPI + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Types SPI Global Types + * @{ + */ + +/** + * @brief Structure definition of SPI initialization. + * @note The parameter u32BaudRatePrescaler is invalid while slave mode + */ +typedef struct { + uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode. + This parameter can be a value of @ref SPI_Wire_Mode_Define */ + uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex. + This parameter can be a value of @ref SPI_Trans_Mode_Define */ + uint32_t u32MasterSlave; /*!< SPI master/slave mode. + This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */ + uint32_t u32ModeFaultDetect; /*!< SPI mode fault detect command. + This parameter can be a value of @ref SPI_Mode_Fault_Detect_Command_Define */ + uint32_t u32Parity; /*!< SPI parity check selection. + This parameter can be a value of @ref SPI_Parity_Check_Define */ + uint32_t u32SpiMode; /*!< SPI mode. + This parameter can be a value of @ref SPI_Mode_Define */ + uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler. + This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */ + uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits. + This parameter can be a value of @ref SPI_Data_Size_Define */ + uint32_t u32FirstBit; /*!< MSB first or LSB first. + This parameter can be a value of @ref SPI_First_Bit_Define */ + uint32_t u32SuspendMode; /*!< SPI communication suspend function. + This parameter can be a value of @ref SPI_Com_Suspend_Func_Define */ + uint32_t u32FrameLevel; /*!< SPI frame level, SPI_1_FRAME ~ SPI_4_FRAME. + This parameter can be a value of @ref SPI_Frame_Level_Define */ +} stc_spi_init_t; + +/** + * @brief Structure definition of SPI delay time configuration. + */ +typedef struct { + uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time) + This parameter can be a value of @ref SPI_Interval_Delay_Time_define */ + uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time) + This parameter can be a value of @ref SPI_Release_Delay_Time_define */ + uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define + This parameter can be a value of @ref SPI_Setup_Delay_Time_define */ +} stc_spi_delay_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Macros SPI Global Macros + * @{ + */ + +/** + * @defgroup SPI_Wire_Mode_Define SPI Wire Mode Define + * @{ + */ +#define SPI_4_WIRE (0UL) +#define SPI_3_WIRE (SPI_CR_SPIMDS) +/** + * @} + */ + +/** + * @defgroup SPI_Trans_Mode_Define SPI Transfer Mode Define + * @{ + */ +#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */ +#define SPI_SEND_ONLY (SPI_CR_TXMDS) /*!< Send only. */ +/** + * @} + */ + +/** + * @defgroup SPI_Master_Slave_Mode_Define SPI Master Slave Mode Define + * @{ + */ +#define SPI_SLAVE (0UL) +#define SPI_MASTER (SPI_CR_MSTR) +/** + * @} + */ + +/** + * @defgroup SPI_Loopback_Selection_Define SPI Loopback Selection Define + * @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode. + * @{ + */ +#define SPI_LOOPBACK_INVD (0UL) +#define SPI_LOOPBACK_MOSI_INVT (SPI_CR_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */ +#define SPI_LOOPBACK_MOSI (SPI_CR_SPLPBK2) /*!< MISO data is the data output by MOSI. */ +/** + * @} + */ + +/** + * @defgroup SPI_Int_Type_Define SPI Interrupt Type Define + * @{ + */ +#define SPI_INT_ERR (SPI_CR_EIE) /*!< Including overload, underload and parity error. */ +#define SPI_INT_TX_BUF_EMPTY (SPI_CR_TXIE) +#define SPI_INT_RX_BUF_FULL (SPI_CR_RXIE) +#define SPI_INT_IDLE (SPI_CR_IDIE) +#define SPI_INT_ALL (SPI_INT_ERR | SPI_INT_TX_BUF_EMPTY | SPI_INT_RX_BUF_FULL | SPI_INT_IDLE ) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Fault_Detect_Command_Define SPI Mode Fault Detect Command Define + * @{ + */ +#define SPI_MD_FAULT_DETECT_DISABLE (0UL) /*!< Disable mode fault detection. */ +#define SPI_MD_FAULT_DETECT_ENABLE (SPI_CR_MODFE) /*!< Enable mode fault detection. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Define SPI Parity Check Mode Define + * @{ + */ +#define SPI_PARITY_INVD (0UL) /*!< Parity check invalid. */ +#define SPI_PARITY_EVEN (SPI_CR_PAE) /*!< Parity check selection even parity. */ +#define SPI_PARITY_ODD (SPI_CR_PAE | SPI_CR_PAOE) /*!< Parity check selection odd parity. */ +/** + * @} + */ + +/** + * @defgroup SPI_SS_Pin_Define SPI SSx Define + * @{ + */ +#define SPI_PIN_SS0 (SPI_CFG1_SS0PV) +#define SPI_PIN_SS1 (SPI_CFG1_SS1PV) +#define SPI_PIN_SS2 (SPI_CFG1_SS2PV) +#define SPI_PIN_SS3 (SPI_CFG1_SS3PV) +/** + * @} + */ + +/** + * @defgroup SPI_SS_Level SPI SS pin valid level + * @{ + */ +#define SPI_SS_VALID_LVL_HIGH (1UL) +#define SPI_SS_VALID_LVL_LOW (0UL) +/** + * @} + */ + +/** + * @defgroup SPI_Read_Target_Buf_Define SPI Read Data Register Target Buffer Define + * @{ + */ +#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */ +#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */ +/** + * @} + */ + +/** + * @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the SPI_DR register will be send to TX_BUFF + * after enough data frame write to the SPI_DR + * @{ + */ +#define SPI_1_FRAME (0UL) /*!< Data 1 frame */ +#define SPI_2_FRAME (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/ +#define SPI_3_FRAME (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/ +#define SPI_4_FRAME (SPI_CFG1_FTHLV) /*!< Data 4 frame.*/ +/** + * @} + */ + +/** + * @defgroup SPI_Interval_Delay_Time_define SPI Interval Time Delay (Next Access Delay Time) define + * @{ + */ +#define SPI_INTERVAL_TIME_1SCK (0UL << SPI_CFG1_MIDI_POS) /*!< 1 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_2SCK (1UL << SPI_CFG1_MIDI_POS) /*!< 2 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_3SCK (2UL << SPI_CFG1_MIDI_POS) /*!< 3 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_4SCK (3UL << SPI_CFG1_MIDI_POS) /*!< 4 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_5SCK (4UL << SPI_CFG1_MIDI_POS) /*!< 5 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_6SCK (5UL << SPI_CFG1_MIDI_POS) /*!< 6 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_7SCK (6UL << SPI_CFG1_MIDI_POS) /*!< 7 SCK + 2 PCLK1 */ +#define SPI_INTERVAL_TIME_8SCK (7UL << SPI_CFG1_MIDI_POS) /*!< 8 SCK + 2 PCLK1 */ +/** + * @} + */ + +/** + * @defgroup SPI_Release_Delay_Time_define SPI Release Time Delay (SCK Invalid Delay Time) Define + * @{ + */ +#define SPI_RELEASE_TIME_1SCK (0UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_2SCK (1UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_3SCK (2UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_4SCK (3UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_5SCK (4UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_6SCK (5UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_7SCK (6UL << SPI_CFG1_MSSDL_POS) +#define SPI_RELEASE_TIME_8SCK (7UL << SPI_CFG1_MSSDL_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Setup_Delay_Time_define SPI Setup Time Delay (SCK Valid Delay Time) Define + * @{ + */ +#define SPI_SETUP_TIME_1SCK (0UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_2SCK (1UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_3SCK (2UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_4SCK (3UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_5SCK (4UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_6SCK (5UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_7SCK (6UL << SPI_CFG1_MSSI_POS) +#define SPI_SETUP_TIME_8SCK (7UL << SPI_CFG1_MSSI_POS) +/** + * @} + */ + +/** + * @defgroup SPI_Com_Suspend_Func_Define SPI Communication Suspend Function Define + * @{ + */ +#define SPI_COM_SUSP_FUNC_OFF (0UL) +#define SPI_COM_SUSP_FUNC_ON (SPI_CR_CSUSPE) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Define SPI Mode Define + * @{ + */ +#define SPI_MD_0 (0UL) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_1 (SPI_CFG2_CPHA) /*!< SCK pin output low in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ +#define SPI_MD_2 (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in odd edge, \ + MOSI/MISO pin data change in even edge */ +#define SPI_MD_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) /*!< SCK pin output high in idle state; \ + MOSI/MISO pin data valid in even edge, \ + MOSI/MISO pin data change in odd edge */ +/** + * @} + */ + +/** + * @defgroup SPI_SCK_Polarity_Define SPI SCK Polarity Define + * @{ + */ +#define SPI_SCK_POLARITY_LOW (0UL) /*!< SCK pin output low in idle state */ +#define SPI_SCK_POLARITY_HIGH (SPI_CFG2_CPOL) /*!< SCK pin output high in idle state */ +/** + * @} + */ + +/** + * @defgroup SPI_SCK_Phase_Define SPI SCK Phase Define + * @{ + */ +#define SPI_SCK_PHASE_ODD_EDGE_SAMPLE (0UL) /*!< MOSI/MISO pin data sample in odd edge, MOSI/MISO pin data change in even edge */ +#define SPI_SCK_PHASE_EVEN_EDGE_SAMPLE (SPI_CFG2_CPHA) /*!< MOSI/MISO pin data sample in even edge, MOSI/MISO pin data change in odd edge */ +/** + * @} + */ + +/** + * @defgroup SPI_Baud_Rate_Prescaler_Define SPI Baudrate Prescaler Define + * @{ + */ +#define SPI_BR_CLK_DIV2 (0UL) /*!< PCLK1 / 2 */ +#define SPI_BR_CLK_DIV4 (1UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 4 */ +#define SPI_BR_CLK_DIV6 (2UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 6 */ +#define SPI_BR_CLK_DIV8 (3UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 8 */ +#define SPI_BR_CLK_DIV10 (4UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 10 */ +#define SPI_BR_CLK_DIV12 (5UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 12 */ +#define SPI_BR_CLK_DIV14 (6UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 14 */ +#define SPI_BR_CLK_DIV16 (7UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 16 */ +#define SPI_BR_CLK_DIV18 (8UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 18 */ +#define SPI_BR_CLK_DIV20 (9UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 20 */ +#define SPI_BR_CLK_DIV22 (10UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 22 */ +#define SPI_BR_CLK_DIV24 (11UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 24 */ +#define SPI_BR_CLK_DIV26 (12UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 26 */ +#define SPI_BR_CLK_DIV28 (13UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 28 */ +#define SPI_BR_CLK_DIV30 (14UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 30 */ +#define SPI_BR_CLK_DIV32 (15UL << SPI_CFG1_CLKDIV_POS) /*!< PCLK1 / 32 */ +#define SPI_BR_CLK_DIV36 ((8UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 36 */ +#define SPI_BR_CLK_DIV40 ((9UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 40 */ +#define SPI_BR_CLK_DIV44 ((10UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 44 */ +#define SPI_BR_CLK_DIV48 ((11UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 48 */ +#define SPI_BR_CLK_DIV52 ((12UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 52 */ +#define SPI_BR_CLK_DIV56 ((13UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 56 */ +#define SPI_BR_CLK_DIV60 ((14UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 60 */ +#define SPI_BR_CLK_DIV64 ((15UL << SPI_CFG1_CLKDIV_POS) | (1UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 64 */ +#define SPI_BR_CLK_DIV72 ((8UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 72 */ +#define SPI_BR_CLK_DIV80 ((9UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 80 */ +#define SPI_BR_CLK_DIV88 ((10UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 88 */ +#define SPI_BR_CLK_DIV96 ((11UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 96 */ +#define SPI_BR_CLK_DIV104 ((12UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 104 */ +#define SPI_BR_CLK_DIV112 ((13UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 112 */ +#define SPI_BR_CLK_DIV120 ((14UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 120 */ +#define SPI_BR_CLK_DIV128 ((15UL << SPI_CFG1_CLKDIV_POS) | (2UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 128 */ +#define SPI_BR_CLK_DIV144 ((8UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 144 */ +#define SPI_BR_CLK_DIV160 ((9UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 160 */ +#define SPI_BR_CLK_DIV176 ((10UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 176 */ +#define SPI_BR_CLK_DIV192 ((11UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 192 */ +#define SPI_BR_CLK_DIV208 ((12UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 208 */ +#define SPI_BR_CLK_DIV224 ((13UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 224 */ +#define SPI_BR_CLK_DIV240 ((14UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 240 */ +#define SPI_BR_CLK_DIV256 ((15UL << SPI_CFG1_CLKDIV_POS) | (3UL << SPI_CFG2_MBR_POS)) /*!< PCLK1 / 256 */ +/** + * @} + */ + +/** + * @defgroup SPI_Data_Size_Define SPI Data Size Define + * @{ + */ +#define SPI_DATA_SIZE_4BIT (0UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_5BIT (1UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_6BIT (2UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_7BIT (3UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_8BIT (4UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_9BIT (5UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_10BIT (6UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_11BIT (7UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_12BIT (8UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_13BIT (9UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_14BIT (10UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_15BIT (11UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_16BIT (12UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_20BIT (13UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_24BIT (14UL << SPI_CFG2_DSIZE_POS) +#define SPI_DATA_SIZE_32BIT (15UL << SPI_CFG2_DSIZE_POS) + +/** + * @} + */ + +/** + * @defgroup SPI_First_Bit_Define SPI First Bit Define + * @{ + */ +#define SPI_FIRST_MSB (0UL) +#define SPI_FIRST_LSB (SPI_CFG2_LSBF) +/** + * @} + */ + +/** + * @defgroup SPI_Comm_Mode_Define SPI communication mode Define + * @{ + */ +#define SPI_COMM_MD_NORMAL (0UL) /*!< Normal communication mode */ +#define SPI_COMM_MD_CONT (SPI_CFG1_CTMDS) /*!< Continuous communication mode */ +/** + * @} + */ + +/** + * @defgroup SPI_State_Flag_Define SPI State Flag Define + * @{ + */ +#define SPI_FLAG_OVERRUN (SPI_SR_OVRERF) +#define SPI_FLAG_IDLE (SPI_SR_IDLNF) +#define SPI_FLAG_MD_FAULT (SPI_SR_MODFERF) +#define SPI_FLAG_PARITY_ERR (SPI_SR_PERF) +#define SPI_FLAG_UNDERRUN (SPI_SR_UDRERF) +#define SPI_FLAG_TX_BUF_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \ + is copied into the shift register, but the transmission \ + of the data bit may not have been completed. */ +#define SPI_FLAG_RX_BUF_FULL (SPI_SR_RDFF) /*!< Indicates that a data was received. */ +#define SPI_FLAG_CLR_ALL (SPI_FLAG_OVERRUN | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | SPI_FLAG_UNDERRUN) +#define SPI_FLAG_ALL (SPI_FLAG_OVERRUN | SPI_FLAG_IDLE | SPI_FLAG_MD_FAULT | SPI_FLAG_PARITY_ERR | \ + SPI_FLAG_UNDERRUN | SPI_FLAG_TX_BUF_EMPTY | SPI_FLAG_RX_BUF_FULL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SPI_Global_Functions + * @{ + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit); +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit); +int32_t SPI_DeInit(CM_SPI_TypeDef *SPIx); + +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState); +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data); +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx); + +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_SetLoopbackMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode); +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +void SPI_SetSSValidLevel(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, uint32_t u32SSLevel); +void SPI_SetSckPolarity(CM_SPI_TypeDef *SPIx, uint32_t u32Polarity); +void SPI_SetSckPhase(CM_SPI_TypeDef *SPIx, uint32_t u32Phase); + +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig); +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin); +void SPI_SetReadBuf(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf); +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig); + +void SPI_SetCommMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode); + +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout); +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout); +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h new file mode 100644 index 0000000000..6479fa7f2f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_sram.h @@ -0,0 +1,234 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.h + * @brief This file contains all the functions prototypes of the SRAM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + 2023-12-15 CDT Refine def group SRAM_ECC_Mode, and refine def group SRAM_Err_Mode as SRAM_Exception_Type + Remove wait cycle relevant code + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SRAM_H__ +#define __HC32_LL_SRAM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SRAM + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Macros SRAM Global Macros + * @{ + */ + +/** + * @defgroup SRAM_Sel SRAM Selection + * @{ + */ +#define SRAM_SRAMH (1UL << 1U) /*!< SRAMH: 0x1FFF8000~0x1FFFFFFF, 32KB */ +#define SRAM_SRAM0 (1UL << 0U) /*!< SRAM0: 0x20000000~0x20007FFF, 32KB */ +#define SRAM_SRAMB (1UL << 2U) /*!< SRAMB: 0x200F0000~0x200F0FFF, 4KB */ +#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM0 | SRAM_SRAMB) +/** + * @} + */ + +/** + * @defgroup SRAM_ECC_SRAM ECC SRAM Definition + * @{ + */ +#define SRAM_ECC_SRAM0 (1UL << 0U) +#define SRAM_ECC_SRAMB (1UL << 1U) +#define SRAM_ECC_SRAM_ALL (SRAM_ECC_SRAM0 | SRAM_ECC_SRAMB) +/** + * @} + */ + +/** + * @defgroup SRAM_Exception_Type SRAM exception type + * @note Even-parity check error, ECC check error. + * @{ + */ +#define SRAM_EXP_TYPE_NMI (0UL) +#define SRAM_EXP_TYPE_RST (1UL) +/** + * @} + */ + +/** + * @defgroup SRAM_Check_SRAM SRAM check sram + * @{ + */ +#define SRAM_CHECK_SRAM0 (SRAMC_CKCR_ECCOAD) +#define SRAM_CHECK_SRAMB (SRAMC_CKCR_BECCOAD) +#define SRAM_CHECK_SRAMH (SRAMC_CKCR_PYOAD) +#define SRAM_CHECK_SRAM_ALL (SRAM_CHECK_SRAM0 | SRAM_CHECK_SRAMB | SRAM_CHECK_SRAMH) +/** + * @} + */ + +/** + * @defgroup SRAM_ECC_Mode SRAM ECC Mode + * @note XX_INVD: The ECC mode is invalid + * XX_MD1: When 1-bit error occurs, ECC error corrects. No 1-bit-error status flag setting, no interrupt or reset. + * When 2-bit error occurs, ECC error detects. 2-bit-error status flag sets and interrupt or reset occurs. + * XX_MD2: When 1-bit error occurs, ECC error corrects. 1-bit-error status flag sets, no interrupt or reset. + * When 2-bit error occurs, ECC error detects. 2-bit-error status flag sets and interrupt or reset occurs. + * XX_MD3: When 1-bit error occurs, ECC error corrects. 1-bit-error status flag sets and interrupt or reset occurs. + * When 2-bit error occurs, ECC error detects. 2-bit-error status flag sets and interrupt or reset occurs. + * @{ + */ +#define SRAM_SRAM0_ECC_INVD (0xFCFFFFFFUL) /*!< ~SRAMC_CKCR_ECCMOD */ +#define SRAM_SRAM0_ECC_MD1 (SRAMC_CKCR_ECCMOD_0) +#define SRAM_SRAM0_ECC_MD2 (SRAMC_CKCR_ECCMOD_1) +#define SRAM_SRAM0_ECC_MD3 (SRAMC_CKCR_ECCMOD) +#define SRAM_SRAMB_ECC_INVD (0xF3FFFFFFUL) /*!< ~SRAMC_CKCR_BECCMOD */ +#define SRAM_SRAMB_ECC_MD1 (SRAMC_CKCR_BECCMOD_0) +#define SRAM_SRAMB_ECC_MD2 (SRAMC_CKCR_BECCMOD_1) +#define SRAM_SRAMB_ECC_MD3 (SRAMC_CKCR_BECCMOD) +#define SRAM_ECC_MD_INVD (SRAM_SRAM0_ECC_INVD & SRAM_SRAMB_ECC_INVD) +/** + * @} + */ + +/** + * @defgroup SRAM_Err_Status_Flag SRAM Error Status Flag + * @{ + */ +#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */ +#define SRAM_FLAG_SRAM0_1ERR (SRAMC_CKSR_SRAM0_1ERR) /*!< SRAM0 ECC 1-bit error. */ +#define SRAM_FLAG_SRAM0_2ERR (SRAMC_CKSR_SRAM0_2ERR) /*!< SRAM0 ECC 2-bit error. */ +#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */ +#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */ +#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */ +#define SRAM_FLAG_ALL (0x1F8UL) + +/** + * @} + */ + +/** + * @defgroup SRAM_Reg_Protect_Key SRAM Register Protect Key + * @{ + */ +#define SRAM_REG_LOCK_KEY (0x76U) +#define SRAM_REG_UNLOCK_KEY (0x77U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SRAM_Global_Functions + * @{ + */ + +/** + * @brief Lock SRAM registers, write protect. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Lock(void) +{ + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_LOCK_KEY); +} + +/** + * @brief Unlock SRAM registers, write enable. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_REG_Unlock(void) +{ + WRITE_REG32(CM_SRAMC->CKPR, SRAM_REG_UNLOCK_KEY); +} + +void SRAM_Init(void); +void SRAM_DeInit(void); + +void SRAM_REG_Lock(void); +void SRAM_REG_Unlock(void); + +void SRAM_SetEccMode(uint32_t u32EccSram, uint32_t u32EccMode); +void SRAM_SetExceptionType(uint32_t u32CheckSram, uint32_t u32ExceptionType); + +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag); +void SRAM_ClearStatus(uint32_t u32Flag); + +void SRAM_ErrorInjectCmd(uint32_t u32EccSram, en_functional_state_t enNewState); +void SRAM_ErrorInjectBitCmd(uint32_t u32EccSram, uint64_t u64BitSel, en_functional_state_t enNewState); +uint32_t SRAM_GetEccErrorAddr(uint32_t u32EccSram); + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SRAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h new file mode 100644 index 0000000000..eb2ee72c8c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_swdt.h @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.h + * @brief This file contains all the functions prototypes of the SWDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Modify macro define: SWDT_LPM_CNT_CONTINUE -> SWDT_LPM_CNT_CONT + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_SWDT_H__ +#define __HC32_LL_SWDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_SWDT + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Types SWDT Global Types + * @{ + */ + +/** + * @brief SWDT Init structure definition + */ +typedef struct { + uint32_t u32CountPeriod; /*!< Specifies the counting period of SWDT. + This parameter can be a value of @ref SWDT_Count_Period */ + uint32_t u32ClockDiv; /*!< Specifies the clock division factor of SWDT. + This parameter can be a value of @ref SWDT_Clock_Division */ + uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of SWDT. + This parameter can be a value of @ref SWDT_Refresh_Range */ + uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep/Stop Mode). + This parameter can be a value of @ref SWDT_LPM_Count */ + uint32_t u32ExceptionType; /*!< Specifies the type of exception response for SWDT. + This parameter can be a value of @ref SWDT_Exception_Type */ +} stc_swdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Macros SWDT Global Macros + * @{ + */ + +/** + * @defgroup SWDT_Count_Period SWDT Count Period + * @{ + */ +#define SWDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define SWDT_CNT_PERIOD4096 (SWDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define SWDT_CNT_PERIOD16384 (SWDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define SWDT_CNT_PERIOD65536 (SWDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup SWDT_Clock_Division SWDT Clock Division + * @{ + */ +#define SWDT_CLK_DIV1 (0UL) /*!< SWDTCLK/1 */ +#define SWDT_CLK_DIV16 (0x04UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/16 */ +#define SWDT_CLK_DIV32 (0x05UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/32 */ +#define SWDT_CLK_DIV64 (0x06UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/64 */ +#define SWDT_CLK_DIV128 (0x07UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/128 */ +#define SWDT_CLK_DIV256 (0x08UL << SWDT_CR_CKS_POS) /*!< SWDTCLK/256 */ +#define SWDT_CLK_DIV2048 (0x0BUL << SWDT_CR_CKS_POS) /*!< SWDTCLK/2048 */ +/** + * @} + */ + +/** + * @defgroup SWDT_Refresh_Range SWDT Refresh Range + * @{ + */ +#define SWDT_RANGE_0TO25PCT (0x01UL << SWDT_CR_WDPT_POS) /*!< 0%~25% */ +#define SWDT_RANGE_25TO50PCT (0x02UL << SWDT_CR_WDPT_POS) /*!< 25%~50% */ +#define SWDT_RANGE_0TO50PCT (0x03UL << SWDT_CR_WDPT_POS) /*!< 0%~50% */ +#define SWDT_RANGE_50TO75PCT (0x04UL << SWDT_CR_WDPT_POS) /*!< 50%~75% */ +#define SWDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */ +#define SWDT_RANGE_25TO75PCT (0x06UL << SWDT_CR_WDPT_POS) /*!< 25%~75% */ +#define SWDT_RANGE_0TO75PCT (0x07UL << SWDT_CR_WDPT_POS) /*!< 0%~75% */ +#define SWDT_RANGE_75TO100PCT (0x08UL << SWDT_CR_WDPT_POS) /*!< 75%~100% */ +#define SWDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */ +#define SWDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << SWDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */ +#define SWDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << SWDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */ +#define SWDT_RANGE_50TO100PCT (0x0CUL << SWDT_CR_WDPT_POS) /*!< 50%~100% */ +#define SWDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << SWDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */ +#define SWDT_RANGE_25TO100PCT (0x0EUL << SWDT_CR_WDPT_POS) /*!< 25%~100% */ +#define SWDT_RANGE_0TO100PCT (0x0FUL << SWDT_CR_WDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup SWDT_LPM_Count SWDT Low Power Mode Count + * @brief Counting control of SWDT in sleep/stop mode. + * @{ + */ +#define SWDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep/stop mode */ +#define SWDT_LPM_CNT_STOP (SWDT_CR_SLPOFF) /*!< Stop counting in sleep/stop mode */ +/** + * @} + */ + +/** + * @defgroup SWDT_Exception_Type SWDT Exception Type + * @brief Specifies the exception response when a refresh error or count overflow occurs. + * @{ + */ +#define SWDT_EXP_TYPE_INT (0UL) /*!< SWDT trigger interrupt */ +#define SWDT_EXP_TYPE_RST (SWDT_CR_ITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup SWDT_Flag SWDT Flag + * @{ + */ +#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */ +#define SWDT_FLAG_REFRESH (SWDT_SR_REF) /*!< Refresh error flag */ +#define SWDT_FLAG_ALL (SWDT_SR_UDF | SWDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief Get SWDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t SWDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_SWDT->SR) & SWDT_SR_CNT); +} + +/* Initialization and configuration functions */ +int32_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit); +void SWDT_FeedDog(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag); +int32_t SWDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h new file mode 100644 index 0000000000..60c12f1812 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr0.h @@ -0,0 +1,231 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.h + * @brief This file contains all the functions prototypes of the TMR0 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR0_H__ +#define __HC32_LL_TMR0_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR0 + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Types TMR0 Global Types + * @{ + */ + +/** + * @brief TMR0 initialization structure definition + * @note The 'u32ClockDiv' is invalid when the value of 'u32ClockSrc' is "TMR0_CLK_SRC_SPEC_EVT". + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Specifies the clock source of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Source */ + uint32_t u32ClockDiv; /*!< Specifies the clock division of TMR0 channel. + This parameter can be a value of @ref TMR0_Clock_Division */ + uint32_t u32Func; /*!< Specifies the function of TMR0 channel. + This parameter can be a value of @ref TMR0_Function */ + uint16_t u16CompareValue; /*!< Specifies the compare value of TMR0 channel. + This parameter can be a value of half-word */ +} stc_tmr0_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Macros TMR0 Global Macros + * @{ + */ + +/** + * @defgroup TMR0_Channel TMR0 Channel + * @{ + */ +#define TMR0_CH_A (0UL) +#define TMR0_CH_B (1UL) +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Source TMR0 Clock Source + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + * @{ + */ +#define TMR0_CLK_SRC_INTERN_CLK (0UL) /*!< Internal clock (Synchronous clock) */ +#define TMR0_CLK_SRC_SPEC_EVT (TMR0_BCONR_SYNCLKA) /*!< Specified event (Synchronous clock) */ +#define TMR0_CLK_SRC_LRC (TMR0_BCONR_SYNSA) /*!< LRC (Asynchronous clock) */ +#define TMR0_CLK_SRC_XTAL32 (TMR0_BCONR_ASYNCLKA | TMR0_BCONR_SYNSA) /*!< XTAL32 (Asynchronous clock) */ +/** + * @} + */ + +/** + * @defgroup TMR0_Clock_Division TMR0 Clock Division + * @{ + */ +#define TMR0_CLK_DIV1 (0UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK */ +#define TMR0_CLK_DIV2 (1UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/2 */ +#define TMR0_CLK_DIV4 (2UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/4 */ +#define TMR0_CLK_DIV8 (3UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/8 */ +#define TMR0_CLK_DIV16 (4UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/16 */ +#define TMR0_CLK_DIV32 (5UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/32 */ +#define TMR0_CLK_DIV64 (6UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/64 */ +#define TMR0_CLK_DIV128 (7UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/128 */ +#define TMR0_CLK_DIV256 (8UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/256 */ +#define TMR0_CLK_DIV512 (9UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/512 */ +#define TMR0_CLK_DIV1024 (10UL << TMR0_BCONR_CKDIVA_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR0_Function TMR0 Function + * @{ + */ +#define TMR0_FUNC_CMP (0UL) /*!< Output compare function */ +#define TMR0_FUNC_CAPT (TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) /*!< Input capture function */ +/** + * @} + */ + +/** + * @defgroup TMR0_Interrupt TMR0 Interrupt + * @{ + */ +#define TMR0_INT_CMP_A (TMR0_BCONR_CMENA) +#define TMR0_INT_CMP_B (TMR0_BCONR_CMENB) +#define TMR0_INT_OVF_A (TMR0_BCONR_OVENA) +#define TMR0_INT_OVF_B (TMR0_BCONR_OVENB) +#define TMR0_INT_ALL (TMR0_INT_CMP_A | TMR0_INT_OVF_A | TMR0_INT_CMP_B | TMR0_INT_OVF_B) +/** + * @} + */ + +/** + * @defgroup TMR0_FLAG TMR0 Flag + * @{ + */ +#define TMR0_FLAG_CMP_A (TMR0_STFLR_CMFA) +#define TMR0_FLAG_CMP_B (TMR0_STFLR_CMFB) +#define TMR0_FLAG_REPEAT_CAPT_A (TMR0_STFLR_ICPA) +#define TMR0_FLAG_REPEAT_CAPT_B (TMR0_STFLR_ICPB) +#define TMR0_FLAG_OVF_A (TMR0_STFLR_OVFA) +#define TMR0_FLAG_OVF_B (TMR0_STFLR_OVFB) +#define TMR0_FLAG_ALL (TMR0_FLAG_CMP_A | TMR0_FLAG_CMP_B | TMR0_FLAG_REPEAT_CAPT_A | \ + TMR0_FLAG_REPEAT_CAPT_B | TMR0_FLAG_OVF_A | TMR0_FLAG_OVF_B) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR0_Global_Functions + * @{ + */ + +/* Initialization functions */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x); +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init); +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init); +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); + +/* Control configuration functions */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch); +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src); +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div); +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func); + +/* Hardware trigger Functions */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState); + +/* Interrupt and flag management functions */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR0_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h new file mode 100644 index 0000000000..80e8926f14 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr4.h @@ -0,0 +1,849 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.h + * @brief This file contains all the functions prototypes of the TMR4 + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR4_H__ +#define __HC32_LL_TMR4_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR4 + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Types TMR4 Global Types + * @{ + */ + +/** + * @brief TMR4 Counter function initialization configuration + * @note The TMR4 division(u16ClockDiv) is valid when clock source is the internal clock. + */ +typedef struct { + uint16_t u16ClockSrc; /*!< TMR4 counter clock source. + This parameter can be a value of @ref TMR4_Count_Clock_Source */ + uint16_t u16ClockDiv; /*!< TMR4 counter internal clock division. + This parameter can be a value of @ref TMR4_Count_Clock_Division. */ + uint16_t u16CountMode; /*!< TMR4 counter mode. + This parameter can be a value of @ref TMR4_Count_Mode */ + uint16_t u16PeriodValue; /*!< TMR4 counter period value. + This parameter can be a value of half-word */ +} stc_tmr4_init_t; + +/** + * @brief The configuration of Output-Compare high channel(OUH/OVH/OWH) + */ +typedef union { + uint16_t OCMRx; /*!< OCMRxH(x=U/V/W) register */ + + struct { /*!< OCMRxH(x=U/V/W) register struct field bit */ + uint16_t OCFDCH : 1; /*!< OCMRxh b0 High channel's OCF status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFPKH : 1; /*!< OCMRxh b1 High channel's OCF status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFUCH : 1; /*!< OCMRxh b2 High channel's OCF status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OCFZRH : 1; /*!< OCMRxh b3 High channel's OCF status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint16_t OPDCH : 2; /*!< OCMRxh b5~b4 High channel's OP output status when high channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPPKH : 2; /*!< OCMRxh b7~b6 High channel's OP output status when high channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPUCH : 2; /*!< OCMRxh b9~b8 High channel's OP output status when high channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPZRH : 2; /*!< OCMRxh b11~b10 High channel's OP output status when high channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNPKH : 2; /*!< OCMRxh b13~b12 High channel's OP output status when high channel match doesn't occur at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint16_t OPNZRH : 2; /*!< OCMRxh b15~b14 High channel's OP output status when high channel match doesn't occur at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrh_t; + +/** + * @brief The configuration of Output-Compare low channel(OUL/OVL/OWL) + */ +typedef union { + uint32_t OCMRx; /*!< OCMRxL(x=U/V/W) register */ + + struct { /*!< OCMRxL(x=U/V/W) register struct field bit*/ + uint32_t OCFDCL : 1; /*!< OCMRxl b0 Low channel's OCF status when low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFPKL : 1; /*!< OCMRxl b1 Low channel's OCF status when low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFUCL : 1; /*!< OCMRxl b2 Low channel's OCF status when low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OCFZRL : 1; /*!< OCMRxl b3 Low channel's OCF status when low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_OCF_State */ + uint32_t OPDCL : 2; /*!< OCMRxl b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPPKL : 2; /*!< OCMRxl b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPUCL : 2; /*!< OCMRxl b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPZRL : 2; /*!< OCMRxl b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNPKL : 2; /*!< OCMRxl b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t OPNZRL : 2; /*!< OCMRxl b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNDCL : 2; /*!< OCMRxl b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNUCL : 2; /*!< OCMRxl b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPDCL : 2; /*!< OCMRxl b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting down + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPPKL : 2; /*!< OCMRxl b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPUCL : 2; /*!< OCMRxl b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition that counter is counting up + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPZRL : 2; /*!< OCMRxl b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNPKL : 2; /*!< OCMRxl b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=Peak + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + uint32_t EOPNZRL : 2; /*!< OCMRxl b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition that counter count=0x0000 + This parameter can be a value of @ref TMR4_OC_Count_Match_Output_Polarity */ + } OCMRx_f; +} un_tmr4_oc_ocmrl_t; + +/** + * @brief TMR4 Output-Compare(OC) initialization configuration + */ +typedef struct { + uint16_t u16CompareValue; /*!< TMR4 OC compare match value. + This parameter can be a value of half-word. */ + uint16_t u16OcInvalidPolarity; /*!< Port output polarity when OC is disabled. + This parameter can be a value of @ref TMR4_OC_Invalid_Output_Polarity. */ + uint16_t u16CompareModeBufCond; /*!< Register OCMR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16CompareValueBufCond; /*!< Register OCCR buffer transfer condition. + This parameter can be a value of @ref TMR4_OC_Buffer_Transfer_Condition. */ + uint16_t u16BufLinkTransObject; /*!< Enable the specified object(OCMR/OCCR) register buffer linked transfer with the counter interrupt mask. + This parameter can be a value of @ref TMR4_OC_Buffer_Object. */ +} stc_tmr4_oc_init_t; + +/** + * @brief TMR4 PWM initialization configuration + * @note The clock division(u16ClockDiv) is valid when TMR4 clock source is the internal clock. + */ +typedef struct { + uint16_t u16Mode; /*!< Select PWM mode + This parameter can be a value of @ref TMR4_PWM_Mode */ + uint16_t u16ClockDiv; /*!< The internal clock division of PWM timer. + This parameter can be a value of @ref TMR4_PWM_Clock_Division. */ + uint16_t u16Polarity; /*!< TMR4 PWM polarity + This parameter can be a value of @ref TMR4_PWM_Polarity */ +} stc_tmr4_pwm_init_t; + +/** + * @brief TMR4 Special-Event(EVT) initialization configuration + */ +typedef struct { + uint16_t u16Mode; /*!< TMR4 event mode + This parameter can be a value of @ref TMR4_Event_Mode */ + uint16_t u16CompareValue; /*!< TMR4 event compare match value. + This parameter can be a value of half-word */ + uint16_t u16OutputEvent; /*!< TMR4 event output event when match count compare condition. + This parameter can be a value of @ref TMR4_Event_Output_Event */ + uint16_t u16MatchCond; /*!< Enable the specified count compare type with counter count to generate event. + This parameter can be a value of @ref TMR4_Event_Match_Condition */ +} stc_tmr4_evt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Macros TMR4 Global Macros + * @{ + */ + +/** + * @defgroup TMR4_Counter_Macros TMR4 Counter Macros + * @{ + */ + +/** + * @defgroup TMR4_Count_Clock_Source TMR4 Count Clock Source + * @{ + */ +#define TMR4_CLK_SRC_INTERNCLK (0U) +#define TMR4_CLK_SRC_EXTCLK (TMR4_CCSR_ECKEN) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Clock_Division TMR4 Count Clock Division + * @{ + */ +#define TMR4_CLK_DIV1 (0U << TMR4_CCSR_CKDIV_POS) /*!< CLK */ +#define TMR4_CLK_DIV2 (1U << TMR4_CCSR_CKDIV_POS) /*!< CLK/2 */ +#define TMR4_CLK_DIV4 (2U << TMR4_CCSR_CKDIV_POS) /*!< CLK/4 */ +#define TMR4_CLK_DIV8 (3U << TMR4_CCSR_CKDIV_POS) /*!< CLK/8 */ +#define TMR4_CLK_DIV16 (4U << TMR4_CCSR_CKDIV_POS) /*!< CLK/16 */ +#define TMR4_CLK_DIV32 (5U << TMR4_CCSR_CKDIV_POS) /*!< CLK/32 */ +#define TMR4_CLK_DIV64 (6U << TMR4_CCSR_CKDIV_POS) /*!< CLK/64 */ +#define TMR4_CLK_DIV128 (7U << TMR4_CCSR_CKDIV_POS) /*!< CLK/128 */ +#define TMR4_CLK_DIV256 (8U << TMR4_CCSR_CKDIV_POS) /*!< CLK/256 */ +#define TMR4_CLK_DIV512 (9U << TMR4_CCSR_CKDIV_POS) /*!< CLK/512 */ +#define TMR4_CLK_DIV1024 (10U << TMR4_CCSR_CKDIV_POS) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Mode TMR4 Count Mode + * @{ + */ +#define TMR4_MD_SAWTOOTH (0U) +#define TMR4_MD_TRIANGLE (TMR4_CCSR_MODE) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag TMR4 Flag + * @{ + */ +#define TMR4_FLAG_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPF) /*!< Count peak flag */ +#define TMR4_FLAG_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZF) /*!< Count valley flag */ +#define TMR4_FLAG_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer flag - channel U */ +#define TMR4_FLAG_RELOAD_TMR_V (1UL << 4U) /*!< TMR4 PWM reload-timer flag - channel V */ +#define TMR4_FLAG_RELOAD_TMR_W (1UL << 8U) /*!< TMR4 PWM reload-timer flag - channel W */ +#define TMR4_FLAG_RELOAD_TMR_X (1UL << 12U) /*!< TMR4 PWM reload-timer flag - channel X */ +#define TMR4_FLAG_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare flag - channel UH */ +#define TMR4_FLAG_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare flag - channel UL */ +#define TMR4_FLAG_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare flag - channel VH */ +#define TMR4_FLAG_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare flag - channel VL */ +#define TMR4_FLAG_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare flag - channel WH */ +#define TMR4_FLAG_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare flag - channel WL */ +#define TMR4_FLAG_OC_CMP_XH (1UL << 22U) /*!< TMR4 output-compare compare flag - channel XH */ +#define TMR4_FLAG_OC_CMP_XL (1UL << 23U) /*!< TMR4 output-compare compare flag - channel XL */ +#define TMR4_FLAG_SCMP_EVT0 (1UL << 24U) /*!< TMR4 event-compare compare flag - event 0 */ +#define TMR4_FLAG_SCMP_EVT1 (1UL << 25U) /*!< TMR4 event-compare compare flag - event 1 */ +#define TMR4_FLAG_SCMP_EVT2 (1UL << 26U) /*!< TMR4 event-compare compare flag - event 2 */ +#define TMR4_FLAG_SCMP_EVT3 (1UL << 27U) /*!< TMR4 event-compare compare flag - event 3 */ +#define TMR4_FLAG_SCMP_EVT4 (1UL << 28U) /*!< TMR4 event-compare compare flag - event 4 */ +#define TMR4_FLAG_SCMP_EVT5 (1UL << 29U) /*!< TMR4 event-compare compare flag - event 5 */ +#define TMR4_FLAG_SCMP_EVT6 (1UL << 30U) /*!< TMR4 event-compare compare flag - event 6 */ +#define TMR4_FLAG_SCMP_EVT7 (1UL << 31U) /*!< TMR4 event-compare compare flag - event 7 */ +#define TMR4_FLAG_ALL (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY | TMR4_FLAG_RELOAD_TMR_U | \ + TMR4_FLAG_RELOAD_TMR_V | TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_RELOAD_TMR_X | \ + TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | \ + TMR4_FLAG_OC_CMP_VL | TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL | \ + TMR4_FLAG_OC_CMP_XH | TMR4_FLAG_OC_CMP_XL | TMR4_FLAG_SCMP_EVT0 | \ + TMR4_FLAG_SCMP_EVT1 | TMR4_FLAG_SCMP_EVT2 | TMR4_FLAG_SCMP_EVT3 | \ + TMR4_FLAG_SCMP_EVT4 | TMR4_FLAG_SCMP_EVT5 | TMR4_FLAG_SCMP_EVT6 | \ + TMR4_FLAG_SCMP_EVT7) +/** + * @} + */ + +/** + * @defgroup TMR4_Interrupt TMR4 Interrupt + * @{ + */ +#define TMR4_INT_CNT_PEAK ((uint32_t)TMR4_CCSR_IRQPEN) /*!< Count peak interrupt */ +#define TMR4_INT_CNT_VALLEY ((uint32_t)TMR4_CCSR_IRQZEN) /*!< Count valley interrupt */ +#define TMR4_INT_RELOAD_TMR_U (1UL << 0U) /*!< TMR4 PWM reload-timer interrupt - channel U */ +#define TMR4_INT_RELOAD_TMR_V (1UL << 1U) /*!< TMR4 PWM reload-timer interrupt - channel W */ +#define TMR4_INT_RELOAD_TMR_W (1UL << 2U) /*!< TMR4 PWM reload-timer interrupt - channel V */ +#define TMR4_INT_RELOAD_TMR_X (1UL << 3U) /*!< TMR4 PWM reload-timer interrupt - channel V */ +#define TMR4_INT_OC_CMP_UH (1UL << 16U) /*!< TMR4 output-compare compare interrupt - channel UH */ +#define TMR4_INT_OC_CMP_UL (1UL << 17U) /*!< TMR4 output-compare compare interrupt - channel UL */ +#define TMR4_INT_OC_CMP_VH (1UL << 18U) /*!< TMR4 output-compare compare interrupt - channel VH */ +#define TMR4_INT_OC_CMP_VL (1UL << 19U) /*!< TMR4 output-compare compare interrupt - channel VL */ +#define TMR4_INT_OC_CMP_WH (1UL << 20U) /*!< TMR4 output-compare compare interrupt - channel WH */ +#define TMR4_INT_OC_CMP_WL (1UL << 21U) /*!< TMR4 output-compare compare interrupt - channel WL */ +#define TMR4_INT_OC_CMP_XH (1UL << 22U) /*!< TMR4 output-compare compare interrupt - channel XH */ +#define TMR4_INT_OC_CMP_XL (1UL << 23U) /*!< TMR4 output-compare compare interrupt - channel XL */ +#define TMR4_INT_SCMP_EVT0 (1UL << 24U) /*!< TMR4 event-compare compare interrupt - event 0 */ +#define TMR4_INT_SCMP_EVT1 (1UL << 25U) /*!< TMR4 event-compare compare interrupt - event 1 */ +#define TMR4_INT_SCMP_EVT2 (1UL << 26U) /*!< TMR4 event-compare compare interrupt - event 2 */ +#define TMR4_INT_SCMP_EVT3 (1UL << 27U) /*!< TMR4 event-compare compare interrupt - event 3 */ +#define TMR4_INT_SCMP_EVT4 (1UL << 28U) /*!< TMR4 event-compare compare interrupt - event 4 */ +#define TMR4_INT_SCMP_EVT5 (1UL << 29U) /*!< TMR4 event-compare compare interrupt - event 5 */ +#define TMR4_INT_SCMP_EVT6 (1UL << 30U) /*!< TMR4 event-compare compare interrupt - event 6 */ +#define TMR4_INT_SCMP_EVT7 (1UL << 31U) /*!< TMR4 event-compare compare interrupt - event 7 */ + +#define TMR4_INT_ALL (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY | TMR4_INT_RELOAD_TMR_U | \ + TMR4_INT_RELOAD_TMR_V | TMR4_INT_RELOAD_TMR_W | TMR4_INT_RELOAD_TMR_X | \ + TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | \ + TMR4_INT_OC_CMP_VL | TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL | \ + TMR4_INT_OC_CMP_XH | TMR4_INT_OC_CMP_XL | TMR4_INT_SCMP_EVT0 | \ + TMR4_INT_SCMP_EVT1 | TMR4_INT_SCMP_EVT2 | TMR4_INT_SCMP_EVT3 | \ + TMR4_INT_SCMP_EVT4 | TMR4_INT_SCMP_EVT5 | TMR4_INT_SCMP_EVT6 | \ + TMR4_INT_SCMP_EVT7) +/** + * @} + */ + +/** + * @defgroup TMR4_Count_Interrupt_Mask_Time TMR4 Count Interrupt Mask Time + * @{ + */ +#define TMR4_INT_CNT_MASK0 (0U) /*!< Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak */ +#define TMR4_INT_CNT_MASK1 (1U) /*!< Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) */ +#define TMR4_INT_CNT_MASK2 (2U) /*!< Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) */ +#define TMR4_INT_CNT_MASK3 (3U) /*!< Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) */ +#define TMR4_INT_CNT_MASK4 (4U) /*!< Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) */ +#define TMR4_INT_CNT_MASK5 (5U) /*!< Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) */ +#define TMR4_INT_CNT_MASK6 (6U) /*!< Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) */ +#define TMR4_INT_CNT_MASK7 (7U) /*!< Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) */ +#define TMR4_INT_CNT_MASK8 (8U) /*!< Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) */ +#define TMR4_INT_CNT_MASK9 (9U) /*!< Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) */ +#define TMR4_INT_CNT_MASK10 (10U) /*!< Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) */ +#define TMR4_INT_CNT_MASK11 (11U) /*!< Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) */ +#define TMR4_INT_CNT_MASK12 (12U) /*!< Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) */ +#define TMR4_INT_CNT_MASK13 (13U) /*!< Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) */ +#define TMR4_INT_CNT_MASK14 (14U) /*!< Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) */ +#define TMR4_INT_CNT_MASK15 (15U) /*!< Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Macros TMR4 Output-Compare Macros + * @{ + */ + +/** + * @defgroup TMR4_OC_Channel TMR4 OC Channel + * @{ + */ +#define TMR4_OC_CH_UH (0UL) /*!< TMR4 OC channel:UH */ +#define TMR4_OC_CH_UL (1UL) /*!< TMR4 OC channel:UL */ +#define TMR4_OC_CH_VH (2UL) /*!< TMR4 OC channel:VH */ +#define TMR4_OC_CH_VL (3UL) /*!< TMR4 OC channel:VL */ +#define TMR4_OC_CH_WH (4UL) /*!< TMR4 OC channel:WH */ +#define TMR4_OC_CH_WL (5UL) /*!< TMR4 OC channel:WL */ +#define TMR4_OC_CH_XH (6UL) /*!< TMR4 OC channel:XH */ +#define TMR4_OC_CH_XL (7UL) /*!< TMR4 OC channel:XL */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Invalid_Output_Polarity TMR4 OC Invalid Output Polarity + * @{ + */ +#define TMR4_OC_INVD_LOW (0U) /*!< TMR4 OC Output low level when OC is invalid */ +#define TMR4_OC_INVD_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level when OC is invalid */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Output_Polarity TMR4 OC Output Polarity + * @{ + */ +#define TMR4_OC_PORT_LOW (0U) /*!< TMR4 OC Output low level */ +#define TMR4_OC_PORT_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OC Output high level */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object TMR4 OC Buffer Object + * @{ + */ +#define TMR4_OC_BUF_NONE (0x00U) /*!< Disable the buffer function of OCCR/OCMR */ +#define TMR4_OC_BUF_CMP_VALUE (0x01U) /*!< The register OCCR buffer function */ +#define TMR4_OC_BUF_CMP_MD (0x02U) /*!< The register OCMR buffer function */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Transfer_Condition TMR4 OC OCCR Buffer Transfer Condition + * @{ + */ +#define TMR4_OC_BUF_COND_IMMED (0U) /*!< Buffer transfer is made when writing to the OCCR/OCMR register. */ +#define TMR4_OC_BUF_COND_VALLEY (1U) /*!< Buffer transfer is made when counter count valley */ +#define TMR4_OC_BUF_COND_PEAK (2U) /*!< Buffer transfer is made when counter count peak */ +#define TMR4_OC_BUF_COND_PEAK_VALLEY (3U) /*!< Buffer transfer is made when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_OCF_State TMR4 OC Count Match OCF State + * @{ + */ +#define TMR4_OC_OCF_HOLD (0U) /*!< Hold OCF when the TMR4 OC count match */ +#define TMR4_OC_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Count_Match_Output_Polarity TMR4 OC Count Match Output Polarity + * @{ + */ +#define TMR4_OC_HOLD (0U) /*!< Hold output when the TMR4 OC count match */ +#define TMR4_OC_HIGH (1U) /*!< Output high when the TMR4 OC count match */ +#define TMR4_OC_LOW (2U) /*!< Output low when the TMR4 OC count match */ +#define TMR4_OC_INVT (3U) /*!< Invert output when the TMR4 OC count match */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Macros TMR4 PWM Macros + * @{ + */ + +/** + * @defgroup TMR4_PWM_Channel TMR4 PWM Channel + * @{ + */ +#define TMR4_PWM_CH_U (0UL) /*!< TMR4 PWM couple channel: U */ +#define TMR4_PWM_CH_V (1UL) /*!< TMR4 PWM couple channel: V */ +#define TMR4_PWM_CH_W (2UL) /*!< TMR4 PWM couple channel: W */ +#define TMR4_PWM_CH_X (3UL) /*!< TMR4 PWM couple channel: X */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Pin TMR4 PWM Pin + * @{ + */ +#define TMR4_PWM_PIN_OUH (0UL) /*!< TMR4 PWM port: TIM4__OUH */ +#define TMR4_PWM_PIN_OUL (1UL) /*!< TMR4 PWM port: TIM4__OUL */ +#define TMR4_PWM_PIN_OVH (2UL) /*!< TMR4 PWM port: TIM4__OVH */ +#define TMR4_PWM_PIN_OVL (3UL) /*!< TMR4 PWM port: TIM4__OVL */ +#define TMR4_PWM_PIN_OWH (4UL) /*!< TMR4 PWM port: TIM4__OWH */ +#define TMR4_PWM_PIN_OWL (5UL) /*!< TMR4 PWM port: TIM4__OWL */ +#define TMR4_PWM_PIN_OXH (6UL) /*!< TMR4 PWM port: TIM4__OXH */ +#define TMR4_PWM_PIN_OXL (7UL) /*!< TMR4 PWM port: TIM4__OXL */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Clock_Division TMR4 PWM Clock Division + * @{ + */ +#define TMR4_PWM_CLK_DIV1 (0U) /*!< CLK */ +#define TMR4_PWM_CLK_DIV2 (1U << TMR4_POCR_DIVCK_POS) /*!< CLK/2 */ +#define TMR4_PWM_CLK_DIV4 (2U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV8 (3U << TMR4_POCR_DIVCK_POS) /*!< CLK/8 */ +#define TMR4_PWM_CLK_DIV16 (4U << TMR4_POCR_DIVCK_POS) /*!< CLK/16 */ +#define TMR4_PWM_CLK_DIV32 (5U << TMR4_POCR_DIVCK_POS) /*!< CLK/32 */ +#define TMR4_PWM_CLK_DIV64 (6U << TMR4_POCR_DIVCK_POS) /*!< CLK/64 */ +#define TMR4_PWM_CLK_DIV128 (7U << TMR4_POCR_DIVCK_POS) /*!< CLK/128 */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Mode TMR4 PWM Mode + * @{ + */ +#define TMR4_PWM_MD_THROUGH (0U) /*!< Through mode */ +#define TMR4_PWM_MD_DEAD_TMR (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */ +#define TMR4_PWM_MD_DEAD_TMR_FILTER (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Polarity TMR4 PWM Polarity + * @{ + */ +#define TMR4_PWM_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */ +#define TMR4_PWM_OXH_INVT_OXL_INVT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */ +#define TMR4_PWM_OXH_INVT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */ +#define TMR4_PWM_OXH_HOLD_OXL_INVT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Dead_Time_Register_Index TMR4 PWM Dead Time Register Index + * @{ + */ +#define TMR4_PWM_PDAR_IDX (0UL) /*!< TMR4_PDARn(n=U/V/W) */ +#define TMR4_PWM_PDBR_IDX (1UL) /*!< TMR4_PDBRn(n=U/V/W) */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Abnormal_Pin_Status TMR4 PWM Abnormal Pin Status + * @{ + */ +#define TMR4_PWM_ABNORMAL_PIN_NORMAL (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal */ +#define TMR4_PWM_ABNORMAL_PIN_HIZ (1UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) to Hi-z */ +#define TMR4_PWM_ABNORMAL_PIN_LOW (2UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output low level */ +#define TMR4_PWM_ABNORMAL_PIN_HIGH (3UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output high level */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Pin_Output_Mode TMR4 PWM Pin Mode + * @{ + */ +#define TMR4_PWM_PIN_OUTPUT_OS (0UL) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output polarity by specified register TMR4_PSCR.OSxy */ +#define TMR4_PWM_PIN_OUTPUT_NORMAL (TMR4_PSCR_OEUH) /*!< TIM4__Oxy(x=U/V/W, y=H/L) output normal PWM */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_OE_Bit_Effect_Time TMR4 PWM Register TMR4_PSCR.OE Bit Effect Time + * @{ + */ +#define TMR4_PWM_OE_EFFECT_IMMED (TMR4_PSCR_ODT_0) /*!< TMR4 PWM register TMR4_PSCR.OE bit immediate effect. */ +#define TMR4_PWM_OE_EFFECT_COUNT_PEAK (TMR4_PSCR_ODT) /*!< TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count peak. */ +#define TMR4_PWM_OE_EFFECT_COUNT_VALLEY (TMR4_PSCR_ODT_1) /*!< TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count valley. */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Macros TMR4 Event Macros + * @{ + */ + +/** + * @defgroup TMR4_Event_Channel TMR4 Event Channel + * @{ + */ +#define TMR4_EVT_CH_UH (0UL) /*!< TMR4 EVT channel:UH */ +#define TMR4_EVT_CH_UL (1UL) /*!< TMR4 EVT channel:UL */ +#define TMR4_EVT_CH_VH (2UL) /*!< TMR4 EVT channel:VH */ +#define TMR4_EVT_CH_VL (3UL) /*!< TMR4 EVT channel:VL */ +#define TMR4_EVT_CH_WH (4UL) /*!< TMR4 EVT channel:WH */ +#define TMR4_EVT_CH_WL (5UL) /*!< TMR4 EVT channel:WL */ +#define TMR4_EVT_CH_XH (6UL) /*!< TMR4 EVT channel:XH */ +#define TMR4_EVT_CH_XL (7UL) /*!< TMR4 EVT channel:XL */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Match_Condition TMR4 Event Match Condition + * @{ + */ +#define TMR4_EVT_MATCH_CNT_UP (TMR4_SCSR_UEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count up */ +#define TMR4_EVT_MATCH_CNT_DOWN (TMR4_SCSR_DEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count down */ +#define TMR4_EVT_MATCH_CNT_PEAK (TMR4_SCSR_PEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count peak */ +#define TMR4_EVT_MATCH_CNT_VALLEY (TMR4_SCSR_ZEN) /*!< Start event operation when match with SCCR&SCMR and TMR4 counter count valley */ +#define TMR4_EVT_MATCH_CNT_ALL (TMR4_EVT_MATCH_CNT_DOWN | TMR4_EVT_MATCH_CNT_UP | \ + TMR4_EVT_MATCH_CNT_PEAK | TMR4_EVT_MATCH_CNT_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask TMR4 Event Mask + * @{ + */ +#define TMR4_EVT_MASK_PEAK (TMR4_SCMR_MPCE) /*!< Match with the count peak interrupt mask of the counter */ +#define TMR4_EVT_MASK_VALLEY (TMR4_SCMR_MZCE) /*!< Match with the count valley interrupt mask of the counter */ +#define TMR4_EVT_MASK_TYPE_ALL (TMR4_EVT_MASK_PEAK | TMR4_EVT_MASK_VALLEY) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Buffer_Transfer_Condition TMR4 Event Buffer Transfer Condition + * @{ + */ +#define TMR4_EVT_BUF_COND_IMMED (0U) /*!< Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register */ +#define TMR4_EVT_BUF_COND_VALLEY (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter count valley */ +#define TMR4_EVT_BUF_COND_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter count peak */ +#define TMR4_EVT_BUF_COND_PEAK_VALLEY (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when counter count peak or valley */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mode TMR4 Event Mode + * @{ + */ +#define TMR4_EVT_MD_CMP (0U) /*!< TMR4 EVT compare mode */ +#define TMR4_EVT_MD_DELAY (TMR4_SCSR_EVTMS) /*!< TMR4 EVT delay mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Delay_Object TMR4 Event Delay Object + * @{ + */ +#define TMR4_EVT_DELAY_OCCRXH (0U) /*!< TMR4 EVT delay object: OCCRxh(x=u/v/w) */ +#define TMR4_EVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 EVT delay object: OCCRxl(x=u/v/w) */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Mask_Times TMR4 Event Mask Times + * @{ + */ +#define TMR4_EVT_MASK0 (0U << TMR4_SCMR_AMC_POS) /*!< Mask 0 time */ +#define TMR4_EVT_MASK1 (1U << TMR4_SCMR_AMC_POS) /*!< Mask 1 times */ +#define TMR4_EVT_MASK2 (2U << TMR4_SCMR_AMC_POS) /*!< Mask 2 times */ +#define TMR4_EVT_MASK3 (3U << TMR4_SCMR_AMC_POS) /*!< Mask 3 times */ +#define TMR4_EVT_MASK4 (4U << TMR4_SCMR_AMC_POS) /*!< Mask 4 times */ +#define TMR4_EVT_MASK5 (5U << TMR4_SCMR_AMC_POS) /*!< Mask 5 times */ +#define TMR4_EVT_MASK6 (6U << TMR4_SCMR_AMC_POS) /*!< Mask 6 times */ +#define TMR4_EVT_MASK7 (7U << TMR4_SCMR_AMC_POS) /*!< Mask 7 times */ +#define TMR4_EVT_MASK8 (8U << TMR4_SCMR_AMC_POS) /*!< Mask 8 times */ +#define TMR4_EVT_MASK9 (9U << TMR4_SCMR_AMC_POS) /*!< Mask 9 times */ +#define TMR4_EVT_MASK10 (10U << TMR4_SCMR_AMC_POS) /*!< Mask 10 times */ +#define TMR4_EVT_MASK11 (11U << TMR4_SCMR_AMC_POS) /*!< Mask 11 times */ +#define TMR4_EVT_MASK12 (12U << TMR4_SCMR_AMC_POS) /*!< Mask 12 times */ +#define TMR4_EVT_MASK13 (13U << TMR4_SCMR_AMC_POS) /*!< Mask 13 times */ +#define TMR4_EVT_MASK14 (14U << TMR4_SCMR_AMC_POS) /*!< Mask 14 times */ +#define TMR4_EVT_MASK15 (15U << TMR4_SCMR_AMC_POS) /*!< Mask 15 times */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Event TMR4 Event Output Event + * @{ + */ +#define TMR4_EVT_OUTPUT_EVT0 (0U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 0 */ +#define TMR4_EVT_OUTPUT_EVT1 (1U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 1 */ +#define TMR4_EVT_OUTPUT_EVT2 (2U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 2 */ +#define TMR4_EVT_OUTPUT_EVT3 (3U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 3 */ +#define TMR4_EVT_OUTPUT_EVT4 (4U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 4 */ +#define TMR4_EVT_OUTPUT_EVT5 (5U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 5 */ +#define TMR4_EVT_OUTPUT_EVT6 (6U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 6 */ +#define TMR4_EVT_OUTPUT_EVT7 (7U << TMR4_SCSR_EVTOS_POS) /*!< TMR4 event output special event 7 */ +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Output_Signal TMR4 Event Output Signal + * @{ + */ +#define TMR4_EVT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT0_SIGNAL (1U) /*!< Output the specified event 0 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT1_SIGNAL (2U) /*!< Output the specified event 1 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT2_SIGNAL (3U) /*!< Output the specified event 2 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT3_SIGNAL (4U) /*!< Output the specified event 3 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT4_SIGNAL (5U) /*!< Output the specified event 4 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT5_SIGNAL (6U) /*!< Output the specified event 5 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT6_SIGNAL (8U) /*!< Output the specified event 6 signal of TMR4 Special-EVT */ +#define TMR4_EVT_OUTPUT_EVT7_SIGNAL (9U) /*!< Output the specified event 7 signal of TMR4 Special-EVT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR4_Global_Functions + * @{ + */ + +/** + * @addtogroup TMR4_Counter_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 counter functions */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init); +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init); +int32_t TMR4_DeInit(CM_TMR4_TypeDef *TMR4x); +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src); +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div); +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode); +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x); +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value); +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x); +void TMR4_Start(CM_TMR4_TypeDef *TMR4x); +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x); +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag); +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState); +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType); +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime); +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType); +void TMR4_PortOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +void TMR4_SyncStartCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +void TMR4_HWStartCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +/** + * @} + */ + +/** + * @addtogroup TMR4_Output_Compare_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 Output-Compare functions */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit); +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit); +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_OC_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState); +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond); +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh); +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl); +/** + * @} + */ + +/** + * @addtogroup TMR4_PWM_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 PWM functions */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit); +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div); +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity); +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value); +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex); +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus); +void TMR4_PWM_SetOEEffectTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Time); +void TMR4_PWM_EmbHWMainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +void TMR4_PWM_MainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState); +void TMR4_PWM_SetPortOutputMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32Mode); + +/** + * @} + */ + +/** + * @addtogroup TMR4_Event_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 event functions */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit); +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit); +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object); +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime); +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value); +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event); +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond); +void TMR4_EVT_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR4_EVT_EventIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState); +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); +void TMR4_EVT_SetOutputEventSignal(CM_TMR4_TypeDef *TMR4x, uint16_t u16Signal); +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR4_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h new file mode 100644 index 0000000000..38b8ff6142 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmr6.h @@ -0,0 +1,873 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.h + * @brief This file contains all the functions prototypes of the TMR6 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Modify macro define for group TMR6_Emb_Ch_Define + 2023-12-15 CDT Modify for headfile update: CM_TMR6CR -> CM_TMR6_COMMON + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMR6_H__ +#define __HC32_LL_TMR6_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMR6 + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Types TMR6 Global Types + * @{ + */ + +/** + * @brief Timer6 count function structure definition + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source @ref TMR6_Count_Src_Define */ + struct { + uint32_t u32ClockDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_Define */ + uint32_t u32CountMode; /*!< Count mode, @ref TMR6_Count_Mode_Define */ + uint32_t u32CountDir; /*!< Count direction, @ref TMR6_Count_Dir_Define */ + } sw_count; + struct { + uint32_t u32CountUpCond; /*!< Hardware count up condition. @ref TMR6_HW_Count_Up_Cond_Define */ + uint32_t u32CountDownCond; /*!< Hardware count down condition. @ref TMR6_HW_Count_Down_Cond_Define */ + } hw_count; + uint32_t u32PeriodValue; /*!< The period reference value. (0x00 ~ 0xFFFF) or (0x00 ~ 0xFFFFFFFF) */ + uint32_t u32CountReload; /*!< Count reload after overflow @ref TMR6_Count_Reload_Define */ +} stc_tmr6_init_t; + +/** + * @brief Timer6 pwm output function structure definition + */ +typedef struct { + uint32_t u32CompareValue; /*!< Range (0 ~ 0xFFFF) or (0 ~ 0xFFFFFFFF) */ + uint32_t u32StartPolarity; /*!< Pin polarity when count start @ref TMR6_Pin_Polarity_Define */ + uint32_t u32StopPolarity; /*!< Pin polarity when count stop @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CountUpMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-up mode \ + @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CountDownMatchAPolarity; /*!< Port state when match compare register A(GCMAR) at count-down mode \ + @ref TMR6_Pin_Polarity_Define */ + uint32_t u32CountUpMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-up mode \ + @ref TMR6_Pin_Polarity_Define*/ + uint32_t u32CountDownMatchBPolarity; /*!< Port state when match compare register B(GCMBR) at count-down mode\ + @ref TMR6_Pin_Polarity_Define */ + uint32_t u32UdfPolarity; /*!< Pin polarity when underflow @ref TMR6_Pin_Polarity_Define */ + uint32_t u32OvfPolarity; /*!< Pin polarity when overflow @ref TMR6_Pin_Polarity_Define */ +} stc_tmr6_pwm_init_t; + +/** + * @brief Timer6 buffer function configuration structure definition + */ +typedef struct { + uint32_t u32BufNum; /*!< The buffer number, and this parameter can be a value of \ + @ref TMR6_Buf_Num_Define */ + uint32_t u32BufTransCond; /*!< The buffer send time, and this parameter can be a value of \ + @ref TMR6_Buf_Trans_Cond_Define */ +} stc_tmr6_buf_config_t; + +/** + * @brief Timer6 Valid period function configuration structure definition + */ +typedef struct { + uint32_t u32CountCond; /*!< The count condition, and this parameter can be a value of \ + @ref TMR6_Valid_Period_Count_Cond_Define */ + uint32_t u32PeriodInterval; /*!< The interval of the valid period @ref TMR6_Valid_Period_Count_Define */ +} stc_tmr6_valid_period_config_t; + +/** + * @brief Timer6 EMB configuration structure definition + */ +typedef struct { + uint32_t u32ValidCh; /*!< Valid EMB event channel @ref TMR6_Emb_Ch_Define */ + uint32_t u32ReleaseMode; /*!< Pin release mode when EMB event invalid @ref TMR6_Emb_Release_Mode_Define */ + uint32_t u32PinStatus; /*!< Pin output status when EMB event valid @ref TMR6_Emb_Pin_Status_Define */ +} stc_tmr6_emb_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32EqualUpDown; /*!< Enable down count dead time register equal to up count DT register \ + @ref TMR6_Deadtime_Reg_Equal_Func_Define */ + uint32_t u32BufUp; /*!< Enable buffer transfer for up count dead time register (DTUBR-->DTUAR) \ + @ref TMR6_Deadtime_CountUp_Buf_Func_Define*/ + uint32_t u32BufDown; /*!< Enable buffer transfer for down count dead time register (DTDBR-->DTDAR) \ + @ref TMR6_Deadtime_CountDown_Buf_Func_Define*/ + uint32_t u32BufTransCond; /*!< Buffer transfer condition for triangular wave mode \ + @ref TMR6_Deadtime_Buf_Trans_Cond_Define */ +} stc_tmr6_deadtime_config_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct { + uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_Define */ + uint32_t u32PosCountMaskFunc; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) during \ + the time of Z phase input mask @ref TMR6_Zmask_Pos_Unit_Clear_Func_Define */ + uint32_t u32RevoCountMaskFunc; /*!< As revolution count timer, the counter function enable(TRUE) or disable(FALSE) \ + during the time of Z phase input mask \ + @ref TMR6_Zmask_Revo_Unit_Count_Func_Define*/ +} stc_tmr6_zmask_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Macros TMR6 Global Macros + * @{ + */ + +/** + * @defgroup TMR6_Count_Src_Define TMR6 Count Source Define + * @{ + */ +#define TMR6_CNT_SRC_SW (0U) /*!< Timer6 normal count function */ +#define TMR6_CNT_SRC_HW (1U) /*!< Timer6 hardware count function */ +/** + * @} + */ + +/** + * @defgroup TMR6_Stat_Flag_Define TMR6 Status Flag Define + * @{ + */ +#define TMR6_FLAG_MATCH_A (TMR6_STFLR_CMAF) /*!< GCMAR match counter */ +#define TMR6_FLAG_MATCH_B (TMR6_STFLR_CMBF) /*!< GCMBR match counter */ +#define TMR6_FLAG_MATCH_C (TMR6_STFLR_CMCF) /*!< GCMCR match counter */ +#define TMR6_FLAG_MATCH_D (TMR6_STFLR_CMDF) /*!< GCMDR match counter */ +#define TMR6_FLAG_MATCH_E (TMR6_STFLR_CMEF) /*!< GCMER match counter */ +#define TMR6_FLAG_MATCH_F (TMR6_STFLR_CMFF) /*!< GCMFR match counter */ +#define TMR6_FLAG_OVF (TMR6_STFLR_OVFF) /*!< Sawtooth wave counter overflow, \ + Triangular wave peak point */ +#define TMR6_FLAG_UDF (TMR6_STFLR_UDFF) /*!< Sawtooth wave counter underflow, \ + Triangular wave valley point */ +#define TMR6_FLAG_DEAD_TIME_ERR (TMR6_STFLR_DTEF) /*!< Dead time error */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSAUF) /*!< SCMAR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A (TMR6_STFLR_CMSADF) /*!< SCMAR match counter when count-down */ +#define TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBUF) /*!< SCMBR match counter when count-up */ +#define TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B (TMR6_STFLR_CMSBDF) /*!< SCMBR match counter when count-down */ +#define TMR6_FLAG_CNT_DIR (TMR6_STFLR_DIRF) /*!< Count direction flag */ +#define TMR6_FLAG_CAPT_AGAIN_A (TMR6_STFLR_CMAF2) /*!< Capture A again flag */ +#define TMR6_FLAG_CAPT_AGAIN_B (TMR6_STFLR_CMBF2) /*!< Capture B again flag */ + +#define TMR6_FLAG_CLR_ALL (0x0C001EFFUL) /*!< Clear all flag */ +#define TMR6_FLAG_ALL (TMR6_FLAG_MATCH_A | TMR6_FLAG_MATCH_B | TMR6_FLAG_MATCH_C | \ + TMR6_FLAG_MATCH_D | TMR6_FLAG_MATCH_E | TMR6_FLAG_MATCH_F | \ + TMR6_FLAG_OVF | TMR6_FLAG_UDF | TMR6_FLAG_DEAD_TIME_ERR | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_A | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_A | \ + TMR6_FLAG_UP_CNT_SPECIAL_MATCH_B | TMR6_FLAG_DOWN_CNT_SPECIAL_MATCH_B | \ + TMR6_FLAG_CNT_DIR | TMR6_FLAG_CAPT_AGAIN_A | TMR6_FLAG_CAPT_AGAIN_B) +/** + * @} + */ + +/** + * @defgroup TMR6_Int_Flag_Define TMR6 Interrupt Flag Define + * @{ + */ +#define TMR6_INT_MATCH_A (TMR6_ICONR_INTENA) /*!< GCMAR register matched */ +#define TMR6_INT_MATCH_B (TMR6_ICONR_INTENB) /*!< GCMBR register matched */ +#define TMR6_INT_MATCH_C (TMR6_ICONR_INTENC) /*!< GCMCR register matched */ +#define TMR6_INT_MATCH_D (TMR6_ICONR_INTEND) /*!< GCMDR register matched */ +#define TMR6_INT_MATCH_E (TMR6_ICONR_INTENE) /*!< GCMER register matched */ +#define TMR6_INT_MATCH_F (TMR6_ICONR_INTENF) /*!< GCMFR register matched */ +#define TMR6_INT_OVF (TMR6_ICONR_INTENOVF) /*!< Counter register overflow */ +#define TMR6_INT_UDF (TMR6_ICONR_INTENUDF) /*!< Counter register underflow */ +#define TMR6_INT_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) /*!< Dead time error */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAU) /*!< SCMAR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A (TMR6_ICONR_INTENSAD) /*!< SCMAR register matched when count-down */ +#define TMR6_INT_UP_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBU) /*!< SCMBR register matched when count-up */ +#define TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B (TMR6_ICONR_INTENSBD) /*!< SCMBR register matched when count-down */ +#define TMR6_INT_ALL (TMR6_INT_MATCH_A | TMR6_INT_MATCH_B | TMR6_INT_MATCH_C | TMR6_INT_MATCH_D |\ + TMR6_INT_MATCH_E | TMR6_INT_MATCH_F | TMR6_INT_OVF | TMR6_INT_UDF | \ + TMR6_INT_DEAD_TIME_ERR | TMR6_INT_UP_CNT_SPECIAL_MATCH_A | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_A | TMR6_INT_UP_CNT_SPECIAL_MATCH_B | \ + TMR6_INT_DOWN_CNT_SPECIAL_MATCH_B) +/** + * @} + */ + +/** + * @defgroup TMR6_Period_Reg_Index_Define TMR6 Period Register Index Define + * @{ + */ +#define TMR6_PERIOD_REG_A (0x00UL) +#define TMR6_PERIOD_REG_B (0x01UL) +#define TMR6_PERIOD_REG_C (0x02UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Compare_Reg_Index_Define TMR6 Compare Register Index Define + * @{ + */ +#define TMR6_CMP_REG_A (0x00UL) +#define TMR6_CMP_REG_B (0x01UL) +#define TMR6_CMP_REG_C (0x02UL) +#define TMR6_CMP_REG_D (0x03UL) +#define TMR6_CMP_REG_E (0x04UL) +#define TMR6_CMP_REG_F (0x05UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Ch_Define TMR6 General/Special Compare Channel Define + * @{ + */ +#define TMR6_CH_A (0x00UL) +#define TMR6_CH_B (0x01UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Num_Define TMR6 Buffer Number Define + * @{ + */ +#define TMR6_BUF_SINGLE (0x00UL) +#define TMR6_BUF_DUAL (TMR6_BCONR_BSEA) +/** + * @} + */ + +/** + * @defgroup TMR6_Buf_Trans_Cond_Define TMR6 Buffer Transfer Time Configuration Define + * @{ + */ +#define TMR6_BUF_TRANS_INVD (0x00UL) +#define TMR6_BUF_TRANS_OVF (0x00000004UL) +#define TMR6_BUF_TRANS_UDF (0x00000008UL) +#define TMR6_BUF_TRANS_OVF_UDF (0x0000000CUL) + +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Cond_Define TMR6 Valid Period Function Count Condition Define + * @{ + */ +#define TMR6_VALID_PERIOD_INVD (0x00UL) /*!< Valid period function off */ +#define TMR6_VALID_PERIOD_CNT_COND_VALLEY (TMR6_VPERR_PCNTE_0) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave valley */ +#define TMR6_VALID_PERIOD_CNT_COND_PEAK (TMR6_VPERR_PCNTE_1) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave peak */ +#define TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK (TMR6_VPERR_PCNTE) /*!< Count when Sawtooth waveform overflow and underflow, \ + triangular wave valley and peak */ +/** + * @} + */ + +/** + * @defgroup TMR6_Valid_Period_Count_Define TMR6 Valid Period Function Count Define + * @{ + */ +#define TMR6_VALID_PERIOD_CNT_INVD (0x00UL) +#define TMR6_VALID_PERIOD_CNT1 (1UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT2 (2UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT3 (3UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT4 (4UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT5 (5UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT6 (6UL << TMR6_VPERR_PCNTS_POS) +#define TMR6_VALID_PERIOD_CNT7 (7UL << TMR6_VPERR_PCNTS_POS) +/** + * @} + */ + +/** + * @defgroup TMR6_DeadTime_Reg_Define TMR6 Dead Time Register Define + * @{ + */ +#define TMR6_DEADTIME_REG_UP_A (0x00U) /*!< Register DTUAR */ +#define TMR6_DEADTIME_REG_DOWN_A (0x01U) /*!< Register DTDAR */ +#define TMR6_DEADTIME_REG_UP_B (0x02U) /*!< Register DTUBR */ +#define TMR6_DEADTIME_REG_DOWN_B (0x03U) /*!< Register DTDBR */ +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Define TMR6 Input And Output Pin Define + * @{ + */ +#define TMR6_IO_PWMA (0x00U) /*!< Pin TIM6__PWMA */ +#define TMR6_IO_PWMB (0x01U) /*!< Pin TIM6__PWMB */ +#define TMR6_INPUT_TRIGA (0x02U) /*!< Input pin TIM6_TRIGA */ +#define TMR6_INPUT_TRIGB (0x03U) /*!< Input pin TIM6_TRIGB */ +/** + * @} + */ + +/** + * @defgroup TMR6_Input_Filter_Clock TMR6 Input Pin Filter Clock Divider Define + * @{ + */ +#define TMR6_FILTER_CLK_DIV1 (0x00U) +#define TMR6_FILTER_CLK_DIV4 (0x01U) +#define TMR6_FILTER_CLK_DIV16 (0x02U) +#define TMR6_FILTER_CLK_DIV64 (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Mode_Define TMR6 Pin Function Mode Selection + * @{ + */ +#define TMR6_PIN_CMP_OUTPUT (0x00UL) +#define TMR6_PIN_CAPT_INPUT (TMR6_PCNAR_CAPMDA) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_State_Define TMR6 Count State + * @{ + */ +#define TMR6_STAT_START (0U) /*!< Count start */ +#define TMR6_STAT_STOP (1U) /*!< Count stop */ +#define TMR6_STAT_OVF (2U) /*!< Count overflow */ +#define TMR6_STAT_UDF (3U) /*!< Count underflow */ +#define TMR6_STAT_UP_CNT_MATCH_A (4U) /*!< Count up match compare register A */ +#define TMR6_STAT_DOWN_CNT_MATCH_A (5U) /*!< Count down match compare register A */ +#define TMR6_STAT_UP_CNT_MATCH_B (6U) /*!< Count up match compare register B */ +#define TMR6_STAT_DOWN_CNT_MATCH_B (7U) /*!< Count down match compare register B */ + +/** + * @} + */ + +/** + * @defgroup TMR6_Pin_Polarity_Define TMR6 Pin Output Polarity + * @{ + */ + +#define TMR6_PWM_LOW (0x00U) +#define TMR6_PWM_HIGH (0x01U) +#define TMR6_PWM_HOLD (0x02U) +#define TMR6_PWM_INVT (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Force_Output_Polarity_Define TMR6 Force Output Polarity Next Period + * @{ + */ +#define TMR6_PWM_FORCE_INVD (0x00U) +#define TMR6_PWM_FORCE_LOW (0x02U) +#define TMR6_PWM_FORCE_HIGH (0x03U) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Ch_Define TMR6 EMB Event Channel + * @{ + */ +#define TMR6_EMB_EVT_CH0 (0x00UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Release_Mode_Define TMR6 EMB Function Release Mode When EMB Event Invalid + * @{ + */ +#define TMR6_EMB_RELEASE_IMMED (0x00UL) +#define TMR6_EMB_RELEASE_OVF (TMR6_PCNAR_EMBRA_0) +#define TMR6_EMB_RELEASE_UDF (TMR6_PCNAR_EMBRA_1) +#define TMR6_EMB_RELEASE_OVF_UDF (TMR6_PCNAR_EMBRA) +/** + * @} + */ + +/** + * @defgroup TMR6_Emb_Pin_Status_Define TMR6 Pin Output Status When EMB Event Valid + * @{ + */ +#define TMR6_EMB_PIN_NORMAL (0x00UL) +#define TMR6_EMB_PIN_HIZ (TMR6_PCNAR_EMBCA_0) +#define TMR6_EMB_PIN_LOW (TMR6_PCNAR_EMBCA_1) +#define TMR6_EMB_PIN_HIGH (TMR6_PCNAR_EMBCA) + +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountUp_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Up Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00UL) +#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_CountDown_Buf_Func_Define TMR6 Dead Time Buffer Function For Count Down Stage + * @{ + */ +#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00UL) +#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_Buf_Trans_Cond_Define TMR6 Dead Time Buffer Transfer Condition Define For Triangular Count Mode + * @{ + */ +#define TMR6_DEADTIME_BUF_COND_INVD (0x00U) +#define TMR6_DEADTIME_BUF_COND_OVF (TMR6_DCONR_DTBTRU) +#define TMR6_DEADTIME_BUF_COND_UDF (TMR6_DCONR_DTBTRD) +#define TMR6_DEADTIME_BUF_COND_OVF_UDF (TMR6_DCONR_DTBTRU | TMR6_DCONR_DTBTRD) +/** + * @} + */ + +/** + * @defgroup TMR6_Deadtime_Reg_Equal_Func_Define TMR6 Dead Time Function DTDAR Equal DTUAR + * @{ + */ +#define TMR6_DEADTIME_EQUAL_OFF (0x00UL) +#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA) +/** + * @} + */ + +/** + * @defgroup TMR6_SW_Sync_Unit_define TMR6 Software Synchronization Start/Stop/Clear/Update Unit Number Define + * @{ + */ +#define TMR6_SW_SYNC_U1 (TMR6_COMMON_SSTAR_SSTA1) +#define TMR6_SW_SYNC_U2 (TMR6_COMMON_SSTAR_SSTA2) +#define TMR6_SW_SYNC_ALL (0x03UL) + +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_start_condition_Define TMR6 Hardware Start Condition Define + * @{ + */ +#define TMR6_START_COND_PWMA_RISING (TMR6_HSTAR_HSTA0) +#define TMR6_START_COND_PWMA_FALLING (TMR6_HSTAR_HSTA1) +#define TMR6_START_COND_PWMB_RISING (TMR6_HSTAR_HSTA2) +#define TMR6_START_COND_PWMB_FALLING (TMR6_HSTAR_HSTA3) +#define TMR6_START_COND_EVT0 (TMR6_HSTAR_HSTA8) +#define TMR6_START_COND_EVT1 (TMR6_HSTAR_HSTA9) +#define TMR6_START_COND_TRIGA_RISING (TMR6_HSTAR_HSTA16) +#define TMR6_START_COND_TRIGA_FALLING (TMR6_HSTAR_HSTA17) +#define TMR6_START_COND_TRIGB_RISING (TMR6_HSTAR_HSTA18) +#define TMR6_START_COND_TRIGB_FALLING (TMR6_HSTAR_HSTA19) +#define TMR6_START_COND_ALL (0x000F030FUL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_stop_condition_Define TMR6 Hardware Stop Condition Define + * @{ + */ +#define TMR6_STOP_COND_PWMA_RISING (TMR6_HSTPR_HSTP0) +#define TMR6_STOP_COND_PWMA_FALLING (TMR6_HSTPR_HSTP1) +#define TMR6_STOP_COND_PWMB_RISING (TMR6_HSTPR_HSTP2) +#define TMR6_STOP_COND_PWMB_FALLING (TMR6_HSTPR_HSTP3) +#define TMR6_STOP_COND_EVT0 (TMR6_HSTPR_HSTP8) +#define TMR6_STOP_COND_EVT1 (TMR6_HSTPR_HSTP9) +#define TMR6_STOP_COND_TRIGA_RISING (TMR6_HSTPR_HSTP16) +#define TMR6_STOP_COND_TRIGA_FALLING (TMR6_HSTPR_HSTP17) +#define TMR6_STOP_COND_TRIGB_RISING (TMR6_HSTPR_HSTP18) +#define TMR6_STOP_COND_TRIGB_FALLING (TMR6_HSTPR_HSTP19) +#define TMR6_STOP_COND_ALL (0x000F030FUL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_clear_condition_Define TMR6 Hardware Clear Condition Define + * @{ + */ +#define TMR6_CLR_COND_PWMA_RISING (TMR6_HCLRR_HCLE0) +#define TMR6_CLR_COND_PWMA_FALLING (TMR6_HCLRR_HCLE1) +#define TMR6_CLR_COND_PWMB_RISING (TMR6_HCLRR_HCLE2) +#define TMR6_CLR_COND_PWMB_FALLING (TMR6_HCLRR_HCLE3) +#define TMR6_CLR_COND_EVT0 (TMR6_HCLRR_HCLE8) +#define TMR6_CLR_COND_EVT1 (TMR6_HCLRR_HCLE9) +#define TMR6_CLR_COND_TRIGA_RISING (TMR6_HCLRR_HCLE16) +#define TMR6_CLR_COND_TRIGA_FALLING (TMR6_HCLRR_HCLE17) +#define TMR6_CLR_COND_TRIGB_RISING (TMR6_HCLRR_HCLE18) +#define TMR6_CLR_COND_TRIGB_FALLING (TMR6_HCLRR_HCLE19) +#define TMR6_CLR_COND_ALL (0x000F030FUL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_update_condition_Define TMR6 Hardware Update Condition Define + * @{ + */ +#define TMR6_UPD_COND_PWMA_RISING (TMR6_HUPDR_HUPD0) +#define TMR6_UPD_COND_PWMA_FALLING (TMR6_HUPDR_HUPD1) +#define TMR6_UPD_COND_PWMB_RISING (TMR6_HUPDR_HUPD2) +#define TMR6_UPD_COND_PWMB_FALLING (TMR6_HUPDR_HUPD3) +#define TMR6_UPD_COND_EVT0 (TMR6_HUPDR_HUPD8) +#define TMR6_UPD_COND_EVT1 (TMR6_HUPDR_HUPD9) +#define TMR6_UPD_COND_TRIGA_RISING (TMR6_HUPDR_HUPD16) +#define TMR6_UPD_COND_TRIGA_FALLING (TMR6_HUPDR_HUPD17) +#define TMR6_UPD_COND_TRIGB_RISING (TMR6_HUPDR_HUPD18) +#define TMR6_UPD_COND_TRIGB_FALLING (TMR6_HUPDR_HUPD19) +#define TMR6_UPD_COND_ALL (0x000F030FUL) +/** + * @} + */ + +/** + * @defgroup TMR6_hardware_capture_condition_Define TMR6 Hardware Capture Condition Define + * @{ + */ +#define TMR6_CAPT_COND_PWMA_RISING (TMR6_HCPAR_HCPA0) +#define TMR6_CAPT_COND_PWMA_FALLING (TMR6_HCPAR_HCPA1) +#define TMR6_CAPT_COND_PWMB_RISING (TMR6_HCPAR_HCPA2) +#define TMR6_CAPT_COND_PWMB_FALLING (TMR6_HCPAR_HCPA3) +#define TMR6_CAPT_COND_EVT0 (TMR6_HCPAR_HCPA8) +#define TMR6_CAPT_COND_EVT1 (TMR6_HCPAR_HCPA9) +#define TMR6_CAPT_COND_TRIGA_RISING (TMR6_HCPAR_HCPA16) +#define TMR6_CAPT_COND_TRIGA_FALLING (TMR6_HCPAR_HCPA17) +#define TMR6_CAPT_COND_TRIGB_RISING (TMR6_HCPAR_HCPA18) +#define TMR6_CAPT_COND_TRIGB_FALLING (TMR6_HCPAR_HCPA19) +#define TMR6_CAPT_COND_XOR_RISING (TMR6_HCPAR_HCPA24) +#define TMR6_CAPT_COND_XOR_FALLING (TMR6_HCPAR_HCPA25) +#define TMR6_CAPT_COND_ALL (0x030F030FUL) +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Up_Cond_Define TMR6 Hardware Count Up Condition Define + * @{ + */ +#define TMR6_CNT_UP_COND_INVD (0U) +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_RISING (TMR6_HCUPR_HCUP0) +#define TMR6_CNT_UP_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCUPR_HCUP1) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCUPR_HCUP2) +#define TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCUPR_HCUP3) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_RISING (TMR6_HCUPR_HCUP4) +#define TMR6_CNT_UP_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCUPR_HCUP5) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCUPR_HCUP6) +#define TMR6_CNT_UP_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCUPR_HCUP7) +#define TMR6_CNT_UP_COND_EVT0 (TMR6_HCUPR_HCUP8) +#define TMR6_CNT_UP_COND_EVT1 (TMR6_HCUPR_HCUP9) +#define TMR6_CNT_UP_COND_TRIGA_RISING (TMR6_HCUPR_HCUP16) +#define TMR6_CNT_UP_COND_TRIGA_FALLING (TMR6_HCUPR_HCUP17) +#define TMR6_CNT_UP_COND_TRIGB_RISING (TMR6_HCUPR_HCUP18) +#define TMR6_CNT_UP_COND_TRIGB_FALLING (TMR6_HCUPR_HCUP19) +#define TMR6_CNT_UP_COND_ALL (0x000F03FFUL) +/** + * @} + */ + +/** + * @defgroup TMR6_HW_Count_Down_Cond_Define TMR6 Hardware Count Down Condition Define + * @{ + */ +#define TMR6_CNT_DOWN_COND_INVD (0U) +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_RISING (TMR6_HCDOR_HCDO0) +#define TMR6_CNT_DOWN_COND_PWMA_LOW_PWMB_FALLING (TMR6_HCDOR_HCDO1) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_RISING (TMR6_HCDOR_HCDO2) +#define TMR6_CNT_DOWN_COND_PWMA_HIGH_PWMB_FALLING (TMR6_HCDOR_HCDO3) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_RISING (TMR6_HCDOR_HCDO4) +#define TMR6_CNT_DOWN_COND_PWMB_LOW_PWMA_FALLING (TMR6_HCDOR_HCDO5) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING (TMR6_HCDOR_HCDO6) +#define TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_FALLING (TMR6_HCDOR_HCDO7) +#define TMR6_CNT_DOWN_COND_EVT0 (TMR6_HCDOR_HCDO8) +#define TMR6_CNT_DOWN_COND_EVT1 (TMR6_HCDOR_HCDO9) +#define TMR6_CNT_DOWN_COND_TRIGA_RISING (TMR6_HCDOR_HCDO16) +#define TMR6_CNT_DOWN_COND_TRIGA_FALLING (TMR6_HCDOR_HCDO17) +#define TMR6_CNT_DOWN_COND_TRIGB_RISING (TMR6_HCDOR_HCDO18) +#define TMR6_CNT_DOWN_COND_TRIGB_FALLING (TMR6_HCDOR_HCDO19) +#define TMR6_CNT_DOWN_COND_ALL (0x000F03FFUL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Dir_Define TMR6 Base Counter Function Direction Define + * @{ + */ +#define TMR6_CNT_UP (TMR6_GCONR_DIR) +#define TMR6_CNT_DOWN (0x00UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Dir_Status_Define TMR6 Count Direction Status Define + * @{ + */ +#define TMR6_STAT_CNT_UP (TMR6_STFLR_DIRF) +#define TMR6_STAT_CNT_DOWN (0x00UL) +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Mode_Define TMR6 Base Counter Function Mode Define + * @{ + */ +#define TMR6_MD_SAWTOOTH (0x00UL) +#define TMR6_MD_TRIANGLE (TMR6_GCONR_MODE) + +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Clock_Define TMR6 Base Counter Clock Source Define + * @{ + */ +#define TMR6_CLK_DIV1 (0x00UL) +#define TMR6_CLK_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV32 (0x05UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV64 (0x06UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV128 (0x07UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV256 (0x08UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV512 (0x09UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_DIV1024 (0x0AUL << TMR6_GCONR_CKDIV_POS) + +/** + * @} + */ + +/** + * @defgroup TMR6_Count_Reload_Define TMR6 Count Stop After Overflow Function Define + * @{ + */ +#define TMR6_CNT_RELOAD_ON (0x00UL) +#define TMR6_CNT_RELOAD_OFF (TMR6_GCONR_OVSTP) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Cycle_Define TMR6 Z Mask Input Function Mask Cycles Number Define + * @{ + */ +#define TMR6_ZMASK_FUNC_INVD (0x00UL) +#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0) +#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1) +#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Pos_Unit_Clear_Func_Define TMR6 Unit As Position Timer, Z Phase Input Mask Function Define For Clear Action + * @{ + */ +#define TMR6_POS_CLR_ZMASK_FUNC_OFF (0x00UL) +#define TMR6_POS_CLR_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKPOS) +/** + * @} + */ + +/** + * @defgroup TMR6_Zmask_Revo_Unit_Count_Func_Define TMR6 Unit As Revolution Timer, Z Phase Input Mask Function Define For Count Action + * @{ + */ +#define TMR6_REVO_CNT_ZMASK_FUNC_OFF (0x00UL) +#define TMR6_REVO_CNT_ZMASK_FUNC_ON (TMR6_GCONR_ZMSKREV) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR6_Global_Functions + * @{ + */ +/** + * @brief Get Software Sync start status + * @param None + * @retval uint32_t Data indicate the read status. + */ +__STATIC_INLINE uint32_t TMR6_GetSWSyncStartStatus(void) +{ + return READ_REG32(CM_TMR6_COMMON->SSTAR); +} + +/* Base count */ +int32_t TMR6_StructInit(stc_tmr6_init_t *pstcTmr6Init); +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_init_t *pstcTmr6Init); + +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode); +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir); +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x); +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div); +void TMR6_CountReloadCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Hardware count */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); + +/* PWM output */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit); +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit); +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity); +void TMR6_PWM_SetForcePolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Polarity); + +/* Input capture */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState); + +/* Pin config */ +void TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div); +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState); +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func); + +/* Universal */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag); +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x); +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x); +void TMR6_Start(CM_TMR6_TypeDef *TMR6x); +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x); + +/* Register write */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value); +void TMR6_SetUpdateValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value); +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value); + +/* Register read */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x); +uint32_t TMR6_GetUpdateValue(const CM_TMR6_TypeDef *TMR6x); +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index); + +/* Buffer function */ +int32_t TMR6_GeneralBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig); +int32_t TMR6_PeriodBufConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_config_t *pstcBufConfig); + +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig); +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Extend function */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState); +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig); +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig); +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig); +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig); +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig); +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig); + +/* Software synchronous control */ +void TMR6_SWSyncStart(uint32_t u32Unit); +void TMR6_SWSyncStop(uint32_t u32Unit); +void TMR6_SWSyncClear(uint32_t u32Unit); +void TMR6_SWSyncUpdate(uint32_t u32Unit); + +/* Hardware control */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +void TMR6_HWUpdateCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState); +void TMR6_HWUpdateCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMR6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h new file mode 100644 index 0000000000..3fe6753b27 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_tmra.h @@ -0,0 +1,574 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.h + * @brief This file contains all the functions prototypes of the TMRA(TimerA) + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TMRA_H__ +#define __HC32_LL_TMRA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TMRA + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Types TMRA Global Types + * @{ + */ +/** + * @brief TMRA initialization structure. + */ +typedef struct { + uint8_t u8CountSrc; /*!< Specifies the count source of TMRA. + This parameter can be a value of @ref TMRA_Count_Src */ + struct { + uint8_t u8ClockDiv; /*!< Specifies the divider of software clock source. + This parameter can be a value of @ref TMRA_Clock_Divider */ + uint8_t u8CountMode; /*!< Specifies count mode. + This parameter can be a value of @ref TMRA_Count_Mode */ + uint8_t u8CountDir; /*!< Specifies count direction. + This parameter can be a value of @ref TMRA_Count_Dir */ + } sw_count; + struct { + uint16_t u16CountUpCond; /*!< Hardware count up condition. + This parameter can be a value of @ref TMRA_Hard_Count_Up_Condition */ + uint16_t u16CountDownCond; /*!< Hardware count down condition. + This parameter can be a value of @ref TMRA_Hard_Count_Down_Condition */ + } hw_count; + uint32_t u32PeriodValue; /*!< Specifies the period reference value. + This parameter can be a number between 0U and 0xFFFFU, inclusive. */ + uint8_t u8CountReload; /*!< Continue counting or stop when counter overflow/underflow. + This parameter can be a value of @ref TMRA_Count_Reload_En */ +} stc_tmra_init_t; + +/** + * @brief TMRA PWM configuration structure. + */ +typedef struct { + uint32_t u32CompareValue; /*!< Specifies compare value of the TMRA channel. + This parameter can be a number between: + 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + 0UL and 0xFFFFUL for 16-bit TimerA units. */ + uint16_t u16StartPolarity; /*!< Specifies the polarity when the counter start counting. + This parameter can be a value of @ref TMRA_PWM_Polarity + NOTE: CAN NOT be specified as TMRA_PWM_LOW or TMRA_PWM_HIGH when + sw_count.u16ClockDiv of @ref stc_tmra_init_t is NOT specified + as @ref TMRA_CLK_DIV1 */ + uint16_t u16StopPolarity; /*!< Specifies the polarity when the counter stop counting. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16CompareMatchPolarity; /*!< Specifies the polarity when the counter matches the compare register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ + uint16_t u16PeriodMatchPolarity; /*!< Specifies the polarity when the counter matches the period register. + This parameter can be a value of @ref TMRA_PWM_Polarity */ +} stc_tmra_pwm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Macros TMRA Global Macros + * @{ + */ + +/** + * @defgroup TMRA_Count_Src TMRA Count Source + * @{ + */ +#define TMRA_CNT_SRC_SW (0U) /*!< Clock source is PCLK. */ +#define TMRA_CNT_SRC_HW (1U) /*!< Clock source is from external pin or peripheral event. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Channel TMRA Channel + * @{ + */ +#define TMRA_CH1 (0U) /*!< Channel 1 of TMRA. */ +#define TMRA_CH2 (1U) /*!< Channel 2 of TMRA. */ +#define TMRA_CH3 (2U) /*!< Channel 3 of TMRA. */ +#define TMRA_CH4 (3U) /*!< Channel 4 of TMRA. */ +#define TMRA_CH5 (4U) /*!< Channel 5 of TMRA. */ +#define TMRA_CH6 (5U) /*!< Channel 6 of TMRA. */ +#define TMRA_CH7 (6U) /*!< Channel 7 of TMRA. */ +#define TMRA_CH8 (7U) /*!< Channel 8 of TMRA. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Dir TMRA Count Direction + * @{ + */ +#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */ +#define TMRA_DIR_UP (TMRA_BCSTRL_DIR) /*!< TMRA count up. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Mode TMRA Count Mode + * @{ + */ +#define TMRA_MD_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */ +#define TMRA_MD_TRIANGLE (TMRA_BCSTRL_MODE) /*!< Count mode is triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Function_Mode TMRA TMRA Function Mode + * @{ + */ +#define TMRA_FUNC_CMP (0x0U) /*!< Function mode of TMRA channel is ouput compare. */ +#define TMRA_FUNC_CAPT (TMRA_CCONR_CAPMD) /*!< Function mode of TMRA channel is input capture. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Reload_En TMRA Count Reload + * @{ + */ +#define TMRA_CNT_RELOAD_DISABLE (TMRA_BCSTRH_OVSTP) /*!< Stop when counter overflow/underflow. */ +#define TMRA_CNT_RELOAD_ENABLE (0U) /*!< When counter overflow/underflow, counter reload to continue counting. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Clock_Divider TMRA Clock Divider + * @{ + */ +#define TMRA_CLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */ +#define TMRA_CLK_DIV2 (0x1U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 2. */ +#define TMRA_CLK_DIV4 (0x2U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 4. */ +#define TMRA_CLK_DIV8 (0x3U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 8. */ +#define TMRA_CLK_DIV16 (0x4U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 16. */ +#define TMRA_CLK_DIV32 (0x5U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 32. */ +#define TMRA_CLK_DIV64 (0x6U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 64. */ +#define TMRA_CLK_DIV128 (0x7U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 128. */ +#define TMRA_CLK_DIV256 (0x8U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 256. */ +#define TMRA_CLK_DIV512 (0x9U << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 512. */ +#define TMRA_CLK_DIV1024 (0xAU << TMRA_BCSTRL_CKDIV_POS) /*!< The clock source of TMRA is PCLK / 1024. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin TMRA Pin With Filter + * @{ + */ +#define TMRA_PIN_TRIG (0U) /*!< Pin TIMA__TRIG. */ +#define TMRA_PIN_CLKA (1U) /*!< Pin TIMA__CLKA. */ +#define TMRA_PIN_CLKB (2U) /*!< Pin TIMA__CLKB. */ +#define TMRA_PIN_PWM1 (3U) /*!< Pin TIMA__PWM1. */ +#define TMRA_PIN_PWM2 (4U) /*!< Pin TIMA__PWM2. */ +#define TMRA_PIN_PWM3 (5U) /*!< Pin TIMA__PWM3. */ +#define TMRA_PIN_PWM4 (6U) /*!< Pin TIMA__PWM4. */ +#define TMRA_PIN_PWM5 (7U) /*!< Pin TIMA__PWM5. */ +#define TMRA_PIN_PWM6 (8U) /*!< Pin TIMA__PWM6. */ +#define TMRA_PIN_PWM7 (9U) /*!< Pin TIMA__PWM7. */ +#define TMRA_PIN_PWM8 (10U) /*!< Pin TIMA__PWM8. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Up_Condition TMRA Hardware Count Up Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_UP_COND_INVD (0U) /*!< TMRA hardware count up condition is INVALID. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_RISING (TMRA_HCUPR_HCUP0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCUPR_HCUP1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCUPR_HCUP2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCUPR_HCUP3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_RISING (TMRA_HCUPR_HCUP4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCUPR_HCUP5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCUPR_HCUP6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCUPR_HCUP7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_RISING (TMRA_HCUPR_HCUP8) /*!< When a rising edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_TRIG_FALLING (TMRA_HCUPR_HCUP9) /*!< When a falling edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CNT_UP_COND_EVT (TMRA_HCUPR_HCUP10) /*!< When the TMRA common trigger event occurred, the counter register counts up. */ +#define TMRA_CNT_UP_COND_SYM_OVF (TMRA_HCUPR_HCUP11) /*!< When the symmetric unit overflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_SYM_UDF (TMRA_HCUPR_HCUP12) /*!< When the symmetric unit underflow, the counter register counts up. */ +#define TMRA_CNT_UP_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Hard_Count_Down_Condition TMRA Hardware Count Down Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ...; unit 11 and 12. + * @{ + */ +#define TMRA_CNT_DOWN_COND_INVD (0U) /*!< TMRA hardware count down condition is INVALID. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_RISING (TMRA_HCDOR_HCDO0) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_LOW_CLKB_FALLING (TMRA_HCDOR_HCDO1) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_RISING (TMRA_HCDOR_HCDO2) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKA_HIGH_CLKB_FALLING (TMRA_HCDOR_HCDO3) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_RISING (TMRA_HCDOR_HCDO4) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_LOW_CLKA_FALLING (TMRA_HCDOR_HCDO5) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING (TMRA_HCDOR_HCDO6) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_FALLING (TMRA_HCDOR_HCDO7) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_RISING (TMRA_HCDOR_HCDO8) /*!< When a rising edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_TRIG_FALLING (TMRA_HCDOR_HCDO9) /*!< When a falling edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_EVT (TMRA_HCDOR_HCDO10) /*!< When the TMRA common trigger event occurred, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_SYM_OVF (TMRA_HCDOR_HCDO11) /*!< When the symmetric unit overflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_SYM_UDF (TMRA_HCDOR_HCDO12) /*!< When the symmetric unit underflow, the counter register counts down. */ +#define TMRA_CNT_DOWN_COND_ALL (0x1FFFU) +/** + * @} + */ + +/** + * @defgroup TMRA_Interrupt_Type TMRA Interrupt Type + * @{ + */ +#define TMRA_INT_OVF (1UL << 4U) /*!< The interrupt of counting overflow. */ +#define TMRA_INT_UDF (1UL << 5U) /*!< The interrupt of counting underflow. */ +#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */ +#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */ +#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */ +#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */ +#define TMRA_INT_CMP_CH5 (1UL << 20U) /*!< The interrupt of compare-match of channel 5. */ +#define TMRA_INT_CMP_CH6 (1UL << 21U) /*!< The interrupt of compare-match of channel 6. */ +#define TMRA_INT_CMP_CH7 (1UL << 22U) /*!< The interrupt of compare-match of channel 7. */ +#define TMRA_INT_CMP_CH8 (1UL << 23U) /*!< The interrupt of compare-match of channel 8. */ +#define TMRA_INT_ALL (0xFF0030UL) +/** + * @} + */ + +/** + * @defgroup TMRA_Event_Type TMRA Event Type + * @{ + */ +#define TMRA_EVT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */ +#define TMRA_EVT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */ +#define TMRA_EVT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */ +#define TMRA_EVT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */ +#define TMRA_EVT_CMP_CH5 (TMRA_ECONR_ETEN5) /*!< The event of compare-match of channel 5. */ +#define TMRA_EVT_CMP_CH6 (TMRA_ECONR_ETEN6) /*!< The event of compare-match of channel 6. */ +#define TMRA_EVT_CMP_CH7 (TMRA_ECONR_ETEN7) /*!< The event of compare-match of channel 7. */ +#define TMRA_EVT_CMP_CH8 (TMRA_ECONR_ETEN8) /*!< The event of compare-match of channel 8. */ +#define TMRA_EVT_ALL (TMRA_EVT_CMP_CH1 | TMRA_EVT_CMP_CH2 | TMRA_EVT_CMP_CH3 | \ + TMRA_EVT_CMP_CH4 | TMRA_EVT_CMP_CH5 | TMRA_EVT_CMP_CH6 | \ + TMRA_EVT_CMP_CH7 | TMRA_EVT_CMP_CH8) +/** + * @} + */ + +/** + * @defgroup TMRA_Status_Flag TMRA Status Flag + * @{ + */ +#define TMRA_FLAG_OVF (1UL << 6U) /*!< The flag of counting overflow. */ +#define TMRA_FLAG_UDF (1UL << 7U) /*!< The flag of counting underflow. */ +#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */ +#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */ +#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */ +#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */ +#define TMRA_FLAG_CMP_CH5 (1UL << 20U) /*!< The flag of compare-match of channel 5. */ +#define TMRA_FLAG_CMP_CH6 (1UL << 21U) /*!< The flag of compare-match of channel 6. */ +#define TMRA_FLAG_CMP_CH7 (1UL << 22U) /*!< The flag of compare-match of channel 7. */ +#define TMRA_FLAG_CMP_CH8 (1UL << 23U) /*!< The flag of compare-match of channel 8. */ +#define TMRA_FLAG_CAPT_AGAIN_CH1 (1UL << 24U) /*!< The flag of capture occurs again after successful capture of channel 1. */ +#define TMRA_FLAG_CAPT_AGAIN_CH2 (1UL << 25U) /*!< The flag of capture occurs again after successful capture of channel 2. */ +#define TMRA_FLAG_CAPT_AGAIN_CH3 (1UL << 26U) /*!< The flag of capture occurs again after successful capture of channel 3. */ +#define TMRA_FLAG_CAPT_AGAIN_CH4 (1UL << 27U) /*!< The flag of capture occurs again after successful capture of channel 4. */ +#define TMRA_FLAG_CAPT_AGAIN_CH5 (1UL << 28U) /*!< The flag of capture occurs again after successful capture of channel 5. */ +#define TMRA_FLAG_CAPT_AGAIN_CH6 (1UL << 29U) /*!< The flag of capture occurs again after successful capture of channel 6. */ +#define TMRA_FLAG_CAPT_AGAIN_CH7 (1UL << 30U) /*!< The flag of capture occurs again after successful capture of channel 7. */ +#define TMRA_FLAG_CAPT_AGAIN_CH8 (1UL << 31U) /*!< The flag of capture occurs again after successful capture of channel 8. */ +#define TMRA_FLAG_ALL (0xFFFF0C0UL) +/** + * @} + */ + +/** + * @defgroup TMRA_Capture_Cond TMRA Capture Condition + * @note 'TMRA_CAPT_COND_TRIG_RISING' and 'TMRA_CAPT_COND_TRIG_FALLING' are only valid for channel 4. + * @{ + */ +#define TMRA_CAPT_COND_INVD (0x0U) /*!< The condition of capture is INVALID. */ +#define TMRA_CAPT_COND_PWM_RISING (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_PWM_FALLING (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_EVT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */ +#define TMRA_CAPT_COND_TRIG_RISING (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 3. */ +#define TMRA_CAPT_COND_TRIG_FALLING (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA__TRIG. + This condition is only valid for channel 3. */ +#define TMRA_CAPT_COND_XOR_RISING (TMRA_CCONR_HICP5) /*!< The condition of capture is TIMA__CLKA XOR TIMA__CLKB == 1. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_XOR_FALLING (TMRA_CCONR_HICP6) /*!< The condition of capture is TIMA__CLKA XOR TIMA__CLKB == 0. + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWM_RISING | TMRA_CAPT_COND_PWM_FALLING | \ + TMRA_CAPT_COND_EVT | TMRA_CAPT_COND_TRIG_RISING | \ + TMRA_CAPT_COND_TRIG_FALLING | TMRA_CAPT_COND_XOR_RISING | \ + TMRA_CAPT_COND_XOR_FALLING) + +/** + * @} + */ + +/** + * @defgroup TMRA_Cmp_Value_Buf_Trans_Cond TMRA Compare Value Buffer Transmission Condition + * @{ + */ +#define TMRA_BUF_TRANS_COND_OVF_UDF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode. + When counting overflow or underflow or counting register was cleared, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +#define TMRA_BUF_TRANS_COND_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,.... */ +#define TMRA_BUF_TRANS_COND_PEAK_VALLEY (TMRA_BCONR_BSE1 | \ + TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak or valley, + transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). */ +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider + * @{ + */ +#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is the clock of TimerA / 1 */ +#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is the clock of TimerA / 4 */ +#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is the clock of TimerA / 16 */ +#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is the clock of TimerA / 64 */ +/** + * @} + */ + +/** + * @defgroup TMRA_Counter_State TMRA Counter State + * @{ + */ +#define TMRA_CNT_STAT_START (0U) /*!< Counter start counting. */ +#define TMRA_CNT_STAT_STOP (1U) /*!< Counter stop counting. */ +#define TMRA_CNT_STAT_MATCH_CMP (2U) /*!< Counter value matches the compare value. */ +#define TMRA_CNT_STAT_MATCH_PERIOD (3U) /*!< Counter value matches the period value. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Polarity TMRA PWM Polarity + * @{ + */ +#define TMRA_PWM_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_HIGH (0x1U) /*!< PWM output high. */ +#define TMRA_PWM_HOLD (0x2U) /*!< PWM output holds the current polarity. */ +#define TMRA_PWM_INVT (0x3U) /*!< PWM output reverses the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity + * @{ + */ +#define TMRA_PWM_FORCE_INVD (0x0U) /*!< Force polarity is invalid. */ +#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC) /*!< Force the PWM output high at the beginning of the next cycle. + The beginning of the next cycle: overflow position or underflow position + of sawtooth wave; valley position of triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition + * @{ + */ +#define TMRA_START_COND_INVD (0x0U) /*!< The condition of start is INVALID. */ +#define TMRA_START_COND_TRIG_RISING (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_TRIG_FALLING (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. + 2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_EVT (TMRA_HCONR_HSTA2) /*!< The condition is that the TMRA common trigger event has occurred. */ +#define TMRA_START_COND_ALL (TMRA_START_COND_TRIG_RISING | TMRA_START_COND_TRIG_FALLING | \ + TMRA_START_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition + * @{ + */ +#define TMRA_STOP_COND_INVD (0x0U) /*!< The condition of stop is INVALID. */ +#define TMRA_STOP_COND_TRIG_RISING (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_TRIG_FALLING (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_EVT (TMRA_HCONR_HSTP2) /*!< The condition is that the TMRA common trigger event has occurred. */ +#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIG_RISING | TMRA_STOP_COND_TRIG_FALLING | \ + TMRA_STOP_COND_EVT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition + * @note Symmetric units: unit 1 and 2; unit 3 and 4; ... ; unit 11 and 12. + * @{ + */ +#define TMRA_CLR_COND_INVD (0x0U) /*!< The condition of clear is INVALID. */ +#define TMRA_CLR_COND_TRIG_RISING (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_TRIG_FALLING (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_EVT (TMRA_HCONR_HCLE2) /*!< The condition is that the TMRA common trigger event has occurred. */ +#define TMRA_CLR_COND_SYM_TRIG_RISING (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_SYM_TRIG_FALLING (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_PWM3_RISING (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_PWM3_FALLING (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIG_RISING | TMRA_CLR_COND_TRIG_FALLING | \ + TMRA_CLR_COND_EVT| TMRA_CLR_COND_SYM_TRIG_RISING | \ + TMRA_CLR_COND_SYM_TRIG_FALLING | TMRA_CLR_COND_PWM3_RISING| \ + TMRA_CLR_COND_PWM3_FALLING) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMRA_Global_Functions + * @{ + */ +/* Base count(use software clock PCLK/HCLK) */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit); +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit); +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint8_t u8Mode); +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint8_t u8Dir); +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint8_t u8Div); + +/* Hardware count */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +/* Set function mode */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func); + +/* Ouput compare */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit); +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit); +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity); +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity); +/* Input capture */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Trigger: hardware trigger to start/stop/clear the counter */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState); + +/* Filter */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div); +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState); + +/* Global */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx); +/* Counting direction, period value, counter value, compare value */ +uint8_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx); + +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value); +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx); +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value); +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch); + +/* Sync start */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState); +/* Reload and continue counting when overflow/underflow */ +void TMRA_CountReloadCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState); + +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond); +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); +void TMRA_SpecialCompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState); + +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag); +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState); +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState); +void TMRA_Start(CM_TMRA_TypeDef *TMRAx); +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx); + +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TMRA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h new file mode 100644 index 0000000000..c51ecfb13b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_trng.h @@ -0,0 +1,128 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.h + * @brief This file contains all the functions prototypes of the TRNG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_TRNG_H__ +#define __HC32_LL_TRNG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_TRNG + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup TRNG_Global_Macros TRNG Global Macros + * @{ + */ + +/** + * @defgroup TRNG_Reload_Init_Value TRNG Reload Initial Value + * @{ + */ +#define TRNG_RELOAD_INIT_VAL_ENABLE (TRNG_MR_LOAD) /* Enable reload new initial value. */ +#define TRNG_RELOAD_INIT_VAL_DISABLE (0x0U) /* Disable reload new initial value. */ +/** + * @} + */ + +/** + * @defgroup TRNG_Shift_Ctrl TRNG Shift Control + * @{ + */ +#define TRNG_SHIFT_CNT32 (0x3UL << TRNG_MR_CNT_POS) /* Shift 32 times when capturing random noise. */ +#define TRNG_SHIFT_CNT64 (0x4UL << TRNG_MR_CNT_POS) /* Shift 64 times when capturing random noise. */ +#define TRNG_SHIFT_CNT128 (0x5UL << TRNG_MR_CNT_POS) /* Shift 128 times when capturing random noise. */ +#define TRNG_SHIFT_CNT256 (0x6UL << TRNG_MR_CNT_POS) /* Shift 256 times when capturing random noise. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TRNG_Global_Functions + * @{ + */ +int32_t TRNG_DeInit(void); +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn); +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint32_t u32RandomLen); + +void TRNG_Start(void); +void TRNG_Cmd(en_functional_state_t enNewState); +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen); +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h new file mode 100644 index 0000000000..4f8d067c9b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_usart.h @@ -0,0 +1,543 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.h + * @brief This file contains all the functions prototypes of the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter) driver library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Remove u32StopBit param from stc_usart_smartcard_init_t structure + 2023-12-15 CDT Add the declaration of API USART_GetFuncState() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_USART_H__ +#define __HC32_LL_USART_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_USART + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup USART_Global_Types USART Global Types + * @{ + */ + +/** + * @brief clock synchronization mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_clocksync_init_t; + +/** + * @brief UART multiple-processor initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_multiprocessor_init_t; + +/** + * @brief UART mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Width_Bit */ + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bit */ + uint32_t u32Parity; /*!< Parity format. + This parameter can be a value of @ref USART_Parity_Control */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ + uint32_t u32StartBitPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Polarity */ + uint32_t u32HWFlowControl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_uart_init_t; + +/** + * @brief LIN mode initialization structure definition + * @note The parameter(u32ClockDiv/u32CKOutput/u32Baudrate) is valid when clock source is the internal clock. + */ +typedef struct { + uint32_t u32ClockSrc; /*!< Clock Source. + This parameter can be a value of @ref USART_Clock_Source */ + uint32_t u32ClockDiv; /*!< Clock division. + This parameter can be a value of @ref USART_Clock_Division. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. + This parameter can be a value of @ref USART_CK_Output_Selection. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is valid when clock source is the internal clock. */ + uint32_t u32OverSampleBit; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Over_Sample_Bit */ + uint32_t u32BmcClockDiv; /*!< BMC clock division. + This parameter can be a value of @ref USART_LIN_BMC_Clock_Division. + @note The clock division is valid when clock source is the internal clock. */ + uint32_t u32DetectBreakLen; /*!< Detect break length. + This parameter can be a value of @ref USART_LIN_Detect_Break_Length */ + uint32_t u32SendBreakLen; /*!< Send break length. + This parameter can be a value of @ref USART_LIN_Send_Break_Length */ + uint32_t u32SendBreakMode; /*!< Send break mode. + This parameter can be a value of @ref USART_LIN_Send_Break_Mode */ +} stc_usart_lin_init_t; + +/** + * @brief Smartcard mode initialization structure definition + */ +typedef struct { + uint32_t u32ClockDiv; /*!< Clock division. This parameter can be a value of @ref USART_Clock_Division. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32CKOutput; /*!< USART_CK output selection. This parameter can be a value of @ref USART_CK_Output_Selection. + @note This parameter is valid when clock source is the internal clock. */ + uint32_t u32Baudrate; /*!< USART baudrate. + This parameter is calculated according with smartcard default ETU and clock. */ + uint32_t u32FirstBit; /*!< Significant bit. + This parameter can be a value of @ref USART_First_Bit */ +} stc_usart_smartcard_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Global_Macros USART Global Macros + * @{ + */ + +/** + * @defgroup USART_Flag USART Flag + * @{ + */ +#define USART_FLAG_RX_FULL (USART_SR_RXNE) /*!< Receive data register not empty flag */ +#define USART_FLAG_OVERRUN (USART_SR_ORE) /*!< Overrun error flag */ +#define USART_FLAG_TX_CPLT (USART_SR_TC) /*!< Transmission complete flag */ +#define USART_FLAG_TX_EMPTY (USART_SR_TXE) /*!< Transmit data register empty flag */ +#define USART_FLAG_FRAME_ERR (USART_SR_FE) /*!< Framing error flag */ +#define USART_FLAG_PARITY_ERR (USART_SR_PE) /*!< Parity error flag */ +#define USART_FLAG_MX_PROCESSOR (USART_SR_MPB) /*!< Receive processor ID flag */ +#define USART_FLAG_RX_TIMEOUT (USART_SR_RTOF) /*!< Receive timeout flag */ +#define USART_FLAG_LIN_ERR (USART_SR_BE) /*!< LIN bus error flag */ +#define USART_FLAG_LIN_WKUP (USART_SR_WKUP) /*!< LIN wakeup signal detection flag */ +#define USART_FLAG_LIN_BREAK (USART_SR_LBD) /*!< LIN break signal detection flag */ +#define USART_FLAG_TX_END (USART_SR_TEND) /*!< Transmission complete flag (can be cleared) */ + +#define USART_FLAG_ALL (USART_FLAG_RX_FULL | USART_FLAG_FRAME_ERR | USART_FLAG_TX_EMPTY | \ + USART_FLAG_OVERRUN | USART_FLAG_PARITY_ERR | USART_FLAG_RX_TIMEOUT | \ + USART_FLAG_TX_CPLT | USART_FLAG_LIN_BREAK | USART_FLAG_LIN_WKUP | \ + USART_FLAG_LIN_ERR | USART_FLAG_MX_PROCESSOR | USART_FLAG_TX_END) + +/** + * @} + */ + +/** + * @defgroup USART_Transmission_Type USART Transmission Type + * @{ + */ +#define USART_TRANS_DATA (0UL) +#define USART_TRANS_ID (USART_TDR_MPID) +/** + * @} + */ + +/** + * @defgroup USART_Function USART Function + * @{ + */ +#define USART_TX (USART_CR1_TE) /*!< USART TX function */ +#define USART_RX (USART_CR1_RE) /*!< USART RX function */ +#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */ +#define USART_INT_TX_CPLT (USART_CR1_TCIE) /*!< USART transmission complete interrupt */ +#define USART_INT_TX_EMPTY (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */ +#define USART_RX_TIMEOUT (USART_CR1_RTOE) /*!< USART RX timeout function */ +#define USART_INT_RX_TIMEOUT (USART_CR1_RTOIE) /*!< USART RX timeout interrupt */ +#define USART_INT_TX_END (USART_CR1_TENDIE) /*!< USART transmission complete interrupt */ +#define USART_LIN (USART_CR2_LINEN << 16UL) /*!< USART LIN function */ +#define USART_LIN_WKUP (USART_CR2_WKUPE << 16UL) /*!< USART LIN wakeup signal detect function */ +#define USART_LIN_ERR (USART_CR2_BEE << 16UL) /*!< USART LIN bus error detect function */ +#define USART_LIN_BREAK (USART_CR2_LBDL << 16UL) /*!< USART LIN bus break field detect function */ +#define USART_LIN_INT_ERR (USART_CR2_BEIE << 16UL) /*!< USART LIN bus error detect interrupt function */ +#define USART_LIN_INT_BREAK (USART_CR2_LBDIE << 16UL) /*!< USART LIN bus break field detect interrupt function */ +#define USART_LIN_INT_WKUP (USART_CR2_WKUPIE << 16UL) /*!< USART LIN bus wakeup signal detect interrupt function */ + +#define USART_FUNC_ALL (USART_TX | USART_RX | USART_INT_RX | USART_INT_TX_CPLT | USART_RX_TIMEOUT | \ + USART_INT_RX_TIMEOUT | USART_INT_TX_EMPTY | USART_LIN | USART_LIN_WKUP | \ + USART_LIN_ERR | USART_LIN_BREAK | USART_LIN_INT_ERR | USART_LIN_INT_BREAK | \ + USART_LIN_INT_WKUP | USART_INT_TX_END) + +/** + * @} + */ + +/** + * @defgroup USART_Parity_Control USART Parity Control + * @{ + */ +#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */ +#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */ +#define USART_PARITY_ODD (USART_CR1_PCE | \ + USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** + * @defgroup USART_Data_Width_Bit USART Data Width Bit + * @{ + */ +#define USART_DATA_WIDTH_8BIT (0UL) /*!< 8 bits */ +#define USART_DATA_WIDTH_9BIT (USART_CR1_M) /*!< 9 bits */ +/** + * @} + */ + +/** + * @defgroup USART_Over_Sample_Bit USART Over Sample Bit + * @{ + */ +#define USART_OVER_SAMPLE_16BIT (0UL) /*!< Oversampling by 16 bits */ +#define USART_OVER_SAMPLE_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */ +/** + * @} + */ + +/** + * @defgroup USART_First_Bit USART First Bit + * @{ + */ +#define USART_FIRST_BIT_LSB (0UL) /*!< LSB(Least Significant Bit) */ +#define USART_FIRST_BIT_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */ +/** + * @} + */ + +/** + * @defgroup USART_Start_Bit_Polarity USART Start Bit Polarity + * @{ + */ +#define USART_START_BIT_LOW (0UL) /*!< Detect RX pin low level */ +#define USART_START_BIT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Source USART Clock Source + * @{ + */ +#define USART_CLK_SRC_INTERNCLK (0UL) /*!< Select internal clock source and don't output clock */ +#define USART_CLK_SRC_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */ +/** + * @} + */ + +/** + * @defgroup USART_CK_Output_Selection USART_CK Output Selection + * @{ + */ +#define USART_CK_OUTPUT_DISABLE (0UL) /*!< Disable USART_CK output */ +#define USART_CK_OUTPUT_ENABLE (USART_CR2_CLKC_0) /*!< Enable USART_CK output. */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Bit USART Stop Bit + * @{ + */ +#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */ +#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */ +/** + * @} + */ + +/** + * @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control + * @{ + */ +#define USART_HW_FLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */ +#define USART_HW_FLOWCTRL_RTS (USART_CR3_CTSE >> 1U) /*!< USART hardware flow control RTS mode */ +#define USART_HW_FLOWCTRL_NONE (0UL) /*!< Disable USART hardware flow control */ +#define USART_HW_FLOWCTRL_RTS_CTS (USART_HW_FLOWCTRL_CTS | \ + USART_HW_FLOWCTRL_RTS) /*!< USART hardware flow control RTS and CTS mode */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Division USART Clock Division + * @{ + */ +#define USART_CLK_DIV1 (0UL) /*!< CLK */ +#define USART_CLK_DIV4 (1UL) /*!< CLK/4 */ +#define USART_CLK_DIV16 (2UL) /*!< CLK/16 */ +#define USART_CLK_DIV64 (3UL) /*!< CLK/64 */ +#define USART_CLK_DIV128 (0UL | USART_PR_ULBREN) /*!< CLK/128 */ +#define USART_CLK_DIV256 (1UL | USART_PR_ULBREN) /*!< CLK/256 */ +#define USART_CLK_DIV512 (2UL | USART_PR_ULBREN) /*!< CLK/512 */ +#define USART_CLK_DIV1024 (3UL | USART_PR_ULBREN) /*!< CLK/1024 */ +/** + * @} + */ + +/** + * @defgroup USART_Max_Timeout USART Max Timeout + * @{ + */ +#define USART_MAX_TIMEOUT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock + * @{ + */ +#define USART_SC_ETU_CLK32 (0UL << USART_CR3_BCN_POS) /*!< 1 etu = 32/f */ +#define USART_SC_ETU_CLK64 (1UL << USART_CR3_BCN_POS) /*!< 1 etu = 64/f */ +#define USART_SC_ETU_CLK128 (3UL << USART_CR3_BCN_POS) /*!< 1 etu = 128/f */ +#define USART_SC_ETU_CLK256 (5UL << USART_CR3_BCN_POS) /*!< 1 etu = 256/f */ +#define USART_SC_ETU_CLK372 (6UL << USART_CR3_BCN_POS) /*!< 1 etu = 372/f */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Mode_Noise_Filter_Width_Level USART Stop Mode Noise Filter Width Level + * @{ + */ +#define USART_STOP_MD_FILTER_LVL1 (0UL) /*!< Filter width level 1 */ +#define USART_STOP_MD_FILTER_LVL2 (PERIC_USART1_NFC_USASRT1_NFS_0) /*!< Filter width level 2 */ +#define USART_STOP_MD_FILTER_LVL3 (PERIC_USART1_NFC_USASRT1_NFS_1) /*!< Filter width level 3 */ +#define USART_STOP_MD_FILTER_LVL4 (PERIC_USART1_NFC_USASRT1_NFS) /*!< Filter width level 4 */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_BMC_Clock_Division USART LIN Baudrate Measure Counter Clock Division + * @{ + */ +#define USART_LIN_BMC_CLK_DIV1 (0UL) /*!< CLK */ +#define USART_LIN_BMC_CLK_DIV2 (USART_PR_LBMPSC_0) /*!< CLK/2 */ +#define USART_LIN_BMC_CLK_DIV4 (USART_PR_LBMPSC_1) /*!< CLK/4 */ +#define USART_LIN_BMC_CLK_DIV8 (USART_PR_LBMPSC) /*!< CLK/8 */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Send_Break_Mode USART LIN Send Break Mode + * @{ + */ +#define USART_LIN_SEND_BREAK_MD_SBK (0UL) /*!< Start send break after USART_CR2 SBK bit set 1 value */ +#define USART_LIN_SEND_BREAK_MD_TDR (USART_CR2_SBKM) /*!< Start send break after USART_DR TDR write 0x00 value */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Detect_Break_Length USART LIN Detect Break Length + * @{ + */ +#define USART_LIN_DETECT_BREAK_10BIT (0UL) /*!< Detect break 10-bit */ +#define USART_LIN_DETECT_BREAK_11BIT (USART_CR2_LBDL) /*!< Detect break 11-bit */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Send_Break_Length USART LIN Send Break Length + * @{ + */ +#define USART_LIN_SEND_BREAK_10BIT (0UL) /*!< Send break 10-bit */ +#define USART_LIN_SEND_BREAK_11BIT (USART_CR2_SBKL_0) /*!< Send break 11-bit */ +#define USART_LIN_SEND_BREAK_13BIT (USART_CR2_SBKL_1) /*!< Send break 13-bit */ +#define USART_LIN_SEND_BREAK_14BIT (USART_CR2_SBKL) /*!< Send break 14-bit */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup USART_Global_Functions + * @{ + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit); +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error); +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit); +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error); +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit); +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error); + +int32_t USART_HalfDuplex_Init(CM_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error); + +int32_t USART_LIN_StructInit(stc_usart_lin_init_t *pstcLinInit); +int32_t USART_LIN_Init(CM_USART_TypeDef *USARTx, const stc_usart_lin_init_t *pstcLinInit, float32_t *pf32Error); + +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit); +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error); + +int32_t USART_DeInit(CM_USART_TypeDef *USARTx); +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState); +en_functional_state_t USART_GetFuncState(CM_USART_TypeDef *USARTx, uint32_t u32Func); +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity); +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit); +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit); +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth); +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit); +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity); +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint16_t u16Type); +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv); +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx); +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc); +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx); +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl); +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx); +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data); +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID); + +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error); + +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock); + +void USART_StopModeNoiseFilterCmd(const CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_SetStopModeNoiseFilter(const CM_USART_TypeDef *USARTx, uint32_t u32Level); + +void USART_LIN_LoopbackCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState); +void USART_LIN_SetBmcClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv); +void USART_LIN_RequestBreakSending(CM_USART_TypeDef *USARTx); +en_flag_status_t USART_LIN_GetRequestBreakStatus(const CM_USART_TypeDef *USARTx); +void USART_LIN_SetBreakMode(CM_USART_TypeDef *USARTx, uint32_t u32Mode); +uint32_t USART_LIN_GetBreakMode(const CM_USART_TypeDef *USARTx); +uint32_t USART_LIN_GetMeasureCount(const CM_USART_TypeDef *USARTx); +uint32_t USART_LIN_GetMeasureBaudrate(const CM_USART_TypeDef *USARTx); +void USART_LIN_SetDetectBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len); +void USART_LIN_SetSendBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len); + +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout); +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout); + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h new file mode 100644 index 0000000000..8b4d1cfa54 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_utility.h @@ -0,0 +1,131 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.h + * @brief This file contains all the functions prototypes of the DDL utility. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_UTILITY_H__ +#define __HC32_LL_UTILITY_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_UTILITY + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup UTILITY_Global_Functions + * @{ + */ + +/* Imprecise delay */ +void DDL_DelayMS(uint32_t u32Count); +void DDL_DelayUS(uint32_t u32Count); + +/* Systick functions */ +int32_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +#if (LL_PRINT_ENABLE == DDL_ON) +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)); +#endif + +/* You can add your own assert functions by implement the function DDL_AssertHandler + definition follow the function DDL_AssertHandler declaration */ +#ifdef __DEBUG +#define DDL_ASSERT(x) \ +do { \ + ((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \ +} while (0) +/* Exported function */ +void DDL_AssertHandler(const char *file, int line); +#else +#define DDL_ASSERT(x) ((void)0U) +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) +#include +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData); + +#define DDL_PrintfInit (void)LL_PrintfInit +#define DDL_Printf (void)printf +#else +#define DDL_PrintfInit(vpDevice, u32Param, pfnPreinit) +#define DDL_Printf(...) +#endif + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h new file mode 100644 index 0000000000..de69cf718c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/inc/hc32_ll_wdt.h @@ -0,0 +1,228 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.h + * @brief This file contains all the functions prototypes of the WDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Modify macro define: WDT_LPM_CNT_CONTINUE -> WDT_LPM_CNT_CONT + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_LL_WDT_H__ +#define __HC32_LL_WDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#include "hc32f4xx.h" +#include "hc32f4xx_conf.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @addtogroup LL_WDT + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Types WDT Global Types + * @{ + */ + +/** + * @brief WDT Init structure definition + */ +typedef struct { + uint32_t u32CountPeriod; /*!< Specifies the counting period of WDT. + This parameter can be a value of @ref WDT_Count_Period */ + uint32_t u32ClockDiv; /*!< Specifies the clock division factor of WDT. + This parameter can be a value of @ref WDT_Clock_Division */ + uint32_t u32RefreshRange; /*!< Specifies the allow refresh range of WDT. + This parameter can be a value of @ref WDT_Refresh_Range */ + uint32_t u32LPMCount; /*!< Specifies the count state in Low Power Mode (Sleep Mode). + This parameter can be a value of @ref WDT_LPM_Count */ + uint32_t u32ExceptionType; /*!< Specifies the type of exception response for WDT. + This parameter can be a value of @ref WDT_Exception_Type */ +} stc_wdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Macros WDT Global Macros + * @{ + */ + +/** + * @defgroup WDT_Count_Period WDT Count Period + * @{ + */ +#define WDT_CNT_PERIOD256 (0UL) /*!< 256 clock cycle */ +#define WDT_CNT_PERIOD4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define WDT_CNT_PERIOD16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define WDT_CNT_PERIOD65536 (WDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup WDT_Clock_Division WDT Clock Division + * @{ + */ +#define WDT_CLK_DIV4 (0x02UL << WDT_CR_CKS_POS) /*!< PLCKx/4 */ +#define WDT_CLK_DIV64 (0x06UL << WDT_CR_CKS_POS) /*!< PLCKx/64 */ +#define WDT_CLK_DIV128 (0x07UL << WDT_CR_CKS_POS) /*!< PLCKx/128 */ +#define WDT_CLK_DIV256 (0x08UL << WDT_CR_CKS_POS) /*!< PLCKx/256 */ +#define WDT_CLK_DIV512 (0x09UL << WDT_CR_CKS_POS) /*!< PLCKx/512 */ +#define WDT_CLK_DIV1024 (0x0AUL << WDT_CR_CKS_POS) /*!< PLCKx/1024 */ +#define WDT_CLK_DIV2048 (0x0BUL << WDT_CR_CKS_POS) /*!< PLCKx/2048 */ +#define WDT_CLK_DIV8192 (0x0DUL << WDT_CR_CKS_POS) /*!< PLCKx/8192 */ +/** + * @} + */ + +/** + * @defgroup WDT_Refresh_Range WDT Refresh Range + * @{ + */ +#define WDT_RANGE_0TO25PCT (0x01UL << WDT_CR_WDPT_POS) /*!< 0%~25% */ +#define WDT_RANGE_25TO50PCT (0x02UL << WDT_CR_WDPT_POS) /*!< 25%~50% */ +#define WDT_RANGE_0TO50PCT (0x03UL << WDT_CR_WDPT_POS) /*!< 0%~50% */ +#define WDT_RANGE_50TO75PCT (0x04UL << WDT_CR_WDPT_POS) /*!< 50%~75% */ +#define WDT_RANGE_0TO25PCT_50TO75PCT (0x05UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~75% */ +#define WDT_RANGE_25TO75PCT (0x06UL << WDT_CR_WDPT_POS) /*!< 25%~75% */ +#define WDT_RANGE_0TO75PCT (0x07UL << WDT_CR_WDPT_POS) /*!< 0%~75% */ +#define WDT_RANGE_75TO100PCT (0x08UL << WDT_CR_WDPT_POS) /*!< 75%~100% */ +#define WDT_RANGE_0TO25PCT_75TO100PCT (0x09UL << WDT_CR_WDPT_POS) /*!< 0%~25% & 75%~100% */ +#define WDT_RANGE_25TO50PCT_75TO100PCT (0x0AUL << WDT_CR_WDPT_POS) /*!< 25%~50% & 75%~100% */ +#define WDT_RANGE_0TO50PCT_75TO100PCT (0x0BUL << WDT_CR_WDPT_POS) /*!< 0%~50% & 75%~100% */ +#define WDT_RANGE_50TO100PCT (0x0CUL << WDT_CR_WDPT_POS) /*!< 50%~100% */ +#define WDT_RANGE_0TO25PCT_50TO100PCT (0x0DUL << WDT_CR_WDPT_POS) /*!< 0%~25% & 50%~100% */ +#define WDT_RANGE_25TO100PCT (0x0EUL << WDT_CR_WDPT_POS) /*!< 25%~100% */ +#define WDT_RANGE_0TO100PCT (0x0FUL << WDT_CR_WDPT_POS) /*!< 0%~100% */ +/** + * @} + */ + +/** + * @defgroup WDT_LPM_Count WDT Low Power Mode Count + * @brief Counting control of WDT in sleep mode. + * @{ + */ +#define WDT_LPM_CNT_CONT (0UL) /*!< Continue counting in sleep mode */ +#define WDT_LPM_CNT_STOP (WDT_CR_SLPOFF) /*!< Stop counting in sleep mode */ +/** + * @} + */ + +/** + * @defgroup WDT_Exception_Type WDT Exception Type + * @brief Specifies the exception response when a refresh error or count overflow occurs. + * @{ + */ +#define WDT_EXP_TYPE_INT (0UL) /*!< WDT trigger interrupt */ +#define WDT_EXP_TYPE_RST (WDT_CR_ITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup WDT_Flag WDT Flag + * @{ + */ +#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */ +#define WDT_FLAG_REFRESH (WDT_SR_REF) /*!< Refresh error flag */ +#define WDT_FLAG_ALL (WDT_SR_UDF | WDT_SR_REF) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup WDT_Global_Functions + * @{ + */ + +/** + * @brief Get WDT count value. + * @param None + * @retval uint16_t Count value + */ +__STATIC_INLINE uint16_t WDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_WDT->SR) & WDT_SR_CNT); +} + +/* Initialization and configuration functions */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +void WDT_FeedDog(void); +uint16_t WDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag); +int32_t WDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_LL_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll.c new file mode 100644 index 0000000000..30b2c7bdb6 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll.c @@ -0,0 +1,182 @@ +/** + ******************************************************************************* + * @file hc32_ll.c + * @brief This file provides firmware functions to low-level drivers (LL). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_Global Global + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup LL_Global_Functions LL Global Functions + * @{ + */ +void LL_PERIPH_WE(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Unlock all EFM registers */ + EFM_REG_Unlock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Unlock FCG register */ + PWC_FCG0_REG_Unlock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Unlock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Unlock all MPU registers */ + MPU_REG_Unlock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Unlock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Unlock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Unlock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Unlock SRAM register: WTCR, CKCR */ + SRAM_REG_Unlock(); + } +#endif +} + +void LL_PERIPH_WP(uint32_t u32Peripheral) +{ +#if (LL_EFM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_EFM) != 0UL) { + /* Lock all EFM registers */ + EFM_REG_Lock(); + } +#endif +#if (LL_FCG_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_FCG) != 0UL) { + /* Lock FCG register */ + PWC_FCG0_REG_Lock(); + } +#endif +#if (LL_GPIO_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_GPIO) != 0UL) { + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_REG_Lock(); + } +#endif +#if (LL_MPU_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_MPU) != 0UL) { + /* Lock all MPU registers */ + MPU_REG_Lock(); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_LVD) != 0UL) { + /* Lock LVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE2); + } +#endif +#if (LL_PWC_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_PWC_CLK_RMU) != 0UL) { + /* Lock PWC, CLK, RMU registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_REG_Lock(PWC_UNLOCK_CODE0 | PWC_UNLOCK_CODE1); + } +#endif +#if (LL_SRAM_ENABLE == DDL_ON) + if ((u32Peripheral & LL_PERIPH_SRAM) != 0UL) { + /* Lock SRAM register: WTCR, CKCR */ + SRAM_REG_Lock(); + } +#endif +} + +/** + * @brief Software sync start timer + * @param [in] u32Tmr Timer of software sync start + * This parameter can be one or any combination of the macros group @ref Timer_SW_Sync_Start_Global_Macros + * @retval None + */ +void LL_TMR_SWSyncStart(uint32_t u32Tmr) +{ + if ((LL_SW_SYNC_START_TMR_ALL & u32Tmr) != 0UL) { + WRITE_REG32(CM_PERIC->TMR_SYNENR, (LL_SW_SYNC_START_TMR_ALL & u32Tmr)); + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c new file mode 100644 index 0000000000..16c909656a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_adc.c @@ -0,0 +1,1153 @@ +/** + ******************************************************************************* + * @file hc32_ll_adc.c + * @brief This file provides firmware functions to manage the Analog-to-Digital + * Converter(ADC). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + API fixed: ADC_DeInit() + 2023-12-15 CDT Add API ADC_MxChCmd(),ADC_ConvDataAverageMxChCmd + Add API ADC_GetResolution() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_adc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ADC ADC + * @brief Analog-to-Digital Converter Driver Library + * @{ + */ + +#if (LL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Local_Macros ADC Local Macros + * @{ + */ + +#define ADC_RMU_TIMEOUT (100U) + +/** + * @defgroup ADC_AWD_DR_CHSR ADC AWD DR CHSR + * @{ + */ +#define ADC_AWDx_DR(awd, reg_base) (*(__IO uint16_t *)((uint32_t)(reg_base) + ((uint32_t)(awd) * 8U))) +#define ADC_AWDx_CHSR(awd, reg_base) (*(__IO uint8_t *)((uint32_t)(reg_base) + ((uint32_t)(awd) * 8U))) +/** + * @} + */ + +/** + * @defgroup ADC_Channel_Max ADC Channel Max + * @{ + */ +#define ADC1_CH_MAX (ADC_CH15) +#define ADC2_CH_MAX (ADC_CH7) +#define ADC3_CH_MAX (ADC_CH11) +#define ADC1_REMAP_CH_MAX (ADC_CH15) +#define ADC2_REMAP_CH_MAX (ADC_CH7) +#define ADC3_REMAP_CH_MAX (ADC_CH11) +#define ADC1_REMAP_PIN_MAX (ADC1_PIN_PC5) +#define ADC2_REMAP_PIN_MAX (ADC2_PIN_PC1) +#define ADC3_REMAP_PIN_MAX (ADC3_PIN_PB10) +#define ADC_SSTR_NUM (16U) +#define ADC1_SSTR_NUM (ADC_SSTR_NUM) +#define ADC2_SSTR_NUM (8U) +#define ADC3_SSTR_NUM (12U) +/** + * @} + */ + +/** + * @defgroup ADC_Check_Parameters_Validity ADC check parameters validity + * @{ + */ +#define IS_ADC_1BIT_MASK(x) (((x) != 0U) && (((x) & ((x) - 1U)) == 0U)) +#define IS_ADC_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* ADC unit check */ +#define IS_ADC_UNIT(x) \ +( ((x) == CM_ADC1) || \ + ((x) == CM_ADC2) || \ + ((x) == CM_ADC3)) + +/* ADC sequence check */ +#define IS_ADC_SEQ(x) (((x) == ADC_SEQ_A) || ((x) == ADC_SEQ_B)) + +/* ADC channel check */ +#define IS_ADC_CH(adc, ch) \ +( (((adc) == CM_ADC1) && ((ch) <= ADC1_CH_MAX)) || \ + (((adc) == CM_ADC2) && ((ch) <= ADC2_CH_MAX)) || \ + (((adc) == CM_ADC3) && ((ch) <= ADC3_CH_MAX))) + +/* ADC MX channel check */ +#define IS_ADC_MX_CH(adc, ch) \ +( (((adc) == CM_ADC1) && IS_ADC_BIT_MASK(ch, ADC1_MX_CH_ALL)) || \ + (((adc) == CM_ADC2) && IS_ADC_BIT_MASK(ch, ADC2_MX_CH_ALL)) || \ + (((adc) == CM_ADC3) && IS_ADC_BIT_MASK(ch, ADC3_MX_CH_ALL))) + +#define IS_ADC_SCAN_MD(x) \ +( ((x) == ADC_MD_SEQA_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT) || \ + ((x) == ADC_MD_SEQA_SEQB_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_CONT_SEQB_SINGLESHOT) || \ + ((x) == ADC_MD_SEQA_BUF) || \ + ((x) == ADC_MD_SEQA_BUF_SEQB_SINGLESHOT)) + +#define IS_ADC_RESOLUTION(x) \ +( ((x) == ADC_RESOLUTION_8BIT) || \ + ((x) == ADC_RESOLUTION_10BIT) || \ + ((x) == ADC_RESOLUTION_12BIT)) + +#define IS_ADC_HARDTRIG(x) \ +( ((x) == ADC_HARDTRIG_ADTRG_PIN) || \ + ((x) == ADC_HARDTRIG_EVT0) || \ + ((x) == ADC_HARDTRIG_EVT1) || \ + ((x) == ADC_HARDTRIG_EVT0_EVT1)) + +#define IS_ADC_DATAALIGN(x) \ +( ((x) == ADC_DATAALIGN_RIGHT) || \ + ((x) == ADC_DATAALIGN_LEFT)) + +#define IS_ADC_SEQA_RESUME_MD(x) \ +( ((x) == ADC_SEQA_RESUME_SCAN_CONT) || \ + ((x) == ADC_SEQA_RESUME_SCAN_RESTART)) + +#define IS_ADC_SAMPLE_TIME(x) ((x) >= 5U) + +#define IS_ADC_SAMPLE_MD(x) \ +( ((x) == ADC_SAMPLE_MD_NORMAL) || \ + ((x) == ADC_SAMPLE_MD_OVER)) + +#define IS_ADC_OVER_SAMPLE_SHIFT(x) \ +( ((x) == ADC_OVER_SAMPLE_SHIFT_0BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_1BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_2BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_3BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_4BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_5BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_6BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_7BIT) || \ + ((x) == ADC_OVER_SAMPLE_SHIFT_8BIT)) + +#define IS_ADC_INT(x) IS_ADC_BIT_MASK(x, ADC_INT_ALL) +#define IS_ADC_FLAG(x) IS_ADC_BIT_MASK(x, ADC_FLAG_ALL) + +/* Scan-average. */ +#define IS_ADC_AVG_CNT(x) (((x) | ADC_AVG_CNT256) == ADC_AVG_CNT256) + +/* Extended channel. */ +#define IS_ADC_EXTCH_SRC(x) \ +( ((x) == ADC_EXTCH_EXTERN_ANALOG_PIN) || \ + ((x) == ADC_EXTCH_INTERN_ANALOG_SRC)) + +/* Channel remapping. */ +#define IS_ADC_REMAP_PIN(adc, pin) \ +( (((adc) == CM_ADC1) && ((pin) <= ADC1_REMAP_PIN_MAX)) || \ + (((adc) == CM_ADC2) && ((pin) <= ADC2_REMAP_PIN_MAX)) || \ + (((adc) == CM_ADC3) && ((pin) <= ADC3_REMAP_PIN_MAX))) +#define IS_ADC_REMAP_CH(adc, ch) \ +( (((adc) == CM_ADC1) && ((ch) <= ADC1_REMAP_CH_MAX)) || \ + (((adc) == CM_ADC2) && ((ch) <= ADC2_REMAP_CH_MAX)) || \ + (((adc) == CM_ADC3) && ((ch) <= ADC3_REMAP_CH_MAX))) + +/* Sync mode. */ +#define IS_ADC_SYNC_MD(x) \ +( ((x) == ADC_SYNC_SINGLE_DELAY_TRIG) || \ + ((x) == ADC_SYNC_SINGLE_PARALLEL_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_DELAY_TRIG) || \ + ((x) == ADC_SYNC_CYCLIC_PARALLEL_TRIG)) + +#define IS_ADC_SYNC(x) \ +( ((x) == ADC_SYNC_ADC1_ADC2) || \ + ((x) == ADC_SYNC_ADC1_ADC2_ADC3)) + +/* Analog watchdog. */ +#define IS_ADC_AWD_MD(x) \ +( ((x) == ADC_AWD_MD_CMP_OUT) || \ + ((x) == ADC_AWD_MD_CMP_IN)) + +#define IS_ADC_AWD(x) ((x) <= ADC_AWD1) + +/* AWD flag check */ +#define IS_ADC_AWD_FLAG(x) IS_ADC_BIT_MASK(x, ADC_AWD_FLAG_ALL) + +/* Two AWD units */ +#define IS_ADC_AWD_COMB_MD(x) \ +( ((x) == ADC_AWD_COMB_INVD) || \ + ((x) == ADC_AWD_COMB_OR) || \ + ((x) == ADC_AWD_COMB_AND) || \ + ((x) == ADC_AWD_COMB_XOR)) + +#define IS_ADC_AWD_INT(x) IS_ADC_BIT_MASK(x, ADC_AWD_INT_ALL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Functions ADC Global Functions + * @{ + */ + +/** + * @brief Initializes the specified ADC peripheral according to the specified parameters + * in the structure pstcAdcInit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure that contains the + * configuration information for the specified ADC. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_Init(CM_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + if (pstcAdcInit != NULL) { + DDL_ASSERT(IS_ADC_SCAN_MD(pstcAdcInit->u16ScanMode)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcAdcInit->u16Resolution)); + DDL_ASSERT(IS_ADC_DATAALIGN(pstcAdcInit->u16DataAlign)); + /* Configures scan mode, resolution, data align. */ + WRITE_REG16(ADCx->CR0, pstcAdcInit->u16ScanMode | pstcAdcInit->u16Resolution | pstcAdcInit->u16DataAlign); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitialize the specified ADC peripheral registers to their default reset values. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval int32_t: + * - LL_OK: De-Initialize success. + * - LL_ERR_TIMEOUT: Timeout. + */ +int32_t ADC_DeInit(CM_ADC_TypeDef *ADCx) +{ + int32_t i32Ret = LL_OK; + uint32_t u32UnitShift; + uint32_t u32UnitBase; + __IO uint8_t u8TimeOut = 0U; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + /* Check FRST register protect */ + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + /* Reset ADC */ + u32UnitBase = (uint32_t)ADCx; + u32UnitShift = (u32UnitBase - CM_ADC1_BASE) / (CM_ADC2_BASE - CM_ADC1_BASE); + CLR_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_ADC1 << u32UnitShift); + /* Ensure reset procedure is completed */ + while (0UL == READ_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_ADC1 << u32UnitShift)) { + u8TimeOut++; + if (u8TimeOut > ADC_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Set each @ref stc_adc_init_t field to default value. + * @param [in] pstcAdcInit Pointer to a @ref stc_adc_init_t structure + * whose fields will be set to default values. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAdcInit == NULL. + */ +int32_t ADC_StructInit(stc_adc_init_t *pstcAdcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcAdcInit != NULL) { + pstcAdcInit->u16ScanMode = ADC_MD_SEQA_SINGLESHOT; + pstcAdcInit->u16Resolution = ADC_RESOLUTION_12BIT; + pstcAdcInit->u16DataAlign = ADC_DATAALIGN_RIGHT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Seq The sequence whose channel specified by 'u8Ch' will be enabled or disabled. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: ADC sequence A. + * @arg ADC_SEQ_B: ADC sequence B. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @note Sequence A and Sequence B CAN NOT include the same channel! + * @note Sequence A can always started by software(by calling @ref ADC_Start()), + * regardless of whether the hardware trigger source is valid or not. + * @note Sequence B must be specified a valid hard trigger by calling functions @ref ADC_TriggerConfig() + * and @ref ADC_TriggerCmd(). + */ +void ADC_ChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint8_t u8Ch, en_functional_state_t enNewState) +{ + uint32_t u32CHSELAddr; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + (u8Seq * 4UL); + if (enNewState == ENABLE) { + /* Enable the specified channel. */ + SET_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } else { + /* Disable the specified channel. */ + CLR_REG32_BIT(RW_MEM32(u32CHSELAddr), 1UL << u8Ch); + } +} + +/** + * @brief Enable or disable the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Seq The sequence whose channel specified by 'u32MxCh' will be enabled or disabled. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: ADC sequence A. + * @arg ADC_SEQ_B: ADC sequence B. + * @param [in] u32MxCh The ADC channel. + * This parameter can be any component of @ref ADC_Mx_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @note Sequence A and Sequence B CAN NOT include the same channel! + * @note Sequence A can always started by software(by calling @ref ADC_Start()), + * regardless of whether the hardware trigger source is valid or not. + * @note Sequence B must be specified a valid hard trigger by calling functions @ref ADC_TriggerConfig() + * and @ref ADC_TriggerCmd(). + */ +void ADC_MxChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint32_t u32MxCh, en_functional_state_t enNewState) +{ + uint32_t u32CHSELAddr; + + DDL_ASSERT(IS_ADC_MX_CH(ADCx, u32MxCh)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + (u8Seq * 4UL); + if (enNewState == ENABLE) { + /* Enable the specified channel. */ + SET_REG32_BIT(RW_MEM32(u32CHSELAddr), u32MxCh); + } else { + /* Disable the specified channel. */ + CLR_REG32_BIT(RW_MEM32(u32CHSELAddr), u32MxCh); + } +} + +/** + * @brief Set sampling time for the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The channel to be set sampling time. + * This parameter can be values of @ref ADC_Channel + * @param [in] u8SampleTime Sampling time for the channel that specified by 'u8Ch'. + * @retval None + */ +void ADC_SetSampleTime(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8SampleTime) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_SAMPLE_TIME(u8SampleTime)); + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + u32Addr = (uint32_t)&ADCx->SSTR0 + u8Ch; + WRITE_REG8(RW_MEM8(u32Addr), u8SampleTime); +} + +/** + * @brief Set scan-average count. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16AverageCount Scan-average count. + * This parameter can be a value of @ref ADC_Average_Count + * @arg ADC_AVG_CNT2: 2 consecutive average conversions. + * @arg ADC_AVG_CNT4: 4 consecutive average conversions. + * @arg ADC_AVG_CNT8: 8 consecutive average conversions. + * @arg ADC_AVG_CNT16: 16 consecutive average conversions. + * @arg ADC_AVG_CNT32: 32 consecutive average conversions. + * @arg ADC_AVG_CNT64: 64 consecutive average conversions. + * @arg ADC_AVG_CNT128: 128 consecutive average conversions. + * @arg ADC_AVG_CNT256: 256 consecutive average conversions. + * @retval None + */ +void ADC_ConvDataAverageConfig(CM_ADC_TypeDef *ADCx, uint16_t u16AverageCount) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AVG_CNT(u16AverageCount)); + MODIFY_REG16(ADCx->CR0, ADC_CR0_AVCNT, u16AverageCount); +} + +/** + * @brief Enable or disable conversion data average calculation channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_ConvDataAverageChCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } else { + CLR_REG32_BIT(ADCx->AVCHSELR, 1UL << u8Ch); + } +} + +/** + * @brief Enable or disable conversion data average calculation channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32MxCh The ADC channel. + * This parameter can be any component of @ref ADC_Mx_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_ConvDataAverageMxChCmd(CM_ADC_TypeDef *ADCx, uint32_t u32MxCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_MX_CH(ADCx, u32MxCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(ADCx->AVCHSELR, u32MxCh); + } else { + CLR_REG32_BIT(ADCx->AVCHSELR, u32MxCh); + } +} + +/** + * @brief Specifies the analog input source of extended channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8ExtChSrc The analog input source of extended channel. + * This parameter can be a value of @ref ADC_Ext_Ch_Analog_Src + * @retval None + */ +void ADC_SetExtChSrc(CM_ADC_TypeDef *ADCx, uint8_t u8ExtChSrc) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_EXTCH_SRC(u8ExtChSrc)); + WRITE_REG8(ADCx->EXCHSELR, u8ExtChSrc); +} + +/** + * @brief Specifies the sample mode. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16Mode The sample mode. + * This parameter can be a value of @ref ADC_Sample_Mode + * @retval None + */ +void ADC_SetSampleMode(CM_ADC_TypeDef *ADCx, uint16_t u16Mode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SAMPLE_MD(u16Mode)); + + if (ADC_SAMPLE_MD_NORMAL == u16Mode) { + CLR_REG16_BIT(ADCx->CR2, ADC_SAMPLE_MD_OVER); + } else { + SET_REG16_BIT(ADCx->CR2, ADC_SAMPLE_MD_OVER); + } +} + +/** + * @brief Specifies the over sample shift value. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16ShiftValue The shift value. + * This parameter can be a value of @ref ADC_Over_Sample_Shift + * @retval None + */ +void ADC_SetOverSampleShift(CM_ADC_TypeDef *ADCx, uint16_t u16ShiftValue) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_OVER_SAMPLE_SHIFT(u16ShiftValue)); + + MODIFY_REG16(ADCx->CR2, ADC_CR2_OVSS, u16ShiftValue); +} + +/** + * @brief Specifies the hard trigger for the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] u16TriggerSel Hard trigger selection. This parameter can be a value of @ref ADC_Hard_Trigger_Sel + * @arg ADC_HARDTRIG_ADTRG_PIN: Selects the following edge of pin ADTRG as the trigger of ADC sequence. + * @arg ADC_HARDTRIG_EVT0: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL0(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT1: Selects an internal event as the trigger of ADC sequence. + This event is specified by register ADCx_TRGSEL1(x=(null), 1, 2, 3). + * @arg ADC_HARDTRIG_EVT0_EVT1: Selects two internal events as the trigger of ADC sequence. + The two events are specified by register ADCx_TRGSEL0 and register ADCx_TRGSEL1. + * @retval None + * @note ADC must be stopped while calling this function. + * @note The trigger source CANNOT be an event that generated by the sequence itself. + */ +void ADC_TriggerConfig(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, uint16_t u16TriggerSel) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_ADC_HARDTRIG(u16TriggerSel)); + + u8Seq *= ADC_TRGSR_TRGSELB_POS; + MODIFY_REG16(ADCx->TRGSR, (uint32_t)ADC_TRGSR_TRGSELA << u8Seq, (uint32_t)u16TriggerSel << u8Seq); +} + +/** + * @brief Enable or disable the hard trigger of the specified ADC sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADCx or CM_ADC + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note ADC must be stopped while calling this function. + */ +void ADC_TriggerCmd(CM_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->TRGSR, (uint32_t)ADC_TRGSR_TRGENA << (u8Seq * ADC_TRGSR_TRGSELB_POS)); + } else { + CLR_REG16_BIT(ADCx->TRGSR, (uint32_t)ADC_TRGSR_TRGENA << (u8Seq * ADC_TRGSR_TRGSELB_POS)); + } +} + +/** + * @brief Enable or disable ADC interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8IntType ADC interrupt. + * This parameter can be values of @ref ADC_Int_Type + * @arg ADC_INT_EOCA: Interrupt of the end of conversion of sequence A. + * @arg ADC_INT_EOCB: Interrupt of the end of conversion of sequence B. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_IntCmd(CM_ADC_TypeDef *ADCx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_INT(u8IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG8_BIT(ADCx->ICR, u8IntType); + } else { + CLR_REG8_BIT(ADCx->ICR, u8IntType); + } +} + +/** + * @brief Start sequence A conversion. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval int32_t + * - LL_OK: Start success. + * - LL_ERR_BUSY: ADC is busy. + */ +int32_t ADC_Start(CM_ADC_TypeDef *ADCx) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + if (1U == READ_REG8(ADCx->STR)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(ADCx->STR, ADC_STR_STRT); + } + + return i32Ret; +} + +/** + * @brief Stop ADC conversion, both sequence A and sequence B. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_Stop(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, 0U); +} + +/** + * @brief Get the ADC value of the specified channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch The ADC channel. + * This parameter can be values of @ref ADC_Channel + * @retval An uint16_t type value of ADC value. + */ +uint16_t ADC_GetValue(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + + return RW_MEM16((uint32_t)&ADCx->DR0 + u8Ch * 2UL); +} + +/** + * @brief Get the ADC resolution. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval An uint16_t type value of ADC resolution. @ref ADC_Resolution + */ +uint16_t ADC_GetResolution(const CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + return READ_REG16_BIT(ADCx->CR0, ADC_CR0_ACCSEL); +} + +/** + * @brief Get the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be a value of @ref ADC_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_GetStatus(const CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + if (READ_REG8_BIT(ADCx->ISR, u8Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified ADC flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Flag ADC status flag. + * This parameter can be valueS of @ref ADC_Status_Flag + * @retval None + */ +void ADC_ClearStatus(CM_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_FLAG(u8Flag)); + + WRITE_REG8(ADCx->ISCLRR, u8Flag); +} + +/** + * @brief Remap the correspondence between ADC channel and analog input pins. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch This parameter can be values of @ref ADC_Channel + * @param [in] u8AdcPin This parameter can be a value of @ref ADC_Remap_Pin + * @retval None + */ +void ADC_ChRemap(CM_ADC_TypeDef *ADCx, uint8_t u8Ch, uint8_t u8AdcPin) +{ + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_REMAP_PIN(ADCx, u8AdcPin)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + MODIFY_REG16(regCHMUXR[u8RegIdx], ((uint32_t)ADC_CHMUXR0_CH00MUX << u8FieldOfs), ((uint32_t)u8AdcPin << u8FieldOfs)); +} + +/** + * @brief Get the ADC pin corresponding to the specified ADC channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8Ch ADC channel. + * This parameter can be one of the following values of @ref ADC_Channel + * @retval An uint8_t type value of ADC pin. @ref ADC_Remap_Pin + */ +uint8_t ADC_GetChPin(const CM_ADC_TypeDef *ADCx, uint8_t u8Ch) +{ + uint8_t u8RetPin; + uint8_t u8FieldOfs; + uint8_t u8RegIdx; + __IO uint16_t *regCHMUXR; + + DDL_ASSERT(IS_ADC_REMAP_CH(ADCx, u8Ch)); + + regCHMUXR = (__IO uint16_t *)((uint32_t)&ADCx->CHMUXR0); + u8RegIdx = u8Ch / 4U; + u8FieldOfs = (u8Ch % 4U) * 4U; + u8RetPin = ((uint8_t)(regCHMUXR[u8RegIdx] >> u8FieldOfs)) & 0xFU; + + return u8RetPin; +} + +/** + * @brief Reset channel-pin mapping. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @retval None + */ +void ADC_ResetChMapping(CM_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + /* CHMUXRx */ + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + if (ADCx == CM_ADC3) { + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + } else if (ADCx == CM_ADC1) { + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); + } else { + /* rsvd */ + } +} + +/** + * @brief Configures synchronous mode. + * @param [in] u16SyncUnit Specify the ADC units which work synchronously. + * This parameter can be a value of @ref ADC_Sync_Unit + * @param [in] u16SyncMode Synchronous mode. + * This parameter can be a value of @ref ADC_Sync_Mode + * @arg ADC_SYNC_SINGLE_DELAY_TRIG: Single shot delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan once. + * @arg ADC_SYNC_SINGLE_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan once. + * @arg ADC_SYNC_CYCLIC_DELAY_TRIG: Cyclic delayed trigger mode. + * When the trigger condition occurs, ADC1 starts first, then ADC2, last ADC3(if has). + * All ADCs scan cyclicly(keep scanning till you stop them). + * @arg ADC_SYNC_CYCLIC_PARALLEL_TRIG: Single shot parallel trigger mode. + * When the trigger condition occurs, all ADCs start at the same time. + * All ADCs scan cyclicly(keep scanning till you stop them). + * @param [in] u8TriggerDelay Trigger delay time(ADCLK cycle), range is [1, 255]. + * @retval None + */ +void ADC_SyncModeConfig(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TriggerDelay) +{ + DDL_ASSERT(IS_ADC_SYNC(u16SyncUnit)); + DDL_ASSERT(IS_ADC_SYNC_MD(u16SyncMode)); + + u16SyncMode |= ((uint16_t)((uint32_t)u8TriggerDelay << ADC_SYNCCR_SYNCDLY_POS)) | u16SyncUnit; + MODIFY_REG16(CM_ADC1->SYNCCR, ADC_SYNCCR_SYNCMD | ADC_SYNCCR_SYNCDLY, u16SyncMode); +} + +/** + * @brief Enable or disable synchronous mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_SyncModeCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_ADC1->SYNCCR_b.SYNCEN, enNewState); +} + +/** + * @brief Configures analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @param [in] pstcAwd Pointer to a @ref stc_adc_awd_config_t structure value that + * contains the configuration information of the AWD. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcAwd == NULL. + */ +int32_t ADC_AWD_Config(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch, const stc_adc_awd_config_t *pstcAwd) +{ + uint32_t u32AwdDr0; + uint32_t u32AwdDr1; + uint32_t u32AwdChsr; + uint32_t u32Addr; + uint8_t u8Pos; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + if (pstcAwd != NULL) { + DDL_ASSERT(IS_ADC_AWD_MD(pstcAwd->u16WatchdogMode)); + + u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + u32AwdDr0 = (uint32_t)&ADCx->AWD0DR0; + u32AwdDr1 = (uint32_t)&ADCx->AWD0DR1; + u32AwdChsr = (uint32_t)&ADCx->AWD0CHSR; + + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, u8Pos), pstcAwd->u16WatchdogMode); + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr0), pstcAwd->u16LowThreshold); + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr1), pstcAwd->u16HighThreshold); + WRITE_REG8(ADC_AWDx_CHSR(u8AwdUnit, u32AwdChsr), u8Ch); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies combination mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16CombMode Combination mode of analog watchdog. + * This parameter can be a value of @ref ADC_AWD_Comb_Mode + * @arg ADC_AWD_COMB_INVD Combination mode is invalid. + * @arg ADC_AWD_COMB_OR: The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. + * @arg ADC_AWD_COMB_AND: The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. + * @arg ADC_AWD_COMB_XOR: Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. + * @retval None + */ +void ADC_AWD_SetCombMode(CM_ADC_TypeDef *ADCx, uint16_t u16CombMode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_COMB_MD(u16CombMode)); + MODIFY_REG16(ADCx->AWDCR, ADC_AWDCR_AWDCM, u16CombMode); +} + +/** + * @brief Specifies the compare mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16WatchdogMode Analog watchdog compare mode. + * This parameter can be a value of @ref ADC_AWD_Mode + * @arg ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * @arg ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + * @retval None + */ +void ADC_AWD_SetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16WatchdogMode) +{ + uint8_t u8Pos; + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_ADC_AWD_MD(u16WatchdogMode)); + + u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, u8Pos), u16WatchdogMode); +} + +/** + * @brief Get the compare mode of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @retval Analog watchdog compare mode. A value of @ref ADC_AWD_Mode + * - ADC_AWD_MD_CMP_OUT: ADCValue > HighThreshold or ADCValue < LowThreshold + * - ADC_AWD_MD_CMP_IN: LowThreshold < ADCValue < HighThreshold + */ +uint16_t ADC_AWD_GetMode(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit) +{ + uint16_t u16RetMode; + + uint8_t u8Pos; + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + u8Pos = (u8AwdUnit * 4U) + ADC_AWDCR_AWD0MD_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + u16RetMode = (uint16_t)PERIPH_BIT_BAND(u32Addr, u8Pos); + + return u16RetMode; +} + +/** + * @brief Specifies the low threshold and high threshold of analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u16LowThreshold Low threshold of analog watchdog. + * @param [in] u16HighThreshold High threshold of analog watchdog. + * @retval None + */ +void ADC_AWD_SetThreshold(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint16_t u16LowThreshold, uint16_t u16HighThreshold) +{ + uint32_t u32AwdDr0; + uint32_t u32AwdDr1; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + u32AwdDr0 = (uint32_t)&ADCx->AWD0DR0; + u32AwdDr1 = (uint32_t)&ADCx->AWD0DR1; + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr0), u16LowThreshold); + WRITE_REG16(ADC_AWDx_DR(u8AwdUnit, u32AwdDr1), u16HighThreshold); +} + +/** + * @brief Select the specified ADC channel as an analog watchdog channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] u8Ch The channel that to be used as an analog watchdog channel. + * This parameter can be a value of @ref ADC_Channel + * @retval None + */ +void ADC_AWD_SelectCh(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, uint8_t u8Ch) +{ + uint32_t u32AwdChsr; + DDL_ASSERT(IS_ADC_CH(ADCx, u8Ch)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + + u32AwdChsr = (uint32_t)&ADCx->AWD0CHSR; + WRITE_REG8(ADC_AWDx_CHSR(u8AwdUnit, u32AwdChsr), u8Ch); +} + +/** + * @brief Enable or disable the specified analog watchdog. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u8AwdUnit AWD unit that is going to be enabled or disabled. + * This parameter can be a value of @ref ADC_AWD_Unit + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_Cmd(CM_ADC_TypeDef *ADCx, uint8_t u8AwdUnit, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD(u8AwdUnit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->AWDCR; + /* Enable bit position: u8AwdUnit * 4 */ + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, (u8AwdUnit * 4UL)), enNewState); +} + +/** + * @brief Enable or disable the specified analog watchdog interrupts. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16IntType Interrupt of AWD. + * This parameter can be a value of @ref ADC_AWD_Int_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_AWD_IntCmd(CM_ADC_TypeDef *ADCx, uint16_t u16IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_INT(u16IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->AWDCR, u16IntType); + } else { + CLR_REG16_BIT(ADCx->AWDCR, u16IntType); + } +} + +/** + * @brief Get the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t ADC_AWD_GetStatus(const CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_FLAG(u32Flag)); + if (READ_REG8_BIT(ADCx->AWDSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified analog watchdog flag. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u32Flag AWD status flag. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @retval None + */ +void ADC_AWD_ClearStatus(CM_ADC_TypeDef *ADCx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AWD_FLAG(u32Flag)); + WRITE_REG8(ADCx->AWDSCLRR, u32Flag); +} + +/** + * @brief Enable or disable automatically clear data register. + * The automatic clearing function is mainly used to detect whether the data register is updated. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void ADC_DataRegAutoClearCmd(CM_ADC_TypeDef *ADCx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } else { + CLR_REG16_BIT(ADCx->CR0, ADC_CR0_CLREN); + } +} + +/** + * @brief Sequence A restart channel selection. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg CM_ADC or CM_ADCx: ADC instance register base. + * @param [in] u16SeqAResumeMode Sequence A resume mode. + * This parameter can be a value of @ref ADC_SeqA_Resume_Mode + * @arg ADC_SEQA_RESUME_SCAN_CONT: Scanning will continue from the interrupted channel. + * @arg ADC_SEQA_RESUME_SCAN_RESTART: Scanning will start from the first channel. + * @retval None + */ +void ADC_SetSeqAResumeMode(CM_ADC_TypeDef *ADCx, uint16_t u16SeqAResumeMode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQA_RESUME_MD(u16SeqAResumeMode)); + WRITE_REG16(ADCx->CR1, u16SeqAResumeMode); +} + +/** + * @} + */ + +#endif /* LL_ADC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c new file mode 100644 index 0000000000..231f4a9631 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_aes.c @@ -0,0 +1,315 @@ +/** + ******************************************************************************* + * @file hc32_ll_aes.c + * @brief This file provides firmware functions to manage the Advanced Encryption + * Standard(AES). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aes.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AES AES + * @brief AES Driver Library + * @{ + */ + +#if (LL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Local_Macros AES Local Macros + * @{ + */ +/* Delay count for timeout */ +#define AES_TIMEOUT (30000UL) +#define AES_RMU_TIMEOUT (100UL) + +/* AES block size */ +#define AES_BLOCK_SIZE (16U) + +/** + * @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity + * @{ + */ +#define IS_AES_KEY_SIZE(x) \ +( ((x) == AES_KEY_SIZE_16BYTE) || \ + ((x) == AES_KEY_SIZE_24BYTE) || \ + ((x) == AES_KEY_SIZE_32BYTE)) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AES_Local_Functions AES Local Functions + * @{ + */ +/** + * @brief Write the input buffer in data register. + * @param [in] pu8SrcData Point to the source data buffer. + * @retval None + */ +static void AES_WriteData(const uint8_t *pu8SrcData) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8SrcData); + + for (i = 0U; i < 4U; i++) { + regDR[i] = pu32Data[i]; + } +} + +/** + * @brief Read the from data register. + * @param [out] pu8Result Point to the result buffer. + * @retval None + */ +static void AES_ReadData(uint8_t *pu8Result) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_AES->DR0; + uint32_t *pu32Result = (uint32_t *)((uint32_t)pu8Result); + + for (i = 0U; i < 4U; i++) { + pu32Result[i] = regDR[i]; + } +} + +/** + * @brief Write the input buffer in key register. + * @param [in] pu8Key Pointer to the key buffer. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @retval None + */ +static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeySize) +{ + uint8_t i; + uint8_t u8KeyWordSize = u8KeySize / 4U; + __IO uint32_t *regKR = &CM_AES->KR0; + const uint32_t *pu32Key = (const uint32_t *)((uint32_t)pu8Key); + + for (i = 0U; i < u8KeyWordSize; i++) { + regKR[i] = pu32Key[i]; + } + switch (u8KeySize) { + case 16U: + u8KeySize = 0U; + break; + case 24U: + u8KeySize = 1U; + break; + case 32U: + u8KeySize = 2U; + break; + default: + break; + } + MODIFY_REG32(CM_AES->CR, AES_CR_KEYSIZE, ((uint32_t)u8KeySize << AES_CR_KEYSIZE_POS)); +} + +/** + * @brief Wait AES operation done. + * @param None + * @retval None + */ +static int32_t AES_WaitDone(void) +{ + __IO uint32_t u32TimeCount = 0UL; + int32_t i32Ret = LL_OK; + + while (bCM_AES->CR_b.START != 0UL) { + if (u32TimeCount++ >= AES_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} +/** + * @} + */ + +/** + * @defgroup AES_Global_Functions AES Global Functions + * @{ + */ + +/** + * @brief AES encryption. + * @param [in] pu8Plaintext Buffer of the plaintext(the source data which will be encrypted). + * @param [in] u32PlaintextSize Length of plaintext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Ciphertext Buffer of the ciphertext. + * @retval int32_t: + * - LL_OK: Encrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Encrypt timeout. + */ +int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Ciphertext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32PlaintextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32PlaintextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES encrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 0UL); + while (u32Index < u32PlaintextSize) { + AES_WriteData(&pu8Plaintext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Ciphertext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} + +/** + * @brief AES decryption. + * @param [in] pu8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted). + * @param [in] u32CiphertextSize Length of ciphertext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeySize AES key size. This parameter can be a value of @ref AES_Key_Size + * @param [out] pu8Plaintext Buffer of the plaintext. + * @retval int32_t: + * - LL_OK: Decrypt successfully. + * - LL_ERR_INVD_PARAM: Invalid parameter. + * - LL_TIMEOUT: Decrypt timeout. + */ +int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, + const uint8_t *pu8Key, uint8_t u8KeySize, + uint8_t *pu8Plaintext) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Index = 0UL; + + DDL_ASSERT(IS_AES_KEY_SIZE(u8KeySize)); + DDL_ASSERT((u32CiphertextSize % AES_BLOCK_SIZE) == 0U); + + if ((pu8Plaintext != NULL) && (u32CiphertextSize > 0UL) && \ + (pu8Key != NULL) && (pu8Ciphertext != NULL)) { + AES_WriteKey(pu8Key, u8KeySize); + /* Set AES decrypt. */ + WRITE_REG32(bCM_AES->CR_b.MODE, 1UL); + while (u32Index < u32CiphertextSize) { + AES_WriteData(&pu8Ciphertext[u32Index]); + /* Start AES calculating. */ + WRITE_REG32(bCM_AES->CR_b.START, 1UL); + /* Wait for AES to stop */ + i32Ret = AES_WaitDone(); + if (i32Ret != LL_OK) { + break; + } + AES_ReadData(&pu8Plaintext[u32Index]); + u32Index += AES_BLOCK_SIZE; + } + } + + return i32Ret; +} + +/** + * @brief De-Initialize AES function. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success. + * - LL_ERR_TIMEOUT: Timeout. + */ +int32_t AES_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeOut = 0U; + /* Check FRST register protect */ + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + /* Reset */ + WRITE_REG32(bCM_RMU->FRST0_b.AES, 0UL); + /* Ensure reset procedure is completed */ + while (0UL == READ_REG32(bCM_RMU->FRST0_b.AES)) { + u32TimeOut++; + if (u32TimeOut > AES_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_AES_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c new file mode 100644 index 0000000000..e3feb125ed --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_aos.c @@ -0,0 +1,316 @@ +/** + ******************************************************************************* + * @file hc32_ll_aos.c + * @brief This file provides firmware functions to manage the AOS. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_aos.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_AOS AOS + * @brief AOS Driver Library + * @{ + */ + +#if (LL_AOS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AOS_Local_Macros AOS Local Macros + * @{ + */ + +/** + * @defgroup AOS_Common_Trigger_ID_Validity AOS Common Trigger ID Validity + * @{ + */ +#define IS_AOS_COMM_TRIG(x) \ +( ((x) != 0UL) && \ + ((x) | AOS_COMM_TRIG_MASK) == AOS_COMM_TRIG_MASK) + +/** + * @} + */ + +/** + * @defgroup AOS_Target_Select_Validity AOS Target Select Validity + * @{ + */ +#define IS_AOS_TARGET(x) \ +( ((x) == AOS_DCU1) || \ + ((x) == AOS_DCU2) || \ + ((x) == AOS_DCU3) || \ + ((x) == AOS_DCU4) || \ + ((x) == AOS_DMA1_0) || \ + ((x) == AOS_DMA1_1) || \ + ((x) == AOS_DMA1_2) || \ + ((x) == AOS_DMA1_3) || \ + ((x) == AOS_DMA1_4) || \ + ((x) == AOS_DMA1_5) || \ + ((x) == AOS_DMA2_0) || \ + ((x) == AOS_DMA2_1) || \ + ((x) == AOS_DMA2_2) || \ + ((x) == AOS_DMA2_3) || \ + ((x) == AOS_DMA2_4) || \ + ((x) == AOS_DMA2_5) || \ + ((x) == AOS_DMA_RC) || \ + ((x) == AOS_TMR6_0) || \ + ((x) == AOS_TMR6_1) || \ + ((x) == AOS_TMR4_0) || \ + ((x) == AOS_TMR4_1) || \ + ((x) == AOS_TMR4_2) || \ + ((x) == AOS_EVTPORT12) || \ + ((x) == AOS_EVTPORT34) || \ + ((x) == AOS_TMR0) || \ + ((x) == AOS_TMRA_0) || \ + ((x) == AOS_TMRA_1) || \ + ((x) == AOS_TMRA_2) || \ + ((x) == AOS_TMRA_3) || \ + ((x) == AOS_ADC1_0) || \ + ((x) == AOS_ADC1_1) || \ + ((x) == AOS_ADC2_0) || \ + ((x) == AOS_ADC2_1) || \ + ((x) == AOS_ADC3_0) || \ + ((x) == AOS_ADC3_1) || \ + ((x) == AOS_COMM_1) || \ + ((x) == AOS_COMM_2)) + +/** + * @} + */ + +/** + * @defgroup AOS_PLU_Check_Parameters_Validity AOS PLU check parameters validity + * @{ + */ +#define IS_AOS_PLU_ID(x) ((x) <= AOS_PLU_ID3) +#define IS_AOS_PLU_SEL(x) ((x) == AOS_PLU_SEL_NONE || (x) <= AOS_PLU_SEL_UNIT3) +#define IS_AOS_PLU_PLIN_ID(x) ((x) <= AOS_PLU_PLIN_ID_D) +#define IS_AOS_PLU_PLIN_SRC(x) ((x) <= AOS_PLU_PLIN_SRC_PORT_IN) +#define IS_AOS_PLU_MODE(x) ((x) <= AOS_PLU_MODE_AND_AND) +/** + * @} + */ + +/** + * @defgroup AOS_PLU_Control_Register AOS PLU Control Register + * @{ + */ +#define AOS_PLUx_CTRL_REG(x) ((__IO uint32_t *)(&(CM_AOS->PLU0_CR) + (x))) +/** + * @} + */ + +#define IS_AOS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/* AOS reset timeout */ +#define AOS_RMU_TIMEOUT (100UL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AOS_Global_Functions AOS Global Functions + * @{ + */ + +/** + * @brief De-Initialize AOS. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t AOS_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeOut = 0U; + + /* Check parameters */ + DDL_ASSERT(IS_AOS_PWC_UNLOCKED()); + + CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_AOS); + /* Ensure reset procedure is completed */ + while (RMU_FRST0_AOS != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_AOS)) { + u32TimeOut++; + if (u32TimeOut > AOS_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Common trigger function command + * @param [in] u32Target AOS target that need to be triggered by common trigger @ref AOS_Target_Select in details + * @param [in] u32CommonTrigger Common trigger ID + * This parameter can be one of the following values: + * @arg AOS_COMM_TRIG1: Common trigger 1. + * @arg AOS_COMM_TRIG2: Common trigger 2. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void AOS_CommonTriggerCmd(uint32_t u32Target, uint32_t u32CommonTrigger, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_AOS_TARGET(u32Target)); + DDL_ASSERT(IS_AOS_COMM_TRIG(u32CommonTrigger)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*(__IO uint32_t *)u32Target, u32CommonTrigger); + } else { + CLR_REG32_BIT(*(__IO uint32_t *)u32Target, u32CommonTrigger); + } +} + +/** + * @brief Set trigger event source + * @param [in] u32Target AOS target that need to be triggered by AOS source @ref AOS_Target_Select in details + * @param [in] enSource AOS source that trigger the AOS target @ref en_event_src_t in details + * @retval None + */ +void AOS_SetTriggerEventSrc(uint32_t u32Target, en_event_src_t enSource) +{ + DDL_ASSERT(IS_AOS_TARGET(u32Target)); + + MODIFY_REG32(*(__IO uint32_t *)u32Target, AOS_TRIG_SEL_MASK, enSource); +} + +/** + * @brief Set trigger event source for PL input + * @param [in] u32PluId PL unit ID.Can be one of @ref AOS_PLU_ID + * @param [in] u32PlinId PL input ID.Can be one of @ref AOS_PLU_PLInput_ID + * @param [in] enSource AOS source @ref en_event_src_t + * @retval None + */ +void AOS_PLU_SetPlinTriggerEventSrc(uint32_t u32PluId, uint32_t u32PlinId, en_event_src_t enSource) +{ + DDL_ASSERT(IS_AOS_PLU_ID(u32PluId)); + DDL_ASSERT(IS_AOS_PLU_PLIN_ID(u32PlinId)); + __IO uint32_t *TRGSELReg; + + TRGSELReg = (__IO uint32_t *)(&(CM_AOS->PLU0_TRGSELA) + (u32PluId * 4U + u32PlinId)); + MODIFY_REG32(*TRGSELReg, AOS_TRIG_SEL_MASK, enSource); +} + +/** + * @brief Set input source for PL input + * @param [in] u32PluId PL unit ID.Can be one of @ref AOS_PLU_ID + * @param [in] u32PlinId PL input ID.Can be one of @ref AOS_PLU_PLInput_ID + * @param [in] u32Source Source of PL input Can be one of @ref AOS_PLU_PLInput_Src + * @retval None + */ +void AOS_PLU_SetPlinSrc(uint32_t u32PluId, uint32_t u32PlinId, uint32_t u32Source) +{ + DDL_ASSERT(IS_AOS_PLU_ID(u32PluId)); + DDL_ASSERT(IS_AOS_PLU_PLIN_ID(u32PlinId)); + DDL_ASSERT(IS_AOS_PLU_PLIN_SRC(u32Source)); + __IO uint32_t *CR; + uint32_t u32SrcMask, u32SrcValue; + + CR = AOS_PLUx_CTRL_REG(u32PluId); + u32SrcMask = AOS_PLU_CR_PLINASEL << (u32PlinId * 2U); + u32SrcValue = u32Source << (AOS_PLU_CR_PLINASEL_POS + (u32PlinId * 2U)); + MODIFY_REG32(*CR, u32SrcMask, u32SrcValue); +} + +/** + * @brief Set PLU logic operation mode + * @param [in] u32PluId PL unit ID.Can be one of @ref AOS_PLU_ID + * @param [in] u32Mode PLU logic operation mode.Can be one of @ref AOS_PLU_Mode + * @retval None + */ +void AOS_PLU_SetLogicOperationMode(uint32_t u32PluId, uint32_t u32Mode) +{ + DDL_ASSERT(IS_AOS_PLU_ID(u32PluId)); + DDL_ASSERT(IS_AOS_PLU_MODE(u32Mode)); + __IO uint32_t *CR; + + CR = AOS_PLUx_CTRL_REG(u32PluId); + MODIFY_REG32(*CR, AOS_PLU_CR_PLMODE, u32Mode); +} + +/** + * @brief Select PL unit or do not select pl unit to trigger the specified AOS target + * @param [in] u32Target AOS target. Can be one of @ref AOS_Target_Select + * @param [in] u32PluSel PL unit selection.Can be one of @ref AOS_PLU_SEL + * @retval None + */ +void AOS_SelectPLU(uint32_t u32Target, uint32_t u32PluSel) +{ + DDL_ASSERT(IS_AOS_TARGET(u32Target)); + DDL_ASSERT(IS_AOS_PLU_SEL(u32PluSel)); + uint32_t u32SELValue; + + if (u32PluSel == AOS_PLU_SEL_NONE) { + u32SELValue = 0U; + } else { + u32SELValue = (u32PluSel + 1U) << AOS_DCU_TRGSEL_PLCHSEL_POS; + } + MODIFY_REG32(*(__IO uint32_t *)u32Target, AOS_DCU_TRGSEL_PLCHSEL, u32SELValue); +} + +/** + * @} + */ + +#endif /* LL_AOS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c new file mode 100644 index 0000000000..6631d6b15e --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_clk.c @@ -0,0 +1,1507 @@ +/** + ******************************************************************************* + * @file hc32_ll_clk.c + * @brief This file provides firmware functions to manage the Clock(CLK). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Modify API CLK_Xtal32Cmd(), CLK_MrcCmd() and CLK_LrcCmd(), use DDL_DelayUS() to replace CLK_Delay() + 2023-12-15 CDT Refine API CLK_XtalStdInit. and add API CLK_XtalStdCmd, CLK_SetXtalStdExceptionType + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_clk.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CLK CLK + * @brief Clock Driver Library + * @{ + */ + +#if (LL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Macros CLK Local Macros + * @{ + */ + +/** + * @brief CLK_FREQ Clock frequency definition + */ +#define CLK_FREQ_48M (48UL*1000UL*1000UL) +#define CLK_FREQ_64M (64UL*1000UL*1000UL) +#define CLK_FREQ_32M (32UL*1000UL*1000UL) + +/** + * @brief Be able to modify TIMEOUT according to board condition. + */ +#define CLK_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_LRC_TIMEOUT (160U) +#define CLK_MRC_TIMEOUT (1U) +#define CLK_XTAL32_TIMEOUT (160U) + +/** + * @brief XTALSTD exception type mask + */ +#define CLK_XTALSTD_EXP_TYPE_MASK (CMU_XTALSTDCR_XTALSTDIE | CMU_XTALSTDCR_XTALSTDRE | CMU_XTALSTDCR_XTALSTDRIS) + +/** + * @brief LRC State ON or OFF + */ +#define CLK_LRC_OFF (CMU_LRCCR_LRCSTP) +#define CLK_LRC_ON (0x00U) + +/** + * @brief MRC State ON or OFF + */ +#define CLK_MRC_OFF (CMU_MRCCR_MRCSTP) +#define CLK_MRC_ON (0x80U) + +/** + * @brief Clk PLL Relevant Parameter Range Definition + */ +#define CLK_PLLP_DEFAULT (0x01UL) +#define CLK_PLLQ_DEFAULT (0x01UL) +#define CLK_PLLR_DEFAULT (0x01UL) +#define CLK_PLLN_DEFAULT (0x13UL) +#define CLK_PLLM_DEFAULT (0x00UL) + +#define CLK_PLLR_DIV_MIN (2UL) +#define CLK_PLLR_DIV_MAX (16UL) +#define CLK_PLLQ_DIV_MIN (2UL) +#define CLK_PLLQ_DIV_MAX (16UL) +#define CLK_PLLP_DIV_MIN (2UL) +#define CLK_PLLP_DIV_MAX (16UL) + +#define CLK_PLL_FREQ_MIN (375UL*100UL*1000UL) +#define CLK_PLL_VCO_IN_MIN (8UL*1000UL*1000UL) +#define CLK_PLL_VCO_IN_MAX (25UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MIN (600UL*1000UL*1000UL) +#define CLK_PLL_VCO_OUT_MAX (1200UL*1000UL*1000UL) +#define CLK_PLLM_DIV_MIN (1UL) +#define CLK_PLLM_DIV_MAX (4UL) +#define CLK_PLLN_MULTI_MIN (25UL) +#define CLK_PLLN_MULTI_MAX (150UL) +#define CLK_PLL_FREQ_MAX (200UL*1000UL*1000UL) + +/** + * @brief Clk PLL Register Redefinition + */ +#define PLL_SRC_REG (CM_CMU->PLLHCFGR) +#define PLL_SRC_BIT (CMU_PLLHCFGR_PLLSRC) +#define PLL_SRC_POS (CMU_PLLHCFGR_PLLSRC_POS) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define PLL_EN_REG (CM_CMU->PLLHCR) + +/** + * @brief Switch clock stable time + * @note Approx. 30us + */ +#define CLK_SYSCLK_SW_STB (30U) + +/** + * @brief Clk FCG Default Value + */ +#define CLK_FCG0_DEFAULT (0xFFFFFA0EUL) +#define CLK_FCG1_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG2_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG3_DEFAULT (0xFFFFFFFFUL) + +/** + * @defgroup CLK_Check_Parameters_Validity CLK Check Parameters Validity + * @{ + */ +/* Check CLK register lock status. */ +#define IS_CLK_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0) +#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/* Parameter valid check for XTAL state */ +#define IS_CLK_XTAL_STATE(x) \ +( ((x) == CLK_XTAL_OFF) || \ + ((x) == CLK_XTAL_ON)) + +/* Parameter valid check for XTAL mode */ +#define IS_CLK_XTAL_MD(x) \ +( ((x) == CLK_XTAL_MD_OSC) || \ + ((x) == CLK_XTAL_MD_EXCLK)) + +/* Parameter valid check for XTAL driver ability mode */ +#define IS_CLK_XTAL_DRV_MD(x) \ +( ((x) == CLK_XTAL_DRV_HIGH) || \ + ((x) == CLK_XTAL_DRV_MID) || \ + ((x) == CLK_XTAL_DRV_LOW) || \ + ((x) == CLK_XTAL_DRV_ULOW)) + +/* Parameter valid check for XTAL stable time selection */ +#define IS_CLK_XTAL_STB_SEL(x) \ +( ((x) == CLK_XTAL_STB_133US) || \ + ((x) == CLK_XTAL_STB_255US) || \ + ((x) == CLK_XTAL_STB_499US) || \ + ((x) == CLK_XTAL_STB_988US) || \ + ((x) == CLK_XTAL_STB_2MS) || \ + ((x) == CLK_XTAL_STB_4MS) || \ + ((x) == CLK_XTAL_STB_8MS) || \ + ((x) == CLK_XTAL_STB_16MS) || \ + ((x) == CLK_XTAL_STB_31MS)) + +/* Parameter valid check for XTALDIV state */ +#define IS_CLK_XTALDIV_STATE(x) \ +( ((x) == CLK_XTALDIV_OFF) || \ + ((x) == CLK_XTALDIV_ON)) + +/* Parameter valid check for XTALSTD state */ +#define IS_CLK_XTALSTD_STATE(x) \ +( ((x) == CLK_XTALSTD_OFF) || \ + ((x) == CLK_XTALSTD_ON)) + +/* Parameter valid check for XTALSTD exception type */ +#define IS_CLK_XTALSTD_EXP_TYPE(x) \ +( ((x) == CLK_XTALSTD_EXP_TYPE_NONE) || \ + ((x) == CLK_XTALSTD_EXP_TYPE_RST) || \ + ((x) == CLK_XTALSTD_EXP_TYPE_INT)) + +/* Parameter valid check for PLL state */ +#define IS_CLK_PLL_STATE(x) \ +( ((x) == CLK_PLL_OFF) || \ + ((x) == CLK_PLL_ON)) + +/* Parameter validity check for PLL input source */ +#define IS_CLK_PLL_SRC(x) \ +( ((x) == CLK_PLL_SRC_XTAL) || \ + ((x) == CLK_PLL_SRC_HRC)) + +/* Parameter validity check for PLL frequency range */ +#define IS_CLK_PLL_FREQ(x) \ +( ((x) <= CLK_PLL_FREQ_MAX) && \ + ((x) >= CLK_PLL_FREQ_MIN)) + +/* Parameter validity check for PLL M divide */ +#define IS_CLK_PLLM_DIV(x) \ +( ((x) <= CLK_PLLM_DIV_MAX) && \ + ((x) >= CLK_PLLM_DIV_MIN)) + +/* Parameter validity check for PLL N multi- */ +#define IS_CLK_PLLN_MULTI(x) \ +( ((x) <= CLK_PLLN_MULTI_MAX) && \ + ((x) >= CLK_PLLN_MULTI_MIN)) + +/* Parameter validity check for PLL P divide */ +#define IS_CLK_PLLP_DIV(x) \ +( ((x) <= CLK_PLLP_DIV_MAX) && \ + ((x) >= CLK_PLLP_DIV_MIN)) + +/* Parameter validity check for PLL_input freq./PLLM(vco_in) */ +#define IS_CLK_PLL_VCO_IN(x) \ +( ((x) <= CLK_PLL_VCO_IN_MAX) && \ + ((x) >= CLK_PLL_VCO_IN_MIN)) + +/* Parameter validity check for PLL vco_in*PLLN(vco_out) */ +#define IS_CLK_PLL_VCO_OUT(x) \ +( ((x) <= CLK_PLL_VCO_OUT_MAX) && \ + ((x) >= CLK_PLL_VCO_OUT_MIN)) + +/* Parameter validity check for PLL R divide */ +#define IS_CLK_PLLR_DIV(x) \ +( ((x) <= CLK_PLLR_DIV_MAX) && \ + ((x) >= CLK_PLLR_DIV_MIN)) + +/* Parameter validity check for PLL Q divide */ +#define IS_CLK_PLLQ_DIV(x) \ +( ((x) <= CLK_PLLQ_DIV_MAX) && \ + ((x) >= CLK_PLLQ_DIV_MIN)) + +/* Parameter valid check for XTAL32 state */ +#define IS_CLK_XTAL32_STATE(x) \ +( ((x) == CLK_XTAL32_OFF) || \ + ((x) == CLK_XTAL32_ON)) + +/* Parameter valid check for XTAL32 driver ability mode */ +#define IS_CLK_XTAL32_DRV_MD(x) \ +( ((x) == CLK_XTAL32_DRV_MID) || \ + ((x) == CLK_XTAL32_DRV_HIGH)) + +/* Parameter valid check for XTAL32 filtering selection */ +#define IS_CLK_XTAL32_FILT_SEL(x) \ +( ((x) == CLK_XTAL32_FILTER_ALL_MD) || \ + ((x) == CLK_XTAL32_FILTER_RUN_MD) || \ + ((x) == CLK_XTAL32_FILTER_OFF)) + +/* Parameter valid check for system clock source */ +#define IS_CLK_SYSCLK_SRC(x) \ +( ((x) == CLK_SYSCLK_SRC_HRC) || \ + ((x) == CLK_SYSCLK_SRC_MRC) || \ + ((x) == CLK_SYSCLK_SRC_LRC) || \ + ((x) == CLK_SYSCLK_SRC_XTAL) || \ + ((x) == CLK_SYSCLK_SRC_XTAL32) || \ + ((x) == CLK_SYSCLK_SRC_PLL)) + +/* Parameter valid check for CLK stable flag. */ +#define IS_CLK_STB_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | CLK_STB_FLAG_MASK) == CLK_STB_FLAG_MASK)) + +/* Parameter valid check for bus clock category */ +#define IS_CLK_BUS_CLK_CATE(x) (((x) & CLK_BUS_CLK_ALL) != (0x00U)) + +/* Parameter valid check for HCLK divider */ +#define IS_CLK_HCLK_DIV(x) \ +( ((x) == CLK_HCLK_DIV1) || \ + ((x) == CLK_HCLK_DIV2) || \ + ((x) == CLK_HCLK_DIV4) || \ + ((x) == CLK_HCLK_DIV8) || \ + ((x) == CLK_HCLK_DIV16) || \ + ((x) == CLK_HCLK_DIV32) || \ + ((x) == CLK_HCLK_DIV64)) + +/* Parameter valid check for PCLK1 divider */ +#define IS_CLK_PCLK1_DIV(x) \ +( ((x) == CLK_PCLK1_DIV1) || \ + ((x) == CLK_PCLK1_DIV2) || \ + ((x) == CLK_PCLK1_DIV4) || \ + ((x) == CLK_PCLK1_DIV8) || \ + ((x) == CLK_PCLK1_DIV16) || \ + ((x) == CLK_PCLK1_DIV32) || \ + ((x) == CLK_PCLK1_DIV64)) + +/* Parameter valid check for PCLK4 divider */ +#define IS_CLK_PCLK4_DIV(x) \ +( ((x) == CLK_PCLK4_DIV1) || \ + ((x) == CLK_PCLK4_DIV2) || \ + ((x) == CLK_PCLK4_DIV4) || \ + ((x) == CLK_PCLK4_DIV8) || \ + ((x) == CLK_PCLK4_DIV16) || \ + ((x) == CLK_PCLK4_DIV32) || \ + ((x) == CLK_PCLK4_DIV64)) + +/* Parameter valid check for PCLK3 divider */ +#define IS_CLK_PCLK3_DIV(x) \ +( ((x) == CLK_PCLK3_DIV1) || \ + ((x) == CLK_PCLK3_DIV2) || \ + ((x) == CLK_PCLK3_DIV4) || \ + ((x) == CLK_PCLK3_DIV8) || \ + ((x) == CLK_PCLK3_DIV16) || \ + ((x) == CLK_PCLK3_DIV32) || \ + ((x) == CLK_PCLK3_DIV64)) + +/* Parameter valid check for EXCLK divider */ +#define IS_CLK_EXCLK_DIV(x) \ +( ((x) == CLK_EXCLK_DIV1) || \ + ((x) == CLK_EXCLK_DIV2) || \ + ((x) == CLK_EXCLK_DIV4) || \ + ((x) == CLK_EXCLK_DIV8) || \ + ((x) == CLK_EXCLK_DIV16) || \ + ((x) == CLK_EXCLK_DIV32) || \ + ((x) == CLK_EXCLK_DIV64)) + +/* Parameter valid check for PCLK0 divider */ +#define IS_CLK_PCLK0_DIV(x) \ +( ((x) == CLK_PCLK0_DIV1) || \ + ((x) == CLK_PCLK0_DIV2) || \ + ((x) == CLK_PCLK0_DIV4) || \ + ((x) == CLK_PCLK0_DIV8) || \ + ((x) == CLK_PCLK0_DIV16) || \ + ((x) == CLK_PCLK0_DIV32) || \ + ((x) == CLK_PCLK0_DIV64)) + +/* Parameter valid check for PCLK2 divider */ +#define IS_CLK_PCLK2_DIV(x) \ +( ((x) == CLK_PCLK2_DIV1) || \ + ((x) == CLK_PCLK2_DIV2) || \ + ((x) == CLK_PCLK2_DIV4) || \ + ((x) == CLK_PCLK2_DIV8) || \ + ((x) == CLK_PCLK2_DIV16) || \ + ((x) == CLK_PCLK2_DIV32) || \ + ((x) == CLK_PCLK2_DIV64)) + +/* Parameter valid check for bus clock */ +#define IS_CLK_BUS_CLK(x) \ +( ((x) == CLK_BUS_HCLK) || \ + ((x) == CLK_BUS_EXCLK) || \ + ((x) == CLK_BUS_PCLK0) || \ + ((x) == CLK_BUS_PCLK1) || \ + ((x) == CLK_BUS_PCLK2) || \ + ((x) == CLK_BUS_PCLK3) || \ + ((x) == CLK_BUS_PCLK4)) + +/* Parameter valid check for CAN clock source */ +#define IS_CLK_CANCLK(x) \ +( ((x) == CLK_MCANCLK_SYSCLK_DIV2) || \ + ((x) == CLK_MCANCLK_SYSCLK_DIV3) || \ + ((x) == CLK_MCANCLK_SYSCLK_DIV4) || \ + ((x) == CLK_MCANCLK_SYSCLK_DIV5) || \ + ((x) == CLK_MCANCLK_SYSCLK_DIV6) || \ + ((x) == CLK_MCANCLK_SYSCLK_DIV7) || \ + ((x) == CLK_MCANCLK_SYSCLK_DIV8) || \ + ((x) == CLK_MCANCLK_PLLQ) || \ + ((x) == CLK_MCANCLK_PLLR) || \ + ((x) == CLK_MCANCLK_XTAL )) + +/* Parameter valid check for CAN channel for clock source config */ +#define IS_CLK_CAN_UNIT(x) \ +( ((x) == CLK_MCAN1) || \ + ((x) == CLK_MCAN2)) + +/* Parameter valid check for peripheral source */ +#define IS_CLK_PERIPHCLK_SRC(x) \ +( ((x) == CLK_PERIPHCLK_PCLK) || \ + ((x) == CLK_PERIPHCLK_PLLQ) || \ + ((x) == CLK_PERIPHCLK_PLLR)) + +/* Parameter valid check for TPIU clock divider */ +#define IS_CLK_TPIUCLK_DIV(x) \ +( ((x) == CLK_TPIUCLK_DIV1) || \ + ((x) == CLK_TPIUCLK_DIV2) || \ + ((x) == CLK_TPIUCLK_DIV4)) + +/* Parameter valid check for CLK MCO clock source . */ +#define IS_CLK_MCO_SRC(x) \ +( ((x) == CLK_MCO_SRC_HRC) || \ + ((x) == CLK_MCO_SRC_MRC) || \ + ((x) == CLK_MCO_SRC_LRC) || \ + ((x) == CLK_MCO_SRC_XTAL) || \ + ((x) == CLK_MCO_SRC_XTAL32) || \ + ((x) == CLK_MCO_SRC_PLLP) || \ + ((x) == CLK_MCO_SRC_PLLQ) || \ + ((x) == CLK_MCO_SRC_HCLK)) + +/* Parameter valid check for CLK MCO clock divide. */ +#define IS_CLK_MCO_DIV(x) \ +( ((x) == CLK_MCO_DIV1) || \ + ((x) == CLK_MCO_DIV2) || \ + ((x) == CLK_MCO_DIV4) || \ + ((x) == CLK_MCO_DIV8) || \ + ((x) == CLK_MCO_DIV16) || \ + ((x) == CLK_MCO_DIV32) || \ + ((x) == CLK_MCO_DIV64) || \ + ((x) == CLK_MCO_DIV128)) + +/* Parameter valid check for CLK MCO channel. */ +#define IS_CLK_MCO_CH(x) \ +( ((x) == CLK_MCO1) || \ + ((x) == CLK_MCO2)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Functions CLK Local Functions + * @{ + */ +/** + * @brief Wait clock stable flag. + * @param [in] u8Flag Specifies the stable flag to be wait. @ref CLK_STB_Flag + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t + */ +static int32_t CLK_WaitStable(uint8_t u8Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_ERR_TIMEOUT; + + while (u32Timeout <= u32Time) { + if (SET == CLK_GetStableStatus(u8Flag)) { + i32Ret = LL_OK; + break; + } + u32Timeout++; + } + return i32Ret; +} + +static void SetSysClockSrc(uint8_t u8Src) +{ + uint8_t u8TmpFlag = 0U; + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_SYSCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW) || (CLK_SYSCLK_SRC_PLL == u8Src)) { + u8TmpFlag = 1U; + /* FCG0 protect judgment */ + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + /* Wait stable after close FCGx. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } + /* Set system clock source */ + WRITE_REG8(CM_CMU->CKSWR, u8Src); + /* Wait stable after setting system clock source */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } +} + +static void GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + stc_clock_scale_t *pstcClockScale; + uint32_t u32HrcValue; + uint8_t plln; + uint8_t pllp; + uint8_t pllm; + + switch (READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + case CLK_SYSCLK_SRC_HRC: + /* HRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLK_SRC_MRC: + /* MRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = MRC_VALUE; + break; + case CLK_SYSCLK_SRC_LRC: + /* LRC is used to system clock */ + pstcClockFreq->u32SysclkFreq = LRC_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL: + /* XTAL is used to system clock */ + pstcClockFreq->u32SysclkFreq = XTAL_VALUE; + break; + case CLK_SYSCLK_SRC_XTAL32: + /* XTAL32 is used to system clock */ + pstcClockFreq->u32SysclkFreq = XTAL32_VALUE; + break; + case CLK_SYSCLK_SRC_PLL: + /* PLLHP is used as system clock. */ + pllp = (uint8_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS); + plln = (uint8_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS); + pllm = (uint8_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS); + /* pll = ((pllin / pllm) * plln) / pllp */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pstcClockFreq->u32SysclkFreq = ((XTAL_VALUE / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } else { + u32HrcValue = HRC_VALUE; + pstcClockFreq->u32SysclkFreq = ((u32HrcValue / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + } + break; + default: + break; + } + + pstcClockScale = (stc_clock_scale_t *)((uint32_t)&CM_CMU->SCFGR); + pstcClockScale->SCFGR = READ_REG32(CM_CMU->SCFGR); + /* Get hclk. */ + pstcClockFreq->u32HclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.HCLKS; + /* Get pclk1. */ + pstcClockFreq->u32Pclk1Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK1S; + /* Get pclk4. */ + pstcClockFreq->u32Pclk4Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK4S; + /* Get pclk3. */ + pstcClockFreq->u32Pclk3Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK3S; + /* Get exclk. */ + pstcClockFreq->u32ExclkFreq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.EXCKS; + /* Get pclk0. */ + pstcClockFreq->u32Pclk0Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK0S; + /* Get pclk2. */ + pstcClockFreq->u32Pclk2Freq = pstcClockFreq->u32SysclkFreq >> pstcClockScale->SCFGR_f.PCLK2S; +} + +static void SetSysClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + uint8_t u8TmpFlag = 0U; + + /* backup FCGx setting */ + __IO uint32_t fcg0 = CM_PWC->FCG0; + __IO uint32_t fcg1 = CM_PWC->FCG1; + __IO uint32_t fcg2 = CM_PWC->FCG2; + __IO uint32_t fcg3 = CM_PWC->FCG3; + + DDL_ASSERT(IS_CLK_HCLK_DIV(u32Div & CMU_SCFGR_HCLKS)); + DDL_ASSERT(IS_CLK_PCLK1_DIV(u32Div & CMU_SCFGR_PCLK1S)); + DDL_ASSERT(IS_CLK_PCLK4_DIV(u32Div & CMU_SCFGR_PCLK4S)); + DDL_ASSERT(IS_CLK_EXCLK_DIV(u32Div & CMU_SCFGR_EXCKS)); + DDL_ASSERT(IS_CLK_PCLK0_DIV(u32Div & CMU_SCFGR_PCLK0S)); + DDL_ASSERT(IS_CLK_PCLK2_DIV(u32Div & CMU_SCFGR_PCLK2S)); + DDL_ASSERT(IS_CLK_PCLK3_DIV(u32Div & CMU_SCFGR_PCLK3S)); + DDL_ASSERT(IS_CLK_BUS_CLK_CATE(u32Clock)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + u8TmpFlag = 1U; + DDL_ASSERT((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + WRITE_REG32(CM_PWC->FCG0, CLK_FCG0_DEFAULT); + WRITE_REG32(CM_PWC->FCG1, CLK_FCG1_DEFAULT); + WRITE_REG32(CM_PWC->FCG2, CLK_FCG2_DEFAULT); + WRITE_REG32(CM_PWC->FCG3, CLK_FCG3_DEFAULT); + /* Wait stable after close FCGx. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } + MODIFY_REG32(CM_CMU->SCFGR, u32Clock, u32Div); + DDL_DelayUS(CLK_SYSCLK_SW_STB); + if (1U == u8TmpFlag) { + WRITE_REG32(CM_PWC->FCG0, fcg0); + WRITE_REG32(CM_PWC->FCG1, fcg1); + WRITE_REG32(CM_PWC->FCG2, fcg2); + WRITE_REG32(CM_PWC->FCG3, fcg3); + /* Wait stable after open fcg. */ + DDL_DelayUS(CLK_SYSCLK_SW_STB); + } +} + +/** + * @} + */ + +/** + * @defgroup CLK_Global_Functions CLK Global Functions + * @{ + */ +/** + * @brief LRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: LRC operate successfully + * - LL_ERR_BUSY: LRC is the system clock, CANNOT stop it. + * @note DO NOT STOP LRC while using it as system clock. + */ +int32_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_LRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->LRCCR, CLK_LRC_ON); + } + /* wait approx, 5 * LRC cycle */ + DDL_DelayUS(CLK_LRC_TIMEOUT); + + return i32Ret; +} + +/** + * @brief MRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: MRC operate successfully + * - LL_ERR_BUSY: MRC is the system clock, CANNOT stop it. + * @note DO NOT STOP MRC while using it as system clock. + */ +int32_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_MRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->MRCCR, CLK_MRC_ON); + } + /* Wait approx. 5 * MRC cycle */ + DDL_DelayUS(CLK_MRC_TIMEOUT); + + return i32Ret; +} + +/** + * @brief HRC function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: HRC operate successfully + * - LL_ERR_BUSY: HRC is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: HRC operate Timeout + * @note DO NOT STOP HRC while using it as system clock or as the PLL source clock. + */ +int32_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_HRC == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else if (CLK_PLL_SRC_HRC == PLL_SRC) { + /* HRC as PLL clock source and PLL is working */ + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_OFF); + } + } else { + WRITE_REG8(CM_CMU->HRCCR, CLK_HRC_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief Set HRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for HRC. + * @retval None + */ +void CLK_HrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->HRCTRM, i8TrimVal); +} + +/** + * @brief Set MRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for MRC. + * @retval None + */ +void CLK_MrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->MRCTRM, i8TrimVal); +} + +/** + * @brief Set LRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for LRC. + * @retval None + */ +void CLK_LrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->LRCTRM, i8TrimVal); +} + +/** + * @brief Init Xtal initial structure with default value. + * @param [in] pstcXtalInit specifies the Parameter of XTAL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_XtalStructInit(stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtalInit->u8State = CLK_XTAL_OFF; + pstcXtalInit->u8Mode = CLK_XTAL_MD_OSC; + pstcXtalInit->u8Drv = CLK_XTAL_DRV_HIGH; + pstcXtalInit->u8StableTime = CLK_XTAL_STB_2MS; + } + return i32Ret; +} + +/** + * @brief XTAL initialize. + * @param [in] pstcXtalInit specifies the XTAL initial config. + * @retval int32_t: + * - LL_OK: XTAL initial successfully. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * - LL_ERR_BUSY: XTAL is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL while using it as system clock. + */ +int32_t CLK_XtalInit(const stc_clock_xtal_init_t *pstcXtalInit) +{ + int32_t i32Ret; + + if (NULL == pstcXtalInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CLK_XTAL_STATE(pstcXtalInit->u8State)); + DDL_ASSERT(IS_CLK_XTAL_DRV_MD(pstcXtalInit->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL_MD(pstcXtalInit->u8Mode)); + DDL_ASSERT(IS_CLK_XTAL_STB_SEL(pstcXtalInit->u8StableTime)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTALSTBCR, pstcXtalInit->u8StableTime); + WRITE_REG8(CM_CMU->XTALCFGR, (0x80U | pstcXtalInit->u8Drv | pstcXtalInit->u8Mode)); + if (CLK_XTAL_ON == pstcXtalInit->u8State) { + i32Ret = CLK_XtalCmd(ENABLE); + } else { + i32Ret = CLK_XtalCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL operate successfully + * - LL_ERR_BUSY: XTAL is the system clock or as the PLL source clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: XTAL operate timeout. + * @note DO NOT STOP XTAL while using it as system clock or as the PLL source clock. + */ +int32_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else if (CLK_PLL_SRC_XTAL == PLL_SRC) { + /* XTAL as PLL clock source and PLL is working */ + if (0UL == PLL_EN_REG) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTALCR, CLK_XTAL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } + + return i32Ret; +} + +/** + * @brief XTAL divide function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_XtalDivCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + CLR_REG32_BIT(CM_CMU->XTALDIVCR, CMU_XTALDIVCR_FRADIVEN); + } else { + SET_REG32_BIT(CM_CMU->XTALDIVCR, CMU_XTALDIVCR_FRADIVEN); + } +} + +/** + * @brief Init Xtal divide initial structure with default value. + * @param [in] pstcXtalDivInit specifies the Parameter of XTAL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_XtalDivStructInit(stc_clock_xtaldiv_init_t *pstcXtalDivInit) +{ + int32_t i32Ret = LL_OK;; + + if (NULL == pstcXtalDivInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcXtalDivInit->u32State = CLK_XTALDIV_OFF; + pstcXtalDivInit->u32Num = 0x3D09U; + pstcXtalDivInit->u32Den = 0x40U; + } + + return i32Ret; +} + +/** + * @brief XTAL divide initialize. + * @param [in] pstcXtalDivInit specifies the XTAL initial config. + * @arg u32State : The new state of the XTAL divide. + * @arg u32Num : The numerator of XTAL divide. + * @arg u32Den : The denominator of XTAL divide. + * @retval int32_t: + * - LL_OK: XTAL divide initial successfully. + * - LL_ERR_INVD_PARAM: NULL pointer. + */ +int32_t CLK_XtalDivInit(const stc_clock_xtaldiv_init_t *pstcXtalDivInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcXtalDivInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_CLK_XTALDIV_STATE(pstcXtalDivInit->u32State)); + + WRITE_REG32(CM_CMU->XTALDIVR, (uint32_t)pstcXtalDivInit->u32Num << CMU_XTALDIVR_NUMER_POS | pstcXtalDivInit->u32Den); + WRITE_REG32(CM_CMU->XTALDIVCR, pstcXtalDivInit->u32State); + } + return i32Ret; +} + +/** + * @brief XTAL status detection function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_XtalStdCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + CLR_REG8_BIT(CM_CMU->XTALSTDCR, CMU_XTALSTDCR_XTALSTDE); + } else { + SET_REG8_BIT(CM_CMU->XTALSTDCR, CMU_XTALSTDCR_XTALSTDE); + } +} + +/** + * @brief Initialise the XTAL status detection. + * @param [in] u8State specifies the Parameter of XTALSTD. + * @param [in] u8ExceptionType specifies the Parameter of XTALSTD. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_XtalStdInit(uint8_t u8State, uint8_t u8ExceptionType) +{ + int32_t i32Ret = LL_OK; + + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_STATE(u8State)); + DDL_ASSERT(IS_CLK_XTALSTD_EXP_TYPE(u8ExceptionType)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if ((CLK_PLL_SRC_XTAL == PLL_SRC) && (u8ExceptionType == CLK_XTALSTD_EXP_TYPE_INT)) { + if (0UL == PLL_EN_REG) { + /* while xtal used as PLL clock source, XTALSTD only choose reset exception */ + i32Ret = LL_ERR_INVD_PARAM; + } + } + if (LL_OK == i32Ret) { + /* Initialize XTALSTD */ + WRITE_REG8(CM_CMU->XTALSTDCR, u8State | u8ExceptionType); + } + + return i32Ret; +} + +/** + * @brief Set XTALSTD exception type. + * @param [in] u8ExceptionType specifies the XTALSTD exception type. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t CLK_SetXtalStdExceptionType(uint8_t u8ExceptionType) +{ + int32_t i32Ret = LL_OK; + + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_EXP_TYPE(u8ExceptionType)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if ((CLK_PLL_SRC_XTAL == PLL_SRC) && (u8ExceptionType == CLK_XTALSTD_EXP_TYPE_INT)) { + if (0UL == PLL_EN_REG) { + /* while xtal used as PLL clock source, XTALSTD only choose reset exception */ + i32Ret = LL_ERR_INVD_PARAM; + } + } + if (LL_OK == i32Ret) { + /* Set exception type */ + MODIFY_REG8(CM_CMU->XTALSTDCR, CLK_XTALSTD_EXP_TYPE_MASK, u8ExceptionType); + } + + return i32Ret; +} + +/** + * @brief Clear the XTAL error flag. + * @param None + * @retval None + * @note The system clock should not be XTAL before call this function. + */ +void CLK_ClearXtalStdStatus(void) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (0x01U == READ_REG8(CM_CMU->XTALSTDSR)) { + /* Clear the XTAL STD flag */ + WRITE_REG8(CM_CMU->XTALSTDSR, 0x00U); + } +} + +/** + * @brief Get the XTAL error flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetXtalStdStatus(void) +{ + return ((0x00U != READ_REG8(CM_CMU->XTALSTDSR)) ? SET : RESET); +} + +/** + * @brief Init Xtal32 initial structure with default value. + * @param [in] pstcXtal32Init specifies the Parameter of XTAL32. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_Xtal32StructInit(stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcXtal32Init->u8State = CLK_XTAL32_ON; + pstcXtal32Init->u8Drv = CLK_XTAL32_DRV_MID; + pstcXtal32Init->u8Filter = CLK_XTAL32_FILTER_ALL_MD; + } + + return i32Ret; +} + +/** + * @brief XTAL32 initialize. + * @param [in] pstcXtal32Init specifies the XTAL32 initial config. + * @arg u8State : The new state of the XTAL32. + * @arg u8Drv : The XTAL32 drive capacity. + * @arg u8Filter : The XTAL32 noise filter on or off. + * @retval int32_t: + * - LL_OK: XTAL32 initial successfully. + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Init(const stc_clock_xtal32_init_t *pstcXtal32Init) +{ + int32_t i32Ret; + + if (NULL == pstcXtal32Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameters check */ + DDL_ASSERT(IS_CLK_XTAL32_STATE(pstcXtal32Init->u8State)); + DDL_ASSERT(IS_CLK_XTAL32_DRV_MD(pstcXtal32Init->u8Drv)); + DDL_ASSERT(IS_CLK_XTAL32_FILT_SEL(pstcXtal32Init->u8Filter)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(CM_CMU->XTAL32CFGR, pstcXtal32Init->u8Drv); + WRITE_REG8(CM_CMU->XTAL32NFR, pstcXtal32Init->u8Filter); + if (CLK_XTAL32_ON == pstcXtal32Init->u8State) { + i32Ret = CLK_Xtal32Cmd(ENABLE); + } else { + i32Ret = CLK_Xtal32Cmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief XTAL32 function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: XTAL32 operate successfully + * - LL_ERR_BUSY: XTAL32 is the system clock, CANNOT stop it. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +int32_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_XTAL32 == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_OFF); + } + } else { + WRITE_REG8(CM_CMU->XTAL32CR, CLK_XTAL32_ON); + /* wait stable*/ + } + /* wait approx. 5 * xtal32 cycle */ + DDL_DelayUS(CLK_XTAL32_TIMEOUT); + + return i32Ret; +} + +/** + * @brief Set PLL source clock. + * @param [in] u32PllSrc PLL source clock. + * @arg CLK_PLL_SRC_XTAL + * @arg CLK_PLL_SRC_HRC + * @retval None + */ +void CLK_SetPLLSrc(uint32_t u32PllSrc) +{ + DDL_ASSERT(IS_CLK_PLL_SRC(u32PllSrc)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, u32PllSrc << PLL_SRC_POS); +} + +/** + * @brief Init PLL initial structure with default value. + * @param [in] pstcPLLInit specifies the Parameter of PLL. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_PLLStructInit(stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcPLLInit->PLLCFGR = 0UL; + pstcPLLInit->PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + pstcPLLInit->PLLCFGR_f.PLLM = CLK_PLLM_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLN = CLK_PLLN_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLP = CLK_PLLP_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLQ = CLK_PLLQ_DEFAULT; + pstcPLLInit->PLLCFGR_f.PLLR = CLK_PLLR_DEFAULT; + pstcPLLInit->u8PLLState = CLK_PLL_OFF; + } + return i32Ret; +} + +/** + * @brief PLL initialize. + * @param [in] pstcPLLInit specifies the structure of PLLH initial config. + * @arg u8PLLState : The new state of the PLLH. + * @arg PLLCFGR : PLLH config. + * @retval int32_t: + * - LL_OK: PLLH initial successfully + * - LL_ERR_TIMEOUT: PLLH initial timeout + * - LL_ERR_BUSY: PLLH is the source clock, CANNOT stop it. + * - LL_ERR_INVD_PARAM: NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 8 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 600 ~ 1200MHz. + * The PLLH frequency (VCOOUT/PLLHP_Q_R) is between 40 ~ 240MHz. + */ +int32_t CLK_PLLInit(const stc_clock_pll_init_t *pstcPLLInit) +{ + int32_t i32Ret; +#ifdef __DEBUG + uint32_t vcoIn; + uint32_t vcoOut; +#endif + + if (NULL == pstcPLLInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CLK_PLL_SRC(pstcPLLInit->PLLCFGR_f.PLLSRC)); + DDL_ASSERT(IS_CLK_PLLM_DIV(pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLN_MULTI(pstcPLLInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLP_DIV(pstcPLLInit->PLLCFGR_f.PLLP + 1UL)); +#ifdef __DEBUG + vcoIn = ((CLK_PLL_SRC_XTAL == pstcPLLInit->PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLInit->PLLCFGR_f.PLLN + 1UL); + DDL_ASSERT(IS_CLK_PLL_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLL_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLP + 1UL))); + DDL_ASSERT(IS_CLK_PLLQ_DIV(pstcPLLInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLR_DIV(pstcPLLInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLL_FREQ(vcoOut / (pstcPLLInit->PLLCFGR_f.PLLQ + 1UL))); +#endif /* __DEBUG */ + DDL_ASSERT(IS_CLK_PLL_STATE(pstcPLLInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* set PLL source in advance */ + MODIFY_REG32(PLL_SRC_REG, PLL_SRC_BIT, pstcPLLInit->PLLCFGR_f.PLLSRC << PLL_SRC_POS); + WRITE_REG32(CM_CMU->PLLHCFGR, pstcPLLInit->PLLCFGR); + if (CLK_PLL_ON == pstcPLLInit->u8PLLState) { + i32Ret = CLK_PLLCmd(ENABLE); + } else { + i32Ret = CLK_PLLCmd(DISABLE); + } + } + + return i32Ret; +} + +/** + * @brief PLL function enable/disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: PLL operate successfully + * - LL_ERR_BUSY: PLL is the system clock, CANNOT stop it. + * - LL_ERR_TIMEOUT: PLL operate timeout + * @note DO NOT STOP PLL while using it as system clock. + */ +int32_t CLK_PLLCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (DISABLE == enNewState) { + if (CLK_SYSCLK_SRC_PLL == READ_REG8_BIT(CM_CMU->CKSWR, CMU_CKSWR_CKSW)) { + i32Ret = LL_ERR_BUSY; + } else { + WRITE_REG8(PLL_EN_REG, CLK_PLL_OFF); + } + } else { + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_XTAL, CLK_TIMEOUT); + } else { + i32Ret = CLK_WaitStable(CLK_STB_FLAG_HRC, CLK_TIMEOUT); + } + if (LL_OK == i32Ret) { + WRITE_REG8(PLL_EN_REG, CLK_PLL_ON); + i32Ret = CLK_WaitStable(CLK_STB_FLAG_PLL, CLK_TIMEOUT); + } + } + + return i32Ret; +} + +/** + * @brief Selects the clock source to output on MCO pin. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] u8Src Specifies the clock source to output. @ref CLK_MCO_Clock_Source + * @param [in] u8Div Specifies the MCOx prescaler. @ref CLK_MCO_Clock_Prescaler + * @retval None + * @note MCO pin should be configured in alternate function 1 mode. + */ +void CLK_MCOConfig(uint8_t u8Ch, uint8_t u8Src, uint8_t u8Div) +{ + __IO uint8_t *MCOCFGRx; + + /* Check the parameters. */ + DDL_ASSERT(IS_CLK_MCO_SRC(u8Src)); + DDL_ASSERT(IS_CLK_MCO_DIV(u8Div)); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + /* enable register write. */ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCO1CFGR + u8Ch)); + /* Config the MCO */ + MODIFY_REG8(*MCOCFGRx, (CMU_MCOCFGR_MCOSEL | CMU_MCOCFGR_MCODIV), (u8Src | u8Div)); +} + +/** + * @brief Enable or disable the MCO1 output. + * @param [in] u8Ch Specifies the MCO channel. @ref CLK_MCO_Channel_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_MCOCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + __IO uint8_t *MCOCFGRx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_CLK_MCO_CH(u8Ch)); + + MCOCFGRx = &(*(__IO uint8_t *)((uint32_t)&CM_CMU->MCO1CFGR + u8Ch)); + /* Enable or disable clock output. */ + MODIFY_REG8(*MCOCFGRx, CMU_MCOCFGR_MCOEN, (uint8_t)enNewState << CMU_MCOCFGR_MCOEN_POS); +} + +/** + * @brief PLL/XTAL/HRC stable flag read. + * @param [in] u8Flag specifies the stable flag to be read. @ref CLK_STB_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CLK_GetStableStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_CLK_STB_FLAG(u8Flag)); + + return ((0x00U != READ_REG8_BIT(CM_CMU->OSCSTBSR, u8Flag)) ? SET : RESET); +} + +/** + * @brief Set the system clock source. + * @param [in] u8Src specifies the source of system clock. @ref CLK_System_Clock_Source + * @retval None + */ +void CLK_SetSysClockSrc(uint8_t u8Src) +{ + /* Set system clock source */ + SetSysClockSrc(u8Src); + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Get bus clock frequency. + * @param [out] pstcClockFreq specifies the pointer to get bus frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_GetClockFreq(stc_clock_freq_t *pstcClockFreq) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcClockFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + GetClockFreq(pstcClockFreq); + } + return i32Ret; +} + +/** + * @brief Get bus clock frequency. + * @param [in] u32Clock specifies the bus clock to get frequency. @ref CLK_Bus_Clock_Sel + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +uint32_t CLK_GetBusClockFreq(uint32_t u32Clock) +{ + uint32_t u32ClockFreq; + DDL_ASSERT(IS_CLK_BUS_CLK(u32Clock)); + + switch (u32Clock) { + case CLK_BUS_HCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS); + break; + case CLK_BUS_PCLK1: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + break; + case CLK_BUS_PCLK4: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK4S) >> CMU_SCFGR_PCLK4S_POS); + break; + case CLK_BUS_PCLK3: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS); + break; + case CLK_BUS_EXCLK: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS); + break; + case CLK_BUS_PCLK0: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS); + break; + case CLK_BUS_PCLK2: + u32ClockFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK2S) >> CMU_SCFGR_PCLK2S_POS); + break; + default: + u32ClockFreq = SystemCoreClock; + break; + } + return u32ClockFreq; +} + +/** + * @brief Get PLL clock frequency. + * @param [out] pstcPllClkFreq specifies the pointer to get PLL frequency. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t CLK_GetPLLClockFreq(stc_pll_clock_freq_t *pstcPllClkFreq) +{ + int32_t i32Ret = LL_OK; + uint32_t pllin; + uint32_t plln; + uint32_t pllm; + uint32_t pllp; + uint32_t pllq; + uint32_t pllr; + + if (NULL == pstcPllClkFreq) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pllp = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHP) >> CMU_PLLHCFGR_PLLHP_POS); + pllq = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHQ) >> CMU_PLLHCFGR_PLLHQ_POS); + pllr = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHR) >> CMU_PLLHCFGR_PLLHR_POS); + plln = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHN) >> CMU_PLLHCFGR_PLLHN_POS); + pllm = (uint32_t)((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLHM) >> CMU_PLLHCFGR_PLLHM_POS); + + /* PLLHP is used as system clock. */ + if (CLK_PLL_SRC_XTAL == PLL_SRC) { + pllin = XTAL_VALUE; + } else { + pllin = HRC_VALUE; + } + pstcPllClkFreq->u32PllVcin = (pllin / (pllm + 1UL)); + pstcPllClkFreq->u32PllVco = ((pllin / (pllm + 1UL)) * (plln + 1UL)); + pstcPllClkFreq->u32PllP = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllp + 1UL); + pstcPllClkFreq->u32PllQ = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllq + 1UL); + pstcPllClkFreq->u32PllR = ((pllin / (pllm + 1UL)) * (plln + 1UL)) / (pllr + 1UL); + } + return i32Ret; +} + +/** + * @brief HCLK/PCLK divide setting. + * @param [in] u32Clock specifies the clock to be divided. @ref CLK_Bus_Clock_Sel + * @param [in] u32Div specifies the clock divide factor. @ref CLK_Clock_Divider + * @retval None + * @note u32Div could choose CLK_HCLK_Divider, CLK_PCLK0_Divider, CLK_PCLK1_Divider, + * CLK_PCLK2_Divider, CLK_PCLK3_Divider, CLK_PCLK4_Divider, CLK_EXCLK_Divider, according to the MCU + */ +void CLK_SetClockDiv(uint32_t u32Clock, uint32_t u32Div) +{ + /* Set clock divider */ + SetSysClockDiv(u32Clock, u32Div); + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Set peripheral clock source. + * @param [in] u16Src specifies the peripheral clock source. @ref CLK_PERIPH_Sel + * @retval None + */ +void CLK_SetPeriClockSrc(uint16_t u16Src) +{ + DDL_ASSERT(IS_CLK_PERIPHCLK_SRC(u16Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG8(CM_CMU->PERICKSEL, u16Src); +} + +/** + * @brief CAN clock source config. + * @param [in] u8Unit specifies the CAN channel for clock source. @ref CLK_CAN_Sel + * @param [in] u8Src specifies the CAN clock source. @ref CLK_CANCLK_Sel + * @retval None + */ +void CLK_SetCANClockSrc(uint8_t u8Unit, uint8_t u8Src) +{ + uint32_t u32UnitPos = 0UL; + + DDL_ASSERT(IS_CLK_CAN_UNIT(u8Unit)); + DDL_ASSERT(IS_CLK_CANCLK(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + while (0UL != u8Unit) { + if (0UL != (u8Unit & 0x1UL)) { + MODIFY_REG16(CM_CMU->CANCKCFGR, (uint32_t)CMU_CANCKCFGR_MCAN1CKS << u32UnitPos, (uint32_t)u8Src << u32UnitPos); + } + u8Unit >>= 1UL; + u32UnitPos += 4U; + } +} + +/** + * @brief Enable or disable the TPIU clock. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CLK_TpiuClockCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKOE, (uint8_t)enNewState << CMU_TPIUCKCFGR_TPIUCKOE_POS); +} + +/** + * @brief TPIU clock divider config. + * @param [in] u8Div specifies the TPIU clock divide factor. @ref CLK_TPIU_Divider + * @arg CLK_TPIUCLK_DIV1: TPIU clock no divide + * @arg CLK_TPIUCLK_DIV2: TPIU clock divide by 2 + * @arg CLK_TPIUCLK_DIV4: TPIU clock divide by 4 + * @retval None + */ +void CLK_SetTpiuClockDiv(uint8_t u8Div) +{ + DDL_ASSERT(IS_CLK_TPIUCLK_DIV(u8Div)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(CM_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKS, u8Div); +} +/** + * @} + */ + +#endif /* LL_CLK_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c new file mode 100644 index 0000000000..0825559f70 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_cmp.c @@ -0,0 +1,1002 @@ +/** + ******************************************************************************* + * @file hc32_ll_cmp.c + * @brief This file provides firmware functions to manage the Comparator(CMP). + * + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_cmp.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CMP CMP + * @brief CMP Driver Library + * @{ + */ + +#if (LL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Macros CMP Local Macros + * @{ + */ + +/** + * @defgroup CMP_Check_Parameters_Validity CMP Check Parameters Validity + * @{ + */ +#define IS_CMP_UNIT(x) \ +( ((x) == CM_CMP1) || \ + ((x) == CM_CMP2) || \ + ((x) == CM_CMP3) || \ + ((x) == CM_CMP4)) + +#define IS_CMP_WIN_MD_UNIT(x) \ +( ((x) == CMP_WIN_CMP12) || \ + ((x) == CMP_WIN_CMP34)) + +#define IS_CMP_POSITIVE_IN(x) \ +( ((x) == CMP_POSITIVE_NONE) || \ + ((x) == CMP_POSITIVE_INP1) || \ + ((x) == CMP_POSITIVE_INP2) || \ + ((x) == CMP_POSITIVE_INP3) || \ + ((x) == CMP_POSITIVE_INP4)) + +#define IS_CMP_NEGATIVE_IN(x) \ +( ((x) == CMP_NEGATIVE_NONE) || \ + ((x) == CMP_NEGATIVE_INM1) || \ + ((x) == CMP_NEGATIVE_INM2) || \ + ((x) == CMP_NEGATIVE_INM3) || \ + ((x) == CMP_NEGATIVE_INM4)) + +#define IS_CMP_WIN_LOW_IN(x) \ +( ((x) == CMP_WIN_LOW_NONE) || \ + ((x) == CMP_WIN_LOW_INM1) || \ + ((x) == CMP_WIN_LOW_INM2) || \ + ((x) == CMP_WIN_LOW_INM3) || \ + ((x) == CMP_WIN_LOW_INM4)) + +#define IS_CMP_WIN_HIGH_IN(x) \ +( ((x) == CMP_WIN_HIGH_NONE) || \ + ((x) == CMP_WIN_HIGH_INM1) || \ + ((x) == CMP_WIN_HIGH_INM2) || \ + ((x) == CMP_WIN_HIGH_INM3) || \ + ((x) == CMP_WIN_HIGH_INM4)) + +#define IS_CMP_WIN12_POSITIVE_IN(x) \ +( ((x) == CMP_WIN_POSITIVE_NONE) || \ + ((x) == CMP_WIN_POSITIVE_INP4)) + +#define IS_CMP_WIN34_POSITIVE_IN(x) \ +( ((x) == CMP_WIN_POSITIVE_NONE) || \ + ((x) == CMP_WIN_POSITIVE_INP2) || \ + ((x) == CMP_WIN_POSITIVE_INP3)) + +#define IS_CMP_SCAN_STABLE(x) \ +( (x) <= 0x3FU) + +#define IS_CMP_SCAN_PERIOD(x) \ +( ((x) > 0x08U) && \ + ((x) <= 0xFFU)) + +#define IS_CMP_SCAN_SRC(x) \ +( ((x) & (~CMP_SCCR_SISL)) == 0U) + +#define IS_CMP_SCAN_MD(x) \ +( ((x) == CMP_SCAN_NONE) || \ + ((x) == CMP_SCAN_INP) || \ + ((x) == CMP_SCAN_INM)) + +#define IS_CMP_OUT_POLARITY(x) \ +( ((x) == CMP_OUT_INVT_OFF) || \ + ((x) == CMP_OUT_INVT_ON)) + +#define IS_CMP_OUT_FILTER(x) \ +( ((x) == CMP_OUT_FILTER_NONE) || \ + ((x) == CMP_OUT_FILTER_CLK) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV2) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV4) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV8) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV16) || \ + ((x) == CMP_OUT_FILTER_CLK_DIV32)) + +#define IS_CMP_OUT_DETECT_EDGE(x) \ +( ((x) == CMP_DETECT_EDGS_NONE) || \ + ((x) == CMP_DETECT_EDGS_RISING) || \ + ((x) == CMP_DETECT_EDGS_FALLING) || \ + ((x) == CMP_DETECT_EDGS_BOTH)) + +#define IS_CMP_OUT_DETECT_EDGE_FLAG(x) \ +( ((x) == CMP_DETECT_EDGS_RISING) || \ + ((x) == CMP_DETECT_EDGS_FALLING) || \ + ((x) == CMP_DETECT_EDGS_BOTH)) + +#define IS_CMP_BLANKWIN_VALID_LVL(x) \ +( ((x) == CMP_BLANKWIN_VALID_LVL_LOW) || \ + ((x) == CMP_BLANKWIN_VALID_LVL_HIGH)) + +#define IS_CMP_BLANKWIN_OUT_LVL(x) \ +( ((x) == CMP_BLANKWIN_OUTPUT_LVL_LOW) || \ + ((x) == CMP_BLANKWIN_OUTPUT_LVL_HIGH) || \ + ((x) == CMP_BLANKWIN_OUTPUT_LVL_HOLD)) + +#define IS_CMP_BLANKWIN_MD(x) \ +( ((x) == CMP_BLANKWIN_MD_LVL) || \ + ((x) == CMP_BLANKWIN_MD_EDGE)) + +#define IS_CMP_BLANKWIN_EDGE(x) \ +( ((x) == CMP_BLANKWIN_VALID_EDGE_NONE) || \ + ((x) == CMP_BLANKWIN_VALID_EDGE_RISING) || \ + ((x) == CMP_BLANKWIN_VALID_EDGE_FALLING) || \ + ((x) == CMP_BLANKWIN_VALID_EDGE_ALL)) + +#define IS_CMP_BLANKWIN_MASK_WIDTH(x) \ +( (x) <= 255U) + +/** + * @} + */ + +#define CMP_SCAN_PERIOD_IMME (0x08U) + +#define CMP_MDR_CENB (CMP_MDR_CENA) +#define CMP_OCR_TWOE (CMP_OCR_BWEN) +#define CMP_OCR_TWOL (CMP_OCR_BWOL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Functions CMP Local Functions + * @{ + */ + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +static void CMP_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = HCLK_VALUE / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + ; + } + } +} + +/** + * @brief Get CMP function status and disable CMP + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval uint16_t The register value + */ +static uint16_t GetCmpFuncStatusAndDisFunc(CM_CMP_TypeDef *CMPx) +{ + uint16_t u16temp; + /* It is possible that the interrupt may occurs after CMP status switch. */ + DDL_ASSERT(READ_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN) == 0U); + + /* Read CMP status */ + u16temp = (uint16_t)(uint8_t)READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Stop CMP function */ + CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + return u16temp; +} + +/** + * @brief Recover CMP function status + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpFuncStatus CMP function status backup value + * @retval None + */ +static void RecoverCmpFuncStatus(CM_CMP_TypeDef *CMPx, uint16_t u16CmpFuncStatus) +{ + if (u16CmpFuncStatus != 0U) { + /* Recover CMP status */ + MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u16CmpFuncStatus); + /* Delay 1us */ + CMP_DelayUS(1U); + } +} + +/** + * @} + */ + +/** + * @defgroup CMP_Global_Functions CMP Global Functions + * @{ + */ + +/** + * @brief Initialize structure stc_cmp_init_t variable with default value. + * @param [in] pstcCmpInit Pointer to a structure variable which will be initialized. @ref stc_cmp_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_StructInit(stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcCmpInit != NULL) { + pstcCmpInit->u16PositiveInput = CMP_POSITIVE_NONE; + pstcCmpInit->u16NegativeInput = CMP_NEGATIVE_NONE; + pstcCmpInit->u16OutPolarity = CMP_OUT_INVT_OFF; + pstcCmpInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE; + pstcCmpInit->u16OutFilter = CMP_OUT_FILTER_NONE; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Initialize structure stc_cmp_window_init_t variable with default value. + * @param [in] pstcCmpWindowInit Pointer to a structure variable. @ref stc_cmp_window_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_WindowStructInit(stc_cmp_window_init_t *pstcCmpWindowInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcCmpWindowInit != NULL) { + pstcCmpWindowInit->u16PositiveInput = CMP_WIN_POSITIVE_NONE; + pstcCmpWindowInit->u16WinVolLow = CMP_NEGATIVE_NONE; + pstcCmpWindowInit->u16WinVolHigh = CMP_NEGATIVE_NONE; + pstcCmpWindowInit->u16OutPolarity = CMP_OUT_INVT_OFF; + pstcCmpWindowInit->u16OutDetectEdge = CMP_DETECT_EDGS_NONE; + pstcCmpWindowInit->u16OutFilter = CMP_OUT_FILTER_NONE; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Initialize structure stc_cmp_blankwindow_t variable with default value. + * @param [in] pstcBlankWindowConfig Pointer to a structure variable. @ref stc_cmp_blankwindow_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_BlankWindowStructInit(stc_cmp_blankwindow_t *pstcBlankWindowConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcBlankWindowConfig != NULL) { + pstcBlankWindowConfig->u8Mode = CMP_BLANKWIN_MD_LVL; + pstcBlankWindowConfig->u16ValidLevelEdge = CMP_BLANKWIN_VALID_LVL_LOW; + pstcBlankWindowConfig->u16MaskWidth = 0U; + pstcBlankWindowConfig->u8OutLevel = CMP_BLANKWIN_OUTPUT_LVL_LOW; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize CMP unit + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval None + */ +void CMP_DeInit(CM_CMP_TypeDef *CMPx) +{ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + + CLR_REG8(CMPx->MDR); + CLR_REG8(CMPx->FIR); + CLR_REG8(CMPx->OCR); + CLR_REG32(CMPx->PMSR); + CLR_REG32(CMPx->BWSR1); + CLR_REG16(CMPx->BWSR2); + CLR_REG32(CMPx->SCCR); + CLR_REG32(CMPx->SCMR); +} + +/** + * @brief CMP normal mode initialize + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] pstcCmpInit CMP function base parameter structure + * @arg pstcCmpInit->u16PositiveInput: @ref CMP_Positive_Input_Select + * @arg pstcCmpInit->u16NegativeInput: @ref CMP_Negative_Input_Select + * @arg pstcCmpInit->u16OutPolarity: @ref CMP_Out_Polarity_Select + * @arg pstcCmpInit->u16OutDetectEdge: @ref CMP_Out_Detect_Edge_Select + * @arg pstcCmpInit->u16OutFilter: @ref CMP_Out_Filter + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_NormalModeInit(CM_CMP_TypeDef *CMPx, const stc_cmp_init_t *pstcCmpInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcCmpInit) { + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u16OutPolarity)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u16OutDetectEdge)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u16OutFilter)); + DDL_ASSERT(IS_CMP_POSITIVE_IN(pstcCmpInit->u16PositiveInput)); + DDL_ASSERT(IS_CMP_NEGATIVE_IN(pstcCmpInit->u16NegativeInput)); + + /* Stop CMP compare */ + CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + + /* Set voltage in */ + WRITE_REG32(CMPx->PMSR, ((uint32_t)pstcCmpInit->u16PositiveInput << CMP_PMSR_CVSL_POS) | (uint32_t)pstcCmpInit->u16NegativeInput); + + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Start CMP compare */ + SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + WRITE_REG8(CMPx->FIR, (pstcCmpInit->u16OutFilter | pstcCmpInit->u16OutDetectEdge)); + WRITE_REG8(CMPx->OCR, pstcCmpInit->u16OutPolarity); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Voltage compare function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_FuncCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + CMP_DelayUS(1U); + } else { + CLR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + } + +} + +/** + * @brief Voltage compare interrupt function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_IntCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN); + } else { + CLR_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN); + } +} + +/** + * @brief Voltage compare output command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_CompareOutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_COEN); + } else { + CLR_REG8_BIT(CMPx->OCR, CMP_OCR_COEN); + } +} + +/** + * @brief Voltage compare output port VCOUT function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_PinVcoutCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE); + } else { + CLR_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE); + } + +} + +/** + * @brief Voltage compare result flag read + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An @ref en_flag_status_t enumeration type value. + * In normal mode + * - RESET: compare voltage < reference voltage + * - SET: compare voltage > reference voltage + * In Window mode + * - RESET: compare voltage < reference low voltage or compare voltage > reference high voltage + * - SET: reference low voltage < compare voltage < reference high voltage + */ +en_flag_status_t CMP_GetStatus(const CM_CMP_TypeDef *CMPx) +{ + en_flag_status_t enRet; + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + enRet = (READ_REG8_BIT(CMPx->MDR, CMP_MDR_CMON) != 0U) ? SET : RESET; + return enRet; +} + +/** + * @brief Set output detect edge + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpEdges CMP output detect edge selection. @ref CMP_Out_Detect_Edge_Select + * @retval None + */ +void CMP_SetOutDetectEdge(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(u8CmpEdges)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output detect edge selection */ + MODIFY_REG8(CMPx->FIR, CMP_FIR_EDGS, u8CmpEdges); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set output filter + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpFilter CMP output filter selection. @ref CMP_Out_Filter + * @retval None + */ +void CMP_SetOutFilter(CM_CMP_TypeDef *CMPx, uint8_t u8CmpFilter) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_FILTER(u8CmpFilter)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + /* CMP output filter selection */ + MODIFY_REG8(CMPx->FIR, CMP_FIR_FCKS, u8CmpFilter); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Clear output detect edge flag + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpEdges CMP output detect edge selection. + * @arg CMP_DETECT_EDGS_RISING + * @arg CMP_DETECT_EDGS_FALLING + * @arg CMP_DETECT_EDGS_BOTH + * @retval None + */ +void CMP_ClearOutDetectFlag(CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE_FLAG(u8CmpEdges)); + MODIFY_REG8(CMPx->FIR, CMP_FIR_CFF | CMP_FIR_CRF, u8CmpEdges << (CMP_FIR_CFF_POS - CMP_FIR_EDGS_POS)); +} + +/** + * @brief Get output detect edge flags + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8CmpEdges CMP output detect edge selection. + * @arg CMP_DETECT_EDGS_RISING + * @arg CMP_DETECT_EDGS_FALLING + * @arg CMP_DETECT_EDGS_BOTH + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CMP_GetOutDetectFlag(const CM_CMP_TypeDef *CMPx, uint8_t u8CmpEdges) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE_FLAG(u8CmpEdges)); + return ((0U != READ_REG8_BIT(CMPx->FIR, u8CmpEdges << (CMP_FIR_CFF_POS - CMP_FIR_EDGS_POS))) ? SET : RESET); +} + +/** + * @brief Set output polarity + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16CmpPolarity CMP output polarity selection. @ref CMP_Out_Polarity_Select + * @retval None + */ +void CMP_SetOutPolarity(CM_CMP_TypeDef *CMPx, uint16_t u16CmpPolarity) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(u16CmpPolarity)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* CMP output polarity selection */ + MODIFY_REG8(CMPx->OCR, CMP_OCR_COPS, u16CmpPolarity); + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set positive in(compare voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16PositiveInput @ref CMP_Positive_Input_Select + * @retval None + */ +void CMP_SetPositiveInput(CM_CMP_TypeDef *CMPx, uint16_t u16PositiveInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_POSITIVE_IN(u16PositiveInput)); + + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG32(CMPx->PMSR, CMP_PMSR_CVSL, (uint32_t)u16PositiveInput << CMP_PMSR_CVSL_POS); + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief Set negative in(reference voltage) + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16NegativeInput @ref CMP_Negative_Input_Select + * @retval None + */ +void CMP_SetNegativeInput(CM_CMP_TypeDef *CMPx, uint16_t u16NegativeInput) +{ + uint16_t u16temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_NEGATIVE_IN(u16NegativeInput)); + /* Read CMP status */ + u16temp = GetCmpFuncStatusAndDisFunc(CMPx); + + /* Set voltage in */ + MODIFY_REG32(CMPx->PMSR, CMP_PMSR_RVSL, u16NegativeInput); + + /* Recover CMP function */ + RecoverCmpFuncStatus(CMPx, u16temp); +} + +/** + * @brief CMP window mode initialize + * @param [in] u8WinCMPx @ref CMP_Window_Mode_Unit + * @param [in] pstcCmpWindowInit CMP function base parameter structure @ref stc_cmp_window_init_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_WindowModeInit(uint8_t u8WinCMPx, const stc_cmp_window_init_t *pstcCmpWindowInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check configuration structure */ + if (NULL != pstcCmpWindowInit) { + /* Check parameters */ + DDL_ASSERT(IS_CMP_WIN_MD_UNIT(u8WinCMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpWindowInit->u16OutPolarity)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpWindowInit->u16OutDetectEdge)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpWindowInit->u16OutFilter)); + DDL_ASSERT(IS_CMP_WIN_LOW_IN(pstcCmpWindowInit->u16WinVolLow)); + DDL_ASSERT(IS_CMP_WIN_HIGH_IN(pstcCmpWindowInit->u16WinVolHigh)); + if (u8WinCMPx == CMP_WIN_CMP12) { + DDL_ASSERT(IS_CMP_WIN12_POSITIVE_IN(pstcCmpWindowInit->u16PositiveInput)); + } else { + DDL_ASSERT(IS_CMP_WIN34_POSITIVE_IN(pstcCmpWindowInit->u16PositiveInput)); + } + + CM_CMP_TypeDef *pCMP_MAIN; + CM_CMP_TypeDef *pCMP_MINOR; + + if (u8WinCMPx == CMP_WIN_CMP12) { + pCMP_MAIN = CM_CMP2; + pCMP_MINOR = CM_CMP1; + } else { + pCMP_MAIN = CM_CMP4; + pCMP_MINOR = CM_CMP3; + } + /* Stop CMP compare */ + CLR_REG8_BIT(pCMP_MINOR->MDR, CMP_MDR_CENB); + CLR_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CENB); + + /* Set positive in(compare voltage), window voltage */ + WRITE_REG32(pCMP_MINOR->PMSR, + ((uint32_t)pstcCmpWindowInit->u16PositiveInput << CMP_PMSR_CVSL_POS) + | (uint32_t)pstcCmpWindowInit->u16WinVolLow); + WRITE_REG32(pCMP_MAIN->PMSR, + ((uint32_t)pstcCmpWindowInit->u16PositiveInput << CMP_PMSR_CVSL_POS) + | (uint32_t)pstcCmpWindowInit->u16WinVolHigh); + /* Select window compare mode */ + SET_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CWDE); + /* Start CMP compare function */ + SET_REG8_BIT(pCMP_MINOR->MDR, CMP_MDR_CENB); + SET_REG8_BIT(pCMP_MAIN->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + CMP_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + WRITE_REG8(pCMP_MAIN->FIR, pstcCmpWindowInit->u16OutFilter | pstcCmpWindowInit->u16OutDetectEdge); + WRITE_REG8(pCMP_MAIN->OCR, pstcCmpWindowInit->u16OutPolarity); + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Blank window function disable specified window source + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16BlankWindowSrc Blank window source. can be any combination of @ref CMP_BlankWindow_Src + * @retval None + */ +void CMP_BlankWindowSrcDisable(CM_CMP_TypeDef *CMPx, uint16_t u16BlankWindowSrc) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + + /* Set blank window valid level high */ + CLR_REG32_BIT(CMPx->BWSR1, (uint32_t)u16BlankWindowSrc << CMP_BWSR1_CTWP0_POS); + /* Disable blank window source */ + CLR_REG32_BIT(CMPx->BWSR1, u16BlankWindowSrc); +} + +/** + * @brief Voltage compare blank window function configuration + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] pstcBlankWindowConfig Configuration structure for blank window mode. + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_BlankWindowConfig(CM_CMP_TypeDef *CMPx, const stc_cmp_blankwindow_t *pstcBlankWindowConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcBlankWindowConfig) { + i32Ret = LL_OK; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_BLANKWIN_MD(pstcBlankWindowConfig->u8Mode)); + if (CMP_BLANKWIN_MD_LVL == pstcBlankWindowConfig->u8Mode) { + DDL_ASSERT(IS_CMP_BLANKWIN_VALID_LVL(pstcBlankWindowConfig->u16ValidLevelEdge)); + } else { + DDL_ASSERT(IS_CMP_BLANKWIN_EDGE(pstcBlankWindowConfig->u16ValidLevelEdge)); + DDL_ASSERT(IS_CMP_BLANKWIN_MASK_WIDTH(pstcBlankWindowConfig->u16MaskWidth)); + } + DDL_ASSERT(IS_CMP_BLANKWIN_OUT_LVL(pstcBlankWindowConfig->u8OutLevel)); + + /* Select blank window mode and output level when blank window valid */ + MODIFY_REG8(CMPx->OCR, CMP_OCR_TWOL | CMP_OCR_BWMD, + pstcBlankWindowConfig->u8OutLevel | pstcBlankWindowConfig->u8Mode); + if (CMP_BLANKWIN_MD_LVL == pstcBlankWindowConfig->u8Mode) { + /* Select blank window valid level */ + if (CMP_BLANKWIN_VALID_LVL_LOW == pstcBlankWindowConfig->u16ValidLevelEdge) { + SET_REG32_BIT(CMPx->BWSR1, (uint32_t)pstcBlankWindowConfig->u16Src << CMP_BWSR1_CTWP0_POS); + } else { + CLR_REG32_BIT(CMPx->BWSR1, (uint32_t)pstcBlankWindowConfig->u16Src << CMP_BWSR1_CTWP0_POS); + } + } else { + WRITE_REG16(CMPx->BWSR2, + pstcBlankWindowConfig->u16ValidLevelEdge | pstcBlankWindowConfig->u16MaskWidth); + } + /* Select blank window source */ + SET_REG32_BIT(CMPx->BWSR1, pstcBlankWindowConfig->u16Src); + } + return i32Ret; +} + +/** + * @brief CMP out blank window function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_BlankWindowCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE); + } else { + CLR_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE); + } +} +/** + * @brief CMP blank window mode set + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u8Mode Blank window mode @ref CMP_BlankWindow_Mode. + * @retval None + */ +void CMP_BlankWindowMode(CM_CMP_TypeDef *CMPx, uint8_t u8Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_BLANKWIN_MD(u8Mode)); + MODIFY_REG8(CMPx->OCR, CMP_OCR_BWMD, u8Mode); +} + +/** + * @brief Get CMP scan INP source + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An uint32_t value @ref CMP_Scan_Inp_Status + */ +uint32_t CMP_GetScanInpSrc(CM_CMP_TypeDef *CMPx) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + return READ_REG32_BIT(CMPx->SCMR, CMP_SCMR_CVST); +} + +/** + * @brief Get CMP scan INM source + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @retval An uint16_t value @ref CMP_Scan_Inm_Status + */ +uint32_t CMP_GetScanInmSrc(CM_CMP_TypeDef *CMPx) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + return READ_REG32_BIT(CMPx->SCMR, CMP_SCMR_RVST); +} + +/** + * @brief CMP set scan input source + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16Src INM or INP source select for scan mode, it can be any combination of member of + * @ref CMP_Scan_Inm_Inp_Src + * @retval None + */ +void CMP_ScanSetSrc(CM_CMP_TypeDef *CMPx, uint16_t u16Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_SCAN_MD(CMPx->MDR)); + DDL_ASSERT(IS_CMP_SCAN_SRC(u16Src)); + + MODIFY_REG32(CMPx->SCCR, CMP_SCCR_SISL, u16Src); +} + +/** + * @brief CMP set scan mode + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16Mode CMP scan mode @ref CMP_Scan_Mode + * @retval None + */ +void CMP_ScanSetMode(CM_CMP_TypeDef *CMPx, uint16_t u16Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_SCAN_MD(u16Mode)); + + MODIFY_REG8(CMPx->MDR, CMP_MDR_CSMD, u16Mode); +} + +/** + * @brief CMP scan function configuration + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] pstcCmpScanConfig Configuration structure for scan mode. + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_ScanConfig(CM_CMP_TypeDef *CMPx, stc_cmp_scan_config_t *pstcCmpScanConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint16_t u16Fltsl; + uint16_t u16FltslDiv; + /* Check instance and configuration structure*/ + if (NULL != pstcCmpScanConfig) { + i32Ret = LL_OK; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_SCAN_MD(pstcCmpScanConfig->u16Mode)); + DDL_ASSERT(IS_CMP_SCAN_STABLE(pstcCmpScanConfig->u16Stable)); + DDL_ASSERT(IS_CMP_SCAN_PERIOD(pstcCmpScanConfig->u16Period)); + DDL_ASSERT(IS_CMP_SCAN_SRC(pstcCmpScanConfig->u16Src)); + + u16Fltsl = READ_REG16_BIT(CMPx->FIR, CMP_FIR_FCKS); + if (0U != u16Fltsl) { + u16FltslDiv = ((uint16_t)1U << (u16Fltsl - 1U)); + } else { + u16FltslDiv = 0U; + } + if (pstcCmpScanConfig->u16Period <= (pstcCmpScanConfig->u16Stable + u16FltslDiv * 4U + CMP_SCAN_PERIOD_IMME)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + MODIFY_REG32(CMPx->SCCR, CMP_SCCR_SSTB | CMP_SCCR_SPRD | CMP_SCCR_SISL, + ((uint32_t)pstcCmpScanConfig->u16Stable << CMP_SCCR_SSTB_POS) | + ((uint32_t)pstcCmpScanConfig->u16Period << CMP_SCCR_SPRD_POS) | + pstcCmpScanConfig->u16Src); + MODIFY_REG8(CMPx->MDR, CMP_MDR_CSMD, pstcCmpScanConfig->u16Mode); + } + } + return i32Ret; +} + +/** + * @brief Initialize structure stc_cmp_scan_config_t variable with default value. + * @param [in] pstcCmpScanConfig Pointer to a structure variable. @ref stc_cmp_scan_config_t + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t CMP_ScanStructInit(stc_cmp_scan_config_t *pstcCmpScanConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (pstcCmpScanConfig != NULL) { + pstcCmpScanConfig->u16Mode = CMP_SCAN_NONE; + pstcCmpScanConfig->u16Src = 0U; + pstcCmpScanConfig->u16Stable = 0U; + pstcCmpScanConfig->u16Period = 9U; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Get CMP scan function stable time and period configuration + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] u16Stable The CMP stable time = T(CMP clock) x u16Stable, The stable time is recommended + * greater than 100nS + * @arg range from 0x00U to 0x3FU + * @param [in] u16Period CMP scan period = T(CMP clock) x u16Period + * @arg range from 0x09 to 0xFF + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + * @note 1. u16Period > (u16Stable + u16OutFilter * 4 + CMP_SCAN_PERIOD_IMME) + * u16OutFilter is configured in CMP_NormalModeInit() function. + */ +int32_t CMP_ScanTimeConfig(CM_CMP_TypeDef *CMPx, uint16_t u16Stable, uint16_t u16Period) +{ + uint16_t u16Fltsl; + uint16_t u16FltslDiv; + int32_t i32Ret = LL_OK; + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_CMP_SCAN_STABLE(u16Stable)); + DDL_ASSERT(IS_CMP_SCAN_PERIOD(u16Period)); + + u16Fltsl = READ_REG16_BIT(CMPx->FIR, CMP_FIR_FCKS); + if (0U != u16Fltsl) { + u16FltslDiv = ((uint16_t)1U << (u16Fltsl - 1U)); + } else { + u16FltslDiv = 0U; + } + + if (u16Period <= (u16Stable + u16FltslDiv * 4U + CMP_SCAN_PERIOD_IMME)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + MODIFY_REG32(CMPx->SCCR, CMP_SCCR_SSTB | CMP_SCCR_SPRD, + ((uint32_t)u16Stable << CMP_SCCR_SSTB_POS) | ((uint32_t)u16Period << CMP_SCCR_SPRD_POS)); + } + return i32Ret; +} + +/** + * @brief CMP scan function command + * @param [in] CMPx Pointer to CMP instance register base + * @arg CM_CMPx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CMP_ScanCmd(CM_CMP_TypeDef *CMPx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_UNIT(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + MODIFY_REG8(CMPx->MDR, CMP_MDR_CSST, (uint8_t)enNewState << CMP_MDR_CSST_POS); +} + +/** + * @} + */ + +#endif /* LL_CMP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c new file mode 100644 index 0000000000..5f2b70f5b8 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_crc.c @@ -0,0 +1,565 @@ +/** + ******************************************************************************* + * @file hc32_ll_crc.c + * @brief This file provides firmware functions to manage the Cyclic Redundancy + * Check(CRC). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_crc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CRC CRC + * @brief Cyclic Redundancy Check Driver Library + * @{ + */ + +#if (LL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Macros CRC Local Macros + * @{ + */ + +/** + * @defgroup CRC_Check_Parameters_Validity CRC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for CRC protocol. */ +#define IS_CRC_PROTOCOL(x) \ +( ((x) == CRC_CRC16) || \ + ((x) == CRC_CRC32)) + +/*! Parameter validity check for CRC data width. */ +#define IS_CRC_DATA_WIDTH(x) \ +( ((x) == CRC_DATA_WIDTH_8BIT) || \ + ((x) == CRC_DATA_WIDTH_16BIT) || \ + ((x) == CRC_DATA_WIDTH_32BIT)) + +/** + * @} + */ + +/** + * @defgroup CRC_Registers_Reset_Value_definition CRC Registers Reset Value + * @{ + */ +#define CRC_CR_RST_VALUE (0x0001UL) +/** + * @} + */ + +/** + * @defgroup CRC_DATA_Register_Address CRC Data Register Address + * @{ + */ +#define CRC_DATA_ADDR ((uint32_t)(&CM_CRC->DAT0)) +/** + * @} + */ + +/** + * @defgroup CRC_Calculate_Clock_Count CRC Calculate Clock Count + * @{ + */ +#define CRC_CALC_CLK_COUNT (10UL) +/** + * @} + */ + +#define CRC_RMU_TIMEOUT (100U) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Functions CRC Local Functions + * @{ + */ + +/** + * @brief Calculate the CRC value of a 8-bit data buffer. + * @param [in] au8Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au8Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData8(const uint8_t au8Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au8Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM8(u32DataAddr) = au8Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 16-bit data buffer. + * @param [in] au16Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in half-word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au16Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData16(const uint16_t au16Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au16Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM16(u32DataAddr) = au16Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Calculate the CRC value of a 32-bit data buffer. + * @param [in] au32Data Pointer to the input data buffer. + * @param [in] u32Len The length(counted in word) of the data to be calculated. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: The au32Data value is NULL or u32Len value is 0. + */ +static int32_t CRC_WriteData32(const uint32_t au32Data[], uint32_t u32Len) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + const uint32_t u32DataAddr = CRC_DATA_ADDR; + + if ((au32Data != NULL) && (u32Len != 0UL)) { + for (i = 0UL; i < u32Len; i++) { + RW_MEM32(u32DataAddr) = au32Data[i]; + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup CRC_Global_Functions CRC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_crc_init_t to default values. + * @param [out] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_StructInit(stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + pstcCrcInit->u32Protocol = CRC_CRC16; + pstcCrcInit->u32InitValue = CRC_INIT_VALUE_DEFAULT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize the CRC. + * @param [in] pstcCrcInit Pointer to a @ref stc_crc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCrcInit value is NULL. + */ +int32_t CRC_Init(const stc_crc_init_t *pstcCrcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCrcInit) { + DDL_ASSERT(IS_CRC_PROTOCOL(pstcCrcInit->u32Protocol)); + + MODIFY_REG32(CM_CRC->CR, CRC_CRC32, pstcCrcInit->u32Protocol); + + /* Set initial value */ + if (CRC_CRC16 == (pstcCrcInit->u32Protocol & CRC_CRC32)) { + WRITE_REG16(CM_CRC->RESLT, (uint16_t)pstcCrcInit->u32InitValue); + } else { + WRITE_REG32(CM_CRC->RESLT, pstcCrcInit->u32InitValue); + } + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief De-initialize the CRC. + * @param None + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first. + */ +int32_t CRC_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + /* Reset CRC */ + WRITE_REG32(bCM_RMU->FRST0_b.CRC, 0UL); + + /* Ensure reset procedure is completed */ + while (READ_REG32(bCM_RMU->FRST0_b.CRC) != 1UL) { + u8TimeOut++; + if (u8TimeOut > CRC_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Get status of the CRC operation result. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_GetResultStatus(void) +{ + uint32_t u32Status; + + u32Status = READ_REG32_BIT(CM_CRC->CR, CRC_CR_FLAG); + + return (u32Status > 0UL) ? SET : RESET; +} + +/** + * @brief Calculate the CRC16 value and start with the previously calculated CRC as initial value. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be calculated. + * @retval The CRC16 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint16_t CRC_CRC16_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint16_t u16CrcValue = 0U; + + if ((pvData != NULL) && (u32Len != 0UL)) { + DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth)); + + /* Write data */ + if (CRC_DATA_WIDTH_32BIT == u8DataWidth) { + (void)CRC_WriteData32((const uint32_t *)pvData, u32Len); + } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) { + (void)CRC_WriteData16((const uint16_t *)pvData, u32Len); + } else { + (void)CRC_WriteData8((const uint8_t *)pvData, u32Len); + } + + /* Get checksum */ + u16CrcValue = (uint16_t)READ_REG16(CM_CRC->RESLT); + } + + return u16CrcValue; +} + +/** + * @brief Calculate the CRC32 value and start with the previously calculated CRC as initial value. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be calculated. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be calculated. + * @retval The CRC32 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint32_t CRC_CRC32_AccumulateData(uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + DDL_ASSERT(IS_CRC_DATA_WIDTH(u8DataWidth)); + + /* Write data */ + if (CRC_DATA_WIDTH_32BIT == u8DataWidth) { + (void)CRC_WriteData32((const uint32_t *)pvData, u32Len); + } else if (CRC_DATA_WIDTH_16BIT == u8DataWidth) { + (void)CRC_WriteData16((const uint16_t *)pvData, u32Len); + } else { + (void)CRC_WriteData8((const uint8_t *)pvData, u32Len); + } + + /* Get checksum */ + u32CrcValue = READ_REG32(CM_CRC->RESLT); + } + + return u32CrcValue; +} + +/** + * @brief Calculate the CRC16 value and start with the specified initial value. + * @param [in] u16InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @retval The CRC16 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint16_t CRC_CRC16_Calculate(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint16_t u16CrcValue = 0U; + + if ((pvData != NULL) && (u32Len != 0UL)) { + /* Set initial value */ + WRITE_REG16(CM_CRC->RESLT, u16InitValue); + + u16CrcValue = CRC_CRC16_AccumulateData(u8DataWidth, pvData, u32Len); + } + + return u16CrcValue; +} + +/** + * @brief Calculate the CRC32 value and start with the specified initial value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the macros group @ref CRC_DATA_Bit_Width + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @retval The CRC32 value. + * @note The function fetch data in byte or half word or word depending on the data bit width(the parameter u8DataWidth). + */ +uint32_t CRC_CRC32_Calculate(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len) +{ + uint32_t u32CrcValue = 0UL; + + if ((pvData != NULL) && (u32Len != 0UL)) { + /* Set initial value */ + WRITE_REG32(CM_CRC->RESLT, u32InitValue); + + u32CrcValue = CRC_CRC32_AccumulateData(u8DataWidth, pvData, u32Len); + } + + return u32CrcValue; +} + +/** + * @brief Check the CRC16 calculating result with the expected value. + * @param [in] u16InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u16ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC16_CheckData(uint16_t u16InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint16_t u16ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus = RESET; + uint32_t u32Expect_Value = u16ExpectValue; + + if ((pvData != NULL) && (u32Len != 0UL)) { + (void)CRC_CRC16_Calculate(u16InitValue, u8DataWidth, pvData, u32Len); + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData16((uint16_t *)((void *)&u32Expect_Value), 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + } + + return enStatus; +} + +/** + * @brief Check the CRC32 calculating result with the expected value. + * @param [in] u32InitValue The CRC initialization value which is the valid bits same as + * the bits of CRC Protocol. + * @param [in] u8DataWidth Bit width of the data. + * This parameter can be one of the following values: + * @arg CRC_DATA_WIDTH_8BIT: 8 Bit + * @arg CRC_DATA_WIDTH_16BIT: 16 Bit + * @arg CRC_DATA_WIDTH_32BIT: 32 Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32Len The length(counted in byte) of the data to be calculated. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC32_CheckData(uint32_t u32InitValue, uint8_t u8DataWidth, const void *pvData, uint32_t u32Len, uint32_t u32ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus = RESET; + uint32_t u32Expect_Value = u32ExpectValue; + + if ((pvData != NULL) && (u32Len != 0UL)) { + (void)CRC_CRC32_Calculate(u32InitValue, u8DataWidth, pvData, u32Len); + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData32(&u32Expect_Value, 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + } + + return enStatus; +} + +/** + * @brief Get the CRC16 check result with the expected value. + * @param [in] u16ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC16_GetCheckResult(uint16_t u16ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus; + uint32_t u32Expect_Value = u16ExpectValue; + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData16((uint16_t *)((void *)&u32Expect_Value), 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + + return enStatus; +} + +/** + * @brief Get the CRC32 check result with the expected value. + * @param [in] u32ExpectValue The expected CRC value to be checked. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t CRC_CRC32_GetCheckResult(uint32_t u32ExpectValue) +{ + __IO uint32_t u32Count = CRC_CALC_CLK_COUNT; + en_flag_status_t enStatus; + uint32_t u32Expect_Value = u32ExpectValue; + + /* Writes the expected CRC value to be checked */ + (void)CRC_WriteData32(&u32Expect_Value, 1UL); + + /* Delay for waiting CRC result flag */ + while (u32Count-- != 0UL) { + __NOP(); + } + + enStatus = CRC_GetResultStatus(); + + return enStatus; +} + +/** + * @} + */ + +#endif /* LL_CRC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_ctc.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_ctc.c new file mode 100644 index 0000000000..60cb773397 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_ctc.c @@ -0,0 +1,524 @@ +/** + ******************************************************************************* + * @file hc32_ll_ctc.c + * @brief This file provides firmware functions to manage the Clock Trimming + * Controller(CTC). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_ctc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_CTC CTC + * @brief CTC Driver Library + * @{ + */ + +#if (LL_CTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CTC_Local_Macros CTC Local Macros + * @{ + */ + +/** + * @defgroup CTC_Check_Parameters_Validity CTC Check Parameters Validity + * @{ + */ +#define IS_CTC_REF_CLK_SRC(x) \ +( ((x) == CTC_REF_CLK_SRC_XTAL) || \ + ((x) == CTC_REF_CLK_SRC_XTAL32) || \ + ((x) == CTC_REF_CLK_SRC_CTCREF)) + +#define IS_CTC_REF_CLK_DIV(x) \ +( ((x) == CTC_REF_CLK_DIV2) || \ + ((x) == CTC_REF_CLK_DIV4) || \ + ((x) == CTC_REF_CLK_DIV8) || \ + ((x) == CTC_REF_CLK_DIV16) || \ + ((x) == CTC_REF_CLK_DIV64) || \ + ((x) == CTC_REF_CLK_DIV256) || \ + ((x) == CTC_REF_CLK_DIV1024) || \ + ((x) == CTC_REF_CLK_DIV4096)) + +#define IS_CTC_OFFSET_VALUE(x) ((x) <= 0xFFUL) + +#define IS_CTC_RELOAD_VALUE(x) ((x) <= 0xFFFFUL) + +#define IS_CTC_TRIM_VALUE(x) ((x) <= 0x3FUL) + +#define IS_CTC_TOLERANT_ERR(x) \ +( ((x) >= 0.0F) && \ + ((x) <= CTC_TOLERANT_ERR_MAX)) + +#define IS_CTC_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | CTC_FLAG_ALL) == CTC_FLAG_ALL)) + +#define IS_CTC_HRC_CLK_DIV(x) \ +( ((x) == CTC_HRC_CLK_DIV1) || \ + ((x) == CTC_HRC_CLK_DIV2) || \ + ((x) == CTC_HRC_CLK_DIV4) || \ + ((x) == CTC_HRC_CLK_DIV8) || \ + ((x) == CTC_HRC_CLK_DIV32) || \ + ((x) == CTC_HRC_CLK_DIV128) || \ + ((x) == CTC_HRC_CLK_DIV512) || \ + ((x) == CTC_HRC_CLK_DIV2048)) + +#define IS_CTC_CTCREF_EDGE(x) \ +( ((x) == CTC_CTCREF_RISING_RISING) || \ + ((x) == CTC_CTCREF_RISING_FALLING) || \ + ((x) == CTC_CTCREF_FALLING_RISING) || \ + ((x) == CTC_CTCREF_FALLING_FALLING)) +/** + * @} + */ + +/** + * @defgroup CTC_Tolerant_Error_Max CTC Tolerant Error Max + * @{ + */ +#define CTC_TOLERANT_ERR_MAX (1.0F) +/** + * @} + */ + +#define CTC_RMU_TIMEOUT (100UL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup CTC_Local_Functions CTC Local Functions + * @{ + */ + +/** + * @brief Get HRC clock frequency. + * @param None + * @retval HRC clock frequency. + */ +static uint32_t CTC_GetHrcClockFreq(void) +{ + return HRC_VALUE; +} + +/** + * @brief Get reference clock division. + * @param [in] u32Cr1RefPsc CTC CR1 REFPSC bits value. + * This parameter can be between Min_Data=0 and Max_Data=7 + * @retval Reference clock division. + */ +static uint32_t CTC_GetRefClockDiv(uint32_t u32Cr1RefPsc) +{ + uint32_t u32RefclkDiv; + + if (u32Cr1RefPsc < CTC_REF_CLK_DIV64) { + u32RefclkDiv = (2UL << u32Cr1RefPsc); + } else { + u32RefclkDiv = (64UL << (2UL * (u32Cr1RefPsc - CTC_REF_CLK_DIV64))); + } + + return u32RefclkDiv; +} + +/** + * @brief Get CTC HRC clock division. + * @param [in] u32Cr1HrcPsc CTC CR1 REFPSC bits value. + * This parameter can be between Min_Data=0 and Max_Data=7 + * @retval CTC HRC clock division. + */ +static uint32_t CTC_GetCtcHrcClockDiv(uint32_t u32Cr1HrcPsc) +{ + uint32_t u32CtcHrcDiv; + + if (u32Cr1HrcPsc < CTC_HRC_CLK_DIV32) { + u32CtcHrcDiv = (1UL << u32Cr1HrcPsc); + } else { + u32CtcHrcDiv = (32UL << (2UL * (u32Cr1HrcPsc - CTC_HRC_CLK_DIV32))); + } + + return u32CtcHrcDiv; +} +/** + * @} + */ + +/** + * @defgroup CTC_Global_Functions CTC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_ctc_ct_init_t to default values. + * @param [out] pstcCtcInit Pointer to a @ref stc_ctc_ct_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCtcInit value is NULL. + */ +int32_t CTC_CT_StructInit(stc_ctc_ct_init_t *pstcCtcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCtcInit) { + pstcCtcInit->u32HrcClockDiv = CTC_HRC_CLK_DIV1; + pstcCtcInit->u32RefClockFreq = 0UL; + pstcCtcInit->u32RefClockSrc = CTC_REF_CLK_SRC_CTCREF; + pstcCtcInit->u32RefClockDiv = CTC_REF_CLK_DIV8; + pstcCtcInit->f32TolerantErrRate = 0.0F; + pstcCtcInit->u8TrimValue = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize CTC continuous trim function. + * @param [in] pstcCtcInit Pointer to a @ref stc_ctc_ct_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_BUSY: CTC state is busy. + * - LL_ERR_INVD_PARAM: If one of following cases matches: + * - The pointer pstcCtcInit value is NULL. + * - Reference frequency is out of range. + * - Calculate reload & offset value out of range. + */ +int32_t CTC_CT_Init(const stc_ctc_ct_init_t *pstcCtcInit) +{ + float32_t f32OffsetValue; + uint32_t u32RegValue; + uint32_t u32ReloadValue; + uint32_t u32OffsetValue; + uint32_t u32RefClockDiv; + uint32_t u32CtcHrcFreq; + uint32_t u32Multiplier; + uint64_t u64InterClock; + int32_t i32Ret = LL_ERR_BUSY; + + /* Check CTC status */ + if (CTC_FLAG_BUSY != (READ_REG32_BIT(CM_CTC->STR, CTC_FLAG_BUSY))) { + if ((NULL == pstcCtcInit) || (0UL == pstcCtcInit->u32RefClockFreq)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CTC_REF_CLK_SRC(pstcCtcInit->u32RefClockSrc)); + DDL_ASSERT(IS_CTC_REF_CLK_DIV(pstcCtcInit->u32RefClockDiv)); + DDL_ASSERT(IS_CTC_TRIM_VALUE(pstcCtcInit->u8TrimValue)); + DDL_ASSERT(IS_CTC_TOLERANT_ERR(pstcCtcInit->f32TolerantErrRate)); + DDL_ASSERT(IS_CTC_HRC_CLK_DIV(pstcCtcInit->u32HrcClockDiv)); + + u32CtcHrcFreq = (CTC_GetHrcClockFreq() / CTC_GetCtcHrcClockDiv(pstcCtcInit->u32HrcClockDiv)); + + u32RefClockDiv = CTC_GetRefClockDiv(pstcCtcInit->u32RefClockDiv); + u64InterClock = ((uint64_t)u32CtcHrcFreq) * ((uint64_t)(u32RefClockDiv)); + u32Multiplier = (uint32_t)(u64InterClock / pstcCtcInit->u32RefClockFreq); + + /* Calculate offset value formula: OFSVAL = (Fhrc / (Fref * Fref_division)) * TA */ + f32OffsetValue = ((float32_t)u32Multiplier) * (pstcCtcInit->f32TolerantErrRate); + u32OffsetValue = (uint32_t)(f32OffsetValue); + + /* Calculate reload value formula: RLDVAL = (Fhrc / (Fref * Fref_division)) + OFSVAL */ + u32ReloadValue = u32Multiplier + u32OffsetValue; + + /* Check reload and offset value */ + if ((IS_CTC_OFFSET_VALUE(u32OffsetValue)) && (IS_CTC_RELOAD_VALUE(u32ReloadValue))) { + /* Set CR1 */ + u32RegValue = (pstcCtcInit->u32RefClockDiv | pstcCtcInit->u32RefClockSrc | \ + ((uint32_t)pstcCtcInit->u8TrimValue << CTC_CR1_TRMVAL_POS)); + u32RegValue |= pstcCtcInit->u32HrcClockDiv; + WRITE_REG32(CM_CTC->CR1, u32RegValue); + + /* Set CR2 */ + u32RegValue = ((u32ReloadValue << CTC_CR2_RLDVAL_POS) | u32OffsetValue); + WRITE_REG32(CM_CTC->CR2, u32RegValue); + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_ctc_st_init_t to default values. + * @param [out] pstcCtcInit Pointer to a @ref stc_ctc_st_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCtcInit value is NULL. + */ +int32_t CTC_ST_StructInit(stc_ctc_st_init_t *pstcCtcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcCtcInit) { + pstcCtcInit->u32HrcClockDiv = CTC_HRC_CLK_DIV1; + pstcCtcInit->f32CtcRefEdgeTime = 0.0F; + pstcCtcInit->f32TolerantErrRate = 0.0F; + pstcCtcInit->u32CtcRefEdge = CTC_CTCREF_RISING_RISING; + pstcCtcInit->u8TrimValue = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize CTC single trim function. + * @param [in] pstcCtcInit Pointer to a @ref stc_ctc_st_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_BUSY: CTC state is busy + * - LL_ERR_INVD_PARAM: If one of following cases matches: + * - pstcCtcInit is NULL. + * - Reference frequency is out of range. + * - Calculate reload & offset value out of range + */ +int32_t CTC_ST_Init(const stc_ctc_st_init_t *pstcCtcInit) +{ + float32_t f32OffsetValue; + uint32_t u32RegValue; + uint32_t u32ReloadValue; + uint32_t u32OffsetValue; + uint32_t u32CtcHrcFreq; + uint32_t u32Multiplier; + int32_t i32Ret = LL_ERR_BUSY; + + /* Check CTC status */ + if (CTC_FLAG_BUSY != (READ_REG32_BIT(CM_CTC->STR, CTC_FLAG_BUSY))) { + if (NULL == pstcCtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_CTC_HRC_CLK_DIV(pstcCtcInit->u32HrcClockDiv)); + DDL_ASSERT(IS_CTC_TOLERANT_ERR(pstcCtcInit->f32TolerantErrRate)); + DDL_ASSERT(IS_CTC_CTCREF_EDGE(pstcCtcInit->u32CtcRefEdge)); + DDL_ASSERT(IS_CTC_TRIM_VALUE(pstcCtcInit->u8TrimValue)); + + /* CTC trim HRC clock frequency */ + u32CtcHrcFreq = (CTC_GetHrcClockFreq() / CTC_GetCtcHrcClockDiv(pstcCtcInit->u32HrcClockDiv)); + + f32OffsetValue = ((float32_t)u32CtcHrcFreq * pstcCtcInit->f32CtcRefEdgeTime); + u32Multiplier = (uint32_t)(f32OffsetValue); + + /* Calculate offset value formula: OFSVAL = ( Fhrc x Ttrim ) x TA */ + f32OffsetValue = ((float32_t)u32Multiplier) * (pstcCtcInit->f32TolerantErrRate); + u32OffsetValue = (uint32_t)(f32OffsetValue); + + /* Calculate reload value formula: RLDVAL = ( Fhrc x Ttrim ) + OFSVAL */ + u32ReloadValue = u32Multiplier + u32OffsetValue; + + /* Check reload and offset value */ + if ((IS_CTC_OFFSET_VALUE(u32OffsetValue)) && (IS_CTC_RELOAD_VALUE(u32ReloadValue))) { + /* Set CR1 */ + u32RegValue = (CTC_CR1_REFCKS_0 | pstcCtcInit->u32HrcClockDiv | pstcCtcInit->u32CtcRefEdge | \ + ((uint32_t)pstcCtcInit->u8TrimValue << CTC_CR1_TRMVAL_POS)); + WRITE_REG32(CM_CTC->CR1, u32RegValue); + + /* Set CR2 */ + u32RegValue = ((u32ReloadValue << CTC_CR2_RLDVAL_POS) | u32OffsetValue); + WRITE_REG32(CM_CTC->CR2, u32RegValue); + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief De-Initialize CTC function. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success + * - LL_ERR_TIMEOUT: Reset time out + */ +int32_t CTC_DeInit(void) +{ + __IO uint32_t u32TimeOut = 0U; + int32_t i32Ret = LL_OK; + + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_CTC); + /* Ensure reset procedure is completed */ + while (RMU_FRST0_CTC != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_CTC)) { + u32TimeOut++; + if (u32TimeOut > CTC_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable CTC error interrupt function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void CTC_IntCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_CTC->CR1, CTC_CR1_ERRIE); + } else { + CLR_REG32_BIT(CM_CTC->CR1, CTC_CR1_ERRIE); + } +} + +/** + * @brief Get CTC flag status. + * @param [in] u32Flag CTC flag + * This parameter can be any composed value of the macros group @ref CTC_Flag + * @arg CTC_FLAG_TRIM_OK: Trimming OK flag + * @arg CTC_FLAG_TRIM_OVF: Trimming overflow flag + * @arg CTC_FLAG_TRIM_UDF: Trimming underflow flag + * @arg CTC_FLAG_BUSY: CTC busy flag + * @retval Returned value can be one of the following values: + */ +en_flag_status_t CTC_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_CTC_FLAG(u32Flag)); + + return ((0UL == READ_REG32_BIT(CM_CTC->STR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Set CTC trimming value. + * @param [in] u8TrimValue CTC trimming value + * This parameter can be Min_Data=0 && Max_Data=0x3F + * @retval None + */ +void CTC_SetTrimValue(uint8_t u8TrimValue) +{ + DDL_ASSERT(IS_CTC_TRIM_VALUE(u8TrimValue)); + + MODIFY_REG32(CM_CTC->CR1, CTC_CR1_TRMVAL, ((uint32_t)u8TrimValue << CTC_CR1_TRMVAL_POS)); +} + +/** + * @brief Get CTC trimming value. + * @param None + * @retval CTC trimming value(between Min_Data=0 and Max_Data=0x3F) + */ +uint8_t CTC_GetTrimValue(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_CTC->CR1, CTC_CR1_TRMVAL) >> CTC_CR1_TRMVAL_POS); +} + +/** + * @brief Set CTC reload value. + * @param [in] u16ReloadValue CTC reload value + * This parameter can be between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +void CTC_SetReloadValue(uint16_t u16ReloadValue) +{ + MODIFY_REG32(CM_CTC->CR2, CTC_CR2_RLDVAL, ((uint32_t)u16ReloadValue << CTC_CR2_RLDVAL_POS)); +} + +/** + * @brief Get CTC reload value. + * @param None + * @retval CTC reload value (between Min_Data=0 and Max_Data=0xFFFF) + */ +uint16_t CTC_GetReloadValue(void) +{ + return (uint16_t)(READ_REG32_BIT(CM_CTC->CR2, CTC_CR2_RLDVAL) >> CTC_CR2_RLDVAL_POS); +} + +/** + * @brief Set CTC offset value. + * @param [in] u8OffsetValue CTC offset value + * This parameter can be between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +void CTC_SetOffsetValue(uint8_t u8OffsetValue) +{ + MODIFY_REG32(CM_CTC->CR2, CTC_CR2_OFSVAL, ((uint32_t)u8OffsetValue << CTC_CR2_OFSVAL_POS)); +} + +/** + * @brief Get CTC offset value. + * @param None + * @retval CTC offset value (between Min_Data=0 and Max_Data=0xFF) + */ +uint8_t CTC_GetOffsetValue(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_CTC->CR2, CTC_CR2_OFSVAL) >> CTC_CR2_OFSVAL_POS); +} + +/** + * @brief Get CTC count value. + * @param None + * @retval CTC count value (between Min_Data=0 and Max_Data=0xFFFF) + */ +uint16_t CTC_GetCountValue(void) +{ + return READ_REG16(CM_CTC->CNT); +} + +/** + * @} + */ + +#endif /* LL_CTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dac.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dac.c new file mode 100644 index 0000000000..fb5d1df776 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dac.c @@ -0,0 +1,560 @@ +/** + ******************************************************************************* + * @file hc32_ll_dac.c + * @brief This file provides firmware functions to manage the Digital-to-Analog + * Converter(DAC). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Refine data validation + 2023-09-30 CDT Add assert for set DAC source and modify IS_AMP_CTRL_ALLOWED() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dac.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DAC DAC + * @brief DAC Driver Library + * @{ + */ + +#if (LL_DAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DAC_Local_Macros DAC Local Macros + * @{ + */ +#define DAC_RESOLUTION (DAC_RESOLUTION_12BIT) +#define DAC_DATA_REG_WIDTH (16U) +#define DAC_DATA_RIGHT_ALIGN_MASK ((2U << DAC_RESOLUTION) - 1U) +#define DAC_DATA_LEFT_ALIGN_MASK (DAC_DATA_RIGHT_ALIGN_MASK << (DAC_DATA_REG_WIDTH - DAC_RESOLUTION)) + +#define DAC_RMU_TIMEOUT (100U) + +/** + * @defgroup DAC_Check_Parameters_Validity DAC Check Parameters Validity + * @{ + */ +#define IS_VALID_UNIT(x) ((x) == CM_DAC) + +#define IS_VALID_CH(x) (((x) == DAC_CH1) || ((x) == DAC_CH2)) + +#define IS_VALID_DATA_ALIGN(x) (((x) == DAC_DATA_ALIGN_LEFT) || ((x) == DAC_DATA_ALIGN_RIGHT)) + +#define IS_VALID_DATA_SRC(x) (((x) == DAC_DATA_SRC_DATAREG) || ((x) == DAC_DATA_SRC_DCU)) + +#define IS_VALID_ADCPRIO_CONFIG(x) ((0U != (x)) && (DAC_ADP_SEL_ALL == ((x) | DAC_ADP_SEL_ALL))) + +#define IS_VALID_RIGHT_ALIGNED_DATA(data) (((data) & ~DAC_DATA_RIGHT_ALIGN_MASK) == 0U) +#define IS_VALID_LEFT_ALIGNED_DATA(data) (((data) & ~DAC_DATA_LEFT_ALIGN_MASK) == 0U) + +#define IS_ADP_CTRL_ALLOWED(x,src1,src2) (((x) == DISABLE) || \ + (((src1) == (DAC_DATA_SRC_DATAREG)) && ((src2) == (DAC_DATA_SRC_DATAREG)))) + +#define IS_AMP_CTRL_ALLOWED(x,Ch) \ +( (READ_REG16_BIT(DACx->DACR, DAC_DACR_EXTDSL1 << (Ch)) == 0U) || \ + ((x) == DISABLE)) + +#define IS_SRC_SET_ALLOWED(Ch, src) \ +( (READ_REG16_BIT(DACx->DACR, DAC_DACR_DAAMP1 << (Ch)) == 0U) || ((src) == (DAC_DATA_SRC_DATAREG))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup DAC_Global_Functions DAC Global Functions + * @{ + */ + +/** + * @brief Set DAC data source for specified channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify the DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] u16Src Specify the data source. + * This parameter can be a value of @ref DAC_DATA_SRC + * - DAC_DATA_SRC_DATAREG: convert source is from data register + * - DAC_DATA_SRC_DCU: convert source is from DCU + * @retval None + */ +void DAC_SetDataSrc(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_VALID_DATA_SRC(u16Src)); + DDL_ASSERT(IS_SRC_SET_ALLOWED(u16Ch, u16Src)); + + MODIFY_REG16(DACx->DACR, DAC_DACR_EXTDSL1 << u16Ch, u16Src << u16Ch); +} + +/** + * @brief DAC data register's data alignment pattern configuration + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Align Specify the data alignment. + * This parameter can be a value of @ref DAC_DATAREG_ALIGN_PATTERN + * - DAC_DATA_ALIGN_LEFT: left alignment + * - DAC_DATA_ALIGN_RIGHT: right alignment + * @retval None + */ +void DAC_DataRegAlignConfig(CM_DAC_TypeDef *DACx, uint16_t u16Align) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_DATA_ALIGN(u16Align)); + + MODIFY_REG16(DACx->DACR, DAC_DACR_DPSEL, u16Align); +} + +/** + * @brief DAC output function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DAC_OutputCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState) +{ + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u16Cmd = (uint16_t)(1UL << (DAC_DAOCR_DAODIS1_POS + u16Ch)); + + if (ENABLE == enNewState) { + CLR_REG16_BIT(DACx->DAOCR, u16Cmd); + } else { + SET_REG16_BIT(DACx->DAOCR, u16Cmd); + } +} + +/** + * @brief DAC AMP function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DAC_AMPCmd(CM_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState) +{ + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_AMP_CTRL_ALLOWED(enNewState, u16Ch)); + u16Cmd = (uint16_t)(1UL << (DAC_DACR_DAAMP1_POS + u16Ch)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(DACx->DACR, u16Cmd); + } else { + CLR_REG16_BIT(DACx->DACR, u16Cmd); + } +} + +/** + * @brief DAC ADC priority function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note please make sure ADC is in stoped status before calling DAC_ADCPrioCmd + */ +void DAC_ADCPrioCmd(CM_DAC_TypeDef *DACx, en_functional_state_t enNewState) +{ +#ifdef __DEBUG + uint16_t u16DataSrc1; + uint16_t u16DataSrc2; +#endif + DDL_ASSERT(IS_VALID_UNIT(DACx)); +#ifdef __DEBUG + u16DataSrc1 = READ_REG16_BIT(DACx->DACR, DAC_DACR_EXTDSL1); + u16DataSrc2 = READ_REG16_BIT(DACx->DACR, DAC_DACR_EXTDSL2); + DDL_ASSERT(IS_ADP_CTRL_ALLOWED(enNewState, u16DataSrc1, u16DataSrc2)); +#endif + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN); + } else { + CLR_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN); + } +} + +/** + * @brief Enable or Disable the ADC priority for the selected ADCx + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16ADCxPrio ADCx priority to be enabled or disabled. + * This parameter can be one or any combination of the following values: + * @arg DAC_ADP_SEL_ADC1 + * @arg DAC_ADP_SEL_ADC2 + * @arg DAC_ADP_SEL_ADC3 + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note please make sure ADC is in stoped status before calling DAC_ADCPrioConfig + */ +void DAC_ADCPrioConfig(CM_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_ADCPRIO_CONFIG(u16ADCxPrio)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(DACx->DAADPCR, u16ADCxPrio); + } else { + CLR_REG16_BIT(DACx->DAADPCR, u16ADCxPrio); + } +} + +/** + * @brief Start the specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_MD: cannot start single channel when \n + * this channel have already been started by \n + * @ref DAC_StartDualCh + */ +int32_t DAC_Start(CM_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + int32_t i32Ret = LL_OK; + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if ((DACx->DACR & DAC_DACR_DAE) != 0U) { + i32Ret = LL_ERR_INVD_MD; + } else { + u16Cmd = (uint16_t)(1UL << (DAC_DACR_DA1E_POS + u16Ch)); + SET_REG16_BIT(DACx->DACR, u16Cmd); + } + + return i32Ret; +} + +/** + * @brief Stop the specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_MD: cannot stop single channel when \n + * this channel is started by \n + * @ref DAC_StartDualCh + */ +int32_t DAC_Stop(CM_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + int32_t i32Ret = LL_OK; + uint16_t u16Cmd; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if ((DACx->DACR & DAC_DACR_DAE) != 0U) { + i32Ret = LL_ERR_INVD_MD; + } else { + u16Cmd = (uint16_t)(1UL << (DAC_DACR_DA1E_POS + u16Ch)); + CLR_REG16_BIT(DACx->DACR, u16Cmd); + } + + return i32Ret; +} + +/** + * @brief Start DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @retval None + */ +void DAC_StartDualCh(CM_DAC_TypeDef *DACx) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + SET_REG16_BIT(DACx->DACR, DAC_DACR_DAE); +} + +/** + * @brief Stop DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @retval None + */ +void DAC_StopDualCh(CM_DAC_TypeDef *DACx) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + CLR_REG16_BIT(DACx->DACR, DAC_DACR_DAE); +} + +/** + * @brief Set the specified data to the data holding register of specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] u16Data Data to be loaded into data holding register of specified channel + * @retval None + */ +void DAC_SetChData(CM_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Data) +{ + __IO uint16_t *u16DADRx; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if (READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_LEFT) { + DDL_ASSERT(IS_VALID_LEFT_ALIGNED_DATA(u16Data)); + } else { + DDL_ASSERT(IS_VALID_RIGHT_ALIGNED_DATA(u16Data)); + } + + u16DADRx = (uint16_t *)((uint32_t) & (DACx->DADR1) + u16Ch * 2UL); + WRITE_REG16(*u16DADRx, u16Data); +} + +/** + * @brief Set the specified data to the data holding register of DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param u16Data1: Data to be loaded into data holding register of channel 1 + * @param u16Data2: Data to be loaded into data holding register of channel 2 + * @retval None + */ +void DAC_SetDualChData(CM_DAC_TypeDef *DACx, uint16_t u16Data1, uint16_t u16Data2) +{ + uint32_t u32Data; + __IO uint32_t *u32DADRx; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + if (READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_LEFT) { + DDL_ASSERT(IS_VALID_LEFT_ALIGNED_DATA(u16Data1)); + DDL_ASSERT(IS_VALID_LEFT_ALIGNED_DATA(u16Data2)); + } else { + DDL_ASSERT(IS_VALID_RIGHT_ALIGNED_DATA(u16Data1)); + DDL_ASSERT(IS_VALID_RIGHT_ALIGNED_DATA(u16Data2)); + } + + u32Data = ((uint32_t)u16Data2 << 16U) | u16Data1; + u32DADRx = (__IO uint32_t *)(uint32_t)(&DACx->DADR1); + WRITE_REG32(*u32DADRx, u32Data); +} + +/** + * @brief Get convert status of specified channel in ADC priority mode + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @retval int32_t: + * - LL_ERR_INVD_MD: Could not get convert status when adc priority is not enabled + * - LL_OK: Data convert completed + * - LL_ERR_BUSY: Data convert is ongoing + */ +int32_t DAC_GetChConvertState(const CM_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + int32_t i32Ret = LL_ERR_INVD_MD; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if (0U != READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN)) { + i32Ret = LL_ERR_BUSY; + + if (READ_REG16_BIT(DACx->DAADPCR, (DAC_DAADPCR_DA1SF << u16Ch)) == 0U) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Fills each pstcDacInit member with its default value + * @param [in] pstcDacInit pointer to a stc_dac_init_t structure which will + * be initialized. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcDacInit is NULL + */ +int32_t DAC_StructInit(stc_dac_init_t *pstcDacInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcDacInit != NULL) { + pstcDacInit->u16Src = DAC_DATA_SRC_DATAREG; + pstcDacInit->enOutput = ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize the DAC peripheral according to the specified parameters + * in the stc_dac_init_t + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be a value of the following: + * @arg DAC_CH1 + * @arg DAC_CH2 + * @param [in] pstcDacInit pointer to a stc_dac_init_t structure that contains + * the configuration information for the specified DAC channel. + * @retval int32_t: + * - LL_OK: Initialize successfully + * - LL_ERR_INVD_PARAM: pstcDacInit is NULL + */ +int32_t DAC_Init(CM_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcDacInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcDacInit != NULL) { + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcDacInit->enOutput)); + DDL_ASSERT(IS_VALID_DATA_SRC(pstcDacInit->u16Src)); + DAC_SetDataSrc(DACx, u16Ch, pstcDacInit->u16Src); + DAC_OutputCmd(DACx, u16Ch, pstcDacInit->enOutput); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be a value of the following: + * @arg CM_DAC or CM_DACx + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @retval None + */ +int32_t DAC_DeInit(CM_DAC_TypeDef *DACx) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + /* Reset DAC */ + CLR_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_DAC); + /* Ensure reset procedure is completed */ + while (RMU_FRST3_DAC != READ_REG32_BIT(CM_RMU->FRST3, RMU_FRST3_DAC)) { + u8TimeOut++; + if (u8TimeOut > DAC_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_DAC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dbgc.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dbgc.c new file mode 100644 index 0000000000..57a5991f65 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dbgc.c @@ -0,0 +1,176 @@ +/** + ******************************************************************************* + * @file hc32_ll_dbgc.c + * @brief This file provides firmware functions to manage the DBGC. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Remove API DBGC_GetChipID()A + Add assert to DBGC_PeriphCmd & DBGC_Periph2Cmd + Add assert IS_DGBC_TRACE_MD and add API DBGC_TraceIoCmd,DBGC_TraceModeConfig + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dbgc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DBGC DBGC + * @brief DBGC Driver Library + * @{ + */ + +#if (LL_DBGC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup DBGC_Local_Macros DBGC Local Macros + * @{ + */ + +/** + * @defgroup DBGC_Check_Parameters_Validity DBGC Check Parameters Validity + * @{ + */ +#define IS_SECURITY_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | DBGC_SECURITY_ALL) == DBGC_SECURITY_ALL)) + +/* Parameter valid check for debug trace mode */ +#define IS_DGBC_TRACE_MD(x) \ +( ((x) == DBGC_TRACE_ASYNC) || \ + ((x) == DBGC_TRACE_SYNC_1BIT) || \ + ((x) == DBGC_TRACE_SYNC_2BIT) || \ + ((x) == DBGC_TRACE_SYNC_4BIT)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DBGC_Global_Functions DBGC Global Functions + * @{ + */ + +/** + * @brief Whether to stop the peripheral while mcu core stop. + * @param [in] u32Periph Specifies the peripheral. @ref DBGC_Periph_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DBGC_PeriphCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_DBGC->MCUSTPCTL, u32Periph); + } else { + SET_REG32_BIT(CM_DBGC->MCUSTPCTL, u32Periph); + } +} + +/** + * @brief Whether to stop the peripheral2 while mcu core stop. + * @param [in] u32Periph Specifies the peripheral. @ref DBGC_Periph2_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DBGC_Periph2Cmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_DBGC->MCUSTPCTL2, u32Periph); + } else { + SET_REG32_BIT(CM_DBGC->MCUSTPCTL2, u32Periph); + } +} + +/** + * @brief Enable or disable the trace pin output. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DBGC_TraceIoCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEIOEN); + } else { + CLR_REG32_BIT(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEIOEN); + } +} + +/** + * @brief Config trace mode. + * @param [in] u32TraceMode Specifies the trace mode. @ref DBGC_Trace_Mode + * @retval None + */ +void DBGC_TraceModeConfig(uint32_t u32TraceMode) +{ + DDL_ASSERT(IS_DGBC_TRACE_MD(u32TraceMode)); + + MODIFY_REG32(CM_DBGC->MCUTRACECTL, DBGC_MCUTRACECTL_TRACEMODE, u32TraceMode); +} + +/** + * @} + */ + +#endif /* LL_DBGC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c new file mode 100644 index 0000000000..ae27bc9b73 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dcu.c @@ -0,0 +1,607 @@ +/** + ******************************************************************************* + * @file hc32_ll_dcu.c + * @brief This file provides firmware functions to manage the DCU(Data Computing + * Unit). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + Modify function DCU_IntCmd() for misra + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dcu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DCU DCU + * @brief DCU Driver Library + * @{ + */ + +#if (LL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Local_Macros DCU Local Macros + * @{ + */ + +#define DCU_RMU_TIMEOUT (100U) + +/** + * @defgroup DCU_Check_Parameters_Validity DCU Check Parameters Validity + * @{ + */ +#define IS_DCU_WAVE_FUNC_UNIT(x) \ +( ((x) == CM_DCU1) || \ + ((x) == CM_DCU2) || \ + ((x) == CM_DCU3) || \ + ((x) == CM_DCU4)) + +#define IS_DCU_UNIT(x) (IS_DCU_WAVE_FUNC_UNIT(x)) + +#define IS_DCU_BASE_FUNC_UNIT_MD(x) \ +( ((x) == DCU_MD_CMP) || \ + ((x) == DCU_MD_ADD) || \ + ((x) == DCU_MD_SUB) || \ + ((x) == DCU_MD_HW_ADD) || \ + ((x) == DCU_MD_HW_SUB) || \ + ((x) == DCU_MD_INVD)) + +#define IS_DCU_WAVE_FUNC_UNIT_MD(x) \ +( IS_DCU_BASE_FUNC_UNIT_MD(x) || \ + ((x) == DCU_MD_TRIANGLE_WAVE) || \ + ((x) == DCU_MD_SAWTOOTH_WAVE_DEC) || \ + ((x) == DCU_MD_SAWTOOTH_WAVE_INC)) + +#define IS_DCU_BASE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_BASE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_WAVE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_WAVE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_CMP_COND(x) \ +( ((x) == DCU_CMP_TRIG_DATA0) || \ + ((x) == DCU_CMP_TRIG_DATA0_DATA1_DATA2)) + +#define IS_DCU_DATA_WIDTH(x) \ +( ((x) == DCU_DATA_WIDTH_8BIT) || \ + ((x) == DCU_DATA_WIDTH_16BIT) || \ + ((x) == DCU_DATA_WIDTH_32BIT)) + +#define IS_DCU_INT_CATEGORY(x) \ +( ((x) == DCU_CATEGORY_OP) || \ + ((x) == DCU_CATEGORY_CMP_WIN) || \ + ((x) == DCU_CATEGORY_CMP_NON_WIN) || \ + ((x) == DCU_CATEGORY_WAVE)) + +#define IS_DCU_INT_OP(x) ((x) == DCU_INT_OP_CARRY) + +#define IS_DCU_INT_CMP_WIN(x) \ +( ((x) == DCU_INT_CMP_WIN_INSIDE) || \ + ((x) == DCU_INT_CMP_WIN_OUTSIDE)) + +#define IS_DCU_INT_CMP_NON_WIN(x) \ +( ((x) != 0UL) || \ + (((x) | DCU_INT_CMP_NON_WIN_ALL) == DCU_INT_CMP_NON_WIN_ALL)) + +#define IS_DCU_INT_WAVE_MD(x) \ +( ((x) != 0UL) && \ + (((x) | DCU_INT_WAVE_MD_ALL) == DCU_INT_WAVE_MD_ALL)) + +#define IS_DCU_DATA_REG(x) \ +( ((x) == DCU_DATA0_IDX) || \ + ((x) == DCU_DATA1_IDX) || \ + ((x) == DCU_DATA2_IDX)) + +#define IS_DCU_WAVE_UPPER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_LOWER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_STEP(x) ((x) <= 0xFFFUL) +/** + * @} + */ + +/** + * @defgroup DCU_Flag_Mask DCU Flag Mask + * @{ + */ +#define DCU_BASE_FUNC_UNIT_FLAG_MASK (0x0E7FUL) +#define DCU_WAVE_FUNC_UNIT_FLAG_MASK (DCU_BASE_FUNC_UNIT_FLAG_MASK | 0x0E00UL) +/** + * @} + */ + +/** + * @defgroup DCU_DATA1_Limit_Position DCU_DATA1 Limit Position + * @{ + */ +#define DCU_DATA1_LOWER_LIMIT_POS (0UL) +#define DCU_DATA1_UPPER_LIMIT_POS (16UL) +/** + * @} + */ + +/** + * @defgroup DCU_Register_Address DCU Register Address + * @{ + */ +#define DCU_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define DCU_DATA_REG_ADDR(_UNITx_, _IDX_) (DCU_REG_ADDR((_UNITx_)->DATA0) + ((_IDX_) << 2UL)) + +#define DCU_DATA_REG8(_UNITx_, _IDX_) (*(__IO uint8_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG16(_UNITx_, _IDX_) (*(__IO uint16_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +#define DCU_DATA_REG32(_UNITx_, _IDX_) (*(__IO uint32_t *)DCU_DATA_REG_ADDR(_UNITx_, _IDX_)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Functions DCU Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_dcu_init_t to default values. + * @param [out] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_StructInit(stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + pstcDcuInit->u32Mode = DCU_MD_INVD; + pstcDcuInit->u32DataWidth = DCU_DATA_WIDTH_8BIT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] pstcDcuInit Pointer to a @ref stc_dcu_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcDcuInit value is NULL. + */ +int32_t DCU_Init(CM_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcDcuInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDcuInit) { + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_MD(pstcDcuInit->u32Mode)); + DDL_ASSERT(IS_DCU_DATA_WIDTH(pstcDcuInit->u32DataWidth)); + + /* Set register: CTL */ + WRITE_REG32(DCUx->CTL, (pstcDcuInit->u32Mode | pstcDcuInit->u32DataWidth)); + + /* Disable interrupt */ + WRITE_REG32(DCUx->INTEVTSEL, 0x00000000UL); + + /* Clear Flag */ + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @retval int32_t: + * - LL_OK: De-Initialize success. + * - LL_ERR_TIMEOUT: Timeout. + */ +int32_t DCU_DeInit(CM_DCU_TypeDef *DCUx) +{ + int32_t i32Ret = LL_OK; + uint32_t u32UnitShift; + uint32_t u32UnitBase; + __IO uint8_t u8TimeOut = 0U; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + /* Check FRST register protect */ + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + /* Reset */ + u32UnitBase = (uint32_t)DCUx; + u32UnitShift = (u32UnitBase - CM_DCU1_BASE) / (CM_DCU2_BASE - CM_DCU1_BASE); + CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_DCU1 << u32UnitShift); + /* Ensure reset procedure is completed */ + while (0UL == READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_DCU1 << u32UnitShift)) { + u8TimeOut++; + if (u8TimeOut > DCU_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] pstcWaveConfig Pointer to a @ref stc_dcu_wave_config_t structure (DCU wave function configuration data structure). + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcWaveConfig value is NULL. + */ +int32_t DCU_WaveConfig(CM_DCU_TypeDef *DCUx, const stc_dcu_wave_config_t *pstcWaveConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcWaveConfig) { + DDL_ASSERT(IS_DCU_WAVE_FUNC_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_WAVE_LOWER_LIMIT(pstcWaveConfig->u32LowerLimit)); + DDL_ASSERT(IS_DCU_WAVE_UPPER_LIMIT(pstcWaveConfig->u32UpperLimit)); + DDL_ASSERT(IS_DCU_WAVE_STEP(pstcWaveConfig->u32Step)); + + WRITE_REG32(DCUx->DATA0, 0x00000000UL); + WRITE_REG32(DCUx->DATA1, ((pstcWaveConfig->u32LowerLimit << DCU_DATA1_LOWER_LIMIT_POS) | \ + (pstcWaveConfig->u32UpperLimit << DCU_DATA1_UPPER_LIMIT_POS))); + WRITE_REG32(DCUx->DATA2, pstcWaveConfig->u32Step); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set DCU operation mode. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Mode DCU mode + * This parameter can be one of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_SetMode(CM_DCU_TypeDef *DCUx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_MD(u32Mode)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_MODE, u32Mode); +} + +/** + * @brief Set DCU data size. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataWidth DCU data width + * This parameter can be one of the macros group @ref DCU_Data_Width + * @arg DCU_DATA_WIDTH_8BIT: DCU data size 8 bit + * @arg DCU_DATA_WIDTH_16BIT: DCU data size 16 bit + * @arg DCU_DATA_WIDTH_32BIT: DCU data size 32 bit + * @retval None + */ +void DCU_SetDataWidth(CM_DCU_TypeDef *DCUx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_DATASIZE, u32DataWidth); +} + +/** + * @brief Set DCU compare trigger condition. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Cond DCU compare trigger condition + * This parameter can be one of the macros group @ref DCU_Compare_Trigger_Condition + * @arg DCU_CMP_TRIG_DATA0: DCU compare triggered by DATA0. + * @arg DCU_CMP_TRIG_DATA0_DATA1_DATA2: DCU compare triggered by DATA0 or DATA1 or DATA2. + * @retval None + */ +void DCU_SetCompareCond(CM_DCU_TypeDef *DCUx, uint32_t u32Cond) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_CMP_COND(u32Cond)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_COMPTRG, u32Cond); +} + +/** + * @brief Get DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DCU_GetStatus(const CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_FLAG(u32Flag)); + + return (0UL == READ_REG32_BIT(DCUx->FLAG, u32Flag)) ? RESET : SET; +} + +/** + * @brief Clear DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be any composed value of the macros group @ref DCU_Mode. + * @retval None + */ +void DCU_ClearStatus(CM_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_FLAG(u32Flag)); + + WRITE_REG32(DCUx->FLAGCLR, u32Flag); +} + +/** + * @brief Enable or disable DCU interrupt function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_GlobalIntCmd(CM_DCU_TypeDef *DCUx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } else { + CLR_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } +} + +/** + * @brief Enable/disable DCU the specified interrupt source. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32IntCategory DCU interrupt category + * This parameter can be one of the macros group @ref DCU_Category. + * @param [in] u32IntType DCU interrupt type + * This parameter can be one of the macros group @ref DCU_Interrupt_Type. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DCU_IntCmd(CM_DCU_TypeDef *DCUx, uint32_t u32IntCategory, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_CATEGORY(u32IntCategory)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DCU_CATEGORY_OP == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_OP(u32IntType)); + u32Type = (u32IntType & DCU_INT_OP_CARRY); + } else if (DCU_CATEGORY_CMP_WIN == u32IntCategory) { + DDL_ASSERT(IS_DCU_INT_CMP_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_WIN_ALL); + } else if (DCU_CATEGORY_WAVE == u32IntCategory) { + DDL_ASSERT(IS_DCU_WAVE_FUNC_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_WAVE_MD(u32IntType)); + u32Type = (u32IntType & DCU_INT_WAVE_MD_ALL); + } else { + DDL_ASSERT(IS_DCU_INT_CMP_NON_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_NON_WIN_ALL); + } + + if (ENABLE == enNewState) { + SET_REG32_BIT(DCUx->INTEVTSEL, u32Type); + } else { + CLR_REG32_BIT(DCUx->INTEVTSEL, u32Type); + } +} + +/** + * @brief Read DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for byte + */ +uint8_t DCU_ReadData8(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG8(DCU_DATA_REG8(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u8Data The data to write. + * @retval None + */ +void DCU_WriteData8(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint8_t u8Data) +{ + __IO uint8_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG8(DCUx, u32DataIndex); + WRITE_REG8(*DATA, u8Data); +} + +/** + * @brief Read DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for half-word + */ +uint16_t DCU_ReadData16(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG16(DCU_DATA_REG16(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u16Data The data to write. + * @retval None + */ +void DCU_WriteData16(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint16_t u16Data) +{ + __IO uint16_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG16(DCUx, u32DataIndex); + WRITE_REG16(*DATA, u16Data); +} + +/** + * @brief Read DCU register DATA for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for word + */ +uint32_t DCU_ReadData32(const CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + return READ_REG32(DCU_DATA_REG32(DCUx, u32DataIndex)); +} + +/** + * @brief Write DCU register DATA0 for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg CM_DCU or CM_DCUx: DCU instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the macros group @ref DCU_Data_Register_Index + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u32Data The data to write. + * @retval None + */ +void DCU_WriteData32(CM_DCU_TypeDef *DCUx, uint32_t u32DataIndex, uint32_t u32Data) +{ + __IO uint32_t *DATA; + + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = &DCU_DATA_REG32(DCUx, u32DataIndex); + WRITE_REG32(*DATA, u32Data); +} + +/** + * @} + */ + +#endif /* LL_DCU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c new file mode 100644 index 0000000000..7dc2e195d3 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_dma.c @@ -0,0 +1,1355 @@ +/** + ******************************************************************************* + * @file hc32_ll_dma.c + * @brief This file provides firmware functions to manage the Direct Memory + * Access (DMA). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Add API DMA_SetDataWidth() + Delete API DMA_AHB_HProtPrivilegeCmd() + Optimize set blocksize & repeat count process + 2023-12-15 CDT Add DMA Repeat size assert + Modify API input param type:u16->u32 + Use macros replace immediate data, modify IS_DMA_NON_SEQ_TRANS_CNT + Add API DMA_ReconfigNonSeqStructInit() & DMA_ReconfigNonSeqInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_dma.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_DMA DMA + * @brief Direct Memory Access Driver Library + * @{ + */ + +#if (LL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Local_Macros DMA Local Macros + * @{ + */ +#define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) + +#define DMA_RMU_TIMEOUT (100U) + +/** + * @defgroup DMA_Check_Parameters_Validity DMA Check Parameters Validity + * @{ + */ +/* Parameter valid check for DMA unit. */ +#define IS_DMA_UNIT(x) \ +( ((x) == CM_DMA1) || \ + ((x) == CM_DMA2)) + +/* Parameter valid check for DMA channel. */ +#define IS_DMA_CH(x) ((x) <= DMA_CH5) + +/* Parameter valid check for DMA multiplex channel. */ +#define IS_DMA_MX_CH(x) \ +( ((x) != 0x00UL) && \ + (((x) | DMA_MX_CH_ALL) == DMA_MX_CH_ALL)) + +/* Parameter valid check for DMA block size. */ +#define IS_DMA_BLOCK_SIZE(x) ((x) <= 1024UL) + +/* Parameter valid check for DMA repeat block size. */ +#define IS_DMA_REPEAT_SIZE(x) ((x) <= 1024UL) +#define IS_DMA_RC_REPEAT_SIZE(x) (((x) > 0U) && ((x) < 1024U)) + +/* Parameter valid check for DMA non-sequence transfer count. */ +#define IS_DMA_NON_SEQ_TRANS_CNT(x) ((x) <= 4096U) +#define IS_DMA_RC_NON_SEQ_TRANS_CNT(x) (((x) > 0U) && ((x) < 4096U)) + +/* Parameter valid check for DMA non-sequence offset. */ +#define IS_DMA_NON_SEQ_OFFSET(x) ((x) <= DMA_SNSEQCTL_SOFFSET) +#define IS_DMA_RC_NON_SEQ_DIST(x) ((x) <= DMA_SNSEQCTLB_SNSDIST) + +/* Parameter valid check for DMA LLP function. */ +#define IS_DMA_LLP_EN(x) \ +( ((x) == DMA_LLP_ENABLE) || \ + ((x) == DMA_LLP_DISABLE)) + +/* Parameter valid check for DMA linked-list-pointer mode. */ +#define IS_DMA_LLP_MD(x) \ +( ((x) == DMA_LLP_RUN) || \ + ((x) == DMA_LLP_WAIT)) + +/* Parameter valid check for address alignment of DMA linked-list-pointer descriptor */ +#define IS_DMA_LLP_ADDR_ALIGN(x) IS_ADDR_ALIGN_WORD(x) + +/* Parameter valid check for DMA error flag. */ +#define IS_DMA_ERR_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_ERR_MASK) == DMA_FLAG_ERR_MASK)) + +/* Parameter valid check for DMA transfer flag. */ +#define IS_DMA_TRANS_FLAG(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_FLAG_TRANS_MASK) == DMA_FLAG_TRANS_MASK)) + +/* Parameter valid check for DMA error interrupt. */ +#define IS_DMA_ERR_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_ERR_MASK) == DMA_INT_ERR_MASK)) + +/* Parameter valid check for DMA transfer interrupt. */ +#define IS_DMA_TRANS_INT(x) \ +( ((x)!= 0x00000000UL) && \ + (((x)| DMA_INT_TRANS_MASK) == DMA_INT_TRANS_MASK)) + +/* Parameter valid check for DMA request status. */ +#define IS_DMA_REQ_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_REQ_MASK) == DMA_STAT_REQ_MASK)) + +/* Parameter valid check for DMA transfer status. */ +#define IS_DMA_TRANS_STAT(x) \ +( ((x) != 0x00000000UL) && \ + (((x) | DMA_STAT_TRANS_MASK) == DMA_STAT_TRANS_MASK)) + +/* Parameter valid check for DMA transfer data width. */ +#define IS_DMA_DATA_WIDTH(x) \ +( ((x) == DMA_DATAWIDTH_8BIT) || \ + ((x) == DMA_DATAWIDTH_16BIT) || \ + ((x) == DMA_DATAWIDTH_32BIT)) + +/* Parameter valid check for DMA source address mode. */ +#define IS_DMA_SADDR_MD(x) \ +( ((x) == DMA_SRC_ADDR_FIX) || \ + ((x) == DMA_SRC_ADDR_INC) || \ + ((x) == DMA_SRC_ADDR_DEC)) + +/* Parameter valid check for DMA destination address mode. */ +#define IS_DMA_DADDR_MD(x) \ +( ((x) == DMA_DEST_ADDR_FIX) || \ + ((x) == DMA_DEST_ADDR_INC) || \ + ((x) == DMA_DEST_ADDR_DEC)) + +/* Parameter valid check for DMA repeat mode. */ +#define IS_DMA_RPT_MD(x) \ +( ((x) == DMA_RPT_NONE) || \ + ((x) == DMA_RPT_SRC) || \ + ((x) == DMA_RPT_DEST) || \ + ((x) == DMA_RPT_BOTH)) + +/* Parameter valid check for DMA non_sequence mode. */ +#define IS_DMA_NON_SEQ_MD(x) \ +( ((x) == DMA_NON_SEQ_NONE) || \ + ((x) == DMA_NON_SEQ_SRC) || \ + ((x) == DMA_NON_SEQ_DEST) || \ + ((x) == DMA_NON_SEQ_BOTH)) + +/* Parameter valid check for DMA global interrupt function. */ +#define IS_DMA_INT_FUNC(x) \ +( ((x) == DMA_INT_ENABLE) || \ + ((x) == DMA_INT_DISABLE)) + +/* Parameter valid check for DMA reconfig count mode. */ +#define IS_DMA_RC_CNT_MD(x) \ +( ((x) == DMA_RC_CNT_KEEP) || \ + ((x) == DMA_RC_CNT_SRC) || \ + ((x) == DMA_RC_CNT_DEST)) + +/* Parameter valid check for DMA reconfig destination address mode. */ +#define IS_DMA_RC_DA_MD(x) \ +( ((x) == DMA_RC_DEST_ADDR_KEEP) || \ + ((x) == DMA_RC_DEST_ADDR_NS) || \ + ((x) == DMA_RC_DEST_ADDR_RPT)) + +/* Parameter valid check for DMA reconfig source address mode. */ +#define IS_DMA_RC_SA_MD(x) \ +( ((x) == DMA_RC_SRC_ADDR_KEEP) || \ + ((x) == DMA_RC_SRC_ADDR_NS) || \ + ((x) == DMA_RC_SRC_ADDR_RPT)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Functions DMA Global Functions + * @{ + */ + +/** + * @brief DMA global function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_Cmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Global setting, ENABLE or DISABLE DMA */ + WRITE_REG32(DMAx->EN, enNewState); +} + +/** + * @brief DMA error IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32ErrInt DMA error IRQ flag. @ref DMA_Int_Request_Err_Sel, @ref DMA_Int_Trans_Err_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ErrIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } +} + +/** + * @brief Get DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer error flag & request error flag + */ +en_flag_status_t DMA_GetErrStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + return (0U != READ_REG32_BIT(DMAx->INTSTAT0, u32Flag) ? SET : RESET); +} + +/** + * @brief Clear DMA error flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA error IRQ flag. @ref DMA_Flag_Trans_Err_Sel, @ref DMA_Flag_Request_Err_Sel + * @retval None + * @note Include transfer error flag & request error flag + */ +void DMA_ClearErrStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR0, u32Flag); +} + +/** + * @brief DMA transfer IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32TransCompleteInt DMA transfer complete IRQ flag. @ref DMA_Int_Btc_Sel, @ref DMA_Int_Tc_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_TransCompleteIntCmd(CM_DMA_TypeDef *DMAx, uint32_t u32TransCompleteInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_INT(u32TransCompleteInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE == enNewState) { + SET_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } else { + CLR_REG32_BIT(DMAx->INTMASK1, u32TransCompleteInt); + } +} + +/** + * @brief Get DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer IRQ flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval An @ref en_flag_status_t enumeration type value. + * @note Include transfer complete flag & block transfer complete flag + */ +en_flag_status_t DMA_GetTransCompleteStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + return ((0U != READ_REG32_BIT(DMAx->INTSTAT1, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear DMA transfer flag. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Flag DMA transfer complete flag. @ref DMA_Flag_Btc_Sel, @ref DMA_Flag_Tc_Sel + * @retval None + * @note Include transfer complete flag & block transfer complete flag + */ +void DMA_ClearTransCompleteStatus(CM_DMA_TypeDef *DMAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_FLAG(u32Flag)); + + SET_REG32_BIT(DMAx->INTCLR1, u32Flag); +} + +/** + * @brief DMA multiplex channel function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8MxCh DMA multiplex channel. @ref DMA_Mx_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_MxChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_MX_CH(u8MxCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + WRITE_REG32(DMAx->CHEN, u8MxCh); + } else { + WRITE_REG32(DMAx->CHENCLR, u8MxCh); + } +} + +/** + * @brief DMA channel function config. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t + */ +int32_t DMA_ChCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + WRITE_REG32(DMAx->CHEN, ((1UL << u8Ch) & DMA_CHEN_CHEN)); + } else { + WRITE_REG32(DMAx->CHENCLR, ((1UL << u8Ch) & DMA_CHENCLR_CHENCLR)); + } + + return LL_OK; +} + +/** + * @brief Get DMA transfer status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA transfer status. @ref DMA_Trans_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetTransStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->CHSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Get DMA request status. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u32Status DMA request status. @ref DMA_Req_Status_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t DMA_GetRequestStatus(const CM_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_REQ_STAT(u32Status)); + + return ((0U != READ_REG32_BIT(DMAx->REQSTAT, u32Status)) ? SET : RESET); +} + +/** + * @brief Config DMA source address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA source address. + * @retval int32_t + */ +int32_t DMA_SetSrcAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr); + + return LL_OK; +} + +/** + * @brief Config DMA destination address. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr DMA destination address. + * @retval int32_t + */ +int32_t DMA_SetDestAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr); + + return LL_OK; +} + +/** + * @brief Config DMA transfer count. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Count DMA transfer count (0: infinite, 1 ~ 65535). + * @retval int32_t + */ +int32_t DMA_SetTransCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Count) +{ + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Count) << DMA_DTCTL_CNT_POS)); + return LL_OK; +} + +/** + * @brief Config DMA block size per transfer. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u16Size DMA block size (range: 0~1024, 0 is for 1024). + * @retval int32_t + */ +int32_t DMA_SetBlockSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(u16Size)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, u16Size); + + return LL_OK; +} + +/** + * @brief Config DMA data width per transfer. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32DataWidth DMA data width. @ref DMA_DataWidth_Sel + * @retval int32_t + */ +int32_t DMA_SetDataWidth(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32DataWidth) +{ + __IO uint32_t *CHxCTL0; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_DATA_WIDTH(u32DataWidth)); + + CHxCTL0 = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHxCTL0, DMA_CHCTL_HSIZE, u32DataWidth); + + return LL_OK; +} + +/** + * @brief Config DMA source repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Size DMA source repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetSrcRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size) +{ + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_REPEAT_SIZE(u32Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_SRPT, (u32Size << DMA_RPT_SRPT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA destination repeat size. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Size DMA destination repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval int32_t + */ +int32_t DMA_SetDestRepeatSize(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Size) +{ + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_REPEAT_SIZE(u32Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_DRPT, (u32Size << DMA_RPT_DRPT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA source transfer count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA source transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SNSCNT, (u32Count << DMA_SNSEQCTL_SNSCNT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA destination transfer count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Count DMA destination transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestCount(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Count) +{ + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(u32Count)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DNSCNT, (u32Count << DMA_DNSEQCTL_DNSCNT_POS)); + + return LL_OK; +} + +/** + * @brief Config DMA source offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA source offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqSrcOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + __IO uint32_t *SNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + SNSEQCTLx = &DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch); + MODIFY_REG32(*SNSEQCTLx, DMA_SNSEQCTL_SOFFSET, u32Offset); + + return LL_OK; +} + +/** + * @brief Config DMA destination offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Offset DMA destination offset (0 ~ 2^20 - 1). + * @retval int32_t + */ +int32_t DMA_SetNonSeqDestOffset(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Offset) +{ + __IO uint32_t *DNSEQCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(u32Offset)); + + DNSEQCTLx = &DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch); + MODIFY_REG32(*DNSEQCTLx, DMA_DNSEQCTL_DOFFSET, u32Offset); + + return LL_OK; +} + +/** + * @brief De-Initialize DMA channel function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval None + */ +void DMA_DeInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + /* Disable */ + SET_REG32_BIT(DMAx->CHENCLR, DMA_CHENCLR_CHENCLR_0 << u8Ch); + + /* Set default value. */ + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), 0UL); + CLR_REG32_BIT(DMAx->INTMASK0, (DMA_INTMASK0_MSKTRNERR_0 | DMA_INTMASK0_MSKREQERR_0) << u8Ch); + CLR_REG32_BIT(DMAx->INTMASK1, (DMA_INTMASK1_MSKTC_0 | DMA_INTMASK1_MSKBTC_0) << u8Ch); + SET_REG32_BIT(DMAx->INTCLR0, (DMA_INTCLR0_CLRTRNERR_0 | DMA_INTCLR0_CLRREQERR_0) << u8Ch); + SET_REG32_BIT(DMAx->INTCLR1, (DMA_INTCLR1_CLRTC_0 | DMA_INTCLR1_CLRBTC_0) << u8Ch); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), 1UL); + WRITE_REG32(DMA_CH_REG(DMAx->CHCTL0, u8Ch), 0x00001000UL); + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), 0UL); + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), 0UL); + +} + +/** + * @brief De-Initialize DMA function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + */ +int32_t DMA_UnitDeInit(CM_DMA_TypeDef *DMAx) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + __IO uint32_t *bCM_RMU_FRST0_DMAx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + if (CM_DMA1 == DMAx) { + bCM_RMU_FRST0_DMAx = &bCM_RMU->FRST0_b.DMA1; + } else { + bCM_RMU_FRST0_DMAx = &bCM_RMU->FRST0_b.DMA2; + } + /* Reset DMA */ + WRITE_REG32(*bCM_RMU_FRST0_DMAx, 0UL); + /* Ensure reset procedure is completed */ + while (READ_REG32(*bCM_RMU_FRST0_DMAx) != 1UL) { + u8TimeOut++; + if (u8TimeOut > DMA_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Initialize DMA config structure. Fill each pstcDmaInit with default value + * @param [in] pstcDmaInit Pointer to a stc_dma_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_StructInit(stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaInit->u32IntEn = DMA_INT_DISABLE; + pstcDmaInit->u32SrcAddr = 0x00UL; + pstcDmaInit->u32DestAddr = 0x00UL; + pstcDmaInit->u32DataWidth = DMA_DATAWIDTH_8BIT; + pstcDmaInit->u32BlockSize = 0x01UL; + pstcDmaInit->u32TransCount = 0x00UL; + pstcDmaInit->u32SrcAddrInc = DMA_SRC_ADDR_FIX; + pstcDmaInit->u32DestAddrInc = DMA_DEST_ADDR_FIX; + } + return i32Ret; +} + +/** + * @brief DMA basic function initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaInit DMA config structure. + * @arg u32IntEn DMA interrupt ENABLE or DISABLE. + * @arg u32SrcAddr DMA source address. + * @arg u32DestAddr DMA destination address. + * @arg u32DataWidth DMA data width. + * @arg u32BlockSize DMA block size. + * @arg u32TransCount DMA transfer count. + * @arg u32SrcAddrInc DMA source address direction. + * @arg u32DestAddrInc DMA destination address direction. + * @retval int32_t: + * - LL_OK: DMA basic function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_Init(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_DATA_WIDTH(pstcDmaInit->u32DataWidth)); + DDL_ASSERT(IS_DMA_SADDR_MD(pstcDmaInit->u32SrcAddrInc)); + DDL_ASSERT(IS_DMA_DADDR_MD(pstcDmaInit->u32DestAddrInc)); + DDL_ASSERT(IS_DMA_BLOCK_SIZE(pstcDmaInit->u32BlockSize)); + DDL_ASSERT(IS_DMA_INT_FUNC(pstcDmaInit->u32IntEn)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), pstcDmaInit->u32SrcAddr); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), pstcDmaInit->u32DestAddr); + + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), ((pstcDmaInit->u32BlockSize & DMA_DTCTL_BLKSIZE) | \ + (pstcDmaInit->u32TransCount << DMA_DTCTL_CNT_POS))); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SINC | DMA_CHCTL_DINC | DMA_CHCTL_HSIZE | DMA_CHCTL_IE), \ + (pstcDmaInit->u32IntEn | pstcDmaInit->u32DataWidth | pstcDmaInit->u32SrcAddrInc | \ + pstcDmaInit->u32DestAddrInc)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA repeat mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaRepeatInit Pointer to a stc_dma_repeat_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA repeat mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_RepeatStructInit(stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRepeatInit->u32Mode = DMA_RPT_NONE; + pstcDmaRepeatInit->u32SrcCount = 0x00UL; + pstcDmaRepeatInit->u32DestCount = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA repeat mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRepeatInit DMA repeat mode config structure. + * @note Call this function after DMA_Init(); + */ +int32_t DMA_RepeatInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_repeat_init_t *pstcDmaRepeatInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRepeatInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RPT_MD(pstcDmaRepeatInit->u32Mode)); + DDL_ASSERT(IS_DMA_REPEAT_SIZE(pstcDmaRepeatInit->u32DestCount)); + DDL_ASSERT(IS_DMA_REPEAT_SIZE(pstcDmaRepeatInit->u32SrcCount)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SRPTEN | DMA_CHCTL_DRPTEN), pstcDmaRepeatInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), \ + ((pstcDmaRepeatInit->u32DestCount << DMA_RPT_DRPT_POS) | pstcDmaRepeatInit->u32SrcCount) & \ + (DMA_RPT_DRPT | DMA_RPT_SRPT)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA non-sequence mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaNonSeqInit Pointer to a stc_dma_nonseq_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA non-sequence mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaNonSeqInit->u32Mode = DMA_NON_SEQ_NONE; + pstcDmaNonSeqInit->u32SrcCount = 0x00UL; + pstcDmaNonSeqInit->u32SrcOffset = 0x00UL; + pstcDmaNonSeqInit->u32DestCount = 0x00UL; + pstcDmaNonSeqInit->u32DestOffset = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA non-sequence mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaNonSeqInit DMA non-sequence mode config structure. + * @retval int32_t: + * - LL_OK: DMA non-sequence function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_NonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_NON_SEQ_MD(pstcDmaNonSeqInit->u32Mode)); + + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32SrcCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_TRANS_CNT(pstcDmaNonSeqInit->u32DestCount)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32SrcOffset)); + DDL_ASSERT(IS_DMA_NON_SEQ_OFFSET(pstcDmaNonSeqInit->u32DestOffset)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), pstcDmaNonSeqInit->u32Mode); + + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32SrcCount << DMA_SNSEQCTL_SNSCNT_POS) | \ + pstcDmaNonSeqInit->u32SrcOffset)); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), ((pstcDmaNonSeqInit->u32DestCount << DMA_DNSEQCTL_DNSCNT_POS) | \ + pstcDmaNonSeqInit->u32DestOffset)); + + } + return i32Ret; +} + +/** + * @brief Initialize DMA Linked List Pointer (hereafter, LLP) mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaLlpInit Pointer to a stc_dma_llp_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA LLP mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaLlpInit->u32State = DMA_LLP_DISABLE; + pstcDmaLlpInit->u32Mode = DMA_LLP_WAIT; + pstcDmaLlpInit->u32Addr = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA LLP mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaLlpInit DMA LLP config structure. + * @arg u32State DMA LLP ENABLE or DISABLE. + * @arg u32Mode DMA LLP auto-run or wait request. + * @arg u32Addr DMA LLP next list pointer address. + * @arg u32AddrSelect DMA LLP address mode. + * @retval int32_t: + * - LL_OK: DMA LLP function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_LlpInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaLlpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_LLP_EN(pstcDmaLlpInit->u32State)); + DDL_ASSERT(IS_DMA_LLP_MD(pstcDmaLlpInit->u32Mode)); + DDL_ASSERT(IS_DMA_LLP_ADDR_ALIGN(pstcDmaLlpInit->u32Addr)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_LLPEN | DMA_CHCTL_LLPRUN), \ + (pstcDmaLlpInit->u32State | pstcDmaLlpInit->u32Mode)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), pstcDmaLlpInit->u32Addr & DMA_LLP_LLP); + + } + + return i32Ret; +} + +/** + * @brief Config DMA LLP value. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] u32Addr Next link pointer address for DMA LLP mode. + * @retval None + */ +void DMA_SetLlpAddr(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_LLP_ADDR_ALIGN(u32Addr)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), (u32Addr & DMA_LLP_LLP)); +} + +/** + * @brief DMA LLP ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_LlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } else { + CLR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + + } +} + +/** + * @brief DMA reconfig function ENABLE or DISABLE. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigCmd(CM_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMAx->RCFGCTL, 1UL); + } else { + CLR_REG32_BIT(DMAx->RCFGCTL, 1UL); + } +} + +/** + * @brief DMA LLP ENABLE or DISABLE for reconfig function. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void DMA_ReconfigLlpCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(DMAx->RCFGCTL, DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_RCFGLLP, \ + ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS) | ((uint32_t)enNewState << DMA_RCFGCTL_RCFGLLP_POS)); +} + +/** + * @brief Initialize DMA re-config mode config structure. + * Fill each pstcDmaRCInit with default value + * @param [in] pstcDmaRCInit Pointer to a stc_dma_reconfig_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA reconfig mode config structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_ReconfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRCInit->u32CountMode = DMA_RC_CNT_KEEP; + pstcDmaRCInit->u32DestAddrMode = DMA_RC_DEST_ADDR_KEEP; + pstcDmaRCInit->u32SrcAddrMode = DMA_RC_SRC_ADDR_KEEP; + } + return i32Ret; +} + +/** + * @brief DMA reconfig mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRCInit DMA reconfig mode config structure + * @arg u32CountMode DMA reconfig count mode. + * @arg u32DestAddrMode DMA reconfig destination address mode. + * @arg u32SrcAddrMode DMA reconfig source address mode. + * @retval int32_t: + * - LL_OK: DMA reconfig function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer +*/ +int32_t DMA_ReconfigInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRCInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_RC_CNT_MD(pstcDmaRCInit->u32CountMode)); + DDL_ASSERT(IS_DMA_RC_DA_MD(pstcDmaRCInit->u32DestAddrMode)); + DDL_ASSERT(IS_DMA_RC_SA_MD(pstcDmaRCInit->u32SrcAddrMode)); + + MODIFY_REG32(DMAx->RCFGCTL, \ + (DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_SARMD | DMA_RCFGCTL_DARMD | DMA_RCFGCTL_CNTMD), \ + (pstcDmaRCInit->u32CountMode | pstcDmaRCInit->u32SrcAddrMode | \ + pstcDmaRCInit->u32DestAddrMode | ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS))); + } + return i32Ret; +} + +/** + * @brief Initialize DMA non-sequence mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaRcNonSeqInit Pointer to a stc_dma_rc_nonseq_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA non-sequence mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t DMA_ReconfigNonSeqStructInit(stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcDmaRcNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcDmaRcNonSeqInit->u32Mode = DMA_NON_SEQ_NONE; + pstcDmaRcNonSeqInit->u32SrcCount = 0x01UL; + pstcDmaRcNonSeqInit->u32SrcDist = 0x00UL; + pstcDmaRcNonSeqInit->u32DestCount = 0x01UL; + pstcDmaRcNonSeqInit->u32DestDist = 0x00UL; + } + return i32Ret; +} + +/** + * @brief DMA non-sequence mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] pstcDmaRcNonSeqInit Pointer to a stc_dma_rc_nonseq_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: DMA non-sequence function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + * @note Call this function after DMA_Init(); + */ +int32_t DMA_ReconfigNonSeqInit(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_rc_nonseq_init_t *pstcDmaRcNonSeqInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRcNonSeqInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_DMA_NON_SEQ_MD(pstcDmaRcNonSeqInit->u32Mode)); + DDL_ASSERT(IS_DMA_RC_NON_SEQ_TRANS_CNT(pstcDmaRcNonSeqInit->u32SrcCount)); + DDL_ASSERT(IS_DMA_RC_NON_SEQ_TRANS_CNT(pstcDmaRcNonSeqInit->u32DestCount)); + DDL_ASSERT(IS_DMA_RC_NON_SEQ_DIST(pstcDmaRcNonSeqInit->u32SrcDist)); + DDL_ASSERT(IS_DMA_RC_NON_SEQ_DIST(pstcDmaRcNonSeqInit->u32DestDist)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), pstcDmaRcNonSeqInit->u32Mode); + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTLB0, u8Ch), + ((pstcDmaRcNonSeqInit->u32SrcCount << DMA_SNSEQCTLB_SNSCNTB_POS) | pstcDmaRcNonSeqInit->u32SrcDist)); + WRITE_REG32(DMA_CH_REG(DMAx->DNSEQCTLB0, u8Ch), + ((pstcDmaRcNonSeqInit->u32DestCount << DMA_DNSEQCTLB_DNSCNTB_POS) | pstcDmaRcNonSeqInit->u32DestDist)); + } + return i32Ret; +} + +/** + * @brief DMA get current source address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source address. + */ +uint32_t DMA_GetSrcAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONSAR0, u8Ch)); +} + +/** + * @brief DMA get current destination address + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination address. + */ +uint32_t DMA_GetDestAddr(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONDAR0, u8Ch)); +} + +/** + * @brief DMA get current transfer count + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current transfer count. + */ +uint32_t DMA_GetTransCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch)) >> DMA_DTCTL_CNT_POS) & 0xFFFFUL); +} + +/** + * @brief DMA get current block size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current block size. + */ +uint32_t DMA_GetBlockSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch), DMA_DTCTL_BLKSIZE)); +} + +/** + * @brief DMA get current source repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source repeat size. + */ +uint32_t DMA_GetSrcRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONRPT0, u8Ch), DMA_RPT_SRPT)); +} + +/** + * @brief DMA get current destination repeat size + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination repeat size. + */ +uint32_t DMA_GetDestRepeatSize(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONRPT0, u8Ch)) >> DMA_RPT_DRPT_POS) & 0x3FFUL); +} + +/** + * @brief DMA get current source count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch)) >> DMA_SNSEQCTLB_SNSCNTB_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current destination count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA,, x can be 0-1 + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestCount(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch)) >> DMA_DNSEQCTL_DNSCNT_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current source offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current source offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch), DMA_SNSEQCTL_SOFFSET)); +} + +/** + * @brief DMA get current destination offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @retval Current destination offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestOffset(const CM_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch), DMA_DNSEQCTL_DOFFSET)); +} + +/** + * @brief Enable or disable AHB HPROT bufferable and cacheable transfer + * @param [in] DMAx DMA unit instance. + * @arg CM_DMAx or CM_DMA + * @param [in] u8Ch DMA channel. @ref DMA_Channel_selection + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note This command can only be enabled when DMA accesses SMC, otherwise please disable it + */ +void DMA_AHB_HProtBufCacheCmd(CM_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_HPROT); + } else { + CLR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_HPROT); + } +} +/** + * @} + */ + +#endif /* LL_DMA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c new file mode 100644 index 0000000000..eae40247d1 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_efm.c @@ -0,0 +1,1479 @@ +/** + ******************************************************************************* + * @file hc32_ll_efm.c + * @brief This file provides firmware functions to manage the Embedded Flash + * Memory unit (EFM). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + 2023-09-30 CDT Remove address assert from EFM_ReadByte() + Refine EFM_SequenceProgram() & EFM_ChipErase(), and put them in RAM + 2023-12-15 CDT Rename EFM_DataCacheResetCmd() as EFM_CacheRamReset() and modify comment + Add API EFM_GetWaferID(), EFM_GetLocation(), EFM_GetLotID() + Modify flash sector number defined and API EFM_SequenceSectorOperateCmd() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_efm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EFM EFM + * @brief Embedded Flash Management Driver Library + * @{ + */ + +#if (LL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Local_Macros EFM Local Macros + * @{ + */ +#ifndef __EFM_FUNC +#define __EFM_FUNC __RAM_FUNC +#endif + +/** + * @defgroup EFM_Timeout_Definition EFM timeout definition + * @{ + */ +#define EFM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM wait read timeout */ +#define EFM_PGM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM Program timeout max 53us */ +#define EFM_ERASE_TIMEOUT (HCLK_VALUE / 50UL) /* EFM Erase timeout max 20ms */ +#define EFM_SEQ_PGM_TIMEOUT (HCLK_VALUE / 62500UL) /* EFM Sequence Program timeout max 16us */ +/** + * @} + */ + +#define REMCR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_EFM->MMF_REMCR0) + (4UL * (x)))) + +#define REG_LEN (32U) +#define EFM_SWAP_FLASH1_END_SECTOR_NUM (EFM_FLASH1_START_SECTOR_NUM + EFM_OTP_END_SECTOR_NUM) +#define EFM_SWAP_FLASH1_END_ADDR (EFM_FLASH_1_START_ADDR + EFM_OTP_END_ADDR1) +#define EFM_OTP_UNLOCK_KEY1 (0x10325476UL) +#define EFM_OTP_UNLOCK_KEY2 (0xEFCDAB89UL) + +/** + * @defgroup EFM_Configuration_Bit_Mask EFM Configuration Bit Mask + * @{ + */ +#define EFM_CACHE_ALL (EFM_FRMC_CRST | EFM_FRMC_PREFETE | EFM_FRMC_DCACHE | EFM_FRMC_ICACHE) + +/** + * @} + */ + +/** + * @defgroup EFM_protect EFM protect define + * @{ + */ +#define EFM_SECURITY_LEN (12UL) +#define EFM_PROTECT1_KEY (0xAF180402UL) +#define EFM_PROTECT2_KEY (0xA85173AEUL) + +#define EFM_PROTECT3_KEY (0x42545048UL) +#define EFM_PROTECT1_ADDR (0x00000430UL) +#define EFM_PROTECT2_ADDR (0x00000434UL) +#define EFM_PROTECT3_ADDR1 (0x00000420UL) +#define EFM_PROTECT3_ADDR2 (0x00000424UL) +#define EFM_PROTECT3_ADDR3 (0x00000428UL) +#define EFM_SECURITY_ADDR (0x03002040UL) + +#define EFM_SWAP_ON_PROTECT_SECTOR_NUM (1U) +/** + * @} + */ + +/** + * @defgroup EFM_Check_Parameters_Validity EFM Check Parameters Validity + * @{ + */ +/* Parameter validity check for efm chip . */ +#define IS_EFM_CHIP(x) ((x) == EFM_CHIP_ALL) + +/* Parameter validity check for flash latency. */ +#define IS_EFM_WAIT_CYCLE(x) ((x) <= EFM_WAIT_CYCLE15) + +/* Parameter validity check for operate mode. */ +#define IS_EFM_OPERATE_MD(x) \ +( ((x) == EFM_MD_PGM_SINGLE) || \ + ((x) == EFM_MD_PGM_READBACK) || \ + ((x) == EFM_MD_PGM_SEQ) || \ + ((x) == EFM_MD_ERASE_SECTOR) || \ + ((x) == EFM_MD_ERASE_ALL_CHIP) || \ + ((x) == EFM_MD_READONLY)) + +/* Parameter validity check for flash interrupt select. */ +#define IS_EFM_INT_SEL(x) (((x) | EFM_INT_ALL) == EFM_INT_ALL) + +/* Parameter validity check for flash flag. */ +#define IS_EFM_FLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for flash clear flag. */ +#define IS_EFM_CLRFLAG(x) (((x) | EFM_FLAG_ALL) == EFM_FLAG_ALL) + +/* Parameter validity check for bus status while flash program or erase. */ +#define IS_EFM_BUS_STATUS(x) \ +( ((x) == EFM_BUS_HOLD) || \ + ((x) == EFM_BUS_RELEASE)) + +/* Parameter validity check for efm address. */ +#define IS_EFM_ADDR(x) \ +( ((x) <= EFM_END_ADDR) || \ + (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR)) || \ + (((x) >= EFM_SECURITY_START_ADDR) && ((x) <= EFM_SECURITY_END_ADDR))) + +/* Parameter validity check for efm erase address. */ +#define IS_EFM_ERASE_ADDR(x) \ +( ((x) <= EFM_END_ADDR) || \ + (((x) >= EFM_OTP_START_ADDR) && ((x) <= EFM_OTP_END_ADDR))) + +/* Parameter validity check for efm erase mode . */ +#define IS_EFM_ERASE_MD(x) \ +( ((x) == EFM_MD_ERASE_ONE_CHIP) || \ + ((x) == EFM_MD_ERASE_FULL)) + +/* Parameter validity check for EFM lock status. */ +#define IS_EFM_REG_UNLOCK() (CM_EFM->FAPRT == 0x00000001UL) + +/* Parameter validity check for EFM_FWMC register lock status. */ +#define IS_EFM_FWMC_UNLOCK() (bCM_EFM->FWMC_b.KEY1LOCK == 0U) + +/* Parameter validity check for OTP lock status. */ +#define IS_EFM_OTP_UNLOCK() (bCM_EFM->FWMC_b.KEY2LOCK == 0U) + +/* Parameter validity check for sector protected register locking. */ +#define IS_EFM_SECTOR_PROTECT_REG_LOCK(x) ((x) == EFM_WLOCK_WLOCK0) + +/* Parameter validity check for EFM sector number */ +#define IS_EFM_SECTOR_NUM(x) ((x) <= 32U) +#define IS_EFM_SECTOR_IDX(x) ((x) < 32U) + +/* Parameter validity check for EFM OTP lock address */ +#define IS_EFM_OTP_LOCK_ADDR(x) \ +( ((x) == EFM_OTP_LOCK_ADDR_START) || \ + (((x) >= EFM_OTP_LOCK_ADDR_START1) && ((x) <= EFM_OTP_LOCK_ADDR_END))) + +/* Parameter validity check for EFM remap lock status. */ +#define IS_EFM_REMAP_UNLOCK() (CM_EFM->MMF_REMPRT == 0x00000001UL) + +/* Parameter validity check for EFM remap index */ +#define IS_EFM_REMAP_IDX(x) \ +( ((x) == EFM_REMAP_IDX0) || \ + ((x) == EFM_REMAP_IDX1)) + +/* Parameter validity check for EFM remap size */ +#define IS_EFM_REMAP_SIZE(x) \ +( ((x) >= EFM_REMAP_4K) && \ + ((x) <= EFM_REMAP_SIZE_MAX)) + +/* Parameter validity check for EFM remap address */ +#define IS_EFM_REMAP_ADDR(x) \ +( ((x) <= EFM_REMAP_ROM_END_ADDR) || \ + (((x) >= EFM_REMAP_RAM_START_ADDR) && \ + ((x) <= EFM_REMAP_RAM_END_ADDR))) + +/* Parameter validity check for EFM remap state */ +#define IS_EFM_REMAP_STATE(x) \ +( ((x) == EFM_REMAP_OFF) || \ + ((x) == EFM_REMAP_ON)) + +/* Parameter validity check for EFM security code length */ +#define IS_EFM_SECURITY_CODE_LEN(x) ((x) <= EFM_SECURITY_LEN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EFM_Local_Functions EFM Local Functions + * @{ + */ +/** + * @brief Wait EFM flag. + * @param [in] u32Flag Specifies the flag to be wait. @ref EFM_Flag_Sel + * @param [in] u32Time Specifies the time to wait while the flag not be set. + * @retval int32_t: + * - LL_OK: Flag was set. + * - LL_ERR_TIMEOUT: Flag was not set. + */ +static int32_t EFM_WaitFlag(uint32_t u32Flag, uint32_t u32Time) +{ + __IO uint32_t u32Timeout = 0UL; + int32_t i32Ret = LL_OK; + + while (SET != EFM_GetStatus(u32Flag)) { + u32Timeout++; + if (u32Timeout > u32Time) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup EFM_Global_Functions EFM Global Functions + * @{ + */ + +/** + * @brief Enable or disable EFM. + * @param [in] u32Flash Specifies the FLASH. @ref EFM_Chip_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_Cmd(uint32_t u32Flash, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CHIP(u32Flash)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_EFM->FSTP, u32Flash); + } else { + SET_REG32_BIT(CM_EFM->FSTP, u32Flash); + } +} + +/** + * @brief Set the efm read wait cycles. + * @param [in] u32WaitCycle Specifies the efm read wait cycles. + * @arg This parameter can be of a value of @ref EFM_Wait_Cycle + * @retval int32_t: + * - LL_OK: Program successfully. + * - LL_ERR_TIMEOUT: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SetWaitCycle(uint32_t u32WaitCycle) +{ + uint32_t u32Timeout = 0UL; + + /* Param valid check */ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_WAIT_CYCLE(u32WaitCycle)); + + MODIFY_REG32(CM_EFM->FRMC, EFM_FRMC_FLWT, u32WaitCycle); + while (u32WaitCycle != READ_REG32_BIT(CM_EFM->FRMC, EFM_FRMC_FLWT)) { + u32Timeout++; + if (u32Timeout > EFM_TIMEOUT) { + return LL_ERR_TIMEOUT; + } + } + return LL_OK; +} + +/** + * @brief Reset cache RAM or cache ram release reset. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_CacheRamReset(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.CRST, enNewState); +} + +/** + * @brief Enable or disable the flash prefetch. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_PrefetchCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.PREFETE, enNewState); +} + +/** + * @brief Enable or disable the flash data cache. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_DCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.DCACHE, enNewState); +} + +/** + * @brief Enable or disable the flash instruction cache. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_ICacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.ICACHE, enNewState); +} + +/** + * @brief Enable or disable the Read of low-voltage mode. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_LowVoltageReadCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, enNewState); +} + +/** + * @brief Enable or disable the EFM swap function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval int32_t: + * - LL_OK: Program successfully. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SwapCmd(en_functional_state_t enNewState) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + if (enNewState == ENABLE) { + /* Set Program single mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Enable flash swap function */ + RW_MEM32(EFM_SWAP_ADDR) = EFM_SWAP_DATA; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } else { + /* Set Sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief Checks whether the swap function enable or disable. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetSwapStatus(void) +{ + return ((0UL == READ_REG32(bCM_EFM->FSWP_b.FSWP)) ? RESET : SET); +} + +/** + * @brief Set the FLASH erase program mode . + * @param [in] u32Mode Specifies the FLASH erase program mode. + * @arg This parameter can be of a value of @ref EFM_OperateMode_Sel + * @retval int32_t: + * - LL_OK: Set mode successfully. + * - LL_ERR_NOT_RDY: EFM is not ready. + */ +int32_t EFM_SetOperateMode(uint32_t u32Mode) +{ + int32_t i32Ret = LL_OK; + DDL_ASSERT(IS_EFM_OPERATE_MD(u32Mode)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_SEQ_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + if (i32Ret == LL_OK) { + /* Set the program or erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, u32Mode); + } + return i32Ret; +} + +/** + * @brief Enable or Disable EFM interrupt. + * @param [in] u32EfmInt Specifies the FLASH interrupt source and status. @ref EFM_Interrupt_Sel + * @arg EFM_INT_OPTEND: End of EFM Operation Interrupt source + * @arg EFM_INT_PEERR: Program/erase error Interrupt source + * @arg EFM_INT_COLERR: Read collide error Interrupt source + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_IntCmd(uint32_t u32EfmInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_INT_SEL(u32EfmInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } else { + CLR_REG32_BIT(CM_EFM->FITE, u32EfmInt); + } +} + +/** + * @brief Check any of the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetAnyStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((0UL == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Check all the specified flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EFM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_FLAG(u32Flag)); + + return ((u32Flag == READ_REG32_BIT(CM_EFM->FSR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear the flash flag. + * @param [in] u32Flag Specifies the FLASH flag to clear. + * @arg This parameter can be of a value of @ref EFM_Flag_Sel + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_CLRFLAG(u32Flag)); + + SET_REG32_BIT(CM_EFM->FSCLR, u32Flag); +} + +/** + * @brief Set bus status while flash program or erase. + * @param [in] u32Status Specifies the new bus status while flash program or erase. + * This parameter can be one of the following values: + * @arg EFM_BUS_HOLD: Bus busy while flash program or erase. + * @arg EFM_BUS_RELEASE: Bus release while flash program or erase. + * @retval None + */ +void EFM_SetBusStatus(uint32_t u32Status) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_BUS_STATUS(u32Status)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + WRITE_REG32(bCM_EFM->FWMC_b.BUSHLDCTL, u32Status); +} + +/** + * @brief EFM read byte. + * @param [in] u32Addr The specified address to read. + * @param [in] pu8ReadBuf The specified read buffer. + * @param [in] u32ByteLen The specified length to read. + * @retval int32_t: + * - LL_OK: Read successfully + * - LL_ERR_INVD_PARAM: Invalid parameter + * - LL_ERR_NOT_RDY: EFM is not ready. + */ +int32_t EFM_ReadByte(uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32ByteLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint8_t *pu8Buf = (uint8_t *)u32Addr; + uint32_t u32Len = u32ByteLen; + uint32_t u32ReadyFlag = EFM_FLAG_RDY; + + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32ByteLen - 1UL)); + + if (NULL != pu8ReadBuf) { + + if (LL_OK == EFM_WaitFlag(u32ReadyFlag, EFM_TIMEOUT)) { + while (0UL != u32Len) { + *(pu8ReadBuf++) = *(pu8Buf++); + u32Len--; + } + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_NOT_RDY; + } + } + + return i32Ret; +} + +/** + * @brief EFM program (single program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successful. + * - LL_ERR_NOT_RDY: EFM if not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_Program(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32LastWord; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_EFM_ADDR(u32Addr + u32Len - 1UL)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + u8Shift = 0U; + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + *u32pDest++ = u32LastWord; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + } + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM single program mode(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successfully + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWord(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE function */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + /* Program data. */ + RW_MEM32(u32Addr) = u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM single program with read back(Word). + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval int32_t: + * - LL_OK: Program successfully + * - LL_ERR: program error + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_ProgramWordReadBack(uint32_t u32Addr, uint32_t u32Data) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + /* Clear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set Program and read back mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_READBACK); + /* Program data. */ + RW_MEM32(u32Addr) = (uint32_t)u32Data; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + + /* Get the flag PGMISMTCH */ + if (SET == EFM_GetStatus(EFM_FLAG_PGMISMTCH << u8Shift)) { + /* Clear flag PGMISMTCH */ + EFM_ClearStatus(EFM_FLAG_PGMISMTCH << u8Shift); + i32Ret = LL_ERR; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM program (sequence program mode). + * @param [in] u32Addr The specified program address. + * @param [in] pu8Buf The pointer of specified program data. + * @param [in] u32Len The length of specified program data. + * @retval int32_t: + * - LL_OK: Program successfully + * - LL_ERR_TIMEOUT: program error timeout + * @note Call EFM_REG_Unlock() unlock EFM register first. + * __EFM_FUNC default value is __RAM_FUNC. + */ +__EFM_FUNC int32_t EFM_SequenceProgram(uint32_t u32Addr, uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32RemainBytes = u32Len % 4UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)u32Addr; + uint32_t u32Timeout; + uint32_t u32LastWord; + + /* Assert */ + if (!IS_EFM_REG_UNLOCK()) { + return LL_ERR_NOT_RDY; + } + if ((!IS_EFM_FWMC_UNLOCK()) || (!IS_EFM_ADDR(u32Addr)) || (!IS_EFM_ADDR(u32Addr + u32Len - 1UL))) { + return LL_ERR_INVD_PARAM; + } + if (!IS_ADDR_ALIGN_WORD(u32Addr)) { + return LL_ERR_INVD_PARAM; + } + + /* CLear the error flag. */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Set sequence program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SEQ); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* wait for operation end flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* Clear operation end flag */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND); + if (u32Timeout++ >= EFM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + } + + if (0U != u32RemainBytes) { + u32LastWord = *u32pSource; + u32LastWord |= 0xFFFFFFFFUL << (u32RemainBytes * 8UL); + *u32pDest++ = u32LastWord; + + /* wait for operation end flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* Clear operation end flag */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND == READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND); + if (u32Timeout++ >= EFM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Wait for ready flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_RDY != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief EFM sector erase. + * @param [in] u32Addr The address in the specified sector. + * @retval int32_t: + * - LL_OK: Erase successful. + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +int32_t EFM_SectorErase(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint8_t u8Shift; + + DDL_ASSERT(IS_EFM_ERASE_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + u8Shift = 0U; + /* Set sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY << u8Shift, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* Clear the operation end flag */ + EFM_ClearStatus(EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief EFM chip erase. + * @param [in] u8Chip Specifies the chip to be erased @ref EFM_Chip_Sel + * @retval int32_t: + * - LL_OK: Erase successfully + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note Call EFM_REG_Unlock() unlock EFM register first. + * __EFM_FUNC default value is __RAM_FUNC. + */ +__EFM_FUNC int32_t EFM_ChipErase(uint8_t u8Chip) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32Addr = 0UL; + uint8_t u8Shift; + uint32_t u32Timeout; + + /* Assert */ + if (!IS_EFM_REG_UNLOCK()) { + return LL_ERR_NOT_RDY; + } + if ((!IS_EFM_FWMC_UNLOCK()) || !IS_EFM_CHIP(u8Chip)) { + return LL_ERR_INVD_PARAM; + } + + u8Shift = 0U; + + /* CLear the error flag. */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + if (1UL == (READ_REG32(bCM_EFM->FSWP_b.FSWP))) { + /* Set Sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + /* wait for operation end flag. */ + u32Timeout = 0UL; + while (EFM_FLAG_OPTEND != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_OPTEND)) { + if (u32Timeout++ >= EFM_PGM_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* CLear the operation end flag */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND); + } + + /* Set chip erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_ALL_CHIP); + /* Erase */ + RW_MEM32(u32Addr) = 0UL; + /* Wait for ready flag. */ + u32Timeout = 0UL; + while ((EFM_FLAG_RDY << u8Shift) != READ_REG32_BIT(CM_EFM->FSR, EFM_FLAG_RDY << u8Shift)) { + if (u32Timeout++ >= EFM_ERASE_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + /* CLear the operation end flag. */ + SET_REG32_BIT(CM_EFM->FSCLR, EFM_FLAG_OPTEND << u8Shift); + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @brief FWMC register write enable or disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_FWMC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + WRITE_REG32(CM_EFM->KEY1, 0x01234567UL); + WRITE_REG32(CM_EFM->KEY1, 0xFEDCBA98UL); + } else { + SET_REG32_BIT(CM_EFM->FWMC, EFM_FWMC_KEY1LOCK); + } +} + +/** + * @brief EFM OTP lock. + * @param [in] u32Addr Specifies the OTP block + * @retval int32_t: + * - LL_OK: Lock successfully + * - LL_ERR_NOT_RDY: EFM is not ready. + * @note The address should be word align. + * Call EFM_REG_Unlock() and EFM_OTP_WP_Unlock() unlock EFM_FWMC register first. + */ +int32_t EFM_OTP_Lock(uint32_t u32Addr) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + + if ((u32Addr >= EFM_OTP_LOCK_ADDR_START) && (u32Addr < EFM_OTP_LOCK_ADDR_END)) { + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_OTP_UNLOCK()); + DDL_ASSERT(IS_EFM_OTP_LOCK_ADDR(u32Addr)); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + /* OTP latch */ + RW_MEM32(u32Addr) = (uint32_t)0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_ERASE_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + } + + return i32Ret; +} + +/** + * @brief Get chip ID. + * @param None + * @retval Returns the value of the Chip ID + */ +uint32_t EFM_GetCID(void) +{ + return READ_REG32(CM_EFM->CHIPID); +} + +/** + * @brief EFM OTP operate unlock. + * @param None + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_OTP_WP_Unlock(void) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + WRITE_REG32(CM_EFM->KEY2, EFM_OTP_UNLOCK_KEY1); + WRITE_REG32(CM_EFM->KEY2, EFM_OTP_UNLOCK_KEY2); +} + +/** + * @brief EFM OTP write protect lock. + * @param None + * @retval None + */ +void EFM_OTP_WP_Lock(void) +{ + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + SET_REG32_BIT(CM_EFM->FWMC, EFM_FWMC_KEY2LOCK); +} + +/** + * @brief EFM OTP Enable. + * @param None + * @retval None + */ +int32_t EFM_OTP_Enable(void) +{ + uint32_t u32Tmp; + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EFM_OTP_UNLOCK()); + + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + if (0xFFFFFFFFUL == RW_MEM32(EFM_OTP_ENABLE_ADDR)) { + /* Enable OTP */ + RW_MEM32(EFM_OTP_ENABLE_ADDR) = (uint32_t)0UL; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + + return i32Ret; +} + +/** + * @brief Sector protected register lock. + * @param [in] u32RegLock Specifies sector protected register locking. + * @arg EFM_WRLOCK0 + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + */ +void EFM_SectorProtectRegLock(uint32_t u32RegLock) +{ + DDL_ASSERT(IS_EFM_SECTOR_PROTECT_REG_LOCK(u32RegLock)); + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + + SET_REG32_BIT(CM_EFM->WLOCK, u32RegLock); +} + +/** + * @brief Set sector lock or unlock (Single). + * @param [in] u8SectorNum Specifies sector for unlock. + * This parameter can be set 0~31. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + * If you want to unlock sequence sectors,Please call EFM_SequenceSectorOperateCmd function + */ +void EFM_SingleSectorOperateCmd(uint8_t u8SectorNum, en_functional_state_t enNewState) +{ + const uint8_t u8BitPos = u8SectorNum % REG_LEN; + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EFM_SECTOR_IDX(u8SectorNum)); + + MODIFY_REG32(CM_EFM->F0NWPRT, 1UL << u8BitPos, (uint32_t)enNewState << u8BitPos); +} + +/** + * @brief Set sector lock or unlock (Sequence). + * @param [in] u32StartSectorNum Specifies start sector to unlock. + * This parameter can be set 0~31. + * @param [in] u16Count Specifies count of sectors to unlock. + * This parameter can be set 1~32. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call EFM_REG_Unlock() unlock EFM register first. + * If you want to unlock only one sector,Please call EFM_SingleSectorOperateCmd function + */ +void EFM_SequenceSectorOperateCmd(uint32_t u32StartSectorNum, uint16_t u16Count, en_functional_state_t enNewState) +{ + uint32_t u32RegValue; + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_SECTOR_IDX(u32StartSectorNum)); + DDL_ASSERT(IS_EFM_SECTOR_NUM(u32StartSectorNum + u16Count)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (SET == EFM_GetSwapStatus()) { + if (1UL == u32StartSectorNum) { + u32RegValue = 1UL | (uint32_t)(((uint64_t)1UL << (u32StartSectorNum + u16Count)) - \ + ((uint64_t)1UL << (u32StartSectorNum + 1UL))); + } else if ((0UL == u32StartSectorNum) && (1U == u16Count)) { + u32RegValue = 1UL << 1U; + } else { + u32RegValue = (uint32_t)(((uint64_t)1UL << (u32StartSectorNum + u16Count)) - \ + ((uint64_t)1UL << u32StartSectorNum)); + } + } else { + u32RegValue = (uint32_t)(((uint64_t)1UL << (u32StartSectorNum + u16Count)) - \ + ((uint64_t)1UL << u32StartSectorNum)); + } + + if (enNewState == ENABLE) { + SET_REG32_BIT(CM_EFM->F0NWPRT, u32RegValue); + } else { + CLR_REG32_BIT(CM_EFM->F0NWPRT, u32RegValue); + } +} + +/** + * @brief Get unique ID. + * @param [out] pstcUID Unique ID struct + * @retval Returns the value of the unique ID + */ +void EFM_GetUID(stc_efm_unique_id_t *pstcUID) +{ + if (NULL != pstcUID) { + pstcUID->u32UniqueID0 = READ_REG32(CM_EFM->UQID0); + pstcUID->u32UniqueID1 = READ_REG32(CM_EFM->UQID1); + pstcUID->u32UniqueID2 = READ_REG32(CM_EFM->UQID2); + } +} + +/** + * @brief Get wafer ID. + * @param None + * @retval uint8_t Returns the value of the wafer ID + */ +uint8_t EFM_GetWaferID(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_EFM->UQID0, EFM_UQID0_WAFER_ID) >> EFM_UQID0_WAFER_ID_POS); +} + +/** + * @brief Get wafer location (x.y). + * @param [out] pstcLocation Wafer coordinate. + * @retval Returns the wafer coordinate + */ +void EFM_GetLocation(stc_efm_location_t *pstcLocation) +{ + if (NULL != pstcLocation) { + pstcLocation->u8X_Location = (uint8_t)(READ_REG32_BIT(CM_EFM->UQID0, EFM_UQID0_X_LOCATION) \ + >> EFM_UQID0_X_LOCATION_POS); + pstcLocation->u8Y_Location = (uint8_t)(READ_REG32_BIT(CM_EFM->UQID0, EFM_UQID0_Y_LOCATION)); + } +} + +/** + * @brief Get LOT ID. + * @param None + * @retval uint64_t Returns the value of the LOT ID + */ +uint64_t EFM_GetLotID(void) +{ + uint64_t u64LotID; + uint32_t u32LotID0; + u32LotID0 = READ_REG32_BIT(CM_EFM->UQID0, EFM_UQID0_LOT_ID) >> EFM_UQID0_LOT_ID_POS; + u64LotID = ((uint64_t)READ_REG32(CM_EFM->UQID1) << 8U) | u32LotID0; + u64LotID = u64LotID | ((uint64_t)((uint8_t)READ_REG32_BIT(CM_EFM->UQID2, EFM_UQID2_LOT_ID)) << 40U); + + return u64LotID; +} + +/** + * @brief Init REMAP initial structure with default value. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_StructInit(stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcEfmRemapInit->u32State = EFM_REMAP_OFF; + pstcEfmRemapInit->u32Addr = 0UL; + pstcEfmRemapInit->u32Size = EFM_REMAP_4K; + } + return i32Ret; +} + +/** + * @brief REMAP initialize. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] pstcEfmRemapInit specifies the Parameter of REMAP. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EFM_REMAP_Init(uint8_t u8RemapIdx, stc_efm_remap_init_t *pstcEfmRemapInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *REMCRx; + + if (NULL == pstcEfmRemapInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(pstcEfmRemapInit->u32Size)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(pstcEfmRemapInit->u32Addr)); + DDL_ASSERT(IS_EFM_REMAP_STATE(pstcEfmRemapInit->u32State)); + if ((pstcEfmRemapInit->u32Addr % (1UL << pstcEfmRemapInit->u32Size)) != 0U) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_EN | EFM_MMF_REMCR_RMTADDR | EFM_MMF_REMCR_RMSIZE, \ + pstcEfmRemapInit->u32State | pstcEfmRemapInit->u32Addr | pstcEfmRemapInit->u32Size); + } + } + return i32Ret; +} + +/** + * @brief EFM REMAP de-initialize. + * @param None + * @retval None + */ +void EFM_REMAP_DeInit(void) +{ + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + + WRITE_REG32(CM_EFM->MMF_REMCR0, 0UL); + WRITE_REG32(CM_EFM->MMF_REMCR1, 0UL); +} + +/** + * @brief Enable or disable REMAP function. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EFM_REMAP_Cmd(uint8_t u8RemapIdx, en_functional_state_t enNewState) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + REMCRx = &REMCR_REG(u8RemapIdx); + if (ENABLE == enNewState) { + SET_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } else { + CLR_REG32_BIT(*REMCRx, EFM_MMF_REMCR_EN); + } +} + +/** + * @brief Set specified REMAP target address. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Addr Specifies the target address. + * @retval None + */ +void EFM_REMAP_SetAddr(uint8_t u8RemapIdx, uint32_t u32Addr) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_ADDR(u32Addr)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMTADDR, u32Addr); +} + +/** + * @brief Set specified REMAP size. + * @param [in] u8RemapIdx Specifies the remap ID. + * @param [in] u32Size Specifies the remap size. + * @retval None + */ +void EFM_REMAP_SetSize(uint8_t u8RemapIdx, uint32_t u32Size) +{ + __IO uint32_t *REMCRx; + + DDL_ASSERT(IS_EFM_REMAP_UNLOCK()); + DDL_ASSERT(IS_EFM_REMAP_IDX(u8RemapIdx)); + DDL_ASSERT(IS_EFM_REMAP_SIZE(u32Size)); + + REMCRx = &REMCR_REG(u8RemapIdx); + MODIFY_REG32(*REMCRx, EFM_MMF_REMCR_RMSIZE, u32Size); +} + +/** + * @brief Enable efm protect. + * @param [in] u8Level Specifies the protect level. @ref EFM_Protect_Level + * @retval None + */ +void EFM_Protect_Enable(uint8_t u8Level) +{ + + if (SET == EFM_GetSwapStatus()) { + (void)EFM_SingleSectorOperateCmd(EFM_SWAP_ON_PROTECT_SECTOR_NUM, ENABLE); + } else { + (void)EFM_SingleSectorOperateCmd(0U, ENABLE); + } + if (EFM_PROTECT_LEVEL1 == u8Level) { + (void)EFM_ProgramWord(EFM_PROTECT1_ADDR, EFM_PROTECT1_KEY); + } else if (EFM_PROTECT_LEVEL2 == u8Level) { + (void)EFM_ProgramWord(EFM_PROTECT2_ADDR, EFM_PROTECT2_KEY); + } else if (EFM_PROTECT_LEVEL3 == u8Level) { + (void)EFM_ProgramWord(EFM_PROTECT3_ADDR1, EFM_PROTECT3_KEY); + (void)EFM_ProgramWord(EFM_PROTECT3_ADDR2, EFM_PROTECT3_KEY); + (void)EFM_ProgramWord(EFM_PROTECT3_ADDR3, EFM_PROTECT3_KEY); + } else { + /* rsvd */ + } +} + +/** + * @brief Write the security code. + * @param [in] pu8Buf Specifies the security code. + * @param [in] u32Len Specified the length of the security code. + * @retval int32_t + */ +int32_t EFM_WriteSecurityCode(uint8_t *pu8Buf, uint32_t u32Len) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t *u32pSource = (uint32_t *)(uint32_t)pu8Buf; + uint32_t *u32pDest = (uint32_t *)EFM_SECURITY_ADDR; + + DDL_ASSERT(IS_EFM_REG_UNLOCK()); + DDL_ASSERT(IS_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_EFM_SECURITY_CODE_LEN(u32Len)); + + /* CLear the error flag. */ + EFM_ClearStatus(EFM_FLAG_ALL); + /* Get CACHE status */ + u32Tmp = READ_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + /* Disable CACHE */ + CLR_REG32_BIT(CM_EFM->FRMC, EFM_CACHE_ALL); + + /* Set sector erase mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_ERASE_SECTOR); + /* Erase */ + RW_MEM32(EFM_SECURITY_ADDR) = 0UL; + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + + /* Set single program mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_PGM_SINGLE); + + while (u32LoopWords-- > 0UL) { + /* program data. */ + *u32pDest++ = *u32pSource++; + /* Wait for ready flag. */ + if (LL_ERR_TIMEOUT == EFM_WaitFlag(EFM_FLAG_RDY, EFM_PGM_TIMEOUT)) { + i32Ret = LL_ERR_NOT_RDY; + } + /* CLear the operation end flag. */ + EFM_ClearStatus(EFM_FLAG_OPTEND); + } + + /* Set read only mode. */ + MODIFY_REG32(CM_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MD_READONLY); + + /* Recover CACHE function */ + MODIFY_REG32(CM_EFM->FRMC, EFM_CACHE_ALL, u32Tmp); + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_EFM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c new file mode 100644 index 0000000000..3540a0ba2a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_emb.c @@ -0,0 +1,696 @@ +/** + ******************************************************************************* + * @file hc32_ll_emb.c + * @brief This file provides firmware functions to manage the EMB + * (Emergency Brake). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Function EMB_TMR4_Init don't call EMB_DeInit + Function EMB_TMR6_Init don't call EMB_DeInit + 2023-12-15 CDT Modify stc_emb_monitor_sys_t structure relevant code + Modify API EMB_ClearStatus assert + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_emb.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EMB EMB + * @brief Emergency Brake Driver Library + * @{ + */ + +#if (LL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Local_Macros EMB Local Macros + * @{ + */ + +/** + * @defgroup EMB_Check_Parameters_Validity EMB Check Parameters Validity + * @{ + */ +#define IS_EMB_GROUP(x) \ +( ((x) == CM_EMB0) || \ + ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3)) +#define IS_EMB_TMR4_GROUP(x) \ +( ((x) == CM_EMB1) || \ + ((x) == CM_EMB2) || \ + ((x) == CM_EMB3)) +#define IS_EMB_TMR6_GROUP(x) ((x) == CM_EMB0) + +#define IS_EMB_OSC_STAT(x) \ +( ((x) == EMB_OSC_ENABLE) || \ + ((x) == EMB_OSC_DISABLE)) + +#define IS_EMB_SRAM_ECC_ERR_STAT(x) \ +( ((x) == EMB_SRAM_ECC_ERR_ENABLE) || \ + ((x) == EMB_SRAM_ECC_ERR_DISABLE)) + +#define IS_EMB_SRAM_PARITY_ERR_STAT(x) \ +( ((x) == EMB_SRAM_PARITY_ERR_ENABLE) || \ + ((x) == EMB_SRAM_PARITY_ERR_DISABLE)) + +#define IS_EMB_LOCKUP_STAT(x) \ +( ((x) == EMB_LOCKUP_ENABLE) || \ + ((x) == EMB_LOCKUP_DISABLE)) + +#define IS_EMB_LVD_STAT(x) \ +( ((x) == EMB_LVD_ENABLE) || \ + ((x) == EMB_LVD_DISABLE)) + +#define IS_EMB_TMR4_PWM_X_STAT(x) \ +( ((x) == EMB_TMR4_PWM_X_ENABLE) || \ + ((x) == EMB_TMR4_PWM_X_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_X_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_X_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_X_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_W_STAT(x) \ +( ((x) == EMB_TMR4_PWM_W_ENABLE) || \ + ((x) == EMB_TMR4_PWM_W_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_W_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_V_STAT(x) \ +( ((x) == EMB_TMR4_PWM_V_ENABLE) || \ + ((x) == EMB_TMR4_PWM_V_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_V_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_HIGH)) + +#define IS_EMB_TMR4_PWM_U_STAT(x) \ +( ((x) == EMB_TMR4_PWM_U_ENABLE) || \ + ((x) == EMB_TMR4_PWM_U_DISABLE)) + +#define IS_EMB_DETECT_TMR4_PWM_U_LVL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_HIGH)) + +#define IS_EMB_CMP1_STAT(x) \ +( ((x) == EMB_CMP1_ENABLE) || \ + ((x) == EMB_CMP1_DISABLE)) + +#define IS_EMB_CMP2_STAT(x) \ +( ((x) == EMB_CMP2_ENABLE) || \ + ((x) == EMB_CMP2_DISABLE)) + +#define IS_EMB_CMP3_STAT(x) \ +( ((x) == EMB_CMP3_ENABLE) || \ + ((x) == EMB_CMP3_DISABLE)) + +#define IS_EMB_CMP4_STAT(x) \ +( ((x) == EMB_CMP4_ENABLE) || \ + ((x) == EMB_CMP4_DISABLE)) + +#define IS_EMB_PORT1_STAT(x) \ +( ((x) == EMB_PORT1_ENABLE) || \ + ((x) == EMB_PORT1_DISABLE)) + +#define IS_EMB_PORT1_DETECT_LVL(x) \ +( ((x) == EMB_PORT1_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT1_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT1_FILTER_STAT(x) \ +( ((x) == EMB_PORT1_FILTER_ENABLE) || \ + ((x) == EMB_PORT1_FILTER_DISABLE)) + +#define IS_EMB_PORT1_FILTER_DIV(x) (((x) & (~EMB_PORT1_FILTER_CLK_DIV_MASK)) == 0UL) +#define IS_EMB_PORT2_STAT(x) \ +( ((x) == EMB_PORT2_ENABLE) || \ + ((x) == EMB_PORT2_DISABLE)) + +#define IS_EMB_PORT2_DETECT_LVL(x) \ +( ((x) == EMB_PORT2_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT2_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT2_FILTER_STAT(x) \ +( ((x) == EMB_PORT2_FILTER_ENABLE) || \ + ((x) == EMB_PORT2_FILTER_DISABLE)) + +#define IS_EMB_PORT2_FILTER_DIV(x) (((x) & (~EMB_PORT2_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_PORT3_STAT(x) \ +( ((x) == EMB_PORT3_ENABLE) || \ + ((x) == EMB_PORT3_DISABLE)) + +#define IS_EMB_PORT3_DETECT_LVL(x) \ +( ((x) == EMB_PORT3_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT3_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT3_FILTER_STAT(x) \ +( ((x) == EMB_PORT3_FILTER_ENABLE) || \ + ((x) == EMB_PORT3_FILTER_DISABLE)) + +#define IS_EMB_PORT3_FILTER_DIV(x) (((x) & (~EMB_PORT3_FILTER_CLK_DIV_MASK)) == 0UL) +#define IS_EMB_PORT4_STAT(x) \ +( ((x) == EMB_PORT4_ENABLE) || \ + ((x) == EMB_PORT4_DISABLE)) + +#define IS_EMB_PORT4_DETECT_LVL(x) \ +( ((x) == EMB_PORT4_DETECT_LVL_LOW) || \ + ((x) == EMB_PORT4_DETECT_LVL_HIGH)) + +#define IS_EMB_PORT4_FILTER_STAT(x) \ +( ((x) == EMB_PORT4_FILTER_ENABLE) || \ + ((x) == EMB_PORT4_FILTER_DISABLE)) + +#define IS_EMB_PORT4_FILTER_DIV(x) (((x) & (~EMB_PORT4_FILTER_CLK_DIV_MASK)) == 0UL) + +#define IS_EMB_TMR6_1_PWM_STAT(x) \ +( ((x) == EMB_TMR6_1_PWM_ENABLE) || \ + ((x) == EMB_TMR6_1_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_1_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_HIGH)) + +#define IS_EMB_TMR6_2_PWM_STAT(x) \ +( ((x) == EMB_TMR6_2_PWM_ENABLE) || \ + ((x) == EMB_TMR6_2_PWM_DISABLE)) + +#define IS_EMB_DETECT_TMR6_2_PWM_LVL(x) \ +( ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_INT(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_INT_ALL) == EMB_INT_ALL)) + +#define IS_EMB_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_FLAG_ALL) == EMB_FLAG_ALL)) + +#define IS_EMB_CLR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | EMB_FLAG_CLR_ALL) == EMB_FLAG_CLR_ALL)) + +#define IS_EMB_RELEASE_PWM_COND(x) \ +( ((x) == EMB_RELEASE_PWM_COND_FLAG_ZERO) || \ + ((x) == EMB_RELEASE_PWM_COND_STAT_ZERO)) + +#define IS_EMB_MONITOR_EVT(x) \ +( ((x) == EMB_EVT_PWMS) || \ + ((x) == EMB_EVT_CMP) || \ + ((x) == EMB_EVT_SYS) || \ + ((x) == EMB_EVT_PORT1) || \ + ((x) == EMB_EVT_PORT2) || \ + ((x) == EMB_EVT_PORT3) || \ + ((x) == EMB_EVT_PORT4)) + +/** + * @} + */ + +#define EMB_PORT1_FILTER_CLK_DIV_MASK EMB_PORT1_FILTER_CLK_DIV128 +#define EMB_PORT2_FILTER_CLK_DIV_MASK EMB_PORT2_FILTER_CLK_DIV128 +#define EMB_PORT3_FILTER_CLK_DIV_MASK EMB_PORT3_FILTER_CLK_DIV128 +#define EMB_PORT4_FILTER_CLK_DIV_MASK EMB_PORT4_FILTER_CLK_DIV128 +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EMB_Global_Functions EMB Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_emb_tmr4_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_StructInit(stc_emb_tmr4_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + pstcEmbInit->stcCmp.u32Cmp4State = EMB_CMP4_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortState = EMB_PORT2_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortLevel = EMB_PORT2_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort2.u32PortFilterState = EMB_PORT2_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortState = EMB_PORT3_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortLevel = EMB_PORT3_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort3.u32PortFilterState = EMB_PORT3_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortState = EMB_PORT4_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortLevel = EMB_PORT4_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort4.u32PortFilterState = EMB_PORT4_FILTER_DISABLE; + + /* PWM */ + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState = EMB_TMR4_PWM_U_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel = EMB_DETECT_TMR4_PWM_U_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState = EMB_TMR4_PWM_V_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel = EMB_DETECT_TMR4_PWM_V_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState = EMB_TMR4_PWM_W_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel = EMB_DETECT_TMR4_PWM_W_BOTH_LOW; + pstcEmbInit->stcTmr4.stcTmr4PwmX.u32PwmState = EMB_TMR4_PWM_X_DISABLE; + pstcEmbInit->stcTmr4.stcTmr4PwmX.u32PwmLevel = EMB_DETECT_TMR4_PWM_X_BOTH_LOW; + + /* System */ + pstcEmbInit->stcSys.u32Osc = EMB_OSC_DISABLE; + pstcEmbInit->stcSys.u32SramEccError = EMB_SRAM_ECC_ERR_DISABLE; + pstcEmbInit->stcSys.u32SramParityError = EMB_SRAM_PARITY_ERR_DISABLE; + pstcEmbInit->stcSys.u32Lockup = EMB_LOCKUP_DISABLE; + pstcEmbInit->stcSys.u32Lvd = EMB_LVD_DISABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR4. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR4_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr4_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR4_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_CMP4_STAT(pstcEmbInit->stcCmp.u32Cmp4State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT2_STAT(pstcEmbInit->stcPort.stcPort2.u32PortState)); + DDL_ASSERT(IS_EMB_PORT2_DETECT_LVL(pstcEmbInit->stcPort.stcPort2.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_DIV(pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_STAT(pstcEmbInit->stcPort.stcPort2.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT3_STAT(pstcEmbInit->stcPort.stcPort3.u32PortState)); + DDL_ASSERT(IS_EMB_PORT3_DETECT_LVL(pstcEmbInit->stcPort.stcPort3.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_DIV(pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_STAT(pstcEmbInit->stcPort.stcPort3.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT4_STAT(pstcEmbInit->stcPort.stcPort4.u32PortState)); + DDL_ASSERT(IS_EMB_PORT4_DETECT_LVL(pstcEmbInit->stcPort.stcPort4.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_DIV(pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_STAT(pstcEmbInit->stcPort.stcPort4.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR4_PWM_U_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_U_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_V_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_V_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_W_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_W_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR4_PWM_X_STAT(pstcEmbInit->stcTmr4.stcTmr4PwmX.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR4_PWM_X_LVL(pstcEmbInit->stcTmr4.stcTmr4PwmX.u32PwmLevel)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcSys.u32Osc)); + DDL_ASSERT(IS_EMB_SRAM_ECC_ERR_STAT(pstcEmbInit->stcSys.u32SramEccError)); + DDL_ASSERT(IS_EMB_SRAM_PARITY_ERR_STAT(pstcEmbInit->stcSys.u32SramParityError)); + DDL_ASSERT(IS_EMB_LOCKUP_STAT(pstcEmbInit->stcSys.u32Lockup)); + DDL_ASSERT(IS_EMB_LVD_STAT(pstcEmbInit->stcSys.u32Lvd)); + + u32Reg2Value = 0UL; + + /* PWM */ + u32Reg1Value = (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmState | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmState | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmState | pstcEmbInit->stcTmr4.stcTmr4PwmX.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr4.stcTmr4PwmU.u32PwmLevel | pstcEmbInit->stcTmr4.stcTmr4PwmV.u32PwmLevel | \ + pstcEmbInit->stcTmr4.stcTmr4PwmW.u32PwmLevel | pstcEmbInit->stcTmr4.stcTmr4PwmX.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \ + pstcEmbInit->stcCmp.u32Cmp3State | pstcEmbInit->stcCmp.u32Cmp4State); + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort2.u32PortState | pstcEmbInit->stcPort.stcPort2.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort3.u32PortState | pstcEmbInit->stcPort.stcPort3.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort4.u32PortState | pstcEmbInit->stcPort.stcPort4.u32PortLevel); + u32Reg2Value |= (pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort2.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort3.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort4.u32PortFilterState); + + /* System */ + u32Reg1Value |= (pstcEmbInit->stcSys.u32Osc | pstcEmbInit->stcSys.u32SramEccError | \ + pstcEmbInit->stcSys.u32Lockup | pstcEmbInit->stcSys.u32SramParityError | \ + pstcEmbInit->stcSys.u32Lvd); + if ((pstcEmbInit->stcSys.u32Osc != 0UL) || (pstcEmbInit->stcSys.u32SramParityError != 0UL) || \ + (pstcEmbInit->stcSys.u32SramEccError != 0UL) || (pstcEmbInit->stcSys.u32Lockup != 0UL) || \ + (pstcEmbInit->stcSys.u32Lvd != 0UL)) { + u32Reg1Value |= EMB_CTL1_SYSEN; + } + + WRITE_REG32(EMBx->CTL2, u32Reg2Value); + WRITE_REG32(EMBx->CTL1, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_emb_tmr6_init_t to default values + * @param [out] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_StructInit(stc_emb_tmr6_init_t *pstcEmbInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + + /* CMP */ + pstcEmbInit->stcCmp.u32Cmp1State = EMB_CMP1_DISABLE; + pstcEmbInit->stcCmp.u32Cmp2State = EMB_CMP2_DISABLE; + pstcEmbInit->stcCmp.u32Cmp3State = EMB_CMP3_DISABLE; + pstcEmbInit->stcCmp.u32Cmp4State = EMB_CMP4_DISABLE; + + /* Port */ + pstcEmbInit->stcPort.stcPort1.u32PortState = EMB_PORT1_DISABLE; + pstcEmbInit->stcPort.stcPort1.u32PortLevel = EMB_PORT1_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort1.u32PortFilterState = EMB_PORT1_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortState = EMB_PORT2_DISABLE; + pstcEmbInit->stcPort.stcPort2.u32PortLevel = EMB_PORT2_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort2.u32PortFilterState = EMB_PORT2_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortState = EMB_PORT3_DISABLE; + pstcEmbInit->stcPort.stcPort3.u32PortLevel = EMB_PORT3_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort3.u32PortFilterState = EMB_PORT3_FILTER_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortState = EMB_PORT4_DISABLE; + pstcEmbInit->stcPort.stcPort4.u32PortLevel = EMB_PORT4_DETECT_LVL_HIGH; + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_CLK_DIV1; + pstcEmbInit->stcPort.stcPort4.u32PortFilterState = EMB_PORT4_FILTER_DISABLE; + /* PWM */ + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel = EMB_DETECT_TMR6_1_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState = EMB_TMR6_1_PWM_DISABLE; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel = EMB_DETECT_TMR6_2_PWM_BOTH_LOW; + pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState = EMB_TMR6_2_PWM_DISABLE; + + /* System */ + pstcEmbInit->stcSys.u32Osc = EMB_OSC_DISABLE; + pstcEmbInit->stcSys.u32SramEccError = EMB_SRAM_ECC_ERR_DISABLE; + pstcEmbInit->stcSys.u32SramParityError = EMB_SRAM_PARITY_ERR_DISABLE; + pstcEmbInit->stcSys.u32Lockup = EMB_LOCKUP_DISABLE; + pstcEmbInit->stcSys.u32Lvd = EMB_LVD_DISABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EMB for TMR6. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] pstcEmbInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcEmbInit value is NULL. + */ +int32_t EMB_TMR6_Init(CM_EMB_TypeDef *EMBx, const stc_emb_tmr6_init_t *pstcEmbInit) +{ + uint32_t u32Reg1Value; + uint32_t u32Reg2Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcEmbInit) { + DDL_ASSERT(IS_EMB_TMR6_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_CMP1_STAT(pstcEmbInit->stcCmp.u32Cmp1State)); + DDL_ASSERT(IS_EMB_CMP2_STAT(pstcEmbInit->stcCmp.u32Cmp2State)); + DDL_ASSERT(IS_EMB_CMP3_STAT(pstcEmbInit->stcCmp.u32Cmp3State)); + DDL_ASSERT(IS_EMB_CMP4_STAT(pstcEmbInit->stcCmp.u32Cmp4State)); + DDL_ASSERT(IS_EMB_PORT1_STAT(pstcEmbInit->stcPort.stcPort1.u32PortState)); + DDL_ASSERT(IS_EMB_PORT1_DETECT_LVL(pstcEmbInit->stcPort.stcPort1.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_DIV(pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT1_FILTER_STAT(pstcEmbInit->stcPort.stcPort1.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT2_STAT(pstcEmbInit->stcPort.stcPort2.u32PortState)); + DDL_ASSERT(IS_EMB_PORT2_DETECT_LVL(pstcEmbInit->stcPort.stcPort2.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_DIV(pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT2_FILTER_STAT(pstcEmbInit->stcPort.stcPort2.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT3_STAT(pstcEmbInit->stcPort.stcPort3.u32PortState)); + DDL_ASSERT(IS_EMB_PORT3_DETECT_LVL(pstcEmbInit->stcPort.stcPort3.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_DIV(pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT3_FILTER_STAT(pstcEmbInit->stcPort.stcPort3.u32PortFilterState)); + DDL_ASSERT(IS_EMB_PORT4_STAT(pstcEmbInit->stcPort.stcPort4.u32PortState)); + DDL_ASSERT(IS_EMB_PORT4_DETECT_LVL(pstcEmbInit->stcPort.stcPort4.u32PortLevel)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_DIV(pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv)); + DDL_ASSERT(IS_EMB_PORT4_FILTER_STAT(pstcEmbInit->stcPort.stcPort4.u32PortFilterState)); + DDL_ASSERT(IS_EMB_TMR6_1_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_1_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel)); + DDL_ASSERT(IS_EMB_TMR6_2_PWM_STAT(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState)); + DDL_ASSERT(IS_EMB_DETECT_TMR6_2_PWM_LVL(pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel)); + DDL_ASSERT(IS_EMB_OSC_STAT(pstcEmbInit->stcSys.u32Osc)); + DDL_ASSERT(IS_EMB_SRAM_ECC_ERR_STAT(pstcEmbInit->stcSys.u32SramEccError)); + DDL_ASSERT(IS_EMB_SRAM_PARITY_ERR_STAT(pstcEmbInit->stcSys.u32SramParityError)); + DDL_ASSERT(IS_EMB_LOCKUP_STAT(pstcEmbInit->stcSys.u32Lockup)); + DDL_ASSERT(IS_EMB_LVD_STAT(pstcEmbInit->stcSys.u32Lvd)); + + u32Reg2Value = 0UL; + + /* PWM */ + u32Reg1Value = (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmState | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmState); + u32Reg2Value |= (pstcEmbInit->stcTmr6.stcTmr6_1.u32PwmLevel | pstcEmbInit->stcTmr6.stcTmr6_2.u32PwmLevel); + + /* CMP */ + u32Reg1Value |= (pstcEmbInit->stcCmp.u32Cmp1State | pstcEmbInit->stcCmp.u32Cmp2State | \ + pstcEmbInit->stcCmp.u32Cmp3State | pstcEmbInit->stcCmp.u32Cmp4State); + + /* PORT */ + u32Reg1Value |= (pstcEmbInit->stcPort.stcPort1.u32PortState | pstcEmbInit->stcPort.stcPort1.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort2.u32PortState | pstcEmbInit->stcPort.stcPort2.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort3.u32PortState | pstcEmbInit->stcPort.stcPort3.u32PortLevel | \ + pstcEmbInit->stcPort.stcPort4.u32PortState | pstcEmbInit->stcPort.stcPort4.u32PortLevel); + u32Reg2Value |= (pstcEmbInit->stcPort.stcPort1.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort1.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort2.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort2.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort3.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort3.u32PortFilterState | \ + pstcEmbInit->stcPort.stcPort4.u32PortFilterDiv | pstcEmbInit->stcPort.stcPort4.u32PortFilterState); + + u32Reg1Value |= (pstcEmbInit->stcSys.u32Osc | pstcEmbInit->stcSys.u32SramEccError | \ + pstcEmbInit->stcSys.u32Lockup | pstcEmbInit->stcSys.u32SramParityError | \ + pstcEmbInit->stcSys.u32Lvd); + if ((pstcEmbInit->stcSys.u32Osc != 0UL) || (pstcEmbInit->stcSys.u32SramParityError != 0UL) || \ + (pstcEmbInit->stcSys.u32SramEccError != 0UL) || (pstcEmbInit->stcSys.u32Lockup != 0UL) || \ + (pstcEmbInit->stcSys.u32Lvd != 0UL)) { + u32Reg1Value |= EMB_CTL1_SYSEN; + } + + WRITE_REG32(EMBx->CTL2, u32Reg2Value); + WRITE_REG32(EMBx->CTL1, u32Reg1Value); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EMB function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @retval None + */ +void EMB_DeInit(CM_EMB_TypeDef *EMBx) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + + WRITE_REG32(EMBx->SOE, 0x00UL); + WRITE_REG32(EMBx->INTEN, 0x00UL); + WRITE_REG32(EMBx->RLSSEL, 0x00UL); +} + +/** + * @brief Set the EMB interrupt function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32IntType EMB interrupt source + * This parameter can be any composed value of the macros group @ref EMB_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_IntCmd(CM_EMB_TypeDef *EMBx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_VALID_EMB_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(EMBx->INTEN, u32IntType); + } else { + CLR_REG32_BIT(EMBx->INTEN, u32IntType); + } +} + +/** + * @brief Clear EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value(prefix with EMB_FLAG) of the macros group @ref EMB_Flag_State. + * @retval None + * @note This parameter u32Flag prefix with EMB_FLAG(eg EMB_FLAG_CMP) of the macros group @ref EMB_Flag_State. + */ +void EMB_ClearStatus(CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_CLR_FLAG(u32Flag)); + + SET_REG32_BIT(EMBx->STATCLR, u32Flag); +} + +/** + * @brief Get EMB flag status. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Flag EMB flag + * This parameter can be any composed value of the macros group @ref EMB_Flag_State. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EMB_GetStatus(const CM_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_FLAG(u32Flag)); + + return (READ_REG32_BIT(EMBx->STAT, u32Flag) == 0UL) ? RESET : SET; +} + +/** + * @brief Start/stop EMB brake by software control + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EMB_SWBrake(CM_EMB_TypeDef *EMBx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(EMBx->SOE, enNewState); +} + +/** + * @brief Set EMB release PWM condition for the specified event. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg CM_EMBx: EMB group instance register base + * @param [in] u32Event Monitor event + * This parameter can be any composed value of the macros group @ref EMB_Monitor_Event. + * @param [in] u32Cond Release PWM condition + * This parameter can be one of the macros group @ref EMB_Release_TMR_PWM_Condition + * @arg EMB_RELEASE_PWM_COND_FLAG_ZERO: Release PWM when flag bit of the specified event is zero + * @arg EMB_RELEASE_PWM_COND_STAT_ZERO: Release PWM when state bit of the specified event is zero + * @retval None + */ +void EMB_SetReleasePwmCond(CM_EMB_TypeDef *EMBx, uint32_t u32Event, uint32_t u32Cond) +{ + DDL_ASSERT(IS_EMB_GROUP(EMBx)); + DDL_ASSERT(IS_EMB_MONITOR_EVT(u32Event)); + DDL_ASSERT(IS_EMB_RELEASE_PWM_COND(u32Cond)); + + if (EMB_RELEASE_PWM_COND_FLAG_ZERO == u32Cond) { + CLR_REG32_BIT(EMBx->RLSSEL, u32Event); + } else { + SET_REG32_BIT(EMBx->RLSSEL, u32Event); + } +} + +/** + * @} + */ + +#endif /* LL_EMB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c new file mode 100644 index 0000000000..a51b860699 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_event_port.c @@ -0,0 +1,442 @@ +/** + ******************************************************************************* + * @file hc32_ll_event_port.c + * @brief This file provides firmware functions to manage the Event Port (EP). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_event_port.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EVENT_PORT EVENT_PORT + * @brief Event Port Driver Library + * @{ + */ + +#if (LL_EVENT_PORT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EP_Local_Macros Event Port Local Macros + * @{ + */ +#define EP_OFFSET (0x1CUL) +#define PEVNTDIR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTDIRR1) + (EP_OFFSET * (x)))) +#define PEVNTIDR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTIDR1) + (EP_OFFSET * (x)))) +#define PEVNTODR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTODR1) + (EP_OFFSET * (x)))) +#define PEVNTORR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTORR1) + (EP_OFFSET * (x)))) +#define PEVNTOSR_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTOSR1) + (EP_OFFSET * (x)))) +#define PEVNTRIS_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTRISR1) + (EP_OFFSET * (x)))) +#define PEVNTFAL_REG(x) (*(__IO uint32_t *)((uint32_t)(&CM_AOS->PEVNTFALR1) + (EP_OFFSET * (x)))) +#define PEVNTTRGSR_RST_VALUE (0x1FFUL) +#define EP_PIN_MAX (16U) + +/** + * @defgroup EP_Check_Parameters_Validity Event Port Check Parameters Validity + * @{ + */ +/*! Parameter validity check for port group. */ +#define IS_EVENT_PORT(port) \ +( ((port) == EVT_PORT_1) || \ + ((port) == EVT_PORT_2) || \ + ((port) == EVT_PORT_3) || \ + ((port) == EVT_PORT_4)) + +/*! Parameter valid check for event port trigger edge. */ +#define IS_EP_TRIG_EDGE(edge) \ +( ((edge) == EP_TRIG_NONE) || \ + ((edge) == EP_TRIG_FALLING) || \ + ((edge) == EP_TRIG_RISING) || \ + ((edge) == EP_TRIG_BOTH)) + +/*! Parameter valid check for event port initial output state. */ +#define IS_EP_STATE(state) \ +( ((state) == EVT_PIN_RESET) || \ + ((state) == EVT_PIN_SET)) + +/*! Parameter valid check for event port filter function. */ +#define IS_EP_FILTER(filter) \ +( ((filter) == EP_FILTER_OFF) || \ + ((filter) == EP_FILTER_ON)) + +/*! Parameter validity check for pin. */ +#define IS_EVENT_PIN(pin) (((pin) & EVT_PIN_MASK ) != 0x0000U) + +/*! Parameter valid check for event port operation after triggered. */ +#define IS_EP_OPS(ops) \ +( ((ops) == EP_OPS_NONE) || \ + ((ops) == EP_OPS_LOW) || \ + ((ops) == EP_OPS_HIGH) || \ + ((ops) == EP_OPS_TOGGLE)) + +/*! Parameter valid check for event port direction. */ +#define IS_EP_DIR(dir) \ +( ((dir) == EP_DIR_IN) || \ + ((dir) == EP_DIR_OUT)) + +/*! Parameter valid check for event port filter clock div. */ +#define IS_EP_FILTER_CLK(clk) \ +( ((clk) == EP_FCLK_DIV1) || \ + ((clk) == EP_FCLK_DIV8) || \ + ((clk) == EP_FCLK_DIV32) || \ + ((clk) == EP_FCLK_DIV64)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EP_Global_Functions Event Port Global Functions + * @{ + */ + +/** + * @brief Initialize Event Port. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] pstcEventPortInit Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_Init(uint8_t u8EventPort, uint16_t u16EventPin, const stc_ep_init_t *pstcEventPortInit) +{ + uint16_t u16PinPos; + int32_t i32Ret = LL_OK; + + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(pstcEventPortInit->u32PinTriggerOps)); + DDL_ASSERT(IS_EP_DIR(pstcEventPortInit->u32PinDir)); + DDL_ASSERT(IS_EP_STATE(pstcEventPortInit->enPinState)); + DDL_ASSERT(IS_EP_TRIG_EDGE(pstcEventPortInit->u32Edge)); + DDL_ASSERT(IS_EP_FILTER(pstcEventPortInit->u32Filter)); + DDL_ASSERT(IS_EP_FILTER_CLK(pstcEventPortInit->u32FilterClock)); + + for (u16PinPos = 0U; u16PinPos < EP_PIN_MAX; u16PinPos++) { + if ((u16EventPin & (1UL << u16PinPos)) != 0U) { + /* Direction config */ + if (EP_DIR_OUT == pstcEventPortInit->u32PinDir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } + /* Set pin initial output value */ + if (EVT_PIN_SET == pstcEventPortInit->enPinState) { + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); + } + /* Set Pin operation after triggered */ + (void)EP_SetTriggerOps(u8EventPort, u16EventPin, pstcEventPortInit->u32PinTriggerOps); + /* Set trigger edge */ + (void)EP_SetTriggerEdge(u8EventPort, u16EventPin, pstcEventPortInit->u32Edge); + } + MODIFY_REG32(CM_AOS->PEVNTNFCR, \ + ((AOS_PEVNTNFCR_NFEN1 | AOS_PEVNTNFCR_DIVS1) << (u8EventPort * 8UL)), \ + ((pstcEventPortInit->u32Filter | pstcEventPortInit->u32FilterClock) << (u8EventPort * 8UL))); + } + } + return i32Ret; +} + +/** + * @brief De-init Event Port register to default value + * @param None + * @retval None + */ +void EP_DeInit(void) +{ + uint8_t u8EventPort; + + /* Restore all registers to default value */ + WRITE_REG32(CM_AOS->PEVNT_TRGSEL12, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNT_TRGSEL34, PEVNTTRGSR_RST_VALUE); + WRITE_REG32(CM_AOS->PEVNTNFCR, 0UL); + for (u8EventPort = EVT_PORT_1; u8EventPort < EVT_PORT_4; u8EventPort++) { + WRITE_REG32(PEVNTDIR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTODR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTORR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTOSR_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTRIS_REG(u8EventPort), 0UL); + WRITE_REG32(PEVNTFAL_REG(u8EventPort), 0UL); + } +} + +/** + * @brief Initialize Event Port config structure. Fill each pstcEventPortInit with default value + * @param [in] pstcEventPortInit: Pointer to a stc_ep_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Event Port structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EP_StructInit(stc_ep_init_t *pstcEventPortInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcEventPortInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset Event Port init structure parameters values */ + pstcEventPortInit->u32PinDir = EP_DIR_IN; + pstcEventPortInit->enPinState = EVT_PIN_RESET; + pstcEventPortInit->u32PinTriggerOps = EP_OPS_NONE; + pstcEventPortInit->u32Edge = EP_TRIG_NONE; + pstcEventPortInit->u32Filter = EP_FILTER_OFF; + pstcEventPortInit->u32FilterClock = EP_FCLK_DIV1; + } + return i32Ret; +} + +/** + * @brief Set event port trigger edge. + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP port peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Edge: Trigger edge, @ref EP_Trigger_Sel for details + * @retval int32_t: + * - LL_OK: Trigger edge set successful + * - LL_ERR_INVD_PARAM: Undefined edge + */ +int32_t EP_SetTriggerEdge(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Edge) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_TRIG_EDGE(u32Edge)); + + /* Set trigger edge */ + switch (u32Edge) { + case EP_TRIG_NONE: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_FALLING: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_RISING: + CLR_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + case EP_TRIG_BOTH: + SET_REG32_BIT(PEVNTFAL_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTRIS_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Set event port operation after triggered + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Ops: The operation after triggered, @ref EP_TriggerOps_Sel for details + * @retval Specified Event port pin input value + */ +int32_t EP_SetTriggerOps(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Ops) +{ + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_OPS(u32Ops)); + + switch (u32Ops) { + case EP_OPS_NONE: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_LOW: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + CLR_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_HIGH: + CLR_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + case EP_OPS_TOGGLE: + SET_REG32_BIT(PEVNTORR_REG(u8EventPort), u16EventPin); + SET_REG32_BIT(PEVNTOSR_REG(u8EventPort), u16EventPin); + break; + default: + i32Ret = LL_ERR_INVD_PARAM; + break; + } + return i32Ret; +} + +/** + * @brief Read specified Event port input data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin input value + */ +en_ep_state_t EP_ReadInputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTIDR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port input data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port input value + */ +uint16_t EP_ReadInputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTIDR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Read specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval Specified Event port pin output value + */ +en_ep_state_t EP_ReadOutputPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + return ((READ_REG32(PEVNTODR_REG(u8EventPort)) & (u16EventPin)) != 0UL) ? EVT_PIN_SET : EVT_PIN_RESET; +} + +/** + * @brief Read specified Event port output data port + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the Event Port peripheral + * @retval Specified Event Port output value + */ +uint16_t EP_ReadOutputPort(uint8_t u8EventPort) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + + return (uint16_t)(READ_REG32(PEVNTODR_REG(u8EventPort)) & 0xFFFFUL); +} + +/** + * @brief Set specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_SetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + SET_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Reset specified Event port output data port pins + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @retval None + */ +void EP_ResetPins(uint8_t u8EventPort, uint16_t u16EventPin) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + + CLR_REG32_BIT(PEVNTODR_REG(u8EventPort), u16EventPin); +} + +/** + * @brief Set specified Event port pins direction + * @param [in] u8EventPort: EVENT_PORT_x, x can be (1~4) to select the EP peripheral + * @param [in] u16EventPin: EVENT_PIN_x, x can be (00~15) to select the EP pin index + * @param [in] u32Dir: Pin direction + * @arg EP_DIR_IN + * @arg EP_DIR_OUT + * @retval None + */ +void EP_SetDir(uint8_t u8EventPort, uint16_t u16EventPin, uint32_t u32Dir) +{ + DDL_ASSERT(IS_EVENT_PORT(u8EventPort)); + DDL_ASSERT(IS_EVENT_PIN(u16EventPin)); + DDL_ASSERT(IS_EP_DIR(u32Dir)); + + if (EP_DIR_OUT == u32Dir) { + SET_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } else { + CLR_REG32_BIT(PEVNTDIR_REG(u8EventPort), u16EventPin); + } +} + +/** + * @} + */ + +#endif /* LL_EVENT_PORT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c new file mode 100644 index 0000000000..3fa0b82d8c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcg.c @@ -0,0 +1,194 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcg.c + * @brief This file provides firmware functions to manage the Function Clock + * Gate (FCG). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcg.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCG FCG + * @brief FCG Driver Library + * @{ + */ + +#if (LL_FCG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCG_Local_Macros FCG Local Macros + * @{ + */ +#define IS_FCG0_UNLOCKED() ((CM_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0) + +/** + * @defgroup FCG_Check_Parameters_Validity FCG Check Parameters Validity + * @{ + */ +/* Parameter validity check for peripheral in fcg0. */ +#define IS_FCG0_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG0_PERIPH_MASK) == FCG_FCG0_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg1. */ +#define IS_FCG1_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG1_PERIPH_MASK) == FCG_FCG1_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg2. */ +#define IS_FCG2_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG2_PERIPH_MASK) == FCG_FCG2_PERIPH_MASK)) + +/* Parameter validity check for peripheral in fcg3. */ +#define IS_FCG3_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | FCG_FCG3_PERIPH_MASK) == FCG_FCG3_PERIPH_MASK)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCG_Global_Functions FCG Global Functions + * @{ + */ + +/** + * @brief Enable or disable the FCG0 peripheral clock. + * @param [in] u32Fcg0Periph The peripheral in FCG0 @ref FCG_FCG0_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_FCG0_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG0, u32Fcg0Periph); + } +} + +/** + * @brief Enable or disable the FCG1 peripheral clock. + * @param [in] u32Fcg1Periph The peripheral in FCG1 @ref FCG_FCG1_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG1, u32Fcg1Periph); + } +} + +/** + * @brief Enable or disable the FCG2 peripheral clock. + * @param [in] u32Fcg2Periph The peripheral in FCG2 @ref FCG_FCG2_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG2, u32Fcg2Periph); + } +} + +/** + * @brief Enable or disable the FCG3 peripheral clock. + * @param [in] u32Fcg3Periph The peripheral in FCG3 @ref FCG_FCG3_Peripheral. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCG_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } else { + SET_REG32_BIT(CM_PWC->FCG3, u32Fcg3Periph); + } +} + +#endif /* LL_FCG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c new file mode 100644 index 0000000000..fecd40ec65 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_fcm.c @@ -0,0 +1,394 @@ +/** + ******************************************************************************* + * @file hc32_ll_fcm.c + * @brief This file provides firmware functions to manage the Frequency Clock + * Measurement (FCM). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_fcm.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_FCM FCM + * @brief FCM Driver Library + * @{ + */ + +#if (LL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Local_Macros FCM Local Macros + * @{ + */ + +/* FCM Registers RESET Value */ +#define FCM_REG_RST_VALUE (0x00000000UL) + +/* FCM interrupt mask */ +#define FCM_INT_MASK (FCM_INT_OVF | FCM_INT_END | FCM_INT_ERR) +/* FCM status flag mask */ +#define FCM_FLAG_MASK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF) + +#define FCM_RMU_TIMEOUT (100UL) +/** + * @defgroup FCM_Check_Parameters_Validity FCM Check Parameters Validity + * @{ + */ + +/* Parameter validity check for FCM target and reference clock source. */ +#define IS_FCM_TARGET_SRC(x) \ +( ((x) == FCM_TARGET_CLK_XTAL) || \ + ((x) == FCM_TARGET_CLK_XTAL32) || \ + ((x) == FCM_TARGET_CLK_HRC) || \ + ((x) == FCM_TARGET_CLK_LRC) || \ + ((x) == FCM_TARGET_CLK_SWDTLRC) || \ + ((x) == FCM_TARGET_CLK_PCLK1) || \ + ((x) == FCM_TARGET_CLK_MRC) || \ + ((x) == FCM_TARGET_CLK_PLLHP)) + +#define IS_FCM_REF_SRC(x) \ +( ((x) == FCM_REF_CLK_EXTCLK) || \ + ((x) == FCM_REF_CLK_XTAL) || \ + ((x) == FCM_REF_CLK_XTAL32) || \ + ((x) == FCM_REF_CLK_HRC) || \ + ((x) == FCM_REF_CLK_LRC) || \ + ((x) == FCM_REF_CLK_SWDTLRC) || \ + ((x) == FCM_REF_CLK_PCLK1) || \ + ((x) == FCM_REF_CLK_MRC) || \ + ((x) == FCM_REF_CLK_PLLHP)) + +/* Parameter validity check for FCM target clock division. */ +#define IS_FCM_TARGET_DIV(x) \ +( ((x) == FCM_TARGET_CLK_DIV1) || \ + ((x) == FCM_TARGET_CLK_DIV4) || \ + ((x) == FCM_TARGET_CLK_DIV8) || \ + ((x) == FCM_TARGET_CLK_DIV32)) + +/* Parameter validity check for FCM external reference input function. */ +#define IS_FCM_EXT_REF_FUNC(x) \ +( ((x) == FCM_EXT_REF_OFF) || \ + ((x) == FCM_EXT_REF_ON)) + +/* Parameter validity check for FCM reference clock edge. */ +#define IS_FCM_REF_EDGE(x) \ +( ((x) == FCM_REF_CLK_RISING) || \ + ((x) == FCM_REF_CLK_FALLING) || \ + ((x) == FCM_REF_CLK_BOTH)) + +/* Parameter validity check for FCM digital filter function. */ +#define IS_FCM_DIG_FILTER(x) \ +( ((x) == FCM_DIG_FILTER_OFF) || \ + ((x) == FCM_DIG_FILTER_DIV1) || \ + ((x) == FCM_DIG_FILTER_DIV4) || \ + ((x) == FCM_DIG_FILTER_DIV16)) + +/* Parameter validity check for FCM reference clock division. */ +#define IS_FCM_REF_DIV(x) \ +( ((x) == FCM_REF_CLK_DIV32) || \ + ((x) == FCM_REF_CLK_DIV128) || \ + ((x) == FCM_REF_CLK_DIV1024) || \ + ((x) == FCM_REF_CLK_DIV8192)) + +/* Parameter validity check for FCM exception type function. */ +#define IS_FCM_EXP_TYPE(x) \ +( ((x) == FCM_EXP_TYPE_INT) || \ + ((x) == FCM_EXP_TYPE_RST)) + +/* Parameter validity check for FCM interrupt. */ +#define IS_FCM_INT(x) (((x) | FCM_INT_MASK) == FCM_INT_MASK) + +/* Parameter validity check for FCM flag state. */ +#define IS_FCM_FLAG(x) \ +( ((x) != 0x00UL) && \ + (((x) | FCM_FLAG_MASK) == FCM_FLAG_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Functions FCM Global Functions + * @{ + */ + +/** + * @brief Initialize FCM. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_Init(const stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_FCM_TARGET_SRC(pstcFcmInit->u32TargetClock)); + DDL_ASSERT(IS_FCM_TARGET_DIV(pstcFcmInit->u32TargetClockDiv)); + DDL_ASSERT(IS_FCM_EXT_REF_FUNC(pstcFcmInit->u32ExtRefClockEnable)); + DDL_ASSERT(IS_FCM_REF_EDGE(pstcFcmInit->u32RefClockEdge)); + DDL_ASSERT(IS_FCM_DIG_FILTER(pstcFcmInit->u32DigitalFilter)); + DDL_ASSERT(IS_FCM_REF_SRC(pstcFcmInit->u32RefClock)); + DDL_ASSERT(IS_FCM_REF_DIV(pstcFcmInit->u32RefClockDiv)); + DDL_ASSERT(IS_FCM_EXP_TYPE(pstcFcmInit->u32ExceptionType)); + + WRITE_REG32(CM_FCM->LVR, pstcFcmInit->u16LowerLimit); + WRITE_REG32(CM_FCM->UVR, pstcFcmInit->u16UpperLimit); + WRITE_REG32(CM_FCM->MCCR, (pstcFcmInit->u32TargetClock | pstcFcmInit->u32TargetClockDiv)); + WRITE_REG32(CM_FCM->RCCR, (pstcFcmInit->u32ExtRefClockEnable | pstcFcmInit->u32RefClockEdge | + pstcFcmInit->u32DigitalFilter | pstcFcmInit->u32RefClock | + pstcFcmInit->u32RefClockDiv)); + MODIFY_REG32(CM_FCM->RIER, FCM_RIER_ERRINTRS, pstcFcmInit->u32ExceptionType); + } + return i32Ret; +} + +/** + * @brief Initialize FCM structure. Fill each pstcFcmInit with default value. + * @param [in] pstcFcmInit Pointer to a @ref stc_fcm_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: FCM structure initialize successful + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET FCM init structure parameters values */ + pstcFcmInit->u16LowerLimit = 0U; + pstcFcmInit->u16UpperLimit = 0U; + pstcFcmInit->u32TargetClock = FCM_TARGET_CLK_XTAL; + pstcFcmInit->u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + pstcFcmInit->u32ExtRefClockEnable = FCM_EXT_REF_OFF; + pstcFcmInit->u32RefClockEdge = FCM_REF_CLK_RISING; + pstcFcmInit->u32DigitalFilter = FCM_DIG_FILTER_OFF; + pstcFcmInit->u32RefClock = FCM_REF_CLK_XTAL; + pstcFcmInit->u32RefClockDiv = FCM_REF_CLK_DIV32; + pstcFcmInit->u32ExceptionType = FCM_EXP_TYPE_INT; + } + return i32Ret; +} + +/** + * @brief De-Initialize FCM. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success. + * - LL_ERR_TIMEOUT: Timeout. + */ +int32_t FCM_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeOut = 0U; + /* Check FRST register protect */ + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + /* Reset FCM */ + WRITE_REG32(bCM_RMU->FRST0_b.FCM, 0UL); + /* Ensure reset procedure is completed */ + while (0UL == READ_REG32(bCM_RMU->FRST0_b.FCM)) { + u32TimeOut++; + if (u32TimeOut > FCM_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Get FCM state, get FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t FCM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + return ((READ_REG32_BIT(CM_FCM->SR, u32Flag) != 0UL) ? SET : RESET); +} + +/** + * @brief Clear FCM state, Clear FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags.This parameter can be one or any + * combination of the following values: @ref FCM_Flag_Sel + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval None. + */ +void FCM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + SET_REG32_BIT(CM_FCM->CLR, u32Flag); +} + +/** + * @brief Get FCM counter value. + * @param None + * @retval FCM counter value. + */ +uint16_t FCM_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(CM_FCM->CNTR) & 0xFFFFU); +} + +/** + * @brief FCM target clock type and division config. + * @param [in] u32ClockSrc Target clock type. @ref FCM_Target_Clock_Src + * @param [in] u32Div Target clock division. @ref FCM_Target_Clock_Div + * @arg FCM_TARGET_CLK_DIV1 + * @arg FCM_TARGET_CLK_DIV4 + * @arg FCM_TARGET_CLK_DIV8 + * @arg FCM_TARGET_CLK_DIV32 + * @retval None. + */ +void FCM_SetTargetClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_TARGET_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_TARGET_DIV(u32Div)); + WRITE_REG32(CM_FCM->MCCR, (u32ClockSrc | u32Div)); +} + +/** + * @brief FCM reference clock type and division config. + * @param [in] u32ClockSrc Reference clock type. @ref FCM_Ref_Clock_Src + * @param [in] u32Div Reference clock division. @ref FCM_Ref_Clock_Div + * @arg FCM_REF_CLK_DIV32 + * @arg FCM_REF_CLK_DIV128 + * @arg FCM_REF_CLK_DIV1024 + * @arg FCM_REF_CLK_DIV8192 + * @retval None. + */ +void FCM_SetRefClock(uint32_t u32ClockSrc, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_REF_SRC(u32ClockSrc)); + DDL_ASSERT(IS_FCM_REF_DIV(u32Div)); + MODIFY_REG32(CM_FCM->RCCR, (FCM_RCCR_INEXS | FCM_RCCR_RCKS | FCM_RCCR_RDIVS), (u32ClockSrc | u32Div)); +} + +/** + * @brief Enable or disable the FCM reset + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_ResetCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_FCM->RIER_b.ERRE, enNewState); +} + +/** + * @brief Enable or disable the FCM interrupt + * @param [in] u32IntType The FCM interrupt type. This parameter can be + * one or any combination @ref FCM_Int_Type + * @arg FCM_INT_OVF: FCM overflow interrupt + * @arg FCM_INT_END: FCM calculate end interrupt + * @arg FCM_INT_ERR: FCM frequency abnormal interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void FCM_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FCM_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_FCM->RIER, u32IntType); + } else { + CLR_REG32_BIT(CM_FCM->RIER, u32IntType); + } +} + +/** + * @brief FCM function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None. + */ +void FCM_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_FCM->STR_b.START, enNewState); +} + +/** + * @} + */ + +#endif /* LL_FCM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c new file mode 100644 index 0000000000..1ca64c6ef0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_gpio.c @@ -0,0 +1,751 @@ +/** + ******************************************************************************* + * @file hc32_ll_gpio.c + * @brief This file provides firmware functions to manage the General Purpose + * Input/Output(GPIO). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify GPIO_SetFunc() + Rename GPIO_ExIntCmd() as GPIO_ExtIntCmd + Optimize API: GPIO_Init(), GPIO_SetFunc(), GPIO_SubFuncCmd(), GPIO_InputMOSCmd(), GPIO_AnalogCmd(), GPIO_ExtIntCmd() + 2023-12-15 CDT Add assert for GPIO register lock status in API GPIO_AnalogCmd(), GPIO_ExtIntCmd() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_gpio.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_GPIO GPIO + * @brief GPIO Driver Library + * @{ + */ + +#if (LL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Types GPIO Local Typedefs + * @{ + */ +/** + * @brief GPIO port pin table definition + */ +typedef struct { + uint8_t u8Port; /*!< GPIO Port Source, @ref GPIO_Port_Source for details */ + uint16_t u16PinMask; /*!< Pin active or inactive, @ref GPIO_All_Pins_Define for details */ +} stc_gpio_port_pin_tbl_t; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Macros GPIO Local Macros + * @{ + */ +/** + * @defgroup GPIO_Registers_Setting_definition GPIO Registers setting definition + * @{ + */ +#define GPIO_PSPCR_RST_VALUE (0x001FU) +#define GPIO_PCCR_RST_VALUE (0x1000U) +#define GPIO_PIN_NUM_MAX (16U) +#define GPIO_PORT_OFFSET (0x40UL) +#define GPIO_PIN_OFFSET (0x04UL) +#define GPIO_REG_OFFSET (0x10UL) +#define GPIO_REG_TYPE uint16_t +#define GPIO_PIDR_BASE ((uint32_t)(&CM_GPIO->PIDRA)) +#define GPIO_PODR_BASE ((uint32_t)(&CM_GPIO->PODRA)) +#define GPIO_POSR_BASE ((uint32_t)(&CM_GPIO->POSRA)) +#define GPIO_PORR_BASE ((uint32_t)(&CM_GPIO->PORRA)) +#define GPIO_POTR_BASE ((uint32_t)(&CM_GPIO->POTRA)) +#define GPIO_POER_BASE ((uint32_t)(&CM_GPIO->POERA)) +#define GPIO_PCR_BASE ((uint32_t)(&CM_GPIO->PCRA0)) +#define GPIO_PFSR_BASE ((uint32_t)(&CM_GPIO->PFSRA0)) + +#define PIDR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PIDR_BASE + GPIO_REG_OFFSET * (x))) +#define PODR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PODR_BASE + GPIO_REG_OFFSET * (x))) +#define POSR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POSR_BASE + GPIO_REG_OFFSET * (x))) +#define PORR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_PORR_BASE + GPIO_REG_OFFSET * (x))) +#define POTR_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POTR_BASE + GPIO_REG_OFFSET * (x))) +#define POER_REG(x) (*(__IO GPIO_REG_TYPE *)(GPIO_POER_BASE + GPIO_REG_OFFSET * (x))) +#define PCR_REG(x, y) (*(__IO uint16_t *)(GPIO_PCR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +#define PFSR_REG(x, y) (*(__IO uint16_t *)(GPIO_PFSR_BASE + (uint32_t)((x) * GPIO_PORT_OFFSET) + (y) * GPIO_PIN_OFFSET)) +/** + * @} + */ + +/** + * @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity + * @{ + */ +/*! Parameter validity check for pin state. */ +#define IS_GPIO_PIN_STATE(state) \ +( ((state) == PIN_STAT_RST) || \ + ((state) == PIN_STAT_SET)) + +/*! Parameter validity check for pin direction. */ +#define IS_GPIO_DIR(dir) \ +( ((dir) == PIN_DIR_IN) || \ + ((dir) == PIN_DIR_OUT)) + +/*! Parameter validity check for pin output type. */ +#define IS_GPIO_OUT_TYPE(type) \ +( ((type) == PIN_OUT_TYPE_CMOS) || \ + ((type) == PIN_OUT_TYPE_NMOS)) + +/*! Parameter validity check for pin driver capacity. */ +#define IS_GPIO_PIN_DRV(drv) \ +( ((drv) == PIN_LOW_DRV) || \ + ((drv) == PIN_MID_DRV) || \ + ((drv) == PIN_HIGH_DRV)) + +/*! Parameter validity check for pin attribute. */ +#define IS_GPIO_ATTR(attr) \ +( ((attr) == PIN_ATTR_DIGITAL) || \ + ((attr) == PIN_ATTR_ANALOG)) + +/*! Parameter validity check for pin latch function. */ +#define IS_GPIO_LATCH(latch) \ +( ((latch) == PIN_LATCH_OFF) || \ + ((latch) == PIN_LATCH_ON)) + +/*! Parameter validity check for internal pull-up resistor. */ +#define IS_GPIO_PIN_PU(pu) \ +( ((pu) == PIN_PU_OFF) || \ + ((pu) == PIN_PU_ON)) + +/*! Parameter validity check for internal pull-down resistor. */ +#define IS_GPIO_PIN_PD(pd) \ +( ((pd) == PIN_PD_OFF) || \ + ((pd) == PIN_PD_ON)) + +/*! Parameter validity check for input MOS alays on. */ +#define IS_GPIO_PIN_INMOS(sw) \ +( ((sw) == PIN_IN_MOS_OFF) || \ + ((sw) == PIN_IN_MOS_ON)) + +/*! Parameter validity check for pin state invert. */ +#define IS_GPIO_PIN_INVERT(invert) \ +( ((invert) == PIN_INVT_OFF) || \ + ((invert) == PIN_INVT_ON)) + +/*! Parameter validity check for pin input type. */ +#define IS_GPIO_IN_TYPE(type) \ +( ((type) == PIN_IN_TYPE_SMT) || \ + ((type) == PIN_IN_TYPE_CMOS)) + +/*! Parameter validity check for external interrupt function. */ +#define IS_GPIO_EXTINT(extint) \ +( ((extint) == PIN_EXTINT_OFF) || \ + ((extint) == PIN_EXTINT_ON)) + +/*! Parameter validity check for pin number. */ +#define IS_GPIO_PIN(pin) \ +( ((pin) != 0U) && \ + (((pin) & GPIO_PIN_ALL) != 0U)) + +/*! Parameter validity check for port source. */ +#define IS_GPIO_PORT(port) \ +( ((port) == GPIO_PORT_A) || \ + ((port) == GPIO_PORT_B) || \ + ((port) == GPIO_PORT_C) || \ + ((port) == GPIO_PORT_D) || \ + ((port) == GPIO_PORT_E) || \ + ((port) == GPIO_PORT_H)) + +/*! Parameter validity check for pin function. */ +#define IS_GPIO_FUNC(func) \ +( ((func) <= GPIO_FUNC_8) || \ + (((func) >= GPIO_FUNC_11) && ((func) <= GPIO_FUNC_15)) || \ + (((func) >= GPIO_FUNC_21) && ((func) <= GPIO_FUNC_22)) || \ + (((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_57))) + +/*! Parameter validity check for debug pin definition. */ +#define IS_GPIO_DEBUG_PORT(port) \ +( ((port) != 0U) && \ + (((port) | GPIO_PIN_DEBUG) == GPIO_PIN_DEBUG)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_GPIO_READ_WAIT(wait) \ +( ((wait) == GPIO_RD_WAIT0) || \ + ((wait) == GPIO_RD_WAIT1) || \ + ((wait) == GPIO_RD_WAIT2) || \ + ((wait) == GPIO_RD_WAIT3) || \ + ((wait) == GPIO_RD_WAIT4) || \ + ((wait) == GPIO_RD_WAIT5) || \ + ((wait) == GPIO_RD_WAIT6) || \ + ((wait) == GPIO_RD_WAIT7)) + +/* Check GPIO register lock status. */ +#define IS_GPIO_UNLOCK() (GPIO_PWPR_WE == (CM_GPIO->PWPR & GPIO_PWPR_WE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Variables GPIO Local Variables + * @{ + */ +static const stc_gpio_port_pin_tbl_t m_astcGpioPortPinTbl[] = { + {GPIO_PORT_A, GPIO_PIN_A_ALL}, + {GPIO_PORT_B, GPIO_PIN_B_ALL}, + {GPIO_PORT_C, GPIO_PIN_C_ALL}, + {GPIO_PORT_D, GPIO_PIN_D_ALL}, + {GPIO_PORT_E, GPIO_PIN_E_ALL}, + {GPIO_PORT_H, GPIO_PIN_H_ALL}, + +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Functions GPIO Global Functions + * @{ + */ + +/** + * @brief Initialize GPIO. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit) +{ + uint8_t u8PinPos; + uint16_t u16PCRVal; + uint16_t u16PCRMask; + int32_t i32Ret = LL_OK; + __IO uint16_t *PCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_UNLOCK()); + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState)); + DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir)); + DDL_ASSERT(IS_GPIO_OUT_TYPE(pstcGpioInit->u16PinOutputType)); + DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv)); + DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch)); + DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp)); + DDL_ASSERT(IS_GPIO_PIN_PD(pstcGpioInit->u16PullDown)); + DDL_ASSERT(IS_GPIO_PIN_INMOS(pstcGpioInit->u16InputMos)); + DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert)); + DDL_ASSERT(IS_GPIO_EXTINT(pstcGpioInit->u16ExtInt)); + DDL_ASSERT(IS_GPIO_IN_TYPE(pstcGpioInit->u16PinInputType)); + DDL_ASSERT(IS_GPIO_ATTR(pstcGpioInit->u16PinAttr)); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + u16PCRVal = pstcGpioInit->u16PinState | pstcGpioInit->u16PinDir | pstcGpioInit->u16PinOutputType | \ + pstcGpioInit->u16PinDrv | pstcGpioInit->u16PullUp | pstcGpioInit->u16Invert | \ + pstcGpioInit->u16ExtInt | pstcGpioInit->u16Latch; + + u16PCRMask = GPIO_PCR_POUT | GPIO_PCR_POUTE | GPIO_PCR_NOD | \ + GPIO_PCR_DRV | GPIO_PCR_PUU | GPIO_PCR_INVE | \ + GPIO_PCR_INTE | GPIO_PCR_LTE ; + u16PCRVal |= pstcGpioInit->u16PinAttr; + u16PCRMask |= GPIO_PCR_DDIS; + u16PCRVal |= pstcGpioInit->u16PullDown | pstcGpioInit->u16InputMos; + u16PCRMask |= GPIO_PCR_PUD | GPIO_PCR_PINAE; + + u16PCRVal |= pstcGpioInit->u16PinInputType; + u16PCRMask |= GPIO_PCR_CINSEL; + PCRx = &PCR_REG(u8Port, u8PinPos); + MODIFY_REG16(*PCRx, u16PCRMask, u16PCRVal); + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } + } + return i32Ret; +} + +/** + * @brief De-init GPIO register to default value + * @param None + * @retval None + */ +void GPIO_DeInit(void) +{ + stc_gpio_init_t stcGpioInit; + uint8_t i; + DDL_ASSERT(IS_GPIO_UNLOCK()); + + (void)GPIO_StructInit(&stcGpioInit); + + for (i = 0U; i < ARRAY_SZ(m_astcGpioPortPinTbl); i++) { + (void)GPIO_Init(m_astcGpioPortPinTbl[i].u8Port, m_astcGpioPortPinTbl[i].u16PinMask, &stcGpioInit); + } + /* GPIO global register reset */ + WRITE_REG16(CM_GPIO->PSPCR, GPIO_PSPCR_RST_VALUE); + WRITE_REG16(CM_GPIO->PCCR, GPIO_PCCR_RST_VALUE); + +} + +/** + * @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: GPIO structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Reset GPIO init structure parameters values */ + pstcGpioInit->u16PinState = PIN_STAT_RST; + pstcGpioInit->u16PinDir = PIN_DIR_IN; + pstcGpioInit->u16PinDrv = PIN_LOW_DRV; + pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL; + pstcGpioInit->u16PullDown = PIN_PD_OFF; + pstcGpioInit->u16InputMos = PIN_IN_MOS_OFF; + pstcGpioInit->u16Latch = PIN_LATCH_OFF; + pstcGpioInit->u16PullUp = PIN_PU_OFF; + pstcGpioInit->u16Invert = PIN_INVT_OFF; + pstcGpioInit->u16ExtInt = PIN_EXTINT_OFF; + pstcGpioInit->u16PinOutputType = PIN_OUT_TYPE_CMOS; + pstcGpioInit->u16PinInputType = PIN_IN_TYPE_SMT; + } + return i32Ret; +} + +/** + * @brief GPIO debug port configure. Set debug pins to GPIO + * @param [in] u8DebugPort: @ref GPIO_DebugPin_Sel for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set to debug port (SWD/JTAG) + * @arg DISABLE: set to GPIO + * @retval None + */ +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + if (ENABLE == enNewState) { + SET_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } else { + CLR_REG16_BIT(CM_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } +} + +/** + * @brief Set specified Port Pin function + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] u16Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint16_t u16Func) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_FUNC(u16Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + MODIFY_REG16(*PFSRx, GPIO_PFSR_FSEL, u16Func); + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @brief GPIO pin sub-function ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_SubFuncCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + uint8_t u8PinPos; + __IO uint16_t *PFSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PFSRx = &PFSR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } else { + CLR_REG16_BIT(*PFSRx, PIN_SUBFUNC_ENABLE); + } + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @brief Set the sub-function, it's a global configuration + * @param [in] u8Func: GPIO_FUNC_x, x can be the suffix in @ref GPIO_Function_Sel for each product + * @retval None + */ +void GPIO_SetSubFunc(uint8_t u8Func) +{ + DDL_ASSERT(IS_GPIO_FUNC(u8Func)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func); +} + +/** + * @brief GPIO output ENABLE. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_OutputCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO GPIO_REG_TYPE *POERx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + POERx = &POER_REG(u8Port); + if (ENABLE == enNewState) { + SET_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } else { + CLR_REG_BIT(*POERx, (GPIO_REG_TYPE)u16Pin); + } +} + +/** + * @brief GPIO read wait cycle configure. + * @param [in] u16ReadWait: @ref GPIO_ReadCycle_Sel for each product + * @retval None + */ +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait) +{ + DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + MODIFY_REG16(CM_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait); +} + +/** + * @brief GPIO input MOS always ON configure. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @arg ENABLE: set input MOS always ON + * @arg DISABLE: set input MOS turns on while read operation + * @retval None + */ +void GPIO_InputMOSCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO uint16_t *PCRx; + uint8_t u8PinPos; + + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCK()); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PCRx = &PCR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PCRx, GPIO_PCR_PINAE); + } else { + CLR_REG16_BIT(*PCRx, GPIO_PCR_PINAE); + } + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @brief Read specified GPIO input data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin input value + */ +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PIDR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO input data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port input value + */ +uint16_t GPIO_ReadInputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PIDR_REG(u8Port)); +} + +/** + * @brief Read specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval Specified GPIO port pin output value + */ +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + return ((READ_REG(PODR_REG(u8Port)) & (u16Pin)) != 0U) ? PIN_SET : PIN_RESET; +} + +/** + * @brief Read specified GPIO output data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @retval Specified GPIO port output value + */ +uint16_t GPIO_ReadOutputPort(uint8_t u8Port) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + return READ_REG(PODR_REG(u8Port)); +} + +/** + * @brief Set specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POSRx = &POSR_REG(u8Port); + SET_REG_BIT(*POSRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Reset specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *PORRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + PORRx = &PORR_REG(u8Port); + SET_REG_BIT(*PORRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief Write specified GPIO data port + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16PortVal: Pin output value + * @retval None + */ +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal) +{ + __IO GPIO_REG_TYPE *PODRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + + PODRx = &PODR_REG(u8Port); + WRITE_REG(*PODRx, (GPIO_REG_TYPE)u16PortVal); +} + +/** + * @brief Toggle specified GPIO output data port pin + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @retval None + */ +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO GPIO_REG_TYPE *POTRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POTRx = &POTR_REG(u8Port); + SET_REG_BIT(*POTRx, (GPIO_REG_TYPE)u16Pin); +} + +/** + * @brief GPIO Analog command. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_AnalogCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO uint16_t *PCRx; + uint8_t u8PinPos; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_UNLOCK()); + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PCRx = &PCR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PCRx, GPIO_PCR_DDIS); + } else { + CLR_REG16_BIT(*PCRx, GPIO_PCR_DDIS); + } + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @brief GPIO external interrupt command. + * @param [in] u8Port: GPIO_PORT_x, x can be the suffix in @ref GPIO_Port_Source for each product + * @param [in] u16Pin: GPIO_PIN_x, x can be the suffix in @ref GPIO_Pins_Define for each product + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void GPIO_ExtIntCmd(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO uint16_t *PCRx; + uint8_t u8PinPos; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_UNLOCK()); + DDL_ASSERT(IS_GPIO_PORT(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + for (u8PinPos = 0U; u8PinPos < GPIO_PIN_NUM_MAX; u8PinPos++) { + if ((u16Pin & 1U) != 0U) { + PCRx = &PCR_REG(u8Port, u8PinPos); + if (ENABLE == enNewState) { + SET_REG16_BIT(*PCRx, GPIO_PCR_INTE); + } else { + CLR_REG16_BIT(*PCRx, GPIO_PCR_INTE); + } + } + u16Pin >>= 1U; + if (0U == u16Pin) { + break; + } + } +} + +/** + * @} + */ + +#endif /* LL_GPIO_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c new file mode 100644 index 0000000000..f2630ddbef --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_hash.c @@ -0,0 +1,350 @@ +/** + ******************************************************************************* + * @file hc32_ll_hash.c + * @brief This file provides firmware functions to manage the HASH + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_hash.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_HASH HASH + * @brief HASH Driver Library + * @{ + */ + +#if (LL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Macros HASH Local Macros + * @{ + */ + +/** + * @defgroup HASH_Miscellaneous_Macros HASH Miscellaneous Macros + * @{ + */ +#define HASH_GROUP_SIZE (64U) +#define HASH_GROUP_SIZE_WORD (HASH_GROUP_SIZE / 4U) +#define HASH_LAST_GROUP_SIZE_MAX (56U) +#define HASH_TIMEOUT (6000U) +#define HASH_MSG_DIGEST_SIZE_WORD (8U) + +/** + * @} + */ + +/** + * @defgroup HASH_Action HASH Action + * @{ + */ +#define HASH_ACTION_START (HASH_CR_START) +/** + * @} + */ + +#define IS_HASH_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/* HASH reset timeout */ +#define HASH_RMU_TIMEOUT (100UL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Functions HASH Local Functions + * @{ + */ + +/** + * @brief Writes the input buffer in data register. + * @param [in] pu8Data The buffer for source data + * @retval None + */ +static void HASH_WriteData(const uint8_t *pu8Data) +{ + uint8_t i; + __IO uint32_t *regDR = &CM_HASH->DR15; + const uint32_t *pu32Data = (const uint32_t *)((uint32_t)pu8Data); + + for (i = 0U; i < HASH_GROUP_SIZE_WORD; i++) { + regDR[i] = __REV(pu32Data[i]); + } +} + +/** + * @brief Memory copy. + * @param [in] pu8Dest Pointer to a destination address. + * @param [in] pu8Src Pointer to a source address. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemCopy(uint8_t *pu8Dest, const uint8_t *pu8Src, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Dest[i] = pu8Src[i]; + i++; + } +} + +/** + * @brief Memory set. + * @param [in] pu8Mem Pointer to an address. + * @param [in] u8Value Data value. + * @param [in] u32Size Data size. + * @retval None + */ +static void HASH_MemSet(uint8_t *pu8Mem, uint8_t u8Value, uint32_t u32Size) +{ + uint32_t i = 0UL; + while (i < u32Size) { + pu8Mem[i] = u8Value; + i++; + } +} + +/** + * @brief Wait for the HASH to stop + * @param [in] u32Action HASH action. This parameter can be a value of @ref HASH_Action. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_Wait(uint32_t u32Action) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeCount = 0UL; + + /* Wait for the HASH to stop */ + while (READ_REG32_BIT(CM_HASH->CR, u32Action) != 0UL) { + if (u32TimeCount++ > HASH_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief HASH Filling data + * @param [in] pu8Data The source data buffer + * @param [in] u32DataSize Length of the input buffer in bytes + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: Works timeout + */ +static int32_t HASH_DoCalc(const uint8_t *pu8Data, uint32_t u32DataSize) +{ + uint8_t u8FillBuffer[HASH_GROUP_SIZE]; + uint32_t u32BitLenHigh; + uint32_t u32BitLenLow; + uint32_t u32Index = 0U; + uint8_t u8FirstGroup = 1U; + uint8_t u8HashEnd = 0U; + uint8_t u8DataEndMark = 0U; + int32_t i32Ret; + + u32BitLenHigh = (u32DataSize >> 29U) & 0x7U; + u32BitLenLow = (u32DataSize << 3U); + + /* Stop hash calculating. */ + i32Ret = HASH_Wait(HASH_ACTION_START); + + while ((i32Ret == LL_OK) && (u8HashEnd == 0U)) { + if (u32DataSize >= HASH_GROUP_SIZE) { + HASH_WriteData(&pu8Data[u32Index]); + u32DataSize -= HASH_GROUP_SIZE; + u32Index += HASH_GROUP_SIZE; + } else if (u32DataSize >= HASH_LAST_GROUP_SIZE_MAX) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + u8FillBuffer[u32DataSize] = 0x80U; + u8DataEndMark = 1U; + HASH_WriteData(u8FillBuffer); + u32DataSize = 0U; + } else { + u8HashEnd = 1U; + } + + if (u8HashEnd != 0U) { + HASH_MemSet(u8FillBuffer, 0, HASH_GROUP_SIZE); + if (u32DataSize > 0U) { + HASH_MemCopy(u8FillBuffer, &pu8Data[u32Index], u32DataSize); + } + if (u8DataEndMark == 0U) { + u8FillBuffer[u32DataSize] = 0x80U; + } + u8FillBuffer[63U] = (uint8_t)(u32BitLenLow); + u8FillBuffer[62U] = (uint8_t)(u32BitLenLow >> 8U); + u8FillBuffer[61U] = (uint8_t)(u32BitLenLow >> 16U); + u8FillBuffer[60U] = (uint8_t)(u32BitLenLow >> 24U); + u8FillBuffer[59U] = (uint8_t)(u32BitLenHigh); + u8FillBuffer[58U] = (uint8_t)(u32BitLenHigh >> 8U); + u8FillBuffer[57U] = (uint8_t)(u32BitLenHigh >> 16U); + u8FillBuffer[56U] = (uint8_t)(u32BitLenHigh >> 24U); + HASH_WriteData(u8FillBuffer); + } + + /* First group and last group check */ + /* check if first group */ + if (u8FirstGroup != 0U) { + u8FirstGroup = 0U; + /* Set first group. */ + WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 1U); + } else { + /* Set continuous group. */ + WRITE_REG32(bCM_HASH->CR_b.FST_GRP, 0U); + } + + /* Start hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 1U); + i32Ret = HASH_Wait(HASH_ACTION_START); + } + /* Stop hash calculating. */ + WRITE_REG32(bCM_HASH->CR_b.START, 0U); + + return i32Ret; +} + +/** + * @brief Read message digest. + * @param [out] pu8MsgDigest Buffer for message digest. + * @retval None + */ +static void HASH_ReadMsgDigest(uint8_t *pu8MsgDigest) +{ + uint8_t i; + __IO uint32_t *regHR = &CM_HASH->HR7; + uint32_t *pu32MsgDigest = (uint32_t *)((uint32_t)pu8MsgDigest); + + for (i = 0U; i < HASH_MSG_DIGEST_SIZE_WORD; i++) { + pu32MsgDigest[i] = __REV(regHR[i]); + } +} + +/** + * @} + */ + +/** + * @defgroup HASH_Global_Functions HASH Global Functions + * @{ + */ + +/** + * @brief De-initializes HASH. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t HASH_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeOut = 0U; + + /* Check parameters */ + DDL_ASSERT(IS_HASH_PWC_UNLOCKED()); + + CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_HASH); + /* Ensure reset procedure is completed */ + while (RMU_FRST0_HASH != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_HASH)) { + u32TimeOut++; + if (u32TimeOut > HASH_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief HASH calculate. + * @param [in] pu8SrcData Pointer to the source data buffer. + * @param [in] u32SrcDataSize Length of the source data buffer in bytes. + * @param [out] pu8MsgDigest Buffer of the digest. The size must be 32 bytes. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: Parameter error. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t HASH_Calculate(const uint8_t *pu8SrcData, uint32_t u32SrcDataSize, uint8_t *pu8MsgDigest) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu8SrcData != NULL) && (u32SrcDataSize != 0UL) && (pu8MsgDigest != NULL)) { + /* Set HASH mode */ + i32Ret = HASH_DoCalc(pu8SrcData, u32SrcDataSize); + if (i32Ret == LL_OK) { + /* Get the message digest result */ + HASH_ReadMsgDigest(pu8MsgDigest); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_HASH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c new file mode 100644 index 0000000000..30af8b8a5b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_i2c.c @@ -0,0 +1,1379 @@ +/** + ******************************************************************************* + * @file hc32_ll_i2c.c + * @brief This file provides firmware functions to manage the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Move macro define I2C_SRC_CLK to head file + 2023-12-15 CDT Remove API I2C_FIFO_ClearRequestStatus() & I2C_FIFO_GetStatus + Modify I2C_Restart() + Refine I2C Flag & API I2C_SlaveAddrConfig/I2C_SlaveMaskAddrConfig + Fix I2C_Deinit + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_i2c.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_I2C I2C + * @brief I2C Driver Library + * @{ + */ + +#if (LL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2C_Local_Macros I2C Local Macros + * @{ + */ +#define I2C_BAUDRATE_MAX (400000UL) + +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x1FE) +#define I2C_7BIT_MAX (0x7FUL) +#define I2C_10BIT_MAX (0x3FFUL) + +/** + * @defgroup I2C_Check_Parameters_Validity I2C Check Parameters Validity + * @{ + */ + +#define IS_I2C_UNIT(x) \ +( ((x) == CM_I2C1) || \ + ((x) == CM_I2C2)) + +#define IS_I2C_DIG_FILTER_CLK(x) ((x) <= I2C_DIG_FILTER_CLK_DIV4) + +#define IS_I2C_7BIT_ADDR(x) ((x) <= I2C_7BIT_MAX) +#define IS_I2C_10BIT_ADDR(x) ((x) <= I2C_10BIT_MAX) + +#define IS_I2C_SPEED(x) \ +( ((x) != 0U) && \ + ((x) <= I2C_BAUDRATE_MAX)) + +#define IS_I2C_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_ALL) == I2C_FLAG_ALL)) + +#define IS_I2C_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_FLAG_CLR_ALL) == I2C_FLAG_CLR_ALL)) + +#define IS_I2C_INT(x) \ +( ((x) != 0U) && \ + (((x) | I2C_INT_ALL) == I2C_INT_ALL)) + +#define IS_I2C_SMBUS_CONFIG(x) \ +( ((x) != 0U) && \ + (((x) | I2C_SMBUS_MATCH_ALL) == I2C_SMBUS_MATCH_ALL)) + +#define IS_I2C_ADDR(mode, addr) \ +( ((I2C_ADDR_7BIT == (mode)) && ((addr) <= 0x7FU)) || \ + ((I2C_ADDR_10BIT == (mode)) && ((addr) <= 0x3FFU)) || \ + (I2C_ADDR_DISABLE == (mode))) + +#define IS_I2C_ADDR_NUM(x) \ +( ((x) == I2C_ADDR0) || \ + ((x) == I2C_ADDR1)) + +#define IS_I2C_CLK_DIV(x) \ +( (x) <= I2C_CLK_DIV128) + +#define IS_I2C_TRANS_DIR(x) \ +( ((x) == I2C_DIR_TX) || \ + ((x) == I2C_DIR_RX)) + +#define IS_I2C_ACK_CONFIG(x) \ +( ((x) == I2C_ACK) || \ + ((x) == I2C_NACK)) + +#define IS_I2C_FLAG_STD(x) \ +( ((x) == RESET) || \ + ((x) == SET)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Functions I2C Global Functions + * @{ + */ + +/** + * @brief Try to wait a status of specified flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag values: + * @param [in] enStatus Expected status @ref en_flag_status_t + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_WaitStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_TIMEOUT; + uint32_t u32RegStatusBit; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + DDL_ASSERT(IS_I2C_FLAG_STD(enStatus)); + + for (;;) { + u32RegStatusBit = (READ_REG32_BIT(I2Cx->SR, u32Flag)); + if (((enStatus == SET) && (u32Flag == u32RegStatusBit)) || ((enStatus == RESET) && (0UL == u32RegStatusBit))) { + i32Ret = LL_OK; + } + + if ((LL_OK == i32Ret) || (0UL == u32Timeout)) { + break; + } else { + u32Timeout--; + } + } + return i32Ret; +} + +/** + * @brief I2C generate start condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief I2C generate restart condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateRestart(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_RESTART); +} + +/** + * @brief I2C generate stop condition + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_GenerateStop(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Set the baudrate for I2C peripheral. + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(Imme+2*Dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * Dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * Imme -- An Immediate data, 516 + * step2: chose a division item which is similar and bigger than div from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_BaudrateConfig(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret = LL_OK; + uint32_t I2cSrcClk; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t Dnfsum = 0UL; + uint32_t Divsum = 2UL; + uint32_t TheoryBaudrate; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2cInit) || (NULL == pf32Error)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Get configuration for i2c */ + I2cSrcClk = I2C_SRC_CLK; + I2cDivClk = 1UL << pstcI2cInit->u32ClockDiv; + SclCnt = pstcI2cInit->u32SclTime; + Baudrate = pstcI2cInit->u32Baudrate; + + /* Judge digital filter status */ + if (0U != READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNFEN)) { + Dnfsum = (READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNF) >> I2C_FLTR_DNF_POS) + 1U; + } + + /* Judge if clock divider on*/ + if (I2C_CLK_DIV1 == pstcI2cInit->u32ClockDiv) { + Divsum = 3UL; + } + + if (I2cDivClk != 0UL) { /* Judge for misra */ + WidthTotal = (float32_t)I2cSrcClk / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = (2.0F * (float32_t)Divsum) + (2.0F * (float32_t)Dnfsum) + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + /* Integer for WidthTotal, rounding off */ + if ((WidthTotal - (float32_t)((uint32_t)WidthTotal)) >= 0.5F) { + WidthTotal = (float32_t)((uint32_t)WidthTotal) + 1.0F; + } else { + WidthTotal = (float32_t)((uint32_t)WidthTotal); + } + + if (WidthTotal <= SumTotal) { + /* Err, Should set a smaller division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + if (WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) { + /* Err, Should set a bigger division value for pstcI2cInit->u32ClockDiv */ + i32Ret = LL_ERR_INVD_PARAM; + } else { + TheoryBaudrate = I2cSrcClk / (uint32_t)WidthTotal / I2cDivClk; + fErr = ((float32_t)Baudrate - (float32_t)TheoryBaudrate) / (float32_t)TheoryBaudrate; + WRITE_REG32(I2Cx->CCR, \ + (pstcI2cInit->u32ClockDiv << I2C_CCR_FREQ_POS) | \ + (((uint32_t)WidthHL / 2U) << I2C_CCR_SLOWW_POS) | \ + (((uint32_t)WidthHL - (((uint32_t)WidthHL) / 2U)) << I2C_CCR_SHIGHW_POS)); + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + } + + if ((NULL != pf32Error) && (LL_OK == i32Ret)) { + *pf32Error = fErr; + } + + return i32Ret; +} + +/** + * @brief De-initialize I2C unit + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval int32_t: + * - LL_OK: No error occurred. + */ +int32_t I2C_DeInit(CM_I2C_TypeDef *I2Cx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + /* RESET peripheral register and internal status*/ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + + return LL_OK; +} + +/** + * @brief Initialize I2C peripheral according to the structure + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] pstcI2cInit Pointer to I2C config structure @ref stc_i2c_init_t + * @arg pstcI2cInit->u32ClockDiv: Division of i2c source clock, reference as: + * step1: calculate div = (I2cSrcClk/Baudrate/(Imme+2*Dnfsum+SclTime) + * I2cSrcClk -- I2c source clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * Dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * Imme -- An Immediate data, 516 + * step2: chose a division item which is similar and bigger than div + * from @ref I2C_Clock_Division. + * @arg pstcI2cInit->u32Baudrate : Baudrate configuration + * @arg pstcI2cInit->u32SclTime : Indicate SCL pin rising and falling + * time, should be number of T(i2c clock period time) + * @param [out] pf32Error Baudrate error + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_Init(CM_I2C_TypeDef *I2Cx, const stc_i2c_init_t *pstcI2cInit, float32_t *pf32Error) +{ + int32_t i32Ret; + + if (NULL == pstcI2cInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SPEED(pstcI2cInit->u32Baudrate)); + DDL_ASSERT(IS_I2C_CLK_DIV(pstcI2cInit->u32ClockDiv)); + + /* Register and internal status reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + + /* I2C baudrate config */ + i32Ret = I2C_BaudrateConfig(I2Cx, pstcI2cInit, pf32Error); + + /* Disable global broadcast address function */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_ENGC); + /* Release software reset */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_SWRST); + /* Disable I2C peripheral */ + CLR_REG32_BIT(I2Cx->CR1, I2C_CR1_PE); + /* Disable slave address function */ + CLR_REG32_BIT(I2Cx->SLR0, I2C_SLR0_SLADDR0EN); + } + return i32Ret; +} + +/** + * @brief I2C slave address config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] u32AddrMode Address mode configuration @ref I2C_Addr_Config + * @param [in] u32Addr The slave address + * @retval None + */ +void I2C_SlaveAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_I2C_ADDR(u32AddrMode, u32Addr)); + + if (I2C_ADDR_DISABLE == u32AddrMode) { + CLR_REG32_BIT(*pu32SLRx, I2C_SLR0_SLADDR0EN); + } else { + if (I2C_ADDR_10BIT == u32AddrMode) { + MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN | I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0, + u32AddrMode | u32Addr); + } else { + MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN | I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0, + u32AddrMode | (u32Addr << 1U)); + } + } +} + +/** + * @brief I2C slave address config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SlaveAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(*pu32SLRx, I2C_SLR0_SLADDR0EN, (uint32_t)enNewState << I2C_SLR0_SLADDR0EN_POS); +} + +/** + * @brief I2C slave address mask function config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] u32AddrMode Address mode configuration @ref I2C_Addr_Config + * @param [in] u32MaskAddr The slave mask address + * @retval None + */ +void I2C_SlaveMaskAddrConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32MaskAddr) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_I2C_ADDR(u32AddrMode, u32MaskAddr)); + + if (I2C_ADDR_10BIT == u32AddrMode) { + MODIFY_REG32(*pu32SLRx, I2C_SLR0_ADDRMOD0 | I2C_SLR0_MSLADDR0, + u32AddrMode | (u32MaskAddr << I2C_SLR0_MSLADDR0_POS)); + } else { + MODIFY_REG32(*pu32SLRx, I2C_SLR0_ADDRMOD0 | I2C_SLR0_MSLADDR0, + u32AddrMode | (u32MaskAddr << (I2C_SLR0_MSLADDR0_POS + 1U))); + } +} + +/** + * @brief I2C mask slave address function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SlaveMaskAddrCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState) +{ + __IO uint32_t *const pu32SLRx = (__IO uint32_t *)((uint32_t)&I2Cx->SLR0 + (u32AddrNum * 4UL)); + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(*pu32SLRx, I2C_SLR0_MASKEN0, (uint32_t)enNewState << I2C_SLR0_MASKEN0_POS); +} + +/** + * @brief I2C function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_PE, (uint32_t)enNewState << I2C_CR1_PE_POS); +} + +/** + * @brief I2C fast ACK config + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_FastAckCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (ENABLE == enNewState) { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } else { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } +} + +/** + * @brief I2C bus wait function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_BusWaitCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } else { + CLR_REG32_BIT(I2Cx->CR4, I2C_CR4_BUSWAIT); + } +} + +/** + * @brief I2C SMBUS function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32SmbusConfig Indicate the SMBUS address match function configuration. @ref I2C_Smbus_Match_Config + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_SMBUS_CONFIG(u32SmbusConfig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } else { + CLR_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } +} + +/** + * @brief I2C SMBUS function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SmbusCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SMBUS, (uint32_t)enNewState << I2C_CR1_SMBUS_POS); +} + +/** + * @brief I2C digital filter function configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32FilterClock Chose the digital filter clock, @ref I2C_Digital_Filter_Clock + * @retval None + */ +void I2C_DigitalFilterConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32FilterClock) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_DIG_FILTER_CLK(u32FilterClock)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNF, u32FilterClock); +} + +/** + * @brief I2C digital filter command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_DigitalFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNFEN, (uint32_t)enNewState << I2C_FLTR_DNFEN_POS); +} + +/** + * @brief I2C analog filter function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_AnalogFilterCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_ANFEN, (uint32_t)enNewState << I2C_FLTR_ANFEN_POS); +} + +/** + * @brief I2C general call command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_GeneralCallCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ENGC, (uint32_t)enNewState << I2C_CR1_ENGC_POS); +} + +/** + * @brief I2C flags status get + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specify the flags to check, This parameter can be any combination of the member from + * @ref I2C_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t I2C_GetStatus(const CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_FLAG(u32Flag)); + + return ((0UL != READ_REG32_BIT(I2Cx->SR, u32Flag)) ? SET : RESET); +} + +/** + * @brief Clear I2C flags + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Flag Specifies the flag to clear, This parameter can be any combination of the member from + * @ref I2C_Flag_Clear + * @retval None + */ +void I2C_ClearStatus(CM_I2C_TypeDef *I2Cx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_CLR_FLAG(u32Flag)); + + WRITE_REG32(I2Cx->CLR, u32Flag); +} + +/** + * @brief I2C FIFO function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_FIFO_Cmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + MODIFY_REG32(I2Cx->FSTR, I2C_FSTR_FEN, (uint32_t)enNewState << I2C_FSTR_FEN_POS); +} + +/** + * @brief I2C Get Transfer FIFO data number + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval uint32_t The transfer FIFO data number + */ +uint32_t I2C_FIFO_GetTxDataNum(const CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + return ((READ_REG32_BIT(I2Cx->SR, I2C_SR_TFST) >> I2C_SR_TFST_POS)); +} + +/** + * @brief I2C get receive FIFO data status + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval uint32_t The FIFO data status @ref I2C_FIFO_Data_Status + */ +uint32_t I2C_FIFO_GetRxDataStatus(const CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + return ((READ_REG32_BIT(I2Cx->FSTR, I2C_FSTR_RFST) >> I2C_FSTR_RFST_POS)); +} + +/** + * @brief I2C get transfer FIFO data status + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval uint32_t The FIFO data status @ref I2C_FIFO_Data_Status + */ +uint32_t I2C_FIFO_GetTxDataStatus(const CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + return ((READ_REG32_BIT(I2Cx->FSTR, I2C_FSTR_TFST) >> I2C_FSTR_TFST_POS)); +} + +/** + * @brief I2C FIFO NACK reset transfer FIFO function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_FIFO_NackResetFIFOCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + MODIFY_REG32(I2Cx->FSTR, I2C_FSTR_NACKTFFLUSH, (uint32_t)enNewState << I2C_FSTR_NACKTFFLUSH_POS); +} + +/** + * @brief I2C flush transfer FIFO + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_FIFO_TxFlush(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->FSTR, I2C_FSTR_TFFLUSH); + CLR_REG32_BIT(I2Cx->FSTR, I2C_FSTR_TFFLUSH); +} + +/** + * @brief I2C flush receive FIFO + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval None + */ +void I2C_FIFO_RxFlush(CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + SET_REG32_BIT(I2Cx->FSTR, I2C_FSTR_RFFLUSH); + CLR_REG32_BIT(I2Cx->FSTR, I2C_FSTR_RFFLUSH); +} + +/** + * @brief I2C Bus free clear function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_BusFreeClearCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + MODIFY_REG32(I2Cx->CR4, I2C_CR4_BUSFREECLREN, (uint32_t)enNewState << I2C_CR4_BUSFREECLREN_POS); +} + +/** + * @brief I2C software reset function command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SWResetCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SWRST, (uint32_t)enNewState << I2C_CR1_SWRST_POS); +} + +/** + * @brief I2C interrupt command + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32IntType Specifies the I2C interrupts @ref I2C_Int_Flag + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_IntCmd(CM_I2C_TypeDef *I2Cx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR2, u32IntType); + } else { + CLR_REG32_BIT(I2Cx->CR2, u32IntType); + } +} + +/** + * @brief I2C send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u8Data The data to be send + * @retval None + */ +void I2C_WriteData(CM_I2C_TypeDef *I2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + WRITE_REG8(I2Cx->DTR, u8Data); +} + +/** + * @brief I2C read data from register + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @retval uint8_t The value of the received data + */ +uint8_t I2C_ReadData(const CM_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + return READ_REG8(I2Cx->DRR); +} + +/** + * @brief I2C ACK status configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32AckConfig I2C ACK configure. @ref I2C_Ack_Config + * @retval None + */ +void I2C_AckConfig(CM_I2C_TypeDef *I2Cx, uint32_t u32AckConfig) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_ACK_CONFIG(u32AckConfig)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ACK, u32AckConfig); +} + +/** + * @brief I2C SCL high level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutH Clock timeout period for high level + * @retval None + */ +void I2C_SCLHighTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutH) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTHIGH, (uint32_t)u16TimeoutH << I2C_SLTR_TOUTHIGH_POS); +} + +/** + * @brief I2C SCL low level timeout configuration + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16TimeoutL Clock timeout period for low level + * @retval None + */ +void I2C_SCLLowTimeoutConfig(CM_I2C_TypeDef *I2Cx, uint16_t u16TimeoutL) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + MODIFY_REG32(I2Cx->SLTR, I2C_SLTR_TOUTLOW, u16TimeoutL); +} + +/** + * @brief Enable or disable I2C SCL high level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLHighTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL low level timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLLowTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL timeout function + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void I2C_SCLTimeoutCmd(CM_I2C_TypeDef *I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } else { + CLR_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } +} + +/** + * @brief I2Cx start + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Start(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_BUSY, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* generate start signal */ + I2C_GenerateStart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief I2Cx restart + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Restart(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_BUSY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Clear start status flag */ + I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_START); + /* Send restart condition */ + I2C_GenerateRestart(I2Cx); + /* Judge if start success*/ + i32Ret = I2C_WaitStatus(I2Cx, (I2C_FLAG_BUSY | I2C_FLAG_START), SET, u32Timeout); + } + + return i32Ret; +} + +/** + * @brief I2Cx send address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction, @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_TransAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_7BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Send I2C address */ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr << 1U) | u8Dir); + + if (I2C_DIR_TX == u8Dir) { + /* If in master transfer process, Need wait transfer end */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + } else { + /* If in master receive process, wait I2C_FLAG_TRA changed to receive */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + } + + if (i32Ret == LL_OK) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send 10 bit address + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u16Addr The address to be sent + * @param [in] u8Dir Transfer direction @ref I2C_Trans_Dir + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR: NACK received + */ +int32_t I2C_Trans10BitAddr(CM_I2C_TypeDef *I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + DDL_ASSERT(IS_I2C_TRANS_DIR(u8Dir)); + DDL_ASSERT(IS_I2C_10BIT_ADDR(u16Addr)); + + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_TX); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive ACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == RESET) { + /* Write SLA(bit7:0)*/ + I2C_WriteData(I2Cx, (uint8_t)(u16Addr & 0xFFU)); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + if (LL_OK == i32Ret) { + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } else { + i32Ret = LL_ERR; + } + } + } + + if ((u8Dir == I2C_DIR_RX) && (LL_OK == i32Ret)) { + /* Restart */ + I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_START); + I2C_GenerateRestart(I2Cx); + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_START, SET, u32Timeout); + + if (LL_OK == i32Ret) { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteData(I2Cx, (uint8_t)((u16Addr >> 7U) & 0x06U) | 0xF0U | I2C_DIR_RX); + /* If in master receive process, Need wait TRA flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TRA, RESET, u32Timeout); + + if (LL_OK == i32Ret) { + /* If receive NACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + i32Ret = LL_ERR; + } + } + } + } + + return i32Ret; +} + +/** + * @brief I2Cx send data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] au8TxData The data array to be sent + * @param [in] u32Size Number of data in array pau8TxData + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_TransData(CM_I2C_TypeDef *I2Cx, uint8_t const au8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Count = 0UL; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8TxData != NULL) { + while ((u32Count != u32Size) && (i32Ret == LL_OK)) { + /* Wait tx buffer empty */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_EMPTY, SET, u32Timeout); + + if (i32Ret == LL_OK) { + /* Send one byte data */ + I2C_WriteData(I2Cx, au8TxData[u32Count]); + + /* Wait transfer end */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_TX_CPLT, SET, u32Timeout); + + /* If receive NACK */ + if (I2C_GetStatus(I2Cx, I2C_FLAG_NACKF) == SET) { + break; + } + u32Count++; + } + } + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_ReceiveData(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx receive data and stop(for master) + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [out] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_MasterReceiveDataAndStop(CM_I2C_TypeDef *I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + uint32_t i; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + if (au8RxData != NULL) { + uint32_t u32FastAckDis = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + + for (i = 0UL; i < u32Size; i++) { + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_RX_FULL, SET, u32Timeout); + + if (0UL == u32FastAckDis) { + if ((u32Size >= 2UL) && (i == (u32Size - 2UL))) { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } else { + if (i != (u32Size - 1UL)) { + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if (i32Ret == LL_OK) { + /* Stop before read last data */ + if (i == (u32Size - 1UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_STOP); + I2C_GenerateStop(I2Cx); + } + /* read data from register */ + au8RxData[i] = I2C_ReadData(I2Cx); + + if (i == (u32Size - 1UL)) { + /* Wait stop flag after DRR read */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + } + } else { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } else { + i32Ret = LL_ERR_INVD_PARAM; + } + + return i32Ret; +} + +/** + * @brief I2Cx stop + * @param [in] I2Cx Pointer to I2C instance register base. + * This parameter can be a value of the following: + * @arg CM_I2C or CM_I2Cx: I2C instance register base. + * @param [in] u32Timeout Maximum count of trying to get a status of a flag in status register + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_TIMEOUT: Failed + */ +int32_t I2C_Stop(CM_I2C_TypeDef *I2Cx, uint32_t u32Timeout) +{ + int32_t i32Ret; + + DDL_ASSERT(IS_I2C_UNIT(I2Cx)); + + /* Clear stop flag */ + while ((SET == I2C_GetStatus(I2Cx, I2C_FLAG_STOP)) && (u32Timeout > 0UL)) { + I2C_ClearStatus(I2Cx, I2C_FLAG_CLR_STOP); + u32Timeout--; + } + I2C_GenerateStop(I2Cx); + /* Wait stop flag */ + i32Ret = I2C_WaitStatus(I2Cx, I2C_FLAG_STOP, SET, u32Timeout); + + return i32Ret; +} + +/** + * @brief Initialize structure stc_i2c_init_t variable with default value. + * @param [out] pstcI2cInit Pointer to a stc_i2c_init_t structure variable which will be initialized. + * @ref stc_i2c_init_t. + * @retval int32_t + * - LL_OK: Success + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t I2C_StructInit(stc_i2c_init_t *pstcI2cInit) +{ + int32_t i32Ret = LL_OK; + if (pstcI2cInit == NULL) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcI2cInit->u32Baudrate = 50000UL; + pstcI2cInit->u32SclTime = 0UL; + pstcI2cInit->u32ClockDiv = I2C_CLK_DIV1; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_I2C_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c new file mode 100644 index 0000000000..c1355e23ae --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_icg.c @@ -0,0 +1,138 @@ +/** + ******************************************************************************* + * @file hc32_ll_icg.c + * @brief This file provides firmware functions to manage the Initial + * Configuration(ICG). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_icg.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_ICG ICG + * @brief Initial Configuration Driver Library + * @{ + */ + +#if (LL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Local_Macros ICG Local Macros + * @{ + */ + +/** + * @brief ICG Start Address + */ +#define ICG_START_ADDR 0x400 +#define ICG_START_ADDR_AC6 ".ARM.__at_0x400" + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @brief ICG parameters configuration + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +const uint32_t u32ICGValue[] __attribute__((section(ICG_START_ADDR_AC6))) = +#elif defined (__GNUC__) && !defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICGValue[] __attribute__((at(ICG_START_ADDR))) = +#elif defined (__ICCARM__) +#pragma location = ICG_START_ADDR +__root static const uint32_t u32ICGValue[] = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~1 */ + ICG_REG_CFG0_CONST, + ICG_REG_CFG1_CONST, + /* ICG 2~4 */ + ICG_REG_CFG2_CONST, + ICG_REG_CFG3_CONST, + ICG_REG_CFG4_CONST, + /* Reserved 0~3 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 4~7 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 8~11 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 12~15 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + /* Reserved 16~18 */ + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, + ICG_REG_RESV_CONST, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +#endif /* LL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c new file mode 100644 index 0000000000..22b5f99ff5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_interrupts.c @@ -0,0 +1,764 @@ +/** + ******************************************************************************* + * @file hc32_ll_interrupts.c + * @brief This file provides firmware functions to manage the Interrupt Controller + * (INTC). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Remove space line + 2023-12-15 CDT Add API INTC_GetIntSrcState() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_interrupts.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_INTERRUPTS INTERRUPTS + * @brief INTC Driver Library + * @{ + */ + +#if (LL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Macros INTC Local Macros + * @{ + */ +/** + * @brief Maximum IRQ handler number + */ +#define IRQ_NUM_MAX (16U) +#define IRQn_MIN (INT000_IRQn) +#define IRQn_MAX (INT015_IRQn) +#define IRQn_OFFSET (0U) +#define EXTINT_CH_NUM_MAX (16U) +#define EIRQCFR_REG (CM_INTC->EIFCR) +#define EIRQFR_REG (CM_INTC->EIFR) +#define NMIENR_REG (CM_INTC->NMIER) +#define NMICFR_REG (CM_INTC->NMIFCR) +#define INTSEL_REG (uint32_t)(&CM_INTC->INTSEL0) +#define INTWKEN_REG (CM_INTC->WKEN) +#define INTSEL_RST_VALUE (0x1FFUL) +#define INTEN_REG_MOD (32U) + +/** + * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for wakeup source from stop mode. */ +#define IS_INTC_WKUP_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | INTC_WUPEN_ALL) == INTC_WUPEN_ALL)) + +/*! Parameter validity check for event index. */ +#define IS_INTC_EVT(event) \ +( ((event) != 0x00UL) && \ + (((event) | INTC_EVT_ALL) == INTC_EVT_ALL)) + +/*! Parameter validity check for interrupt index. */ +#define IS_INTC_INT(it) \ +( ((it) != 0x00UL) && \ + (((it) | INTC_INT_ALL) == INTC_INT_ALL)) + +/*! Parameter validity check for software interrupt index. */ +#define IS_INTC_SWI(swi) \ +( ((swi) != 0x00UL) && \ + (((swi) | SWINT_ALL) == SWINT_ALL)) + +/*! Parameter validity check for NMI trigger source. */ +#define IS_NMI_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | NMI_SRC_ALL) == NMI_SRC_ALL)) + +/*! Parameter validity check for EXTINT filter A function. */ +#define IS_EXTINT_FAE(fae) \ +( ((fae) == EXTINT_FILTER_OFF) || \ + ((fae) == EXTINT_FILTER_ON)) + +/*! Parameter validity check for EXTINT filter A clock division. */ +#define IS_EXTINT_FACLK(faclk) \ +( ((faclk) == EXTINT_FCLK_DIV1) || \ + ((faclk) == EXTINT_FCLK_DIV8) || \ + ((faclk) == EXTINT_FCLK_DIV32) || \ + ((faclk) == EXTINT_FCLK_DIV64)) + +/*! Parameter validity check for EXTINT filter B function. */ +#define IS_NMI_EXTINT_FBE(fbe) \ +( ((fbe) == NMI_EXTINT_FILTER_B_OFF) || \ + ((fbe) == NMI_EXTINT_FILTER_B_ON)) + +/*! Parameter validity check for EXTINT filter B time. */ +#define IS_NMI_EXTINT_FBTIME(fbtime) \ +( ((fbtime) == NMI_EXTINT_FCLK_B_500NS) || \ + ((fbtime) == NMI_EXTINT_FCLK_B_1US) || \ + ((fbtime) == NMI_EXTINT_FCLK_B_2US) || \ + ((fbtime) == NMI_EXTINT_FCLK_B_4US)) + +/*! Parameter validity check for EXTINT trigger edge. */ +#define IS_EXTINT_TRIG(trigger) \ +( ((trigger) == EXTINT_TRIG_LOW) || \ + ((trigger) == EXTINT_TRIG_RISING) || \ + ((trigger) == EXTINT_TRIG_FALLING) || \ + ((trigger) == EXTINT_TRIG_BOTH)) + +/*! Parameter validity check for EXTINT channel. */ +#define IS_EXTINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXTINT_CH_ALL) == EXTINT_CH_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Variable INTC Local Variable + * @{ + */ +static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL}; +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Functions INTC Global Functions + * @{ + */ +/** + * @brief IRQ sign in function + * @param [in] pstcIrqSignConfig: pointer of IRQ registration structure + * @arg enIntSrc: can be any value @ref en_int_src_t + * @arg enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @arg pfnCallback: Callback function + * @retval int32_t: + * - LL_OK: IRQ register successfully + * - LL_ERR_INVD_PARAM: IRQ No. and Peripheral Int source are not match; NULL pointer. + * - LL_ERR_UNINIT: Specified IRQ entry was signed before. + */ +int32_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcIrqSignConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(pstcIrqSignConfig->enIntSrc <= INT_SRC_MAX); + if (pstcIrqSignConfig->enIRQn > INT015_IRQn) { + i32Ret = LL_ERR_INVD_PARAM; + } + + else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4U * (uint32_t)(pstcIrqSignConfig->enIRQn))); + /* for MISRAC2004-12.4 */ + if (INTSEL_RST_VALUE == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else if ((uint32_t)(pstcIrqSignConfig->enIntSrc) == ((*INTC_SELx) & INTSEL_RST_VALUE)) { + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } else { + i32Ret = LL_ERR_UNINIT; + } + } + } + return i32Ret; +} + +/** + * @brief IRQ sign out function + * @param [in] enIRQn: can be any value from IRQn_MIN ~ IRQn_MAX for different product + * @retval int32_t: + * - LL_OK: IRQ sign out successfully + * - LL_ERR_INVD_PARAM: IRQ No. is out of range + */ +int32_t INTC_IrqSignOut(IRQn_Type enIRQn) +{ + __IO uint32_t *INTC_SELx; + int32_t i32Ret = LL_OK; + + if ((enIRQn < IRQn_MIN) || (enIRQn > IRQn_MAX)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + INTC_SELx = (__IO uint32_t *)(INTSEL_REG + (4UL * (uint32_t)enIRQn)); + WRITE_REG32(*INTC_SELx, INTSEL_RST_VALUE); + m_apfnIrqHandler[(uint8_t)enIRQn - IRQn_OFFSET] = NULL; + } + return i32Ret; +} + +/** + * @brief Stop mode wake-up source configure + * @param [in] u32WakeupSrc: Wake-up source, @ref INTC_Stop_Wakeup_Source_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_WKUP_SRC(u32WakeupSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(INTWKEN_REG, u32WakeupSrc); + } else { + CLR_REG32_BIT(INTWKEN_REG, u32WakeupSrc); + } +} + +/** + * @brief Event or Interrupt output configure + * @param [in] u32Event: Event index, @ref INTC_Event_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_EVT(u32Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->EVTER, u32Event); + } else { + CLR_REG32_BIT(CM_INTC->EVTER, u32Event); + } +} + +/** + * @brief Interrupt function configure + * @param [in] u32Int: Interrupt index, @ref INT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_INT(u32Int)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->IER, u32Int); + } else { + CLR_REG32_BIT(CM_INTC->IER, u32Int); + } +} + +/** + * @brief Software Interrupt initialize function + * @param [in] u32Ch: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] pfnCallback: Callback function + * @param [in] u32Priority: Software interrupt priority + * @retval None + */ +void INTC_SWIntInit(uint32_t u32Ch, const func_ptr_t pfnCallback, uint32_t u32Priority) +{ + stc_irq_signin_config_t stcIrqSignConfig; + + stcIrqSignConfig.enIRQn = (IRQn_Type)(__CLZ(__RBIT(u32Ch))); + (void)(pfnCallback); + + NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn); + NVIC_SetPriority(stcIrqSignConfig.enIRQn, u32Priority); + NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); +} + +/** + * @brief Software Interrupt function configure + * @param [in] u32SWInt: Software Interrupt channel, @ref SWINT_Channel_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_SWIntCmd(uint32_t u32SWInt, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_SWI(u32SWInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } else { + CLR_REG32_BIT(CM_INTC->SWIER, u32SWInt); + } +} + +/** + * @brief Initialize NMI. Fill each pstcNmiInit with default value + * @param [in] pstcNmiInit: Pointer to a stc_nmi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcNmiInit->u32Src = 0UL; + } + return i32Ret; +} + +/** + * @brief Initialize NMI. + * @param [in] pstcNmiInit: Pointer to a pstcNmiInit structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: NMI initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t NMI_Init(const stc_nmi_init_t *pstcNmiInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(pstcNmiInit->u32Src)); + /* Clear all NMI trigger source before set */ + WRITE_REG32(NMICFR_REG, NMI_SRC_ALL); + + /* NMI trigger source configure */ + WRITE_REG32(NMIENR_REG, pstcNmiInit->u32Src); + + } + return i32Ret; +} + +/** + * @brief Get NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t NMI_GetNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + return (((READ_REG32(CM_INTC->NMIFR) & u32Src)) != 0UL) ? SET : RESET; +} + +/** + * @brief Set NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void NMI_NmiSrcCmd(uint32_t u32Src, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(NMIENR_REG, u32Src); + } else { + CLR_REG32_BIT(NMIENR_REG, u32Src); + } +} + +/** + * @brief Clear specified NMI trigger source + * @param [in] u32Src: NMI trigger source, @ref NMI_TriggerSrc_Sel for diff. MCU in details + * @retval None + */ +void NMI_ClearNmiStatus(uint32_t u32Src) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32Src)); + + SET_REG32_BIT(NMICFR_REG, u32Src); +} + +/** + * @brief Initialize External interrupt. + * @param [in] u32Ch: ExtInt channel. + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_Init(uint32_t u32Ch, const stc_extint_init_t *pstcExtIntInit) +{ + uint8_t u8ExtIntPos; + int32_t i32Ret = LL_OK; + uint32_t EIRQCRVal; + __IO uint32_t *EIRQCRx; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32Ch)); + DDL_ASSERT(IS_EXTINT_FAE(pstcExtIntInit->u32Filter)); + DDL_ASSERT(IS_EXTINT_FACLK(pstcExtIntInit->u32FilterClock)); + DDL_ASSERT(IS_EXTINT_TRIG(pstcExtIntInit->u32Edge)); + DDL_ASSERT(IS_NMI_EXTINT_FBE(pstcExtIntInit->u32FilterB)); + DDL_ASSERT(IS_NMI_EXTINT_FBTIME(pstcExtIntInit->u32FilterBClock)); + for (u8ExtIntPos = 0U; u8ExtIntPos < EXTINT_CH_NUM_MAX; u8ExtIntPos++) { + if (0UL != (u32Ch & (1UL << u8ExtIntPos))) { + EIRQCRVal = pstcExtIntInit->u32Filter | pstcExtIntInit->u32FilterClock | \ + pstcExtIntInit->u32Edge; + EIRQCRVal |= (pstcExtIntInit->u32FilterB | pstcExtIntInit->u32FilterBClock); + EIRQCRx = (__IO uint32_t *)((uint32_t)&CM_INTC->EIRQCR0 + 4UL * u8ExtIntPos); + WRITE_REG32(*EIRQCRx, EIRQCRVal); + } + } + } + return i32Ret; +} + +/** + * @brief Initialize ExtInt. Fill each pstcExtIntInit with default value + * @param [in] pstcExtIntInit: Pointer to a stc_extint_init_t structure + * that contains configuration information. + * @retval int32_t: + * - LL_OK: EXTINT structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t EXTINT_StructInit(stc_extint_init_t *pstcExtIntInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcExtIntInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Configure to default value */ + pstcExtIntInit->u32Filter = EXTINT_FILTER_OFF; + pstcExtIntInit->u32FilterClock = EXTINT_FCLK_DIV1; + pstcExtIntInit->u32Edge = EXTINT_TRIG_FALLING; + pstcExtIntInit->u32FilterB = NMI_EXTINT_FILTER_B_OFF; + pstcExtIntInit->u32FilterBClock = NMI_EXTINT_FCLK_B_500NS; + } + return i32Ret; +} + +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval None + */ +void EXTINT_ClearExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + SET_REG32_BIT(EIRQCFR_REG, u32ExtIntCh); +} + +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExtIntCh: External interrupt channel, @ref EXTINT_Channel_Sel for details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t EXTINT_GetExtIntStatus(uint32_t u32ExtIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXTINT_CH(u32ExtIntCh)); + + return ((READ_REG16(EIRQFR_REG) & u32ExtIntCh) != 0U) ? SET : RESET; +} + +/** + * @brief Interrupt source interrupt function configure + * @param [in] enIntSrc: Interrupt source, can be any value @ref en_int_src_t + * @param [in] enNewState: An @ref en_functional_state_t enumeration value. + * @retval None + */ +void INTC_IntSrcCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState) +{ + __IO uint32_t *INTENx; + + /* Parameter validity checking */ + DDL_ASSERT(enIntSrc <= INT_SRC_MAX); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + INTENx = (__IO uint32_t *)((uint32_t)&CM_INTC->INTEN0 + 4UL * ((uint32_t)enIntSrc / INTEN_REG_MOD)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*INTENx, 1UL << ((uint32_t)enIntSrc & 0x1FU)); + } else { + CLR_REG32_BIT(*INTENx, 1UL << ((uint32_t)enIntSrc & 0x1FU)); + } +} + +/** + * @brief Get interrupt source interrupt status + * @param [in] enIntSrc: Interrupt source, can be any value @ref en_int_src_t + * @retval An @ref en_functional_state_t enumeration type value. + */ +en_functional_state_t INTC_GetIntSrcState(en_int_src_t enIntSrc) +{ + __IO uint32_t *INTENx; + + /* Parameter validity checking */ + DDL_ASSERT(enIntSrc <= INT_SRC_MAX); + + INTENx = (__IO uint32_t *)((uint32_t)&CM_INTC->INTEN0 + 4UL * ((uint32_t)enIntSrc / INTEN_REG_MOD)); + + return ((*INTENx & (1UL << ((uint32_t)enIntSrc & 0x1FU))) != 0UL) ? ENABLE : DISABLE; +} + +/** + * @brief Interrupt No.000 IRQ handler + * @param None + * @retval None + */ +void IRQ000_Handler(void) +{ + m_apfnIrqHandler[INT000_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.001 IRQ handler + * @param None + * @retval None + */ +void IRQ001_Handler(void) +{ + m_apfnIrqHandler[INT001_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.002 IRQ handler + * @param None + * @retval None + */ +void IRQ002_Handler(void) +{ + m_apfnIrqHandler[INT002_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.003 IRQ handler + * @param None + * @retval None + */ +void IRQ003_Handler(void) +{ + m_apfnIrqHandler[INT003_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.004 IRQ handler + * @param None + * @retval None + */ +void IRQ004_Handler(void) +{ + m_apfnIrqHandler[INT004_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.005 IRQ handler + * @param None + * @retval None + */ +void IRQ005_Handler(void) +{ + m_apfnIrqHandler[INT005_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.006 IRQ handler + * @param None + * @retval None + */ +void IRQ006_Handler(void) +{ + m_apfnIrqHandler[INT006_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.007 IRQ handler + * @param None + * @retval None + */ +void IRQ007_Handler(void) +{ + m_apfnIrqHandler[INT007_IRQn](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.008 IRQ handler + * @param None + * @retval None + */ +void IRQ008_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT008_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.009 IRQ handler + * @param None + * @retval None + */ +void IRQ009_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT009_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.010 IRQ handler + * @param None + * @retval None + */ +void IRQ010_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT010_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.011 IRQ handler + * @param None + * @retval None + */ +void IRQ011_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT011_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.012 IRQ handler + * @param None + * @retval None + */ +void IRQ012_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT012_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.013 IRQ handler + * @param None + * @retval None + */ +void IRQ013_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT013_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.014 IRQ handler + * @param None + * @retval None + */ +void IRQ014_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT014_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @brief Interrupt No.015 IRQ handler + * @param None + * @retval None + */ +void IRQ015_Handler(void) +{ + m_apfnIrqHandler[(uint32_t)INT015_IRQn - IRQn_OFFSET](); + /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ + __DSB(); +} + +/** + * @} + */ + +#endif /* LL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c new file mode 100644 index 0000000000..63334751fc --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_keyscan.c @@ -0,0 +1,257 @@ +/** + ******************************************************************************* + * @file hc32_ll_keyscan.c + * @brief This file provides firmware functions to manage the matrix keyscan + * function (KEYSCAN). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_keyscan.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_KEYSCAN KEYSCAN + * @brief Matrix keyscan Driver Library + * @{ + */ + +#if (LL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Local_Macros KEYSCAN Local Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Check_Parameters_Validity KEYSCAN Check Parameters Validity + * @{ + */ +/*! Parameter valid check for KEYSCAN HiZ state cycles. */ +#define IS_KEYSCAN_HIZ_CYCLE(clc) \ +( ((clc) == KEYSCAN_HIZ_CYCLE_4) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_8) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_16) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_32) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_64) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_256) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_512) || \ + ((clc) == KEYSCAN_HIZ_CYCLE_1024)) + +/*! Parameter valid check for KEYSCAN low level output cycles. */ +#define IS_KEYSCAN_LOW_CYCLE(clc) \ +( ((clc) == KEYSCAN_LOW_CYCLE_4) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_32K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_64K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_128K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_256K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_512K) || \ + ((clc) == KEYSCAN_LOW_CYCLE_1M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_2M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_4M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_8M) || \ + ((clc) == KEYSCAN_LOW_CYCLE_16M)) + +/*! Parameter valid check for KEYSCAN scan clock. */ +#define IS_KEYSCAN_CLK(clk) \ +( ((clk) == KEYSCAN_CLK_HCLK) || \ + ((clk) == KEYSCAN_CLK_LRC) || \ + ((clk) == KEYSCAN_CLK_XTAL32)) + +/*! Parameter valid check for KEYSCAN keyout pins. */ +#define IS_KEYSCAN_OUT(out) \ +( ((out) == KEYSCAN_OUT_0T1) || \ + ((out) == KEYSCAN_OUT_0T2) || \ + ((out) == KEYSCAN_OUT_0T3) || \ + ((out) == KEYSCAN_OUT_0T4) || \ + ((out) == KEYSCAN_OUT_0T5) || \ + ((out) == KEYSCAN_OUT_0T6) || \ + ((out) == KEYSCAN_OUT_0T7)) + +/*! Parameter valid check for KEYSCAN keyin(EIRQ) pins. */ +#define IS_KEYSCAN_IN(in) \ +( ((in) != 0x00U) && \ + (((in) | KEYSCAN_IN_ALL) == KEYSCAN_IN_ALL)) + +/** + * @} + */ + +#define KEYSCAN_RMU_TIMEOUT (100U) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Functions KEYSCAN Global Functions + * @{ + */ + +/** + * @brief KEYSCAN function config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void KEYSCAN_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(CM_KEYSCAN->SER, enNewState); +} + +/** + * @brief Initialize KEYSCAN config structure. Fill each pstcKeyscanInit with default value + * @param [in] pstcKeyscanInit Pointer to a stc_keyscan_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: KEYSCAN structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcKeyscanInit->u32HizCycle = KEYSCAN_HIZ_CYCLE_4; + pstcKeyscanInit->u32LowCycle = KEYSCAN_LOW_CYCLE_4; + pstcKeyscanInit->u32KeyClock = KEYSCAN_CLK_HCLK; + pstcKeyscanInit->u32KeyOut = KEYSCAN_OUT_0T1; + pstcKeyscanInit->u32KeyIn = KEYSCAN_IN_0; + } + return i32Ret; +} + +/** + * @brief KEYSCAN initialize. + * @param [in] pstcKeyscanInit KEYSCAN config structure. + * @arg u32HizCycle Hiz state keep cycles during low level output. + * @arg u32LowCycle Low level output cycles. + * @arg u32KeyClock Scan clock. + * @arg u32KeyOut KEYOUT selection. + * @arg u32KeyIn KEYIN(EIRQ) selection. + * @retval int32_t: + * - LL_OK: KEYSCAN function initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcKeyscanInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_KEYSCAN_HIZ_CYCLE(pstcKeyscanInit->u32HizCycle)); + DDL_ASSERT(IS_KEYSCAN_LOW_CYCLE(pstcKeyscanInit->u32LowCycle)); + DDL_ASSERT(IS_KEYSCAN_CLK(pstcKeyscanInit->u32KeyClock)); + DDL_ASSERT(IS_KEYSCAN_OUT(pstcKeyscanInit->u32KeyOut)); + DDL_ASSERT(IS_KEYSCAN_IN(pstcKeyscanInit->u32KeyIn)); + + WRITE_REG32(CM_KEYSCAN->SCR, \ + (pstcKeyscanInit->u32HizCycle | pstcKeyscanInit->u32LowCycle | \ + pstcKeyscanInit->u32KeyClock | pstcKeyscanInit->u32KeyOut | \ + pstcKeyscanInit->u32KeyIn)); + } + return i32Ret; +} + +/** + * @brief De-initialize the KEYSCAN. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success. + * - LL_ERR_TIMEOUT: Timeout + */ +int32_t KEYSCAN_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0); + + /* Reset KEYSCAN */ + WRITE_REG32(bCM_RMU->FRST0_b.KEY, 0UL); + + /* Ensure reset procedure is completed */ + while (0UL == READ_REG32(bCM_RMU->FRST0_b.KEY)) { + u8TimeOut++; + if (u8TimeOut > KEYSCAN_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_mcan.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_mcan.c new file mode 100644 index 0000000000..515011a568 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_mcan.c @@ -0,0 +1,2883 @@ +/** + ******************************************************************************* + * @file hc32_ll_mcan.c + * @brief This file provides firmware functions to manage the MCAN. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Optimized driver: + 1. Integrated stc_mcan_classic_config_t and stc_mcan_fd_config_t into stc_mcan_bit_time_config_t + 2. Integrated u32FdIso into u32FrameFormat. + 3. Removed API MCAN_SetFdIsoOperation(), added API MCAN_SetFrameFormat(). + 4. Optimized the handling of the parameter stc_mcan_filter_t.u32FilterIndex + 5. Add 5 APIs for better get protocol status(register PSR): + MCAN_GetTdcValue(), MCAN_GetDataLastErrorCode(), MCAN_GetLastErrorCode(), + MCAN_GetComState(), MCAN_GetProtocolFlagStatus() + 6. Changed u8Activity of stc_mcan_protocol_status_t to u8ComState. + 7. Changed u8MsgStorageIndex of stc_mcan_hpm_status_t to u8MsgIndex. + 8. Optimized local function MCAN_FilterInitConfig() + 9. When the frame to be transmitted is a remote frame, do not write the data field to the message RAM. + When the received frame is a remote frame, do not read the data field from the message RAM. + Optimized comments. + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_mcan.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_MCAN MCAN + * @brief MCAN Driver Library + * @{ + */ + +#if (LL_MCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MCAN_Local_Macros MCAN Local Macros + * @{ + */ + +/** + * @defgroup MCAN_Private_Constants MCAN Private Constants + * @{ + */ +#define MCAN_TIMEOUT_COUNT (100U) +#define MCAN_TIMEOUT_VALUE (SystemCoreClock / 1000UL) + +#define MCAN_DATA_SIZE_MIN (MCAN_DATA_SIZE_8BYTE) +#define MCAN_DATA_SIZE_MAX (MCAN_DATA_SIZE_64BYTE) + +#define CAN20_DATA_SIZE_MAX (8U) + +#define MCAN_STD_FILTER_NUM_MAX (128U) +#define MCAN_EXT_FILTER_NUM_MAX (64U) +#define MCAN_RX_FIFO0_NUM_MAX (64U) +#define MCAN_RX_FIFO1_NUM_MAX (64U) +#define MCAN_RX_BUF_NUM_MAX (64U) +#define MCAN_TX_EVT_NUM_MAX (32U) +#define MCAN_TX_ELMT_NUM_MAX (32U) + +#define MCAN_FRAME_ESI_POS (31U) /*!< Position of Error State Indicator */ +#define MCAN_FRAME_ANMF_POS (31U) +#define MCAN_FRAME_XTD_POS (30U) /*!< Position of Extended ID */ +#define MCAN_FRAME_RTR_POS (29U) /*!< Position of Remote Transmission Request */ +#define MCAN_FRAME_MM_L_POS (24U) /*!< Position of Message Marker */ +#define MCAN_FRAME_FIDX_POS (24U) +#define MCAN_FRAME_EFC_POS (23U) +#define MCAN_FRAME_TSCE_POS (22U) +#define MCAN_FRAME_ET_POS (22U) /*!< Position of Event type */ +#define MCAN_FRAME_FDF_POS (21U) /*!< Position of FD Format */ +#define MCAN_FRAME_BRS_POS (20U) /*!< Position of Bit Rate Switch */ +#define MCAN_FRAME_STDID_POS (18U) /*!< Position of Standard ID */ +#define MCAN_FRAME_DLC_POS (16U) /*!< Position of Data Length Code */ +#define MCAN_FRAME_MM_H_POS (8U) /*!< Position of Message Marker */ + +#define MCAN_FRAME_ESI_MASK (1UL << MCAN_FRAME_ESI_POS) +#define MCAN_FRAME_ANMF_MASK (1UL << MCAN_FRAME_ANMF_POS) +#define MCAN_FRAME_XTD_MASK (1UL << MCAN_FRAME_XTD_POS) +#define MCAN_FRAME_RTR_MASK (1UL << MCAN_FRAME_RTR_POS) +#define MCAN_FRAME_MM_L_MASK (0xFFUL << MCAN_FRAME_MM_L_POS) +#define MCAN_FRAME_FIDX_MASK (0x7FUL << MCAN_FRAME_FIDX_POS) +#define MCAN_FRAME_EFC_MASK (1UL << MCAN_FRAME_EFC_POS) +#define MCAN_FRAME_TSCE_MASK (1UL << MCAN_FRAME_TSCE_POS) +#define MCAN_FRAME_ET_MASK (3UL << MCAN_FRAME_ET_POS) +#define MCAN_FRAME_FDF_MASK (1UL << MCAN_FRAME_FDF_POS) +#define MCAN_FRAME_BRS_MASK (1UL << MCAN_FRAME_BRS_POS) +#define MCAN_FRAME_STDID_MASK (MCAN_STD_ID_MASK << MCAN_FRAME_STDID_POS) +#define MCAN_FRAME_EXTID_MASK (MCAN_EXT_ID_MASK) +#define MCAN_FRAME_DLC_MASK (0xFUL << MCAN_FRAME_DLC_POS) +#define MCAN_FRAME_MM_H_MASK (0xFFUL << MCAN_FRAME_MM_H_POS) +#define MCAN_FRAME_TS_MASK (0x0000FFFFUL) + +#define MCAN_FILTER_SFTYPE_POS (30U) +#define MCAN_FILTER_SFCFG_POS (27U) +#define MCAN_FILTER_SFID1_POS (16U) +#define MCAN_FILTER_SFDBGMSG_POS (9U) + +#define MCAN_FILTER_EFTYPE_POS (30U) +#define MCAN_FILTER_EFCFG_POS (29U) + +/* Allocate start address of each part */ +#define MCAN_STD_FILTER_SA(u) (MCAN_MSG_RAM_BASE + READ_REG32_BIT((u)->SIDFC, MCAN_SIDFC_FLSSA)) +#define MCAN_EXT_FILTER_SA(u) (MCAN_MSG_RAM_BASE + READ_REG32_BIT((u)->XIDFC, MCAN_XIDFC_FLESA)) +#define MCAN_RX_FIFO0_SA(u) (MCAN_MSG_RAM_BASE + READ_REG32_BIT((u)->RXF0C, MCAN_RXF0C_F0SA)) +#define MCAN_RX_FIFO1_SA(u) (MCAN_MSG_RAM_BASE + READ_REG32_BIT((u)->RXF1C, MCAN_RXF1C_F1SA)) +#define MCAN_RX_BUF_SA(u) (MCAN_MSG_RAM_BASE + READ_REG32_BIT((u)->RXBC, MCAN_RXBC_RBSA)) +#define MCAN_TX_EVT_FIFO_SA(u) (MCAN_MSG_RAM_BASE + READ_REG32_BIT((u)->TXEFC, MCAN_TXEFC_EFSA)) +#define MCAN_TX_ELMT_SA(u) (MCAN_MSG_RAM_BASE + READ_REG32_BIT((u)->TXBC, MCAN_TXBC_TBSA)) + +/* Allocate number of each part */ +#define MCAN_GET_STD_FILTER_NUM(u) (READ_REG32_BIT((u)->SIDFC, MCAN_SIDFC_LSS) >> MCAN_SIDFC_LSS_POS) +#define MCAN_GET_EXT_FILTER_NUM(u) (READ_REG32_BIT((u)->XIDFC, MCAN_XIDFC_LSE) >> MCAN_XIDFC_LSE_POS) +#define MCAN_GET_RX_FIFO0_NUM(u) (READ_REG32_BIT((u)->RXF0C, MCAN_RXF0C_F0S) >> MCAN_RXF0C_F0S_POS) +#define MCAN_GET_RX_FIFO1_NUM(u) (READ_REG32_BIT((u)->RXF1C, MCAN_RXF1C_F1S) >> MCAN_RXF1C_F1S_POS) +#define MCAN_GET_TX_EVT_FIFO_NUM(u) (READ_REG32_BIT((u)->TXEFC, MCAN_TXEFC_EFS) >> MCAN_TXEFC_EFS_POS) +#define MCAN_GET_TX_BUF_NUM(u) (READ_REG32_BIT((u)->TXBC, MCAN_TXBC_NDTB) >> MCAN_TXBC_NDTB_POS) +#define MCAN_GET_TX_FQ_NUM(u) (READ_REG32_BIT((u)->TXBC, MCAN_TXBC_TFQS) >> MCAN_TXBC_TFQS_POS) + +/* Data field size */ +#define MCAN_RX_FIFO0_DS(u) (READ_REG32_BIT((u)->RXESC, MCAN_RXESC_F0DS)) +#define MCAN_RX_FIFO1_DS(u) (READ_REG32_BIT((u)->RXESC, MCAN_RXESC_F1DS) >> MCAN_RXESC_F1DS_POS) +#define MCAN_RX_BUF_DS(u) (READ_REG32_BIT((u)->RXESC, MCAN_RXESC_RBDS) >> MCAN_RXESC_RBDS_POS) +#define MCAN_TX_DS(u) (READ_REG32_BIT((u)->TXESC, MCAN_TXESC_TBDS)) + +/* Element size */ +#define MCAN_STD_FILTER_ES (4U) +#define MCAN_EXT_FILTER_ES (8U) +#define MCAN_TX_EVT_ES (8U) +#define MCAN_RX_FIFO0_ES(u) ((uint32_t)m_au8ElmtSize[MCAN_RX_FIFO0_DS(u)]) +#define MCAN_RX_FIFO1_ES(u) ((uint32_t)m_au8ElmtSize[MCAN_RX_FIFO1_DS(u)]) +#define MCAN_RX_BUF_ES(u) ((uint32_t)m_au8ElmtSize[MCAN_RX_BUF_DS(u)]) +#define MCAN_TX_ES(u) ((uint32_t)m_au8ElmtSize[MCAN_TX_DS(u)]) + +#define MCAN_GET_ES(ds) ((uint32_t)m_au8ElmtSize[(ds)]) + +#define MCAN_RX_FIFO0_REAL_DS(u) m_au8DLC2Size[MCAN_RX_FIFO0_DS(u) + 8U] +#define MCAN_RX_FIFO1_REAL_DS(u) m_au8DLC2Size[MCAN_RX_FIFO1_DS(u) + 8U] +#define MCAN_RX_BUF_REAL_DS(u) m_au8DLC2Size[MCAN_RX_BUF_DS(u) + 8U] +#define MCAN_TX_REAL_DS(u) m_au8DLC2Size[MCAN_TX_DS(u) + 8U] + +#define GET_BIT_POS(val) (__CLZ(__RBIT(val))) + +/** + * @} + */ + +/** + * @defgroup MCAN_Check_Parameters_Validity MCAN Check Parameters Validity + * @{ + */ +#define IS_MCAN_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_ADC_1BIT_MASK(x) (((x) != 0U) && (((x) & ((x) - 1U)) == 0U)) + +#define IS_MCAN_FUNC_EN(x, en) (((x) == 0U) || ((x) == (en))) + +#define IS_MCAN_RANGE(x, min, max) (((x) >= (min)) && ((x) <= (max))) + +/* MCAN unit */ +#define IS_MCAN_UNIT(x) (((x) == CM_MCAN1) || ((x) == CM_MCAN2)) + +/* MCAN operating mode */ +#define IS_MCAN_MD(x) \ +( ((x) == MCAN_MD_NORMAL) || \ + ((x) == MCAN_MD_RESTRICTED_OP) || \ + ((x) == MCAN_MD_BUS_MON) || \ + ((x) == MCAN_MD_INTERN_LOOPBACK) || \ + ((x) == MCAN_MD_EXTERN_LOOPBACK)) + +/* MCAN frame format */ +#define IS_MCAN_FRAME_FORMAT(x) \ +( ((x) == MCAN_FRAME_CLASSIC) || \ + ((x) == MCAN_FRAME_ISO_FD_NO_BRS) || \ + ((x) == MCAN_FRAME_ISO_FD_BRS) || \ + ((x) == MCAN_FRAME_NON_ISO_FD_NO_BRS) || \ + ((x) == MCAN_FRAME_NON_ISO_FD_BRS)) + +/* Nominal bit time */ +#define IS_MCAN_NBRP(x) IS_MCAN_RANGE(x, 1U, 512U) +#define IS_MCAN_NSEG1(x) IS_MCAN_RANGE(x, 3U, 257U) +#define IS_MCAN_NSEG2(x) IS_MCAN_RANGE(x, 2U, 128U) +#define IS_MCAN_NSJW(x) IS_MCAN_RANGE(x, 1U, 128U) + +/* FD data bit time */ +#define IS_MCAN_DBRP(tdc, x) \ +( (((tdc) == MCAN_FD_TDC_DISABLE) && IS_MCAN_RANGE(x, 1U, 32U)) || \ + (((tdc) == MCAN_FD_TDC_ENABLE) && IS_MCAN_RANGE(x, 1U, 2U))) +#define IS_MCAN_DSEG1(x) IS_MCAN_RANGE(x, 2U, 33U) +#define IS_MCAN_DSEG2(x) IS_MCAN_RANGE(x, 1U, 16U) +#define IS_MCAN_DSJW(x) IS_MCAN_RANGE(x, 1U, 16U) + +/* FD data SSP offset */ +#define IS_MCAN_SSP(x) ((x) <= 127U) +#define IS_MCAN_TDC_FILTER(x) ((x) <= 127U) + +/* MCAN Automatic Retransmission */ +#define IS_MCAN_AUTO_RETX_EN(x) \ +( ((x) == MCAN_AUTO_RETX_DISABLE) || \ + ((x) == MCAN_AUTO_RETX_ENABLE)) + +/* MCAN transmit pause */ +#define IS_MCAN_TX_PAUSE_EN(x) \ +( ((x) == MCAN_TX_PAUSE_DISABLE) || \ + ((x) == MCAN_TX_PAUSE_ENABLE)) + +/* MCAN Tx event message marker */ +#define IS_MCAN_MSG_MARKER_CFG(x) \ +( ((x) == MCAN_MSG_MARKER_8BIT) || \ + ((x) == MCAN_MSG_MARKER_16BIT)) + +/* MCAN protocol exception handling */ +#define IS_MCAN_PXH_EN(x) \ +( ((x) == MCAN_PROTOCOL_EXP_DISABLE) || \ + ((x) == MCAN_PROTOCOL_EXP_ENABLE)) + +/* MCAN Tx pin control */ +#define IS_MCAN_PIN_CTRL(x) \ +( ((x) == MCAN_TX_PIN_NORMAL) || \ + ((x) == MCAN_TX_PIN_MONITOR) || \ + ((x) == MCAN_TX_PIN_DOMINANT) || \ + ((x) == MCAN_TX_PIN_RECESSIVE)) + +/* MCAN message RAM */ +#define IS_MCAN_MSG_RAM_OFFSET_ADDR(x) ((((x) & 0x3UL) == 0U) && ((x) < MCAN_MSG_RAM_SIZE)) +#define IS_MCAN_STD_FILTER_NUM(x) ((x) <= MCAN_STD_FILTER_NUM_MAX) +#define IS_MCAN_EXT_FILTER_NUM(x) ((x) <= MCAN_EXT_FILTER_NUM_MAX) +#define IS_MCAN_RX_FIFO0_NUM(x) ((x) <= MCAN_RX_FIFO0_NUM_MAX) +#define IS_MCAN_RX_FIFO1_NUM(x) ((x) <= MCAN_RX_FIFO1_NUM_MAX) +#define IS_MCAN_RX_BUF_NUM(x) ((x) <= MCAN_RX_BUF_NUM_MAX) +#define IS_MCAN_TX_EVT_NUM(x) ((x) <= MCAN_TX_EVT_NUM_MAX) +#define IS_MCAN_TX_ELMT_NUM(x) ((x) <= MCAN_TX_ELMT_NUM_MAX) +#define IS_MCAN_MSG_RAM_END_ADDR(x) ((x) <= MCAN_MSG_RAM_END) + +/* MCAN data field size */ +#define IS_MCAN_DATA_FIELD_SIZE(x) ((x) <= MCAN_DATA_SIZE_MAX) + +/* Tx FIFO/Queue operation mode */ +#define IS_MCAN_TX_FIFO_QUEUE_MD(x) (((x) == MCAN_TX_FIFO_MD) || ((x) == MCAN_TX_QUEUE_MD)) + +/* MCAN filter */ +#define IS_MCAN_ID_TYPE(x) (((x) == MCAN_STD_ID) || ((x) == MCAN_EXT_ID)) +#define IS_MCAN_STD_ID_VAL(x) ((x) <= MCAN_STD_ID_MASK) +#define IS_MCAN_EXT_ID_VAL(x) ((x) <= MCAN_EXT_ID_MASK) + +#define IS_MCAN_STD_FILTER_TYPE(x) \ +( ((x) == MCAN_FILTER_RANGE) || \ + ((x) == MCAN_FILTER_DUAL ) || \ + ((x) == MCAN_FILTER_MASK)) + +#define IS_MCAN_EXT_FILTER_TYPE(x) \ +( ((x) == MCAN_FILTER_RANGE) || \ + ((x) == MCAN_FILTER_DUAL) || \ + ((x) == MCAN_FILTER_MASK) || \ + ((x) == MCAN_FILTER_RANGE_NO_EIDM)) + +#define IS_MCAN_FILTER_CFG(x) \ +( ((x) == MCAN_FILTER_DISABLE) || \ + ((x) == MCAN_FILTER_TO_RX_FIFO0) || \ + ((x) == MCAN_FILTER_TO_RX_FIFO1) || \ + ((x) == MCAN_FILTER_REJECT) || \ + ((x) == MCAN_FILTER_HP_NO_STORAGE) || \ + ((x) == MCAN_FILTER_HP_TO_RX_FIFO0) || \ + ((x) == MCAN_FILTER_HP_TO_RX_FIFO1) || \ + ((x) == MCAN_FILTER_TO_RX_BUF)) + +/* Non-matching frame operation */ +#define IS_MCAN_NMF_OP(x) \ +( ((x) == MCAN_NMF_ACCEPT_IN_RX_FIFO0) || \ + ((x) == MCAN_NMF_ACCEPT_IN_RX_FIFO1) || \ + ((x) == MCAN_NMF_REJECT)) + +/* Remote frame operation */ +#define IS_MCAN_REMOTE_FRAME_OP(x) \ +( ((x) == MCAN_REMOTE_FRAME_FILTER) || \ + ((x) == MCAN_REMOTE_FRAME_REJECT )) + +/* Rx FIFO */ +#define IS_MCAN_RX_FIFO(x) \ +( ((x) == MCAN_RX_FIFO0) || \ + ((x) == MCAN_RX_FIFO1)) + +/* Rx FIFO operation mode */ +#define IS_MCAN_RX_FIFO_MD(x) \ +( ((x) == MCAN_RX_FIFO_BLOCKING) || \ + ((x) == MCAN_RX_FIFO_OVERWRITE)) + +/* Watermark FIFO */ +#define IS_MCAN_WATERMARK_FIFO(x) \ +( ((x) == MCAN_WATERMARK_TX_EVT_FIFO) || \ + ((x) == MCAN_WATERMARK_RX_FIFO0) || \ + ((x) == MCAN_WATERMARK_RX_FIFO1)) + +/* RAM watchdog counter start value */ +#define IS_MCAN_RAM_WDT_START_VAL(x) ((x) <= 255U) + +/* MCAN timestamp counter */ +#define IS_MCAN_TS_PRESC(x) (((x) >= 1U) && ((x) <= 16U )) + +/* MCAN timeout counter */ +#define IS_MCAN_TO_SEL(x) \ +( ((x) == MCAN_TIMEOUT_CONT) || \ + ((x) == MCAN_TIMEOUT_TX_EVT_FIFO) || \ + ((x) == MCAN_TIMEOUT_RX_FIFO0) || \ + ((x) == MCAN_TIMEOUT_RX_FIFO1)) + +#define IS_MCAN_TO_PERIOD(x) ((x) <= 65535U) + +/* MCAN frame bit field */ +#define IS_MCAN_FRAME_RTR(x) (((x) == 0U) || ((x) == 1U)) +#define IS_MCAN_FRAME_DLC(x) ((x) <= MCAN_DLC64) +#define IS_MCAN_FRAME_ESI(x) (((x) == 0U) || ((x) == 1U)) +#define IS_MCAN_FRAME_BRS(x) (((x) == 0U) || ((x) == 1U)) +#define IS_MCAN_FRAME_FDF(x) (((x) == 0U) || ((x) == 1U)) +#define IS_MCAN_FRAME_EFC(x) (((x) == 0U) || ((x) == 1U)) + +#define IS_MCAN_FRAME_MSG_MARKER(wmm, x) \ +( (((wmm) == 0U) && ((x) <= 255UL)) || \ + (((wmm) != 0U) && ((x) <= 65535UL))) + +/* One Tx buffer check */ +#define IS_MCAN_1TXBUF(x) IS_ADC_1BIT_MASK(x) +#define IS_MCAN_TX_BUF(x) IS_MCAN_BIT_MASK(x, MCAN_TX_BUF_ALL) + +/* Interrupt */ +#define IS_MCAN_INT_LINE(x) \ +( ((x) == MCAN_INT_LINE0) || \ + ((x) == MCAN_INT_LINE1)) +#define IS_MCAN_INT_TYPE(x) IS_MCAN_BIT_MASK(x, MCAN_INT_ALL) +#define IS_MCAN_TX_BUF_NOTICE(x) IS_MCAN_BIT_MASK(x, MCAN_INT_TX_CPLT | MCAN_INT_TX_ABORT_CPLT) + +/* Interrupt flag */ +#define IS_MCAN_FLAG(x) IS_MCAN_BIT_MASK(x, MCAN_FLAG_ALL) + +/* Protocol status flag */ +#define IS_MCAN_PS_FLAG(x) IS_MCAN_BIT_MASK(x, MCAN_PROTOCOL_FLAG_ALL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup MCAN_Local_Variables MCAN Local Variables + * @{ + */ +static const uint8_t m_au8DLC2Size[16U] = { + 0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U +}; + +static const uint8_t m_au8ElmtSize[8U] = {16U, 20U, 24U, 28U, 32U, 40U, 56U, 72U}; + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup MCAN_Local_Functions MCAN Local Functions + * @{ + */ + +/** + * @brief Specifies MCAN operating mode. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32Mode MCAN operating mode. + * This parameter can be a value of @ref MCAN_Operating_Mode + * @arg MCAN_MD_NORMAL: Normal mode. + * @arg MCAN_MD_RESTRICTED_OP: Restricted operation mode. + * @arg MCAN_MD_BUS_MON: Bus monitoring mode. + * @arg MCAN_MD_INTERN_LOOPBACK: Internal loopBack mode. + * @arg MCAN_MD_EXTERN_LOOPBACK: External loopBack mode. + * @retval None + */ +static void MCAN_SetMode(CM_MCAN_TypeDef *MCANx, uint32_t u32Mode) +{ + /* Set MCAN operating mode: + |----------------------|-----------|----------|-----------|----------| + | | CCCR.TEST | CCCR.MON | TEST.LBCK | CCCR.ASM | + |----------------------|-----------|----------|-----------|----------| + | Normal | 0 | 0 | 0 | 0 | + |----------------------|-----------|----------|-----------|----------| + | Restricted Operation | 0 | 0 | 0 | 1 | + |----------------------|-----------|----------|-----------|----------| + | Bus Monitoring | 0 | 1 | 0 | 0 | + |----------------------|-----------|----------|-----------|----------| + | Internal LoopBack | 1 | 1 | 1 | 0 | + |----------------------|-----------|----------|-----------|----------| + | External LoopBack | 1 | 0 | 1 | 0 | + |----------------------|-----------|----------|-----------|----------| + */ + /* Default mode: normal mode */ + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_TEST | MCAN_CCCR_MON | MCAN_CCCR_ASM); + CLR_REG32_BIT(MCANx->TEST, MCAN_TEST_LBCK); + /* Switch mode according to the parameter u32Mode */ + switch (u32Mode) { + case MCAN_MD_RESTRICTED_OP: + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_ASM); + break; + case MCAN_MD_BUS_MON: + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_MON); + break; + case MCAN_MD_INTERN_LOOPBACK: + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_TEST | MCAN_CCCR_MON); + SET_REG32_BIT(MCANx->TEST, MCAN_TEST_LBCK); + break; + case MCAN_MD_EXTERN_LOOPBACK: + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_TEST); + SET_REG32_BIT(MCANx->TEST, MCAN_TEST_LBCK); + break; + default: + /* Nothing to do: normal mode */ + break; + } +} + +/** + * @brief Configures MCAN message RAM. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pstcMsgRam Pointer to a @ref stc_mcan_msg_ram_config_t type structure + * which contains the message RAM configuration information. + * @retval None + */ +static void MCAN_MsgRamInitConfig(CM_MCAN_TypeDef *MCANx, stc_mcan_msg_ram_config_t *pstcMsgRam) +{ + uint32_t u32EndAddr; + uint32_t u32StartAddr = pstcMsgRam->u32AddrOffset; + uint32_t u32TxElmtNum = pstcMsgRam->u32TxBufferNum + pstcMsgRam->u32TxFifoQueueNum; + + /* Start address(offset address) 4byte alignment required */ + DDL_ASSERT(IS_MCAN_MSG_RAM_OFFSET_ADDR(u32StartAddr)); + DDL_ASSERT(IS_MCAN_STD_FILTER_NUM(pstcMsgRam->u32StdFilterNum)); + DDL_ASSERT(IS_MCAN_EXT_FILTER_NUM(pstcMsgRam->u32ExtFilterNum)); + DDL_ASSERT(IS_MCAN_RX_FIFO0_NUM(pstcMsgRam->u32RxFifo0Num)); + DDL_ASSERT(IS_MCAN_RX_FIFO1_NUM(pstcMsgRam->u32RxFifo1Num)); + DDL_ASSERT(IS_MCAN_RX_BUF_NUM(pstcMsgRam->u32RxBufferNum)); + DDL_ASSERT(IS_MCAN_TX_EVT_NUM(pstcMsgRam->u32TxEventNum)); + DDL_ASSERT(IS_MCAN_TX_ELMT_NUM(u32TxElmtNum)); + + /* Standard filter start address and elements number */ + WRITE_REG32(MCANx->SIDFC, u32StartAddr); + SET_REG32_BIT(MCANx->SIDFC, (pstcMsgRam->u32StdFilterNum << MCAN_SIDFC_LSS_POS)); + + /* Extended filter start address and elements number */ + u32StartAddr += (pstcMsgRam->u32StdFilterNum * MCAN_STD_FILTER_ES); + WRITE_REG32(MCANx->XIDFC, (pstcMsgRam->u32ExtFilterNum << MCAN_XIDFC_LSE_POS) | u32StartAddr); + + /* Rx FIFO0 start address and elements number */ + u32StartAddr += (pstcMsgRam->u32ExtFilterNum * MCAN_EXT_FILTER_ES); + WRITE_REG32(MCANx->RXF0C, (pstcMsgRam->u32RxFifo0Num << MCAN_RXF0C_F0S_POS) | u32StartAddr); + + /* Rx FIFO1 start address and elements number */ + u32StartAddr += (pstcMsgRam->u32RxFifo0Num * MCAN_GET_ES(pstcMsgRam->u32RxFifo0DataSize)); + WRITE_REG32(MCANx->RXF1C, (pstcMsgRam->u32RxFifo1Num << MCAN_RXF1C_F1S_POS) | u32StartAddr); + + /* Rx buffer list start address */ + u32StartAddr += (pstcMsgRam->u32RxFifo1Num * MCAN_GET_ES(pstcMsgRam->u32RxFifo1DataSize)); + WRITE_REG32(MCANx->RXBC, u32StartAddr); + + /* Tx event FIFO start address and elements number */ + u32StartAddr += (pstcMsgRam->u32RxBufferNum * MCAN_GET_ES(pstcMsgRam->u32RxBufferDataSize)); + WRITE_REG32(MCANx->TXEFC, (pstcMsgRam->u32TxEventNum << MCAN_TXEFC_EFS_POS) | u32StartAddr); + + /* Tx buffer list start address, dedicated Tx buffers number, Tx FIFO/queue elements number */ + u32StartAddr += (pstcMsgRam->u32TxEventNum * MCAN_TX_EVT_ES); + WRITE_REG32(MCANx->TXBC, (pstcMsgRam->u32TxFifoQueueNum << MCAN_TXBC_TFQS_POS) | \ + (pstcMsgRam->u32TxBufferNum << MCAN_TXBC_NDTB_POS) | \ + u32StartAddr); + u32StartAddr += (u32TxElmtNum * MCAN_GET_ES(pstcMsgRam->u32TxDataSize)); + /* Get total allocated size */ + pstcMsgRam->u32AllocatedSize = u32StartAddr - pstcMsgRam->u32AddrOffset; + + /* Message RAM end address */ + u32EndAddr = MCAN_MSG_RAM_BASE + u32StartAddr; + /* Assert the end address is not out of range. */ + DDL_ASSERT(IS_MCAN_MSG_RAM_END_ADDR(u32EndAddr)); + + /* Configure Rx FIFO0, Rx FIFO1 and Rx buffer data filed size */ + if (pstcMsgRam->u32RxFifo0Num > 0U) { + DDL_ASSERT(IS_MCAN_DATA_FIELD_SIZE(pstcMsgRam->u32RxFifo0DataSize)); + MODIFY_REG32(MCANx->RXESC, MCAN_RXESC_F0DS, (pstcMsgRam->u32RxFifo0DataSize << MCAN_RXESC_F0DS_POS)); + } + if (pstcMsgRam->u32RxFifo1Num > 0U) { + DDL_ASSERT(IS_MCAN_DATA_FIELD_SIZE(pstcMsgRam->u32RxFifo1DataSize)); + MODIFY_REG32(MCANx->RXESC, MCAN_RXESC_F1DS, (pstcMsgRam->u32RxFifo1DataSize << MCAN_RXESC_F1DS_POS)); + } + if (pstcMsgRam->u32RxBufferNum > 0U) { + DDL_ASSERT(IS_MCAN_DATA_FIELD_SIZE(pstcMsgRam->u32RxBufferDataSize)); + MODIFY_REG32(MCANx->RXESC, MCAN_RXESC_RBDS, (pstcMsgRam->u32RxBufferDataSize << MCAN_RXESC_RBDS_POS)); + } + + /* Configure Tx data filed size */ + if (u32TxElmtNum > 0U) { + DDL_ASSERT(IS_MCAN_DATA_FIELD_SIZE(pstcMsgRam->u32TxDataSize)); + WRITE_REG32(MCANx->TXESC, pstcMsgRam->u32TxDataSize); + + if (pstcMsgRam->u32TxFifoQueueNum > 0U) { + DDL_ASSERT(IS_MCAN_TX_FIFO_QUEUE_MD(pstcMsgRam->u32TxFifoQueueMode)); + MODIFY_REG32(MCANx->TXBC, MCAN_TXBC_TFQM, pstcMsgRam->u32TxFifoQueueMode); + } + } + + /* Flush the allocated Message RAM area */ + u32StartAddr = pstcMsgRam->u32AddrOffset + MCAN_MSG_RAM_BASE; + while (u32StartAddr < u32EndAddr) { + RW_MEM32(u32StartAddr) = 0x0UL; + u32StartAddr += 4UL; + } +} + +/** + * @brief Configures MCAN acceptance filters when initializing the MCAN module. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pstcFilter Pointer to a @ref stc_mcan_filter_config_t type structure which + * contains the acceptance filters configuration information. + * @retval None + */ +static void MCAN_FilterInitConfig(CM_MCAN_TypeDef *MCANx, stc_mcan_filter_config_t *pstcFilter) +{ + uint32_t i; + + if (pstcFilter->pstcStdFilterList != NULL) { + for (i = 0U; i < pstcFilter->u32StdFilterConfigNum; i++) { + pstcFilter->pstcStdFilterList[i].u32FilterIndex = i; + (void)MCAN_FilterConfig(MCANx, &pstcFilter->pstcStdFilterList[i]); + } + } + + if (pstcFilter->pstcExtFilterList != NULL) { + for (i = 0U; i < pstcFilter->u32ExtFilterConfigNum; i++) { + pstcFilter->pstcExtFilterList[i].u32FilterIndex = i; + (void)MCAN_FilterConfig(MCANx, &pstcFilter->pstcExtFilterList[i]); + } + } +} + +/** + * @brief Copy Tx message to the message RAM. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pTxMsg Pointer to a @ref stc_mcan_tx_msg_t structure that contains + * the information of the message that to be transmitted. + * @param [in] u32TxPutIndex Index of the Tx buffer to be configured. + * @retval None + */ +static void MCAN_CopyTxMsgToRam(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_msg_t *pTxMsg, uint32_t u32TxPutIndex) +{ + uint8_t i; + uint32_t u32T0; + uint32_t u32T1; + uint32_t u32TxAddr; + uint32_t u32MsgMarkerCfg; + uint32_t u32DataSize; + + /* Build first word of Tx header element */ + if (pTxMsg->IDE == MCAN_STD_ID) { + /* Standard frame */ + u32T0 = ((pTxMsg->ESI << MCAN_FRAME_ESI_POS) | \ + (pTxMsg->RTR << MCAN_FRAME_RTR_POS) | \ + (pTxMsg->ID << MCAN_FRAME_STDID_POS)); + } else { + /* Extended frame */ + u32T0 = ((pTxMsg->ESI << MCAN_FRAME_ESI_POS) | \ + (pTxMsg->IDE << MCAN_FRAME_XTD_POS) | \ + (pTxMsg->RTR << MCAN_FRAME_RTR_POS) | \ + pTxMsg->ID); + } + + u32MsgMarkerCfg = pTxMsg->u32MsgMarker << MCAN_FRAME_MM_L_POS; + if (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_WMM) != 0U) { + u32MsgMarkerCfg |= (pTxMsg->u32MsgMarker & MCAN_FRAME_MM_H_MASK); + } + /* Build second word of Tx header element */ + u32T1 = (u32MsgMarkerCfg | \ + (pTxMsg->u32StoreTxEvent << MCAN_FRAME_EFC_POS) | \ + (pTxMsg->FDF << MCAN_FRAME_FDF_POS) | \ + (pTxMsg->BRS << MCAN_FRAME_BRS_POS) | \ + (pTxMsg->DLC << MCAN_FRAME_DLC_POS)); + /* Calculate Tx element address */ + u32TxAddr = MCAN_TX_ELMT_SA(MCANx); + u32TxAddr += (u32TxPutIndex * MCAN_TX_ES(MCANx)); + + /* Write Tx element header to the message RAM */ + RW_MEM32(u32TxAddr) = u32T0; + u32TxAddr += 4U; + RW_MEM32(u32TxAddr) = u32T1; + + u32DataSize = m_au8DLC2Size[pTxMsg->DLC]; + /* Determine the CAN frame format: classical CAN or FD CAN */ + if (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_FDOE) == 0U) { + /* Max 8 bytes for classical CAN */ + if (u32DataSize > CAN20_DATA_SIZE_MAX) { + u32DataSize = CAN20_DATA_SIZE_MAX; + } + } else { + DDL_ASSERT(u32DataSize <= MCAN_TX_REAL_DS(MCANx)); + } + if (pTxMsg->RTR == 0U) { + /* Write Tx payload to the message RAM */ + for (i = 0U; i < u32DataSize; i += 4U) { + u32TxAddr += 4U; + RW_MEM32(u32TxAddr) = (((uint32_t)pTxMsg->au8Data[i + 3U] << 24U) | \ + ((uint32_t)pTxMsg->au8Data[i + 2U] << 16U) | \ + ((uint32_t)pTxMsg->au8Data[i + 1U] << 8U) | \ + (uint32_t)pTxMsg->au8Data[i]); + } + } +} + +/** + * @brief Get the number of the Rx buffer that has an allocated area into the message RAM. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint32_t type value of the number of the Rx buffer + */ +static uint32_t MCAN_GetRxBufferNum(const CM_MCAN_TypeDef *MCANx) +{ + uint32_t u32Temp; + /* Get Tx event FIFO start address */ + u32Temp = MCAN_TX_EVT_FIFO_SA(MCANx); + /* Get Rx buffer size */ + u32Temp -= MCAN_RX_BUF_SA(MCANx); + /* Get Rx buffer number */ + return (u32Temp / MCAN_RX_BUF_ES(MCANx)); +} + +/** + * @} + */ + +/** + * @defgroup MCAN_Global_Functions MCAN Global Functions + * @{ + */ + +/** + * @brief Initializes the specified MCAN peripheral according to the specified parameters + * in the structure pstcMcanInit. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pstcMcanInit Pointer to a @ref stc_mcan_init_t structure value that + * contains the configuration information for the MCAN. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcMcanInit == NULL + */ +int32_t MCAN_Init(CM_MCAN_TypeDef *MCANx, stc_mcan_init_t *pstcMcanInit) +{ + uint32_t u32Config; + uint32_t u32Mask; + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t u32TimeoutValue = MCAN_TIMEOUT_VALUE; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pstcMcanInit != NULL) { + DDL_ASSERT(IS_MCAN_MD(pstcMcanInit->u32Mode)); + DDL_ASSERT(IS_MCAN_FRAME_FORMAT(pstcMcanInit->u32FrameFormat)); + DDL_ASSERT(IS_MCAN_NBRP(pstcMcanInit->stcBitTime.u32NominalPrescaler)); + DDL_ASSERT(IS_MCAN_NSEG1(pstcMcanInit->stcBitTime.u32NominalTimeSeg1)); + DDL_ASSERT(IS_MCAN_NSEG2(pstcMcanInit->stcBitTime.u32NominalTimeSeg2)); + DDL_ASSERT(IS_MCAN_NSJW(pstcMcanInit->stcBitTime.u32NominalSyncJumpWidth)); + /* If FD enabled */ + if ((pstcMcanInit->u32FrameFormat & MCAN_CCCR_FDOE) == MCAN_CCCR_FDOE) { + DDL_ASSERT(IS_MCAN_DBRP(pstcMcanInit->stcBitTime.u32TDC, \ + pstcMcanInit->stcBitTime.u32DataPrescaler)); + DDL_ASSERT(IS_MCAN_DSEG1(pstcMcanInit->stcBitTime.u32DataTimeSeg1)); + DDL_ASSERT(IS_MCAN_DSEG2(pstcMcanInit->stcBitTime.u32DataTimeSeg2)); + DDL_ASSERT(IS_MCAN_DSJW(pstcMcanInit->stcBitTime.u32DataSyncJumpWidth)); + if (pstcMcanInit->stcBitTime.u32TDC == MCAN_FD_TDC_ENABLE) { + DDL_ASSERT(IS_MCAN_SSP(pstcMcanInit->stcBitTime.u32SspOffset)); + DDL_ASSERT(IS_MCAN_TDC_FILTER(pstcMcanInit->stcBitTime.u32TdcFilter)); + } + } + DDL_ASSERT(IS_MCAN_AUTO_RETX_EN(pstcMcanInit->u32AutoRetx)); + DDL_ASSERT(IS_MCAN_TX_PAUSE_EN(pstcMcanInit->u32TxPause)); + DDL_ASSERT(IS_MCAN_PXH_EN(pstcMcanInit->u32ProtocolException)); + + if (pstcMcanInit->stcFilter.u32StdFilterConfigNum > 0U) { + DDL_ASSERT(pstcMcanInit->stcFilter.u32StdFilterConfigNum <= \ + (uint8_t)pstcMcanInit->stcMsgRam.u32StdFilterNum); + } + if (pstcMcanInit->stcFilter.u32ExtFilterConfigNum > 0U) { + DDL_ASSERT(pstcMcanInit->stcFilter.u32ExtFilterConfigNum <= \ + (uint8_t)pstcMcanInit->stcMsgRam.u32ExtFilterNum); + } + + i32Ret = LL_OK; + /* Exit from sleep mode */ + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSR); + /* Check sleep mode acknowledge */ + while (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSA) == MCAN_CCCR_CSA) { + u32TimeoutValue--; + if (u32TimeoutValue == 0u) { + i32Ret = LL_ERR_TIMEOUT; + } + } + + if (i32Ret == LL_OK) { + /* Request initialization */ + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_INIT); + /* Wait until the CCCR.INIT is set */ + u32TimeoutValue = MCAN_TIMEOUT_VALUE; + while (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_INIT) == 0U) { + u32TimeoutValue--; + if (u32TimeoutValue == 0u) { + i32Ret = LL_ERR_TIMEOUT; + } + } + } + + if (i32Ret == LL_OK) { + /* Enable configuration change */ + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CCE); + + /* Frame format, automatic retransmission, transmit pause, protocol exception handling */ + u32Mask = MCAN_FRAME_NON_ISO_FD_BRS | MCAN_CCCR_DAR | MCAN_CCCR_TXP | MCAN_CCCR_PXHD; + u32Config = pstcMcanInit->u32FrameFormat | pstcMcanInit->u32AutoRetx | \ + pstcMcanInit->u32TxPause | pstcMcanInit->u32ProtocolException; + MODIFY_REG32(MCANx->CCCR, u32Mask, u32Config); + + /* Nominal bit time */ + u32Config = ((pstcMcanInit->stcBitTime.u32NominalPrescaler - 1U) << MCAN_NBTP_NBRP_POS) | \ + ((pstcMcanInit->stcBitTime.u32NominalTimeSeg1 - 2U) << MCAN_NBTP_NTSEG1_POS) | \ + ((pstcMcanInit->stcBitTime.u32NominalSyncJumpWidth - 1U) << MCAN_NBTP_NSJW_POS) | \ + (pstcMcanInit->stcBitTime.u32NominalTimeSeg2 - 1U); + WRITE_REG32(MCANx->NBTP, u32Config); + + /* Data bit time */ + if ((pstcMcanInit->u32FrameFormat & MCAN_CCCR_FDOE) == MCAN_CCCR_FDOE) { + u32Config = ((pstcMcanInit->stcBitTime.u32DataPrescaler - 1U) << MCAN_DBTP_DBRP_POS) | \ + ((pstcMcanInit->stcBitTime.u32DataTimeSeg1 - 2U) << MCAN_DBTP_DTSEG1_POS) | \ + (pstcMcanInit->stcBitTime.u32DataSyncJumpWidth - 1U) | \ + ((pstcMcanInit->stcBitTime.u32DataTimeSeg2 - 1U) << MCAN_DBTP_DTSEG2_POS); + WRITE_REG32(MCANx->DBTP, u32Config); + if (pstcMcanInit->stcBitTime.u32TDC == MCAN_FD_TDC_ENABLE) { + SET_REG32_BIT(MCANx->DBTP, pstcMcanInit->stcBitTime.u32TDC); + u32Config = (pstcMcanInit->stcBitTime.u32SspOffset << MCAN_TDCR_TDCO_POS) | \ + pstcMcanInit->stcBitTime.u32TdcFilter; + WRITE_REG32(MCANx->TDCR, u32Config); + } + } + + /* MCAN operating mode */ + MCAN_SetMode(MCANx, pstcMcanInit->u32Mode); + /* MCAN message RAM */ + MCAN_MsgRamInitConfig(MCANx, &pstcMcanInit->stcMsgRam); + /* MCAN message filter */ + MCAN_FilterInitConfig(MCANx, &pstcMcanInit->stcFilter); + /* Reject all non-matching frames. */ + WRITE_REG32(MCANx->GFC, 0x3FUL); + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set each member of @ref stc_mcan_init_t to a default value. + * The default value for bit time is an example for application, based on the 40MHz MCAN clock. + * The default value set nominal bit rate to 500Kbps, set data bit rate to 4Mbps. + * Nominal prescaler: 1 + * Nominal total TQs: 80 + * Nominal time segment before sample point: 64 + * Nominal time segment after sample point: 16 + * Nominal (re)synchronization jump width: 16 + * Nominal sample point: 80% + * Data prescaler: 1 + * Data total TQs: 10 + * Data time segment before sample point: 8 + * Data time segment after sample point: 2 + * Data (re)synchronization jump width: 2 + * Data sample point: 80% + * @param [in] pstcMcanInit Pointer to a @ref stc_mcan_init_t structure + * whose members will be set to default values. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcMcanInit == NULL. + */ +int32_t MCAN_StructInit(stc_mcan_init_t *pstcMcanInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcMcanInit != NULL) { + pstcMcanInit->u32Mode = MCAN_MD_NORMAL; + pstcMcanInit->u32FrameFormat = MCAN_FRAME_ISO_FD_BRS; + pstcMcanInit->u32AutoRetx = MCAN_AUTO_RETX_ENABLE; + pstcMcanInit->u32TxPause = MCAN_TX_PAUSE_DISABLE; + pstcMcanInit->u32ProtocolException = MCAN_PROTOCOL_EXP_ENABLE; + /* Nominal bit time, for classical CAN and CAN FD arbitration phase */ + pstcMcanInit->stcBitTime.u32NominalPrescaler = 1U; + pstcMcanInit->stcBitTime.u32NominalTimeSeg1 = 64U; + pstcMcanInit->stcBitTime.u32NominalTimeSeg2 = 16U; + pstcMcanInit->stcBitTime.u32NominalSyncJumpWidth = 16U; + /* Data bit time, for CAN FD data phase */ + pstcMcanInit->stcBitTime.u32DataPrescaler = 1U; + pstcMcanInit->stcBitTime.u32DataTimeSeg1 = 8U; + pstcMcanInit->stcBitTime.u32DataTimeSeg2 = 2U; + pstcMcanInit->stcBitTime.u32DataSyncJumpWidth = 2U; + pstcMcanInit->stcBitTime.u32TDC = MCAN_FD_TDC_ENABLE; + pstcMcanInit->stcBitTime.u32SspOffset = 8U; + pstcMcanInit->stcBitTime.u32TdcFilter = 0U; + /* Message RAM */ + pstcMcanInit->stcMsgRam.u32AddrOffset = 0U; + pstcMcanInit->stcMsgRam.u32StdFilterNum = 0U; + pstcMcanInit->stcMsgRam.u32ExtFilterNum = 0U; + pstcMcanInit->stcMsgRam.u32RxFifo0Num = 0U; + pstcMcanInit->stcMsgRam.u32RxFifo0DataSize = MCAN_DATA_SIZE_8BYTE; + pstcMcanInit->stcMsgRam.u32RxFifo1Num = 0U; + pstcMcanInit->stcMsgRam.u32RxFifo1DataSize = MCAN_DATA_SIZE_8BYTE; + pstcMcanInit->stcMsgRam.u32RxBufferNum = 0U; + pstcMcanInit->stcMsgRam.u32RxBufferDataSize = MCAN_DATA_SIZE_8BYTE; + pstcMcanInit->stcMsgRam.u32TxEventNum = 0U; + pstcMcanInit->stcMsgRam.u32TxBufferNum = 0U; + pstcMcanInit->stcMsgRam.u32TxFifoQueueNum = 0U; + pstcMcanInit->stcMsgRam.u32TxFifoQueueMode = MCAN_TX_FIFO_MD; + pstcMcanInit->stcMsgRam.u32TxDataSize = MCAN_DATA_SIZE_8BYTE; + /* Acceptance filter */ + pstcMcanInit->stcFilter.pstcStdFilterList = NULL; + pstcMcanInit->stcFilter.pstcExtFilterList = NULL; + pstcMcanInit->stcFilter.u32StdFilterConfigNum = 0U; + pstcMcanInit->stcFilter.u32ExtFilterConfigNum = 0U; + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Deinitialize the MCAN peripheral registers to their default reset values. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval None + */ +void MCAN_DeInit(CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + /* Stop the MCAN module: return value is voluntary ignored. */ + (void)MCAN_Stop(MCANx); + /* Disable interrupt lines. */ + WRITE_REG32(MCANx->ILE, 0U); + /* Set registers to their default reset values. */ + WRITE_REG32(MCANx->DBTP, 0x0A33U); + WRITE_REG32(MCANx->TEST, 0x0U); + WRITE_REG32(MCANx->RWD, 0x0U); + WRITE_REG32(MCANx->CCCR, 0x3U); + WRITE_REG32(MCANx->NBTP, 0x06000A03UL); + WRITE_REG32(MCANx->TSCC, 0x0U); + WRITE_REG32(MCANx->TOCC, 0x0U); + WRITE_REG32(MCANx->TDCR, 0x0U); + WRITE_REG32(MCANx->IR, 0x0U); + WRITE_REG32(MCANx->IE, 0x0U); + WRITE_REG32(MCANx->ILS, 0x0U); + WRITE_REG32(MCANx->GFC, 0x0U); + WRITE_REG32(MCANx->SIDFC, 0x0U); + WRITE_REG32(MCANx->XIDFC, 0x0U); + WRITE_REG32(MCANx->XIDAM, 0x1FFFFFFFUL); + WRITE_REG32(MCANx->NDAT1, 0x0U); + WRITE_REG32(MCANx->NDAT2, 0x0U); + WRITE_REG32(MCANx->RXF0C, 0x0U); + WRITE_REG32(MCANx->RXBC, 0x0U); + WRITE_REG32(MCANx->RXF1C, 0x0U); + WRITE_REG32(MCANx->RXESC, 0x0U); + WRITE_REG32(MCANx->TXBC, 0x0U); + WRITE_REG32(MCANx->TXESC, 0x0U); + WRITE_REG32(MCANx->TXBAR, 0x0U); + WRITE_REG32(MCANx->TXBCR, 0x0U); + WRITE_REG32(MCANx->TXBTIE, 0x0U); + WRITE_REG32(MCANx->TXBCIE, 0x0U); + WRITE_REG32(MCANx->TXEFC, 0x0U); +} + +/** + * @brief Leave the initialization mode and start the MCAN module. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval None + */ +void MCAN_Start(CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_INIT); +} + +/** + * @brief Stop the MCAN module and enable access to configuration registers. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Operation timeout. + */ +int32_t MCAN_Stop(CM_MCAN_TypeDef *MCANx) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32Counter = 0U; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + /* Request initialization */ + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_INIT); + /* Wait until the CCCR.INIT bit is set */ + while (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_INIT) == 0U) { + u32Counter++; + if (u32Counter > MCAN_TIMEOUT_COUNT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + /* Exit from sleep mode */ + if (i32Ret == LL_OK) { + u32Counter = 0U; + /* Exit from sleep mode */ + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSR); + /* Wait until MCAN exits sleep mode */ + while (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSA) == MCAN_CCCR_CSA) { + u32Counter++; + if (u32Counter > MCAN_TIMEOUT_COUNT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + } + + if (i32Ret == LL_OK) { + /* Enable configuration change */ + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CCE); + } + + return i32Ret; +} + +/** + * @brief Enter MCAN peripheral in sleep mode. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Operation timeout. + */ +int32_t MCAN_EnterSleepMode(CM_MCAN_TypeDef *MCANx) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeoutValue = MCAN_TIMEOUT_VALUE; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + /* Request clock stop */ + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSR); + /* Wait until MCAN is ready for sleep */ + while (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSA) == 0U) { + u32TimeoutValue--; + if (u32TimeoutValue == 0U) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Exit sleep mode. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Operation timeout. + */ +int32_t MCAN_ExitSleepMode(CM_MCAN_TypeDef *MCANx) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeoutValue = MCAN_TIMEOUT_VALUE; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + /* Reset clock stop request */ + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSR); + /* Wait until MCAN exits sleep mode */ + while (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_CSA) == MCAN_CCCR_CSA) { + u32TimeoutValue--; + if (u32TimeoutValue == 0U) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + if (i32Ret == LL_OK) { + /* Enter normal operation */ + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_INIT); + } + + return i32Ret; +} + +/** + * @brief Get the address of each element that allocated into the message RAM + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pstcAddr Pointer to a @ref stc_mcan_msg_ram_addr_t type structure + * which contains the message RAM configuration information. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcMcanInit == NULL. + */ +int32_t MCAN_GetMsgRamAddr(const CM_MCAN_TypeDef *MCANx, stc_mcan_msg_ram_addr_t *pstcAddr) +{ + uint32_t i; + uint32_t u32ElementNum; + uint32_t u32ElementSize; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pstcAddr != NULL) { + /* Get start address */ + pstcAddr->u32StdFilterStartAddr = MCAN_STD_FILTER_SA(MCANx); + pstcAddr->u32ExtFilterStartAddr = MCAN_EXT_FILTER_SA(MCANx); + pstcAddr->u32RxFifo0StartAddr = MCAN_RX_FIFO0_SA(MCANx); + pstcAddr->u32RxFifo1StartAddr = MCAN_RX_FIFO1_SA(MCANx); + pstcAddr->u32RxBufferStartAddr = MCAN_RX_BUF_SA(MCANx); + pstcAddr->u32TxEventStartAddr = MCAN_TX_EVT_FIFO_SA(MCANx); + pstcAddr->u32TxBufferStartAddr = MCAN_TX_ELMT_SA(MCANx); + u32ElementNum = MCAN_GET_TX_BUF_NUM(MCANx); + pstcAddr->u32TxFifoQueueStartAddr = pstcAddr->u32TxBufferStartAddr + u32ElementNum * MCAN_TX_ES(MCANx); + u32ElementNum = MCAN_GET_TX_FQ_NUM(MCANx); + pstcAddr->u32EndAddr = pstcAddr->u32TxFifoQueueStartAddr + u32ElementNum * MCAN_TX_ES(MCANx); + + /* Get each standard filter element address. */ + if (pstcAddr->pu32StdFilterAddrList != NULL) { + u32ElementNum = MCAN_GET_STD_FILTER_NUM(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32StdFilterAddrList[i] = pstcAddr->u32StdFilterStartAddr + i * MCAN_STD_FILTER_ES; + } + } + /* Get each extended filter element address. */ + if (pstcAddr->pu32ExtFilterAddrList != NULL) { + u32ElementNum = MCAN_GET_EXT_FILTER_NUM(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32ExtFilterAddrList[i] = pstcAddr->u32ExtFilterStartAddr + i * MCAN_EXT_FILTER_ES; + } + } + /* Get each Rx FIFO0 element address. */ + if (pstcAddr->pu32RxFifo0AddrList != NULL) { + u32ElementNum = MCAN_GET_RX_FIFO0_NUM(MCANx); + u32ElementSize = MCAN_RX_FIFO0_ES(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32RxFifo0AddrList[i] = pstcAddr->u32RxFifo0StartAddr + i * u32ElementSize; + } + } + /* Get each Rx FIFO1 element address. */ + if (pstcAddr->pu32RxFifo1AddrList != NULL) { + u32ElementNum = MCAN_GET_RX_FIFO1_NUM(MCANx); + u32ElementSize = MCAN_RX_FIFO1_ES(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32RxFifo1AddrList[i] = pstcAddr->u32RxFifo1StartAddr + i * u32ElementSize; + } + } + /* Get each Rx buffer element address. */ + if (pstcAddr->pu32RxBufferAddrList != NULL) { + u32ElementNum = MCAN_GetRxBufferNum(MCANx); + u32ElementSize = MCAN_RX_BUF_ES(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32RxBufferAddrList[i] = pstcAddr->u32RxBufferStartAddr + i * u32ElementSize; + } + } + /* Get each Tx event FIFO element address. */ + if (pstcAddr->pu32TxEventAddrList != NULL) { + u32ElementNum = MCAN_GET_TX_EVT_FIFO_NUM(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32TxEventAddrList[i] = pstcAddr->u32TxEventStartAddr + i * MCAN_TX_EVT_ES; + } + } + /* Get each dedicated Tx buffer element address. */ + if (pstcAddr->pu32TxBufferAddrList != NULL) { + u32ElementNum = MCAN_GET_TX_BUF_NUM(MCANx); + u32ElementSize = MCAN_TX_ES(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32TxBufferAddrList[i] = pstcAddr->u32TxBufferStartAddr + i * u32ElementSize; + } + } + /* Get each Tx FIFO/Queue element address. */ + if (pstcAddr->pu32TxFifoQueueAddrList != NULL) { + u32ElementNum = MCAN_GET_TX_FQ_NUM(MCANx); + u32ElementSize = MCAN_TX_ES(MCANx); + for (i = 0U; i < u32ElementNum; i++) { + pstcAddr->pu32TxFifoQueueAddrList[i] = pstcAddr->u32TxFifoQueueStartAddr + i * u32ElementSize; + } + } + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Configure a reception filter element in the message RAM according to the specified parameters + * in the stc_mcan_filter_t structure. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pstcFilter Pointer to a @ref stc_mcan_filter_t structure that + * contains the filter configuration information. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcFilter == NULL. + * @note Call this API after message RAM configured. + */ +int32_t MCAN_FilterConfig(const CM_MCAN_TypeDef *MCANx, const stc_mcan_filter_t *pstcFilter) +{ + uint32_t u32F0; + uint32_t u32F1; + uint32_t *pu32FilterMem; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pstcFilter != NULL) { + i32Ret = LL_OK; + DDL_ASSERT(IS_MCAN_ID_TYPE(pstcFilter->u32IdType)); + DDL_ASSERT(IS_MCAN_FILTER_CFG(pstcFilter->u32FilterConfig)); + if (pstcFilter->u32FilterConfig == MCAN_FILTER_TO_RX_BUF) { + DDL_ASSERT(pstcFilter->u32RxBufferIndex < MCAN_GetRxBufferNum(MCANx)); + } + + /* Build filter configuration value */ + if (pstcFilter->u32IdType == MCAN_STD_ID) { + /* Configures the standard ID filter element */ + DDL_ASSERT(pstcFilter->u32FilterIndex < MCAN_GET_STD_FILTER_NUM(MCANx)); + DDL_ASSERT(IS_MCAN_STD_ID_VAL(pstcFilter->u32FilterId1)); + + /* Build the filter element */ + if (pstcFilter->u32FilterConfig == MCAN_FILTER_TO_RX_BUF) { + u32F0 = ((pstcFilter->u32FilterConfig << MCAN_FILTER_SFCFG_POS) | \ + (pstcFilter->u32FilterId1 << MCAN_FILTER_SFID1_POS) | \ + pstcFilter->u32RxBufferIndex); + } else { + DDL_ASSERT(IS_MCAN_STD_FILTER_TYPE(pstcFilter->u32FilterType)); + DDL_ASSERT(IS_MCAN_STD_ID_VAL(pstcFilter->u32FilterId2)); + u32F0 = ((pstcFilter->u32FilterType << MCAN_FILTER_SFTYPE_POS) | \ + (pstcFilter->u32FilterConfig << MCAN_FILTER_SFCFG_POS) | \ + (pstcFilter->u32FilterId1 << MCAN_FILTER_SFID1_POS) | \ + pstcFilter->u32FilterId2); + } + + /* Calculate filter address */ + pu32FilterMem = (uint32_t *)(MCAN_STD_FILTER_SA(MCANx) + (pstcFilter->u32FilterIndex * MCAN_STD_FILTER_ES)); + + /* Write filter element to the message RAM */ + pu32FilterMem[0] = u32F0; + } else { + /* Configures the extended ID filter element */ + DDL_ASSERT(pstcFilter->u32FilterIndex < MCAN_GET_EXT_FILTER_NUM(MCANx)); + DDL_ASSERT(IS_MCAN_EXT_ID_VAL(pstcFilter->u32FilterId1)); + + /* Build the first word of the filter element */ + u32F0 = ((pstcFilter->u32FilterConfig << MCAN_FILTER_EFCFG_POS) | pstcFilter->u32FilterId1); + + /* Build the second word of the filter element */ + if (pstcFilter->u32FilterConfig == MCAN_FILTER_TO_RX_BUF) { + u32F1 = pstcFilter->u32RxBufferIndex; + } else { + DDL_ASSERT(IS_MCAN_EXT_FILTER_TYPE(pstcFilter->u32FilterType)); + DDL_ASSERT(IS_MCAN_EXT_ID_VAL(pstcFilter->u32FilterId2)); + u32F1 = ((pstcFilter->u32FilterType << MCAN_FILTER_EFTYPE_POS) | pstcFilter->u32FilterId2); + } + + /* Calculate filter address */ + pu32FilterMem = (uint32_t *)(MCAN_EXT_FILTER_SA(MCANx) + (pstcFilter->u32FilterIndex * MCAN_EXT_FILTER_ES)); + + /* Write filter element to the message RAM */ + pu32FilterMem[0U] = u32F0; + pu32FilterMem[1U] = u32F1; + } + } + + return i32Ret; +} + +/** + * @brief Configures the MCAN global filter. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32StdNmfOperation The operation of non-matching standard frame. + * This parameter can be a value of @ref MCAN_NMF_Operation + * @arg MCAN_NMF_ACCEPT_IN_RX_FIFO0: Accept non-matching standard frames in Rx FIFO0. + * @arg MCAN_NMF_ACCEPT_IN_RX_FIFO1: Accept non-matching standard frames in Rx FIFO1. + * @arg MCAN_NMF_REJECT: Reject all non-matching standard frames. + * @param [in] u32ExtNmfOperation The operation of non-matching extended frame. + * This parameter can be a value of @ref MCAN_NMF_Operation + * @arg MCAN_NMF_ACCEPT_IN_RX_FIFO0: Accept non-matching extended frames in Rx FIFO0. + * @arg MCAN_NMF_ACCEPT_IN_RX_FIFO1: Accept non-matching extended frames in Rx FIFO1. + * @arg MCAN_NMF_REJECT: Reject all non-matching extended frames. + * @param [in] u32StdRemoteOperation The operation of standard remote frame. + * This parameter can be a value of @ref MCAN_Remote_Frame_Operation + * @arg MCAN_REMOTE_FRAME_FILTER: Filter standard remote frames with ID. + * @arg MCAN_REMOTE_FRAME_REJECT: Reject all standard remote frames. + * @param [in] u32ExtRemoteOperation The operation of extended remote frame. + * This parameter can be a value of @ref MCAN_Remote_Frame_Operation + * @arg MCAN_REMOTE_FRAME_FILTER: Filter extended remote frames with ID. + * @arg MCAN_REMOTE_FRAME_REJECT: Reject all extended remote frames. + * @retval None + */ +void MCAN_GlobalFilterConfig(CM_MCAN_TypeDef *MCANx, \ + uint32_t u32StdNmfOperation, uint32_t u32ExtNmfOperation, \ + uint32_t u32StdRemoteOperation, uint32_t u32ExtRemoteOperation) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_NMF_OP(u32StdNmfOperation)); + DDL_ASSERT(IS_MCAN_NMF_OP(u32ExtNmfOperation)); + DDL_ASSERT(IS_MCAN_REMOTE_FRAME_OP(u32StdRemoteOperation)); + DDL_ASSERT(IS_MCAN_REMOTE_FRAME_OP(u32ExtRemoteOperation)); + + WRITE_REG32(MCANx->GFC, ((u32StdNmfOperation << MCAN_GFC_ANFS_POS) | \ + (u32ExtNmfOperation << MCAN_GFC_ANFE_POS) | \ + (u32StdRemoteOperation << MCAN_GFC_RRFS_POS) | \ + (u32ExtRemoteOperation << MCAN_GFC_RRFE_POS))); +} + +/** + * @brief Set the extended ID mask. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32Mask Extended ID AND(logic AND operation) mask. + * This parameter must be a number between 0 and 0x1FFFFFFF. + * For acceptance filtering of extended frames the extended ID AND + * mask is ANDed with the message ID of a received frame. With the + * reset value of all bits set to one(0x1FFFFFFF) the mask is not active. + * @retval None + */ +void MCAN_SetExtIDMask(CM_MCAN_TypeDef *MCANx, uint32_t u32Mask) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_EXT_ID_VAL(u32Mask)); + WRITE_REG32(MCANx->XIDAM, u32Mask); +} + +/** + * @brief Configures the Rx FIFO operation mode. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg MCAN_RX_FIFO0: Rx FIFO0 + * @arg MCAN_RX_FIFO1: Rx FIFO1 + * @param [in] u32OperationMode Rx FIFO operation mode. + * This parameter can be one of @ref MCAN_Rx_Fifo_Operation_Mode + * @arg MCAN_RX_FIFO_BLOCKING: Rx FIFO blocking mode. + * New received message will not be stored. + * @arg MCAN_RX_FIFO_OVERWRITE: Rx FIFO overwrite mode. + * New received message will overwrite the oldest received message. + * @retval None + */ +void MCAN_RxFifoOperationModeConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32RxFifo, uint32_t u32OperationMode) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_RX_FIFO(u32RxFifo)); + DDL_ASSERT(IS_MCAN_RX_FIFO_MD(u32OperationMode)); + + if (u32RxFifo == MCAN_RX_FIFO0) { + /* Set Rx FIFO0 operation mode */ + MODIFY_REG32(MCANx->RXF0C, MCAN_RXF0C_F0OM, u32OperationMode); + } else { + /* Set Rx FIFO1 operation mode */ + MODIFY_REG32(MCANx->RXF1C, MCAN_RXF1C_F1OM, u32OperationMode); + } +} + +/** + * @brief Set the watermark of the specified FIFO. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32Fifo FIFO that supports watermark interrupt. + * This parameter can be one of the following values: + * @arg MCAN_WATERMARK_RX_FIFO0: Rx FIFO0. + * @arg MCAN_WATERMARK_RX_FIFO1: Rx FIFO1. + * @arg MCAN_WATERMARK_TX_EVT_FIFO: Tx event FIFO. + * @param [in] u32Watermark Level for FIFO watermark interrupt. + * This parameter must be a number between: + * - 0 and u32RxFifo0Num of @ref stc_mcan_msg_ram_config_t, if u32Fifo is MCAN_WATERMARK_RX_FIFO0 + * - 0 and u32RxFifo1Num of @ref stc_mcan_msg_ram_config_t, if u32Fifo is MCAN_WATERMARK_RX_FIFO1 + * - 0 and u32TxEventNum of @ref stc_mcan_msg_ram_config_t, if u32Fifo is MCAN_WATERMARK_TX_EVT_FIFO + * @retval None + * @note Call this API after message RAM configured. + */ +void MCAN_SetFifoWatermark(CM_MCAN_TypeDef *MCANx, uint32_t u32Fifo, uint32_t u32Watermark) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_WATERMARK_FIFO(u32Fifo)); + + switch (u32Fifo) { + case MCAN_WATERMARK_RX_FIFO0: + /* Set Rx FIFO0 watermark */ + DDL_ASSERT(u32Watermark <= MCAN_GET_RX_FIFO0_NUM(MCANx)); + MODIFY_REG32(MCANx->RXF0C, MCAN_RXF0C_F0WM, (u32Watermark << MCAN_RXF0C_F0WM_POS)); + break; + + case MCAN_WATERMARK_RX_FIFO1: + /* Set Rx FIFO1 watermark */ + DDL_ASSERT(u32Watermark <= MCAN_GET_RX_FIFO1_NUM(MCANx)); + MODIFY_REG32(MCANx->RXF1C, MCAN_RXF1C_F1WM, (u32Watermark << MCAN_RXF1C_F1WM_POS)); + break; + + case MCAN_WATERMARK_TX_EVT_FIFO: + /* Set Tx event FIFO watermark */ + DDL_ASSERT(u32Watermark <= MCAN_GET_TX_EVT_FIFO_NUM(MCANx)); + MODIFY_REG32(MCANx->TXEFC, MCAN_TXEFC_EFWM, (u32Watermark << MCAN_TXEFC_EFWM_POS)); + break; + + default: + break; + } +} + +/** + * @brief Set the start value of the message RAM watchdog counter. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32StartValue The start value of the message RAM watchdog counter. + * This parameter must be a number between 0x00 and 0xFF, + * with the reset value of 0x00 the counter is disabled. + * @retval None + */ +void MCAN_RamWatchdogConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32StartValue) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_RAM_WDT_START_VAL(u32StartValue)); + + /* Set the message RAM watchdog counter start value */ + MODIFY_REG32(MCANx->RWD, MCAN_RWD_WDC, u32StartValue); +} + +/** + * @brief Get the actual message RAM watchdog counter value. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint8_t type value of the actual message RAM watchdog counter value. + */ +uint8_t MCAN_GetRamWatchdogCountValue(const CM_MCAN_TypeDef *MCANx) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + return (uint8_t)(READ_REG32_BIT(MCANx->RWD, MCAN_RWD_WDV) >> MCAN_RWD_WDV_POS); +} + +/** + * @brief Configures MCAN timestamp. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32TsPrescaler Timestamp counter prescaler. + * This parameter must be a value between 1 and 16. + * @retval None + */ +void MCAN_TimestampCounterConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32TsPrescaler) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_TS_PRESC(u32TsPrescaler)); + + /* Set timestamp prescaler */ + MODIFY_REG32(MCANx->TSCC, MCAN_TSCC_TCP, (u32TsPrescaler - 1U) << MCAN_TSCC_TCP_POS); +} + +/** + * @brief Enable or disable the timestamp counter. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable timestamp counter. + * @arg DISABLE: Disable timestamp counter. + * @retval None + */ +void MCAN_TimestampCounterCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + /* Enable timestamp counter */ + SET_REG32_BIT(MCANx->TSCC, MCAN_TSCC_TSS_0); + } else { + /* Disable timestamp counter */ + CLR_REG32_BIT(MCANx->TSCC, MCAN_TSCC_TSS); + } +} + +/** + * @brief Get the timestamp counter value. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint16_t type value of timestamp counter. + */ +uint16_t MCAN_GetTimestampCounter(const CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + return (uint16_t)(MCANx->TSCV); +} + +/** + * @brief Reset the timestamp counter to zero. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval None + */ +void MCAN_ResetTimestampCounter(CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + /* Reset timestamp counter. */ + CLR_REG32(MCANx->TSCV); +} + +/** + * @brief Set the watermark of the specified FIFO. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32ToSelect Timeout select. + * This parameter can be one of @ref MCAN_Timeout_Select + * @arg MCAN_TIMEOUT_CONT: Timeout continuous operation. + * @arg MCAN_TIMEOUT_TX_EVT_FIFO: Timeout controlled by Tx event FIFO. + * @arg MCAN_TIMEOUT_RX_FIFO0: Timeout controlled by Rx FIFO0. + * @arg MCAN_TIMEOUT_RX_FIFO1: Timeout controlled by Rx FIFO1. + * @param [in] u32ToPeriod Start value of the timeout counter.Configures the Timeout Period. + * This parameter must be a number between 0x0000 and 0xFFFF + * @retval None + */ +void MCAN_TimeoutCounterConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32ToSelect, uint32_t u32ToPeriod) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_TO_SEL(u32ToSelect)); + DDL_ASSERT(IS_MCAN_TO_PERIOD(u32ToPeriod)); + + /* Select timeout operation and configure period */ + MODIFY_REG32(MCANx->TOCC, (MCAN_TOCC_TOS | MCAN_TOCC_TOP), + (u32ToSelect | (u32ToPeriod << MCAN_TOCC_TOP_POS))); +} + +/** + * @brief Enable or disable the timeout counter. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable timeout counter. + * @arg DISABLE: Disable timeout counter. + * @retval None + */ +void MCAN_TimeoutCounterCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + /* Enable timeout counter */ + SET_REG32_BIT(MCANx->TOCC, MCAN_TOCC_ETOC); + } else { + /* Disable timeout counter */ + CLR_REG32_BIT(MCANx->TOCC, MCAN_TOCC_ETOC); + } +} + +/** + * @brief Get the timeout counter value. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint16_t type value of timeout counter. + */ +uint16_t MCAN_GetTimeoutCounter(const CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + return (uint16_t)(MCANx->TOCV); +} + +/** + * @brief Reset the timeout counter to its start value. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval None + */ +void MCAN_ResetTimeoutCounter(CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (READ_REG32_BIT(MCANx->TOCC, MCAN_TOCC_TOS) == MCAN_TIMEOUT_CONT) { + /* Reset timeout counter to start value */ + CLR_REG32(MCANx->TOCV); + } +} + +/** + * @brief Configure the transmitter delay compensation + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32SspOffset Transmitter delay compensation offset. + * @param [in] u32TdcFilter Transmitter delay compensation filter window length. + * This parameter must be a number between 0x00 and 0x7F + * @retval None + */ +void MCAN_TxDelayCompensationConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32SspOffset, uint32_t u32TdcFilter) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_SSP(u32SspOffset)); + DDL_ASSERT(IS_MCAN_TDC_FILTER(u32TdcFilter)); + + /* Configure TDC offset and filter window */ + WRITE_REG32(MCANx->TDCR, ((u32SspOffset << MCAN_TDCR_TDCO_POS) | (u32TdcFilter << MCAN_TDCR_TDCF_POS))); +} + +/** + * @brief Enable or disable the transmitter delay compensation. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable transmitter delay compensation. + * @arg DISABLE: Disable transmitter delay compensation. + * @retval None + */ +void MCAN_TxDelayCompensationCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + /* Enable transmitter delay compensation */ + SET_REG32_BIT(MCANx->DBTP, MCAN_DBTP_TDC); + } else { + /* Disable transmitter delay compensation */ + CLR_REG32_BIT(MCANx->DBTP, MCAN_DBTP_TDC); + } +} + +/** + * @brief Specifies the CAN frame format. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32FrameFormat CAN frame format. + * This parameter can be a value of @ref MCAN_Frame_Format + * @arg MCAN_FRAME_CLASSIC: Classic CAN mode. + * @arg MCAN_FRAME_ISO_FD_NO_BRS: ISO CAN FD mode without bit rate switching. + * @arg MCAN_FRAME_ISO_FD_BRS: ISO CAN FD mode with bit rate switching. + * @arg MCAN_FRAME_NON_ISO_FD_NO_BRS: Non-ISO CAN FD mode without bit rate switching. + * @arg MCAN_FRAME_NON_ISO_FD_BRS: Non-ISO CAN FD mode with bit rate switching. + * @retval None + */ +void MCAN_SetFrameFormat(CM_MCAN_TypeDef *MCANx, uint32_t u32FrameFormat) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_FRAME_FORMAT(u32FrameFormat)); + + MODIFY_REG32(MCANx->CCCR, MCAN_FRAME_NON_ISO_FD_BRS, u32FrameFormat); +} + +/** + * @brief Enable or disable the edge filtering during bus integration. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable edge filtering. + * @arg DISABLE: Disable edge filtering. + * @retval None + */ +void MCAN_EdgeFilteringCmd(CM_MCAN_TypeDef *MCANx, en_functional_state_t enNewState) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + /* Enable edge filtering */ + SET_REG32_BIT(MCANx->CCCR, MCAN_CCCR_EFBI); + } else { + /* Disable edge filtering */ + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_EFBI); + } +} + +/** + * @brief Config message marker for Tx event + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32MsgMarker Message marker configuration. + * @arg MCAN_MSG_MARKER_8BIT: 8-bit message marker used. + * @arg MCAN_MSG_MARKER_16BIT: 16-bit Message Marker used, replacing 16-bit timestamps in Tx Event FIFO. + * @retval None + */ +void MCAN_TxEventMsgMarkerConfig(CM_MCAN_TypeDef *MCANx, uint32_t u32MsgMarker) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_MSG_MARKER_CFG(u32MsgMarker)); + + MODIFY_REG32(MCANx->CCCR, MCAN_CCCR_WMM, u32MsgMarker); +} + +/** + * @brief Add a message to the Tx FIFO/Queue and activate the corresponding transmission request. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pTxMsg Pointer to a @ref stc_mcan_tx_msg_t structure that contains + * the information of the message that to be transmitted. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pTxMsg == NULL. + * Tx FIFO/queue has an allocated area into the message RAM. + * Size of the message data payload is bigger than the configured value. + * - LL_ERR_BUF_FULL: Tx FIFO/queue is full. + */ +int32_t MCAN_AddMsgToTxFifoQueue(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_msg_t *pTxMsg) +{ + uint32_t u32TxPutIndex; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + if (pTxMsg != NULL) { + DDL_ASSERT(IS_MCAN_ID_TYPE(pTxMsg->IDE)); + if (pTxMsg->IDE == MCAN_STD_ID) { + DDL_ASSERT(IS_MCAN_STD_ID_VAL(pTxMsg->ID)); + } else { + DDL_ASSERT(IS_MCAN_EXT_ID_VAL(pTxMsg->ID)); + } + DDL_ASSERT(IS_MCAN_FRAME_RTR(pTxMsg->RTR)); + DDL_ASSERT(IS_MCAN_FRAME_DLC(pTxMsg->DLC)); + DDL_ASSERT(IS_MCAN_FRAME_ESI(pTxMsg->ESI)); + DDL_ASSERT(IS_MCAN_FRAME_BRS(pTxMsg->BRS)); + DDL_ASSERT(IS_MCAN_FRAME_FDF(pTxMsg->FDF)); + DDL_ASSERT(IS_MCAN_FRAME_EFC(pTxMsg->u32StoreTxEvent)); + u32TxPutIndex = READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_WMM); + DDL_ASSERT(IS_MCAN_FRAME_MSG_MARKER(u32TxPutIndex, pTxMsg->u32MsgMarker)); + + /* Check that the Tx FIFO/Queue has an allocated area into the message RAM. + Check that the data field size is not bigger than the configured value. */ + if (READ_REG32_BIT(MCANx->TXBC, MCAN_TXBC_TFQS) != 0U) { + /* Check that the Tx FIFO/queue is not full */ + if (READ_REG32_BIT(MCANx->TXFQS, MCAN_TXFQS_TFQF) == 0U) { + /* Retrieve the Tx FIFO put index */ + u32TxPutIndex = (READ_REG32_BIT(MCANx->TXFQS, MCAN_TXFQS_TFQPI) >> MCAN_TXFQS_TFQPI_POS); + + /* Add the message to the Tx FIFO/Queue */ + MCAN_CopyTxMsgToRam(MCANx, pTxMsg, u32TxPutIndex); + + /* Store the last Tx FIFO/queue request buffer index. */ + pTxMsg->u32LastTxFifoQueueRequest = 1UL << u32TxPutIndex; + /* Activate the corresponding transmission request. */ + WRITE_REG32(MCANx->TXBAR, pTxMsg->u32LastTxFifoQueueRequest); + + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_BUF_FULL; + } + } + } + + return i32Ret; +} + +/** + * @brief Add a message to a dedicated Tx buffer. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] pTxMsg Pointer to a @ref stc_mcan_tx_msg_t structure that contains + * the information of the message that to be transmitted. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pTxMsg == NULL. + * The selected buffer has no allocated area into the message RAM. + * Size of the message data payload is bigger than the configured value. + * - LL_ERR_BUSY: There is a transmission request pending for the selected buffer. + */ +int32_t MCAN_AddMsgToTxBuffer(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_msg_t *pTxMsg) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32TxPutIndex; + uint32_t u32TxBufferNum; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + if (pTxMsg != NULL) { + DDL_ASSERT(IS_MCAN_ID_TYPE(pTxMsg->IDE)); + if (pTxMsg->IDE == MCAN_STD_ID) { + DDL_ASSERT(IS_MCAN_STD_ID_VAL(pTxMsg->ID)); + } else { + DDL_ASSERT(IS_MCAN_EXT_ID_VAL(pTxMsg->ID)); + } + DDL_ASSERT(IS_MCAN_FRAME_RTR(pTxMsg->RTR)); + DDL_ASSERT(IS_MCAN_FRAME_DLC(pTxMsg->DLC)); + DDL_ASSERT(IS_MCAN_FRAME_ESI(pTxMsg->ESI)); + DDL_ASSERT(IS_MCAN_FRAME_BRS(pTxMsg->BRS)); + DDL_ASSERT(IS_MCAN_FRAME_FDF(pTxMsg->FDF)); + DDL_ASSERT(IS_MCAN_FRAME_EFC(pTxMsg->u32StoreTxEvent)); + u32TxPutIndex = READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_WMM); + DDL_ASSERT(IS_MCAN_FRAME_MSG_MARKER(u32TxPutIndex, pTxMsg->u32MsgMarker)); + DDL_ASSERT(IS_MCAN_1TXBUF(pTxMsg->u32TxBuffer)); + u32TxBufferNum = MCAN_GET_TX_BUF_NUM(MCANx); + u32TxPutIndex = GET_BIT_POS(pTxMsg->u32TxBuffer); + DDL_ASSERT(u32TxPutIndex < u32TxBufferNum); + + /* Check that the selected buffer has an allocated area into the message RAM. + Check that the data field size is not bigger than the configured value. */ + if (u32TxPutIndex < u32TxBufferNum) { + /* Check that there is no transmission request pending for the selected buffer */ + if (READ_REG32_BIT(MCANx->TXBRP, pTxMsg->u32TxBuffer) == 0U) { + /* Add the message to the Tx buffer */ + MCAN_CopyTxMsgToRam(MCANx, pTxMsg, u32TxPutIndex); + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_BUSY; + } + } + } + + return i32Ret; +} + +/** + * @brief Enable transmission request of the specified Tx buffer(s). + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32TxBuffer Tx buffer(s) location. + * This parameter can be any combination of @ref MCAN_Tx_Location + * @retval None + */ +void MCAN_EnableTxBufferRequest(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer) +{ +#ifdef __DEBUG + uint32_t u32TxBufferNum; +#endif + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); +#ifdef __DEBUG + u32TxBufferNum = MCAN_GET_TX_BUF_NUM(MCANx); + u32TxBufferNum += MCAN_GET_TX_FQ_NUM(MCANx); + if (u32TxBufferNum < MCAN_TX_ELMT_NUM_MAX) { + DDL_ASSERT(IS_MCAN_BIT_MASK(u32TxBuffer, (1UL << u32TxBufferNum) - 1U)); + } +#endif + + /* Add transmission request */ + WRITE_REG32(MCANx->TXBAR, u32TxBuffer); +} + +/** + * @brief Abort the transmission request of the specified Tx buffer(s). + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32TxBuffer Tx buffer(s) location. + * This parameter can be any combination of @ref MCAN_Tx_Location + * @retval None + */ +void MCAN_AbortTxRequest(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer) +{ +#ifdef __DEBUG + uint32_t u32TxBufferNum; +#endif + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); +#ifdef __DEBUG + u32TxBufferNum = MCAN_GET_TX_BUF_NUM(MCANx); + u32TxBufferNum += MCAN_GET_TX_FQ_NUM(MCANx); + if (u32TxBufferNum < MCAN_TX_ELMT_NUM_MAX) { + DDL_ASSERT(IS_MCAN_BIT_MASK(u32TxBuffer, (1UL << u32TxBufferNum) - 1U)); + } +#endif + + /* Add cancellation request */ + WRITE_REG32(MCANx->TXBCR, u32TxBuffer); +} + +/** + * @brief Get a received frame from the Rx buffer/FIFO zone into the message RAM. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32RxLocation Location of the received message to be read. + * This parameter can be a value of @ref MCAN_Rx_Location + * @param [out] pRxMsg Pointer to a @ref stc_mcan_rx_msg_t structure which is used to save + * the received frame. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pRxMsg == NULL; + * The selected Rx FIFO has no allocated area into the message RAM; + * The selected Rx buffer is out of range. + * - LL_ERR_BUF_EMPTY: The selected Rx FIFO is empty. + */ +int32_t MCAN_GetRxMsg(CM_MCAN_TypeDef *MCANx, uint32_t u32RxLocation, stc_mcan_rx_msg_t *pRxMsg) +{ + uint32_t i; + uint32_t u32RxRamAddr = 0U; + uint32_t u32Tmp; + uint32_t u32DataFiledSize = 0U; + uint32_t u32RxGetIndex = 0U; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pRxMsg != NULL) { + i32Ret = LL_OK; + if (u32RxLocation == MCAN_RX_FIFO0) { + /* Check that the Rx FIFO0 has an allocated area into the message RAM */ + if (READ_REG32_BIT(MCANx->RXF0C, MCAN_RXF0C_F0S) == 0U) { + i32Ret = LL_ERR_INVD_PARAM; + } + + if (i32Ret == LL_OK) { + /* Check that the Rx FIFO0 is not empty */ + if (READ_REG32_BIT(MCANx->RXF0S, MCAN_RXF0S_F0FL) == 0U) { + i32Ret = LL_ERR_BUF_EMPTY; + } + } + + if (i32Ret == LL_OK) { + /* Calculate Rx FIFO0 element index*/ + u32RxGetIndex = (READ_REG32_BIT(MCANx->RXF0S, MCAN_RXF0S_F0GI) >> MCAN_RXF0S_F0GI_POS); + + /* Calculate Rx FIFO0 element address */ + u32RxRamAddr = MCAN_RX_FIFO0_SA(MCANx); + u32RxRamAddr += (u32RxGetIndex * MCAN_RX_FIFO0_ES(MCANx)); + + /* Get the configured data filed size of Rx FIFO0 */ + u32DataFiledSize = MCAN_RX_FIFO0_REAL_DS(MCANx); + } + } else if (u32RxLocation == MCAN_RX_FIFO1) { + /* Check that the Rx FIFO1 has an allocated area into the message RAM */ + if (READ_REG32_BIT(MCANx->RXF1C, MCAN_RXF1C_F1S) == 0U) { + i32Ret = LL_ERR_INVD_PARAM; + } + + if (i32Ret == LL_OK) { + /* Check that the Rx FIFO1 is not empty */ + if (READ_REG32_BIT(MCANx->RXF1S, MCAN_RXF1S_F1FL) == 0U) { + i32Ret = LL_ERR_BUF_EMPTY; + } + } + + if (i32Ret == LL_OK) { + /* Calculate Rx FIFO1 element index */ + u32RxGetIndex = (READ_REG32_BIT(MCANx->RXF1S, MCAN_RXF1S_F1GI) >> MCAN_RXF1S_F1GI_POS); + + /* Calculate Rx FIFO1 element address */ + u32RxRamAddr = MCAN_RX_FIFO1_SA(MCANx); + u32RxRamAddr += (u32RxGetIndex * MCAN_RX_FIFO1_ES(MCANx)); + + /* Get the configured data filed size of Rx FIFO1 */ + u32DataFiledSize = MCAN_RX_FIFO1_REAL_DS(MCANx); + } + } else { + /* Rx element is assigned to a dedicated Rx buffer. + Check that the selected buffer has an allocated area into the message RAM. */ + if (u32RxLocation >= MCAN_GetRxBufferNum(MCANx)) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Calculate Rx buffer address */ + u32RxRamAddr = MCAN_RX_BUF_SA(MCANx); + u32RxRamAddr += (u32RxLocation * MCAN_RX_BUF_ES(MCANx)); + + /* Get the configured data filed size of Rx buffer */ + u32DataFiledSize = MCAN_RX_BUF_REAL_DS(MCANx); + } + } + + if (i32Ret == LL_OK) { + /* Retrieve ID type */ + pRxMsg->IDE = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_XTD_MASK) >> MCAN_FRAME_XTD_POS; + /* Retrieve ID type */ + if (pRxMsg->IDE == MCAN_STD_ID) { + /* Standard ID element */ + pRxMsg->ID = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_STDID_MASK) >> MCAN_FRAME_STDID_POS; + } else { + /* Extended ID element */ + pRxMsg->ID = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_EXTID_MASK); + } + + /* Retrieve Rx frame type */ + pRxMsg->RTR = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_RTR_MASK) >> MCAN_FRAME_RTR_POS; + + /* Retrieve ESI */ + pRxMsg->ESI = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_ESI_MASK) >> MCAN_FRAME_ESI_POS; + + /* Increment Rx memory pointer to second word of Rx FIFO element */ + u32RxRamAddr += 4UL; + + /* Retrieve Rx timestamp */ + pRxMsg->u32RxTimestamp = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_TS_MASK); + + /* Retrieve DLC */ + pRxMsg->DLC = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_DLC_MASK) >> MCAN_FRAME_DLC_POS; + pRxMsg->u32DataSize = m_au8DLC2Size[pRxMsg->DLC]; + + /* Retrieve BRS */ + pRxMsg->BRS = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_BRS_MASK) >> MCAN_FRAME_BRS_POS; + + /* Retrieve FDF */ + pRxMsg->FDF = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_FDF_MASK) >> MCAN_FRAME_FDF_POS; + /* Determine the CAN frame format: classical CAN or FD CAN */ + if (pRxMsg->FDF == 0U) { + /* Max 8 bytes for classical CAN */ + if (pRxMsg->u32DataSize > CAN20_DATA_SIZE_MAX) { + pRxMsg->u32DataSize = CAN20_DATA_SIZE_MAX; + } + } else { + /* Max size of the stored data is the allocated size */ + if (pRxMsg->u32DataSize > u32DataFiledSize) { + pRxMsg->u32DataSize = u32DataFiledSize; + } + } + + /* Retrieve filter index */ + pRxMsg->u32FilterIndex = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_FIDX_MASK) >> MCAN_FRAME_FIDX_POS; + + /* Retrieve non-matching frame */ + pRxMsg->u32NmfFlag = READ_REG32_BIT(RW_MEM32(u32RxRamAddr), MCAN_FRAME_ANMF_MASK) >> MCAN_FRAME_ANMF_POS; + + /* Increment Rx memory pointer to payload of Rx FIFO element */ + /* Retrieve Rx payload */ + if (pRxMsg->RTR == 0U) { + /* Read the Rx payload from the message RAM. */ + for (i = 0U; i < pRxMsg->u32DataSize; i += 4U) { + u32RxRamAddr += 4U; + u32Tmp = RW_MEM32(u32RxRamAddr); + pRxMsg->au8Data[i] = (uint8_t)(u32Tmp); + pRxMsg->au8Data[i + 1U] = (uint8_t)(u32Tmp >> 8U); + pRxMsg->au8Data[i + 2U] = (uint8_t)(u32Tmp >> 16U); + pRxMsg->au8Data[i + 3U] = (uint8_t)(u32Tmp >> 24U); + } + } + + if (u32RxLocation == MCAN_RX_FIFO0) { + /* Rx element is assigned to the Rx FIFO0. + Acknowledge the Rx FIFO0 that the oldest element + is read so that it increments the get index. */ + WRITE_REG32(MCANx->RXF0A, u32RxGetIndex); + } else if (u32RxLocation == MCAN_RX_FIFO1) { + /* Rx element is assigned to the Rx FIFO1. + Acknowledge the Rx FIFO1 that the oldest element + is read so that it increments the get index. */ + WRITE_REG32(MCANx->RXF1A, u32RxGetIndex); + } else { + /* Rx element is assigned to a dedicated Rx buffer. + Clear the new data flag of the current Rx buffer. */ + if (u32RxLocation < MCAN_RX_BUF32) { + WRITE_REG32(MCANx->NDAT1, (1UL << u32RxLocation)); + } else { + WRITE_REG32(MCANx->NDAT2, (1UL << (u32RxLocation & 0x1FUL))); + } + } + } + } + + return i32Ret; +} + +/** + * @brief Get a Tx event from the Tx event FIFO zone into the message RAM. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [out] pTxEvent Pointer to a @ref stc_mcan_tx_event_t structure which is used to save + * the Tx event. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pTxEvent == NULL; + * - LL_ERR_BUF_EMPTY: The Tx event FIFO is empty. + */ +int32_t MCAN_GetTxEvent(CM_MCAN_TypeDef *MCANx, stc_mcan_tx_event_t *pTxEvent) +{ + uint32_t u32TxEventAddr; + uint32_t u32GetIndex; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pTxEvent != NULL) { + i32Ret = LL_OK; + + /* Check that the Tx Event FIFO has an allocated area into the message RAM */ + if (READ_REG32_BIT(MCANx->TXEFC, MCAN_TXEFC_EFS) == 0U) { + /* The Tx event has no allocated area into the message RAM. */ + i32Ret = LL_ERR_INVD_PARAM; + } + + /* Check that the Tx event FIFO is not empty */ + if (i32Ret == LL_OK) { + if (READ_REG32_BIT(MCANx->TXEFS, MCAN_TXEFS_EFFL) == 0U) { + /* The Tx event FIFO is empty */ + i32Ret = LL_ERR_BUF_EMPTY; + } + } + + if (i32Ret == LL_OK) { + /* Calculate Tx event FIFO element address */ + u32GetIndex = READ_REG32_BIT(MCANx->TXEFS, MCAN_TXEFS_EFGI) >> MCAN_TXEFS_EFGI_POS; + u32TxEventAddr = MCAN_TX_EVT_FIFO_SA(MCANx) + (u32GetIndex * MCAN_TX_EVT_ES); + + /* Retrieve ID type */ + pTxEvent->IDE = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_XTD_MASK) >> MCAN_FRAME_XTD_POS; + + /* Retrieve ID */ + if (pTxEvent->IDE == MCAN_STD_ID) { + /* Standard ID element */ + pTxEvent->ID = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_STDID_MASK) >> MCAN_FRAME_STDID_POS; + } else { + /* Extended ID element */ + pTxEvent->ID = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_EXTID_MASK); + } + + /* Retrieve Tx frame type */ + pTxEvent->RTR = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_RTR_MASK) >> MCAN_FRAME_RTR_POS; + + /* Retrieve ESI */ + pTxEvent->ESI = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_ESI_MASK) >> MCAN_FRAME_ESI_POS; + + /* Increment Tx event memory pointer to second word of Tx event FIFO element */ + u32TxEventAddr += 4UL; + + /* Retrieve DLC */ + pTxEvent->DLC = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_DLC_MASK) >> MCAN_FRAME_DLC_POS; + + /* Retrieve BRS */ + pTxEvent->BRS = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_BRS_MASK) >> MCAN_FRAME_BRS_POS; + + /* Retrieve FDF */ + pTxEvent->FDF = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_FDF_MASK) >> MCAN_FRAME_FDF_POS; + + /* Retrieve event type */ + pTxEvent->u32EventType = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_ET_MASK) >> MCAN_FRAME_ET_POS; + + /* Retrieve message marker */ + pTxEvent->u32MsgMarker = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_MM_L_MASK) >> MCAN_FRAME_MM_L_POS; + /* If 16-bit(wide) message marker used */ + if (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_WMM) != 0U) { + pTxEvent->u32MsgMarker |= READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_MM_H_MASK); + } else { + /* Retrieve Tx timestamp. It is invalid if 16-bit(wide) message marker used. */ + pTxEvent->u32TxTimestamp = READ_REG32_BIT(RW_MEM32(u32TxEventAddr), MCAN_FRAME_TS_MASK); + } + + /* Acknowledge the Tx event FIFO that the oldest element is + read so that it increments the get index. */ + WRITE_REG32(MCANx->TXEFA, u32GetIndex); + } + } + + return i32Ret; +} + +/** + * @brief Get high priority message status. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [out] pHpmStatus Pointer to a @ref stc_mcan_hpm_status_t structure which is used to save + * the status of the high priority message. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pHpmStatus == NULL. + */ +int32_t MCAN_GetHighPriorityMsgStatus(const CM_MCAN_TypeDef *MCANx, stc_mcan_hpm_status_t *pHpmStatus) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pHpmStatus != NULL) { + pHpmStatus->u8FilterListType = (uint8_t)(READ_REG32_BIT(MCANx->HPMS, MCAN_HPMS_FLST) >> MCAN_HPMS_FLST_POS); + pHpmStatus->u8FilterIndex = (uint8_t)(READ_REG32_BIT(MCANx->HPMS, MCAN_HPMS_FIDX) >> MCAN_HPMS_FIDX_POS); + pHpmStatus->u8MsgStorage = (uint8_t)(READ_REG32_BIT(MCANx->HPMS, MCAN_HPMS_MSI) >> MCAN_HPMS_MSI_POS); + pHpmStatus->u8MsgIndex = (uint8_t)READ_REG32_BIT(MCANx->HPMS, MCAN_HPMS_BIDX); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get protocol status. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [out] pProtocolStatus Pointer to a @ref stc_mcan_protocol_status_t structure which is used to save + * the protocol status. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pProtocolStatus == NULL. + */ +int32_t MCAN_GetProtocolStatus(const CM_MCAN_TypeDef *MCANx, stc_mcan_protocol_status_t *pProtocolStatus) +{ + uint32_t u32Status; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pProtocolStatus != NULL) { + /* Read the protocol status register */ + u32Status = READ_REG32(MCANx->PSR); + + /* Fill the protocol status structure */ + pProtocolStatus->u8LastErrorCode = (uint8_t)(u32Status & MCAN_PSR_LEC); + pProtocolStatus->u8DataLastErrorCode = (uint8_t)((u32Status & MCAN_PSR_DLEC) >> MCAN_PSR_DLEC_POS); + pProtocolStatus->u8ComState = (uint8_t)((u32Status & MCAN_PSR_ACT) >> MCAN_PSR_ACT_POS); + pProtocolStatus->u8ErrorPassiveFlag = (uint8_t)((u32Status & MCAN_PSR_EP) >> MCAN_PSR_EP_POS); + pProtocolStatus->u8WarningFlag = (uint8_t)((u32Status & MCAN_PSR_EW) >> MCAN_PSR_EW_POS); + pProtocolStatus->u8BusOffFlag = (uint8_t)((u32Status & MCAN_PSR_BO) >> MCAN_PSR_BO_POS); + pProtocolStatus->u8RxESIFlag = (uint8_t)((u32Status & MCAN_PSR_RESI) >> MCAN_PSR_RESI_POS); + pProtocolStatus->u8RxBRSFlag = (uint8_t)((u32Status & MCAN_PSR_RBRS) >> MCAN_PSR_RBRS_POS); + pProtocolStatus->u8RxFDFFlag = (uint8_t)((u32Status & MCAN_PSR_RFDF) >> MCAN_PSR_RFDF_POS); + pProtocolStatus->u8ProtocolExceptionFlag = (uint8_t)((u32Status & MCAN_PSR_PXE) >> MCAN_PSR_PXE_POS); + pProtocolStatus->u8TdcValue = (uint8_t)((u32Status & MCAN_PSR_TDCV) >> MCAN_PSR_TDCV_POS); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get the TDC value that used by CAN FD frame transmission. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint8_t value between 0~127. + */ +uint8_t MCAN_GetTdcValue(const CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + return (uint8_t)(READ_REG32_BIT(MCANx->PSR, MCAN_PSR_TDCV) >> MCAN_PSR_TDCV_POS); +} + +/** + * @brief Get the last error code of data phase(data bit time used). + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint8_t value of @ref MCAN_Protocol_Error_Code + */ +uint8_t MCAN_GetDataLastErrorCode(const CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + return (uint8_t)(READ_REG32_BIT(MCANx->PSR, MCAN_PSR_DLEC) >> MCAN_PSR_DLEC_POS); +} + +/** + * @brief Get the last error code of classical CAN frame or CAN FD frame arbitraion phase(nominal bit time used). + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint8_t value of @ref MCAN_Protocol_Error_Code + */ +uint8_t MCAN_GetLastErrorCode(const CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + return (uint8_t)READ_REG32_BIT(MCANx->PSR, MCAN_PSR_LEC); +} + +/** + * @brief Get the communication state. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint8_t value of @ref MCAN_Com_State + */ +uint8_t MCAN_GetComState(const CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + return (uint8_t)(READ_REG32_BIT(MCANx->PSR, MCAN_PSR_ACT) >> MCAN_PSR_ACT_POS); +} + +/** + * @brief Get the status of the specified protocol flag. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32PsFlag Protocol flag. + * This parameter can be any combination of @ref MCAN_Protocol_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t MCAN_GetProtocolFlagStatus(const CM_MCAN_TypeDef *MCANx, uint32_t u32PsFlag) +{ + en_flag_status_t enStatus = RESET; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_PS_FLAG(u32PsFlag)); + + if (READ_REG32_BIT(MCANx->PSR, u32PsFlag) != 0U) { + /* Return SET if one the specified flags is SET. */ + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Get error counter values. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [out] pErrorCounter Pointer to a @ref stc_mcan_error_counter_t structure which is used to save + * the error counter values. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pErrorCounter == NULL. + */ +int32_t MCAN_GetErrorCounter(const CM_MCAN_TypeDef *MCANx, stc_mcan_error_counter_t *pErrorCounter) +{ + uint32_t u32Counter; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (pErrorCounter != NULL) { + /* Read the error counters register */ + u32Counter = READ_REG32(MCANx->ECR); + + /* Fill the error counters structure */ + pErrorCounter->u8TxErrorCount = (uint8_t)(u32Counter & MCAN_ECR_TEC); + pErrorCounter->u8RxErrorCount = (uint8_t)((u32Counter & MCAN_ECR_REC) >> MCAN_ECR_REC_POS); + pErrorCounter->u8RxErrorPassive = (uint8_t)((u32Counter & MCAN_ECR_RP) >> MCAN_ECR_RP_POS); + pErrorCounter->u8ErrorLogging = (uint8_t)((u32Counter & MCAN_ECR_CEL) >> MCAN_ECR_CEL_POS); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get the status of the specified interrupt flag. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32Flag MCAN interrupt flag. + * This parameter can be any combination of @ref MCAN_Interrupt_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t MCAN_GetStatus(const CM_MCAN_TypeDef *MCANx, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_FLAG(u32Flag)); + + if (READ_REG32_BIT(MCANx->IR, u32Flag) != 0U) { + /* Return SET if one the specified flags is SET. */ + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the specified interrupt flag. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32Flag MCAN interrupt flag. + * This parameter can be any combination of @ref MCAN_Interrupt_Flag + * @retval None + */ +void MCAN_ClearStatus(CM_MCAN_TypeDef *MCANx, uint32_t u32Flag) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_FLAG(u32Flag)); + + WRITE_REG32(MCANx->IR, u32Flag); +} + +/** + * @brief Get the transmission occurred buffer list. + * Each Tx buffer has its own transmission occurred bit. The bits are set when the corresponding + * TXBRP bit is cleared after a successful transmission. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint32_t type value. + */ +uint32_t MCAN_GetTxOccurredList(const CM_MCAN_TypeDef *MCANx) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + return READ_REG32(MCANx->TXBTO); +} + +/** + * @brief Get the cancellation occurred buffer list. + * Each Tx buffer has its own cancellation finished bit. The bits are set when the corresponding + * TXBRP bit is cleared after a cancellation was requested via TXBCR. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint32_t type value. + */ +uint32_t MCAN_GetTxAbortedList(const CM_MCAN_TypeDef *MCANx) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + return READ_REG32(MCANx->TXBCF); +} + +/** + * @brief Check if the transmission of the specified Tx buffer has occurred. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32TxBuffer A Tx buffer. + * This parameter can be a value of @ref MCAN_Tx_Location + * @retval int32_t: + * - LL_OK: The transmission of the specified Tx buffer has occurred. + * - LL_ERR_BUSY: The transmission of the specified Tx buffer has not occurred. + */ +int32_t MCAN_CheckTxOccurred(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer) +{ + int32_t i32Ret = LL_ERR_BUSY; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_1TXBUF(u32TxBuffer)); + + if (READ_REG32_BIT(MCANx->TXBTO, u32TxBuffer) != 0U) { + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Check if the cancellation of the specified Tx buffer has occurred. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32TxBuffer A Tx buffer. + * This parameter can be a value of @ref MCAN_Tx_Location + * @retval int32_t: + * - LL_OK: The cancellation of the specified Tx buffer has occurred. + * - LL_ERR_BUSY: The cancellation of the specified Tx buffer has not occurred. + */ +int32_t MCAN_CheckTxAborted(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer) +{ + int32_t i32Ret = LL_ERR_BUSY; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_1TXBUF(u32TxBuffer)); + + if (READ_REG32_BIT(MCANx->TXBCF, u32TxBuffer) != 0U) { + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Check if a new message is received in the selected Rx buffer. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32RxBufferIndex Rx buffer index. + * This parameter must be a number between 0 and 63(MCAN_RX_BUF0~MCAN_RX_BUF63 of @ref MCAN_Rx_Location). + * @retval int32_t: + * - LL_OK: A new message is received in the selected Rx buffer. + * - LL_ERR_INVD_PARAM: u32RxBufferIndex is larger than the number of Rx buffer that allocated into the message RAM. + * - LL_ERR_BUF_EMPTY: The selected Rx buffer is empty. + */ +int32_t MCAN_CheckRxBufferMsgAvailable(CM_MCAN_TypeDef *MCANx, uint32_t u32RxBufferIndex) +{ + uint32_t u32RxBufferNum; + uint32_t u32RxBufferMask; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + u32RxBufferNum = MCAN_GetRxBufferNum(MCANx); + DDL_ASSERT(u32RxBufferIndex < u32RxBufferNum); + + if (u32RxBufferIndex < u32RxBufferNum) { + i32Ret = LL_ERR_BUF_EMPTY; + if (u32RxBufferIndex < 32U) { + u32RxBufferMask = 1UL << u32RxBufferIndex; + if (READ_REG32_BIT(MCANx->NDAT1, u32RxBufferMask) != 0U) { + WRITE_REG32(MCANx->NDAT1, u32RxBufferMask); + i32Ret = LL_OK; + } + } else { + u32RxBufferMask = 1UL << (u32RxBufferIndex & 0x1FUL); + if (READ_REG32_BIT(MCANx->NDAT2, u32RxBufferMask) != 0U) { + WRITE_REG32(MCANx->NDAT2, u32RxBufferMask); + i32Ret = LL_OK; + } + } + } + + return i32Ret; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx buffer. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32TxBuffer Tx buffer(s). + * This parameter can be any combination of @ref MCAN_Tx_Location + * @retval int32_t: + * - LL_OK: Pending transmission request on Tx buffer(s). + * - LL_ERR_BUF_EMPTY: No pending transmission request on Tx buffer(s). + */ +int32_t MCAN_CheckTxBufferPending(const CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer) +{ + int32_t i32Ret = LL_ERR_BUF_EMPTY; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + /* Check pending transmission request on the selected buffer */ + if (READ_REG32_BIT(MCANx->TXBRP, u32TxBuffer) != 0U) { + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get the fill level of the specified Rx FIFO. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32RxFifo Rx FIFO. + * This parameter can be one of the following values: + * @arg MCAN_RX_FIFO0: Rx FIFO0 + * @arg MCAN_RX_FIFO1: Rx FIFO1 + * @retval An uint32_t type value of the fill level. + */ +uint32_t MCAN_GetRxFifoFillLevel(const CM_MCAN_TypeDef *MCANx, uint32_t u32RxFifo) +{ + uint32_t u32FillLevel; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_RX_FIFO(u32RxFifo)); + + if (u32RxFifo == MCAN_RX_FIFO0) { + u32FillLevel = READ_REG32_BIT(MCANx->RXF0S, MCAN_RXF0S_F0FL); + } else { + u32FillLevel = READ_REG32_BIT(MCANx->RXF1S, MCAN_RXF1S_F1FL); + } + + return u32FillLevel; +} + +/** + * @brief Get the Tx FIFO free level(number of consecutive free Tx FIFO). + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval An uint32_t type value of the Tx FIFO free level. + */ +uint32_t MCAN_GetTxFifoFreeLevel(const CM_MCAN_TypeDef *MCANx) +{ + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + return READ_REG32_BIT(MCANx->TXFQS, MCAN_TXFQS_TFFL); +} + +/** + * @brief Check if the specified MCAN peripheral entered restricted operation mode. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval int32_t: + * - LL_OK: Restricted operation mode active. + * - LL_ERR: Normal operation mode. + */ +int32_t MCAN_CheckRestrictedOperationMode(const CM_MCAN_TypeDef *MCANx) +{ + int32_t i32Ret = LL_ERR; + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (READ_REG32_BIT(MCANx->CCCR, MCAN_CCCR_ASM) != 0U) { + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Exit restricted operation mode. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval None + */ +void MCAN_ExitRestrictedOperationMode(CM_MCAN_TypeDef *MCANx) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + /* Exit Restricted Operation mode */ + CLR_REG32_BIT(MCANx->CCCR, MCAN_CCCR_ASM); +} + +/** + * @brief Get the Tx Buffer number of message whose transmission was started last. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval uint8_t: + * - 0-31: Tx buffer number. + * - 0xFF: Value of TEST.TXBNS not valid. + */ +uint8_t MCAN_GetStartedTxBufferNum(const CM_MCAN_TypeDef *MCANx) +{ + uint8_t u8TxBufferNum = 0xFFU; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + if (READ_REG32_BIT(MCANx->TEST, MCAN_TEST_SVAL) != 0U) { + u8TxBufferNum = (uint8_t)(READ_REG32_BIT(MCANx->TEST, MCAN_TEST_TXBNS) >> MCAN_TEST_TXBNS_POS); + } + + return u8TxBufferNum; +} + +/** + * @brief Get the Tx Buffer number of message that is ready for transmission. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval uint8_t: + * - 0-31: Tx buffer number. + * - 0xFF: Value of TEST.TXBNP not valid. + */ +uint8_t MCAN_GetPreparedTxBufferNum(const CM_MCAN_TypeDef *MCANx) +{ + uint8_t u8TxBufferNum = 0xFFU; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + if (READ_REG32_BIT(MCANx->TEST, MCAN_TEST_PVAL) != 0U) { + u8TxBufferNum = (uint8_t)(READ_REG32_BIT(MCANx->TEST, MCAN_TEST_TXBNP) >> MCAN_TEST_TXBNP_POS); + } + + return u8TxBufferNum; +} + +/** + * @brief Get the logical state of the bus. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @retval uint8_t: + * - 0: The CAN bus is dominant. + * - 1: The CAN bus is recessive. + */ +uint8_t MCAN_GetBusLogicalState(const CM_MCAN_TypeDef *MCANx) +{ + uint8_t u8LogicalState = 0U; + + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + + if (READ_REG32_BIT(MCANx->TEST, MCAN_TEST_RX) != 0U) { + u8LogicalState = 1U; + } + + return u8LogicalState; +} + +/** + * @brief Control of transmit pin + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32PinCtrl Control of transmit pin + * This parameter can be one of the following values: + * @arg MCAN_TX_PIN_NORMAL: Tx pin controlled by the CAN Core, updated at the end of the CAN bit time + * @arg MCAN_TX_PIN_MONITOR: Sample Point can be monitored at Tx pin + * @arg MCAN_TX_PIN_DOMINANT: Dominant ('0') level at Tx pin + * @arg MCAN_TX_PIN_RECESSIVE: Recessive ('1') level at Tx pin + * @retval None + */ +void MCAN_TxPinControl(CM_MCAN_TypeDef *MCANx, uint32_t u32PinCtrl) +{ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_PIN_CTRL(u32PinCtrl)); + + MODIFY_REG32(MCANx->TEST, MCAN_TEST_TX, u32PinCtrl); +} + +/** + * @brief Enable or disable the specifed interrupt(s) of the MCAN. + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32IntType The MCAN interrupt(s). + * This parameter can be any combination of @ref MCAN_Interrupt + * @param [in] u32IntLine Interrupt line, indicates the specified interrupt(s) will be assigned to. + * This parameter can be a value of @ref MCAN_Interrupt_Line + * @arg MCAN_INT_LINE0: The specified interrupt(s) will be assigned to interrupt line 0 when enNewState is ENABLE. + * @arg MCAN_INT_LINE1: The specified interrupt(s) will be assigned to interrupt line 1 when enNewState is ENABLE. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable the specifed interrupt(s). + * @arg DISABLE: Disable the specifed interrupt(s). + * @retval None + */ +void MCAN_IntCmd(CM_MCAN_TypeDef *MCANx, uint32_t u32IntType, uint32_t u32IntLine, \ + en_functional_state_t enNewState) +{ + uint32_t u32ILS; + + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); + DDL_ASSERT(IS_MCAN_INT_TYPE(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + DDL_ASSERT(IS_MCAN_INT_LINE(u32IntLine)); + + SET_REG32_BIT(MCANx->IE, u32IntType); + if (u32IntLine == MCAN_INT_LINE0) { + CLR_REG32_BIT(MCANx->ILS, u32IntType); + /* Enable interrupt line 0 */ + SET_REG32_BIT(MCANx->ILE, MCAN_INT_LINE0); + } else { + SET_REG32_BIT(MCANx->ILS, u32IntType); + /* Enable interrupt line 1 */ + SET_REG32_BIT(MCANx->ILE, MCAN_INT_LINE1); + } + } else { + CLR_REG32_BIT(MCANx->IE, u32IntType); + u32ILS = MCANx->ILS; + if ((MCANx->IE | u32ILS) == u32ILS) { + /* Disable interrupt line 0 */ + CLR_REG32_BIT(MCANx->ILE, MCAN_INT_LINE0); + } + + if ((MCANx->IE & u32ILS) == 0U) { + /* Disable interrupt line 1 */ + CLR_REG32_BIT(MCANx->ILE, MCAN_INT_LINE1); + } + } +} + +/** + * @brief Enable or disable the specifed notification(s) of the specifed Tx buffer(s). + * @param [in] MCANx Pointer to MCAN instance register base. + * This parameter can be a value of the following: + * @arg CM_MCAN1: MCAN1 instance register base. + * @arg CM_MCAN2: MCAN2 instance register base. + * @param [in] u32TxBuffer Tx buffer(s). + * This parameter can be any combination of @ref MCAN_Tx_Location + * @param [in] u32Notification Notification(s) of Tx buffer. + * This parameter can be any combination of the following parameters: + * @arg MCAN_INT_TX_CPLT: Transmission completed interrupt. + * The Tx buffer can cause transmission completed completed interrupt + * only when its own transmission completed interrupt is enabled. + * @arg MCAN_INT_TX_ABORT_CPLT: Transmission cancellation finished interrupt. + * The Tx buffer can cause transmission cancellation finished interrupt + * only when its own transmission cancellation finished interrupt is enabled. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable the specifed interrupt(s). + * @arg DISABLE: Disable the specifed interrupt(s). + * @retval None + */ +void MCAN_TxBufferNotificationCmd(CM_MCAN_TypeDef *MCANx, uint32_t u32TxBuffer, \ + uint32_t u32Notification, en_functional_state_t enNewState) +{ +#ifdef __DEBUG + uint32_t u32TxBufferNum; +#endif + /* Check function parameters */ + DDL_ASSERT(IS_MCAN_UNIT(MCANx)); +#ifdef __DEBUG + u32TxBufferNum = MCAN_GET_TX_BUF_NUM(MCANx); + u32TxBufferNum += MCAN_GET_TX_FQ_NUM(MCANx); + if (u32TxBufferNum < MCAN_TX_ELMT_NUM_MAX) { + DDL_ASSERT(IS_MCAN_BIT_MASK(u32TxBuffer, (1UL << u32TxBufferNum) - 1U)); + } +#endif + DDL_ASSERT(IS_MCAN_TX_BUF_NOTICE(u32Notification)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + if ((u32Notification & MCAN_INT_TX_CPLT) != 0U) { + /* Enable Tx buffer transmission interrupt to set TC flag in IR register, + but interrupt will only occur if TC is enabled in IE register */ + SET_REG32_BIT(MCANx->TXBTIE, u32TxBuffer); + } + + if ((u32Notification & MCAN_INT_TX_ABORT_CPLT) != 0U) { + /* Enable Tx buffer cancellation finished interrupt to set TCF flag in IR register, + but interrupt will only occur if TCF is enabled in IE register */ + SET_REG32_BIT(MCANx->TXBCIE, u32TxBuffer); + } + } else { + if ((u32Notification & MCAN_INT_TX_CPLT) != 0U) { + /* Disable Tx buffer transmission interrupts */ + CLR_REG32_BIT(MCANx->TXBTIE, u32TxBuffer); + } + + if ((u32Notification & MCAN_INT_TX_ABORT_CPLT) != 0U) { + /* Disable Tx buffer cancellation finished interrupt */ + CLR_REG32_BIT(MCANx->TXBCIE, u32TxBuffer); + } + } +} + +/** + * @} + */ + +#endif /* LL_MCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c new file mode 100644 index 0000000000..679ea32100 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_mpu.c @@ -0,0 +1,1193 @@ +/** + ******************************************************************************* + * @file hc32_ll_mpu.c + * @brief This file provides firmware functions to manage the Memory Protection + * Unit(MPU). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Optimize MPU_ClearStatus function + 2023-12-15 CDT Add API MPU_UnitInit(), MPU_UnitStructInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_mpu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_MPU MPU + * @brief Memory Protection Unit Driver Library + * @{ + */ + +#if (LL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Local_Macros MPU Local Macros + * @{ + */ + +/* Number of MPU region */ +#define MPU_REGION_MAX_NUM (16UL) + +/* Number of MPU unit */ +#define MPU_UNIT_MAX_NUM (2UL) + +/* Number of SP unit */ +#define MPU_SP_UNIT_MAX_NUM (2UL) + +/* MPU Register Combination Mask */ +#define MPU_UNIT_CONFIG_MASK (MPU_SCR_SMPUBRP | MPU_SCR_SMPUBWP | MPU_SCR_SMPUACT) +/* DMA units have 16 regions */ +#define MPU_16REGION_UNIT (MPU_UNIT_DMA1 | MPU_UNIT_DMA2) + +/* Get the specified register address of the MPU Intrusion Control */ +#define MPU_RGD_ADDR(__NUM__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->RGD0)) + ((uint32_t)(__NUM__) << 2U)) +#define MPU_RGE_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGE)) + ((uint32_t)(__UNIT__) << 4U)) +#define MPU_RGWP_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGWP)) + ((uint32_t)(__UNIT__) << 4U)) +#define MPU_RGRP_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1RGRP)) + ((uint32_t)(__UNIT__) << 4U)) +#define MPU_CR_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->S1CR)) + ((uint32_t)(__UNIT__) << 4U)) + +/* Get the SP register address */ +#define MPU_SPPBA_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->MSPPBA)) + ((uint32_t)(__UNIT__) << 3U)) +#define MPU_SPPCTL_ADDR(__UNIT__) (__IO uint32_t *)((uint32_t)(&(CM_MPU->MSPPCTL)) + ((uint32_t)(__UNIT__) << 3U)) + +/** + * @defgroup MPU_Check_Parameters_Validity MPU Check Parameters Validity + * @{ + */ +#define IS_MPU_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_UNIT_ALL) == MPU_UNIT_ALL)) + +#define IS_MPU_INIT_UNIT(x) \ +( ((x) == MPU_UNIT_DMA1) || \ + ((x) == MPU_UNIT_DMA2)) + +#define IS_MPU_REGION(x) ((x) <= MPU_REGION_NUM15) + +#define IS_MPU_UNIT_REGION(unit, region) \ +( (((unit) | MPU_16REGION_UNIT) == MPU_16REGION_UNIT) || \ + ((region) <= MPU_REGION_NUM7)) + +#define IS_MPU_BACKGROUND_WR(x) \ +( ((x) == MPU_BACKGROUND_WR_DISABLE) || \ + ((x) == MPU_BACKGROUND_WR_ENABLE)) + +#define IS_MPU_BACKGROUND_RD(x) \ +( ((x) == MPU_BACKGROUND_RD_DISABLE) || \ + ((x) == MPU_BACKGROUND_RD_ENABLE)) + +#define IS_MPU_EXP_TYPE(x) \ +( ((x) == MPU_EXP_TYPE_NONE) || \ + ((x) == MPU_EXP_TYPE_BUS_ERR) || \ + ((x) == MPU_EXP_TYPE_NMI) || \ + ((x) == MPU_EXP_TYPE_RST)) + +#define IS_MPU_REGION_WR(x) \ +( ((x) == MPU_REGION_WR_DISABLE) || \ + ((x) == MPU_REGION_WR_ENABLE)) + +#define IS_MPU_REGION_RD(x) \ +( ((x) == MPU_REGION_RD_DISABLE) || \ + ((x) == MPU_REGION_RD_ENABLE)) + +#define IS_MPU_REGION_SIZE(x) \ +( ((x) >= MPU_REGION_SIZE_32BYTE) && \ + ((x) <= MPU_REGION_SIZE_4GBYTE)) + +#define IS_MPU_REGION_BASE_ADDER(addr, size) \ +( ((addr) & ((uint32_t)(~((uint64_t)0xFFFFFFFFUL << ((size) + 1U))))) == 0UL) + +#define IS_MPU_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_FLAG_ALL) == MPU_FLAG_ALL)) + +#define IS_MPU_IP_TYPE(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_IP_ALL) == MPU_IP_ALL)) + +#define IS_MPU_IP_EXP_TYPE(x) \ +( ((x) == MPU_IP_EXP_TYPE_NONE) || \ + ((x) == MPU_IP_EXP_TYPE_BUS_ERR)) + +#define IS_MPU_SP_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_SP_UNIT_ALL) == MPU_SP_UNIT_ALL)) + +#define IS_MPU_SP_EXP_TYPE(x) \ +( ((x) == MPU_SP_EXP_TYPE_NMI) || \ + ((x) == MPU_SP_EXP_TYPE_RST)) + +#define IS_MPU_SP_START_ADDR(x) \ +( ((x) | MPU_PSPPBA_PSPPBA) == MPU_PSPPBA_PSPPBA) + +#define IS_MPU_SP_ADDR_SIZE(x) \ +( ((x) >= 4UL) && ((x) <= 65536UL)) + +#define IS_MPU_UNLOCK() ((CM_MPU->WP & MPU_WP_MPUWE) == MPU_WP_MPUWE) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Functions MPU Global Functions + * @{ + */ + +/** + * @brief De-Initialize MPU. + * @param None + * @retval None + */ +void MPU_DeInit(void) +{ + uint32_t i; + __IO uint32_t *RGD; + __IO uint32_t *RGE; + __IO uint32_t *RGWP; + __IO uint32_t *RGRP; + __IO uint32_t *CR; + __IO uint32_t *SPPBA; + __IO uint32_t *SPPCTL; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + + for (i = 0UL; i < MPU_REGION_MAX_NUM; i++) { + RGD = MPU_RGD_ADDR(i); + WRITE_REG32(*RGD, 0UL); + } + WRITE_REG32(CM_MPU->ECLR, MPU_FLAG_ALL); + WRITE_REG32(CM_MPU->IPPR, 0UL); + for (i = 0UL; i < MPU_UNIT_MAX_NUM; i++) { + RGE = MPU_RGE_ADDR(i); + WRITE_REG32(*RGE, 0UL); + RGWP = MPU_RGWP_ADDR(i); + WRITE_REG32(*RGWP, 0UL); + RGRP = MPU_RGRP_ADDR(i); + WRITE_REG32(*RGRP, 0UL); + CR = MPU_CR_ADDR(i); + WRITE_REG32(*CR, 0UL); + } + for (i = 0UL; i < MPU_SP_UNIT_MAX_NUM; i++) { + SPPBA = MPU_SPPBA_ADDR(i); + WRITE_REG32(*SPPBA, 0UL); + SPPCTL = MPU_SPPCTL_ADDR(i); + WRITE_REG32(*SPPCTL, 0UL); + } +} + +/** + * @brief Initialize MPU. + * @param [in] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_Init(const stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma1.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma1.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma1.u32BackgroundRead)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma2.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BACKGROUND_WR(pstcMpuInit->stcDma2.u32BackgroundWrite)); + DDL_ASSERT(IS_MPU_BACKGROUND_RD(pstcMpuInit->stcDma2.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->S1CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma1.u32ExceptionType | pstcMpuInit->stcDma1.u32BackgroundWrite | + pstcMpuInit->stcDma1.u32BackgroundRead)); + MODIFY_REG32(CM_MPU->S2CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma2.u32ExceptionType | pstcMpuInit->stcDma2.u32BackgroundWrite | + pstcMpuInit->stcDma2.u32BackgroundRead)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_init_t member with default value. + * @param [out] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcMpuInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcMpuInit->stcDma1.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma1.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma1.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + pstcMpuInit->stcDma2.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma2.u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcMpuInit->stcDma2.u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Initialize MPU Unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] pstcUnitInit Pointer to a @ref stc_mpu_unit_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_UnitInit(uint32_t u32Unit, stc_mpu_unit_init_t *pstcUnitInit) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos; + int32_t i32Ret = LL_OK; + + if (NULL == pstcUnitInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_INIT_UNIT(u32Unit)); + + u32UnitPos = __CLZ(__RBIT(u32Unit)); + + CR = MPU_CR_ADDR(u32UnitPos); + WRITE_REG32(*CR, pstcUnitInit->u32MpuState | pstcUnitInit->u32ExceptionType | \ + pstcUnitInit->u32BackgroundWrite | pstcUnitInit->u32BackgroundRead); + } + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_unit_init_t member with default value. + * @param [out] pstcUnitInit Pointer to a @ref stc_mpu_unit_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_unit_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_UnitStructInit(stc_mpu_unit_init_t *pstcUnitInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcUnitInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcUnitInit->u32MpuState = MPU_UNIT_DISABLE; + pstcUnitInit->u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcUnitInit->u32BackgroundWrite = MPU_BACKGROUND_WR_DISABLE; + pstcUnitInit->u32BackgroundRead = MPU_BACKGROUND_RD_DISABLE; + } + return i32Ret; +} + +/** + * @brief Set the exception type of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] u32Type Exception type of MPU unit. + * This parameter can be one of the following values: + * @arg MPU_EXP_TYPE_NONE: The host unit access protection regions will be ignored + * @arg MPU_EXP_TYPE_BUS_ERR: The host unit access protection regions will be ignored and a bus error will be triggered + * @arg MPU_EXP_TYPE_NMI: The host unit access protection regions will be ignored and a NMI interrupt will be triggered + * @arg MPU_EXP_TYPE_RST: The host unit access protection regions will trigger the reset + * @retval None + */ +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32Type) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_EXP_TYPE(u32Type)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + MODIFY_REG32(*CR, MPU_SCR_SMPUACT, u32Type); + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the write of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundWriteCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*CR, MPU_SCR_SMPUBWP); + } else { + SET_REG32_BIT(*CR, MPU_SCR_SMPUBWP); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_BackgroundReadCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*CR, MPU_SCR_SMPUBRP); + } else { + SET_REG32_BIT(*CR, MPU_SCR_SMPUBRP); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + CR = MPU_CR_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + SET_REG32_BIT(*CR, MPU_SCR_SMPUE); + } else { + CLR_REG32_BIT(*CR, MPU_SCR_SMPUE); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Gets the status of MPU flag. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t MPU_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_MPU->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear the flag of MPU. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Flag + * @retval None + */ +void MPU_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + WRITE_REG32(CM_MPU->ECLR, u32Flag); +} + +/** + * @brief Initialize the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *RGD; + __IO uint32_t *RGWP; + __IO uint32_t *RGRP; + uint32_t i; + uint32_t u32UnitNum = MPU_UNIT_MAX_NUM; + stc_mpu_region_permission_t RegionBuffer[MPU_UNIT_MAX_NUM]; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(pstcRegionInit->u32BaseAddr, pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma1.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma1.u32RegionRead)); + DDL_ASSERT(IS_MPU_REGION_WR(pstcRegionInit->stcDma2.u32RegionWrite)); + DDL_ASSERT(IS_MPU_REGION_RD(pstcRegionInit->stcDma2.u32RegionRead)); + + RGD = MPU_RGD_ADDR(u32Num); + WRITE_REG32(*RGD, (pstcRegionInit->u32Size | pstcRegionInit->u32BaseAddr)); + /* Configure the read/write permission for the region */ + RegionBuffer[0] = pstcRegionInit->stcDma1; + RegionBuffer[1] = pstcRegionInit->stcDma2; + if ((u32Num >= MPU_REGION_NUM8) && (u32Num <= MPU_REGION_NUM15)) { + u32UnitNum = 2UL; + } + for (i = 0UL; i < u32UnitNum; i++) { + /* Configure the write permission for the region */ + RGWP = MPU_RGWP_ADDR(i); + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionWrite) { + CLR_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + /* Configure the read permission for the region */ + RGRP = MPU_RGRP_ADDR(i); + if (MPU_REGION_WR_DISABLE != RegionBuffer[i].u32RegionRead) { + CLR_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + } + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_region_init_t member with default value. + * @param [out] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_region_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRegionInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRegionInit->u32BaseAddr = 0UL; + pstcRegionInit->u32Size = MPU_REGION_SIZE_32BYTE; + pstcRegionInit->stcDma1.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma1.u32RegionRead = MPU_REGION_RD_DISABLE; + pstcRegionInit->stcDma2.u32RegionWrite = MPU_REGION_WR_DISABLE; + pstcRegionInit->stcDma2.u32RegionRead = MPU_REGION_RD_DISABLE; + } + + return i32Ret; +} + +/** + * @brief Set the base address of the region. + * @note The effective bits of the 'u32Addr' are related to the 'size' of the region, + * and the low 'size+1' bits are fixed at 0. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Addr The base address of the region. + * @retval None + */ +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + + RGD = MPU_RGD_ADDR(u32Num); + /* Check parameters */ + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(u32Addr, READ_REG32_BIT(*RGD, MPU_RGD_MPURGSIZE))); + + MODIFY_REG32(*RGD, MPU_RGD_MPURGADDR, u32Addr); +} + +/** + * @brief Set the size of the region. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Size The size of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_SIZE_32BYTE: 32 Byte + * @arg MPU_REGION_SIZE_64BYTE: 64 Byte + * @arg MPU_REGION_SIZE_128BYTE: 126 Byte + * @arg MPU_REGION_SIZE_256BYTE: 256 Byte + * @arg MPU_REGION_SIZE_512BYTE: 512 Byte + * @arg MPU_REGION_SIZE_1KBYTE: 1K Byte + * @arg MPU_REGION_SIZE_2KBYTE: 2K Byte + * @arg MPU_REGION_SIZE_4KBYTE: 4K Byte + * @arg MPU_REGION_SIZE_8KBYTE: 8K Byte + * @arg MPU_REGION_SIZE_16KBYTE: 16K Byte + * @arg MPU_REGION_SIZE_32KBYTE: 32K Byte + * @arg MPU_REGION_SIZE_64KBYTE: 64K Byte + * @arg MPU_REGION_SIZE_128KBYTE: 128K Byte + * @arg MPU_REGION_SIZE_256KBYTE: 256K Byte + * @arg MPU_REGION_SIZE_512KBYTE: 512K Byte + * @arg MPU_REGION_SIZE_1MBYTE: 1M Byte + * @arg MPU_REGION_SIZE_2MBYTE: 2M Byte + * @arg MPU_REGION_SIZE_4MBYTE: 4M Byte + * @arg MPU_REGION_SIZE_8MBYTE: 8M Byte + * @arg MPU_REGION_SIZE_16MBYTE: 16M Byte + * @arg MPU_REGION_SIZE_32MBYTE: 32M Byte + * @arg MPU_REGION_SIZE_64MBYTE: 64M Byte + * @arg MPU_REGION_SIZE_128MBYTE: 128M Byte + * @arg MPU_REGION_SIZE_256MBYTE: 256M Byte + * @arg MPU_REGION_SIZE_512MBYTE: 512M Byte + * @arg MPU_REGION_SIZE_1GBYTE: 1G Byte + * @arg MPU_REGION_SIZE_2GBYTE: 2G Byte + * @arg MPU_REGION_SIZE_4GBYTE: 4G Byte + * @retval None + */ +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(u32Size)); + + RGD = MPU_RGD_ADDR(u32Num); + MODIFY_REG32(*RGD, MPU_RGD_MPURGSIZE, u32Size); +} + +/** + * @brief Enable or disable the write of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionWriteCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGWP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + /* Configure the write permission for the region */ + RGWP = MPU_RGWP_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the read of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionReadCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGRP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + /* Configure the read permission for the region */ + RGRP = MPU_RGRP_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + CLR_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } else { + SET_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGE; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + RGE = MPU_RGE_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + SET_REG32_BIT(*RGE, (0x1UL << u32Num)); + } else { + CLR_REG32_BIT(*RGE, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Initialize the SP unit of MPU. + * @param [in] u32Unit The type of MPU SP unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_SP_Unit_Type + * @param [in] pstcSpInit Pointer to a @ref stc_mpu_sp_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_SPInit(uint32_t u32Unit, const stc_mpu_sp_init_t *pstcSpInit) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t *SPPBA; + __IO uint32_t *SPPCTL; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + if (NULL == pstcSpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_SP_EXP_TYPE(pstcSpInit->u32ExceptionType)); + DDL_ASSERT(IS_MPU_SP_START_ADDR(pstcSpInit->u32Addr)); + DDL_ASSERT(IS_MPU_SP_ADDR_SIZE(pstcSpInit->u32Size)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(pstcSpInit->u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(pstcSpInit->u32Size)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + SPPBA = MPU_SPPBA_ADDR(u32UnitPos); + WRITE_REG32(*SPPBA, pstcSpInit->u32Addr & MPU_PSPPBA_PSPPBA); + SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos); + MODIFY_REG32(*SPPCTL, (MPU_MSPPCTL_MSPPACT | MPU_MSPPCTL_MSPPSIZE), + (pstcSpInit->u32ExceptionType | (pstcSpInit->u32Size - 1U))); + } + u32Temp >>= 1UL; + u32UnitPos++; + } + } + + return i32Ret; +} + +/** + * @brief Fills each stc_mpu_sp_init_t member with default value. + * @param [out] pstcSpInit Pointer to a @ref stc_mpu_sp_init_t structure + * @retval int32_t: + * - LL_OK: stc_mpu_sp_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t MPU_SPStructInit(stc_mpu_sp_init_t *pstcSpInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcSpInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcSpInit->u32ExceptionType = MPU_SP_EXP_TYPE_NMI; + pstcSpInit->u32Addr = 0UL; + pstcSpInit->u32Size = 0x04UL; + } + + return i32Ret; +} + +/** + * @brief Set the start address of the SP. + * @param [in] u32Unit The type of MPU SP unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_SP_Unit_Type + * @param [in] u32Addr The start address of the SP. + This parameter can be a number between 0UL and 0xFFFFFFFCUL. + * @retval None + */ +void MPU_SetSPStartAddr(uint32_t u32Unit, uint32_t u32Addr) +{ + __IO uint32_t *SPPBA; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_SP_START_ADDR(u32Addr)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Addr)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + SPPBA = MPU_SPPBA_ADDR(u32UnitPos); + WRITE_REG32(*SPPBA, u32Addr & MPU_PSPPBA_PSPPBA); + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Set the address size of the SP. + * @param [in] u32Unit The type of MPU SP unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_SP_Unit_Type + * @param [in] u32Size The size of the SP. + * This parameter can be a number between 4UL and 65536UL. + * @retval None + */ +void MPU_SetSPSize(uint32_t u32Unit, uint32_t u32Size) +{ + __IO uint32_t *SPPCTL; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_SP_ADDR_SIZE(u32Size)); + DDL_ASSERT(IS_ADDR_ALIGN_WORD(u32Size)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos); + MODIFY_REG32(*SPPCTL, MPU_MSPPCTL_MSPPSIZE, (u32Size - 1U)); + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Set the exception type of the SP. + * @param [in] u32Unit The type of MPU SP unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_SP_Unit_Type + * @param [in] u32Type Exception type of MPU SP unit. + * This parameter can be one of the following values: + * @arg MPU_SP_EXP_TYPE_NMI: The SP access outside specified range will trigger a NMI interrupt. + * @arg MPU_SP_EXP_TYPE_RST: The SP access outside specified range will trigger a reset. + * @retval None + */ +void MPU_SetSPExceptionType(uint32_t u32Unit, uint32_t u32Type) +{ + __IO uint32_t *SPPCTL; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_SP_EXP_TYPE(u32Type)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos); + MODIFY_REG32(*SPPCTL, MPU_MSPPCTL_MSPPACT, u32Type); + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Enable or disable the access control of the unit for the SP. + * @param [in] u32Unit The type of MPU SP unit. + * This parameter can be one or any combination of the following values: + * @arg @ref MPU_SP_Unit_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_SPCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *SPPCTL; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_SP_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) { + if (0UL != (u32Temp & 0x1UL)) { + SPPCTL = MPU_SPPCTL_ADDR(u32UnitPos); + if (DISABLE != enNewState) { + SET_REG32_BIT(*SPPCTL, MPU_MSPPCTL_MSPPE); + } else { + CLR_REG32_BIT(*SPPCTL, MPU_MSPPCTL_MSPPE); + } + + } + u32Temp >>= 1UL; + u32UnitPos++; + } +} + +/** + * @brief Set the type of exception to access the protected IP. + * @param [in] u32Type Exception type of MPU IP. + * This parameter can be one of the following values: + * @arg MPU_IP_EXP_TYPE_NONE: Access to the protected IP will be ignored + * @arg MPU_IP_EXP_TYPE_BUS_ERR: Access to the protected IP will trigger a bus error + * @retval None + */ +void MPU_IP_SetExceptionType(uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_EXP_TYPE(u32Type)); + + WRITE_REG32(bCM_MPU->IPPR_b.BUSERRE, (u32Type >> MPU_IPPR_BUSERRE_POS)); +} + +/** + * @brief Enable or disable write for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_WriteCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } else { + SET_REG32_BIT(CM_MPU->IPPR, (u32Periph << 1U)); + } +} + +/** + * @brief Enable or disable read for the IP. + * @param [in] u32Periph The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_EFM: EFM module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_MPU: MPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_RMU_CMU_PWC: RMU, CMU and PWC modules + * @arg MPU_IP_FCG: PWR_FCG0/1/2/3 and PWR_FCG0PC registers + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void MPU_IP_ReadCmd(uint32_t u32Periph, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + CLR_REG32_BIT(CM_MPU->IPPR, u32Periph); + } else { + SET_REG32_BIT(CM_MPU->IPPR, u32Periph); + } +} + +/** + * @} + */ + +#endif /* LL_MPU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c new file mode 100644 index 0000000000..302294744f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_pwc.c @@ -0,0 +1,1257 @@ +/** + ******************************************************************************* + * @file hc32_ll_pwc.c + * @brief This file provides firmware functions to manage the Power Control(PWC). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Remove redundant assert + Modify API PWC_PD_Enter() #use assert to replace the unlock, and add return value + Modify API PWC_WKT_SetCompareValue() + Refine PWC_SLEEP_Enter() + Add API PWC_PD_SetIoState() & PWC_PD_SetMode() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_pwc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_PWC PWC + * @brief Power Control Driver Library + * @{ + */ + +#if (LL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Macros PWC Local Macros + * @{ + */ + +/* Get the backup register address of PWC */ + +#define PWC_MD_SWITCH_TIMEOUT (30UL) +#define PWC_MD_SWITCH_TIMEOUT2 (0x1000UL) + +#define PWC_LVD_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EN_BIT (PWC_PVDCR0_PVD1EN) +#define PWC_LVD_EXT_INPUT_EN_REG (CM_PWC->PVDCR0) +#define PWC_LVD_EXT_INPUT_EN_BIT (PWC_PVDCR0_EXVCCINEN) +#define PWC_LVD_CMP_OUTPUT_EN_REG (CM_PWC->PVDCR1) +#define PWC_LVD_CMP_OUTPUT_EN_BIT (PWC_PVDCR1_PVD1CMPOE) +#define PWC_LVD_FILTER_EN_REG (CM_PWC->PVDFCR) +#define PWC_LVD_FILTER_EN_BIT (PWC_PVDFCR_PVD1NFDIS) +#define PWC_LVD_STATUS_REG (CM_PWC->PVDDSR) + +#define PWC_LVD2_POS (4U) +#define PWC_LVD_BIT_OFFSET(x) ((uint8_t)((x) * PWC_LVD2_POS)) +#define PWC_LVD_EN_BIT_OFFSET(x) (x) + +#define PWC_RAM_MASK (PWC_RAMPC0_RAMPDC0 | PWC_RAMPC0_RAMPDC10) + +#define PWC_PRAM_MASK (PWC_RAM_PD_MCAN | PWC_RAM_PD_CACHE ) + +#define PWC_LVD_FLAG_MASK (PWC_LVD1_FLAG_MON | PWC_LVD1_FLAG_DETECT | \ + PWC_LVD2_FLAG_MON | PWC_LVD2_FLAG_DETECT) + +#define PWC_LVD_EXP_NMI_POS (8U) + +/** + * @defgroup PWC_Check_Parameters_Validity PWC Check Parameters Validity + * @{ + */ + +/* Check PWC register lock status. */ +#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) +/* Check PWC LVD register lock status. */ +#define IS_PWC_LVD_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB3) == PWC_FPRC_FPRCB3) +/* Parameter validity check for EFM lock status. */ +#define IS_PWC_EFM_UNLOCKED() (CM_EFM->FAPRT == 0x00000001UL) + +/* Parameter validity check for stop type */ +#define IS_PWC_STOP_TYPE(x) \ +( ((x) == PWC_STOP_WFI) || \ + ((x) == PWC_STOP_WFE_INT) || \ + ((x) == PWC_STOP_WFE_EVT)) + +/* Parameter validity check for sleep type */ +#define IS_PWC_SLEEP_TYPE(x) \ +( ((x) == PWC_SLEEP_WFI) || \ + ((x) == PWC_SLEEP_WFE_INT) || \ + ((x) == PWC_SLEEP_WFE_EVT)) + +/* Parameter validity check for internal RAM setting of power mode control */ +#define IS_PWC_RAM_CONTROL(x) \ +( ((x) != 0x00UL) && \ + (((x) | PWC_RAM_MASK) == PWC_RAM_MASK)) + +/* Parameter validity check for peripheral RAM setting of power mode control */ +#define IS_PWC_PRAM_CONTROL(x) \ +( ((x) != 0x00UL) && \ + (((x) | PWC_PRAM_MASK) == PWC_PRAM_MASK)) + +/* Parameter validity check for RAM setting of MCU operating mode */ +#define IS_PWC_RAM_MD(x) \ +( ((x) == PWC_RAM_HIGH_SPEED) || \ + ((x) == PWC_RAM_ULOW_SPEED)) + +/* Parameter validity check for LVD channel. */ +#define IS_PWC_LVD_CH(x) \ +( ((x) == PWC_LVD_CH1) || \ + ((x) == PWC_LVD_CH2)) + +/* Parameter validity check for LVD function setting. */ +#define IS_PWC_LVD_EN(x) \ +( ((x) == PWC_LVD_ON) || \ + ((x) == PWC_LVD_OFF)) + +/* Parameter validity check for LVD compare output setting. */ +#define IS_PWC_LVD_CMP_EN(x) \ +( ((x) == PWC_LVD_CMP_ON) || \ + ((x) == PWC_LVD_CMP_OFF)) + +/* Parameter validity check for PWC LVD exception type. */ +#define IS_PWC_LVD_EXP_TYPE(x) \ +( ((x) == PWC_LVD_EXP_TYPE_NONE) || \ + ((x) == PWC_LVD_EXP_TYPE_NMI) || \ + ((x) == PWC_LVD_EXP_TYPE_RST)) + +/* Parameter validity check for LVD digital noise filter function setting. */ +#define IS_PWC_LVD_FILTER_EN(x) \ +( ((x) == PWC_LVD_FILTER_ON) || \ + ((x) == PWC_LVD_FILTER_OFF)) + +/* Parameter validity check for LVD digital noise filter clock setting. */ +#define IS_PWC_LVD_FILTER_CLK(x) \ +( ((x) == PWC_LVD_FILTER_LRC_DIV1) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV2) || \ + ((x) == PWC_LVD_FILTER_LRC_DIV4) || \ + ((x) == PWC_LVD_FILTER_LRC_MUL2)) + +/* Parameter validity check for LVD detect voltage setting. */ +#define IS_PWC_LVD_THRESHOLD_VOLTAGE(x) \ +( ((x) == PWC_LVD_THRESHOLD_LVL0) || \ + ((x) == PWC_LVD_THRESHOLD_LVL1) || \ + ((x) == PWC_LVD_THRESHOLD_LVL2) || \ + ((x) == PWC_LVD_THRESHOLD_LVL3) || \ + ((x) == PWC_LVD_THRESHOLD_LVL4) || \ + ((x) == PWC_LVD_THRESHOLD_LVL5) || \ + ((x) == PWC_LVD_THRESHOLD_LVL6) || \ + ((x) == PWC_LVD_THRESHOLD_LVL7)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_TRIG_EDGE(x) \ +( ((x) == PWC_LVD_TRIG_FALLING) || \ + ((x) == PWC_LVD_TRIG_RISING) || \ + ((x) == PWC_LVD_TRIG_BOTH)) + +/* Parameter validity check for LVD trigger setting. */ +#define IS_PWC_LVD_CLR_FLAG(x) \ +( ((x) == PWC_LVD1_FLAG_DETECT) || \ + ((x) == PWC_LVD2_FLAG_DETECT)) + +/* Parameter validity check for LVD flag. */ +#define IS_PWC_LVD_GET_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LVD_FLAG_MASK) == PWC_LVD_FLAG_MASK)) + +/* Parameter validity check for power down mode. */ +#define IS_PWC_PD_MD(x) \ +( ((x) == PWC_PD_MD1) || \ + ((x) == PWC_PD_MD2) || \ + ((x) == PWC_PD_MD3) || \ + ((x) == PWC_PD_MD4)) + +/* Parameter validity check for IO state while power down mode. */ +#define IS_PWC_PD_IO_STATE(x) \ +( ((x) == PWC_PD_IO_KEEP1) || \ + ((x) == PWC_PD_IO_KEEP2) || \ + ((x) == PWC_PD_IO_HIZ)) + +/* Parameter validity check for power down mode wake up event with trigger. */ +#define IS_PWC_WAKEUP_TRIG_EVT(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_TRIG_ALL) == PWC_PD_WKUP_TRIG_ALL)) + +/* Parameter validity check for power down mode wake up trigger edge. */ +#define IS_PWC_WAKEUP_TRIG(x) \ +( ((x) == PWC_PD_WKUP_TRIG_FALLING) || \ + ((x) == PWC_PD_WKUP_TRIG_RISING)) + +/* Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP_FLAG(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_PD_WKUP_FLAG_ALL) == PWC_PD_WKUP_FLAG_ALL)) + +/* Parameter validity check for stop mode drive capacity. */ +#define IS_PWC_STOP_DRV(drv) \ +( ((drv) == PWC_STOP_DRV_HIGH) || \ + ((drv) == PWC_STOP_DRV_LOW)) + +/* Parameter validity check for vcap selection while power down mode. */ +#define IS_PWC_PD_VCAP_SEL(x) \ +( ((x) == PWC_PD_VCAP_0P1UF) || \ + ((x) == PWC_PD_VCAP_0P047UF)) + +/* Parameter validity check for clock setting after wake-up from stop mode. */ +#define IS_PWC_STOP_CLK(x) \ +( ((x) == PWC_STOP_CLK_KEEP) || \ + ((x) == PWC_STOP_CLK_MRC)) + +/* Parameter validity check for flash wait setting after wake-up from stop mode. */ +#define IS_PWC_STOP_FLASH_WAIT(x) \ +( ((x)== PWC_STOP_FLASH_WAIT_ON) || \ + ((x)== PWC_STOP_FLASH_WAIT_OFF)) + +/* Parameter validity check for ex-bus setting in stop mode. */ +#define IS_PWC_STOP_EXBUS(x) \ +( ((x)== PWC_STOP_EXBUS_HIZ) || \ + ((x)== PWC_STOP_EXBUS_HOLD)) + +#define IS_PWC_LDO_SEL(x) \ +( ((x) != 0x00U) && \ + (((x) | PWC_LDO_MASK) == PWC_LDO_MASK)) + +/* Parameter validity check for WKT Clock Source. */ +#define IS_PWC_WKT_CLK_SRC(x) \ +( ((x)== PWC_WKT_CLK_SRC_64HZ) || \ + ((x)== PWC_WKT_CLK_SRC_XTAL32) || \ + ((x)== PWC_WKT_CLK_SRC_LRC)) + +/* Parameter validity check for WKT Comparision Value. */ +#define IS_PWC_WKT_COMPARISION_VALUE(x) ((x) <= 0x0FFFU) + +/* Parameter validity check for RTC clock selection. */ +#define IS_PWC_RTC_CLK_SEL(x) \ +( ((x) == PWC_RTC_CLK_LRC) || \ + ((x) == PWC_RTC_CLK_XTAL_DIV)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup PWC_Global_Functions PWC Global Functions + * @{ + */ + +/** + * @brief Enter power down mode. + * @param None + * @retval int32_t: + * - LL_ERR_TIMEOUT: Enter PD mode timeout + * @note Not return LL_OK because if enter PD mode ok, the MCU will shut down, and reset after woken-up. + */ +int32_t PWC_PD_Enter(void) +{ + int32_t i32Ret; + uint32_t u32Timeout = 0UL; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + /* Ensure pvd not reset exception */ + CLR_REG8_BIT(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD2IRS); + for (; ;) { + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + SET_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + __WFI(); + u32Timeout++; + if (u32Timeout > 1000UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Enter stop mode. + * @param [in] u8StopType specifies the type of enter stop's command. + * @arg PWC_STOP_WFI Enter stop mode by WFI, and wake-up by interrupt handle. + * @arg PWC_STOP_WFE_INT Enter stop mode by WFE, and wake-up by interrupt request. + * @arg PWC_STOP_WFE_EVT Enter stop mode by WFE, and wake-up by event. + * @retval None + */ +void PWC_STOP_Enter(uint8_t u8StopType) +{ + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_STOP_TYPE(u8StopType)); + DDL_ASSERT(0U == (CM_PWC->PWRC0 & PWC_PWRC0_PDMDS)); + + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + if (PWC_STOP_WFI == u8StopType) { + __WFI(); + } else { + if (PWC_STOP_WFE_INT == u8StopType) { + SET_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); + } + __SEV(); + __WFE(); + __WFE(); + } + +} + +/** + * @brief Enter sleep mode. + * @param [in] u8SleepType specifies the type of enter sleep's command. + * @arg PWC_SLEEP_WFI Enter sleep mode by WFI, and wake-up by interrupt handle. + * @arg PWC_SLEEP_WFE_INT Enter sleep mode by WFE, and wake-up by interrupt request. + * @arg PWC_SLEEP_WFE_EVT Enter sleep mode by WFE, and wake-up by event. + + * @retval None + */ +void PWC_SLEEP_Enter(uint8_t u8SleepType) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_SLEEP_TYPE(u8SleepType)); + + CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_STOP); + CLR_REG8_BIT(CM_PWC->PWRC0, PWC_PWRC0_PWDN); + + if (PWC_SLEEP_WFI == u8SleepType) { + __WFI(); + } else { + if (PWC_SLEEP_WFE_INT == u8SleepType) { + SET_REG32_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); + } + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Configure ram run mode. + * @param [in] u16Mode Specifies the mode to run. + * @arg PWC_RAM_HIGH_SPEED + * @arg PWC_RAM_ULOW_SPEED + * @retval None + */ +void PWC_RamModeConfig(uint16_t u16Mode) +{ + DDL_ASSERT(IS_PWC_RAM_MD(u16Mode)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG16(CM_PWC->RAMOPM, u16Mode); +} + +/** + * @brief Initialize LVD config structure. Fill each pstcLvdInit with default value + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_StructInit(stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* RESET LVD init structure parameters values */ + pstcLvdInit->u32State = PWC_LVD_OFF; + pstcLvdInit->u32CompareOutputState = PWC_LVD_CMP_OFF; + pstcLvdInit->u32ExceptionType = PWC_LVD_EXP_TYPE_NONE; + pstcLvdInit->u32Filter = PWC_LVD_FILTER_OFF; + pstcLvdInit->u32FilterClock = PWC_LVD_FILTER_LRC_MUL2; + pstcLvdInit->u32ThresholdVoltage = PWC_LVD_THRESHOLD_LVL0; + pstcLvdInit->u32TriggerEdge = PWC_LVD_TRIG_FALLING; + } + return i32Ret; +} + +/** + * @brief LVD configuration. + * @param [in] u8Ch LVD channel @ref PWC_LVD_Channel. + * @param [in] pstcLvdInit Pointer to a stc_pwc_lvd_init_t structure that contains configuration information. + * @retval int32_t: + * - LL_OK: LVD initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_LVD_Init(uint8_t u8Ch, const stc_pwc_lvd_init_t *pstcLvdInit) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcLvdInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_EN(pstcLvdInit->u32State)); + DDL_ASSERT(IS_PWC_LVD_EXP_TYPE(pstcLvdInit->u32ExceptionType)); + DDL_ASSERT(IS_PWC_LVD_CMP_EN(pstcLvdInit->u32CompareOutputState)); + DDL_ASSERT(IS_PWC_LVD_FILTER_EN(pstcLvdInit->u32Filter)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(pstcLvdInit->u32FilterClock)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(pstcLvdInit->u32ThresholdVoltage)); + DDL_ASSERT(IS_PWC_LVD_TRIG_EDGE(pstcLvdInit->u32TriggerEdge)); + + /* disable filter function in advance */ + SET_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS << PWC_LVD_BIT_OFFSET(u8Ch))); + MODIFY_REG8(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32Filter | pstcLvdInit->u32FilterClock) << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Config LVD threshold voltage */ + MODIFY_REG8(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32ThresholdVoltage << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Enable LVD */ + MODIFY_REG8(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch, pstcLvdInit->u32State << u8Ch); + /* Enable compare output */ + MODIFY_REG8(CM_PWC->PVDCR1, PWC_PVDCR1_PVD1CMPOE << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32CompareOutputState << PWC_LVD_BIT_OFFSET(u8Ch)); + MODIFY_REG8(CM_PWC->PVDICR, PWC_PVDICR_PVD1EDGS << PWC_LVD_BIT_OFFSET(u8Ch), \ + pstcLvdInit->u32TriggerEdge << PWC_LVD_BIT_OFFSET(u8Ch)); + /* config PVDIRE & PWC_PVDCR1_PVD1IRS while PVDEN & PVDCMPOE enable */ + MODIFY_REG8(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) << PWC_LVD_BIT_OFFSET(u8Ch), \ + (pstcLvdInit->u32ExceptionType & 0xFFU) << PWC_LVD_BIT_OFFSET(u8Ch)); + + } + return i32Ret; +} + +/** + * @brief De-initialize PWC LVD. + * @param [in] u8Ch LVD channel @ref PWC_LVD_Channel. + * @retval None + */ +void PWC_LVD_DeInit(uint8_t u8Ch) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + /* Disable LVD */ + CLR_REG_BIT(CM_PWC->PVDCR0, PWC_PVDCR0_PVD1EN << u8Ch); + /* Disable Ext-Vcc */ + if (PWC_LVD_CH2 == u8Ch) { + CLR_REG8_BIT(CM_PWC->PVDCR0, PWC_PVDCR0_EXVCCINEN); + } else { + /* rsvd */ + } + /* Reset filter */ + CLR_REG8_BIT(CM_PWC->PVDFCR, (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Reset configure */ + CLR_REG8_BIT(CM_PWC->PVDCR1, (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS | PWC_PVDCR1_PVD1CMPOE) << \ + PWC_LVD_BIT_OFFSET(u8Ch)); + CLR_REG8_BIT(CM_PWC->PVDICR, PWC_PVDICR_PVD1EDGS << PWC_LVD_BIT_OFFSET(u8Ch)); + /* Reset threshold voltage */ + CLR_REG8_BIT(CM_PWC->PVDLCR, PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Enable or disable LVD. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_Cmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_EN_REG, PWC_LVD_EN_BIT << PWC_LVD_EN_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD external input. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_ExtInputCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } else { + CLR_REG_BIT(PWC_LVD_EXT_INPUT_EN_REG, PWC_LVD_EXT_INPUT_EN_BIT); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_CompareOutputCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + CLR_REG_BIT(PWC_LVD_CMP_OUTPUT_EN_REG, PWC_LVD_CMP_OUTPUT_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD digital filter. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LVD_DigitalFilterCmd(uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } else { + SET_REG_BIT(PWC_LVD_FILTER_EN_REG, PWC_LVD_FILTER_EN_BIT << PWC_LVD_BIT_OFFSET(u8Ch)); + } +} + +/** + * @brief Enable or disable LVD compare output. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] u32Clock Specifies filter clock. @ref PWC_LVD_DFS_Clk_Sel + * @retval None + */ +void PWC_LVD_SetFilterClock(uint8_t u8Ch, uint32_t u32Clock) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_FILTER_CLK(u32Clock)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + MODIFY_REG8(CM_PWC->PVDFCR, PWC_PVDFCR_PVD1NFCKS << PWC_LVD_BIT_OFFSET(u8Ch), \ + u32Clock << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Set LVD threshold voltage. + * @param [in] u8Ch Specifies which channel to operate. @ref PWC_LVD_Channel. + * @param [in] u32Voltage Specifies threshold voltage. @ref PWC_LVD_Detection_Voltage_Sel + * @retval None + */ +void PWC_LVD_SetThresholdVoltage(uint8_t u8Ch, uint32_t u32Voltage) +{ + DDL_ASSERT(IS_PWC_LVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_LVD_THRESHOLD_VOLTAGE(u32Voltage)); + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PVDLCR, (PWC_PVDLCR_PVD1LVL << PWC_LVD_BIT_OFFSET(u8Ch)), \ + u32Voltage << PWC_LVD_BIT_OFFSET(u8Ch)); +} + +/** + * @brief Get LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @retval An @ref en_flag_status_t enumeration value + * @note PVDxDETFLG is available when PVDCR0.PVDxEN and PVDCR1.PVDxCMPOE are set to '1' + */ +en_flag_status_t PWC_LVD_GetStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_GET_FLAG(u8Flag)); + return ((0x00U != READ_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag)) ? SET : RESET); +} + +/** + * @brief Clear LVD flag. + * @param [in] u8Flag LVD flag to be get @ref PWC_LVD_Flag + * @arg PWC_LVD1_FLAG_DETECT + * @arg PWC_LVD2_FLAG_DETECT + * @retval None + */ +void PWC_LVD_ClearStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_LVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_LVD_CLR_FLAG(u8Flag)); + + CLR_REG8_BIT(PWC_LVD_STATUS_REG, u8Flag); +} + +/** + * @brief LDO(HRC & PLL) command. + * @param [in] u16Ldo Specifies the ldo to command. + * @arg PWC_LDO_PLL + * @arg PWC_LDO_HRC + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_LDO_Cmd(uint16_t u16Ldo, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_LDO_SEL(u16Ldo)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } else { + SET_REG8_BIT(CM_PWC->PWRC1, u16Ldo); + } +} + +/** + * @brief Switch high speed to ultra low speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background. + */ +int32_t PWC_HighSpeedToLowSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + + while (PWC_RAM_ULOW_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_ULOW_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL == READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, ENABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + CLR_REG8_BIT(CM_PWC->PWRC3, PWC_PWRC3_DDAS); + MODIFY_REG8(CM_PWC->PWRC2, PWC_PWRC2_DVS, PWC_PWRC2_DVS_1); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + return LL_OK; +} + +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval int32_t: + * - LL_OK: Mode switch successful. + * - LL_ERR: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +int32_t PWC_LowSpeedToHighSpeed(void) +{ + uint32_t u32To = PWC_MD_SWITCH_TIMEOUT2; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_EFM_UNLOCKED()); + SET_REG8_BIT(CM_PWC->PWRC3, PWC_PWRC3_DDAS); + SET_REG8_BIT(CM_PWC->PWRC2, PWC_PWRC2_DVS); + + /* Delay 30uS*/ + DDL_DelayUS(PWC_MD_SWITCH_TIMEOUT); + + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + + while (PWC_RAM_HIGH_SPEED != READ_REG16(CM_PWC->RAMOPM)) { + WRITE_REG16(CM_PWC->RAMOPM, PWC_RAM_HIGH_SPEED); + if (0UL == u32To--) { + return LL_ERR; + } + } + + u32To = PWC_MD_SWITCH_TIMEOUT2; + while (0UL != READ_REG32(bCM_EFM->FRMC_b.LVM)) { + WRITE_REG32(bCM_EFM->FRMC_b.LVM, DISABLE); + if (0UL == u32To--) { + return LL_ERR; + } + } + + return LL_OK; +} + +/** + * @brief Ram area power down command. + * @param [in] u32Ram Specifies which ram to operate. @ref PWC_PD_Ram + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_RamCmd(uint32_t u32Ram, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_RAM_CONTROL(u32Ram)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->RAMPC0, u32Ram); + } else { + CLR_REG8_BIT(CM_PWC->RAMPC0, u32Ram); + } +} + +/** + * @brief VDR area power down command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_VdrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_VVDRSD); + } else { + SET_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_VVDRSD); + } +} + +/** + * @brief Ram area power down command. + * @param [in] u32PeriphRam Specifies which ram to operate. @ref PWC_PD_Periph_Ram + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power down mode + * @arg DISABLE: Run mode + * @retval None + */ +void PWC_PD_PeriphRamCmd(uint32_t u32PeriphRam, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_PRAM_CONTROL(u32PeriphRam)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PRAMLPC, u32PeriphRam); + } else { + CLR_REG8_BIT(CM_PWC->PRAMLPC, u32PeriphRam); + } +} + +/** + * @brief Initialize Power down mode config structure. Fill each pstcPDModeConfig with default value + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_StructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcPDModeConfig->u8IOState = PWC_PD_IO_KEEP1; + pstcPDModeConfig->u8Mode = PWC_PD_MD1; + pstcPDModeConfig->u8VcapCtrl = PWC_PD_VCAP_0P1UF; + } + return i32Ret; +} + +/** + * @brief Power down mode config structure. + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Power down mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_PD_Config(const stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_PD_IO_STATE(pstcPDModeConfig->u8IOState)); + DDL_ASSERT(IS_PWC_PD_MD(pstcPDModeConfig->u8Mode)); + DDL_ASSERT(IS_PWC_PD_VCAP_SEL(pstcPDModeConfig->u8VcapCtrl)); + + MODIFY_REG8(CM_PWC->PWRC0, (PWC_PWRC0_IORTN | PWC_PWRC0_PDMDS), \ + (pstcPDModeConfig->u8IOState | pstcPDModeConfig->u8Mode)); + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_PDTS, pstcPDModeConfig->u8VcapCtrl << PWC_PWRC1_PDTS_POS); + } + return i32Ret; +} + +/** + * @brief Set IO state while PD mode. + * @param [in] u8IoState IO state while power down mode + * @arg PWC_PD_IO_KEEP1 + * @arg PWC_PD_IO_KEEP2 + * @arg PWC_PD_IO_HIZ + * @retval None + */ +void PWC_PD_SetIoState(uint8_t u8IoState) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_PD_IO_STATE(u8IoState)); + + MODIFY_REG8(CM_PWC->PWRC0, PWC_PWRC0_IORTN, u8IoState); +} + +/** + * @brief Set power down mode. + * @param [in] u8PdMode Power down mode + * @arg PWC_PD_MD1 Power down mode 1 + * @arg PWC_PD_MD2 Power down mode 2 + * @arg PWC_PD_MD3 Power down mode 3 + * @arg PWC_PD_MD4 Power down mode 4 + * @retval None + */ +void PWC_PD_SetMode(uint8_t u8PdMode) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + DDL_ASSERT(IS_PWC_PD_MD(u8PdMode)); + + MODIFY_REG8(CM_PWC->PWRC0, PWC_PWRC0_PDMDS, u8PdMode); +} + +/** + * @brief Power down mode wake up event config. + * @param [in] u32Event Wakeup Event. @ref PWC_WKUP_Event_Sel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_PD_WakeupCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + uint8_t u8Event0 = (uint8_t)u32Event; + uint8_t u8Event1 = (uint8_t)(u32Event >> PWC_PD_WKUP1_POS); + uint8_t u8Event2 = (uint8_t)(u32Event >> PWC_PD_WKUP2_POS); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + SET_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + SET_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } else { + CLR_REG8_BIT(CM_PWC->PDWKE0, u8Event0); + CLR_REG8_BIT(CM_PWC->PDWKE1, u8Event1); + CLR_REG8_BIT(CM_PWC->PDWKE2, u8Event2); + } +} + +/** + * @brief Power down mode wake up event trigger config. + * @param [in] u8Event PVD and wake up pin. @ref PWC_WKUP_Trigger_Event_Sel + * @param [in] u8TrigEdge The trigger edge. + * @arg PWC_PD_WKUP_TRIG_FALLING + * @arg PWC_PD_WKUP_TRIG_RISING + * @retval None + */ +void PWC_PD_SetWakeupTriggerEdge(uint8_t u8Event, uint8_t u8TrigEdge) +{ + DDL_ASSERT(IS_PWC_WAKEUP_TRIG_EVT(u8Event)); + DDL_ASSERT(IS_PWC_WAKEUP_TRIG(u8TrigEdge)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (PWC_PD_WKUP_TRIG_RISING == u8TrigEdge) { + SET_REG8_BIT(CM_PWC->PDWKES, u8Event); + } else { + CLR_REG8_BIT(CM_PWC->PDWKES, u8Event); + } +} + +/** + * @brief Get wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t PWC_PD_GetWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = READ_REG8_BIT(CM_PWC->PDWKF0, u16Flag); + u8Flag1 = READ_REG8_BIT(CM_PWC->PDWKF1, (u16Flag >> PWC_PD_WKUP_FLAG1_POS)); + + return (((0U != u8Flag0) || (0U != u8Flag1)) ? SET : RESET); +} + +/** + * @brief Clear wake up event flag. + * @param [in] u16Flag Wake up event. @ref PWC_WKUP_Event_Flag_Sel + * @retval None + */ +void PWC_PD_ClearWakeupStatus(uint16_t u16Flag) +{ + uint8_t u8Flag0; + uint8_t u8Flag1; + + DDL_ASSERT(IS_PWC_WKUP_FLAG(u16Flag)); + + u8Flag0 = (uint8_t)u16Flag; + u8Flag1 = (uint8_t)(u16Flag >> PWC_PD_WKUP_FLAG1_POS); + + CLR_REG8_BIT(CM_PWC->PDWKF0, u8Flag0); + CLR_REG8_BIT(CM_PWC->PDWKF1, u8Flag1); +} + +/** + * @brief Stop mode config. + * @param [in] pstcStopConfig Chip config before entry stop mode. + * @arg u8StopDrv, MCU from which speed mode entry stop mode. + * @arg u16Clock, System clock setting after wake-up from stop mode. + * @arg u16FlashWait, Whether wait flash stable after wake-up from stop mode. + * @arg u16ExBusHold, ExBus status in stop mode. + * @retval int32_t: + * - LL_OK: Stop mode config successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_Config(const stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + DDL_ASSERT(IS_PWC_STOP_CLK(pstcStopConfig->u16Clock)); + DDL_ASSERT(IS_PWC_STOP_FLASH_WAIT(pstcStopConfig->u16FlashWait)); + DDL_ASSERT(IS_PWC_STOP_EXBUS(pstcStopConfig->u16ExBusHold)); + DDL_ASSERT(IS_PWC_STOP_DRV(pstcStopConfig->u8StopDrv)); + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, pstcStopConfig->u8StopDrv); + MODIFY_REG16(CM_PWC->STPMCR, (PWC_STPMCR_EXBUSOE | PWC_STPMCR_CKSMRC | PWC_STPMCR_FLNWT), \ + (pstcStopConfig->u16ExBusHold | pstcStopConfig->u16Clock | pstcStopConfig->u16FlashWait)); + + } + return i32Ret; +} + +/** + * @brief Initialize stop mode config structure. Fill each pstcStopConfig with default value + * @param [in] pstcStopConfig Pointer to a stc_pwc_stop_mode_config_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: Stop down mode structure initialize successful + * - LL_ERR_INVD_PARAM: NULL pointer + */ +int32_t PWC_STOP_StructInit(stc_pwc_stop_mode_config_t *pstcStopConfig) +{ + int32_t i32Ret = LL_OK; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcStopConfig->u16Clock = PWC_STOP_CLK_KEEP; + pstcStopConfig->u16FlashWait = PWC_STOP_FLASH_WAIT_ON; + pstcStopConfig->u16ExBusHold = PWC_STOP_EXBUS_HIZ; + pstcStopConfig->u8StopDrv = PWC_STOP_DRV_HIGH; + } + return i32Ret; +} + +/** + * @brief Stop mode wake up clock config. + * @param [in] u8Clock System clock setting after wake-up from stop mode. @ref PWC_STOP_CLK_Sel + * @retval None + */ +void PWC_STOP_ClockSelect(uint8_t u8Clock) +{ + DDL_ASSERT(IS_PWC_STOP_CLK(u8Clock)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_CKSMRC, (uint16_t)u8Clock); + +} + +/** + * @brief Stop mode wake up flash wait config. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_STOP_FlashWaitCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_FLNWT); + } else { + SET_REG16_BIT(CM_PWC->STPMCR, PWC_STPMCR_FLNWT); + } +} + +/** + * @brief Stop mode ex-bus status config. + * @param [in] u16ExBusHold ExBus status in stop mode. + * @arg PWC_STOP_EXBUS_HIZ + * @arg PWC_STOP_EXBUS_HOLD + * @retval None + */ +void PWC_STOP_ExBusHoldConfig(uint16_t u16ExBusHold) +{ + DDL_ASSERT(IS_PWC_STOP_EXBUS(u16ExBusHold)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(CM_PWC->STPMCR, PWC_STPMCR_EXBUSOE, u16ExBusHold); +} + +/** + * @brief Stop mode driver capacity config. + * @param [in] u8StopDrv Drive capacity while enter stop mode. + * @arg PWC_STOP_DRV_HIGH + * @arg PWC_STOP_DRV_LOW + * @retval None + */ +void PWC_STOP_SetDrv(uint8_t u8StopDrv) +{ + DDL_ASSERT(IS_PWC_STOP_DRV(u8StopDrv)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC1, PWC_PWRC1_STPDAS, u8StopDrv); +} + +/** + * @brief PWC power monitor command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note This monitor power is used for ADC and output to REGC pin. + */ +void PWC_PowerMonitorCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + if (ENABLE == enNewState) { + SET_REG8_BIT(CM_PWC->PWRC4, PWC_PWRC4_ADBUFE); + } else { + CLR_REG8_BIT(CM_PWC->PWRC4, PWC_PWRC4_ADBUFE); + } + +} + +/** + * @brief WKT Timer Initialize. + * @param [in] u16ClkSrc Clock source. + * This parameter can be one of the values @ref PWC_WKT_Clock_Source. + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_Config(uint16_t u16ClkSrc, uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_CLK_SRC(u16ClkSrc)); + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG16(CM_PWC->WKTCR, (uint16_t)(u16ClkSrc | (u16CmpVal & PWC_WKTCR_WKTMCMP))); +} + +/** + * @brief SET WKT Timer compare value. + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP, u16CmpVal); +} + +/** + * @brief Get WKT Timer compare value. + * @param None + * @retval uint16_t WKT Compare value + */ +uint16_t PWC_WKT_GetCompareValue(void) +{ + uint16_t u16CmpVal; + + u16CmpVal = READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKTMCMP); + + return u16CmpVal; +} + +/** + * @brief ENABLE or DISABLE WKT Timer. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void PWC_WKT_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_ON); + } else { + MODIFY_REG16(CM_PWC->WKTCR, PWC_WKTCR_WKTCE, PWC_WKT_OFF); + } + +} + +/** + * @brief Get WKT Timer count match flag. + * @param None + * @retval An @ref en_flag_status_t enumeration type value. enumeration value: + */ +en_flag_status_t PWC_WKT_GetStatus(void) +{ + en_flag_status_t enFlagState; + + enFlagState = (0U != READ_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF)) ? SET : RESET; + + return enFlagState; +} + +/** + * @brief Clear WKT Timer count match flag. + * @param None + * @retval None + */ +void PWC_WKT_ClearStatus(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + CLR_REG16_BIT(CM_PWC->WKTCR, PWC_WKTCR_WKOVF); +} + +/** + * @brief ENABLE or DISABLE XTAL32 power. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power on + * @arg DISABLE: Power off + * @retval None + */ +void PWC_XTAL32_PowerCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_CSDIS); + } else { + SET_REG_BIT(CM_PWC->PWRC5, PWC_PWRC5_CSDIS); + } +} + +/** + * @brief Ret_Sram area power command. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Power on + * @arg DISABLE: Power off + * @retval None + */ +void PWC_RetSram_PowerCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (ENABLE == enNewState) { + CLR_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_SRAMBSD); + } else { + SET_REG8_BIT(CM_PWC->PWRC5, PWC_PWRC5_SRAMBSD); + } +} + +/** + * @brief Set RTC clock. + * @param [in] u8Clock Reset event. @ref PWC_Rtc_Clock_Sel + * @retval None + */ +void PWC_SetRtcClock(uint8_t u8Clock) +{ + DDL_ASSERT(IS_PWC_RTC_CLK_SEL(u8Clock)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(CM_PWC->PWRC6, PWC_PWRC6_RTCCKSEL, u8Clock); +} + +/** + * @} + */ + +#endif /* LL_PWC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c new file mode 100644 index 0000000000..da1774e88f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_qspi.c @@ -0,0 +1,495 @@ +/** + ******************************************************************************* + * @file hc32_ll_qspi.c + * @brief This file provides firmware functions to manage the QSPI. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Optimize QSPI_ClearStatus function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_qspi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_QSPI QSPI + * @brief QSPI Driver Library + * @{ + */ + +#if (LL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Macros QSPI Local Macros + * @{ + */ + +/* QSPI registers Mask */ +#define QSPI_CR_CLR_MASK (QSPI_CR_DIV | QSPI_CR_SPIMD3 | QSPI_CR_PFSAE | \ + QSPI_CR_PFE | QSPI_CR_MDSEL) +#define QSPI_FCR_CLR_MASK (QSPI_FCR_DUTY | QSPI_FCR_DMCYCN | QSPI_FCR_SSNLD | \ + QSPI_FCR_SSNHD | QSPI_FCR_FOUR_BIC | QSPI_FCR_AWSL) +#define QSPI_CUSTOM_MD_CLR_MASK (QSPI_CR_IPRSL | QSPI_CR_APRSL | QSPI_CR_DPRSL) + +/** + * @defgroup QSPI_Check_Parameters_Validity QSPI check parameters validity + * @{ + */ + +#define IS_QSPI_CLK_DIV(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_CLK_DIV64) == QSPI_CLK_DIV64)) + +#define IS_QSPI_SPI_MD(x) \ +( ((x) == QSPI_SPI_MD0) || \ + ((x) == QSPI_SPI_MD3)) + +#define IS_QSPI_PREFETCH_MD(x) \ +( ((x) == QSPI_PREFETCH_MD_INVD) || \ + ((x) == QSPI_PREFETCH_MD_EDGE_STOP) || \ + ((x) == QSPI_PREFETCH_MD_IMMED_STOP)) + +#define IS_QSPI_READ_MD(x) \ +( ((x) == QSPI_RD_MD_STD_RD) || \ + ((x) == QSPI_RD_MD_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_DUAL_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_OUTPUT_FAST_RD) || \ + ((x) == QSPI_RD_MD_QUAD_IO_FAST_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_STANDARD_RD) || \ + ((x) == QSPI_RD_MD_CUSTOM_FAST_RD)) + +#define IS_QSPI_DUMMY_CYCLE(x) (((x) | QSPI_DUMMY_CYCLE18) == QSPI_DUMMY_CYCLE18) + +#define IS_QSPI_ADDR_WIDTH(x) \ +( ((x) == QSPI_ADDR_WIDTH_8BIT) || \ + ((x) == QSPI_ADDR_WIDTH_16BIT) || \ + ((x) == QSPI_ADDR_WIDTH_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_24BIT) || \ + ((x) == QSPI_ADDR_WIDTH_32BIT_INSTR_32BIT)) + +#define IS_QSPI_QSSN_SETUP_TIME(x) \ +( ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK0P5) || \ + ((x) == QSPI_QSSN_SETUP_ADVANCE_QSCK1P5)) + +#define IS_QSPI_QSSN_RELEASE_TIME(x) \ +( ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK0P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK1P5) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK32) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_QSCK128) || \ + ((x) == QSPI_QSSN_RELEASE_DELAY_INFINITE)) + +#define IS_QSPI_QSSN_INTERVAL_TIME(x) ((x) <= QSPI_QSSN_INTERVAL_QSCK16) + +#define IS_QSPI_INSTR_PROTOCOL(x) \ +( ((x) == QSPI_INSTR_PROTOCOL_1LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_2LINE) || \ + ((x) == QSPI_INSTR_PROTOCOL_4LINE)) + +#define IS_QSPI_ADDR_PROTOCOL(x) \ +( ((x) == QSPI_ADDR_PROTOCOL_1LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_2LINE) || \ + ((x) == QSPI_ADDR_PROTOCOL_4LINE)) + +#define IS_QSPI_DATA_PROTOCOL(x) \ +( ((x) == QSPI_DATA_PROTOCOL_1LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_2LINE) || \ + ((x) == QSPI_DATA_PROTOCOL_4LINE)) + +#define IS_QSPI_WP_PIN_LVL(x) \ +( ((x) == QSPI_WP_PIN_LOW) || \ + ((x) == QSPI_WP_PIN_HIGH)) + +#define IS_QSPI_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_ALL) == QSPI_FLAG_ALL)) + +#define IS_QSPI_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | QSPI_FLAG_CLR_ALL) == QSPI_FLAG_CLR_ALL)) + +#define IS_QSPI_BLOCK_SIZE(x) ((x) <= (QSPI_EXAR_EXADR >> QSPI_EXAR_EXADR_POS)) + +#define IS_QSPI_DIRECT_COMM_PROTOCOL(x) \ +( ((x) == QSPI_DIRECT_COMM_PROTOCOL_1LINE) || \ + ((x) == QSPI_DIRECT_COMM_PROTOCOL_2LINE) || \ + ((x) == QSPI_DIRECT_COMM_PROTOCOL_4LINE)) + +#define IS_QSPI_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/* QSPI reset timeout */ +#define QSPI_RMU_TIMEOUT (100UL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Functions QSPI Global Functions + * @{ + */ + +/** + * @brief De-initializes QSPI. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t QSPI_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeOut = 0U; + + /* Check parameters */ + DDL_ASSERT(IS_QSPI_PWC_UNLOCKED()); + + CLR_REG32_BIT(CM_RMU->FRST1, RMU_FRST1_QSPI); + /* Ensure reset procedure is completed */ + while (RMU_FRST1_QSPI != READ_REG32_BIT(CM_RMU->FRST1, RMU_FRST1_QSPI)) { + u32TimeOut++; + if (u32TimeOut > QSPI_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Initialize QSPI. + * @param [in] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_Init(const stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Duty = 0UL; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLK_DIV(pstcQspiInit->u32ClockDiv)); + DDL_ASSERT(IS_QSPI_SPI_MD(pstcQspiInit->u32SpiMode)); + DDL_ASSERT(IS_QSPI_PREFETCH_MD(pstcQspiInit->u32PrefetchMode)); + DDL_ASSERT(IS_QSPI_READ_MD(pstcQspiInit->u32ReadMode)); + DDL_ASSERT(IS_QSPI_DUMMY_CYCLE(pstcQspiInit->u32DummyCycle)); + DDL_ASSERT(IS_QSPI_ADDR_WIDTH(pstcQspiInit->u32AddrWidth)); + DDL_ASSERT(IS_QSPI_QSSN_SETUP_TIME(pstcQspiInit->u32SetupTime)); + DDL_ASSERT(IS_QSPI_QSSN_RELEASE_TIME(pstcQspiInit->u32ReleaseTime)); + DDL_ASSERT(IS_QSPI_QSSN_INTERVAL_TIME(pstcQspiInit->u32IntervalTime)); + + /* Duty cycle compensation */ + if (0UL == (pstcQspiInit->u32ClockDiv & QSPI_CLK_DIV2)) { + u32Duty = QSPI_FCR_DUTY; + } + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_CLR_MASK, (pstcQspiInit->u32ClockDiv | pstcQspiInit->u32SpiMode | + pstcQspiInit->u32PrefetchMode | pstcQspiInit->u32ReadMode)); + WRITE_REG32(CM_QSPI->CSCR, ((pstcQspiInit->u32ReleaseTime >> 8U) | pstcQspiInit->u32IntervalTime)); + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_CLR_MASK, (pstcQspiInit->u32DummyCycle | pstcQspiInit->u32AddrWidth | + pstcQspiInit->u32SetupTime | (pstcQspiInit->u32ReleaseTime & 0xFFU) | u32Duty)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_qspi_init_t member with default value. + * @param [out] pstcQspiInit Pointer to a @ref stc_qspi_init_t structure + * @retval int32_t: + * - LL_OK: stc_qspi_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_StructInit(stc_qspi_init_t *pstcQspiInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcQspiInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcQspiInit->u32ClockDiv = QSPI_CLK_DIV2; + pstcQspiInit->u32SpiMode = QSPI_SPI_MD0; + pstcQspiInit->u32PrefetchMode = QSPI_PREFETCH_MD_INVD; + pstcQspiInit->u32ReadMode = QSPI_RD_MD_STD_RD; + pstcQspiInit->u32DummyCycle = QSPI_DUMMY_CYCLE3; + pstcQspiInit->u32AddrWidth = QSPI_ADDR_WIDTH_24BIT; + pstcQspiInit->u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5; + pstcQspiInit->u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK0P5; + pstcQspiInit->u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1; + } + + return i32Ret; +} + +/** + * @brief Set the level of WP pin. + * @param [in] u32Level The level value. + * This parameter can be one of the following values: + * @arg QSPI_WP_PIN_LOW: WP(QSIO2) pin output low + * @arg QSPI_WP_PIN_HIGH: WP(QSIO2) pin output high + * @retval None + */ +void QSPI_SetWpPinLevel(uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_WP_PIN_LVL(u32Level)); + + MODIFY_REG32(CM_QSPI->FCR, QSPI_FCR_WPOL, u32Level); +} + +/** + * @brief Set the prefetch mode. + * @param [in] u32Mode The prefetch mode. + * This parameter can be one of the following values: + * @arg QSPI_PREFETCH_MD_INVD: Disable prefetch + * @arg QSPI_PREFETCH_MD_EDGE_STOP: Stop prefetch at the edge of byte + * @arg QSPI_PREFETCH_MD_IMMED_STOP: Stop prefetch at current position immediately + * @retval None + */ +void QSPI_SetPrefetchMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_PREFETCH_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, (QSPI_CR_PFE | QSPI_CR_PFSAE), u32Mode); +} + +/** + * @brief Selects the block to access. + * @param [in] u8Block Memory block number (range is 0 to 63) + * @retval None + */ +void QSPI_SelectMemoryBlock(uint8_t u8Block) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_BLOCK_SIZE(u8Block)); + + WRITE_REG32(CM_QSPI->EXAR, ((uint32_t)u8Block << QSPI_EXAR_EXADR_POS)); +} + +/** + * @brief Set the read mode. + * @param [in] u32Mode Read mode. + * This parameter can be one of the following values: + * @arg QSPI_RD_MD_STD_RD: Standard read mode (no dummy cycles) + * @arg QSPI_RD_MD_FAST_RD: Fast read mode (dummy cycles between address and data) + * @arg QSPI_RD_MD_DUAL_OUTPUT_FAST_RD: Fast read dual output mode (data on 2 lines) + * @arg QSPI_RD_MD_DUAL_IO_FAST_RD: Fast read dual I/O mode (address and data on 2 lines) + * @arg QSPI_RD_MD_QUAD_OUTPUT_FAST_RD: Fast read quad output mode (data on 4 lines) + * @arg QSPI_RD_MD_QUAD_IO_FAST_RD: Fast read quad I/O mode (address and data on 4 lines) + * @arg QSPI_RD_MD_CUSTOM_STANDARD_RD: Custom standard read mode + * @arg QSPI_RD_MD_CUSTOM_FAST_RD: Custom fast read mode + * @retval None + */ +void QSPI_SetReadMode(uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_READ_MD(u32Mode)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CR_MDSEL, u32Mode); +} + +/** + * @brief Configure the custom read. + * @param [in] pstcCustomMode Pointer to a @ref stc_qspi_custom_mode_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t QSPI_CustomReadConfig(const stc_qspi_custom_mode_t *pstcCustomMode) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcCustomMode) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_QSPI_INSTR_PROTOCOL(pstcCustomMode->u32InstrProtocol)); + DDL_ASSERT(IS_QSPI_ADDR_PROTOCOL(pstcCustomMode->u32AddrProtocol)); + DDL_ASSERT(IS_QSPI_DATA_PROTOCOL(pstcCustomMode->u32DataProtocol)); + + MODIFY_REG32(CM_QSPI->CR, QSPI_CUSTOM_MD_CLR_MASK, (pstcCustomMode->u32InstrProtocol | + pstcCustomMode->u32AddrProtocol | pstcCustomMode->u32DataProtocol)); + WRITE_REG32(CM_QSPI->CCMD, pstcCustomMode->u8InstrCode); + } + + return i32Ret; +} + +/** + * @brief Enable or disable XIP mode. + * @param [in] u8ModeCode Enter or exit XIP mode code + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void QSPI_XipModeCmd(uint8_t u8ModeCode, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(CM_QSPI->XCMD, u8ModeCode); + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } else { + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_XIPE); + } +} + +/** + * @brief Enter direct communication mode. + * @param None + * @retval None + */ +void QSPI_EnterDirectCommMode(void) +{ + /* Enter direct communication mode */ + SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); +} + +/** + * @brief Exit direct communication mode. + * @param None + * @retval None + */ +void QSPI_ExitDirectCommMode(void) +{ + /* Exit direct communication mode */ + CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); +} + +/** + * @brief Write data in direct communication mode. + * @param [in] u32Protocol Direct communication protocol. + * This parameter can be one of the following values: + * @arg QSPI_DIRECT_COMM_PROTOCOL_1LINE: Direct Comm Protocol on 1 line + * @arg QSPI_DIRECT_COMM_PROTOCOL_2LINE: Direct Comm Protocol on 2 lines + * @arg QSPI_DIRECT_COMM_PROTOCOL_4LINE: Direct Comm Protocol on 4 lines + * @param [in] u8Value Byte data. + * @retval None + */ +void QSPI_WriteDirectCommValue(uint32_t u32Protocol, uint8_t u8Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_DIRECT_COMM_PROTOCOL(u32Protocol)); + + WRITE_REG32(CM_QSPI->DCOM, (u32Protocol | u8Value)); +} + +/** + * @brief Get the size of prefetched buffer. + * @param None + * @retval uint8_t Prefetched buffer size. + */ +uint8_t QSPI_GetPrefetchBufSize(void) +{ + return (uint8_t)(READ_REG32_BIT(CM_QSPI->SR, QSPI_SR_PFNUM) >> QSPI_SR_PFNUM_POS); +} + +/** + * @brief Get QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_DIRECT_COMM_BUSY: Serial transfer being processed + * @arg QSPI_FLAG_XIP_MD: XIP mode + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_PREFETCH_BUF_FULL: Prefetch buffer is full + * @arg QSPI_FLAG_PREFETCH_STOP: Prefetch function operating + * @arg QSPI_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_QSPI_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(CM_QSPI->SR, u32Flag)) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear QSPI flag. + * @param [in] u32Flag QSPI flag type + * This parameter can be one or any combination of the following values: + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode + * @arg QSPI_FLAG_CLR_ALL: All of the above + * @retval None + */ +void QSPI_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_QSPI_CLR_FLAG(u32Flag)); + + WRITE_REG32(CM_QSPI->SR2, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_QSPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c new file mode 100644 index 0000000000..f50fc31a5d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_rmu.c @@ -0,0 +1,290 @@ +/** + ******************************************************************************* + * @file hc32_ll_rmu.c + * @brief This file provides firmware functions to manage the Reset Manage Unit + * (RMU). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rmu.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RMU RMU + * @brief RMU Driver Library + * @{ + */ + +#if (LL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Local_Macros RMU Local Macros + * @{ + */ +#define IS_RMU_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +#define RMU_TIMEOUT (100U) + +/** + * @defgroup RMU_Check_Parameters_Validity RMU Check Parameters Validity + * @{ + */ + +/*! Parameter validity check for RMU reset cause. */ +#define IS_VALID_RMU_RST_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FLAG_ALL) == RMU_FLAG_ALL)) + +/*! Parameter validity check for RMU reset register0. */ +#define IS_FRST0_PERIPH(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FRST0_PERIPH_ALL ) == RMU_FRST0_PERIPH_ALL)) + +/*! Parameter validity check for RMU reset register1. */ +#define IS_FRST1_PERIPH(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FRST1_PERIPH_ALL) == RMU_FRST1_PERIPH_ALL)) + +/*! Parameter validity check for RMU reset register2. */ +#define IS_FRST2_PERIPH(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FRST2_PERIPH_ALL) == RMU_FRST2_PERIPH_ALL)) + +/*! Parameter validity check for RMU reset register3. */ +#define IS_FRST3_PERIPH(x) \ +( ((x) != 0UL) && \ + (((x) | RMU_FRST3_PERIPH_ALL) == RMU_FRST3_PERIPH_ALL)) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Functions RMU Global Functions + * @{ + */ + +/** + * @brief Get the reset cause. + * @param [in] u32RmuResetCause Reset flags that need to be queried, @ref RMU_ResetCause in details + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause) +{ + en_flag_status_t enStatus; + DDL_ASSERT(IS_VALID_RMU_RST_FLAG(u32RmuResetCause)); + + enStatus = ((0UL == READ_REG32_BIT(CM_RMU->RSTF0, u32RmuResetCause)) ? RESET : SET); + return enStatus; +} + +/** + * @brief Clear reset Status. + * @param None + * @retval NOne + * @note Clear reset flag should be done after read RMU_RSTF0 register. + * Call PWC_Unlock(PWC_UNLOCK_CODE_1) unlock RMU_RSTF0 register first. + */ +void RMU_ClearStatus(void) +{ + DDL_ASSERT(IS_RMU_UNLOCKED()); + SET_REG_BIT(CM_RMU->RSTF0, RMU_RSTF0_CLRF); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); +} + +/** + * @brief Enable or disable LOCKUP reset. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_PRSTCR0 register first. + */ +void RMU_CPULockUpCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_RMU_UNLOCKED()); + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bCM_RMU->PRSTCR0_b.LKUPREN, enNewState); +} + +/** + * @brief Reset FRST0 peripheral. + * @param [in] u32Frst0Periph The peripheral in FRST0 @ref RMU_FRST0_Peripheral. + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first. + */ +int32_t RMU_Frst0PeriphReset(uint32_t u32Frst0Periph) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + /* Check RMU register protect */ + DDL_ASSERT(IS_RMU_UNLOCKED()); + DDL_ASSERT(IS_FRST0_PERIPH(u32Frst0Periph)); + + /* Reset */ + CLR_REG32_BIT(CM_RMU->FRST0, u32Frst0Periph); + /* Ensure reset procedure is completed */ + while (u32Frst0Periph != READ_REG32_BIT(CM_RMU->FRST0, u32Frst0Periph)) { + u8TimeOut++; + if (u8TimeOut > RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Reset FRST1 peripheral. + * @param [in] u32Frst1Periph The peripheral in FRST1 @ref RMU_FRST1_Peripheral. + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first. + */ +int32_t RMU_Frst1PeriphReset(uint32_t u32Frst1Periph) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + /* Check RMU register protect */ + DDL_ASSERT(IS_RMU_UNLOCKED()); + DDL_ASSERT(IS_FRST1_PERIPH(u32Frst1Periph)); + + /* Reset */ + CLR_REG32_BIT(CM_RMU->FRST1, u32Frst1Periph); + /* Ensure reset procedure is completed */ + while (u32Frst1Periph != READ_REG32_BIT(CM_RMU->FRST1, u32Frst1Periph)) { + u8TimeOut++; + if (u8TimeOut > RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Reset FRST2 peripheral. + * @param [in] u32Frst2Periph The peripheral in FRST2 @ref RMU_FRST2_Peripheral. + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first. + */ +int32_t RMU_Frst2PeriphReset(uint32_t u32Frst2Periph) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + /* Check RMU register protect */ + DDL_ASSERT(IS_RMU_UNLOCKED()); + DDL_ASSERT(IS_FRST2_PERIPH(u32Frst2Periph)); + + /* Reset */ + CLR_REG32_BIT(CM_RMU->FRST2, u32Frst2Periph); + /* Ensure reset procedure is completed */ + while (u32Frst2Periph != READ_REG32_BIT(CM_RMU->FRST2, u32Frst2Periph)) { + u8TimeOut++; + if (u8TimeOut > RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Reset FRST3 peripheral. + * @param [in] u32Frst3Periph The peripheral in FRST3 @ref RMU_FRST3_Peripheral. + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first. + */ +int32_t RMU_Frst3PeriphReset(uint32_t u32Frst3Periph) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + /* Check RMU register protect */ + DDL_ASSERT(IS_RMU_UNLOCKED()); + DDL_ASSERT(IS_FRST3_PERIPH(u32Frst3Periph)); + + /* Reset */ + CLR_REG32_BIT(CM_RMU->FRST3, u32Frst3Periph); + /* Ensure reset procedure is completed */ + while (u32Frst3Periph != READ_REG32_BIT(CM_RMU->FRST3, u32Frst3Periph)) { + u8TimeOut++; + if (u8TimeOut > RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_RMU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c new file mode 100644 index 0000000000..007b3d098a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_rtc.c @@ -0,0 +1,943 @@ +/** + ******************************************************************************* + * @file hc32_ll_rtc.c + * @brief This file provides firmware functions to manage the Real-Time + * Clock(RTC). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_rtc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_RTC RTC + * @brief Real-Time Clock Driver Library + * @{ + */ + +#if (LL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Local_Macros RTC Local Macros + * @{ + */ + +/* RTC software reset timeout(ms) */ +#define RTC_SW_RST_TIMEOUT (100UL) +/* RTC mode switch timeout(ms) */ +#define RTC_MD_SWITCH_TIMEOUT (100UL) + +/** + * @defgroup RTC_Check_Parameters_Validity RTC Check Parameters Validity + * @{ + */ +#define IS_RTC_DATA_FMT(x) \ +( ((x) == RTC_DATA_FMT_DEC) || \ + ((x) == RTC_DATA_FMT_BCD)) + +#define IS_RTC_CLK_SRC(x) \ +( ((x) == RTC_CLK_SRC_XTAL32) || \ + ((x) == RTC_CLK_SRC_LRC) || \ + ((x) == RTC_CLK_SRC_XTAL_DIV)) + +#define IS_RTC_HOUR_FMT(x) \ +( ((x) == RTC_HOUR_FMT_12H) || \ + ((x) == RTC_HOUR_FMT_24H)) + +#define IS_RTC_INT_PERIOD(x) \ +( ((x) == RTC_INT_PERIOD_INVD) || \ + ((x) == RTC_INT_PERIOD_PER_HALF_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_SEC) || \ + ((x) == RTC_INT_PERIOD_PER_MINUTE) || \ + ((x) == RTC_INT_PERIOD_PER_HOUR) || \ + ((x) == RTC_INT_PERIOD_PER_DAY) || \ + ((x) == RTC_INT_PERIOD_PER_MONTH)) + +#define IS_RTC_CLK_COMPEN(x) \ +( ((x) == RTC_CLK_COMPEN_DISABLE) || \ + ((x) == RTC_CLK_COMPEN_ENABLE)) + +#define IS_RTC_CLK_COMPEN_MD(x) \ +( ((x) == RTC_CLK_COMPEN_MD_DISTRIBUTED) || \ + ((x) == RTC_CLK_COMPEN_MD_UNIFORM)) + +#define IS_RTC_HOUR_12H_AM_PM(x) \ +( ((x) == RTC_HOUR_12H_AM) || \ + ((x) == RTC_HOUR_12H_PM)) + +#define IS_RTC_GET_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_ALL) == RTC_FLAG_ALL)) + +#define IS_RTC_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | RTC_FLAG_CLR_ALL) == RTC_FLAG_CLR_ALL)) + +#define IS_RTC_INT(x) \ +( ((x) != 0U) && \ + (((x) | RTC_INT_ALL) == RTC_INT_ALL)) + +#define IS_RTC_YEAR(x) ((x) <= 99U) + +#define IS_RTC_MONTH(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_DAY(x) (((x) >= 1U) && ((x) <= 31U)) + +#define IS_RTC_HOUR_12H(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_HOUR_24H(x) ((x) <= 23U) + +#define IS_RTC_MINUTE(x) ((x) <= 59U) + +#define IS_RTC_SEC(x) ((x) <= 59U) + +#define IS_RTC_WEEKDAY(x) ((x) <= 6U) + +#define IS_RTC_ALARM_WEEKDAY(x) (((x) >= 0x01U) && ((x) <= 0x7FU)) + +#define IS_RTC_COMPEN_VALUE(x) ((x) <= 0x1FFU) + +#define IS_RTC_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Functions RTC Global Functions + * @{ + */ + +/** + * @brief De-Initialize RTC. + * @param None + * @retval int32_t: + * - LL_OK: De-Initialize success + * - LL_ERR_TIMEOUT: De-Initialize timeout + */ +int32_t RTC_DeInit(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + WRITE_REG32(bCM_RTC->CR0_b.RESET, RESET); + /* Waiting for normal count status or end of RTC software reset */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + /* Reset all RTC registers */ + WRITE_REG32(bCM_RTC->CR0_b.RESET, SET); + /* Waiting for RTC software reset to complete */ + u32Count = RTC_SW_RST_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR0_b.RESET)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + + return i32Ret; +} + +/** + * @brief Initialize RTC. + * @param [in] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(pstcRtcInit->u8ClockSrc)); + DDL_ASSERT(IS_RTC_HOUR_FMT(pstcRtcInit->u8HourFormat)); + DDL_ASSERT(IS_RTC_INT_PERIOD(pstcRtcInit->u8IntPeriod)); + DDL_ASSERT(IS_RTC_CLK_COMPEN(pstcRtcInit->u8ClockCompen)); + DDL_ASSERT(IS_RTC_COMPEN_VALUE(pstcRtcInit->u16CompenValue)); + DDL_ASSERT(IS_RTC_CLK_COMPEN_MD(pstcRtcInit->u8CompenMode)); + DDL_ASSERT(IS_RTC_PWC_UNLOCKED()); + + /* RTC CR3 Configuration */ + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), pstcRtcInit->u8ClockSrc & (RTC_CR3_LRCEN | RTC_CR3_RCKSEL)); + MODIFY_REG8(CM_PWC->PWRC6, PWC_PWRC6_RTCCKSEL, pstcRtcInit->u8ClockSrc & PWC_PWRC6_RTCCKSEL); + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, (RTC_CR1_PRDS | RTC_CR1_AMPM | RTC_CR1_ONEHZSEL), + (pstcRtcInit->u8IntPeriod | pstcRtcInit->u8HourFormat | pstcRtcInit->u8CompenMode)); + /* RTC Compensation Configuration */ + MODIFY_REG8(CM_RTC->ERRCRH, (RTC_ERRCRH_COMPEN | RTC_ERRCRH_COMP8), + (pstcRtcInit->u8ClockCompen | (uint8_t)((pstcRtcInit->u16CompenValue >> 8U) & 0x01U))); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(pstcRtcInit->u16CompenValue & 0xFFU)); + } + + return i32Ret; +} + +/** + * @brief Fills each stc_rtc_init_t member with default value. + * @param [out] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval int32_t: + * - LL_OK: stc_rtc_init_t member initialize success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcRtcInit->u8ClockSrc = RTC_CLK_SRC_LRC; + pstcRtcInit->u8HourFormat = RTC_HOUR_FMT_24H; + pstcRtcInit->u8IntPeriod = RTC_INT_PERIOD_INVD; + pstcRtcInit->u8ClockCompen = RTC_CLK_COMPEN_DISABLE; + pstcRtcInit->u8CompenMode = RTC_CLK_COMPEN_MD_DISTRIBUTED; + pstcRtcInit->u16CompenValue = 0U; + } + + return i32Ret; +} + +/** + * @brief Enter RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Enter mode success + * - LL_ERR_TIMEOUT: Enter mode timeout + */ +int32_t RTC_EnterRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Exit RTC read/write mode. + * @param None + * @retval int32_t: + * - LL_OK: Exit mode success + * - LL_ERR_TIMEOUT: Exit mode timeout + */ +int32_t RTC_ExitRwMode(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + if (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Confirm the condition for RTC to enter low power mode. + * @param None + * @retval int32_t: + * - LL_OK: Can enter low power mode + * - LL_ERR_TIMEOUT: Can't enter low power mode + */ +int32_t RTC_ConfirmLPMCond(void) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check RTC work status */ + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, SET); + /* Waiting for RTC RWEN bit set */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + if (LL_OK == i32Ret) { + WRITE_REG32(bCM_RTC->CR2_b.RWREQ, RESET); + /* Waiting for RTC RWEN bit reset */ + u32Count = RTC_MD_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bCM_RTC->CR2_b.RWEN)) { + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + } + } + + return i32Ret; +} + +/** + * @brief Set the RTC interrupt period. + * @param [in] u8Period Specifies the interrupt period. + * This parameter can be one of the following values: + * @arg RTC_INT_PERIOD_INVD: Period interrupt invalid + * @arg RTC_INT_PERIOD_PER_HALF_SEC: Interrupt per half second + * @arg RTC_INT_PERIOD_PER_SEC: Interrupt per second + * @arg RTC_INT_PERIOD_PER_MINUTE: Interrupt per minute + * @arg RTC_INT_PERIOD_PER_HOUR: Interrupt per hour + * @arg RTC_INT_PERIOD_PER_DAY: Interrupt per day + * @arg RTC_INT_PERIOD_PER_MONTH: Interrupt per month + * @retval None + */ +void RTC_SetIntPeriod(uint8_t u8Period) +{ + uint32_t u32RtcSta; + uint32_t u32IntSta; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT_PERIOD(u8Period)); + + u32RtcSta = READ_REG32(bCM_RTC->CR1_b.START); + u32IntSta = READ_REG32(bCM_RTC->CR2_b.PRDIE); + /* Disable period interrupt when START=1 and clear period flag after write */ + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, RESET); + } + + /* RTC CR1 Configuration */ + MODIFY_REG8(CM_RTC->CR1, RTC_CR1_PRDS, u8Period); + WRITE_REG32(bCM_RTC->CR2_b.PRDF, RESET); + + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) { + WRITE_REG32(bCM_RTC->CR2_b.PRDIE, SET); + } +} + +/** + * @brief Set the RTC clock source. + * @param [in] u8Src Specifies the clock source. + * This parameter can be one of the following values: + * @arg @ref RTC_Clock_Source + * @retval None + */ +void RTC_SetClockSrc(uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLK_SRC(u8Src)); + DDL_ASSERT(IS_RTC_PWC_UNLOCKED()); + + MODIFY_REG8(CM_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), u8Src & (RTC_CR3_LRCEN | RTC_CR3_RCKSEL)); + MODIFY_REG8(CM_PWC->PWRC6, PWC_PWRC6_RTCCKSEL, u8Src & PWC_PWRC6_RTCCKSEL); +} + +/** + * @brief Set RTC clock compensation value. + * @param [in] u16Value Specifies the clock compensation value of RTC. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF. + * @retval None + */ +void RTC_SetClockCompenValue(uint16_t u16Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_COMPEN_VALUE(u16Value)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMP8, ((uint32_t)u16Value >> 8U) & 0x01U); + WRITE_REG8(CM_RTC->ERRCRL, (uint8_t)(u16Value & 0x00FFU)); +} + +/** + * @brief Get RTC counter status. + * @param None + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: RTC counter started + * - DISABLE: RTC counter stopped + */ +en_functional_state_t RTC_GetCounterState(void) +{ + en_functional_state_t enState = DISABLE; + + if (0UL != READ_REG32(bCM_RTC->CR1_b.START)) { + enState = ENABLE; + } + + return enState; +} + +/** + * @brief Enable or disable RTC count. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.START, enNewState); +} + +/** + * @brief Enable or disable RTC LRC function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_LrcCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR3_b.LRCEN, enNewState); +} + +/** + * @brief Enable or disable RTC 1HZ output. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_OneHzOutputCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR1_b.ONEHZOE, enNewState); +} + +/** + * @brief Enable or disable clock compensation. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_ClockCompenCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->ERRCRH_b.COMPEN, enNewState); +} + +/** + * @brief Set RTC current date. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Set date success + * - LL_ERR: Set date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + DDL_ASSERT(IS_RTC_YEAR(RTC_BCD2DEC(pstcRtcDate->u8Year))); + DDL_ASSERT(IS_RTC_MONTH(RTC_BCD2DEC(pstcRtcDate->u8Month))); + DDL_ASSERT(IS_RTC_DAY(RTC_BCD2DEC(pstcRtcDate->u8Day))); + } else { + DDL_ASSERT(IS_RTC_YEAR(pstcRtcDate->u8Year)); + DDL_ASSERT(IS_RTC_MONTH(pstcRtcDate->u8Month)); + DDL_ASSERT(IS_RTC_DAY(pstcRtcDate->u8Day)); + } + DDL_ASSERT(IS_RTC_WEEKDAY(pstcRtcDate->u8Weekday)); + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_DEC2BCD(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_DEC2BCD(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_DEC2BCD(pstcRtcDate->u8Day); + } + + WRITE_REG8(CM_RTC->YEAR, pstcRtcDate->u8Year); + WRITE_REG8(CM_RTC->MON, pstcRtcDate->u8Month); + WRITE_REG8(CM_RTC->DAY, pstcRtcDate->u8Day); + WRITE_REG8(CM_RTC->WEEK, pstcRtcDate->u8Weekday); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current date. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval int32_t: + * - LL_OK: Get date success + * - LL_ERR: Get date failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcDate) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC date registers */ + pstcRtcDate->u8Year = READ_REG8(CM_RTC->YEAR); + pstcRtcDate->u8Month = READ_REG8(CM_RTC->MON); + pstcRtcDate->u8Day = READ_REG8(CM_RTC->DAY); + pstcRtcDate->u8Weekday = READ_REG8(CM_RTC->WEEK); + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcDate->u8Year = RTC_BCD2DEC(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = RTC_BCD2DEC(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = RTC_BCD2DEC(pstcRtcDate->u8Day); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC current time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Set time success + * - LL_ERR: Set time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcTime->u8Hour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcTime->u8Minute))); + DDL_ASSERT(IS_RTC_SEC(RTC_BCD2DEC(pstcRtcTime->u8Second))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcTime->u8Hour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcTime->u8AmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcTime->u8Hour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcTime->u8Minute)); + DDL_ASSERT(IS_RTC_SEC(pstcRtcTime->u8Second)); + } + + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_DEC2BCD(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_DEC2BCD(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_DEC2BCD(pstcRtcTime->u8Second); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcTime->u8AmPm)) { + SET_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->HOUR, pstcRtcTime->u8Hour); + WRITE_REG8(CM_RTC->MIN, pstcRtcTime->u8Minute); + WRITE_REG8(CM_RTC->SEC, pstcRtcTime->u8Second); + + /* Exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Get RTC current time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval int32_t: + * - LL_OK: Get time success + * - LL_ERR: Get time failed + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcTime) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + /* Enter read/write mode */ + if (LL_OK != RTC_EnterRwMode()) { + i32Ret = LL_ERR; + } else { + /* Get RTC time registers */ + pstcRtcTime->u8Hour = READ_REG8(CM_RTC->HOUR); + pstcRtcTime->u8Minute = READ_REG8(CM_RTC->MIN); + pstcRtcTime->u8Second = READ_REG8(CM_RTC->SEC); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcTime->u8Hour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcTime->u8Hour, RTC_HOUR_12H_PM); + pstcRtcTime->u8AmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcTime->u8AmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcTime->u8Hour = RTC_BCD2DEC(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = RTC_BCD2DEC(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = RTC_BCD2DEC(pstcRtcTime->u8Second); + } + + /* exit read/write mode */ + if (LL_OK != RTC_ExitRwMode()) { + i32Ret = LL_ERR; + } + } + } + + return i32Ret; +} + +/** + * @brief Set RTC alarm time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [in] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Set RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + if (RTC_DATA_FMT_DEC != u8Format) { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + } + DDL_ASSERT(IS_RTC_MINUTE(RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute))); + } else { + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + DDL_ASSERT(IS_RTC_HOUR_12H(pstcRtcAlarm->u8AlarmHour)); + DDL_ASSERT(IS_RTC_HOUR_12H_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } else { + DDL_ASSERT(IS_RTC_HOUR_24H(pstcRtcAlarm->u8AlarmHour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcAlarm->u8AlarmMinute)); + } + DDL_ASSERT(IS_RTC_ALARM_WEEKDAY(pstcRtcAlarm->u8AlarmWeekday)); + + /* Configure alarm registers */ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_DEC2BCD(pstcRtcAlarm->u8AlarmMinute); + } + if ((RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) && + (RTC_HOUR_12H_PM == pstcRtcAlarm->u8AlarmAmPm)) { + SET_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + } + + WRITE_REG8(CM_RTC->ALMHOUR, pstcRtcAlarm->u8AlarmHour); + WRITE_REG8(CM_RTC->ALMMIN, pstcRtcAlarm->u8AlarmMinute); + WRITE_REG8(CM_RTC->ALMWEEK, pstcRtcAlarm->u8AlarmWeekday); + } + + return i32Ret; +} + +/** + * @brief Get RTC alarm time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FMT_DEC: Decimal data format + * @arg RTC_DATA_FMT_BCD: BCD data format + * @param [out] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval int32_t: + * - LL_OK: Get RTC alarm time success + * - LL_ERR_INVD_PARAM: Invalid parameter + */ +int32_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcRtcAlarm) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FMT(u8Format)); + + /* Get RTC date and time register */ + pstcRtcAlarm->u8AlarmWeekday = READ_REG8(CM_RTC->ALMWEEK); + pstcRtcAlarm->u8AlarmMinute = READ_REG8(CM_RTC->ALMMIN); + pstcRtcAlarm->u8AlarmHour = READ_REG8(CM_RTC->ALMHOUR); + + if (RTC_HOUR_FMT_12H == READ_REG32(bCM_RTC->CR1_b.AMPM)) { + if (RTC_HOUR_12H_PM == (pstcRtcAlarm->u8AlarmHour & RTC_HOUR_12H_PM)) { + CLR_REG8_BIT(pstcRtcAlarm->u8AlarmHour, RTC_HOUR_12H_PM); + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_PM; + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_12H_AM; + } + } else { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR_24H; + } + + /* Check decimal format*/ + if (RTC_DATA_FMT_DEC == u8Format) { + pstcRtcAlarm->u8AlarmHour = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = RTC_BCD2DEC(pstcRtcAlarm->u8AlarmMinute); + } + } + + return i32Ret; +} + +/** + * @brief Enable or disable RTC alarm. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_AlarmCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bCM_RTC->CR2_b.ALME, enNewState); +} + +/** + * @brief Enable or disable specified RTC interrupt. + * @param [in] u32IntType Specifies the RTC interrupt source. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void RTC_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32IntTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32IntTemp = u32IntType & 0x0000FFUL; + if (0UL != u32IntTemp) { + if (DISABLE != enNewState) { + SET_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } else { + CLR_REG8_BIT(CM_RTC->CR2, u32IntTemp); + } + } + +} + +/** + * @brief Get RTC flag status. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t RTC_GetStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_GET_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + if (0U != (READ_REG8_BIT(CM_RTC->CR2, u8FlagTemp))) { + enFlagSta = SET; + } + } + + return enFlagSta; +} + +/** + * @brief Clear RTC flag. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg @ref RTC_Flag + * @arg RTC_FLAG_CLR_ALL: All of the above + * @retval None + */ +void RTC_ClearStatus(uint32_t u32Flag) +{ + uint8_t u8FlagTemp; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLR_FLAG(u32Flag)); + + u8FlagTemp = (uint8_t)(u32Flag & 0xFFU); + if (0U != u8FlagTemp) { + CLR_REG8_BIT(CM_RTC->CR2, u8FlagTemp); + } + +} + +/** + * @} + */ + +#endif /* LL_RTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c new file mode 100644 index 0000000000..a380b2615f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_smc.c @@ -0,0 +1,520 @@ +/** + ******************************************************************************* + * @file hc32_ll_smc.c + * @brief This file provides firmware functions to manage the EXMC_SMC + * (External Memory Controller: Static Memory Controller). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_smc.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_EXMC EXMC + * @brief External Memory Controller Driver Library + * @{ + */ + +/** + * @defgroup LL_SMC SMC + * @brief Static Memory Controller Driver Library + * @{ + */ + +#if (LL_SMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Local_Macros EXMC_SMC Local Macros + * @{ + */ + +/** + * @defgroup EXMC_SMC_Check_Parameters_Validity EXMC_SMC Check Parameters Validity + * @{ + */ + +#define IS_EXMC_SMC_MEMORY_WIDTH(x) \ +( ((x) == EXMC_SMC_MEMORY_WIDTH_8BIT) || \ + ((x) == EXMC_SMC_MEMORY_WIDTH_16BIT)) + +#define IS_EXMC_SMC_READ_MD(x) \ +( ((x) == EXMC_SMC_READ_SYNC) || \ + ((x) == EXMC_SMC_READ_ASYNC)) + +#define IS_EXMC_SMC_WRITE_MD(x) \ +( ((x) == EXMC_SMC_WRITE_SYNC) || \ + ((x) == EXMC_SMC_WRITE_ASYNC)) + +#define IS_EXMC_SMC_CHIP(x) ((x) == EXMC_SMC_CHIP0) + +#define IS_EXMC_SMC_BLS_SYNC(x) \ +( ((x) == EXMC_SMC_BLS_SYNC_CS) || \ + ((x) == EXMC_SMC_BLS_SYNC_WE)) + +#define IS_EXMC_SMC_BAA_PORT(x) \ +( ((x) == EXMC_SMC_BAA_PORT_DISABLE) || \ + ((x) == EXMC_SMC_BAA_PORT_ENABLE)) + +#define IS_EXMC_SMC_ADV_PORT(x) \ +( ((x) == EXMC_SMC_ADV_PORT_DISABLE) || \ + ((x) == EXMC_SMC_ADV_PORT_ENABLE)) + +#define IS_EXMC_SMC_CMD(x) \ +( ((x) == EXMC_SMC_CMD_MDREGCONFIG) || \ + ((x) == EXMC_SMC_CMD_UPDATEREGS) || \ + ((x) == EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS)) + +#define IS_EXMC_SMC_CRE_POLARITY(x) \ +( ((x) == EXMC_SMC_CRE_POLARITY_LOW) || \ + ((x) == EXMC_SMC_CRE_POLARITY_HIGH)) + +#define IS_EXMC_SMC_SAMPLE_CLK(x) \ +( ((x) == EXMC_SMC_SAMPLE_CLK_INTERNCLK) || \ + ((x) == EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT) || \ + ((x) == EXMC_SMC_SAMPLE_CLK_EXTCLK)) + +#define IS_EXMC_SMC_MAP_ADDR(match, msk) \ +( (EXMC_SMC_MAP_ADDR((match), (msk)) >= EXMC_SMC_ADDR_MIN) && \ + (EXMC_SMC_MAP_ADDR((match), (msk)) <= EXMC_SMC_ADDR_MAX)) + +#define IS_EXMC_SMC_REFRESH_PERIOD(x) ((x) <= (uint8_t)SMC_RFTR_REFPRD) + +#define IS_EXMC_SMC_CMD_ADDR(x) ((x) <= 0xFFFFFUL) + +#define IS_EXMC_SMC_TIMING_RC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_SMC_TIMING_WC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_SMC_TIMING_CEOE_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_WP_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_TR_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_ADV_CYCLE(x) ((x) <= 7UL) +/** + * @} + */ + +/* EXMC_SMC map address */ +#define EXMC_SMC_MAP_ADDR(MATCH, MSK) ((~((MATCH) ^ (MSK))) << 24U) + +/** + * @defgroup EXMC_SMC_Register EXMC_SMC Register + * @{ + */ +#define EXMC_SMC_CPSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&CM_SMC->CPSR0)) + (0x20UL * (__CHIPx__)))) +#define EXMC_SMC_TMSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&CM_SMC->TMSR0)) + (0x20UL * (__CHIPx__)))) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Register_Bit_Mask EXMC_SMC Register Bit Mask + * @{ + */ +#define SMC_CSCR0_ADDMSKx_POS(__CHIPx__) (((__CHIPx__) & 0x03UL) << 3U) +#define SMC_CSCR0_ADDMSKx(__CHIPx__) (SMC_CSCR0_ADDMSK0 << SMC_CSCR0_ADDMSKx_POS((__CHIPx__))) + +#define SMC_CSCR1_ADDMATx_POS(__CHIPx__) (((__CHIPx__) & 0x03UL) << 3U) +#define SMC_CSCR1_ADDMATx(__CHIPx__) (SMC_CSCR1_ADDMAT0 << SMC_CSCR1_ADDMATx_POS((__CHIPx__))) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Register_Reset_Value EXMC_SMC Register Reset Value + * @{ + */ +#define EXMC_SMC_BACR_RST_VALUE (0x00000300UL) +/** + * @} + */ + +#define EXMC_SMC_RMU_TIMEOUT (100U) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Functions EXMC_SMC Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure @ref stc_exmc_smc_init_t to default values + * @param [out] pstcSmcInit Pointer to a @ref stc_exmc_smc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmcInit value is NULL. + */ +int32_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcSmcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmcInit) { + pstcSmcInit->stcChipConfig.u32ReadMode = EXMC_SMC_READ_ASYNC; + pstcSmcInit->stcChipConfig.u32WriteMode = EXMC_SMC_WRITE_ASYNC; + pstcSmcInit->stcChipConfig.u32MemoryWidth = EXMC_SMC_MEMORY_WIDTH_16BIT; + pstcSmcInit->stcChipConfig.u32BAA = EXMC_SMC_BAA_PORT_DISABLE; + pstcSmcInit->stcChipConfig.u32ADV = EXMC_SMC_ADV_PORT_DISABLE; + pstcSmcInit->stcChipConfig.u32BLS = EXMC_SMC_BLS_SYNC_CS; + pstcSmcInit->stcChipConfig.u32AddrMask = 0xF8UL; /* Address space 128M: 0x60000000 ~ 0x67FFFFFF */ + pstcSmcInit->stcChipConfig.u32AddrMatch = 0x60UL; + + pstcSmcInit->stcTimingConfig.u8RC = 7U; + pstcSmcInit->stcTimingConfig.u8WC = 7U; + pstcSmcInit->stcTimingConfig.u8CEOE = 1U; + pstcSmcInit->stcTimingConfig.u8WP = 5U; + pstcSmcInit->stcTimingConfig.u8TR = 0U; + pstcSmcInit->stcTimingConfig.u8ADV = 1U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize EXMC_SMC function. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @param [in] pstcSmcInit Pointer to a @ref stc_exmc_smc_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmcInit value is NULL. + */ +int32_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcSmcInit) +{ + uint32_t u32TMCR; + uint32_t u32CPCR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmcInit) { + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_SMC_READ_MD(pstcSmcInit->stcChipConfig.u32ReadMode)); + DDL_ASSERT(IS_EXMC_SMC_WRITE_MD(pstcSmcInit->stcChipConfig.u32WriteMode)); + DDL_ASSERT(IS_EXMC_SMC_MEMORY_WIDTH(pstcSmcInit->stcChipConfig.u32MemoryWidth)); + DDL_ASSERT(IS_EXMC_SMC_BAA_PORT(pstcSmcInit->stcChipConfig.u32BAA)); + DDL_ASSERT(IS_EXMC_SMC_ADV_PORT(pstcSmcInit->stcChipConfig.u32ADV)); + DDL_ASSERT(IS_EXMC_SMC_BLS_SYNC(pstcSmcInit->stcChipConfig.u32BLS)); + DDL_ASSERT(IS_EXMC_SMC_MAP_ADDR(pstcSmcInit->stcChipConfig.u32AddrMatch, pstcSmcInit->stcChipConfig.u32AddrMask)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcSmcInit->stcTimingConfig.u8RC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WC_CYCLE(pstcSmcInit->stcTimingConfig.u8WC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_CEOE_CYCLE(pstcSmcInit->stcTimingConfig.u8CEOE)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WP_CYCLE(pstcSmcInit->stcTimingConfig.u8WP)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_TR_CYCLE(pstcSmcInit->stcTimingConfig.u8TR)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_ADV_CYCLE(pstcSmcInit->stcTimingConfig.u8ADV)); + + u32TMCR = (((uint32_t)pstcSmcInit->stcTimingConfig.u8RC << SMC_TMCR_T_RC_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8WC << SMC_TMCR_T_WC_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8CEOE << SMC_TMCR_T_CEOE_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8WP << SMC_TMCR_T_WP_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8TR << SMC_TMCR_T_TR_POS) | \ + ((uint32_t)pstcSmcInit->stcTimingConfig.u8ADV << SMC_TMCR_T_ADV_POS)); + u32CPCR = (pstcSmcInit->stcChipConfig.u32ReadMode | \ + pstcSmcInit->stcChipConfig.u32WriteMode | \ + pstcSmcInit->stcChipConfig.u32MemoryWidth | \ + pstcSmcInit->stcChipConfig.u32BAA | \ + pstcSmcInit->stcChipConfig.u32ADV | \ + pstcSmcInit->stcChipConfig.u32BLS); + WRITE_REG32(CM_SMC->TMCR, u32TMCR); /* Set SMC timing.*/ + WRITE_REG32(CM_SMC->CPCR, u32CPCR); /* Set SMC chip configuration.*/ + + /* Set chip selection address match/mask space for SMC.*/ + MODIFY_REG32(CM_SMC->CSCR0, SMC_CSCR0_ADDMSKx(u32Chip), \ + (pstcSmcInit->stcChipConfig.u32AddrMask << SMC_CSCR0_ADDMSKx_POS(u32Chip))); + MODIFY_REG32(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip), \ + (pstcSmcInit->stcChipConfig.u32AddrMatch << SMC_CSCR1_ADDMATx_POS(u32Chip))); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize EXMC_SMC function. + * @param None + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first. + */ +int32_t EXMC_SMC_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + /* Disable SMC */ + CLR_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN); + + /* Reset SMC */ + WRITE_REG32(bCM_RMU->FRST3_b.SMC, 0UL); + + /* Ensure reset procedure is completed */ + while (READ_REG32(bCM_RMU->FRST3_b.SMC) != 1UL) { + u8TimeOut++; + if (u8TimeOut > EXMC_SMC_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Enable/Disable SMC. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_SMC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN); + } else { + CLR_REG32_BIT(CM_PERIC->SMC_ENAR, PERIC_SMC_ENAR_SMCEN); + } +} + +/** + * @brief Enable or disable SMC pin mux. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_SMC->BACR, SMC_BACR_MUXMD); + } else { + CLR_REG32_BIT(CM_SMC->BACR, SMC_BACR_MUXMD); + } +} + +/** + * @brief Set SMC sample clock. + * @param [in] u32SampleClock Sample clock + * This parameter can be one of the macros group @ref EXMC_SMC_Command + * @arg EXMC_SMC_SAMPLE_CLK_INTERNCLK: Internal EXCLK + * @arg EXMC_SMC_SAMPLE_CLK_INTERNCLK_INVT: Invert internal EXCLK + * @arg EXMC_SMC_SAMPLE_CLK_EXTCLK: External clock from EXMC_CLK port + * @retval None + */ +void EXMC_SMC_SetSampleClock(uint32_t u32SampleClock) +{ + DDL_ASSERT(IS_EXMC_SMC_SAMPLE_CLK(u32SampleClock)); + + MODIFY_REG32(CM_SMC->BACR, SMC_BACR_CKSEL, u32SampleClock); +} + +/** + * @brief Set SMC refresh period value + * @param [in] u8PeriodVal The SMC refresh period value + * @arg This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F + * @retval None + */ +void EXMC_SMC_SetRefreshPeriod(uint8_t u8PeriodVal) +{ + DDL_ASSERT(IS_EXMC_SMC_REFRESH_PERIOD(u8PeriodVal)); + + WRITE_REG32(CM_SMC->RFTR, u8PeriodVal); +} + +/** + * @brief Set EXMC_SMC command. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @param [in] u32Cmd The command. + * This parameter can be one of the macros group @ref EXMC_SMC_Command + * @arg EXMC_SMC_CMD_MDREGCONFIG: Configure mode register + * @arg EXMC_SMC_CMD_UPDATEREGS: Update mode register + * @arg EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS: Configure mode register and update + * @param [in] u32CrePolarity The command. + * This parameter can be one of the macros group @ref EXMC_SMC_CRE_Polarity + * @arg EXMC_SMC_CRE_POLARITY_LOW: CRE is LOW + * @arg EXMC_SMC_CRE_POLARITY_HIGH: CRE is HIGH when ModeReg write occurs + * @param [in] u32Addr The address parameter is valid when CMD type is MdRegConfig or MdRegConfig + * and UpdateRegs only. + * @retval None + */ +void EXMC_SMC_SetCommand(uint32_t u32Chip, uint32_t u32Cmd, uint32_t u32CrePolarity, uint32_t u32Addr) +{ + uint32_t u32SmcCmdr; + + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_SMC_CMD(u32Cmd)); + DDL_ASSERT(IS_EXMC_SMC_CRE_POLARITY(u32CrePolarity)); + DDL_ASSERT(IS_EXMC_SMC_CMD_ADDR(u32Addr)); + + /* Set SMC_CMDR register for SMC.*/ + u32SmcCmdr = (u32Addr | u32CrePolarity | u32Cmd | (u32Chip << SMC_CMDR_CMDCHIP_POS)); + WRITE_REG32(CM_SMC->CMDR, u32SmcCmdr); +} + +/** + * @brief Get the start address of the specified SMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @retval The start address of the specified SMC chip. + */ +uint32_t EXMC_SMC_GetChipStartAddr(uint32_t u32Chip) +{ + uint32_t u32Match; + + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + u32Match = READ_REG32_BIT(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) >> SMC_CSCR1_ADDMATx_POS(u32Chip); + return (u32Match << 24U); +} + +/** + * @brief Get the end address of the specified SMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @retval The end address of the specified SMC chip + */ +uint32_t EXMC_SMC_GetChipEndAddr(uint32_t u32Chip) +{ + uint32_t u32Mask; + uint32_t u32Match; + + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + u32Mask = (READ_REG32_BIT(CM_SMC->CSCR0, SMC_CSCR0_ADDMSKx(u32Chip)) >> SMC_CSCR0_ADDMSKx_POS(u32Chip)); + u32Match = (READ_REG32_BIT(CM_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) >> SMC_CSCR1_ADDMATx_POS(u32Chip)); + + return (~((u32Match ^ u32Mask) << 24U)); +} + +/** + * @brief Get SMC chip configure. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @param [in] pstcChipConfig Pointer to a @ref stc_exmc_smc_chip_config_t structure. + * @retval int32_t: + * - LL_OK: Get successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcChipConfig value is NULL. + */ +int32_t EXMC_SMC_GetChipConfig(uint32_t u32Chip, stc_exmc_smc_chip_config_t *pstcChipConfig) +{ + __IO uint32_t *SMC_CPSRx; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcChipConfig) { + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + SMC_CPSRx = EXMC_SMC_CPSRx(u32Chip); + pstcChipConfig->u32ReadMode = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_RSYN); + pstcChipConfig->u32WriteMode = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_WSYN); + pstcChipConfig->u32MemoryWidth = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_MW); + pstcChipConfig->u32BAA = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_BAAS); + pstcChipConfig->u32ADV = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADVS); + pstcChipConfig->u32BLS = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_BLSS); + pstcChipConfig->u32AddrMask = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADDMSK) >> SMC_CPSR_ADDMSK_POS; + pstcChipConfig->u32AddrMatch = READ_REG32_BIT(*SMC_CPSRx, SMC_CPSR_ADDMAT) >> SMC_CPSR_ADDMAT_POS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Get SMC timing configure. + * @param [in] u32Chip The chip number. + * This parameter can be one of the macros group @ref EXMC_SMC_Chip + * @param [in] pstcTimingConfig Pointer to a @ref stc_exmc_smc_timing_config_t structure. + * @retval int32_t: + * - LL_OK: Get successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTimingConfig value is NULL. + */ +int32_t EXMC_SMC_GetTimingConfig(uint32_t u32Chip, stc_exmc_smc_timing_config_t *pstcTimingConfig) +{ + __IO uint32_t *SMC_TMSRx; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTimingConfig) { + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + SMC_TMSRx = EXMC_SMC_TMSRx(u32Chip); + pstcTimingConfig->u8RC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_RC) >> SMC_TMCR_T_RC_POS); + pstcTimingConfig->u8WC = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_WC) >> SMC_TMCR_T_WC_POS); + pstcTimingConfig->u8CEOE = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_CEOE) >> SMC_TMCR_T_CEOE_POS); + pstcTimingConfig->u8WP = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_WP) >> SMC_TMCR_T_WP_POS); + pstcTimingConfig->u8TR = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_TR) >> SMC_TMCR_T_TR_POS); + pstcTimingConfig->u8ADV = (uint8_t)(READ_REG32_BIT(*SMC_TMSRx, SMC_TMCR_T_ADV) >> SMC_TMCR_T_ADV_POS); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SMC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c new file mode 100644 index 0000000000..a88b4cec10 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_spi.c @@ -0,0 +1,1148 @@ +/** + ******************************************************************************* + * @file hc32_ll_spi.c + * @brief This file provides firmware functions to manage the Serial Peripheral + * Interface(SPI). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-12-15 CDT Modify some assert + Rename some API SPI_xxxConfig as SPI_Setxxx + Add Send restriction in SPI_TxRx function + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_spi.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SPI SPI + * @brief Serial Peripheral Interface Driver Library + * @{ + */ + +#if (LL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Macros SPI Local Macros + * @{ + */ +#define SPI_CFG1_DEFAULT (0x00000010UL) +#define SPI_CFG2_DEFAULT (0x00000F1DUL) + +#define SPI_SS0_VALID_CFG (0UL) +#define SPI_SS1_VALID_CFG (SPI_CFG2_SSA_0) +#define SPI_SS2_VALID_CFG (SPI_CFG2_SSA_1) +#define SPI_SS3_VALID_CFG (SPI_CFG2_SSA_0 | SPI_CFG2_SSA_1) + +#define SPI_SR_DEFAULT (0x00000020UL) + +#define SPI_RMU_TIMEOUT (100U) + +/** + * @defgroup SPI_Check_Parameters_Validity SPI Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for SPI peripheral */ +#define IS_VALID_SPI_UNIT(x) \ +( ((x) == CM_SPI1) || \ + ((x) == CM_SPI2) || \ + ((x) == CM_SPI3)) + +/*! Parameter valid check for SPI wire mode */ +#define IS_SPI_WIRE_MD(x) \ +( ((x) == SPI_4_WIRE) || \ + ((x) == SPI_3_WIRE)) + +/*! Parameter valid check for SPI transfer mode */ +#define IS_SPI_TRANS_MD(x) \ +( ((x) == SPI_FULL_DUPLEX) || \ + ((x) == SPI_SEND_ONLY)) + +/*! Parameter valid check for SPI master slave mode */ +#define IS_SPI_MASTER_SLAVE(x) \ +( ((x) == SPI_SLAVE) || \ + ((x) == SPI_MASTER)) + +/*! Parameter valid check for SPI loopback mode */ +#define IS_SPI_SPLPBK(x) \ +( ((x) == SPI_LOOPBACK_INVD) || \ + ((x) == SPI_LOOPBACK_MOSI_INVT) || \ + ((x) == SPI_LOOPBACK_MOSI)) + +/*! Parameter valid check for SPI communication suspend function status */ +#define IS_SPI_SUSPD_MD_STAT(x) \ +( ((x) == SPI_COM_SUSP_FUNC_OFF) || \ + ((x) == SPI_COM_SUSP_FUNC_ON)) + +/*! Parameter valid check for SPI data frame level */ +#define IS_SPI_DATA_FRAME(x) \ +( ((x) == SPI_1_FRAME) || \ + ((x) == SPI_2_FRAME) || \ + ((x) == SPI_3_FRAME) || \ + ((x) == SPI_4_FRAME)) + +/*! Parameter valid check for SPI fault detect function status */ +#define IS_SPI_MD_FAULT_DETECT_CMD(x) \ +( ((x) == SPI_MD_FAULT_DETECT_DISABLE) || \ + ((x) == SPI_MD_FAULT_DETECT_ENABLE)) + +/*! Parameter valid check for SPI parity check mode */ +#define IS_SPI_PARITY_CHECK(x) \ +( ((x) == SPI_PARITY_INVD) || \ + ((x) == SPI_PARITY_EVEN) || \ + ((x) == SPI_PARITY_ODD)) + +/*! Parameter valid check for SPI interval time delay */ +#define IS_SPI_INTERVAL_DELAY(x) \ +( ((x) == SPI_INTERVAL_TIME_1SCK) || \ + ((x) == SPI_INTERVAL_TIME_2SCK) || \ + ((x) == SPI_INTERVAL_TIME_3SCK) || \ + ((x) == SPI_INTERVAL_TIME_4SCK) || \ + ((x) == SPI_INTERVAL_TIME_5SCK) || \ + ((x) == SPI_INTERVAL_TIME_6SCK) || \ + ((x) == SPI_INTERVAL_TIME_7SCK) || \ + ((x) == SPI_INTERVAL_TIME_8SCK)) + +/*! Parameter valid check for SPI release time delay */ +#define IS_SPI_RELEASE_DELAY(x) \ +( ((x) == SPI_RELEASE_TIME_1SCK) || \ + ((x) == SPI_RELEASE_TIME_2SCK) || \ + ((x) == SPI_RELEASE_TIME_3SCK) || \ + ((x) == SPI_RELEASE_TIME_4SCK) || \ + ((x) == SPI_RELEASE_TIME_5SCK) || \ + ((x) == SPI_RELEASE_TIME_6SCK) || \ + ((x) == SPI_RELEASE_TIME_7SCK) || \ + ((x) == SPI_RELEASE_TIME_8SCK)) + +/*! Parameter valid check for SPI Setup time delay delay */ +#define IS_SPI_SETUP_DELAY(x) \ +( ((x) == SPI_SETUP_TIME_1SCK) || \ + ((x) == SPI_SETUP_TIME_2SCK) || \ + ((x) == SPI_SETUP_TIME_3SCK) || \ + ((x) == SPI_SETUP_TIME_4SCK) || \ + ((x) == SPI_SETUP_TIME_5SCK) || \ + ((x) == SPI_SETUP_TIME_6SCK) || \ + ((x) == SPI_SETUP_TIME_7SCK) || \ + ((x) == SPI_SETUP_TIME_8SCK)) + +/*! Parameter valid check for SPI read data register target buffer */ +#define IS_SPI_RD_TARGET_BUFF(x) \ +( ((x) == SPI_RD_TARGET_RD_BUF) || \ + ((x) == SPI_RD_TARGET_WR_BUF)) + +/*! Parameter valid check for SPI mode */ +#define IS_SPI_SPI_MD(x) \ +( ((x) == SPI_MD_0) || \ + ((x) == SPI_MD_1) || \ + ((x) == SPI_MD_2) || \ + ((x) == SPI_MD_3)) + +/*! Parameter valid check for SPI SCK Polarity */ +#define IS_SPI_SCK_POLARITY(x) \ +( ((x) == SPI_SCK_POLARITY_LOW) || \ + ((x) == SPI_SCK_POLARITY_HIGH)) + +/*! Parameter valid check for SPI SCK Phase */ +#define IS_SPI_SCK_PHASE(x) \ +( ((x) == SPI_SCK_PHASE_ODD_EDGE_SAMPLE) || \ + ((x) == SPI_SCK_PHASE_EVEN_EDGE_SAMPLE)) + +/*! Parameter valid check for SPI SS signal */ +#define IS_SPI_SS_PIN(x) \ +( ((x) == SPI_PIN_SS0) || \ + ((x) == SPI_PIN_SS1) || \ + ((x) == SPI_PIN_SS2) || \ + ((x) == SPI_PIN_SS3)) + +/*! Parameter valid check for SPI SS valid level */ +#define IS_SPI_SS_VALID_LVL(x) \ +( ((x) == SPI_SS_VALID_LVL_HIGH) || \ + ((x) == SPI_SS_VALID_LVL_LOW)) + +/*! Parameter valid check for SPI baudrate prescaler */ +#define IS_SPI_CLK_DIV(x) \ +( ((x) == SPI_BR_CLK_DIV2) || \ + ((x) == SPI_BR_CLK_DIV4) || \ + ((x) == SPI_BR_CLK_DIV6) || \ + ((x) == SPI_BR_CLK_DIV8) || \ + ((x) == SPI_BR_CLK_DIV10) || \ + ((x) == SPI_BR_CLK_DIV12) || \ + ((x) == SPI_BR_CLK_DIV14) || \ + ((x) == SPI_BR_CLK_DIV16) || \ + ((x) == SPI_BR_CLK_DIV18) || \ + ((x) == SPI_BR_CLK_DIV20) || \ + ((x) == SPI_BR_CLK_DIV22) || \ + ((x) == SPI_BR_CLK_DIV24) || \ + ((x) == SPI_BR_CLK_DIV26) || \ + ((x) == SPI_BR_CLK_DIV28) || \ + ((x) == SPI_BR_CLK_DIV30) || \ + ((x) == SPI_BR_CLK_DIV32) || \ + ((x) == SPI_BR_CLK_DIV36) || \ + ((x) == SPI_BR_CLK_DIV40) || \ + ((x) == SPI_BR_CLK_DIV44) || \ + ((x) == SPI_BR_CLK_DIV48) || \ + ((x) == SPI_BR_CLK_DIV52) || \ + ((x) == SPI_BR_CLK_DIV56) || \ + ((x) == SPI_BR_CLK_DIV60) || \ + ((x) == SPI_BR_CLK_DIV64) || \ + ((x) == SPI_BR_CLK_DIV72) || \ + ((x) == SPI_BR_CLK_DIV80) || \ + ((x) == SPI_BR_CLK_DIV88) || \ + ((x) == SPI_BR_CLK_DIV96) || \ + ((x) == SPI_BR_CLK_DIV104) || \ + ((x) == SPI_BR_CLK_DIV112) || \ + ((x) == SPI_BR_CLK_DIV120) || \ + ((x) == SPI_BR_CLK_DIV128) || \ + ((x) == SPI_BR_CLK_DIV144) || \ + ((x) == SPI_BR_CLK_DIV160) || \ + ((x) == SPI_BR_CLK_DIV176) || \ + ((x) == SPI_BR_CLK_DIV192) || \ + ((x) == SPI_BR_CLK_DIV208) || \ + ((x) == SPI_BR_CLK_DIV224) || \ + ((x) == SPI_BR_CLK_DIV240) || \ + ((x) == SPI_BR_CLK_DIV256)) + +/*! Parameter valid check for SPI data bits */ +#define IS_SPI_DATA_SIZE(x) \ +( ((x) == SPI_DATA_SIZE_4BIT) || \ + ((x) == SPI_DATA_SIZE_5BIT) || \ + ((x) == SPI_DATA_SIZE_6BIT) || \ + ((x) == SPI_DATA_SIZE_7BIT) || \ + ((x) == SPI_DATA_SIZE_8BIT) || \ + ((x) == SPI_DATA_SIZE_9BIT) || \ + ((x) == SPI_DATA_SIZE_10BIT) || \ + ((x) == SPI_DATA_SIZE_11BIT) || \ + ((x) == SPI_DATA_SIZE_12BIT) || \ + ((x) == SPI_DATA_SIZE_13BIT) || \ + ((x) == SPI_DATA_SIZE_14BIT) || \ + ((x) == SPI_DATA_SIZE_15BIT) || \ + ((x) == SPI_DATA_SIZE_16BIT) || \ + ((x) == SPI_DATA_SIZE_20BIT) || \ + ((x) == SPI_DATA_SIZE_24BIT) || \ + ((x) == SPI_DATA_SIZE_32BIT)) + +/*! Parameter valid check for SPI LSB MSB mode */ +#define IS_SPI_FIRST_BIT(x) \ +( ((x) == SPI_FIRST_MSB) || \ + ((x) == SPI_FIRST_LSB)) + +/*! Parameter valid check for SPI Communication mode */ +#define IS_SPI_COMM_MD(x) \ +( ((x) == SPI_COMM_MD_NORMAL) || \ + ((x) == SPI_COMM_MD_CONT)) + +/*! Parameter valid check for interrupt flag */ +#define IS_SPI_INT(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_INT_ALL) == SPI_INT_ALL)) + +/*! Parameter valid check for SPI status flag */ +#define IS_SPI_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_ALL) == SPI_FLAG_ALL)) + +/*! Parameter valid check for SPI status flag for clear */ +#define IS_SPI_CLR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_FLAG_CLR_ALL) == SPI_FLAG_CLR_ALL)) + +/*! Parameter valid check for SPI command*/ +#define IS_SPI_CMD_ALLOWED(x) \ +( (READ_REG32_BIT(SPIx->SR, SPI_FLAG_MD_FAULT) == 0UL) || \ + ((x) == DISABLE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Func SPI Local Functions + * @{ + */ + +/** + * @brief SPI check status. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32FlagMask Bit mask of status flag. + * @param [in] u32Value Valid value of the status. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_WaitStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32FlagMask, uint32_t u32Value, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + + while (READ_REG32_BIT(SPIx->SR, u32FlagMask) != u32Value) { + if (u32Timeout == 0UL) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Timeout--; + } + return i32Ret; +} + +/** + * @brief SPI master release delay. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32TransMode SPI transfer mode @ref SPI_Trans_Mode_Define + * @retval None + * @note The delay while CPHA = 0 and full duplex mode in continue communication mode(1 SCK). + * @note The delay while send only mode in continue communication mode(x SCK). + */ +static void SPI_MasterReleaseDelay(CM_SPI_TypeDef *SPIx, uint32_t u32TransMode) +{ + uint32_t u32BusFreq, u32SpiDiv, u32DataBits; + uint32_t u32Speed, u32Temp; + uint32_t u32DelayTime = 1U; + + u32BusFreq = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + u32SpiDiv = (((READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_CLKDIV) >> SPI_CFG1_CLKDIV_POS) + 1U) << 1U); + u32SpiDiv *= (1UL << (READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_MBR) >> SPI_CFG2_MBR_POS)); + u32Speed = u32BusFreq / u32SpiDiv; + if (SPI_FULL_DUPLEX == u32TransMode) { + /* Communication speed below 1Mhz */ + if ((u32Speed < 1000000UL) && (u32Speed > 0U)) { + u32DelayTime = 1000000UL / u32Speed; + if (0U != (1000000UL % u32Speed)) { + u32DelayTime += 1U; + } + } + } else { + if (SPI_CFG2_MSSIE == READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE)) { + u32Temp = (READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI) >> SPI_CFG1_MSSI_POS); + } else { + u32Temp = 0U; + } + if (0U == READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA)) { + u32Temp += 1U; + } + u32DataBits = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + if (u32DataBits <= SPI_DATA_SIZE_16BIT) { + u32Temp += (u32DataBits >> SPI_CFG2_DSIZE_POS) + 4U; + } else if (u32DataBits == SPI_DATA_SIZE_20BIT) { + u32Temp += 20U; + } else if (u32DataBits == SPI_DATA_SIZE_24BIT) { + u32Temp += 24U; + } else { + u32Temp += 32U; + } + /* Total wait time below 1us */ + u32Speed = u32Speed / u32Temp; + if ((u32Speed < 1000000UL) && (u32Speed > 0U)) { + u32DelayTime = 1000000UL / u32Speed; + if (0U != (1000000UL % u32Speed)) { + u32DelayTime += 1U; + } + } + } + DDL_DelayUS(u32DelayTime); +} + +/** + * @brief SPI transmit and receive data in full duplex mode. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * @param [in] u32Len The length of the data in byte or half word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + */ +static int32_t SPI_TxRx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32BitSize; + __IO uint32_t u32TxCnt = 0U, u32RxCnt = 0U; + __IO uint32_t u32Count = 0U; + int32_t i32Ret = LL_OK; + uint32_t u32Tmp; + __UNUSED __IO uint32_t u32Read; + __IO uint32_t u32TxAllow = 1U; + uint32_t u32MSMode; + __IO uint32_t u32FrameCnt; + uint32_t u32FrameNum = READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_FTHLV) + 1UL; + DDL_ASSERT(0UL == (u32Len % u32FrameNum)); + + u32MSMode = READ_REG32_BIT(SPIx->CR, SPI_CR_MSTR); + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + while (u32RxCnt < u32Len) { + /* Tx data */ + if (u32TxCnt < u32Len) { + /* Wait TX buffer empty. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, 0U); + if ((i32Ret == LL_OK) && (((u32MSMode == SPI_MASTER) && (u32TxAllow == 1U)) || (u32MSMode == SPI_SLAVE))) { + if (pvTxBuf != NULL) { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32TxCnt]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32FrameCnt++; + u32TxCnt++; + } + } else { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + WRITE_REG32(SPIx->DR, 0xFFFFFFFFUL); + u32FrameCnt++; + u32TxCnt++; + } + } + u32TxAllow = 0U; + } + } + + /* RX data */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_RX_BUF_FULL, SPI_FLAG_RX_BUF_FULL, 0U); + if (i32Ret == LL_OK) { + if (pvRxBuf != NULL) { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + u32Tmp = READ_REG32(SPIx->DR); + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + ((uint8_t *)pvRxBuf)[u32RxCnt] = (uint8_t)u32Tmp; + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + ((uint16_t *)pvRxBuf)[u32RxCnt] = (uint16_t)u32Tmp; + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + ((uint32_t *)pvRxBuf)[u32RxCnt] = (uint32_t)u32Tmp; + } + u32FrameCnt++; + u32RxCnt++; + } + } else { + /* Dummy read */ + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + u32Read = READ_REG32(SPIx->DR); + u32FrameCnt++; + u32RxCnt++; + } + } + u32TxAllow = 1U; + u32Count = 0U; + } + + /* check timeout */ + if (u32Count > u32Timeout) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count++; + } + + if ((SPI_MASTER == READ_REG32_BIT(SPIx->CR, SPI_CR_MSTR)) && (i32Ret == LL_OK)) { + if (SPI_COMM_MD_NORMAL == READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_CTMDS)) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } else { + if (0U == READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA)) { + SPI_MasterReleaseDelay(SPIx, SPI_FULL_DUPLEX); + } + } + } + + return i32Ret; +} + +/** + * @brief SPI send data only. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32Len The length of the data in byte or half word or word. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: SPI transmit timeout. + */ +static int32_t SPI_Tx(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + __IO uint32_t u32TxCnt = 0U; + uint32_t u32BitSize; + int32_t i32Ret = LL_OK; + __IO uint32_t u32FrameCnt; + uint32_t u32FrameNum = READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_FTHLV) + 1UL; + DDL_ASSERT(0UL == (u32Len % u32FrameNum)); + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + while (u32TxCnt < u32Len) { + u32FrameCnt = 0UL; + while (u32FrameCnt < u32FrameNum) { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32TxCnt]); + } else if (u32BitSize <= SPI_DATA_SIZE_16BIT) { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } else { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32FrameCnt++; + u32TxCnt++; + } + /* Wait TX buffer empty. */ + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_TX_BUF_EMPTY, SPI_FLAG_TX_BUF_EMPTY, u32Timeout); + if (i32Ret != LL_OK) { + break; + } + } + + if ((SPI_MASTER == READ_REG32_BIT(SPIx->CR, SPI_CR_MSTR)) && (i32Ret == LL_OK)) { + if (SPI_COMM_MD_NORMAL == READ_REG32_BIT(SPIx->CFG1, SPI_CFG1_CTMDS)) { + i32Ret = SPI_WaitStatus(SPIx, SPI_FLAG_IDLE, 0UL, u32Timeout); + } else { + SPI_MasterReleaseDelay(SPIx, SPI_SEND_ONLY); + } + } + + return i32Ret; +} + +/** + * @} + */ + +/** + * @defgroup SPI_Global_Functions SPI Global Functions + * @{ + */ + +/** + * @brief Initializes the SPI peripheral according to the specified parameters + * in the structure stc_spi_init. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that contains + * the configuration information for the SPI. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL or configuration parameter error. + * @note -In the 3-Wire slave mode and CHPA = 0, the function needs to cooperate with other processes to communicate properly. + * @note -The parameter u32BaudRatePrescaler is invalid while slave mode + */ +int32_t SPI_Init(CM_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcSpiInit) { + DDL_ASSERT(IS_SPI_WIRE_MD(pstcSpiInit->u32WireMode)); + DDL_ASSERT(IS_SPI_TRANS_MD(pstcSpiInit->u32TransMode)); + DDL_ASSERT(IS_SPI_MASTER_SLAVE(pstcSpiInit->u32MasterSlave)); + DDL_ASSERT(IS_SPI_MD_FAULT_DETECT_CMD(pstcSpiInit->u32ModeFaultDetect)); + DDL_ASSERT(IS_SPI_PARITY_CHECK(pstcSpiInit->u32Parity)); + DDL_ASSERT(IS_SPI_SPI_MD(pstcSpiInit->u32SpiMode)); + DDL_ASSERT(IS_SPI_CLK_DIV(pstcSpiInit->u32BaudRatePrescaler)); + DDL_ASSERT(IS_SPI_DATA_SIZE(pstcSpiInit->u32DataBits)); + DDL_ASSERT(IS_SPI_FIRST_BIT(pstcSpiInit->u32FirstBit)); + DDL_ASSERT(IS_SPI_SUSPD_MD_STAT(pstcSpiInit->u32SuspendMode)); + DDL_ASSERT(IS_SPI_DATA_FRAME(pstcSpiInit->u32FrameLevel)); + + /* Configuration parameter check */ + if ((SPI_MASTER == pstcSpiInit->u32MasterSlave) && (SPI_MD_FAULT_DETECT_ENABLE == pstcSpiInit->u32ModeFaultDetect)) { + /* pstcSpiInit->u32ModeFaultDetect can not be SPI_MD_FAULT_DETECT_ENABLE in master mode */ + } else { + WRITE_REG32(SPIx->CR, pstcSpiInit->u32WireMode | pstcSpiInit->u32TransMode | pstcSpiInit->u32MasterSlave | \ + pstcSpiInit->u32SuspendMode | pstcSpiInit->u32ModeFaultDetect | pstcSpiInit->u32Parity); + if (SPI_MASTER == pstcSpiInit->u32MasterSlave) { + MODIFY_REG32(SPIx->CFG1, (SPI_CFG1_FTHLV | SPI_CFG1_CLKDIV), + (pstcSpiInit->u32FrameLevel | (pstcSpiInit->u32BaudRatePrescaler & SPI_CFG1_CLKDIV))); + WRITE_REG32(SPIx->CFG2, pstcSpiInit->u32SpiMode | pstcSpiInit->u32FirstBit | pstcSpiInit->u32DataBits | \ + (pstcSpiInit->u32BaudRatePrescaler & SPI_CFG2_MBR)); + } else { + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_FTHLV, pstcSpiInit->u32FrameLevel); + WRITE_REG32(SPIx->CFG2, pstcSpiInit->u32SpiMode | pstcSpiInit->u32FirstBit | pstcSpiInit->u32DataBits); + } + + i32Ret = LL_OK; + } + } + return i32Ret; +} + +/** + * @brief De-initializes the SPI peripheral. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t SPI_DeInit(CM_SPI_TypeDef *SPIx) +{ + uint32_t i; + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + __IO uint32_t *bCM_RMU_FRST1_SPIx = NULL; + const uint32_t au32SPIx[] = {CM_SPI1_BASE, CM_SPI2_BASE, CM_SPI3_BASE}; + + /* Check RMU_FRST register protect */ + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + for (i = 0UL; i < ARRAY_SZ(au32SPIx); i++) { + if ((uint32_t)SPIx == au32SPIx[i]) { + bCM_RMU_FRST1_SPIx = (__IO uint32_t *)((uint32_t)&bCM_RMU->FRST1_b.SPI1 + (i << 2)); + break; + } + } + + /* Reset SPI */ + WRITE_REG32(*bCM_RMU_FRST1_SPIx, 0UL); + + /* Ensure reset procedure is completed */ + while (READ_REG32(*bCM_RMU_FRST1_SPIx) != 1UL) { + u8TimeOut++; + if (u8TimeOut > SPI_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + return i32Ret; +} + +/** + * @brief Set a default value for the SPI initialization structure. + * @param [in] pstcSpiInit Pointer to a stc_spi_init_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcSpiInit == NULL. + */ +int32_t SPI_StructInit(stc_spi_init_t *pstcSpiInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSpiInit) { + pstcSpiInit->u32WireMode = SPI_4_WIRE; + pstcSpiInit->u32TransMode = SPI_FULL_DUPLEX; + pstcSpiInit->u32MasterSlave = SPI_MASTER; + pstcSpiInit->u32ModeFaultDetect = SPI_MD_FAULT_DETECT_DISABLE; + pstcSpiInit->u32Parity = SPI_PARITY_INVD; + pstcSpiInit->u32SpiMode = SPI_MD_0; + pstcSpiInit->u32BaudRatePrescaler = SPI_BR_CLK_DIV8; + pstcSpiInit->u32DataBits = SPI_DATA_SIZE_8BIT; + pstcSpiInit->u32FirstBit = SPI_FIRST_MSB; + pstcSpiInit->u32SuspendMode = SPI_COM_SUSP_FUNC_OFF; + pstcSpiInit->u32FrameLevel = SPI_1_FRAME; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Enable or disable SPI interrupt. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32IntType SPI interrupt type. Can be one or any + * combination of the parameter @ref SPI_Int_Type_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_IntCmd(CM_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_INT(u32IntType)); + + if (enNewState == ENABLE) { + SET_REG32_BIT(SPIx->CR, u32IntType); + } else { + CLR_REG32_BIT(SPIx->CR, u32IntType); + } +} + +/** + * @brief SPI function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SPI_Cmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_CMD_ALLOWED(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR, SPI_CR_SPE); + } else { + CLR_REG32_BIT(SPIx->CR, SPI_CR_SPE); + } +} + +/** + * @brief Write SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Data The data will be written to the data register. + * @retval None. + */ +void SPI_WriteData(CM_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + WRITE_REG32(SPIx->DR, u32Data); +} + +/** + * @brief Read SPI data register. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @retval uint32_t A 32-bit data of SPI data register. + */ +uint32_t SPI_ReadData(const CM_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return READ_REG32(SPIx->DR); +} + +/** + * @brief SPI get status flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any + * combination of the parameter of @ref SPI_State_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SPI_GetStatus(const CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + en_flag_status_t enFlag = RESET; + uint32_t u32Status; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_FLAG(u32Flag)); + + u32Status = READ_REG32(SPIx->SR); + if (SPI_FLAG_IDLE == (SPI_FLAG_IDLE & u32Flag)) { + CLR_REG32_BIT(u32Flag, SPI_FLAG_IDLE); + if (0U == (u32Status & SPI_FLAG_IDLE)) { + enFlag = SET; + } + } + if (0U != READ_REG32_BIT(u32Status, u32Flag)) { + enFlag = SET; + } + + return enFlag; +} + +/** + * @brief SPI clear state flag. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Flag SPI state flag. Can be one or any combination of the parameter below + * @arg SPI_FLAG_OVERRUN + * @arg SPI_FLAG_MD_FAULT + * @arg SPI_FLAG_PARITY_ERR + * @arg SPI_FLAG_UNDERRUN + * @retval None + */ +void SPI_ClearStatus(CM_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_CLR_FLAG(u32Flag)); + + CLR_REG32_BIT(SPIx->SR, u32Flag); +} + +/** + * @brief SPI loopback function configuration. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Mode Loopback mode. Can be one parameter @ref SPI_Loopback_Selection_Define + * @retval None + */ +void SPI_SetLoopbackMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SPLPBK(u32Mode)); + + MODIFY_REG32(SPIx->CR, SPI_CR_SPLPBK | SPI_CR_SPLPBK2, u32Mode); +} + +/** + * @brief SPI parity check error self diagnosis function enable or disable. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ + +void SPI_ParityCheckCmd(CM_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(SPIx->CR, SPI_CR_PATE); + } else { + CLR_REG32_BIT(SPIx->CR, SPI_CR_PATE); + } +} + +/** + * @brief SPI signals delay time configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that contains + * the configuration information for the SPI delay time. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL + */ +int32_t SPI_DelayTimeConfig(CM_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcDelayConfig) { + DDL_ASSERT(IS_SPI_INTERVAL_DELAY(pstcDelayConfig->u32IntervalDelay)); + DDL_ASSERT(IS_SPI_RELEASE_DELAY(pstcDelayConfig->u32ReleaseDelay)); + DDL_ASSERT(IS_SPI_SETUP_DELAY(pstcDelayConfig->u32SetupDelay)); + + /* Interval delay */ + if (SPI_INTERVAL_TIME_1SCK == pstcDelayConfig->u32IntervalDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MIDI); + } else { + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MIDI, pstcDelayConfig->u32IntervalDelay); + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + } + + /* SCK release delay */ + if (SPI_RELEASE_TIME_1SCK == pstcDelayConfig->u32ReleaseDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSDL); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSDL, pstcDelayConfig->u32ReleaseDelay); + } + + /* Setup delay */ + if (SPI_SETUP_TIME_1SCK == pstcDelayConfig->u32SetupDelay) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + CLR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSI, pstcDelayConfig->u32SetupDelay); + } + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set a default value for the SPI delay time configuration structure. + * @param [in] pstcDelayConfig Pointer to a stc_spi_delay_t structure that + * contains configuration information. + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_INVD_PARAM: pstcDelayConfig == NULL. + */ +int32_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcDelayConfig) { + pstcDelayConfig->u32IntervalDelay = SPI_INTERVAL_TIME_1SCK; + pstcDelayConfig->u32ReleaseDelay = SPI_RELEASE_TIME_1SCK; + pstcDelayConfig->u32SetupDelay = SPI_SETUP_TIME_1SCK; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the communication mode. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Mode Specify the communication mode @ref SPI_Comm_Mode_Define + * @retval None + */ +void SPI_SetCommMode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_COMM_MD(u32Mode)); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_CTMDS, u32Mode); +} + +/** + * @brief SPI SS signal valid level configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @param [in] u32SSLevel Specify the SS valid level @ref SPI_SS_Level + * @arg SPI_SS_VALID_LVL_HIGH: SS high level valid + * @arg SPI_SS_VALID_LVL_LOW: SS low level valid + * @retval None + */ +void SPI_SetSSValidLevel(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin, uint32_t u32SSLevel) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + DDL_ASSERT(IS_SPI_SS_VALID_LVL(u32SSLevel)); + + if (SPI_SS_VALID_LVL_HIGH == u32SSLevel) { + SET_REG32_BIT(SPIx->CFG1, u32SSPin); + } else { + CLR_REG32_BIT(SPIx->CFG1, u32SSPin); + } +} + +/** + * @brief Set the SPI SCK polarity. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Polarity Specify the SPI SCK polarity @ref SPI_SCK_Polarity_Define + * @retval None + */ +void SPI_SetSckPolarity(CM_SPI_TypeDef *SPIx, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SCK_POLARITY(u32Polarity)); + + if (SPI_SCK_POLARITY_LOW == u32Polarity) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPOL); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPOL); + } +} + +/** + * @brief Set the SPI SCK phase. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32Phase Specify the SPI SCK phase @ref SPI_SCK_Phase_Define + * @retval None + */ +void SPI_SetSckPhase(CM_SPI_TypeDef *SPIx, uint32_t u32Phase) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SCK_PHASE(u32Phase)); + + if (SPI_SCK_PHASE_ODD_EDGE_SAMPLE == u32Phase) { + CLR_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA); + } else { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_CPHA); + } +} + +/** + * @brief SPI valid SS signal configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @retval None + */ +void SPI_SSPinSelect(CM_SPI_TypeDef *SPIx, uint32_t u32SSPin) +{ + uint32_t u32RegConfig; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + + switch (u32SSPin) { + case SPI_PIN_SS0: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + case SPI_PIN_SS1: + u32RegConfig = SPI_SS1_VALID_CFG; + break; + case SPI_PIN_SS2: + u32RegConfig = SPI_SS2_VALID_CFG; + break; + case SPI_PIN_SS3: + u32RegConfig = SPI_SS3_VALID_CFG; + break; + default: + u32RegConfig = SPI_SS0_VALID_CFG; + break; + } + MODIFY_REG32(SPIx->CFG2, SPI_CFG2_SSA, u32RegConfig); +} + +/** + * @brief SPI read buffer configuration + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] u32ReadBuf Target buffer for read operation @ref SPI_Read_Target_Buf_Define + * @retval None + */ +void SPI_SetReadBuf(CM_SPI_TypeDef *SPIx, uint32_t u32ReadBuf) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_RD_TARGET_BUFF(u32ReadBuf)); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_SPRDTD, u32ReadBuf); +} + +/** + * @brief SPI transmit data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32TxLen The length of the data to be sent. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit timeout. + * - LL_ERR_INVD_PARAM: pvTxBuf == NULL or u32TxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -In the send only slave mode, the function needs to increase an appropriate delay after calling to ensure the + * integrity of data transmission. + */ +int32_t SPI_Trans(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLen, uint32_t u32Timeout) +{ + uint32_t u32Flags; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (u32TxLen != 0U)) { + u32Flags = READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); + if (u32Flags == SPI_SEND_ONLY) { + /* Transmit data in send only mode. */ + i32Ret = SPI_Tx(SPIx, pvTxBuf, u32TxLen, u32Timeout); + } else { + /* Transmit data in full duplex mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, NULL, u32TxLen, u32Timeout); + } + } + return i32Ret; +} + +/** + * @brief SPI receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvRxBuf The pointer to the buffer which the received data to be stored. + * @param [in] u32RxLen The length of the data to be received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or u32RxLen == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + */ +int32_t SPI_Receive(CM_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLen, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvRxBuf != NULL) && (u32RxLen != 0U)) { + /* Receives data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, NULL, pvRxBuf, u32RxLen, u32Timeout); + } + return i32Ret; +} + +/** + * @brief SPI transmit and receive data. + * @param [in] SPIx SPI unit + * @arg CM_SPIx or CM_SPI + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * If this pointer is NULL and the pvRxBuf is NOT NULL, the MOSI output high + * and the the received data will be stored in the buffer pointed by pvRxBuf. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * This for full duplex transfer. + * @param [in] u32Len The length of the data(in byte or half word) to be sent and received. + * @param [in] u32Timeout Timeout value. + * @retval int32_t: + * - LL_OK: No errors occurred + * - LL_ERR_TIMEOUT: SPI transmit and receive timeout. + * - LL_ERR_INVD_PARAM: pvRxBuf == NULL or pvRxBuf == NULL or u32Len == 0U + * @note SPI receives data while sending data. + */ +int32_t SPI_TransReceive(CM_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pvTxBuf != NULL) && (pvRxBuf != NULL) && (u32Len != 0U)) { + /* Transmit and receive data in full duplex master mode. */ + i32Ret = SPI_TxRx(SPIx, pvTxBuf, pvRxBuf, u32Len, u32Timeout); + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c new file mode 100644 index 0000000000..27fc8ae98b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_sram.c @@ -0,0 +1,359 @@ +/** + ******************************************************************************* + * @file hc32_ll_sram.c + * @brief This file provides firmware functions to manage the SRAM. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT API fixed: SRAM_ClearStatus() + 2023-12-15 CDT Refine SRAM_SetEccMode, and refine SRAM_SetErrorMode() as SRAM_SetExceptionType + Remove wait cycle relevant code + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_sram.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SRAM SRAM + * @brief SRAM Driver Library + * @{ + */ + +#if (LL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Local_Macros SRAM Local Macros + * @{ + */ + +/** + * @defgroup SRAM_Configuration_Bits_Mask SRAM Configuration Bits Mask + * @{ + */ +#define SRAM_CYCLE_MASK (0x00000007UL) +/** + * @} + */ + +#define SRAM_EI_BIT_MASK (0x7FFFFFFFFFUL) + +/** + * @defgroup SRAM_Ecc_Mode_Mask SRAM ecc mode mask + * @{ + */ +#define SRAM_ECC_MD_MASK (SRAMC_CKCR_ECCMOD | SRAMC_CKCR_BECCMOD) +/** + * @} + */ + +/** + * @defgroup SRAM_Exception_Type_Mask SRAM exception type mask + * @{ + */ +#define SRAM_EXP_TYPE_MASK (SRAMC_CKCR_ECCOAD | SRAMC_CKCR_BECCOAD | SRAMC_CKCR_PYOAD) +/** + * @} + */ + +/** + * @defgroup SRAM_Check_Parameters_Validity SRAM check parameters validity + * @{ + */ +#define IS_SRAM_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +/* Parameter valid check for SRAM wait cycle */ +#define IS_SRAM_WAIT_CYCLE(x) ((x) <= SRAM_WAIT_CYCLE7) + +/* Parameter valid check for SRAM selection */ +#define IS_SRAM_SEL(x) IS_SRAM_BIT_MASK(x, SRAM_SRAM_ALL) + +/* Parameter valid check for SRAM ECC SRAM */ +#define IS_SRAM_ECC_SRAM(x) IS_SRAM_BIT_MASK(x, SRAM_ECC_SRAM_ALL) + +/* Parameter valid check for SRAM ECC SRAM */ +#define IS_SRAM_CHECK_SRAM(x) IS_SRAM_BIT_MASK(x, SRAM_CHECK_SRAM_ALL) + +/* Parameter valid check for SRAM flag */ +#define IS_SRAM_FLAG(x) IS_SRAM_BIT_MASK(x, SRAM_FLAG_ALL) + +/* Check SRAM CKPR register lock status. */ +#define IS_SRAM_CKPR_UNLOCK() (CM_SRAMC->CKPR == SRAM_REG_UNLOCK_KEY) + +/* Parameter valid check for SRAM exception type mode */ +#define IS_SRAM_EXP_TYPE(x) \ +( ((x) == SRAM_EXP_TYPE_NMI) || \ + ((x) == SRAM_EXP_TYPE_RST)) + +/* Parameter valid check for SRAM ECC mode */ +#define IS_SRAM_ECC_MD(x) \ +( (((x) | SRAM_ECC_MD_MASK) == 0xFFFFFFFFUL) || \ + (((x) | SRAM_ECC_MD_MASK) == SRAM_ECC_MD_MASK)) + +/* Parameter valid check for SRAM error inject bit */ +#define IS_SRAM_EI_BIT(x) \ +( ((x) != 0x00UL) && \ + (((x) | SRAM_EI_BIT_MASK) == SRAM_EI_BIT_MASK)) + +/* Parameter valid check for SRAM ECC SRAM */ +#define IS_SRAM_ECC_SRAM_ONLY(x) \ +( ((x) == SRAM_ECC_SRAM0) || \ + ((x) == SRAM_ECC_SRAMB)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Functions SRAM Global Functions + * @{ + */ + +/** + * @brief Initializes SRAM. + * @param None + * @retval None + */ +void SRAM_Init(void) +{ + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief De-initializes SRAM. RESET the registers of SRAM. + * @param None + * @retval None + * @note Call SRAM_REG_Unlock to unlock registers WTCR and CKCR first. + */ +void SRAM_DeInit(void) +{ + /* Call SRAM_REG_Unlock to unlock register WTCR and CKCR. */ + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + WRITE_REG32(CM_SRAMC->CKCR, 0UL); + SET_REG32_BIT(CM_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief Specifies ECC mode. + * @param [in] u32EccSram The ECC SRAM. + * This parameter can be any combination of @ref SRAM_ECC_SRAM + * @param [in] u32EccMode The ECC mode. + * This parameter can be any combination of @ref SRAM_ECC_Mode, but only choose + * one value of SRAM_SRAM0_ECC_xx and SRAM_SRAMB_ECC_xx + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + * The sram of u32EccMode should be the same with the sram of u32EccSram. + */ +void SRAM_SetEccMode(uint32_t u32EccSram, uint32_t u32EccMode) +{ + uint32_t u32Mask = 0UL; + uint32_t u32Pos = 0UL; + + DDL_ASSERT(IS_SRAM_ECC_SRAM(u32EccSram)); + DDL_ASSERT(IS_SRAM_ECC_MD(u32EccMode)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + while (0UL != u32EccSram) { + if (1UL == (u32EccSram & 0x01UL)) { + u32Mask |= (SRAMC_CKCR_ECCMOD << u32Pos); + } + u32EccSram >>= 1UL; + u32Pos += 2UL; + } + + MODIFY_REG32(CM_SRAMC->CKCR, u32Mask, u32EccMode); +} + +/** + * @brief Specifies the exception type while the choosen sram check error occurred. + * @param [in] u32CheckSram The check SRAM. + * This parameter can be any combination of @ref SRAM_Check_SRAM + * @param [in] u32ExceptionType The operation after check error occurred. + * This parameter can be a value of @ref SRAM_Exception_Type + * @retval None + * @note Call SRAM_REG_Unlock to unlock register CKCR first. + */ +void SRAM_SetExceptionType(uint32_t u32CheckSram, uint32_t u32ExceptionType) +{ + DDL_ASSERT(IS_SRAM_CHECK_SRAM(u32CheckSram)); + DDL_ASSERT(IS_SRAM_EXP_TYPE(u32ExceptionType)); + DDL_ASSERT(IS_SRAM_CKPR_UNLOCK()); + + if (SRAM_EXP_TYPE_RST == u32ExceptionType) { + SET_REG32_BIT(CM_SRAMC->CKCR, u32CheckSram); + } else { + CLR_REG32_BIT(CM_SRAMC->CKCR, u32CheckSram); + } +} + +/** + * @brief Get the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be a value of @ref SRAM_Err_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + if (READ_REG32_BIT(CM_SRAMC->CKSR, u32Flag) != 0U) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be values of @ref SRAM_Err_Status_Flag + * @retval None + */ +void SRAM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_SRAM_FLAG(u32Flag)); + WRITE_REG32(CM_SRAMC->CKSR, u32Flag); +} + +/** + * @brief Enable or disable error injection. + * @param [in] u32EccSram The SRAM selection. + * This parameter can be any combination of @ref SRAM_ECC_SRAM + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SRAM_ErrorInjectCmd(uint32_t u32EccSram, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_SRAM_ECC_SRAM(u32EccSram)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if ((u32EccSram & SRAM_ECC_SRAM0) != 0U) { + WRITE_REG32(CM_SRAMC->SRAM0_EIEN, enNewState); + } + if ((u32EccSram & SRAM_ECC_SRAMB) != 0U) { + WRITE_REG32(CM_SRAMC->SRAMB_EIEN, enNewState); + } +} + +/** + * @brief Enable or disable error injection bit of SRAM_ECC_SRAM. + * @param [in] u32EccSram The SRAM selection. + * This parameter can be any combination of @ref SRAM_ECC_SRAM + * @param [in] u64BitSel Bit selection. Only bit0~bit38 valid. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void SRAM_ErrorInjectBitCmd(uint32_t u32EccSram, uint64_t u64BitSel, en_functional_state_t enNewState) +{ + uint32_t u32Eibit0 = (uint32_t)(u64BitSel & SRAMC_SRAM0_EIBIT0); + uint32_t u32Eibit1 = (uint32_t)((u64BitSel >> 32U) & SRAMC_SRAM0_EIBIT1_EIBIT); + + DDL_ASSERT(IS_SRAM_ECC_SRAM(u32EccSram)); + DDL_ASSERT(IS_SRAM_EI_BIT(u64BitSel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + if ((u32EccSram & SRAM_ECC_SRAM0) != 0U) { + SET_REG32_BIT(CM_SRAMC->SRAM0_EIBIT0, u32Eibit0); + SET_REG32_BIT(CM_SRAMC->SRAM0_EIBIT1, u32Eibit1); + } + if ((u32EccSram & SRAM_ECC_SRAMB) != 0U) { + SET_REG32_BIT(CM_SRAMC->SRAMB_EIBIT0, u32Eibit0); + SET_REG32_BIT(CM_SRAMC->SRAMB_EIBIT1, u32Eibit1); + } + } else { + if ((u32EccSram & SRAM_ECC_SRAM0) != 0U) { + CLR_REG32_BIT(CM_SRAMC->SRAM0_EIBIT0, u32Eibit0); + CLR_REG32_BIT(CM_SRAMC->SRAM0_EIBIT1, u32Eibit1); + } + if ((u32EccSram & SRAM_ECC_SRAMB) != 0U) { + CLR_REG32_BIT(CM_SRAMC->SRAMB_EIBIT0, u32Eibit0); + CLR_REG32_BIT(CM_SRAMC->SRAMB_EIBIT1, u32Eibit1); + } + } + +} + +/** + * @brief Get access address when 1bit or 2bit ECC error occurs in SRAM0/SRAMB. + * @param [in] u32EccSram The SRAM selection. + * This parameter can be any combination of @ref SRAM_ECC_SRAM + * @retval An uint32_t type value of access address. If 'u32EccSram' is not equal to the value upon, + * it will return 0xFFFFFFFFUL. + */ +uint32_t SRAM_GetEccErrorAddr(uint32_t u32EccSram) +{ + uint32_t u32RetAddr; + + DDL_ASSERT(IS_SRAM_ECC_SRAM_ONLY(u32EccSram)); + + if (u32EccSram == SRAM_ECC_SRAM0) { + u32RetAddr = READ_REG32(CM_SRAMC->SRAM0_ECCERRADDR); + } else { + u32RetAddr = READ_REG32(CM_SRAMC->SRAMB_ECCERRADDR); + } + + return u32RetAddr; +} + +/** + * @} + */ + +#endif /* LL_SRAM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c new file mode 100644 index 0000000000..3fb813e6d9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_swdt.c @@ -0,0 +1,257 @@ +/** + ******************************************************************************* + * @file hc32_ll_swdt.c + * @brief This file provides firmware functions to manage the Specialized Watch + * Dog Timer(SWDT). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Optimize SWDT_ClearStatus function timeout + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_swdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_SWDT SWDT + * @brief Specialized Watch Dog Timer + * @{ + */ + +#if (LL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Local_Macros SWDT Local Macros + * @{ + */ + +/* SWDT Refresh Key */ +#define SWDT_REFRESH_KEY_START (0x0123UL) +#define SWDT_REFRESH_KEY_END (0x3210UL) + +/* SWDT clear flag timeout(ms) */ +#define SWDT_CLR_FLAG_TIMEOUT (400UL) + +/* SWDT Registers Clear Mask */ +#define SWDT_CR_CLR_MASK (SWDT_CR_PERI | SWDT_CR_CKS | SWDT_CR_WDPT | \ + SWDT_CR_SLPOFF | SWDT_CR_ITS) + +/** + * @defgroup SWDT_Check_Parameters_Validity SWDT Check Parameters Validity + * @{ + */ + +#define IS_SWDT_CNT_PERIOD(x) \ +( ((x) == SWDT_CNT_PERIOD256) || \ + ((x) == SWDT_CNT_PERIOD4096) || \ + ((x) == SWDT_CNT_PERIOD16384) || \ + ((x) == SWDT_CNT_PERIOD65536)) + +#define IS_SWDT_CLK_DIV(x) \ +( ((x) == SWDT_CLK_DIV1) || \ + ((x) == SWDT_CLK_DIV16) || \ + ((x) == SWDT_CLK_DIV32) || \ + ((x) == SWDT_CLK_DIV64) || \ + ((x) == SWDT_CLK_DIV128) || \ + ((x) == SWDT_CLK_DIV256) || \ + ((x) == SWDT_CLK_DIV2048)) + +#define IS_SWDT_REFRESH_RANGE(x) \ +( ((x) == SWDT_RANGE_0TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT) || \ + ((x) == SWDT_RANGE_25TO50PCT) || \ + ((x) == SWDT_RANGE_0TO50PCT) || \ + ((x) == SWDT_RANGE_50TO75PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == SWDT_RANGE_25TO75PCT) || \ + ((x) == SWDT_RANGE_0TO75PCT) || \ + ((x) == SWDT_RANGE_75TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_50TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == SWDT_RANGE_25TO100PCT)) + +#define IS_SWDT_LPM_CNT(x) \ +( ((x) == SWDT_LPM_CNT_CONT) || \ + ((x) == SWDT_LPM_CNT_STOP)) + +#define IS_SWDT_EXP_TYPE(x) \ +( ((x) == SWDT_EXP_TYPE_INT) || \ + ((x) == SWDT_EXP_TYPE_RST)) + +#define IS_SWDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SWDT_FLAG_ALL) == SWDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief Initializes SWDT. + * @param [in] pstcSwdtInit Pointer to a @ref stc_swdt_init_t structure + * @retval int32_t: + * - LL_OK: Initializes success + * - LL_ERR_INVD_PARAM: pstcSwdtInit == NULL + */ +int32_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit) +{ + int32_t i32Ret = LL_OK; + uint32_t u32Temp; + + if (NULL == pstcSwdtInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_SWDT_CNT_PERIOD(pstcSwdtInit->u32CountPeriod)); + DDL_ASSERT(IS_SWDT_CLK_DIV(pstcSwdtInit->u32ClockDiv)); + DDL_ASSERT(IS_SWDT_REFRESH_RANGE(pstcSwdtInit->u32RefreshRange)); + DDL_ASSERT(IS_SWDT_LPM_CNT(pstcSwdtInit->u32LPMCount)); + DDL_ASSERT(IS_SWDT_EXP_TYPE(pstcSwdtInit->u32ExceptionType)); + + u32Temp = pstcSwdtInit->u32CountPeriod | pstcSwdtInit->u32ClockDiv | + pstcSwdtInit->u32RefreshRange | pstcSwdtInit->u32LPMCount | pstcSwdtInit->u32ExceptionType; + /* SWDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(CM_SWDT->CR, SWDT_CR_CLR_MASK, u32Temp); + } + + return i32Ret; +} + +/** + * @brief SWDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void SWDT_FeedDog(void) +{ + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_START); + WRITE_REG32(CM_SWDT->RR, SWDT_REFRESH_KEY_END); +} + +/** + * @brief Get SWDT flag status. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_SWDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear SWDT flag. + * @param [in] u32Flag SWDT flag type + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count underflow flag + * @arg SWDT_FLAG_REFRESH: Refresh error flag + * @arg SWDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t SWDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + /* Waiting for FLAG bit clear */ + u32Count = SWDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 25000UL); + while (0UL != READ_REG32_BIT(CM_SWDT->SR, u32Flag)) { + CLR_REG32_BIT(CM_SWDT->SR, u32Flag); + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_SWDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c new file mode 100644 index 0000000000..c242b25364 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr0.c @@ -0,0 +1,624 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr0.c + * @brief This file provides firmware functions to manage the TMR0 + * (TMR0). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr0.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR0 TMR0 + * @brief TMR0 Driver Library + * @{ + */ + +#if (LL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Local_Macros TMR0 Local Macros + * @{ + */ +/* Max channel number */ +#define TMR0_CH_MAX (2UL) + +#define TMR0_CLK_SRC_MASK (TMR0_BCONR_SYNSA | TMR0_BCONR_SYNCLKA | TMR0_BCONR_ASYNCLKA) +#define TMR0_BCONR_CLR_MASK (TMR0_BCONR_CAPMDA | TMR0_BCONR_CKDIVA | TMR0_BCONR_HICPA | TMR0_CLK_SRC_MASK) + +/** + * @defgroup TMR0_Register_Address TMR0 Register Address + * @{ + */ +#define TMR0_CNTR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CNTAR)) + ((__CH__) << 2UL)) +#define TMR0_CMPR_ADDR(__UNIT__, __CH__) (__IO uint32_t*)((uint32_t)(&((__UNIT__)->CMPAR)) + ((__CH__) << 2UL)) +/** + * @} + */ +#define TMR0_CH_OFFSET(__CH__) ((__CH__) << 4U) + +/** + * @defgroup TMR0_Check_Parameters_Validity TMR0 Check Parameters Validity + * @{ + */ +#define IS_TMR0_UNIT(x) \ +( ((x) == CM_TMR0_1) || \ + ((x) == CM_TMR0_2)) + +#define IS_TMR0_CH(x) \ +( ((x) == TMR0_CH_A) || \ + ((x) == TMR0_CH_B)) + +#define IS_TMR0_CLK_SRC(x) \ +( ((x) == TMR0_CLK_SRC_INTERN_CLK) || \ + ((x) == TMR0_CLK_SRC_SPEC_EVT) || \ + ((x) == TMR0_CLK_SRC_LRC) || \ + ((x) == TMR0_CLK_SRC_XTAL32)) + +#define IS_TMR0_CLK_DIV(x) \ +( ((x) == TMR0_CLK_DIV1) || \ + ((x) == TMR0_CLK_DIV2) || \ + ((x) == TMR0_CLK_DIV4) || \ + ((x) == TMR0_CLK_DIV8) || \ + ((x) == TMR0_CLK_DIV16) || \ + ((x) == TMR0_CLK_DIV32) || \ + ((x) == TMR0_CLK_DIV64) || \ + ((x) == TMR0_CLK_DIV128) || \ + ((x) == TMR0_CLK_DIV256) || \ + ((x) == TMR0_CLK_DIV512) || \ + ((x) == TMR0_CLK_DIV1024)) + +#define IS_TMR0_FUNC(x) \ +( ((x) == TMR0_FUNC_CMP) || \ + ((x) == TMR0_FUNC_CAPT)) + +#define IS_TMR0_INT(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_INT_ALL) == TMR0_INT_ALL)) + +#define IS_TMR0_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | TMR0_FLAG_ALL) == TMR0_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Functions TMR0 Global Functions + * @{ + */ + +/** + * @brief De-Initialize TMR0 function + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @retval None + */ +void TMR0_DeInit(CM_TMR0_TypeDef *TMR0x) +{ + uint32_t u32Ch; + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + + WRITE_REG32(TMR0x->BCONR, 0UL); + WRITE_REG32(TMR0x->STFLR, 0UL); + for (u32Ch = 0UL; u32Ch < TMR0_CH_MAX; u32Ch++) { + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, 0x0000FFFFUL); + } +} + +/** + * @brief Initialize TMR0 function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_Init(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, const stc_tmr0_init_t *pstcTmr0Init) +{ + __IO uint32_t *CNTR; + __IO uint32_t *CMPR; + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(pstcTmr0Init->u32ClockSrc)); + DDL_ASSERT(IS_TMR0_CLK_DIV(pstcTmr0Init->u32ClockDiv)); + DDL_ASSERT(IS_TMR0_FUNC(pstcTmr0Init->u32Func)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, 0UL); + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, pstcTmr0Init->u16CompareValue); + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CLR_MASK << TMR0_CH_OFFSET(u32Ch)), + ((pstcTmr0Init->u32ClockSrc | pstcTmr0Init->u32ClockDiv | + pstcTmr0Init->u32Func) << TMR0_CH_OFFSET(u32Ch))); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr0_init_t to default values. + * @param [out] pstcTmr0Init Pointer to a @ref stc_tmr0_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize success + * - LL_ERR_INVD_PARAM: pstcTmr0Init is NULL + */ +int32_t TMR0_StructInit(stc_tmr0_init_t *pstcTmr0Init) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcTmr0Init) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + pstcTmr0Init->u32ClockSrc = TMR0_CLK_SRC_INTERN_CLK; + pstcTmr0Init->u32ClockDiv = TMR0_CLK_DIV1; + pstcTmr0Init->u32Func = TMR0_FUNC_CMP; + pstcTmr0Init->u16CompareValue = 0xFFFFU; + } + return i32Ret; +} + +/** + * @brief Start TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Start(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Stop TMR0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval None + */ +void TMR0_Stop(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_CSTA << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 counter value. + * @note Setting the count requires stop tmr0. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the counter register + * @retval None + */ +void TMR0_SetCountValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CNTR, u16Value); +} + +/** + * @brief Get Tmr0 counter value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval uint16_t The counter register data + */ +uint16_t TMR0_GetCountValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CNTR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CNTR = TMR0_CNTR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CNTR); +} + +/** + * @brief Set Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u16Value The data to write to the compare register + * @retval None + */ +void TMR0_SetCompareValue(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + WRITE_REG32(*CMPR, u16Value); +} + +/** + * @brief Get Tmr0 compare value. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @retval The compare register data + */ +uint16_t TMR0_GetCompareValue(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch) +{ + __IO uint32_t *CMPR; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + + CMPR = TMR0_CMPR_ADDR(TMR0x, u32Ch); + return (uint16_t)READ_REG32(*CMPR); +} + +/** + * @brief Set clock source. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Src Specifies the clock source + * This parameter can be a value of the following: + * @arg @ref TMR0_Clock_Source + * @retval None + */ +void TMR0_SetClockSrc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_SRC(u32Src)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_CLK_SRC_MASK << TMR0_CH_OFFSET(u32Ch)), (u32Src << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set the division of clock. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Div Specifies the clock source division + * This parameter can be a value of the following: + * @arg TMR0_CLK_DIV1: Clock source / 1 + * @arg TMR0_CLK_DIV2: Clock source / 2 + * @arg TMR0_CLK_DIV4: Clock source / 4 + * @arg TMR0_CLK_DIV8: Clock source / 8 + * @arg TMR0_CLK_DIV16: Clock source / 16 + * @arg TMR0_CLK_DIV32: Clock source / 32 + * @arg TMR0_CLK_DIV64: Clock source / 64 + * @arg TMR0_CLK_DIV128: Clock source / 128 + * @arg TMR0_CLK_DIV256: Clock source / 256 + * @arg TMR0_CLK_DIV512: Clock source / 512 + * @arg TMR0_CLK_DIV1024: Clock source / 1024 + * @retval None. + */ +void TMR0_SetClockDiv(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CKDIVA << TMR0_CH_OFFSET(u32Ch)), (u32Div << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Set Tmr0 Function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] u32Func Select TMR0 function + * This parameter can be a value of the following: + * @arg TMR0_FUNC_CMP: Select the Compare function + * @arg TMR0_FUNC_CAPT: Select the Capture function + * @retval None + */ +void TMR0_SetFunc(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, uint32_t u32Func) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_TMR0_FUNC(u32Func)); + + MODIFY_REG32(TMR0x->BCONR, ((TMR0_BCONR_CAPMDA | TMR0_BCONR_HICPA) << TMR0_CH_OFFSET(u32Ch)), + (u32Func << TMR0_CH_OFFSET(u32Ch))); +} + +/** + * @brief Enable or disable HardWare trigger capture function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWCaptureCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HICPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger start function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStartCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTAA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger stop function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWStopCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HSTPA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable HardWare trigger clear function. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Ch TMR0 channel + * This parameter can be one of the following values: + * @arg @ref TMR0_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_HWClearCondCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } else { + CLR_REG32_BIT(TMR0x->BCONR, (TMR0_BCONR_HCLEA << TMR0_CH_OFFSET(u32Ch))); + } +} + +/** + * @brief Enable or disable specified Tmr0 interrupt. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32IntType TMR0 interrupt type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_Interrupt. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR0_IntCmd(CM_TMR0_TypeDef *TMR0x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DISABLE != enNewState) { + SET_REG32_BIT(TMR0x->BCONR, u32IntType); + } else { + CLR_REG32_BIT(TMR0x->BCONR, u32IntType); + } +} + +/** + * @brief Get Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR0_GetStatus(const CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(TMR0x->STFLR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear Tmr0 status. + * @param [in] TMR0x Pointer to TMR0 unit instance + * This parameter can be one of the following values: + * @arg CM_TMR0 or CM_TMR0_x: TMR0 unit instance + * @param [in] u32Flag TMR0 flag type + * This parameter can be any combination value of the following values: + * @arg @ref TMR0_FLAG + * @retval None + */ +void TMR0_ClearStatus(CM_TMR0_TypeDef *TMR0x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_TMR0_UNIT(TMR0x)); + DDL_ASSERT(IS_TMR0_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR0x->STFLR, u32Flag); +} + +/** + * @} + */ + +#endif /* LL_TMR0_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c new file mode 100644 index 0000000000..0cbc4de4b5 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr4.c @@ -0,0 +1,2455 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr4.c + * @brief This file provides firmware functions to manage the TMR4(Timer4). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr4.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR4 TMR4 + * @brief TMR4 Driver Library + * @{ + */ + +#if (LL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Local_Macros TMR4 Local Macros + * @{ + */ + +/** + * @defgroup TMR4_Check_Parameters_Validity TMR4 Check Parameters Validity + * @{ + */ +#define IS_TMR4_UNIT(x) \ +( ((x) == CM_TMR4_1) || \ + ((x) == CM_TMR4_2) || \ + ((x) == CM_TMR4_3)) + +#define IS_TMR4_SYNC_ST_UNIT(x) \ +( ((x) == CM_TMR4_2) || \ + ((x) == CM_TMR4_3)) + +#define IS_TMR4_CLK_DIV(x) \ +( ((x) == TMR4_CLK_DIV1) || \ + ((x) == TMR4_CLK_DIV2) || \ + ((x) == TMR4_CLK_DIV4) || \ + ((x) == TMR4_CLK_DIV8) || \ + ((x) == TMR4_CLK_DIV16) || \ + ((x) == TMR4_CLK_DIV32) || \ + ((x) == TMR4_CLK_DIV64) || \ + ((x) == TMR4_CLK_DIV128) || \ + ((x) == TMR4_CLK_DIV256) || \ + ((x) == TMR4_CLK_DIV512) || \ + ((x) == TMR4_CLK_DIV1024)) + +#define IS_TMR4_MD(x) \ +( ((x) == TMR4_MD_SAWTOOTH) || \ + ((x) == TMR4_MD_TRIANGLE)) + +#define IS_TMR4_CLK_SRC(x) \ +( ((x) == TMR4_CLK_SRC_INTERNCLK) || \ + ((x) == TMR4_CLK_SRC_EXTCLK)) + +#define IS_TMR4_INT_CNT_MASKTIME(x) ((x) <= TMR4_INT_CNT_MASK15) + +#define IS_TMR4_INT_CNT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_CNT_MASK) == TMR4_INT_CNT_MASK)) + +#define IS_TMR4_INT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_INT_ALL) == TMR4_INT_ALL)) + +#define IS_TMR4_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR4_FLAG_ALL) == TMR4_FLAG_ALL)) + +#define IS_TMR4_OC_HIGH_CH(x) (((x) & 0x1UL) == 0UL) +#define IS_TMR4_OC_LOW_CH(x) (((x) & 0x1UL) == 1UL) + +#define IS_TMR4_OC_BUF_OBJECT(x) \ +( (((x) | TMR4_OC_BUF_OBJECT_MASK) == TMR4_OC_BUF_OBJECT_MASK)) + +#define IS_TMR4_OC_BUF_COND(x) \ +( ((x) == TMR4_OC_BUF_COND_IMMED) || \ + ((x) == TMR4_OC_BUF_COND_PEAK) || \ + ((x) == TMR4_OC_BUF_COND_VALLEY) || \ + ((x) == TMR4_OC_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_INVD_POLARITY(x) \ +( ((x) == TMR4_OC_INVD_LOW) || \ + ((x) == TMR4_OC_INVD_HIGH)) + +#define IS_TMR4_PWM_MD(x) \ +( ((x) == TMR4_PWM_MD_THROUGH) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR) || \ + ((x) == TMR4_PWM_MD_DEAD_TMR_FILTER)) + +#define IS_TMR4_PWM_POLARITY(x) \ +( ((x) == TMR4_PWM_OXH_HOLD_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_HOLD) || \ + ((x) == TMR4_PWM_OXH_HOLD_OXL_INVT) || \ + ((x) == TMR4_PWM_OXH_INVT_OXL_INVT)) + +#define IS_TMR4_PWM_CLK_DIV(x) (((x) | TMR4_PWM_CLK_DIV128) == TMR4_PWM_CLK_DIV128) + +#define IS_TMR4_PWM_DEADTIME_REG_IDX(x) \ +( ((x) == TMR4_PWM_PDAR_IDX) || \ + ((x) == TMR4_PWM_PDBR_IDX)) + +#define IS_TMR4_PWM_OE_EFFECT(x) \ +( ((x) == TMR4_PWM_OE_EFFECT_IMMED) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_PEAK) || \ + ((x) == TMR4_PWM_OE_EFFECT_COUNT_VALLEY)) + +#define IS_TMR4_PWM_PIN_MD(x) \ +( ((x) == TMR4_PWM_PIN_OUTPUT_OS) || \ + ((x) == TMR4_PWM_PIN_OUTPUT_NORMAL)) + +#define IS_TMR4_EVT_MATCH_COND(x) (((x) | TMR4_EVT_MATCH_CNT_ALL) == TMR4_EVT_MATCH_CNT_ALL) + +#define IS_TMR4_EVT_MASK_TYPE(x) \ +( ((x) != 0U) || \ + (((x) | TMR4_EVT_MASK_TYPE_ALL) == TMR4_EVT_MASK_TYPE_ALL)) + +#define IS_TMR4_EVT_DELAY_OBJECT(x) \ +( ((x) == TMR4_EVT_DELAY_OCCRXH) || \ + ((x) == TMR4_EVT_DELAY_OCCRXL)) + +#define IS_TMR4_EVT_MD(x) \ +( ((x) == TMR4_EVT_MD_DELAY) || \ + ((x) == TMR4_EVT_MD_CMP)) + +#define IS_TMR4_EVT_MASK(x) (((x) | TMR4_EVT_MASK15) == TMR4_EVT_MASK15) + +#define IS_TMR4_EVT_BUF_COND(x) \ +( ((x) == TMR4_EVT_BUF_COND_IMMED) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK) || \ + ((x) == TMR4_EVT_BUF_COND_VALLEY) || \ + ((x) == TMR4_EVT_BUF_COND_PEAK_VALLEY)) + +#define IS_TMR4_OC_CH(x) ((x) <= TMR4_OC_CH_XL) +#define IS_TMR4_PWM_CH(x) ((x) <= TMR4_PWM_CH_X) +#define IS_TMR4_PWM_PIN(x) ((x) <= TMR4_PWM_PIN_OXL) +#define IS_TMR4_EVT_CH(x) ((x) <= TMR4_EVT_CH_XL) +#define IS_TMR4_EVT_OUTPUT_EVT(x) \ +( ((x) >> TMR4_SCSR_EVTOS_POS) <= (TMR4_EVT_OUTPUT_EVT7 >> TMR4_SCSR_EVTOS_POS)) +#define IS_TMR4_EVT_OUTPUT_SIGNAL(x) (((x) <= TMR4_EVT_OUTPUT_EVT5_SIGNAL) || \ + ((x) == TMR4_EVT_OUTPUT_EVT6_SIGNAL) || ((x) == TMR4_EVT_OUTPUT_EVT7_SIGNAL)) + +#define IS_TMR4_PWM_ABNORMAL_PIN_STAT(x) ((x) <= TMR4_PWM_ABNORMAL_PIN_HIGH) +/** + * @} + */ + +/** + * @defgroup TMR4_Channel_Max TMR4 Channel Max + * @{ + */ +#define TMR4_OC_CH_MAX (TMR4_OC_CH_XL) +#define TMR4_PWM_CH_MAX (TMR4_PWM_CH_X) +#define TMR4_EVT_CH_MAX (TMR4_EVT_CH_XL) +/** + * @} + */ + +/** + * @defgroup TMR4_Flag_Interrupt_Mask TMR4 Flag and Interrupt Mask + * @{ + */ +#define TMR4_FLAG_CNT_MASK (TMR4_FLAG_CNT_PEAK | TMR4_FLAG_CNT_VALLEY) +#define TMR4_INT_CNT_MASK (TMR4_INT_CNT_PEAK | TMR4_INT_CNT_VALLEY) + +#define TMR4_FLAG_OC_MASK (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL | TMR4_FLAG_OC_CMP_VH | \ + TMR4_FLAG_OC_CMP_VL | TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL | \ + TMR4_FLAG_OC_CMP_XH | TMR4_FLAG_OC_CMP_XL) +#define TMR4_INT_OC_MASK (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL | TMR4_INT_OC_CMP_VH | \ + TMR4_INT_OC_CMP_VL | TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL | \ + TMR4_INT_OC_CMP_XH | TMR4_INT_OC_CMP_XL) + +#define TMR4_FLAG_RELOAD_TMR_MASK (TMR4_FLAG_RELOAD_TMR_U | TMR4_FLAG_RELOAD_TMR_V | \ + TMR4_FLAG_RELOAD_TMR_W | TMR4_FLAG_RELOAD_TMR_X) +#define TMR4_INT_RELOAD_TMR_MASK (TMR4_INT_RELOAD_TMR_U | TMR4_INT_RELOAD_TMR_V | \ + TMR4_INT_RELOAD_TMR_W | TMR4_INT_RELOAD_TMR_X) + +#define TMR4_FLAG_SCMP_EVT_MASK (TMR4_FLAG_SCMP_EVT0 | TMR4_FLAG_SCMP_EVT1 | TMR4_FLAG_SCMP_EVT2 | \ + TMR4_FLAG_SCMP_EVT3 | TMR4_FLAG_SCMP_EVT4 | TMR4_FLAG_SCMP_EVT5 | \ + TMR4_FLAG_SCMP_EVT6 | TMR4_FLAG_SCMP_EVT7) +#define TMR4_INT_SCMP_EVT_MASK (TMR4_INT_SCMP_EVT0 | TMR4_INT_SCMP_EVT1 | TMR4_INT_SCMP_EVT2 | \ + TMR4_INT_SCMP_EVT3 | TMR4_INT_SCMP_EVT4 | TMR4_INT_SCMP_EVT5 | \ + TMR4_INT_SCMP_EVT6 | TMR4_INT_SCMP_EVT7) +/** + * @} + */ + +#define RCSR_REG_TYPE uint32_t + +/** + * @defgroup TMR4_Registers_Reset_Value TMR4 Registers Reset Value + * @{ + */ +#define TMR4_CCSR_RST_VALUE (0x0040U) +#define TMR4_SCER_RST_VALUE (0xFF00U) +#define TMR4_SCMR_RST_VALUE (0xFF00U) +#define TMR4_POCR_RST_VALUE (0xFF00U) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Buffer_Object_Mask TMR4 OC Buffer Object Mask + * @{ + */ +#define TMR4_OC_BUF_OBJECT_MASK (TMR4_OC_BUF_CMP_VALUE | TMR4_OC_BUF_CMP_MD) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit_Mask TMR4_OCSR Bit Mask + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCSR_OCEx_MASK(CH) (((uint16_t)TMR4_OCSR_OCEH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCPx_MASK(CH) (((uint16_t)TMR4_OCSR_OCPH) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIE_MASK (TMR4_OCSR_OCIEH | TMR4_OCSR_OCIEL) +#define TMR4_OCSR_OCF_MASK (TMR4_OCSR_OCFH | TMR4_OCSR_OCFL) +#define TMR4_OCSR_MASK(CH) \ +( ((uint16_t)(TMR4_OCSR_OCEH | TMR4_OCSR_OCPH | TMR4_OCSR_OCIEH | TMR4_OCSR_OCFH)) << (((CH) % 2UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit TMR4_OCSR Bit + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCSR_OCEx(CH, OCEx) (((uint16_t)OCEx) << (((uint16_t)((CH) % 2UL)) + TMR4_OCSR_OCEH_POS)) +#define TMR4_OCSR_OCPx(CH, OCPx) (((uint16_t)OCPx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCIEx(CH, OCIEx) (((uint16_t)OCIEx) << ((CH) % 2UL)) +#define TMR4_OCSR_OCFx(CH, OCFx) (((uint16_t)OCFx) << ((CH) % 2UL)) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit_Mask TMR4_OCER Bit Mask + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCER_CxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_CHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_MxBUFEN_MASK(CH) (((uint16_t)TMR4_OCER_MHBUFEN) << (((CH) % 2UL) << 1U)) +#define TMR4_OCER_LMCx_MASK(CH) (((uint16_t)TMR4_OCER_LMCH) << ((CH) % 2UL)) +#define TMR4_OCER_LMMx_MASK(CH) (((uint16_t)TMR4_OCER_LMMH) << ((CH) % 2UL)) +#define TMR4_OCER_MCECx_MASK(CH) (((uint16_t)TMR4_OCER_MCECH) << ((CH) % 2UL)) +#define TMR4_OCER_MASK(CH) \ +( (((uint16_t)(TMR4_OCER_CHBUFEN | TMR4_OCER_MHBUFEN)) << (((CH) % 2UL) << 1U)) | \ + (((uint16_t)(TMR4_OCER_LMCH | TMR4_OCER_LMMH | TMR4_OCER_MCECH)) << ((CH) % 2UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit TMR4_OCER Bit + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OC channel + * @{ + */ +#define TMR4_OCER_CxBUFEN(CH, CxBUFEN) ((uint16_t)((uint16_t)(CxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_CHBUFEN_POS))) +#define TMR4_OCER_MxBUFEN(CH, MxBUFEN) ((uint16_t)((uint16_t)(MxBUFEN) << ((((CH) % 2UL) << 1U) + TMR4_OCER_MHBUFEN_POS))) +#define TMR4_OCER_LMCx(CH, LMCx) ((uint16_t)(LMCx) << ((((CH) % 2UL)) + TMR4_OCER_LMCH_POS)) +#define TMR4_OCER_LMMx(CH, LMMx) ((uint16_t)(LMMx) << ((((CH) % 2UL)) + TMR4_OCER_LMMH_POS)) +#define TMR4_OCER_MCECx(CH, MCECx) ((uint16_t)(MCECx) << ((((CH) % 2UL)) + TMR4_OCER_MCECH_POS)) +/** + * @} + */ + +/** + * @defgroup TMR4_RCSR_Bit_Mask TMR4_RCSR Bit Mask + * @brief Get the specified TMR4_RCSR register bis value of the specified TMR4 PWM channel + * @{ + */ +#define TMR4_RCSR_RTIDx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTIDU) << (CH))) +#define TMR4_RCSR_RTIFx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTIFU) << ((CH) << 2U))) +#define TMR4_RCSR_RTICx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTICU) << ((CH) << 2U))) +#define TMR4_RCSR_RTEx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTEU) << ((CH) << 2U))) +#define TMR4_RCSR_RTSx_MASK(CH) ((RCSR_REG_TYPE)(((RCSR_REG_TYPE)TMR4_RCSR_RTSU) << ((CH) << 2U))) +#define TMR4_RCSR_MASK(CH) (TMR4_RCSR_RTIDx_MASK(CH) | TMR4_RCSR_RTIFx_MASK(CH) | TMR4_RCSR_RTICx_MASK(CH) | \ + TMR4_RCSR_RTEx_MASK(CH) | TMR4_RCSR_RTSx_MASK(CH)) +/** + * @} + */ + +/** + * @defgroup TMR4_PSCR_Bit_Mask TMR4_PSCR Bit Mask + * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel + * @{ + */ +#define TMR4_PSCR_OExy_MASK(PORT) (TMR4_PSCR_OEUH << (PORT)) +#define TMR4_PSCR_OSxy_MASK(PORT) (TMR4_PSCR_OSUH << ((PORT) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_PSCR_Bit TMR4_PSCR Bit + * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel + * @{ + */ +#define TMR4_PSCR_OExy(PORT, OExy) ((OExy) << (PORT)) +#define TMR4_PSCR_OSxy(PORT, OSxy) ((OSxy) << (((PORT) << 1U) + TMR4_PSCR_OSUH_POS)) +/** + * @} + */ + +/** + * @defgroup TMR4_Register TMR4 Register + * @{ + */ +#define TMR4_REG_ADDR(_REG_) ((uint32_t)(&(_REG_))) +#define TMR4_REG16(_ADDR_) ((__IO uint16_t *)(_ADDR_)) +#define TMR4_REG32(_ADDR_) ((__IO uint32_t *)(_ADDR_)) +#define TMR4_RCSR_REG(_ADDR_) ((__IO RCSR_REG_TYPE *)(_ADDR_)) + +/** + * @defgroup TMR4_OC_Register_UVW TMR4 OC Register + * @brief Get the specified OC register address of the specified TMR4 unit + * @{ + */ +#define _TMR4_OCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCCRUH) + ((CH) << 2U)) +#define _TMR4_OCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCMRUH) + ((CH) << 2U)) +#define _TMR4_OCER(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCERU) + (((CH) & 0x06UL) << 1U)) +#define _TMR4_OCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->OCSRU) + (((CH) & 0x06UL) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register_UVW TMR4 PWM Register + * @brief Get the specified PWM register address of the specified TMR4 unit + * @{ + */ +#define _TMR4_RCSR(UNIT) TMR4_RCSR_REG(TMR4_REG_ADDR((UNIT)->RCSR)) +#define _TMR4_POCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->POCRU) + ((CH) << 2U)) +#define _TMR4_PFSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PFSRU) + ((CH) << 3U)) +#define _TMR4_PDR(UNIT, CH, IDX) TMR4_REG16(TMR4_REG_ADDR((UNIT)->PDARU) + ((CH) << 3U) + ((IDX) << 1U)) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register_UVW TMR4 Event Register + * @brief Get the specified event register address of the specified TMR4 unit + * @{ + */ +#define _TMR4_SCCR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCCRUH) + ((CH) << 2U)) +#define _TMR4_SCSR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCSRUH) + ((CH) << 2U)) +#define _TMR4_SCMR(UNIT, CH) TMR4_REG16(TMR4_REG_ADDR((UNIT)->SCMRUH) + ((CH) << 2U)) +/** + * @} + */ + +/** + * @defgroup TMR4_OC_Register TMR4 OC Register + * @{ + */ +#define TMR4_OCCR(UNIT, CH) _TMR4_OCCR(UNIT, CH) +#define TMR4_OCMR(UNIT, CH) _TMR4_OCMR(UNIT, CH) +#define TMR4_OCER(UNIT, CH) _TMR4_OCER(UNIT, CH) +#define TMR4_OCSR(UNIT, CH) _TMR4_OCSR(UNIT, CH) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register TMR4 PWM Register + * @{ + */ +#define TMR4_RCSR(UNIT) _TMR4_RCSR(UNIT) +#define TMR4_POCR(UNIT, CH) _TMR4_POCR(UNIT, CH) +#define TMR4_PFSR(UNIT, CH) _TMR4_PFSR(UNIT, CH) +#define TMR4_PDR(UNIT, CH, IDX) _TMR4_PDR(UNIT, CH, IDX) +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Register TMR4 Event Register + * @{ + */ +#define TMR4_SCCR(UNIT, CH) _TMR4_SCCR(UNIT, CH) +#define TMR4_SCSR(UNIT, CH) _TMR4_SCSR(UNIT, CH) +#define TMR4_SCMR(UNIT, CH) _TMR4_SCMR(UNIT, CH) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR4_Global_Functions TMR4 Global Functions + * @{ + */ + +/** + * @defgroup TMR4_Counter_Global_Functions TMR4 Counter Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_init_t to default values + * @param [out] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_StructInit(stc_tmr4_init_t *pstcTmr4Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + pstcTmr4Init->u16PeriodValue = 0xFFFFU; + pstcTmr4Init->u16CountMode = TMR4_MD_SAWTOOTH; + pstcTmr4Init->u16ClockSrc = TMR4_CLK_SRC_INTERNCLK; + pstcTmr4Init->u16ClockDiv = TMR4_CLK_DIV1; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] pstcTmr4Init Pointer to a @ref stc_tmr4_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcCntInit value is NULL. + */ +int32_t TMR4_Init(CM_TMR4_TypeDef *TMR4x, const stc_tmr4_init_t *pstcTmr4Init) +{ + uint16_t u16Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4Init) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(pstcTmr4Init->u16ClockSrc)); + DDL_ASSERT(IS_TMR4_CLK_DIV(pstcTmr4Init->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_MD(pstcTmr4Init->u16CountMode)); + + /* Set TMR4_CCSR */ + u16Value = (pstcTmr4Init->u16ClockDiv | pstcTmr4Init->u16ClockSrc | \ + pstcTmr4Init->u16CountMode | TMR4_CCSR_CLEAR | TMR4_CCSR_STOP); + WRITE_REG16(TMR4x->CCSR, u16Value); + + /* Set TMR4_CVPR: default value */ + WRITE_REG16(TMR4x->CVPR, 0x0000U); + + /* Set TMR4 period */ + WRITE_REG16(TMR4x->CPSR, pstcTmr4Init->u16PeriodValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-Initialize TMR4 counter function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval int32_t: + * - LL_OK: Reset success. + */ +int32_t TMR4_DeInit(CM_TMR4_TypeDef *TMR4x) +{ + uint32_t u32Ch; + int32_t i32Ret = LL_OK; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + /* Configures the registers to reset value. */ + WRITE_REG16(TMR4x->CCSR, TMR4_CCSR_RST_VALUE); + WRITE_REG16(TMR4x->CPSR, 0xFFFFU); + WRITE_REG16(TMR4x->CVPR, 0x0000U); + WRITE_REG16(TMR4x->CNTR, 0x0000U); + + /* De-initialize OC */ + for (u32Ch = 0UL; u32Ch <= TMR4_OC_CH_MAX; u32Ch++) { + TMR4_OC_DeInit(TMR4x, u32Ch); + } + + /* De-initialize PWM */ + MODIFY_REG32(TMR4x->PSCR, (TMR4_PSCR_MOE | TMR4_PSCR_AOE), 0UL); + for (u32Ch = 0UL; u32Ch <= TMR4_PWM_CH_MAX; u32Ch++) { + TMR4_PWM_DeInit(TMR4x, u32Ch); + } + + /* De-initialize special event */ + WRITE_REG16(TMR4x->SCER, TMR4_SCER_RST_VALUE); + for (u32Ch = 0UL; u32Ch <= TMR4_OC_CH_MAX; u32Ch++) { + TMR4_EVT_DeInit(TMR4x, u32Ch); + } + + return i32Ret; +} + +/** + * @brief Set TMR4 counter clock source + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Src TMR4 counter clock source + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Source + * @arg TMR4_CLK_SRC_INTERNCLK: Uses the internal clock as counter's count clock + * @arg TMR4_CLK_SRC_EXTCLK: Uses an external input clock as counter's count clock + * @retval None + * @note The clock division function is valid when clock source is internal clock. + */ +void TMR4_SetClockSrc(CM_TMR4_TypeDef *TMR4x, uint16_t u16Src) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_SRC(u16Src)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_ECKEN, u16Src); +} + +/** + * @brief Set TMR4 counter clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Div TMR4 clock division + * This parameter can be one of the macros group @ref TMR4_Count_Clock_Division + * @arg TMR4_CLK_DIV1: CLK + * @arg TMR4_CLK_DIV2: CLK/2 + * @arg TMR4_CLK_DIV4: CLK/4 + * @arg TMR4_CLK_DIV8: CLK/8 + * @arg TMR4_CLK_DIV16: CLK/16 + * @arg TMR4_CLK_DIV32: CLK/32 + * @arg TMR4_CLK_DIV64: CLK/64 + * @arg TMR4_CLK_DIV128: CLK/128 + * @arg TMR4_CLK_DIV256: CLK/256 + * @arg TMR4_CLK_DIV512: CLK/512 + * @arg TMR4_CLK_DIV1024: CLK/1024 + * @retval None + * @note The clock division function is valid when clock source is the internal clock. + */ +void TMR4_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint16_t u16Div) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_CLK_DIV(u16Div)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_CKDIV, u16Div); +} + +/** + * @brief Set TMR4 counter count mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Mode TMR4 counter count mode + * This parameter can be one of the macros group @ref TMR4_Count_Mode + * @arg TMR4_MD_SAWTOOTH: TMR4 count mode sawtooth wave + * @arg TMR4_MD_TRIANGLE: TMR4 count mode triangular + * @retval None + */ +void TMR4_SetCountMode(CM_TMR4_TypeDef *TMR4x, uint16_t u16Mode) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_MD(u16Mode)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_MODE, u16Mode); +} + +/** + * @brief Get the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The period value of the TMR4 counter + */ +uint16_t TMR4_GetPeriodValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CPSR); +} + +/** + * @brief Set the period value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The period value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetPeriodValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CPSR, u16Value); +} + +/** + * @brief Get the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval The count value of the TMR4 counter + */ +uint16_t TMR4_GetCountValue(const CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + return READ_REG16(TMR4x->CNTR); +} + +/** + * @brief Set the count value of the TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Value The count value of the TMR4 counter + * @arg number of 16bit + * @retval None + */ +void TMR4_SetCountValue(CM_TMR4_TypeDef *TMR4x, uint16_t u16Value) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + WRITE_REG16(TMR4x->CNTR, u16Value); +} + +/** + * @brief Clear TMR4 counter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_ClearCountValue(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_CLEAR); +} + +/** + * @brief Start TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Start(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Stop TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @retval None + */ +void TMR4_Stop(CM_TMR4_TypeDef *TMR4x) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Clear TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval None + */ +void TMR4_ClearStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ClearFlag; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag */ + if ((u32Flag & TMR4_FLAG_CNT_MASK) > 0UL) { + CLR_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)); + } + + /* Output-compare flag */ + u32ClearFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ClearFlag > 0UL) { + /* TMR4_OCSRU */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRV */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRW */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + + /* TMR4_OCSRX */ + u32ClearFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_XH | TMR4_FLAG_OC_CMP_XL)) >> 16U); + if (u32ClearFlag > 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_XH); + CLR_REG16_BIT(*OCSR, u32ClearFlag); + } + } + + /* PWM reload timer flag */ + u32ClearFlag = ((u32Flag & TMR4_FLAG_RELOAD_TMR_MASK) << 5U); + if (u32ClearFlag > 0UL) { + SET_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32ClearFlag); + } + + /* Event-compare interrupt */ + u32ClearFlag = ((u32Flag & TMR4_FLAG_SCMP_EVT_MASK) >> 24U); + if (u32ClearFlag > 0UL) { + CLR_REG16_BIT(TMR4x->SCFR, u32ClearFlag); + } +} + +/** + * @brief Get TMR4 flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Flag TMR4 flag + * This parameter can be any composed value of the macros group @ref TMR4_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR4_GetStatus(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Flag) +{ + uint32_t u32ReadFlag; + uint8_t u8FlagSetCount = 0; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_FLAG(u32Flag)); + + /* Counter flag status */ + if (READ_REG16_BIT(TMR4x->CCSR, (u32Flag & TMR4_FLAG_CNT_MASK)) > 0U) { + u8FlagSetCount++; + } + + /* Output-compare interrupt */ + u32ReadFlag = (u32Flag & TMR4_FLAG_OC_MASK); + if (u32ReadFlag > 0UL) { + /* TMR4_OCSRU */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_UH | TMR4_FLAG_OC_CMP_UL)) >> 10U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRV */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_VH | TMR4_FLAG_OC_CMP_VL)) >> 12U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRW */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_WH | TMR4_FLAG_OC_CMP_WL)) >> 14U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* TMR4_OCSRX */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_OC_CMP_XH | TMR4_FLAG_OC_CMP_XL)) >> 16U); + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_XH); + if (READ_REG16_BIT(*OCSR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + } + + /* PWM reload timer flag status */ + u32ReadFlag = ((u32Flag & (TMR4_FLAG_RELOAD_TMR_MASK)) << 4U); + if (READ_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + /* Event-compare interrupt */ + u32ReadFlag = ((u32Flag & TMR4_FLAG_SCMP_EVT_MASK) >> 24U); + if (READ_REG16_BIT(TMR4x->SCFR, u32ReadFlag) > 0U) { + u8FlagSetCount++; + } + + return (u8FlagSetCount == 0U) ? RESET : SET; +} + +/** + * @brief Enable or disable the specified TMR4 interrupt + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be any composed value of the macros group @ref TMR4_Interrupt + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_IntCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32Type; + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Counter interrupt */ + u32Type = (u32IntType & TMR4_INT_CNT_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? SET_REG16_BIT(TMR4x->CCSR, u32Type) : CLR_REG16_BIT(TMR4x->CCSR, u32Type); + } + + /* Output-compare interrupt */ + u32Type = (u32IntType & TMR4_INT_OC_MASK); + if (u32Type > 0UL) { + /* TMR4_OCSRU */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_UH | TMR4_INT_OC_CMP_UL)) >> 12U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_UH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRV */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_VH | TMR4_INT_OC_CMP_VL)) >> 14U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_VH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRW */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_WH | TMR4_INT_OC_CMP_WL)) >> 16U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_WH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + + /* TMR4_OCSRX */ + u32Type = ((u32IntType & (TMR4_INT_OC_CMP_XH | TMR4_INT_OC_CMP_XL)) >> 18U); + if (u32Type != 0UL) { + OCSR = TMR4_OCSR(TMR4x, TMR4_OC_CH_XH); + (ENABLE == enNewState) ? SET_REG16_BIT(*OCSR, u32Type) : CLR_REG16_BIT(*OCSR, u32Type); + } + } + + /* PWM reload timer interrupt */ + u32Type = (u32IntType & TMR4_INT_RELOAD_TMR_MASK); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? CLR_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32Type) : SET_REG_BIT(TMR4x->RCSR, (RCSR_REG_TYPE)u32Type); + } + + /* Event-compare interrupt */ + u32Type = ((u32IntType & TMR4_INT_SCMP_EVT_MASK) >> 24U); + if (u32Type > 0UL) { + (ENABLE == enNewState) ? SET_REG16_BIT(TMR4x->SCIR, u32Type) : CLR_REG16_BIT(TMR4x->SCIR, u32Type); + } +} + +/** + * @brief Enable or disable the TMR4 counter period buffer function. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PeriodBufCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } else { + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_BUFEN); + } +} + +/** + * @brief Get TMR4 count interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) + */ +uint16_t TMR4_GetCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + + if (TMR4_INT_CNT_VALLEY == u32IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIM) >> TMR4_CVPR_ZIM_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIM) >> TMR4_CVPR_PIM_POS); + } + + return u16MaskTimes; +} + +/** + * @brief Set TMR4 counter interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @param [in] u16MaskTime TMR4 counter interrupt mask times + * This parameter can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * @arg TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for counter count every time at "0x0000" or peak + * @arg TMR4_INT_CNT_MASK1: Counter interrupt flag is set once when counter counts 2 times at "0x0000" or peak (skipping 1 count) + * @arg TMR4_INT_CNT_MASK2: Counter interrupt flag is set once when counter counts 3 times at "0x0000" or peak (skipping 2 count) + * @arg TMR4_INT_CNT_MASK3: Counter interrupt flag is set once when counter counts 4 times at "0x0000" or peak (skipping 3 count) + * @arg TMR4_INT_CNT_MASK4: Counter interrupt flag is set once when counter counts 5 times at "0x0000" or peak (skipping 4 count) + * @arg TMR4_INT_CNT_MASK5: Counter interrupt flag is set once when counter counts 6 times at "0x0000" or peak (skipping 5 count) + * @arg TMR4_INT_CNT_MASK6: Counter interrupt flag is set once when counter counts 7 times at "0x0000" or peak (skipping 6 count) + * @arg TMR4_INT_CNT_MASK7: Counter interrupt flag is set once when counter counts 8 times at "0x0000" or peak (skipping 7 count) + * @arg TMR4_INT_CNT_MASK8: Counter interrupt flag is set once when counter counts 9 times at "0x0000" or peak (skipping 8 count) + * @arg TMR4_INT_CNT_MASK9: Counter interrupt flag is set once when counter counts 10 times at "0x0000" or peak (skipping 9 count) + * @arg TMR4_INT_CNT_MASK10: Counter interrupt flag is set once when counter counts 11 times at "0x0000" or peak (skipping 10 count) + * @arg TMR4_INT_CNT_MASK11: Counter interrupt flag is set once when counter counts 12 times at "0x0000" or peak (skipping 11 count) + * @arg TMR4_INT_CNT_MASK12: Counter interrupt flag is set once when counter counts 13 times at "0x0000" or peak (skipping 12 count) + * @arg TMR4_INT_CNT_MASK13: Counter interrupt flag is set once when counter counts 14 times at "0x0000" or peak (skipping 13 count) + * @arg TMR4_INT_CNT_MASK14: Counter interrupt flag is set once when counter counts 15 times at "0x0000" or peak (skipping 14 count) + * @arg TMR4_INT_CNT_MASK15: Counter interrupt flag is set once when counter counts 16 times at "0x0000" or peak (skipping 15 count) + * @retval None + */ +void TMR4_SetCountIntMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType, uint16_t u16MaskTime) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + DDL_ASSERT(IS_TMR4_INT_CNT_MASKTIME(u16MaskTime)); + + if (TMR4_INT_CNT_VALLEY == (u32IntType & TMR4_INT_CNT_VALLEY)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_ZIM, (u16MaskTime << TMR4_CVPR_ZIM_POS)); + } + + if (TMR4_INT_CNT_PEAK == (u32IntType & TMR4_INT_CNT_PEAK)) { + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_PIM, (u16MaskTime << TMR4_CVPR_PIM_POS)); + } +} + +/** + * @brief Get TMR4 counter current interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32IntType TMR4 interrupt source + * This parameter can be one of the macros group @ref TMR4_Interrupt + * @arg TMR4_INT_CNT_PEAK: Count peak interrupt + * @arg TMR4_INT_CNT_VALLEY : Count valley interrupt + * @retval Returned value can be one of the macros group @ref TMR4_Count_Interrupt_Mask_Time + * - TMR4_INT_CNT_MASK0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak + * - TMR4_INT_CNT_MASK1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skipping 1 count) + * - TMR4_INT_CNT_MASK2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skipping 2 count) + * - TMR4_INT_CNT_MASK3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skipping 3 count) + * - TMR4_INT_CNT_MASK4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skipping 4 count) + * - TMR4_INT_CNT_MASK5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skipping 5 count) + * - TMR4_INT_CNT_MASK6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skipping 6 count) + * - TMR4_INT_CNT_MASK7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skipping 7 count) + * - TMR4_INT_CNT_MASK8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skipping 8 count) + * - TMR4_INT_CNT_MASK9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skipping 9 count) + * - TMR4_INT_CNT_MASK10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skipping 10 count) + * - TMR4_INT_CNT_MASK11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skipping 11 count) + * - TMR4_INT_CNT_MASK12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skipping 12 count) + * - TMR4_INT_CNT_MASK13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skipping 13 count) + * - TMR4_INT_CNT_MASK14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skipping 14 count) + * - TMR4_INT_CNT_MASK15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skipping 15 count) + */ +uint16_t TMR4_GetCurrentCountIntMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32IntType) +{ + uint16_t u16MaskTimes; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_INT_CNT(u32IntType)); + + if (TMR4_INT_CNT_VALLEY == u32IntType) { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIC) >> TMR4_CVPR_ZIC_POS); + } else { + u16MaskTimes = (READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIC) >> TMR4_CVPR_PIC_POS); + } + + return u16MaskTimes; +} + +/** + * @brief Enable or disable port output TMR4 counter direction signal + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PortOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS); + } else { + CLR_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS); + } +} + +/** + * @brief Enable or disable sync start of the TMR4 count. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note This function is valid for only CM_TMR4_2 and CM_TMR4_3 + */ +void TMR4_SyncStartCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_SYNC_ST_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_SYNST); + } else { + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_SYNST); + } +} + +/** + * @brief Enable or disable hardware start of the TMR4 count. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_HWStartCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_HST); + } else { + CLR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_HST); + } +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Output_Compare_Global_Functions TMR4 Output-Compare Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_oc_init_t to default values + * @param [out] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_StructInit(stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + pstcTmr4OcInit->u16CompareValue = 0U; + pstcTmr4OcInit->u16OcInvalidPolarity = TMR4_OC_INVD_LOW; + pstcTmr4OcInit->u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED; + pstcTmr4OcInit->u16BufLinkTransObject = TMR4_OC_BUF_NONE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] pstcTmr4OcInit Pointer to a @ref stc_tmr4_oc_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4OcInit value is NULL. + */ +int32_t TMR4_OC_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_oc_init_t *pstcTmr4OcInit) +{ + uint16_t u16Value; + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4OcInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(pstcTmr4OcInit->u16OcInvalidPolarity)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareModeBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(pstcTmr4OcInit->u16CompareValueBufCond)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(pstcTmr4OcInit->u16BufLinkTransObject)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Set output polarity when OC is disabled. */ + MODIFY_REG16(*OCSR, TMR4_OCSR_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, pstcTmr4OcInit->u16OcInvalidPolarity)); + + /* Set OCMR&&OCCR buffer function */ + u16Value = (TMR4_OCER_MxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareModeBufCond) | \ + TMR4_OCER_CxBUFEN(u32Ch, pstcTmr4OcInit->u16CompareValueBufCond)); + if (TMR4_OC_BUF_CMP_VALUE == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_VALUE)) { + u16Value |= TMR4_OCER_LMCx_MASK(u32Ch); + } + + if (TMR4_OC_BUF_CMP_MD == (pstcTmr4OcInit->u16BufLinkTransObject & TMR4_OC_BUF_CMP_MD)) { + u16Value |= TMR4_OCER_LMMx_MASK(u32Ch); + } + + MODIFY_REG16(*OCER, TMR4_OCER_MASK(u32Ch), u16Value); + + /* Set OC compare value */ + WRITE_REG16(*OCCR, pstcTmr4OcInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 OC + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval None + */ +void TMR4_OC_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *OCER; + __IO uint16_t *OCSR; + __IO uint16_t *OCCR; + __IO uint16_t *OCMRxH; + __IO uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + OCER = TMR4_OCER(TMR4x, u32Ch); + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + /* Clear bits: port output valid && OP level && interrupt */ + CLR_REG16_BIT(*OCSR, TMR4_OCSR_MASK(u32Ch)); + + /* Clear bits: OCMR&&OCCR buffer */ + CLR_REG16_BIT(*OCER, TMR4_OCER_MASK(u32Ch)); + + /* Set OC compare match value */ + WRITE_REG16(*OCCR, 0x0000U); + + /* Set OCMR value */ + if ((u32Ch & 0x01UL) == 0UL) { + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + WRITE_REG16(*OCMRxH, 0x0000U); + } else { + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + WRITE_REG32(*OCMRxL, 0x00000000UL); + } +} + +/** + * @brief Get TMR4 OC OCCR compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The compare value of the TMR4 OC OCCR register + */ +uint16_t TMR4_OC_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + return READ_REG16(*OCCR); +} + +/** + * @brief Set TMR4 OC compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Value The compare value of the TMR4 OC OCCR register + * @arg number of 16bit + * @retval None + */ +void TMR4_OC_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *OCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCCR = TMR4_OCCR(TMR4x, u32Ch); + + WRITE_REG16(*OCCR, u16Value); +} + +/** + * @brief Enable or disable the TMR4 OC of the specified channel. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_Cmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR port output compare */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCEx_MASK(u32Ch), TMR4_OCSR_OCEx(u32Ch, enNewState)); +} + +/** + * @brief Extend the matching conditions of TMR4 OC channel + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_OC_ExtendControlCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + /* Set OCER register: Extend match function */ + MODIFY_REG16(*OCER, TMR4_OCER_MCECx_MASK(u32Ch), TMR4_OCER_MCECx(u32Ch, enNewState)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer interval response function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer: OCCR/OCMR + * This parameter can be any composed value of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: Enable the OCMR/OCMR register buffer function. + * @arg DISABLE: Disable the OCMR/OCMR register buffer function. + * @retval None + */ +void TMR4_OC_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16Object, en_functional_state_t enNewState) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMCx_MASK(u32Ch), TMR4_OCER_LMCx(u32Ch, enNewState)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR link transfer function */ + MODIFY_REG16(*OCER, TMR4_OCER_LMMx_MASK(u32Ch), TMR4_OCER_LMMx(u32Ch, enNewState)); + } +} + +/** + * @brief Get TMR4 OC output current polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval Returned value can be one of the macros group @ref TMR4_OC_Output_Polarity + * - TMR4_OC_PORT_LOW: TMR4 OC output low level + * - TMR4_OC_PORT_HIGH: TMR4 OC output high level + */ +uint16_t TMR4_OC_GetPolarity(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCSR; + uint16_t u16Polarity; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Get OCSR register: OC output polarity */ + u16Polarity = READ_REG16_BIT(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch)); + return (u16Polarity >> (u32Ch % 2UL)); +} + +/** + * @brief Set TMR4 OC invalid output polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Polarity TMR4 OC invalid output polarity. + * This parameter can be one of the macros group @ref TMR4_OC_Invalid_Output_Polarity + * @arg TMR4_OC_INVD_LOW: TMR4 OC output low level when OC is invalid + * @arg TMR4_OC_INVD_HIGH: TMR4 OC output high level when OC is invalid + * @retval None + */ +void TMR4_OC_SetOcInvalidPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *OCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_INVD_POLARITY(u16Polarity)); + + /* Get pointer of current channel OC register address */ + OCSR = TMR4_OCSR(TMR4x, u32Ch); + + /* Set OCSR register: OC invalid output polarity */ + MODIFY_REG16(*OCSR, TMR4_OCSR_OCPx_MASK(u32Ch), TMR4_OCSR_OCPx(u32Ch, u16Polarity)); +} + +/** + * @brief Set TMR4 OC OCCR/OCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] u16Object TMR4 OC register buffer type: OCCR/OCMR + * This parameter can be any composed value of the macros group @ref TMR4_OC_Buffer_Object + * @arg TMR4_OC_BUF_CMP_VALUE: The register OCCR buffer function + * @arg TMR4_OC_BUF_CMP_MD: The register OCMR buffer function + * @param [in] u16BufCond TMR4 OC OCCR/OCMR buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_OC_Buffer_Transfer_Condition + * @arg TMR4_OC_BUF_COND_IMMED: Buffer transfer is made when writing to the OCCR/OCMR register. + * @arg TMR4_OC_BUF_COND_VALLEY: Buffer transfer is made when counter count valley. + * @arg TMR4_OC_BUF_COND_PEAK: Buffer transfer is made when counter count peak. + * @arg TMR4_OC_BUF_COND_PEAK_VALLEY: Buffer transfer is made when counter count peak or valley. + * @retval None + */ +void TMR4_OC_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object, uint16_t u16BufCond) +{ + __IO uint16_t *OCER; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_OC_BUF_OBJECT(u16Object)); + DDL_ASSERT(IS_TMR4_OC_BUF_COND(u16BufCond)); + + /* Get pointer of current channel OC register address */ + OCER = TMR4_OCER(TMR4x, u32Ch); + + if (TMR4_OC_BUF_CMP_VALUE == (u16Object & TMR4_OC_BUF_CMP_VALUE)) { + /* Set OCER register: OCCR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_CxBUFEN_MASK(u32Ch), TMR4_OCER_CxBUFEN(u32Ch, u16BufCond)); + } + + if (TMR4_OC_BUF_CMP_MD == (u16Object & TMR4_OC_BUF_CMP_MD)) { + /* Set OCER register: OCMR buffer mode */ + MODIFY_REG16(*OCER, TMR4_OCER_MxBUFEN_MASK(u32Ch), TMR4_OCER_MxBUFEN(u32Ch, u16BufCond)); + } +} + +/** + * @brief Get the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The TMR4 OC high channel mode + * @note The function only can get high channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +uint16_t TMR4_OC_GetHighChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + return READ_REG16(*OCMRxH); +} + +/** + * @brief Set the TMR4 OC high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] unTmr4Ocmrh The TMR4 OC high channel mode @ref un_tmr4_oc_ocmrh_t + * @retval None + * @note The function only can set high channel mode:TMR4_OC_CH_xH(x = U/V/W) + */ +void TMR4_OC_SetHighChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrh_t unTmr4Ocmrh) +{ + __IO uint16_t *OCMRxH; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_HIGH_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxH = TMR4_OCMR(TMR4x, u32Ch); + WRITE_REG16(*OCMRxH, unTmr4Ocmrh.OCMRx); +} + +/** + * @brief Get the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @retval The TMR4 OC low channel mode + * @note The function only can get low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +uint32_t TMR4_OC_GetLowChCompareMode(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + return READ_REG32(*OCMRxL); +} + +/** + * @brief Set the TMR4 OC low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 OC channel. + * This parameter can be one of the macros group @ref TMR4_OC_Channel + * @param [in] unTmr4Ocmrl The TMR4 OC low channel mode @ref un_tmr4_oc_ocmrl_t + * @retval None + * @note The function only can set low channel mode:TMR4_OC_CH_xL(x = U/V/W) + */ +void TMR4_OC_SetLowChCompareMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, un_tmr4_oc_ocmrl_t unTmr4Ocmrl) +{ + __IO uint32_t *OCMRxL; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_OC_LOW_CH(u32Ch)); + + /* Get pointer of current channel OC register address */ + OCMRxL = (__IO uint32_t *)((uint32_t)TMR4_OCMR(TMR4x, u32Ch)); + WRITE_REG32(*OCMRxL, unTmr4Ocmrl.OCMRx); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Global_Functions TMR4 PWM Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_pwm_init_t to default values + * @param [out] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + pstcTmr4PwmInit->u16Mode = TMR4_PWM_MD_THROUGH; + pstcTmr4PwmInit->u16ClockDiv = TMR4_PWM_CLK_DIV1; + pstcTmr4PwmInit->u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] pstcTmr4PwmInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4PwmInit value is NULL. + */ +int32_t TMR4_PWM_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_pwm_init_t *pstcTmr4PwmInit) +{ + uint16_t POCRValue; + __IO uint16_t *POCR; + RCSR_REG_TYPE RCSRValue; + __IO RCSR_REG_TYPE *RCSR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4PwmInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_MD(pstcTmr4PwmInit->u16Mode)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(pstcTmr4PwmInit->u16ClockDiv)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(pstcTmr4PwmInit->u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + + /* Set POCR register */ + POCRValue = (pstcTmr4PwmInit->u16Mode | pstcTmr4PwmInit->u16ClockDiv | pstcTmr4PwmInit->u16Polarity); + WRITE_REG16(*POCR, POCRValue); + + /* Set RCSR register */ + RCSRValue = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch)); + MODIFY_REG(*RCSR, TMR4_RCSR_MASK(u32Ch), RCSRValue); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *POCR; + __IO RCSR_REG_TYPE *RCSR; + RCSR_REG_TYPE RCSRValue; + __IO uint16_t *PDAR; + __IO uint16_t *PDBR; + __IO uint16_t *PFSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + RCSR = TMR4_RCSR(TMR4x); + PDAR = TMR4_PDR(TMR4x, u32Ch, TMR4_PWM_PDAR_IDX); + PDBR = TMR4_PDR(TMR4x, u32Ch, TMR4_PWM_PDBR_IDX); + PFSR = TMR4_PFSR(TMR4x, u32Ch); + + /* Set POCR register to reset value */ + WRITE_REG16(*POCR, TMR4_POCR_RST_VALUE); + + /* Set RCSR register */ + RCSRValue = (TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch)); + MODIFY_REG(*RCSR, TMR4_RCSR_MASK(u32Ch), RCSRValue); + + /* Set PDAR/PDBR register to reset value */ + WRITE_REG16(*PDAR, 0U); + WRITE_REG16(*PDBR, 0U); + + /* Set POCR register to reset value */ + WRITE_REG16(*PFSR, 0U); + + /* Set abnormal pin status to reset value */ + TMR4_PWM_SetAbnormalPinStatus(TMR4x, ((u32Ch << 1) + 0UL), TMR4_PWM_ABNORMAL_PIN_HIZ); + TMR4_PWM_SetAbnormalPinStatus(TMR4x, ((u32Ch << 1) + 1UL), TMR4_PWM_ABNORMAL_PIN_HIZ); + + /* Set port output mode to reset value */ + TMR4_PWM_SetPortOutputMode(TMR4x, ((u32Ch << 1) + 0UL), TMR4_PWM_PIN_OUTPUT_OS); + TMR4_PWM_SetPortOutputMode(TMR4x, ((u32Ch << 1) + 1UL), TMR4_PWM_PIN_OUTPUT_OS); +} + +/** + * @brief Set TMR4 PWM clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Div TMR4 PWM internal clock division + * This parameter can be one of the macros group @ref TMR4_PWM_Clock_Division + * @arg TMR4_PWM_CLK_DIV1: CLK + * @arg TMR4_PWM_CLK_DIV2: CLK/2 + * @arg TMR4_PWM_CLK_DIV4: CLK/4 + * @arg TMR4_PWM_CLK_DIV8: CLK/8 + * @arg TMR4_PWM_CLK_DIV16: CLK/16 + * @arg TMR4_PWM_CLK_DIV32: CLK/32 + * @arg TMR4_PWM_CLK_DIV64: CLK/64 + * @arg TMR4_PWM_CLK_DIV128: CLK/128 + * @retval None + */ +void TMR4_PWM_SetClockDiv(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Div) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_CLK_DIV(u16Div)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_DIVCK, u16Div); +} + +/** + * @brief Set TMR4 PWM output polarity. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Polarity TMR4 PWM output polarity + * This parameter can be one of the macros group @ref TMR4_PWM_Polarity + * @arg TMR4_PWM_OXH_HOLD_OXL_HOLD: Output PWML and PWMH signals without changing the level + * @arg TMR4_PWM_OXH_INVT_OXL_INVT: Output both PWML and PWMH signals reversed + * @arg TMR4_PWM_OXH_INVT_OXL_HOLD: Output the PWMH signal reversed, outputs the PWML signal without changing the level + * @arg TMR4_PWM_OXH_HOLD_OXL_INVT: Output the PWMH signal without changing the level, Outputs the PWML signal reversed + * @retval None + */ +void TMR4_PWM_SetPolarity(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Polarity) +{ + __IO uint16_t *POCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_POLARITY(u16Polarity)); + + /* Get pointer of current channel PWM register address */ + POCR = TMR4_POCR(TMR4x, u32Ch); + + MODIFY_REG16(*POCR, TMR4_POCR_LVLS, u16Polarity); +} + +/** + * @brief Start TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StartReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG_BIT(TMR4x->RCSR, TMR4_RCSR_RTEx_MASK(u32Ch)); +} + +/** + * @brief Stop TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @retval None + */ +void TMR4_PWM_StopReloadTimer(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + SET_REG_BIT(TMR4x->RCSR, TMR4_RCSR_RTSx_MASK(u32Ch)); +} + +/** + * @brief Set TMR4 PWM filter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u16Value TMR4 PWM filter count value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetFilterCountValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *PFSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + PFSR = TMR4_PFSR(TMR4x, u32Ch); + + WRITE_REG16(*PFSR, u16Value); +} + +/** + * @brief Set TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @param [in] u16Value TMR4 PWM dead time register value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetDeadTimeValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex, uint16_t u16Value) +{ + __IO uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + WRITE_REG16(*PDR, u16Value); +} + +/** + * @brief Get TMR4 PWM dead time count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the macros group @ref TMR4_PWM_Channel + * @param [in] u32DeadTimeIndex TMR4 PWM dead time register index + * This parameter can be one of the macros group @ref TMR4_PWM_Dead_Time_Register_Index + * @arg TMR4_PWM_PDAR_IDX: TMR4_PDARn + * @arg TMR4_PWM_PDBR_IDX: TMR4_PDBRn + * @retval TMR4 PWM dead time register value + */ +uint16_t TMR4_PWM_GetDeadTimeValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint32_t u32DeadTimeIndex) +{ + __I uint16_t *PDR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_PWM_DEADTIME_REG_IDX(u32DeadTimeIndex)); + + /* Get pointer of current channel PWM register address */ + PDR = TMR4_PDR(TMR4x, u32Ch, u32DeadTimeIndex); + + return READ_REG16(*PDR); +} + +/** + * @brief Set TMR4 PWM register TMR4_PSCR.OE bit effect time + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Time Effect time + * This parameter can be one of the macros group @ref TMR4_PWM_OE_Bit_Effect_Time + * @arg TMR4_PWM_OE_EFFECT_IMMED: TMR4 PWM register TMR4_PSCR.OE bit immediate effect + * @arg TMR4_PWM_OE_EFFECT_COUNT_PEAK: TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count peak + * @arg TMR4_PWM_OE_EFFECT_COUNT_VALLEY: TMR4 PWM register TMR4_PSCR.OE bit effect when TMR4 counter count valley + * @retval None + */ +void TMR4_PWM_SetOEEffectTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Time) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_OE_EFFECT(u32Time)); + + MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_ODT, u32Time); +} + +/** + * @brief Enable or disable the TMR4 PWM main output by hardware after clear EMB event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @arg ENABLE: The TMR4_PSCR.MOE bit automatically set to 1 by hardware to restore the PWM normal output. + * @arg DISABLE: The TMR4_PSCR.MOE bit can only be set to 1 by software to restore the PWM normal output. + * @retval None + */ +void TMR4_PWM_EmbHWMainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE); + } else { + CLR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE); + } +} + +/** + * @brief Enable or disable the TMR4 PWM main output function. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_PWM_MainOutputCmd(CM_TMR4_TypeDef *TMR4x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE); + } else { + CLR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE); + } +} + +/** + * @brief Set TMR4 PWM port output mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32PwmPin TMR4 PWM pin + * This parameter can be one of the macros group @ref TMR4_PWM_Pin + * @param [in] u32Mode The PWM port output mode + * This parameter can be one of the macros group @ref TMR4_PWM_Pin_Output_Mode + * @arg TMR4_PWM_PIN_OUTPUT_OS: TIM4__Oxy(x=U/V/W,y=H/L) output polarity by specified OSxy + * @arg TMR4_PWM_PIN_OUTPUT_NORMAL: TIM4__Oxy(x=U/V/W,y=H/L) output normal PWM + * @retval None + */ +void TMR4_PWM_SetPortOutputMode(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32Mode) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_PIN(u32PwmPin)); + DDL_ASSERT(IS_TMR4_PWM_PIN_MD(u32Mode)); + + MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_OExy_MASK(u32PwmPin), TMR4_PSCR_OExy(u32PwmPin, u32Mode)); +} + +/** + * @brief Set TMR4 PWM pin status when below conditions occur:1.EMB 2.MOE=0 3.MOE=1&OExy=0 + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32PwmPin TMR4 PWM pin + * This parameter can be one of the macros group @ref TMR4_PWM_Pin + * @param [in] u32PinStatus TMR4 PWM pin status + * This parameter can be one of the macros group @ref TMR4_PWM_Abnormal_Pin_Status. + * @retval None + */ +void TMR4_PWM_SetAbnormalPinStatus(CM_TMR4_TypeDef *TMR4x, uint32_t u32PwmPin, uint32_t u32PinStatus) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_PWM_ABNORMAL_PIN_STAT(u32PinStatus)); + DDL_ASSERT(IS_TMR4_PWM_PIN(u32PwmPin)); + + MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_OSxy_MASK(u32PwmPin), TMR4_PSCR_OSxy(u32PwmPin, u32PinStatus)); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_Event_Global_Functions TMR4 Event Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_tmr4_evt_init_t to default values + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_StructInit(stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + pstcTmr4EventInit->u16Mode = TMR4_EVT_MD_CMP; + pstcTmr4EventInit->u16CompareValue = 0U; + pstcTmr4EventInit->u16OutputEvent = TMR4_EVT_OUTPUT_EVT0; + pstcTmr4EventInit->u16MatchCond = 0U; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] pstcTmr4EventInit Pointer to a @ref stc_tmr4_evt_init_t structure + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcTmr4EventInit value is NULL. + */ +int32_t TMR4_EVT_Init(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, const stc_tmr4_evt_init_t *pstcTmr4EventInit) +{ + uint16_t u16Value; + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcTmr4EventInit) { + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MD(pstcTmr4EventInit->u16Mode)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(pstcTmr4EventInit->u16OutputEvent)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(pstcTmr4EventInit->u16MatchCond)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCSR register */ + u16Value = (pstcTmr4EventInit->u16Mode | pstcTmr4EventInit->u16OutputEvent | pstcTmr4EventInit->u16MatchCond); + WRITE_REG16(*SCSR, u16Value); + + /* Set SCMR register */ + WRITE_REG16(*SCMR, 0xFF00U); + + /* Set SCCR register: compare value */ + WRITE_REG16(*SCCR, pstcTmr4EventInit->u16CompareValue); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval None + */ +void TMR4_EVT_DeInit(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *SCCR; + __IO uint16_t *SCSR; + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + SCSR = TMR4_SCSR(TMR4x, u32Ch); + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Configure default parameter */ + WRITE_REG16(*SCCR, 0x0U); + WRITE_REG16(*SCSR, 0x0000U); + WRITE_REG16(*SCMR, TMR4_SCMR_RST_VALUE); +} + +/** + * @brief Set TMR4 event delay object + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Object TMR4 event delay object + * This parameter can be one of the macros group @ref TMR4_Event_Delay_Object + * @arg TMR4_EVT_DELAY_OCCRXH: TMR4 event delay object - OCCRxh + * @arg TMR4_EVT_DELAY_OCCRXL: TMR4 event delay object - OCCRxl + * @retval None + */ +void TMR4_EVT_SetDelayObject(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Object) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_DELAY_OBJECT(u16Object)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTDS, u16Object); +} + +/** + * @brief Set TMR4 event trigger event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskTime Mask times + * This parameter can be one of the macros group @ref TMR4_Event_Mask_Times + * @arg TMR4_EVT_MASK0: Mask 0 times + * @arg TMR4_EVT_MASK1: Mask 1 times + * @arg TMR4_EVT_MASK2: Mask 2 times + * @arg TMR4_EVT_MASK3: Mask 3 times + * @arg TMR4_EVT_MASK4: Mask 4 times + * @arg TMR4_EVT_MASK5: Mask 5 times + * @arg TMR4_EVT_MASK6: Mask 6 times + * @arg TMR4_EVT_MASK7: Mask 7 times + * @arg TMR4_EVT_MASK8: Mask 8 times + * @arg TMR4_EVT_MASK9: Mask 9 times + * @arg TMR4_EVT_MASK10: Mask 10 times + * @arg TMR4_EVT_MASK11: Mask 11 times + * @arg TMR4_EVT_MASK12: Mask 12 times + * @arg TMR4_EVT_MASK13: Mask 13 times + * @arg TMR4_EVT_MASK14: Mask 14 times + * @arg TMR4_EVT_MASK15: Mask 15 times + * @retval None + */ +void TMR4_EVT_SetMaskTime(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16MaskTime) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK(u16MaskTime)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + /* Set SCMR register */ + MODIFY_REG16(*SCMR, TMR4_SCMR_AMC, u16MaskTime); +} + +/** + * @brief Get TMR4 event SCCR register value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval Returned value can be one of the macros group @ref TMR4_Event_Mask_Times + * - TMR4_EVT_MASK0: Mask 0 times + * - TMR4_EVT_MASK1: Mask 1 times + * - TMR4_EVT_MASK2: Mask 2 times + * - TMR4_EVT_MASK3: Mask 3 times + * - TMR4_EVT_MASK4: Mask 4 times + * - TMR4_EVT_MASK5: Mask 5 times + * - TMR4_EVT_MASK6: Mask 6 times + * - TMR4_EVT_MASK7: Mask 7 times + * - TMR4_EVT_MASK8: Mask 8 times + * - TMR4_EVT_MASK9: Mask 9 times + * - TMR4_EVT_MASK10: Mask 10 times + * - TMR4_EVT_MASK11: Mask 11 times + * - TMR4_EVT_MASK12: Mask 12 times + * - TMR4_EVT_MASK13: Mask 13 times + * - TMR4_EVT_MASK14: Mask 14 times + * - TMR4_EVT_MASK15: Mask 15 times + */ +uint16_t TMR4_EVT_GetMaskTime(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + return READ_REG16_BIT(*SCMR, TMR4_SCMR_AMC); +} + +/** + * @brief Set TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Value SCCR register value + * @arg number of 16bit + * @retval None + */ +void TMR4_EVT_SetCompareValue(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Value) +{ + __IO uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + /* Set SCCR register */ + WRITE_REG16(*SCCR, u16Value); +} + +/** + * @brief Get TMR4 event compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @retval SCCR register value + */ +uint16_t TMR4_EVT_GetCompareValue(const CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __I uint16_t *SCCR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + SCCR = TMR4_SCCR(TMR4x, u32Ch); + + return READ_REG16(*SCCR); +} + +/** + * @brief Set TMR4 output event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Event TMR4 event output event + * This parameter can be one of the macros group @ref TMR4_Event_Output_Event + * @retval None + */ +void TMR4_EVT_SetOutputEvent(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Event) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_EVT(u16Event)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*SCSR, TMR4_SCSR_EVTOS, u16Event); +} + +/** + * @brief Set the SCCR&SCMR buffer transfer condition + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16BufCond The buffer transfer condition + * This parameter can be one of the macros group @ref TMR4_Event_Buffer_Transfer_Condition + * @arg TMR4_EVT_BUF_COND_IMMED: Register SCCR&SCMR buffer transfer when writing to the SCCR&SCMR register + * @arg TMR4_EVT_BUF_COND_VALLEY: Register SCCR&SCMR buffer transfer when counter count valley + * @arg TMR4_EVT_BUF_COND_PEAK: Register SCCR&SCMR buffer transfer when counter count peak + * @arg TMR4_EVT_BUF_COND_PEAK_VALLEY: Register SCCR&SCMR buffer transfer when counter count peak or valley + * @retval None + */ +void TMR4_EVT_SetCompareBufCond(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16BufCond) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_BUF_COND(u16BufCond)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + MODIFY_REG16(*SCSR, TMR4_SCSR_BUFEN, u16BufCond); +} + +/** + * @brief Enable or disable the buffer interval response function of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_BufIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } else { + CLR_REG16_BIT(*SCSR, TMR4_SCSR_LMC); + } +} + +/** + * @brief Enable or disable the specified interval response of TMR4 event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16MaskType The specified mask compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Mask + * @arg TMR4_EVT_MASK_VALLEY: Compare with the counter valley interrupt mask counter + * @arg TMR4_EVT_MASK_PEAK: Compare with the counter peak interrupt mask counter + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_EventIntervalResponseCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, + uint16_t u16MaskType, en_functional_state_t enNewState) +{ + __IO uint16_t *SCMR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MASK_TYPE(u16MaskType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCMR = TMR4_SCMR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCMR, u16MaskType); + } else { + CLR_REG16_BIT(*SCMR, u16MaskType); + } +} + +/** + * @brief Enable or disable the specified count compare type of TMR4 event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u32Ch TMR4 event channel + * This parameter can be one of the macros group @ref TMR4_Event_Channel + * @param [in] u16Cond The specified count compare type of TMR4 event + * This parameter can be any composed value of the macros group @ref TMR4_Event_Match_Condition + * @arg TMR4_EVT_MATCH_CNT_UP: Start event operate when match with SCCR&SCMR and TMR4 counter count up + * @arg TMR4_EVT_MATCH_CNT_DOWN: Start event operate when match with SCCR&SCMR and TMR4 counter count down + * @arg TMR4_EVT_MATCH_CNT_VALLEY: Start event operate when match with SCCR&SCMR and TMR4 counter count valley + * @arg TMR4_EVT_MATCH_CNT_PEAK: Start event operate when match with SCCR&SCMR and TMR4 counter count peak + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR4_EVT_MatchCondCmd(CM_TMR4_TypeDef *TMR4x, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + __IO uint16_t *SCSR; + + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_CH(u32Ch)); + DDL_ASSERT(IS_TMR4_EVT_MATCH_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get actual address of register list of current channel */ + SCSR = TMR4_SCSR(TMR4x, u32Ch); + + if (ENABLE == enNewState) { + SET_REG16_BIT(*SCSR, u16Cond); + } else { + CLR_REG16_BIT(*SCSR, u16Cond); + } +} + +/** + * @brief Set TMR4 event signal output to port + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg CM_TMR4 or CM_TMR4_x: TMR4 unit instance register base + * @param [in] u16Signal TMR4 event signal selection + * This parameter can be one of the macros group @ref TMR4_Event_Output_Signal + * @retval None + */ +void TMR4_EVT_SetOutputEventSignal(CM_TMR4_TypeDef *TMR4x, uint16_t u16Signal) +{ + DDL_ASSERT(IS_TMR4_UNIT(TMR4x)); + DDL_ASSERT(IS_TMR4_EVT_OUTPUT_SIGNAL(u16Signal)); + + MODIFY_REG16(TMR4x->SCER, TMR4_SCER_EVTRS, u16Signal); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LL_TMR4_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c new file mode 100644 index 0000000000..ff5dedf6d9 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmr6.c @@ -0,0 +1,1849 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmr6.c + * @brief This file provides firmware functions to manage the TMR6(TMR6). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify typo + 2023-12-15 CDT Modify for headfile update: CM_TMR6CR -> CM_TMR6_COMMON + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmr6.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMR6 TMR6 + * @brief TMR6 Driver Library + * @{ + */ + +#if (LL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Local_Macros TMR6 Local Macros + * @{ + */ + +/* Timer6 registers reset value */ +#define TMR6_REG_RST_VALUE_U32 (0xFFFFFFFFUL) +#define TMR6_REG_RST_VALUE_U16 (0xFFFFU) +#define TMR6_REG_GCONR_RST_VALUE (0x00000100UL) + +/* Define for BCONR register configuration */ +#define BCONR_FUNC_CMD_MASK (0x01UL) +#define BCONR_GEN_CFG_MASK (0x0000000EUL) +#define BCONR_GEN_CFG_CHB_OFS (0x04UL) +#define BCONR_PERIOD_CFG_MASK (0x0000000EUL) +#define BCONR_PERIOD_CFG_OFS (0x08UL) +#define BCONR_SPECIAL_CFG_MASK (0x0000000EUL) +#define BCONR_SPECIAL_CFG_CHA_OFS (0x10UL) +#define BCONR_SPECIAL_CFG_CHB_OFS (0x14UL) + +/* Define mask value for PWM output configuration for PCNAR/PCNBR register */ +#define PCNA_BR_REG_OUTPUT_CFG_MASK (0x8000FFFFUL) +#define PCNA_BR_REG_EMB_CFG_MASK (TMR6_PCNAR_EMBSA | TMR6_PCNAR_EMBRA | TMR6_PCNAR_EMBCA) +#define PCONR_REG_POLARITY_MASK (0x03UL) + +/* Define mask value for GCONR register */ +#define TMR6_INIT_MASK (TMR6_GCONR_DIR | TMR6_GCONR_MODE | TMR6_GCONR_CKDIV) +#define TMR6_ZMASK_CFG_MASK (TMR6_GCONR_ZMSKVAL | TMR6_GCONR_ZMSKPOS | TMR6_GCONR_ZMSKREV) + +/** + * @defgroup TMR6_Check_Param_Validity TMR6 Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for normal timer6 unit */ +#define IS_VALID_TMR6_UNIT(x) \ +( ((x) == CM_TMR6_1) || \ + ((x) == CM_TMR6_2)) + +/*! Parameter valid check for timer6 count source */ +#define IS_TMR6_CNT_SRC(x) \ +( ((x) == TMR6_CNT_SRC_SW) || \ + ((x) == TMR6_CNT_SRC_HW)) + +/*! Parameter valid check for interrupt source configuration */ +#define IS_VALID_IRQ(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_INT_ALL) == TMR6_INT_ALL)) + +/*! Parameter valid check for status bit read */ +#define IS_VALID_GET_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_ALL) == TMR6_FLAG_ALL)) + +/*! Parameter valid check for status bit clear */ +#define IS_VALID_CLR_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_FLAG_CLR_ALL) == TMR6_FLAG_CLR_ALL)) + +/*! Parameter valid check for period register */ +#define IS_VALID_PERIOD_REG(x) \ +( (x) <= TMR6_PERIOD_REG_C) + +/*! Parameter valid check for general compare register */ +#define IS_VALID_CMP_REG(x) \ +( (x) <= TMR6_CMP_REG_F) + +/*! Parameter valid check for general/special compare channel */ +#define IS_VALID_CNT_CH(x) \ +( ((x) == TMR6_CH_A) || \ + ((x) == TMR6_CH_B)) + +/*! Parameter valid check for buffer function number */ +#define IS_VALID_BUF_NUM(x) \ +( ((x) == TMR6_BUF_SINGLE) || \ + ((x) == TMR6_BUF_DUAL)) + +/*! Parameter valid check for buffer transfer timer configuration */ +#define IS_VALID_BUF_TRANS_TRIG(x) \ +( ((x) == TMR6_BUF_TRANS_INVD) || \ + ((x) == TMR6_BUF_TRANS_OVF) || \ + ((x) == TMR6_BUF_TRANS_UDF) || \ + ((x) == TMR6_BUF_TRANS_OVF_UDF)) + +/*! Parameter valid check for count condition for valid period function */ +#define IS_VALID_PERIOD_CNT_COND(x) \ +( ((x) == TMR6_VALID_PERIOD_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_VALLEY) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_PEAK) || \ + ((x) == TMR6_VALID_PERIOD_CNT_COND_VALLEY_PEAK)) + +/*! Parameter valid check for count condition for valid period count */ +#define IS_VALID_PERIOD_CNT(x) \ +( ((x) == TMR6_VALID_PERIOD_CNT_INVD) || \ + ((x) == TMR6_VALID_PERIOD_CNT1) || \ + ((x) == TMR6_VALID_PERIOD_CNT2) || \ + ((x) == TMR6_VALID_PERIOD_CNT3) || \ + ((x) == TMR6_VALID_PERIOD_CNT4) || \ + ((x) == TMR6_VALID_PERIOD_CNT5) || \ + ((x) == TMR6_VALID_PERIOD_CNT6) || \ + ((x) == TMR6_VALID_PERIOD_CNT7)) + +/*! Parameter valid check for count register data range */ +#define IS_VALID_REG_RANGE_U16(x) ((x) <= 0xFFFFUL) + +/*! Parameter valid check for dead time register */ +#define IS_VALID_DEADTIME_REG(x) \ +( ((x) == TMR6_DEADTIME_REG_UP_A) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_A) || \ + ((x) == TMR6_DEADTIME_REG_UP_B) || \ + ((x) == TMR6_DEADTIME_REG_DOWN_B)) + +/*! Parameter valid check for pin */ +#define IS_VALID_PIN(x) \ +( ((x) == TMR6_IO_PWMA) || \ + ((x) == TMR6_IO_PWMB) || \ + ((x) == TMR6_INPUT_TRIGA) || \ + ((x) == TMR6_INPUT_TRIGB)) + +/*! Parameter valid check for input pin filter clock */ +#define IS_VALID_FILTER_CLK(x) \ +( ((x) == TMR6_FILTER_CLK_DIV1) || \ + ((x) == TMR6_FILTER_CLK_DIV4) || \ + ((x) == TMR6_FILTER_CLK_DIV16) || \ + ((x) == TMR6_FILTER_CLK_DIV64)) + +/*! Parameter valid check for PWM pin status */ +#define IS_VALID_PWM_POLARITY(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH) || \ + ((x) == TMR6_PWM_HOLD) || \ + ((x) == TMR6_PWM_INVT)) + +/*! Parameter valid check for force PWM output pin */ +#define IS_VALID_PWM_FORCE_POLARITY(x) \ +( ((x) == TMR6_PWM_FORCE_INVD) || \ + ((x) == TMR6_PWM_FORCE_LOW) || \ + ((x) == TMR6_PWM_FORCE_HIGH)) + +/*! Parameter valid check for PWM pin status for count start and stop */ +#define IS_VALID_PWM_POLARITY_START_STOP(x) \ +( ((x) == TMR6_PWM_LOW) || \ + ((x) == TMR6_PWM_HIGH) || \ + ((x) == TMR6_PWM_HOLD)) + +#define IS_VALID_CNT_STAT(x) \ +( ((x) == TMR6_STAT_START) || \ + ((x) == TMR6_STAT_STOP) || \ + ((x) == TMR6_STAT_OVF) || \ + ((x) == TMR6_STAT_UDF) || \ + ((x) == TMR6_STAT_UP_CNT_MATCH_A) || \ + ((x) == TMR6_STAT_DOWN_CNT_MATCH_A) || \ + ((x) == TMR6_STAT_UP_CNT_MATCH_B) || \ + ((x) == TMR6_STAT_DOWN_CNT_MATCH_B)) + +/*! Parameter valid check for pin mode */ +#define IS_VALID_PIN_MD(x) \ +( ((x) == TMR6_PIN_CMP_OUTPUT) || \ + ((x) == TMR6_PIN_CAPT_INPUT)) + +/*! Parameter valid check for EMB event valid channel */ +#define IS_VALID_EMB_CH(x) ((x) == TMR6_EMB_EVT_CH0) + +/*! Parameter valid check for EMB release mode when EMB event invalid */ +#define IS_VALID_EMB_RELEASE_MD(x) \ +( ((x) == TMR6_EMB_RELEASE_IMMED) || \ + ((x) == TMR6_EMB_RELEASE_OVF) || \ + ((x) == TMR6_EMB_RELEASE_UDF) || \ + ((x) == TMR6_EMB_RELEASE_OVF_UDF)) + +/*! Parameter valid check for pin output status when EMB event valid */ +#define IS_VALID_EMB_VALID_PIN_POLARITY(x) \ +( ((x) == TMR6_EMB_PIN_NORMAL) || \ + ((x) == TMR6_EMB_PIN_HIZ) || \ + ((x) == TMR6_EMB_PIN_LOW) || \ + ((x) == TMR6_EMB_PIN_HIGH)) + +/*! Parameter valid check for dead time buffer function for DTUAR and DTUBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_UP_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_UP_BUF_ON)) + +/*! Parameter valid check for dead time buffer function for DTDAR and DTDBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(x) \ +( ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_OFF) || \ + ((x) == TMR6_DEADTIME_CNT_DOWN_BUF_ON)) + +/*! Parameter valid check for dead time buffer transfer condition */ +#define IS_VALID_DEADTIME_BUF_TRANS_COND_REG(x) \ +( ((x) == TMR6_DEADTIME_BUF_COND_INVD) || \ + ((x) == TMR6_DEADTIME_BUF_COND_OVF) || \ + ((x) == TMR6_DEADTIME_BUF_COND_UDF) || \ + ((x) == TMR6_DEADTIME_BUF_COND_OVF_UDF)) + +/*! Parameter valid check for dead time equal function for DTUAR and DTDAR register */ +#define IS_VALID_DEADTIME_EQUAL_FUNC_REG(x) \ +( ((x) == TMR6_DEADTIME_EQUAL_OFF) || \ + ((x) == TMR6_DEADTIME_EQUAL_ON)) + +/*! Parameter valid check for start condition */ +#define IS_VALID_START_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_START_COND_ALL) == TMR6_START_COND_ALL)) + +/*! Parameter valid check for stop condition */ +#define IS_VALID_STOP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_STOP_COND_ALL) == TMR6_STOP_COND_ALL)) + +/*! Parameter valid check for clear condition */ +#define IS_VALID_CLR_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CLR_COND_ALL) == TMR6_CLR_COND_ALL)) + +/*! Parameter valid check for update condition */ +#define IS_VALID_UPD_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_UPD_COND_ALL) == TMR6_UPD_COND_ALL)) + +/*! Parameter valid check for capture condition */ +#define IS_VALID_CAPT_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CAPT_COND_ALL) == TMR6_CAPT_COND_ALL)) + +/*! Parameter valid check for hardware count up condition */ +#define IS_VALID_CNT_UP_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_UP_COND_ALL) == TMR6_CNT_UP_COND_ALL)) + +/*! Parameter valid check for hardware count down condition */ +#define IS_VALID_CNT_DOWN_COND(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_CNT_DOWN_COND_ALL) == TMR6_CNT_DOWN_COND_ALL)) + +/*! Parameter valid check for count Mode */ +#define IS_VALID_CNT_MD(x) \ +( ((x) == TMR6_MD_SAWTOOTH) || \ + ((x) == TMR6_MD_TRIANGLE)) + +/*! Parameter valid check for count direction */ +#define IS_VALID_CNT_DIR(x) \ +( ((x) == TMR6_CNT_UP) || \ + ((x) == TMR6_CNT_DOWN)) + +/*! Parameter valid check for count clock division */ +#define IS_VALID_CNT_CLK_DIV(x) \ +( ((x) == TMR6_CLK_DIV1) || \ + ((x) == TMR6_CLK_DIV2) || \ + ((x) == TMR6_CLK_DIV4) || \ + ((x) == TMR6_CLK_DIV8) || \ + ((x) == TMR6_CLK_DIV16) || \ + ((x) == TMR6_CLK_DIV32) || \ + ((x) == TMR6_CLK_DIV64) || \ + ((x) == TMR6_CLK_DIV128) || \ + ((x) == TMR6_CLK_DIV256) || \ + ((x) == TMR6_CLK_DIV512) || \ + ((x) == TMR6_CLK_DIV1024)) + +/*! Parameter valid check for count reload mode */ +#define IS_VALID_CNT_RELOAD_MD(x) \ +( ((x) == TMR6_CNT_RELOAD_ON) || \ + ((x) == TMR6_CNT_RELOAD_OFF)) + +/*! Parameter valid check for Z Mask input function mask cycles number */ +#define IS_VALID_ZMASK_CYCLES(x) \ +( ((x) == TMR6_ZMASK_FUNC_INVD) || \ + ((x) == TMR6_ZMASK_CYCLE_4) || \ + ((x) == TMR6_ZMASK_CYCLE_8) || \ + ((x) == TMR6_ZMASK_CYCLE_16)) + +/*! Parameter valid check for Z Mask function of timer6 position unit */ +#define IS_VALID_POS_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_POS_CLR_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_POS_CLR_ZMASK_FUNC_ON)) + +/*! Parameter valid check for Z Mask function of timer6 revolution unit */ +#define IS_VALID_REVO_UNIT_ZMASK_FUNC(x) \ +( ((x) == TMR6_REVO_CNT_ZMASK_FUNC_OFF) || \ + ((x) == TMR6_REVO_CNT_ZMASK_FUNC_ON)) + +/*! Parameter valid check for software sync control unit */ +#define IS_VALID_SW_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_SW_SYNC_ALL) == TMR6_SW_SYNC_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR6_Global_Functions TMR6 Global Functions + * @{ + */ + +/** + * @brief Initialize the timer6 count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcTmr6Init Pointer of configuration structure @ref stc_tmr6_init_t + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_Init(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcTmr6Init) { + /* Check parameters */ + DDL_ASSERT(IS_TMR6_CNT_SRC(pstcTmr6Init->u8CountSrc)); + + if (pstcTmr6Init->u8CountSrc == TMR6_CNT_SRC_SW) { + /* Normal count */ + DDL_ASSERT(IS_VALID_CNT_MD(pstcTmr6Init->sw_count.u32CountMode)); + DDL_ASSERT(IS_VALID_CNT_DIR(pstcTmr6Init->sw_count.u32CountDir)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(pstcTmr6Init->sw_count.u32ClockDiv)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_INIT_MASK, (pstcTmr6Init->sw_count.u32CountMode | pstcTmr6Init->sw_count.u32CountDir | \ + pstcTmr6Init->sw_count.u32ClockDiv)); + } else { + /* Hardware count */ + DDL_ASSERT(IS_VALID_CNT_UP_COND(pstcTmr6Init->hw_count.u32CountUpCond) || + (pstcTmr6Init->hw_count.u32CountUpCond == TMR6_CNT_UP_COND_INVD)); + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(pstcTmr6Init->hw_count.u32CountDownCond) || + (pstcTmr6Init->hw_count.u32CountDownCond == TMR6_CNT_DOWN_COND_INVD)); + + WRITE_REG32(TMR6x->HCUPR, pstcTmr6Init->hw_count.u32CountUpCond); + WRITE_REG32(TMR6x->HCDOR, pstcTmr6Init->hw_count.u32CountDownCond); + } + + DDL_ASSERT(IS_VALID_CNT_RELOAD_MD(pstcTmr6Init->u32CountReload)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_OVSTP, pstcTmr6Init->u32CountReload); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcTmr6Init->u32PeriodValue)); + WRITE_REG32(TMR6x->PERAR, pstcTmr6Init->u32PeriodValue); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set timer6 base count mode + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Mode @ref TMR6_Count_Mode_Define + * @retval None + */ +void TMR6_SetCountMode(CM_TMR6_TypeDef *TMR6x, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_MD(u32Mode)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_MODE, u32Mode); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Dir @ref TMR6_Count_Dir_Define + * @retval None + */ +void TMR6_SetCountDir(CM_TMR6_TypeDef *TMR6x, uint32_t u32Dir) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DIR(u32Dir)); + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_DIR, u32Dir); +} + +/** + * @brief Set timer6 base count direction + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Count direction @ref TMR6_Count_Dir_Status_Define + */ +uint32_t TMR6_GetCountDir(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + return READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_DIRF); +} + +/** + * @brief Set timer6 clock division + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Div @ref TMR6_Count_Clock_Define + * @retval None + */ +void TMR6_SetClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CLK_DIV(u32Div)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_GCONR_CKDIV, u32Div); +} + +/** + * @brief Timer6 count reload function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_CountReloadCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_OVSTP); + } else { + SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_OVSTP); + } +} + +/** + * @brief Hardware increase condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Up_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWCountUpCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_UP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCUPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCUPR, u32Cond); + } +} + +/** + * @brief Hardware decrease condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_HW_Count_Down_Cond_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWCountDownCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_DOWN_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCDOR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCDOR, u32Cond); + } +} + +/** + * @brief Initialize the timer6 hardware count function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] pstcPwmInit Pointer of initialize structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_Init(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t *TMR6_GCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Ch); + + if (NULL != pstcPwmInit) { + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StartPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY_START_STOP(pstcPwmInit->u32StopPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountDownMatchBPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountUpMatchBPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountDownMatchAPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32CountUpMatchAPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32UdfPolarity)); + DDL_ASSERT(IS_VALID_PWM_POLARITY(pstcPwmInit->u32OvfPolarity)); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(pstcPwmInit->u32CompareValue)); + WRITE_REG32(*TMR6_GCMxR, pstcPwmInit->u32CompareValue); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, PCNA_BR_REG_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CountDownMatchBPolarity << TMR6_PCNAR_CMBDCA_POS \ + | pstcPwmInit->u32CountUpMatchBPolarity << TMR6_PCNAR_CMBUCA_POS \ + | pstcPwmInit->u32CountDownMatchAPolarity << TMR6_PCNAR_CMADCA_POS \ + | pstcPwmInit->u32CountUpMatchAPolarity << TMR6_PCNAR_CMAUCA_POS \ + | pstcPwmInit->u32UdfPolarity << TMR6_PCNAR_UDFCA_POS \ + | pstcPwmInit->u32OvfPolarity << TMR6_PCNAR_OVFCA_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCNAR_STPCA_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCNAR_STACA_POS); + } else { + MODIFY_REG32(TMR6x->PCNBR, PCNA_BR_REG_OUTPUT_CFG_MASK, \ + pstcPwmInit->u32CountDownMatchBPolarity << TMR6_PCNBR_CMBDCB_POS \ + | pstcPwmInit->u32CountUpMatchBPolarity << TMR6_PCNBR_CMBUCB_POS \ + | pstcPwmInit->u32CountDownMatchAPolarity << TMR6_PCNBR_CMADCB_POS \ + | pstcPwmInit->u32CountUpMatchAPolarity << TMR6_PCNBR_CMAUCB_POS \ + | pstcPwmInit->u32UdfPolarity << TMR6_PCNBR_UDFCB_POS \ + | pstcPwmInit->u32OvfPolarity << TMR6_PCNBR_OVFCB_POS \ + | pstcPwmInit->u32StopPolarity << TMR6_PCNBR_STPCB_POS \ + | pstcPwmInit->u32StartPolarity << TMR6_PCNBR_STACB_POS); + } + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 PWM output command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PWM_OutputCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32Tmp; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + u32Tmp = 0xFFFFFFFFUL; + } else { + u32Tmp = 0UL; + } + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_OUTENA, u32Tmp); + } else { + MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_OUTENB, u32Tmp); + } +} + +/** + * @brief Timer6 set pin polarity + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32CountState Polarity set for @ref TMR6_Count_State_Define + * @param [in] u32Polarity @ref TMR6_Pin_Polarity_Define + * @retval None + */ +void TMR6_PWM_SetPolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32CountState, uint32_t u32Polarity) +{ + uint32_t u32PolarityMask = PCONR_REG_POLARITY_MASK; + + uint8_t au8Pos[8] = {TMR6_PCNAR_STACA_POS, TMR6_PCNAR_STPCA_POS, TMR6_PCNAR_OVFCA_POS, TMR6_PCNAR_UDFCA_POS, \ + TMR6_PCNAR_CMAUCA_POS, TMR6_PCNAR_CMADCA_POS, TMR6_PCNAR_CMBUCA_POS, TMR6_PCNAR_CMBDCA_POS + }; + DDL_ASSERT(IS_VALID_PWM_POLARITY(u32Polarity)); + DDL_ASSERT(IS_VALID_CNT_STAT(u32CountState)); + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + + u32Polarity <<= au8Pos[u32CountState]; + u32PolarityMask <<= au8Pos[u32CountState]; + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, u32PolarityMask, u32Polarity); + } else { + MODIFY_REG32(TMR6x->PCNBR, u32PolarityMask, u32Polarity); + } +} + +/** + * @brief Timer6 set force polarity when next period + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch @ref TMR6_Count_Ch_Define + * @param [in] u32Polarity @ref TMR6_Force_Output_Polarity_Define + * @retval None + */ +void TMR6_PWM_SetForcePolarity(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Polarity) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PWM_FORCE_POLARITY(u32Polarity)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_FORCA, u32Polarity << TMR6_PCNAR_FORCA_POS); + } else { + MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_FORCB, u32Polarity << TMR6_PCNBR_FORCB_POS); + } +} + +/** + * @brief Hardware capture condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Input pin select @ref TMR6_Count_Ch_Define + * @param [in] u32Cond Events source for hardware capture, maybe one or any combination of the parameter + * @ref TMR6_hardware_capture_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWCaptureCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + __IO uint32_t *HCPxR; + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_CAPT_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + HCPxR = (__IO uint32_t *)((uint32_t)&TMR6x->HCPAR + (u32Ch * 4UL)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(*HCPxR, u32Cond); + } else { + CLR_REG32_BIT(*HCPxR, u32Cond); + } +} + +/** + * @brief Port input filter function configuration(Trig) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Pin to be configured @ref TMR6_Pin_Define + * @param [in] u32Div Filter clock @ref TMR6_Input_Filter_Clock + * @retval None + */ +void TMR6_SetFilterClockDiv(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, uint32_t u32Div) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_VALID_FILTER_CLK(u32Div)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFICKGA, u32Div << TMR6_FCNGR_NOFICKGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFICKGB, u32Div << TMR6_FCNGR_NOFICKGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFICKTA, u32Div << TMR6_COMMON_FCNTR_NOFICKTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFICKTB, u32Div << TMR6_COMMON_FCNTR_NOFICKTB_POS); + break; + default: + break; + } +} + +/** + * @brief Port input filter function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Pin Input port to be configured @ref TMR6_Pin_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_FilterCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Pin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PIN(u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + switch (u32Pin) { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFIENGA, ((uint32_t)enNewState) << TMR6_FCNGR_NOFIENGA_POS); + break; + case TMR6_IO_PWMB: + MODIFY_REG32(TMR6x->FCNGR, TMR6_FCNGR_NOFIENGB, ((uint32_t)enNewState) << TMR6_FCNGR_NOFIENGB_POS); + break; + case TMR6_INPUT_TRIGA: + MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFIENTA, ((uint32_t)enNewState) << TMR6_COMMON_FCNTR_NOFIENTA_POS); + break; + case TMR6_INPUT_TRIGB: + MODIFY_REG32(CM_TMR6_COMMON->FCNTR, TMR6_COMMON_FCNTR_NOFIENTB, ((uint32_t)enNewState) << TMR6_COMMON_FCNTR_NOFIENTB_POS); + break; + default: + break; + } +} + +/** + * @brief Set channel function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] u32Func IO mode @ref TMR6_Pin_Mode_Define + * @retval None + */ +void TMR6_SetFunc(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, uint32_t u32Func) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_PIN_MD(u32Func)); + + switch (u32Ch) { + case TMR6_CH_A: + MODIFY_REG32(TMR6x->PCNAR, TMR6_PCNAR_CAPMDA, u32Func); + break; + case TMR6_CH_B: + MODIFY_REG32(TMR6x->PCNBR, TMR6_PCNBR_CAPMDB, u32Func); + break; + default: + break; + } +} + +/** + * @brief Timer6 interrupt enable or disable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32IntType Irq flag, Can be one or any combination of the values from + * @ref TMR6_Int_Flag_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_IntCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->ICONR, u32IntType); + } else { + CLR_REG32_BIT(TMR6x->ICONR, u32IntType); + } +} + +/** + * @brief Get Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMR6_GetStatus(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + en_flag_status_t enStatus = RESET; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_GET_FLAG(u32Flag)); + + if (0UL != READ_REG32_BIT(TMR6x->STFLR, u32Flag)) { + enStatus = SET; + } + return enStatus; +} + +/** + * @brief Clear Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Flag Status bit to be read, Can be one or any combination of the values from + * @ref TMR6_Stat_Flag_Define + * @retval None + */ +void TMR6_ClearStatus(CM_TMR6_TypeDef *TMR6x, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_FLAG(u32Flag)); + + CLR_REG32_BIT(TMR6x->STFLR, u32Flag); +} + +/** + * @brief Get Timer6 period number when valid period function enable + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for periods number + */ +uint32_t TMR6_GetPeriodNum(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return (READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_VPERNUM) >> TMR6_STFLR_VPERNUM_POS); +} + +/** + * @brief De-initialize the timer6 unit + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_DeInit(CM_TMR6_TypeDef *TMR6x) +{ + uint32_t u32RefRegResetValue; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + u32RefRegResetValue = TMR6_REG_RST_VALUE_U16; + + WRITE_REG32(TMR6x->GCONR, TMR6_REG_GCONR_RST_VALUE); + WRITE_REG32(TMR6x->CNTER, 0UL); + WRITE_REG32(TMR6x->PERAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->PERBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->PERCR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMCR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMDR, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMER, u32RefRegResetValue); + WRITE_REG32(TMR6x->GCMFR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMCR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMDR, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMER, u32RefRegResetValue); + WRITE_REG32(TMR6x->SCMFR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTUAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTDAR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTUBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->DTDBR, u32RefRegResetValue); + WRITE_REG32(TMR6x->ICONR, 0UL); + WRITE_REG32(TMR6x->BCONR, 0UL); + WRITE_REG32(TMR6x->DCONR, 0UL); + WRITE_REG32(TMR6x->PCNAR, 0UL); + WRITE_REG32(TMR6x->PCNBR, 0UL); + WRITE_REG32(TMR6x->FCNGR, 0UL); + WRITE_REG32(CM_TMR6_COMMON->FCNTR, 0UL); + WRITE_REG32(TMR6x->VPERR, 0UL); + WRITE_REG32(TMR6x->STFLR, 0UL); + WRITE_REG32(TMR6x->HSTAR, 0UL); + WRITE_REG32(TMR6x->HSTPR, 0UL); + WRITE_REG32(TMR6x->HCLRR, 0UL); + WRITE_REG32(TMR6x->HUPDR, 0UL); + WRITE_REG32(TMR6x->HCPAR, 0UL); + WRITE_REG32(TMR6x->HCPBR, 0UL); + WRITE_REG32(TMR6x->HCUPR, 0UL); + WRITE_REG32(TMR6x->HCDOR, 0UL); + + WRITE_REG32(CM_TMR6_COMMON->SSTAR, 0UL); + WRITE_REG32(CM_TMR6_COMMON->SSTPR, 0UL); + WRITE_REG32(CM_TMR6_COMMON->SCLRR, 0UL); + WRITE_REG32(CM_TMR6_COMMON->SUPDR, 0UL); +} + +/** + * @brief Timer6 count start + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Start(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 count stop + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval None + */ +void TMR6_Stop(CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + CLR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); +} + +/** + * @brief Timer6 counter register set + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetCountValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(TMR6x->CNTER, u32Value); +} + +/** + * @brief Timer6 update register set + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetUpdateValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(TMR6x->UPDAR, u32Value); +} + +/** + * @brief Timer6 get counter register value + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for the count register value + */ +uint32_t TMR6_GetCountValue(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->CNTER); +} + +/** + * @brief Timer6 get update register value + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @retval uint32_t Data for register value + */ +uint32_t TMR6_GetUpdateValue(const CM_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->UPDAR); +} + +/** + * @brief Timer6 set period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @param [in] u32Value Period value for write + * @retval None + */ +void TMR6_SetPeriodValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_PERxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + + TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_PERxR, u32Value); +} + +/** + * @brief Timer6 set general compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_GCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_GCMxR, u32Value); +} + +/** + * @brief Timer6 set special compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_Compare_Reg_Index_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetSpecialCompareValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_SCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_SCMxR, u32Value); +} + +/** + * @brief Timer6 set dead time register + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be write, @ref TMR6_DeadTime_Reg_Define + * @param [in] u32Value Value for write + * @retval None + */ +void TMR6_SetDeadTimeValue(CM_TMR6_TypeDef *TMR6x, uint32_t u32Index, uint32_t u32Value) +{ + __IO uint32_t *TMR6_DTxyR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG32(*TMR6_DTxyR, u32Value); +} + +/** + * @brief Timer6 get general compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index General compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_GCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_GCMxR = (uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_GCMxR); +} + +/** + * @brief Timer6 get special compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Special compare register to be read, @ref TMR6_Compare_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetSpecialCompareValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_SCMxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32Index)); + TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32Index); + + return READ_REG32(*TMR6_SCMxR); +} + +/** + * @brief Timer6 Get period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Period register to be write, @ref TMR6_Period_Reg_Index_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetPeriodValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_PERxR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32Index)); + TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32Index); + + return READ_REG32(*TMR6_PERxR); +} + +/** + * @brief Timer6 get dead time register + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Index Dead time register to be write, @ref TMR6_DeadTime_Reg_Define + * @retval uint32_t Data for value of the register + */ +uint32_t TMR6_GetDeadTimeValue(const CM_TMR6_TypeDef *TMR6x, uint32_t u32Index) +{ + __IO uint32_t *TMR6_DTxyR; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32Index)); + TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32Index); + + return READ_REG32(*TMR6_DTxyR); +} + +/** + * @brief Timer6 general compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_GeneralBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK, (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond)); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_GEN_CFG_MASK << BCONR_GEN_CFG_CHB_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_GEN_CFG_CHB_OFS); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 general compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_GeneralBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK, enNewState); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_GEN_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_GEN_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 special compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Special compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_SpecialBufConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_SPECIAL_CFG_CHA_OFS); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_SPECIAL_CFG_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_SPECIAL_CFG_CHB_OFS); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 special compare buffer function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_SpecialBufCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHA_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHA_OFS); + } else { + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_SPECIAL_CFG_CHB_OFS, \ + ((uint32_t)enNewState) << BCONR_SPECIAL_CFG_CHB_OFS); + } +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcBufConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PeriodBufConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcBufConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_BUF_NUM(pstcBufConfig->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TRIG(pstcBufConfig->u32BufTransCond)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_PERIOD_CFG_MASK << BCONR_PERIOD_CFG_OFS, \ + (pstcBufConfig->u32BufNum | pstcBufConfig->u32BufTransCond) << BCONR_PERIOD_CFG_OFS); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 period buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_PeriodBufCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->BCONR, BCONR_FUNC_CMD_MASK << BCONR_PERIOD_CFG_OFS, + ((uint32_t)enNewState) << BCONR_PERIOD_CFG_OFS); +} + +/** + * @brief Timer6 valid period function configuration for special compare function + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcValidperiodConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + if (NULL != pstcValidperiodConfig) { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_CNT_COND(pstcValidperiodConfig->u32CountCond)); + DDL_ASSERT(IS_VALID_PERIOD_CNT(pstcValidperiodConfig->u32PeriodInterval)); + + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_PCNTS | TMR6_VPERR_PCNTE, \ + pstcValidperiodConfig->u32CountCond | pstcValidperiodConfig->u32PeriodInterval); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Timer6 valid period function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch General compare buffer chose, @ref TMR6_Count_Ch_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_ValidPeriodCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (TMR6_CH_A == u32Ch) { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIA, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIA_POS); + } else { + MODIFY_REG32(TMR6x->VPERR, TMR6_VPERR_SPPERIB, ((uint32_t)enNewState) << TMR6_VPERR_SPPERIB_POS); + } +} + +/** + * @brief Timer6 dead time function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_DeadTimeFuncCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } else { + CLR_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } +} + +/** + * @brief DeadTime function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcDeadTimeConfig Timer6 dead time config pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcDeadTimeConfig) { + DDL_ASSERT(IS_VALID_DEADTIME_EQUAL_FUNC_REG(pstcDeadTimeConfig->u32EqualUpDown)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(pstcDeadTimeConfig->u32BufUp)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(pstcDeadTimeConfig->u32BufDown)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_TRANS_COND_REG(pstcDeadTimeConfig->u32BufTransCond)); + + WRITE_REG32(TMR6x->DCONR, pstcDeadTimeConfig->u32EqualUpDown | pstcDeadTimeConfig->u32BufUp \ + | pstcDeadTimeConfig->u32BufDown | pstcDeadTimeConfig->u32BufTransCond); + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Timer6 unit Z phase input mask config + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] pstcZMaskConfig Pointer of configuration structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfig(CM_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcZMaskConfig) { + DDL_ASSERT(IS_VALID_ZMASK_CYCLES(pstcZMaskConfig->u32ZMaskCycle)); + DDL_ASSERT(IS_VALID_POS_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32PosCountMaskFunc)); + DDL_ASSERT(IS_VALID_REVO_UNIT_ZMASK_FUNC(pstcZMaskConfig->u32RevoCountMaskFunc)); + + MODIFY_REG32(TMR6x->GCONR, TMR6_ZMASK_CFG_MASK, pstcZMaskConfig->u32ZMaskCycle | \ + pstcZMaskConfig->u32PosCountMaskFunc | pstcZMaskConfig->u32RevoCountMaskFunc); + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief EMB function configuration + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Ch Channel to be configured @ref TMR6_Count_Ch_Define + * @param [in] pstcEmbConfig Point EMB function Config Pointer + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfig(CM_TMR6_TypeDef *TMR6x, uint32_t u32Ch, const stc_tmr6_emb_config_t *pstcEmbConfig) +{ + __IO uint32_t *PCNXR; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcEmbConfig) { + DDL_ASSERT(IS_VALID_CNT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_EMB_CH(pstcEmbConfig->u32ValidCh)); + DDL_ASSERT(IS_VALID_EMB_RELEASE_MD(pstcEmbConfig->u32ReleaseMode)); + DDL_ASSERT(IS_VALID_EMB_VALID_PIN_POLARITY(pstcEmbConfig->u32PinStatus)); + + if (TMR6_CH_A == u32Ch) { + PCNXR = (__IO uint32_t *)&TMR6x->PCNAR; + } else { + PCNXR = (__IO uint32_t *)&TMR6x->PCNBR; + } + + MODIFY_REG32(*PCNXR, PCNA_BR_REG_EMB_CFG_MASK, pstcEmbConfig->u32ValidCh | pstcEmbConfig->u32ReleaseMode + | pstcEmbConfig->u32PinStatus); + i32Ret = LL_OK; + } + return i32Ret; + +} + +/** + * @brief Software Sync Start + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStart(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6_COMMON->SSTAR, u32Unit); +} + +/** + * @brief Software Sync Stop + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncStop(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6_COMMON->SSTPR, u32Unit); +} + +/** + * @brief Software Sync clear + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncClear(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6_COMMON->SCLRR, u32Unit); +} + +/** + * @brief Software Sync update + * @param [in] u32Unit Software Sync units, This parameter can be one or any combination of the parameter + * @ref TMR6_SW_Sync_Unit_define + * @retval None + */ +void TMR6_SWSyncUpdate(uint32_t u32Unit) +{ + DDL_ASSERT(IS_VALID_SW_UNIT(u32Unit)); + WRITE_REG32(CM_TMR6_COMMON->SUPDR, u32Unit); +} + +/** + * @brief Hardware start function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStartCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTAR, TMR6_HSTAR_STAS, ((uint32_t)enNewState) << TMR6_HSTAR_STAS_POS); +} + +/** + * @brief Hardware stop function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStopCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTPR, TMR6_HSTPR_STPS, ((uint32_t)enNewState) << TMR6_HSTPR_STPS_POS); +} + +/** + * @brief Hardware clear function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWClearCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HCLRR, TMR6_HCLRR_CLES, ((uint32_t)enNewState) << TMR6_HCLRR_CLES_POS); +} + +/** + * @brief Hardware update function command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWUpdateCmd(CM_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HUPDR, TMR6_HUPDR_UPDS, ((uint32_t)enNewState) << TMR6_HUPDR_UPDS_POS); +} + +/** + * @brief Hardware start condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware start, maybe one or any combination of the parameter + * @ref TMR6_hardware_start_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStartCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_START_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTAR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTAR, u32Cond); + } +} + +/** + * @brief Hardware stop condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware stop, maybe one or any combination of the parameter + * @ref TMR6_hardware_stop_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWStopCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STOP_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HSTPR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HSTPR, u32Cond); + } +} + +/** + * @brief Hardware clear condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware clear, maybe one or any combination of the parameter + * @ref TMR6_hardware_clear_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWClearCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CLR_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HCLRR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HCLRR, u32Cond); + } +} + +/** + * @brief Hardware update condition command + * @param [in] TMR6x Timer6 unit + * @arg CM_TMR6_x + * @param [in] u32Cond Events source for hardware update, maybe one or any combination of the parameter + * @ref TMR6_hardware_update_condition_Define + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMR6_HWUpdateCondCmd(CM_TMR6_TypeDef *TMR6x, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_UPD_COND(u32Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(TMR6x->HUPDR, u32Cond); + } else { + CLR_REG32_BIT(TMR6x->HUPDR, u32Cond); + } +} + +/** + * @brief Set the fields of structure stc_tmr6_init_t to default values + * @param [out] pstcTmr6Init Pointer to a @ref stc_tmr6_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_StructInit(stc_tmr6_init_t *pstcTmr6Init) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegResetValue; + + /* Check structure pointer */ + if (NULL != pstcTmr6Init) { + pstcTmr6Init->u8CountSrc = TMR6_CNT_SRC_SW; + pstcTmr6Init->sw_count.u32ClockDiv = TMR6_CLK_DIV1; + pstcTmr6Init->sw_count.u32CountMode = TMR6_MD_SAWTOOTH; + pstcTmr6Init->sw_count.u32CountDir = TMR6_CNT_UP; + pstcTmr6Init->hw_count.u32CountUpCond = TMR6_CNT_UP_COND_INVD; + pstcTmr6Init->hw_count.u32CountDownCond = TMR6_CNT_DOWN_COND_INVD; + u32RefRegResetValue = TMR6_REG_RST_VALUE_U16; + pstcTmr6Init->u32CountReload = TMR6_CNT_RELOAD_ON; + pstcTmr6Init->u32PeriodValue = u32RefRegResetValue; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_buf_config_t to default values + * @param [out] pstcBufConfig Pointer to a @ref stc_tmr6_buf_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_BufFuncStructInit(stc_tmr6_buf_config_t *pstcBufConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcBufConfig) { + pstcBufConfig->u32BufNum = TMR6_BUF_SINGLE; + pstcBufConfig->u32BufTransCond = TMR6_BUF_TRANS_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_valid_period_config_t to default values + * @param [out] pstcValidperiodConfig Pointer to a @ref stc_tmr6_valid_period_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_config_t *pstcValidperiodConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcValidperiodConfig) { + pstcValidperiodConfig->u32CountCond = TMR6_VALID_PERIOD_INVD; + pstcValidperiodConfig->u32PeriodInterval = TMR6_VALID_PERIOD_CNT_INVD; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_emb_config_t to default values + * @param [out] pstcEmbConfig Pointer to a @ref stc_tmr6_emb_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_EMBConfigStructInit(stc_tmr6_emb_config_t *pstcEmbConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcEmbConfig) { + pstcEmbConfig->u32ValidCh = TMR6_EMB_EVT_CH0; + pstcEmbConfig->u32ReleaseMode = TMR6_EMB_RELEASE_IMMED; + pstcEmbConfig->u32PinStatus = TMR6_EMB_PIN_NORMAL; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_deadtime_config_t to default values + * @param [out] pstcDeadTimeConfig Pointer to a @ref stc_tmr6_deadtime_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_DeadTimeStructInit(stc_tmr6_deadtime_config_t *pstcDeadTimeConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcDeadTimeConfig) { + pstcDeadTimeConfig->u32EqualUpDown = TMR6_DEADTIME_EQUAL_OFF; + pstcDeadTimeConfig->u32BufUp = TMR6_DEADTIME_CNT_UP_BUF_OFF; + pstcDeadTimeConfig->u32BufDown = TMR6_DEADTIME_CNT_DOWN_BUF_OFF; + pstcDeadTimeConfig->u32BufTransCond = TMR6_DEADTIME_BUF_COND_INVD; + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_zmask_config_t to default values + * @param [out] pstcZMaskConfig Pointer to a @ref stc_tmr6_zmask_config_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_ZMaskConfigStructInit(stc_tmr6_zmask_config_t *pstcZMaskConfig) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + /* Check structure pointer */ + if (NULL != pstcZMaskConfig) { + pstcZMaskConfig->u32ZMaskCycle = TMR6_ZMASK_FUNC_INVD; + pstcZMaskConfig->u32PosCountMaskFunc = TMR6_POS_CLR_ZMASK_FUNC_OFF; + pstcZMaskConfig->u32RevoCountMaskFunc = TMR6_REVO_CNT_ZMASK_FUNC_OFF; + + i32Ret = LL_OK; + } + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_tmr6_pwm_init_t to default values + * @param [out] pstcPwmInit Pointer to a @ref stc_tmr6_pwm_init_t structure + * @retval int32_t: + * - LL_OK: Successfully done + * - LL_ERR_INVD_PARAM: Parameter error + */ +int32_t TMR6_PWM_StructInit(stc_tmr6_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32RefRegResetValue; + + /* Check structure pointer */ + if (NULL != pstcPwmInit) { + pstcPwmInit->u32StartPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32StopPolarity = TMR6_PWM_LOW; + + u32RefRegResetValue = TMR6_REG_RST_VALUE_U32; + pstcPwmInit->u32CountDownMatchBPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32CountUpMatchBPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32CountDownMatchAPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32CountUpMatchAPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32UdfPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32OvfPolarity = TMR6_PWM_LOW; + pstcPwmInit->u32CompareValue = u32RefRegResetValue; + i32Ret = LL_OK; + } + return i32Ret; +} +/** + * @} + */ + +#endif /* LL_TMR6_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c new file mode 100644 index 0000000000..03a8848d0a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_tmra.c @@ -0,0 +1,1206 @@ +/** + ******************************************************************************* + * @file hc32_ll_tmra.c + * @brief This file provides firmware functions to manage the TMRA(TimerA). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_tmra.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TMRA TMRA + * @brief TMRA Driver Library + * @{ + */ + +#if (LL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Local_Macros TMRA Local Macros + * @{ + */ +/** + * @defgroup TMRA_Registers_Setting_definition TMRA Registers setting definition + * @{ + */ +#define TMRA_REG_TYPE uint32_t +#define TMRA_REG_VALUE_MAX (0xFFFFFFFFUL) + +#define SET_VAL_BY_ADDR(addr, v) (*(__IO TMRA_REG_TYPE *)(addr)) = (TMRA_REG_TYPE)(v) +#define GET_VAL_BY_ADDR(addr) (*(__IO TMRA_REG_TYPE *)(addr)) +/** + * @} + */ + +/** + * @defgroup TMRA_Configuration_Bit_Mask TMRA Configuration Bit Mask + * @{ + */ +#define TMRA_BCSTRH_INT_MASK (TMRA_BCSTRH_ITENUDF | TMRA_BCSTRH_ITENOVF) +#define TMRA_BCSTRH_FLAG_MASK (TMRA_BCSTRH_UDFF | TMRA_BCSTRH_OVFF) +#define TMRA_FCONR_FILTER_CLK_MASK (0x3UL) +#define TMRA_CCONR_FILTER_CLK_MASK (TMRA_CCONR_NOFICKCP) +#define TMRA_PWM_POLARITY_MASK (TMRA_PCONR_STAC) +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Pin_Max TMRA Pin With Filter Max + * @{ + */ +#define TMRA_PIN_MAX (TMRA_PIN_PWM8) +/** + * @} + */ + +/** + * @defgroup TMRA_Check_Parameters_Validity TMRA check parameters validity + * @{ + */ +#define IS_TMRA_BIT_MASK(x, mask) (((x) != 0U) && (((x) | (mask)) == (mask))) + +#define IS_TMRA_UNIT(x) \ +( ((x) == CM_TMRA_1) || \ + ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_3) || \ + ((x) == CM_TMRA_4) || \ + ((x) == CM_TMRA_5)) + +#define IS_TMRA_SYNC_UNIT(x) (((x) == CM_TMRA_2) || ((x) == CM_TMRA_4)) + +#define IS_TMRA_SYM_UNIT(x) \ +( ((x) == CM_TMRA_1) || \ + ((x) == CM_TMRA_2) || \ + ((x) == CM_TMRA_3) || \ + ((x) == CM_TMRA_4)) + +#define IS_TMRA_CH(x) ((x) <= TMRA_CH8) + +#define IS_TMRA_UNIT_CH(unit, ch) (IS_TMRA_UNIT(unit) && IS_TMRA_CH(ch)) + +#define IS_TMRA_CNT_SRC(x) (((x) == TMRA_CNT_SRC_SW) || ((x) == TMRA_CNT_SRC_HW)) + +#define IS_TMRA_FUNC(x) (((x) == TMRA_FUNC_CMP) || ((x) == TMRA_FUNC_CAPT)) + +#define IS_TMRA_DIR(x) (((x) == TMRA_DIR_DOWN) || ((x) == TMRA_DIR_UP)) + +#define IS_TMRA_MD(x) (((x) == TMRA_MD_SAWTOOTH) || ((x) == TMRA_MD_TRIANGLE)) + +#define IS_TMRA_CNT_RELOAD(x) (((x) == TMRA_CNT_RELOAD_DISABLE) || ((x) == TMRA_CNT_RELOAD_ENABLE)) + +#define IS_TMRA_CMPVAL_BUF_CH(x) \ +( ((x) == TMRA_CH1) || ((x) == TMRA_CH3) || ((x) == TMRA_CH5) || ((x) == TMRA_CH7)) + +#define IS_TMRA_CLK_DIV(x) \ +( ((x) == TMRA_CLK_DIV1) || \ + ((x) == TMRA_CLK_DIV2) || \ + ((x) == TMRA_CLK_DIV4) || \ + ((x) == TMRA_CLK_DIV8) || \ + ((x) == TMRA_CLK_DIV16) || \ + ((x) == TMRA_CLK_DIV32) || \ + ((x) == TMRA_CLK_DIV64) || \ + ((x) == TMRA_CLK_DIV128) || \ + ((x) == TMRA_CLK_DIV256) || \ + ((x) == TMRA_CLK_DIV512) || \ + ((x) == TMRA_CLK_DIV1024)) + +#define IS_TMRA_FILTER_PIN(x) ((x) <= TMRA_PIN_MAX) + +#define IS_TMRA_CNT_UP_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_UP_COND_ALL) + +#define IS_TMRA_CNT_DOWN_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CNT_DOWN_COND_ALL) + +#define IS_TMRA_INT(x) IS_TMRA_BIT_MASK(x, TMRA_INT_ALL) + +#define IS_TMRA_EVT(x) IS_TMRA_BIT_MASK(x, TMRA_EVT_ALL) + +#define IS_TMRA_FLAG(x) IS_TMRA_BIT_MASK(x, TMRA_FLAG_ALL) + +#define IS_TMRA_CAPT_COND(x) IS_TMRA_BIT_MASK(x, TMRA_CAPT_COND_ALL) + +#define IS_TMRA_FILTER_CLK_DIV(x) ((x) <= TMRA_FILTER_CLK_DIV64) + +#define IS_TMRA_UNIT_INT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_INT(x)) + +#define IS_TMRA_CH_EVT(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_EVT(x)) + +#define IS_TMRA_UNIT_FPIN(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FILTER_PIN(x)) + +#define IS_TMRA_UNIT_FLAG(u, x) (IS_TMRA_UNIT(u) && IS_TMRA_FLAG(x)) + +#define IS_TMRA_BUF_TRANS_COND(x) \ +( ((x) == TMRA_BUF_TRANS_COND_OVF_UDF_CLR) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK) || \ + ((x) == TMRA_BUF_TRANS_COND_VALLEY) || \ + ((x) == TMRA_BUF_TRANS_COND_PEAK_VALLEY)) + +#define IS_TMRA_PWM_START_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_STOP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD)) + +#define IS_TMRA_PWM_CMP_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_PERIOD_POLARITY(x) \ +( ((x) == TMRA_PWM_LOW) || \ + ((x) == TMRA_PWM_HIGH) || \ + ((x) == TMRA_PWM_HOLD) || \ + ((x) == TMRA_PWM_INVT)) + +#define IS_TMRA_PWM_FORCE_POLARITY(x) \ +( ((x) == TMRA_PWM_FORCE_INVD) || \ + ((x) == TMRA_PWM_FORCE_LOW) || \ + ((x) == TMRA_PWM_FORCE_HIGH)) + +#define IS_TMRA_PWM_POLARITY(st, pol) \ +( (((st) == TMRA_CNT_STAT_START) && IS_TMRA_PWM_START_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_STOP) && IS_TMRA_PWM_STOP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_CMP) && IS_TMRA_PWM_CMP_POLARITY(pol)) || \ + (((st) == TMRA_CNT_STAT_MATCH_PERIOD) && IS_TMRA_PWM_PERIOD_POLARITY(pol))) + +#define IS_TMRA_START_COND(x) IS_TMRA_BIT_MASK((x), TMRA_START_COND_ALL) + +#define IS_TMRA_STOP_COND(x) IS_TMRA_BIT_MASK((x), TMRA_STOP_COND_ALL) + +#define IS_TMRA_CLR_COND(x) IS_TMRA_BIT_MASK((x), TMRA_CLR_COND_ALL) + +/** + * @} + */ + +/** + * @defgroup TMRA_Miscellaneous_Macros TMRA Miscellaneous Macros + * @{ + */ +#define TMRA_PIN_PWM_OFFSET (3U) + +#define TMRA_CH_NUM (8U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Functions TMRA Global Functions + * @{ + */ +/** + * @brief Initializes the specified TMRA peripheral according to the specified parameters + * in the structure stc_tmra_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_Init(CM_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + if (pstcTmraInit != NULL) { + DDL_ASSERT(IS_TMRA_CNT_SRC(pstcTmraInit->u8CountSrc)); + + if (pstcTmraInit->u8CountSrc == TMRA_CNT_SRC_SW) { + DDL_ASSERT(IS_TMRA_MD(pstcTmraInit->sw_count.u8CountMode)); + DDL_ASSERT(IS_TMRA_DIR(pstcTmraInit->sw_count.u8CountDir)); + DDL_ASSERT(IS_TMRA_CLK_DIV(pstcTmraInit->sw_count.u8ClockDiv)); + + WRITE_REG8(TMRAx->BCSTRL, pstcTmraInit->sw_count.u8CountMode | \ + pstcTmraInit->sw_count.u8CountDir | \ + pstcTmraInit->sw_count.u8ClockDiv); + } else { + DDL_ASSERT(IS_TMRA_CNT_UP_COND(pstcTmraInit->hw_count.u16CountUpCond) || \ + (pstcTmraInit->hw_count.u16CountUpCond == TMRA_CNT_UP_COND_INVD)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(pstcTmraInit->hw_count.u16CountDownCond) || \ + (pstcTmraInit->hw_count.u16CountDownCond == TMRA_CNT_DOWN_COND_INVD)); + WRITE_REG16(TMRAx->HCUPR, pstcTmraInit->hw_count.u16CountUpCond); + WRITE_REG16(TMRAx->HCDOR, pstcTmraInit->hw_count.u16CountDownCond); + } + + /* Counter reload */ + DDL_ASSERT(IS_TMRA_CNT_RELOAD(pstcTmraInit->u8CountReload)); + WRITE_REG8(TMRAx->BCSTRH, pstcTmraInit->u8CountReload); + + /* Specifies period value. */ + TMRA_SetPeriodValue(TMRAx, pstcTmraInit->u32PeriodValue); + + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the TMRA initialization structure. + * @param [out] pstcTmraInit Pointer to a stc_tmra_init_t structure value that + * contains the configuration information for the TMRA. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcTmraInit == NULL. + */ +int32_t TMRA_StructInit(stc_tmra_init_t *pstcTmraInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcTmraInit != NULL) { + pstcTmraInit->u8CountSrc = TMRA_CNT_SRC_SW; + pstcTmraInit->sw_count.u8ClockDiv = TMRA_CLK_DIV1; + pstcTmraInit->sw_count.u8CountMode = TMRA_MD_SAWTOOTH; + pstcTmraInit->sw_count.u8CountDir = TMRA_DIR_UP; + pstcTmraInit->hw_count.u16CountUpCond = TMRA_CNT_UP_COND_INVD; + pstcTmraInit->hw_count.u16CountDownCond = TMRA_CNT_DOWN_COND_INVD; + pstcTmraInit->u32PeriodValue = (TMRA_REG_TYPE)0xFFFFFFFFUL; + pstcTmraInit->u8CountReload = TMRA_CNT_RELOAD_ENABLE; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Specifies the counting mode for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u8Mode Count mode. + * This parameter can be a value of @ref TMRA_Count_Mode + * @arg TMRA_MD_SAWTOOTH: Count mode is sawtooth wave. + * @arg TMRA_MD_TRIANGLE: Count mode is triangle wave. + * @retval None + */ +void TMRA_SetCountMode(CM_TMRA_TypeDef *TMRAx, uint8_t u8Mode) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_MD(u8Mode)); + MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_MODE, u8Mode); +} + +/** + * @brief Specifies the counting direction for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u8Dir Count direction. + * This parameter can be a value of @ref TMRA_Count_Dir + * @arg TMRA_DIR_DOWN: TMRA count down. + * @arg TMRA_DIR_UP: TMRA count up. + * @retval None + */ +void TMRA_SetCountDir(CM_TMRA_TypeDef *TMRAx, uint8_t u8Dir) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_DIR(u8Dir)); + MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_DIR, u8Dir); +} + +/** + * @brief Specifies the clock divider for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u8Div Clock divider. + * This parameter can be a value of @ref TMRA_Clock_Divider + * @retval None + */ +void TMRA_SetClockDiv(CM_TMRA_TypeDef *TMRAx, uint8_t u8Div) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLK_DIV(u8Div)); + MODIFY_REG8(TMRAx->BCSTRL, TMRA_BCSTRL_CKDIV, u8Div); +} + +/** + * @brief Enable or disable the specified hardware count up condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count up condition. + * This parameter can be values of @ref TMRA_Hard_Count_Up_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountUpCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_UP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCUPR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCUPR, u16Cond); + } +} + +/** + * @brief Enable or disable the specified hardware count down condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware count down condition. + * This parameter can be values of @ref TMRA_Hard_Count_Down_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCountDownCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_DOWN_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCDOR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCDOR, u16Cond); + } +} + +/** + * @brief Specifies function mode of TMRA. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Func Function mode of TMRA. + * This parameter can be a value of @ref TMRA_Function_Mode + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval None + */ +void TMRA_SetFunc(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Func) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_FUNC(u16Func)); + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32CCONRAddr), TMRA_CCONR_CAPMD, u16Func); +} + +/** + * @brief Initializes the PWM according to the specified parameters + * in the structure stc_tmra_pwm_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_Init(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, const stc_tmra_pwm_init_t *pstcPwmInit) +{ + uint32_t u32CMPARAddr; + uint32_t u32PCONRAddr; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + if (pstcPwmInit != NULL) { + DDL_ASSERT(IS_TMRA_PWM_START_POLARITY(pstcPwmInit->u16StartPolarity)); + DDL_ASSERT(IS_TMRA_PWM_STOP_POLARITY(pstcPwmInit->u16StopPolarity)); + DDL_ASSERT(IS_TMRA_PWM_CMP_POLARITY(pstcPwmInit->u16CompareMatchPolarity)); + DDL_ASSERT(IS_TMRA_PWM_PERIOD_POLARITY(pstcPwmInit->u16PeriodMatchPolarity)); + + u32Ch *= 4U; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch; + SET_VAL_BY_ADDR(u32CMPARAddr, pstcPwmInit->u32CompareValue); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + u32Ch; + RW_MEM16(u32PCONRAddr) = (uint16_t)((pstcPwmInit->u16StartPolarity << TMRA_PCONR_STAC_POS) | \ + (pstcPwmInit->u16StopPolarity << TMRA_PCONR_STPC_POS) | \ + (pstcPwmInit->u16CompareMatchPolarity << TMRA_PCONR_CMPC_POS) | \ + (pstcPwmInit->u16PeriodMatchPolarity << TMRA_PCONR_PERC_POS)); + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Set a default value for the PWM initialization structure. + * @param [out] pstcPwmInit Pointer to a stc_tmra_pwm_init_t structure value that + * contains the configuration information for PWM. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pstcPwmInit == NULL. + */ +int32_t TMRA_PWM_StructInit(stc_tmra_pwm_init_t *pstcPwmInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (pstcPwmInit != NULL) { + pstcPwmInit->u32CompareValue = TMRA_REG_VALUE_MAX; + pstcPwmInit->u16StartPolarity = TMRA_PWM_HIGH; + pstcPwmInit->u16StopPolarity = TMRA_PWM_LOW; + pstcPwmInit->u16CompareMatchPolarity = TMRA_PWM_INVT; + pstcPwmInit->u16PeriodMatchPolarity = TMRA_PWM_INVT; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Enable or disable the PWM ouput of the specified channel. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_PWM_OutputCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + WRITE_REG32(PERIPH_BIT_BAND(u32PCONRAddr, TMRA_PCONR_OUTEN_POS), enNewState); +} + +/** + * @brief Specifies the ouput polarity of the PWM at the specified state of counter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u8CountState TMRA counter state. + * This parameter can be a value @ref TMRA_Counter_State + * @param [in] u16Polarity The polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Polarity + * @retval None + * @note The polarity(high or low) when counting start is only valid when the clock is not divided(BCSTRL.CKDIV == 0). + */ +void TMRA_PWM_SetPolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint8_t u8CountState, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_POLARITY(u8CountState, u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), + (uint16_t)TMRA_PWM_POLARITY_MASK << (u8CountState * 2U), + u16Polarity << (u8CountState * 2U)); +} + +/** + * @brief Specifies the force polarity of the PWM. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Polarity The force polarity of PWM. + * This parameter can be a value @ref TMRA_PWM_Force_Polarity + * @retval None + */ +void TMRA_PWM_SetForcePolarity(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_PWM_FORCE_POLARITY(u16Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (u32Ch * 4U); + MODIFY_REG16(RW_MEM16(u32PCONRAddr), TMRA_PCONR_FORC, u16Polarity); +} + +/** + * @brief Enable or disable the specified capture condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value @ref TMRA_Channel + * @param [in] u16Cond The capture condition. + * This parameter can be a value @ref TMRA_Capture_Cond + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWCaptureCondCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond, en_functional_state_t enNewState) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + DDL_ASSERT(IS_TMRA_CAPT_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + +#if defined __DEBUG + if ((u16Cond & (TMRA_CAPT_COND_TRIG_RISING | TMRA_CAPT_COND_TRIG_FALLING)) != 0U) { + DDL_ASSERT(u32Ch == TMRA_CH3); + } + + if ((u16Cond & (TMRA_CAPT_COND_XOR_RISING | TMRA_CAPT_COND_XOR_FALLING)) != 0U) { + DDL_ASSERT(u32Ch == TMRA_CH4); + } +#endif + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (u32Ch * 4U); + if (enNewState == ENABLE) { + SET_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } else { + CLR_REG16_BIT(RW_MEM16(u32CCONRAddr), u16Cond); + } +} + +/** + * @brief Enable or disable hardware start condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware start condition. + * This parameter can be a value @ref TMRA_Hardware_Start_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStartCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_START_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware stop condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware stop condition. + * This parameter can be a value @ref TMRA_Hardware_Stop_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWStopCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_STOP_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Enable or disable hardware clear condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u16Cond Hardware clear condition. + * This parameter can be a value @ref TMRA_Hardware_Clear_Condition + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_HWClearCondCmd(CM_TMRA_TypeDef *TMRAx, uint16_t u16Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CLR_COND(u16Cond)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if ((u16Cond & (TMRA_CLR_COND_SYM_TRIG_RISING | TMRA_CLR_COND_SYM_TRIG_FALLING)) != 0U) { + /* The specified condition is not valid for TimerA5 */ + DDL_ASSERT(TMRAx != CM_TMRA_5); + } + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->HCONR, u16Cond); + } else { + CLR_REG16_BIT(TMRAx->HCONR, u16Cond); + } +} + +/** + * @brief Specifies the clock divider of filter. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be a value of @ref TMRA_Filter_Pin + * @param [in] u16Div The clock source divider of the filter. + * This parameter can be a value of @ref TMRA_Filter_Clock_Divider + * @arg TMRA_FILTER_CLK_DIV1: The filter clock is the clock of timerA / 1. + * @arg TMRA_FILTER_CLK_DIV4: The filter clock is the clock of timerA / 4. + * @arg TMRA_FILTER_CLK_DIV16: The filter clock is the clock of timerA / 16. + * @arg TMRA_FILTER_CLK_DIV64: The filter clock is the clock of timerA / 64. + * @retval None + */ +void TMRA_SetFilterClockDiv(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, uint16_t u16Div) +{ + uint32_t u32Ch; + uint32_t u32CCONRAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFICKTG_POS, TMRA_FCONR_NOFICKCA_POS, TMRA_FCONR_NOFICKCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_TMRA_FILTER_CLK_DIV(u16Div)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + MODIFY_REG16(TMRAx->FCONR, + (TMRA_FCONR_FILTER_CLK_MASK << au8Offset[u32Pin]), + (u16Div << au8Offset[u32Pin])); + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32CCONRAddr), + TMRA_CCONR_FILTER_CLK_MASK, + (u16Div << TMRA_CCONR_NOFICKCP_POS)); + } +} + +/** + * @brief Enable or disable the filter function of the specified TMRA input pin. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Pin The pin with filter of TMRA. + * This parameter can be values of @ref TMRA_Filter_Pin + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_FilterCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Pin, en_functional_state_t enNewState) +{ + uint8_t u8EnPos; + uint32_t u32Ch; + uint32_t u32RegAddr; + const uint8_t au8Offset[] = { + TMRA_FCONR_NOFIENTG_POS, TMRA_FCONR_NOFIENCA_POS, TMRA_FCONR_NOFIENCB_POS, + }; + + DDL_ASSERT(IS_TMRA_UNIT_FPIN(TMRAx, u32Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (u32Pin < TMRA_PIN_PWM_OFFSET) { + u32RegAddr = (uint32_t)&TMRAx->FCONR; + u8EnPos = au8Offset[u32Pin]; + } else { + u32Ch = u32Pin - TMRA_PIN_PWM_OFFSET; + u32RegAddr = (uint32_t)&TMRAx->CCONR1 + u32Ch * 4U; + u8EnPos = TMRA_CCONR_NOFIENCP_POS; + } + WRITE_REG32(PERIPH_BIT_BAND(u32RegAddr, u8EnPos), enNewState); +} + +/** + * @brief De-initializes the TMRA peripheral. Reset all registers of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_DeInit(CM_TMRA_TypeDef *TMRAx) +{ + uint32_t i; + uint32_t u32ChNum = TMRA_CH_NUM; + uint32_t u32AddrOffset; + uint32_t u32PERARAddr; + uint32_t u32CNTERAddr; + uint32_t u32CMPARAddr; + uint32_t u32CCONRAddr; + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1; + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1; + + for (i = 0U; i < u32ChNum; i++) { + u32AddrOffset = i * 4U; + RW_MEM16(u32CMPARAddr + u32AddrOffset) = 0xFFFFU; + RW_MEM16(u32CCONRAddr + u32AddrOffset) = 0x0U; + RW_MEM16(u32PCONRAddr + u32AddrOffset) = 0x0U; + } + + SET_VAL_BY_ADDR(u32PERARAddr, 0xFFFFFFFFUL); + SET_VAL_BY_ADDR(u32CNTERAddr, 0x0U); + WRITE_REG8(TMRAx->BCSTRL, 0x2U); + WRITE_REG8(TMRAx->BCSTRH, 0x0U); + WRITE_REG16(TMRAx->ICONR, 0x0U); + WRITE_REG16(TMRAx->ECONR, 0x0U); + WRITE_REG16(TMRAx->FCONR, 0x0U); + WRITE_REG16(TMRAx->STFLR, 0x0U); + WRITE_REG16(TMRAx->HCONR, 0x0U); + WRITE_REG16(TMRAx->HCUPR, 0x0U); + WRITE_REG16(TMRAx->HCDOR, 0x0U); + WRITE_REG16(TMRAx->BCONR1, 0x0U); + WRITE_REG16(TMRAx->BCONR2, 0x0U); + WRITE_REG16(TMRAx->BCONR3, 0x0U); + WRITE_REG16(TMRAx->BCONR4, 0x0U); +} + +/** + * @brief Get the counting direction of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint8_t type value of counting direction. + * -TMRA_DIR_DOWN: TMRA count down. + * -TMRA_DIR_UP: TMRA count up. + */ +uint8_t TMRA_GetCountDir(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return READ_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_DIR); +} + +/** + * @brief Set period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The period value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * 0UL and 0xFFFFUL for 16-bit TimerA units. + * @retval None + */ +void TMRA_SetPeriodValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32PERARAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32PERARAddr = (uint32_t)&TMRAx->PERAR; + SET_VAL_BY_ADDR(u32PERARAddr, u32Value); +} + +/** + * @brief Get period value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of period value between: + * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * - 0UL and 0xFFFFUL for 16-bit TimerA units. + */ +uint32_t TMRA_GetPeriodValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->PERAR); +} + +/** + * @brief Set general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Value The general counter value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * 0UL and 0xFFFFUL for 16-bit TimerA units. + * @retval None + */ +void TMRA_SetCountValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Value) +{ + uint32_t u32CNTERAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + u32CNTERAddr = (uint32_t)&TMRAx->CNTER; + SET_VAL_BY_ADDR(u32CNTERAddr, u32Value); +} + +/** + * @brief Get general counter value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval An uint32_t type type value of counter value between: + * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * - 0UL and 0xFFFFUL for 16-bit TimerA units. + */ +uint32_t TMRA_GetCountValue(const CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->CNTER); +} + +/** + * @brief Set comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @param [in] u32Value The comparison value to be set. + * This parameter can be a number between: + * 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * 0UL and 0xFFFFUL for 16-bit TimerA units. + * @retval None + */ +void TMRA_SetCompareValue(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint32_t u32Value) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + SET_VAL_BY_ADDR(u32CMPARAddr, u32Value); +} + +/** + * @brief Get comparison value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be a value of @ref TMRA_Channel + * @retval An uint32_t type type value of comparison value value between: + * - 0UL and 0xFFFFFFFFUL for 32-bit TimerA units. + * - 0UL and 0xFFFFUL for 16-bit TimerA units. + */ +uint32_t TMRA_GetCompareValue(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT_CH(TMRAx, u32Ch)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + u32Ch * 4U; + return GET_VAL_BY_ADDR(u32CMPARAddr); +} + +/** + * @brief Enable or disable synchronous-start. When an even unit enables synchronous-start function, + * start the symmetric odd unit can start the even unit at the same time. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x(x is an even number) + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_SyncStartCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_TMRA_SYNC_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&TMRAx->BCSTRL; + WRITE_REG32(PERIPH_BIT_BAND(u32Addr, TMRA_BCSTRL_SYNST_POS), enNewState); +} + +/** + * @brief Enable or disable reload and continue counting when overflow/underflow. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_CountReloadCmd(CM_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + CLR_REG8_BIT(TMRAx->BCSTRH, TMRA_BCSTRH_OVSTP); + } else { + SET_REG8_BIT(TMRAx->BCSTRH, TMRA_BCSTRH_OVSTP); + } +} + +/** + * @brief Specifies the condition of compare value buffer transmission. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] u16Cond Buffer condition of the specified TMRA unit. + * This parameter can be a value of @ref TMRA_Cmp_Value_Buf_Trans_Cond + * @arg TMRA_BUF_TRANS_COND_OVF_UDF_CLR: This configuration value applies to non-triangular wave counting mode. + * When counting overflow or underflow or counting register was cleared, + * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_PEAK: In triangle wave count mode, when count reached peak, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_VALLEY: In triangle wave count mode, when count reached valley, + * transfer CMMARm(m=2,4,6,8,...) to CMMARn(n=1,3,5,7,...). + * @arg TMRA_BUF_TRANS_COND_PEAK_VALLEY: In triangle wave count mode, when count reached peak or valley, + * transfer CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). + * @retval None + * @note The specified condition is only valid when TMRA_BCONR.BEN is set. + */ +void TMRA_SetCompareBufCond(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, uint16_t u16Cond) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_TMRA_BUF_TRANS_COND(u16Cond)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + MODIFY_REG16(RW_MEM16(u32BCONRAddr), TMRA_BUF_TRANS_COND_PEAK_VALLEY, u16Cond); +} + +/** + * @brief Enable or disable compare value buffer. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note DO NOT set both TMRA_BCONR.BSEN and TMRA_BCONR.BEN to '1'. + */ +void TMRA_CompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + + if (enNewState == ENABLE) { + /* DO NOT set both TMRA_BCONR.BSEN and TMRA_BCONR.BEN to '1'. */ + DDL_ASSERT(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BSEN_POS) == 0U); + } + WRITE_REG32(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BEN_POS), enNewState); +} + +/** + * @brief Enable or disable special compare value buffer transmission condition. + * When the counter register(CNTER) of the symmetric unit of TimerAx is read, + * TimerAx transfers CMPARm(m=2,4,6,8,...) to CMPARn(n=1,3,5,7,...). + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Ch TMRA channel. + * This parameter can be one of the odd channels of @ref TMRA_Channel + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note DO NOT set both TMRA_BCONR.BSEN and TMRA_BCONR.BEN to '1'. + */ +void TMRA_SpecialCompareBufCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32Ch, en_functional_state_t enNewState) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_SYM_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CMPVAL_BUF_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + u32Ch * 4U; + if (enNewState == ENABLE) { + /* DO NOT set both TMRA_BCONR.BSEN and TMRA_BCONR.BEN to '1'. */ + DDL_ASSERT(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BEN_POS) == 0U); + } + WRITE_REG32(PERIPH_BIT_BAND(u32BCONRAddr, TMRA_BCONR_BSEN_POS), enNewState); +} + +/** + * @brief Get the status of the specified flag. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be a value of @ref TMRA_Status_Flag + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t TMRA_GetStatus(const CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + uint8_t u8BCSTR; + uint16_t u16STFLR; + en_flag_status_t enStatus = RESET; + + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + u8BCSTR = (uint8_t)(u32Flag & TMRA_BCSTRH_FLAG_MASK); + u16STFLR = (uint16_t)(u32Flag >> 16U); + u8BCSTR = READ_REG8_BIT(TMRAx->BCSTRH, u8BCSTR); + u16STFLR = READ_REG16_BIT(TMRAx->STFLR, u16STFLR); + + if ((u8BCSTR != 0U) || (u16STFLR != 0U)) { + enStatus = SET; + } + + return enStatus; +} + +/** + * @brief Clear the status of the specified flags. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be values of @ref TMRA_Status_Flag + * @retval None + */ +void TMRA_ClearStatus(CM_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_TMRA_UNIT_FLAG(TMRAx, u32Flag)); + + CLR_REG8_BIT(TMRAx->BCSTRH, u32Flag & TMRA_BCSTRH_FLAG_MASK); + CLR_REG16_BIT(TMRAx->STFLR, u32Flag >> 16U); +} + +/** + * @brief Enable of disable the specified interrupts of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32IntType The interrupt type of TMRA. + * This parameter can be values of @ref TMRA_Interrupt_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_IntCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32BCSTRH; + uint32_t u32ICONR; + + DDL_ASSERT(IS_TMRA_UNIT_INT(TMRAx, u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCSTRH = u32IntType & TMRA_BCSTRH_INT_MASK; + u32ICONR = u32IntType >> 16U; + if (enNewState == ENABLE) { + SET_REG8_BIT(TMRAx->BCSTRH, u32BCSTRH); + SET_REG16_BIT(TMRAx->ICONR, u32ICONR); + } else { + CLR_REG8_BIT(TMRAx->BCSTRH, u32BCSTRH); + CLR_REG16_BIT(TMRAx->ICONR, u32ICONR); + } +} + +/** + * @brief Enable of disable the specified event of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @param [in] u32EventType The event type of TMRA. + * This parameter can be values of @ref TMRA_Event_Type + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TMRA_EventCmd(CM_TMRA_TypeDef *TMRAx, uint32_t u32EventType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_CH_EVT(TMRAx, u32EventType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == ENABLE) { + SET_REG16_BIT(TMRAx->ECONR, u32EventType); + } else { + CLR_REG16_BIT(TMRAx->ECONR, u32EventType); + } +} + +/** + * @brief Start the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Start(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + SET_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_START); +} + +/** + * @brief Stop the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg CM_TMRA_x or CM_TMRA + * @retval None + */ +void TMRA_Stop(CM_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + CLR_REG8_BIT(TMRAx->BCSTRL, TMRA_BCSTRL_START); +} +/** + * @} + */ + +#endif /* LL_TMRA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c new file mode 100644 index 0000000000..090d10c42f --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_trng.c @@ -0,0 +1,257 @@ +/** + ******************************************************************************* + * @file hc32_ll_trng.c + * @brief This file provides firmware functions to manage the True Random + * Number Generator(TRNG). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_trng.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_TRNG TRNG + * @brief TRNG Driver Library + * @{ + */ + +#if (LL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TRNG_Local_Macros TRNG Local Macros + * @{ + */ +#define TRNG_TIMEOUT (20000UL) + +/** + * @defgroup TRNG_Check_Parameters_Validity TRNG Check Parameters Validity + * @{ + */ +#define IS_TRNG_SHIFT_CNT(x) \ +( ((x) == TRNG_SHIFT_CNT32) || \ + ((x) == TRNG_SHIFT_CNT64) || \ + ((x) == TRNG_SHIFT_CNT128) || \ + ((x) == TRNG_SHIFT_CNT256)) + +#define IS_RNG_RELOAD_INIT_VAL_EN(x) \ +( ((x) == TRNG_RELOAD_INIT_VAL_ENABLE) || \ + ((x) == TRNG_RELOAD_INIT_VAL_DISABLE)) + +#define IS_TRNG_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/* TRNG reset timeout */ +#define TRNG_RMU_TIMEOUT (100UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TRNG_Global_Functions TRNG Global Functions + * @{ + */ + +/** + * @brief De-initializes TRNG. + * @param None + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + */ +int32_t TRNG_DeInit(void) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32TimeOut = 0U; + + /* Check parameters */ + DDL_ASSERT(IS_TRNG_PWC_UNLOCKED()); + + CLR_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_TRNG); + /* Ensure reset procedure is completed */ + while (RMU_FRST0_TRNG != READ_REG32_BIT(CM_RMU->FRST0, RMU_FRST0_TRNG)) { + u32TimeOut++; + if (u32TimeOut > TRNG_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Initializes TRNG. + * @param [in] u32ShiftCount TRNG shift control. This parameter can be a value of @ref TRNG_Shift_Ctrl + * @arg TRNG_SHIFT_CNT32: Shift 32 times when capturing random noise. + * @arg TRNG_SHIFT_CNT64: Shift 64 times when capturing random noise. + * @arg TRNG_SHIFT_CNT128: Shift 128 times when capturing random noise. + * @arg TRNG_SHIFT_CNT256: Shift 256 times when capturing random noise. + * @param [in] u32ReloadInitValueEn Enable or disable load new initial value. + * This parameter can be a value of @ref TRNG_Reload_Init_Value + * @arg TRNG_RELOAD_INIT_VAL_ENABLE: Enable load new initial value. + * @arg TRNG_RELOAD_INIT_VAL_DISABLE: Disable load new initial value. + * @retval None + */ +void TRNG_Init(uint32_t u32ShiftCount, uint32_t u32ReloadInitValueEn) +{ + + /* MRC is required */ + DDL_ASSERT(READ_REG32(bCM_CMU->MRCCR_b.MRCSTP) == 0U); + DDL_ASSERT(IS_TRNG_SHIFT_CNT(u32ShiftCount)); + DDL_ASSERT(IS_RNG_RELOAD_INIT_VAL_EN(u32ReloadInitValueEn)); + WRITE_REG32(CM_TRNG->MR, u32ShiftCount | u32ReloadInitValueEn); +} + +/** + * @brief Start TRNG and get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u32RandomLen The size(in word) of the destination buffer. + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_TIMEOUT: Works timeout. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GenerateRandom(uint32_t *pu32Random, uint32_t u32RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + __IO uint32_t u32TimeCount = TRNG_TIMEOUT; + uint32_t u32Count = 0U; + + if ((pu32Random != NULL) && (u32RandomLen > 0U)) { + while (u32RandomLen != u32Count) { + /* Start TRNG */ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); + /* Wait generating done. */ + i32Ret = LL_ERR_TIMEOUT; + while (u32TimeCount-- != 0UL) { + if (READ_REG32(bCM_TRNG->CR_b.RUN) == 0U) { + i32Ret = LL_OK; + break; + } + } + + if (i32Ret == LL_OK) { + /* Get the random number. */ + pu32Random[u32Count++] = READ_REG32(CM_TRNG->DR0); + if (u32Count < u32RandomLen) { + pu32Random[u32Count++] = READ_REG32(CM_TRNG->DR1); + } + } + } + } + + return i32Ret; +} + +/** + * @brief Start TRNG + * @param None + * @retval None + */ +void TRNG_Start(void) +{ + WRITE_REG32(bCM_TRNG->CR_b.RUN, 1U); +} + +/** + * @brief TRNG function enable or disable. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void TRNG_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + } else { + CLR_REG32_BIT(CM_TRNG->CR, TRNG_CR_EN); + } +} + +/** + * @brief Get random number. + * @param [out] pu32Random The destination buffer to store the random number. + * @param [in] u8RandomLen The size(in word) of the destination buffer.(MAX = 2U) + * @retval int32_t: + * - LL_OK: No error occurred. + * - LL_ERR_INVD_PARAM: pu32Random == NULL or u8RandomLen == 0 + */ +int32_t TRNG_GetRandom(uint32_t *pu32Random, uint8_t u8RandomLen) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if ((pu32Random != NULL) && (u8RandomLen > 0U)) { + /* Get the random number. */ + pu32Random[0U] = READ_REG32(CM_TRNG->DR0); + if (u8RandomLen > 1U) { + pu32Random[1U] = READ_REG32(CM_TRNG->DR1); + } + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_TRNG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c new file mode 100644 index 0000000000..dc08ea8fb2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_usart.c @@ -0,0 +1,2177 @@ +/** + ******************************************************************************* + * @file hc32_ll_usart.c + * @brief This file provides firmware functions to manage the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify return type of function USART_DeInit() + 2023-09-30 CDT Modify USART_SmartCard_Init() for stc_usart_smartcard_init_t has modified(u32StopBit has removed) + Fix bug: did not enable MP while USART_MultiProcessor_Init() + API refined: USART_SetBaudrate() + 2023-12-15 CDT Add API USART_GetFuncState() + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_USART USART + * @brief USART Driver Library + * @{ + */ + +#if (LL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/** + * @defgroup USART_Local_Types USART Local Types + * @{ + */ + +/** + * @brief usart BRR division calculate structure definition + */ +typedef struct { + uint32_t u32UsartClock; /*!< USART clock. */ + uint32_t u32Baudrate; /*!< USART baudrate. */ + uint32_t u32Integer; /*!< Pointer to BRR integer division value. */ + uint32_t u32Fraction; /*!< Pointer to BRR fraction division value. */ + float32_t f32Error; /*!< E(%) baudrate error rate. */ +} stc_usart_brr_t; + +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Local_Macros USART Local Macros + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity USART Check Parameters Validity + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Unit USART Check Parameters Validity Unit + * @{ + */ +#define IS_USART_UNIT(x) \ +( ((x) == CM_USART1) || \ + ((x) == CM_USART2) || \ + ((x) == CM_USART3) || \ + ((x) == CM_USART4) || \ + ((x) == CM_USART5) || \ + ((x) == CM_USART6)) +#define IS_USART_SMARTCARD_UNIT(x) \ +( ((x) == CM_USART1) || \ + ((x) == CM_USART2) || \ + ((x) == CM_USART4) || \ + ((x) == CM_USART5)) +#define IS_USART_LIN_UNIT(x) \ +( ((x) == CM_USART3) || \ + ((x) == CM_USART6)) +#define IS_USART_STOP_MD_UNIT(x) ((x) == CM_USART1) +#define IS_USART_TIMEOUT_UNIT(x) \ +( ((x) == CM_USART1) || \ + ((x) == CM_USART2) || \ + ((x) == CM_USART4) || \ + ((x) == CM_USART5)) +/** + * @} + */ + +#define IS_USART_FUNC(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FUNC_ALL) == USART_FUNC_ALL)) + +#define IS_USART_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | USART_FLAG_ALL) == USART_FLAG_ALL)) + +#define IS_USART_TRANS_TYPE(x) \ +( ((x) == USART_TRANS_ID) || \ + ((x) == USART_TRANS_DATA)) + +#define IS_USART_PARITY(x) \ +( ((x) == USART_PARITY_ODD) || \ + ((x) == USART_PARITY_EVEN) || \ + ((x) == USART_PARITY_NONE)) + +#define IS_USART_DATA_WIDTH(x) \ +( ((x) == USART_DATA_WIDTH_8BIT) || \ + ((x) == USART_DATA_WIDTH_9BIT)) + +#define IS_USART_STOPBIT(x) \ +( ((x) == USART_STOPBIT_1BIT) || \ + ((x) == USART_STOPBIT_2BIT)) + +#define IS_USART_FIRST_BIT(x) \ +( ((x) == USART_FIRST_BIT_MSB) || \ + ((x) == USART_FIRST_BIT_LSB)) + +#define IS_USART_OVER_SAMPLE_BIT(x) \ +( ((x) == USART_OVER_SAMPLE_8BIT) || \ + ((x) == USART_OVER_SAMPLE_16BIT)) + +#define IS_USART_START_BIT_POLARITY(x) \ +( ((x) == USART_START_BIT_LOW) || \ + ((x) == USART_START_BIT_FALLING)) + +#define IS_USART_CLK_SRC(x) \ +( ((x) == USART_CLK_SRC_EXTCLK) || \ + ((x) == USART_CLK_SRC_INTERNCLK)) + +#define IS_USART_CK_OUTPUT(x) \ +( ((x) == USART_CK_OUTPUT_ENABLE) || \ + ((x) == USART_CK_OUTPUT_DISABLE)) + +#define IS_USART_CLK_DIV(x) ((x) <= USART_CLK_DIV_MAX) + +#define IS_USART_DATA(x) ((x) <= 0x01FFUL) + +/** + * @defgroup USART_Check_Parameters_Validity_Hardware_Flow_Control USART Check Parameters Validity Hardware Flow Control + * @{ + */ +#define IS_USART_HW_FLOWCTRL(x) \ +( ((x) == USART_HW_FLOWCTRL_NONE) || \ + ((x) == USART_HW_FLOWCTRL_CTS) || \ + ((x) == USART_HW_FLOWCTRL_RTS) || \ + ((x) == USART_HW_FLOWCTRL_RTS_CTS)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Smartcard_Clock USART Check Parameters Validity Smartcard Clock + * @{ + */ +#define IS_USART_SMARTCARD_ETU_CLK(x) \ +( ((x) == USART_SC_ETU_CLK32) || \ + ((x) == USART_SC_ETU_CLK64) || \ + ((x) == USART_SC_ETU_CLK128) || \ + ((x) == USART_SC_ETU_CLK256) || \ + ((x) == USART_SC_ETU_CLK372)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Stopmode_Filter USART Check Parameters Validity Stopmode Filter + * @{ + */ +#define IS_USART_STOP_MD_FILTER(x) \ +( ((x) == USART_STOP_MD_FILTER_LVL1) || \ + ((x) == USART_STOP_MD_FILTER_LVL2) || \ + ((x) == USART_STOP_MD_FILTER_LVL3) || \ + ((x) == USART_STOP_MD_FILTER_LVL4)) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_Timeout_Function USART Check Parameters Validity Timeout Function + * @{ + */ +#define IS_USART_TIMEOUT_FUNC(x, func) \ +( IS_USART_TIMEOUT_UNIT(x) || \ + ((!IS_USART_TIMEOUT_UNIT(x)) && (((func) & (USART_RX_TIMEOUT | USART_INT_RX_TIMEOUT)) == 0UL))) +/** + * @} + */ + +/** + * @defgroup USART_Check_Parameters_Validity_LIN_Function USART Check Parameters Validity LIN Function + * @{ + */ +#define IS_USART_LIN_FUNC(x, func) \ +( IS_USART_LIN_UNIT(x) || \ + ((!IS_USART_LIN_UNIT(x)) && (((func) & USART_LIN_FUNC_MASK) == 0UL))) + +#define IS_USART_LIN_BMC_CLK_DIV(x) \ +( ((x) == USART_LIN_BMC_CLK_DIV1) || \ + ((x) == USART_LIN_BMC_CLK_DIV2) || \ + ((x) == USART_LIN_BMC_CLK_DIV4) || \ + ((x) == USART_LIN_BMC_CLK_DIV8)) + +#define IS_USART_LIN_SEND_BREAK_MD(x) \ +( ((x) == USART_LIN_SEND_BREAK_MD_SBK) || \ + ((x) == USART_LIN_SEND_BREAK_MD_TDR)) + +#define IS_USART_LIN_DETECT_BREAK_LEN(x) \ +( ((x) == USART_LIN_DETECT_BREAK_10BIT) || \ + ((x) == USART_LIN_DETECT_BREAK_11BIT)) + +#define IS_USART_LIN_SEND_BREAK_LEN(x) \ +( ((x) == USART_LIN_SEND_BREAK_10BIT) || \ + ((x) == USART_LIN_SEND_BREAK_11BIT) || \ + ((x) == USART_LIN_SEND_BREAK_13BIT) || \ + ((x) == USART_LIN_SEND_BREAK_14BIT)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup USART_Flag_Error_Mask USART Flag Error Mask + * @{ + */ +#define USART_FLAG_ERR_MASK (USART_FLAG_OVERRUN | \ + USART_FLAG_FRAME_ERR | \ + USART_FLAG_PARITY_ERR) +/** + * @} + */ + +/** + * @defgroup USART_Registers_Reset_Value_definition USART Registers Reset Value + * @{ + */ +#define USART_CR1_RST_VALUE (0x80000000UL) + +#define USART_CR2_RST_VALUE (0x0600UL) +/** + * @} + */ + +/** + * @defgroup USART_LIN_Function_Mask USART LIN Function Mask + * @{ + */ +#define USART_LIN_FUNC_OFFSET (16U) + +#define USART_LIN_FUNC_MASK (USART_LIN | \ + USART_LIN_ERR | \ + USART_LIN_WKUP | \ + USART_LIN_INT_WKUP | \ + USART_LIN_INT_BREAK | \ + USART_LIN_INT_ERR) +/** + * @} + */ + +/** + * @defgroup USART_BRR_Division_Max USART BRR Register Division Max + * @{ + */ +#define USART_BRR_DIV_INTEGER_MAX (0xFFUL) +#define USART_BRR_DIV_FRACTION_MAX (0x7FUL) +/** + * @} + */ + +/** + * @defgroup USART_Clock_Division_Max USART Clock Division Max + * @{ + */ +#define USART_CLK_DIV_MAX (USART_CLK_DIV1024) +/** + * @} + */ + +/** + * @defgroup USART_Default_Baudrate USART Default Baudrate + * @{ + */ +#define USART_DEFAULT_BAUDRATE (9600UL) +/** + * @} + */ + +#define USART_RMU_TIMEOUT (100U) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup USART_Local_Functions USART Local Functions + * @{ + */ +/** + * @brief Try to wait the expected status of specified flags + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag + * This parameter can be a value of @ref USART_Flag + * @param [in] enStatus Expected status + * This parameter can be one of the following values: + * @arg SET: Wait flag set + * @arg RESET: Wait flag reset + * @param [in] u32Timeout Maximum count(Max value @ref USART_Max_Timeout) of trying to get status + * @retval int32_t: + * - LL_OK: Complete wait the expected status of the specified flags. + * - LL_ERR_TIMEOUT: Wait timeout. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +static int32_t USART_WaitStatus(const CM_USART_TypeDef *USARTx, + uint32_t u32Flag, + en_flag_status_t enStatus, + uint32_t u32Timeout) +{ + int32_t i32Ret = LL_OK; + __IO uint32_t u32To = 0UL; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + while (USART_GetStatus(USARTx, u32Flag) != enStatus) { + /* Block checking flag if timeout value is USART_TIMEOUT_MAX */ + if ((u32To > u32Timeout) && (u32Timeout < USART_MAX_TIMEOUT)) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + + u32To++; + } + + return i32Ret; +} + +/** + * @brief Calculate baudrate division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartBrr Pointer to a stc_usart_brr_t structure. + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + */ +static int32_t UART_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcUartBrr) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + uint64_t u64Temp; + uint64_t u64Temp0; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_IntegerMod; + uint32_t DIV_Fraction; + float32_t f32CalcError; + uint32_t u32FractionFlag = 1UL; + int32_t i32Ret = LL_ERR; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + C = pstcUartBrr->u32UsartClock; + B = pstcUartBrr->u32Baudrate; + if ((C > 0UL) && (B > 0UL)) { + OVER8 = READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8) >> USART_CR1_OVER8_POS; + + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV_Integer = (C / (B * 8UL * (2UL - OVER8))) - 1U; + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcUartBrr->u32Integer = DIV_Integer; + DIV_IntegerMod = C % (B * 8UL * (2UL - OVER8)); + if (0UL == DIV_IntegerMod) { + /* Get accurate baudrate without fraction */ + pstcUartBrr->f32Error = (float32_t)0.0F; + i32Ret = LL_OK; + } else { + /* UART mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */ + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp0 = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * \ + ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + + /* u64Temp = u64Temp0 *256 + C/2 */ + u64Temp0 = (u64Temp0 << 8UL); + u64Temp = u64Temp0 + ((uint64_t)C >> 1); /* +(C >> 1) for rounding off */ + if (u64Temp > (uint64_t)(UINT32_MAX)) { + DIV_Fraction = (uint32_t)(u64Temp / C) - 128UL; + } else { + DIV_Fraction = ((uint32_t)u64Temp) / C - 128UL; + } + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + pstcUartBrr->u32Fraction = DIV_Fraction; + /* E(%) = C * (128 + DIV_Fraction) / (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B)) - 1 */ + u64Temp = u64Temp0; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32CalcError = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + pstcUartBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } else { + u32FractionFlag = 0UL; + } + } + } + if (0UL == u32FractionFlag) { + /* Integer rounding off */ + DIV_Integer = ((((C * 10UL) / (B * 8UL * (2UL - OVER8))) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcUartBrr->u32Integer = DIV_Integer; + /* E(%) = C / (8 * (2 - OVER8) * (DIV_Integer + 1) * B) - 1 */ + /* u64Temp = (8 * (2 - OVER8) * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + \ + (uint64_t)1UL) * (uint64_t)B); + f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + pstcUartBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + return i32Ret; +} + +/** + * @brief Calculate baudrate division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcClockSyncBrr Pointer to a stc_usart_brr_t structure. + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + */ +static int32_t ClockSync_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcClockSyncBrr) +{ + uint32_t B; + uint32_t C; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_IntegerMod; + uint32_t DIV_Fraction; + float32_t f32CalcError; + uint32_t u32FractionFlag = 1UL; + int32_t i32Ret = LL_ERR; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + C = pstcClockSyncBrr->u32UsartClock; + B = pstcClockSyncBrr->u32Baudrate; + if ((C > 0UL) && (B > 0UL)) { + /* Clock sync mode baudrate integer calculation formula: */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV_Integer = (C / (B * 4UL)) - 1UL; + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcClockSyncBrr->u32Integer = DIV_Integer; + DIV_IntegerMod = C % (B * 4UL); + if (0UL == DIV_IntegerMod) { + /* Get accurate baudrate without fraction */ + pstcClockSyncBrr->f32Error = (float32_t)0.0F; + i32Ret = LL_OK; + } else { + /* Clock sync mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = 256 * (4 * (DIV_Integer + 1) * B) / C - 128 */ + + /* u64Temp = (4 * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + DIV_Fraction = (uint32_t)((256UL * u64Temp + ((uint64_t)C >> 1)) / C - 128UL); /* +(C >> 1) for rounding off */ + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + pstcClockSyncBrr->u32Fraction = DIV_Fraction; + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32CalcError = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + pstcClockSyncBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } else { + u32FractionFlag = 0UL; + } + } + } + if (0UL == u32FractionFlag) { + /* Integer rounding off */ + DIV_Integer = ((((C * 10UL) / (B * 4UL)) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcClockSyncBrr->u32Integer = DIV_Integer; + /* E(%) = C / (4 * (DIV_Integer + 1) * B) - 1 */ + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + pstcClockSyncBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + return i32Ret; +} + +/** + * @brief Calculate baudrate division for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcSmartCardBrr Pointer to a stc_usart_brr_t structure. + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR: Set unsuccessfully. + */ +static int32_t SmartCard_CalculateBrr(const CM_USART_TypeDef *USARTx, stc_usart_brr_t *pstcSmartCardBrr) +{ + uint32_t B; + uint32_t C; + uint32_t BCN; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_IntegerMod; + uint32_t DIV_Fraction; + float32_t f32CalcError; + const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U}; + int32_t i32Ret = LL_ERR; + + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + + C = pstcSmartCardBrr->u32UsartClock; + B = pstcSmartCardBrr->u32Baudrate; + if ((C > 0UL) && (B > 0UL)) { + BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN)); + BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS]; + /* Smartcard mode baudrate integer calculation formula: */ + /* B = C / (2 * BCN * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */ + DIV_Integer = (C / (B * BCN * 2UL)) - 1UL; + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcSmartCardBrr->u32Integer = DIV_Integer; + DIV_IntegerMod = C % (B * BCN * 2UL); + if (0UL == DIV_IntegerMod) { + /* Get accurate baudrate without fraction */ + pstcSmartCardBrr->f32Error = (float32_t)0.0F; + i32Ret = LL_OK; + } else { + /* Smartcard mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / ((2 * BCN) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (2 * BCN * (DIV_Integer + 1) * B) / C) - 128 */ + + /* u64Temp = (2 * BCN * (DIV_Integer + 1) * B) */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + DIV_Fraction = (uint32_t)((256UL * u64Temp + ((uint64_t)C >> 1)) / C - 128UL); /* +(C >> 1) for rounding off */ + if (DIV_Fraction <= USART_BRR_DIV_FRACTION_MAX) { + pstcSmartCardBrr->u32Fraction = DIV_Fraction; + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32CalcError = (float32_t)((float64_t)u64Dividend / (float64_t)(u64Temp)) - 1.0F; + pstcSmartCardBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + if (LL_ERR == i32Ret) { + /* Integer rounding off */ + DIV_Integer = (((C * 10UL) / (B * BCN * 2UL) + 5UL) / 10UL) - 1UL; /* +5UL for rounding off */ + if (DIV_Integer <= USART_BRR_DIV_INTEGER_MAX) { + pstcSmartCardBrr->u32Integer = DIV_Integer; + /* E(%) = C / (2 * BCN * (DIV_Integer + 1) * B) - 1 */ + /* u64Temp = 4 * (DIV_Integer + 1) * B */ + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + f32CalcError = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + pstcSmartCardBrr->f32Error = f32CalcError; + i32Ret = LL_OK; + } + } + } + return i32Ret; +} + +/** + * @brief Get bus(which USART mounts on) clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART clock frequency value + */ +static uint32_t USART_GetBusClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + + (void)USARTx; + + u32BusClock = SystemCoreClock >> (READ_REG32_BIT(CM_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + + return u32BusClock; +} + +/** + * @brief Get USART clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART clock frequency value + */ +static uint32_t USART_GetUsartClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + uint32_t u32UsartClockDiv; + uint32_t u32UsartClock; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + u32BusClock = USART_GetBusClockFreq(USARTx); + + if (USART_PR_ULBREN == READ_REG32_BIT(USARTx->PR, USART_PR_ULBREN)) { + u32UsartClockDiv = (128UL << READ_REG32_BIT(USARTx->PR, USART_PR_PSC)); + } else { + u32UsartClockDiv = (1UL << (READ_REG32_BIT(USARTx->PR, USART_PR_PSC) * 2UL)); + } + + u32UsartClock = u32BusClock / u32UsartClockDiv; + return u32UsartClock; +} + +/** + * @brief Get USART BMC clock frequency value. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval USART BMC clock frequency value + */ +static uint32_t USART_GetLinBmcClockFreq(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BusClock; + uint32_t u32UsartBmcDiv; + uint32_t u32UsartBmcClock; + + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + u32BusClock = USART_GetBusClockFreq(USARTx); + u32UsartBmcDiv = (1UL << (READ_REG32_BIT((USARTx)->PR, USART_PR_LBMPSC) >> USART_PR_LBMPSC_POS)); + + u32UsartBmcClock = u32BusClock / u32UsartBmcDiv; + return u32UsartBmcClock; +} + +/** + * @} + */ + +/** + * @defgroup USART_Global_Functions USART Global Functions + * @{ + */ + +/** + * @brief Set the fields of structure stc_usart_clocksync_init_t to default values. + * @param [out] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL. + */ +int32_t USART_ClockSync_StructInit(stc_usart_clocksync_init_t *pstcClockSyncInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + pstcClockSyncInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcClockSyncInit->u32ClockDiv = USART_CLK_DIV1; + pstcClockSyncInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcClockSyncInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcClockSyncInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize clock synchronization function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcClockSyncInit Pointer to a @ref stc_usart_clocksync_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcClockSyncInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_ClockSync_Init(CM_USART_TypeDef *USARTx, + const stc_usart_clocksync_init_t *pstcClockSyncInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcClockSyncInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcClockSyncInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcClockSyncInit->u32FirstBit)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcClockSyncInit->u32HWFlowControl)); + + u32CR1Value = (pstcClockSyncInit->u32FirstBit | USART_CR1_MS | USART_CR1_SBS); + u32CR2Value = (pstcClockSyncInit->u32ClockSrc | USART_CR2_RST_VALUE); + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + u32CR2Value |= USART_CK_OUTPUT_ENABLE; + } + u32CR3Value = pstcClockSyncInit->u32HWFlowControl; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcClockSyncInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcClockSyncInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcClockSyncInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcClockSyncInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_multiprocessor_init_t to default values. + * @param [out] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMultiProcessorInit value is NULL. + */ +int32_t USART_MultiProcessor_StructInit(stc_usart_multiprocessor_init_t *pstcMultiProcessorInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + pstcMultiProcessorInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcMultiProcessorInit->u32ClockDiv = USART_CLK_DIV1; + pstcMultiProcessorInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcMultiProcessorInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcMultiProcessorInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcMultiProcessorInit->u32StopBit = USART_STOPBIT_1BIT; + pstcMultiProcessorInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcMultiProcessorInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcMultiProcessorInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcMultiProcessorInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART multiple processor function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcMultiProcessorInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcMxProcessorInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_MultiProcessor_Init(CM_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcMultiProcessorInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcMultiProcessorInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcMultiProcessorInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcMultiProcessorInit->u32CKOutput)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcMultiProcessorInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcMultiProcessorInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcMultiProcessorInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcMultiProcessorInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcMultiProcessorInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcMultiProcessorInit->u32HWFlowControl)); + + u32CR1Value = (pstcMultiProcessorInit->u32DataWidth | pstcMultiProcessorInit->u32OverSampleBit | \ + pstcMultiProcessorInit->u32FirstBit | pstcMultiProcessorInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | USART_CR2_MPE | pstcMultiProcessorInit->u32ClockSrc | \ + pstcMultiProcessorInit->u32CKOutput | pstcMultiProcessorInit->u32StopBit); + u32CR3Value = pstcMultiProcessorInit->u32HWFlowControl; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcMultiProcessorInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcMultiProcessorInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcMultiProcessorInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcMultiProcessorInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_uart_init_t to default values. + * @param [out] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL. + */ +int32_t USART_UART_StructInit(stc_usart_uart_init_t *pstcUartInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + pstcUartInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcUartInit->u32ClockDiv = USART_CLK_DIV1; + pstcUartInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcUartInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcUartInit->u32DataWidth = USART_DATA_WIDTH_8BIT; + pstcUartInit->u32StopBit = USART_STOPBIT_1BIT; + pstcUartInit->u32Parity = USART_PARITY_NONE; + pstcUartInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcUartInit->u32FirstBit = USART_FIRST_BIT_LSB; + pstcUartInit->u32StartBitPolarity = USART_START_BIT_FALLING; + pstcUartInit->u32HWFlowControl = USART_HW_FLOWCTRL_RTS; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize UART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_UART_Init(CM_USART_TypeDef *USARTx, const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcUartInit) { + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcUartInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcUartInit->u32CKOutput)); + DDL_ASSERT(IS_USART_PARITY(pstcUartInit->u32Parity)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcUartInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOPBIT(pstcUartInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcUartInit->u32OverSampleBit)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcUartInit->u32FirstBit)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(pstcUartInit->u32StartBitPolarity)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(pstcUartInit->u32HWFlowControl)); + + u32CR1Value = (pstcUartInit->u32Parity | pstcUartInit->u32DataWidth | pstcUartInit->u32FirstBit | \ + pstcUartInit->u32OverSampleBit | pstcUartInit->u32StartBitPolarity); + u32CR2Value = (USART_CR2_RST_VALUE | pstcUartInit->u32ClockSrc | \ + pstcUartInit->u32CKOutput | pstcUartInit->u32StopBit); + u32CR3Value = pstcUartInit->u32HWFlowControl; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + if (USART_CLK_SRC_INTERNCLK == pstcUartInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcUartInit->u32ClockDiv)); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcUartInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcUartInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Initialize UART half duplex function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcUartInit Pointer to a @ref stc_usart_uart_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcUartInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_HalfDuplex_Init(CM_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcUartInit, float32_t *pf32Error) +{ + int32_t i32Ret; + + i32Ret = USART_UART_Init(USARTx, pstcUartInit, pf32Error); + if (LL_OK == i32Ret) { + /* Set CR3: UART half duplex */ + SET_REG32_BIT(USARTx->CR3, USART_CR3_HDSEL); + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_lin_init_t to default values. + * @param [out] pstcLinInit Pointer to a @ref stc_usart_lin_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcLinInit is NULL. + */ +int32_t USART_LIN_StructInit(stc_usart_lin_init_t *pstcLinInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcLinInit) { + pstcLinInit->u32ClockSrc = USART_CLK_SRC_INTERNCLK; + pstcLinInit->u32ClockDiv = USART_CLK_DIV1; + pstcLinInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcLinInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcLinInit->u32OverSampleBit = USART_OVER_SAMPLE_16BIT; + pstcLinInit->u32BmcClockDiv = USART_LIN_BMC_CLK_DIV1; + pstcLinInit->u32DetectBreakLen = USART_LIN_DETECT_BREAK_10BIT; + pstcLinInit->u32SendBreakLen = USART_LIN_SEND_BREAK_10BIT; + pstcLinInit->u32SendBreakMode = USART_LIN_SEND_BREAK_MD_SBK; + i32Ret = LL_OK; + } + + return i32Ret; +} + +/** + * @brief Initialize LIN function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcLinInit Pointer to a @ref stc_usart_lin_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcLinInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_LIN_Init(CM_USART_TypeDef *USARTx, const stc_usart_lin_init_t *pstcLinInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32PRValue; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcLinInit) { + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(pstcLinInit->u32ClockSrc)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcLinInit->u32CKOutput)); + DDL_ASSERT(IS_USART_CLK_DIV(pstcLinInit->u32ClockDiv)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(pstcLinInit->u32OverSampleBit)); + + u32CR1Value = (pstcLinInit->u32OverSampleBit | USART_CR1_SBS); + u32CR2Value = (pstcLinInit->u32ClockSrc | pstcLinInit->u32CKOutput | USART_CR2_LINEN | USART_CR2_RST_VALUE); + + DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(pstcLinInit->u32DetectBreakLen)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(pstcLinInit->u32SendBreakLen)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MD(pstcLinInit->u32SendBreakMode)); + u32CR2Value |= (pstcLinInit->u32DetectBreakLen | pstcLinInit->u32SendBreakLen | pstcLinInit->u32SendBreakMode); + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, 0UL); + + if (USART_CLK_SRC_INTERNCLK == pstcLinInit->u32ClockSrc) { + DDL_ASSERT(IS_USART_CLK_DIV(pstcLinInit->u32ClockDiv)); + u32PRValue = pstcLinInit->u32ClockDiv; + + DDL_ASSERT(IS_USART_LIN_BMC_CLK_DIV(pstcLinInit->u32BmcClockDiv)); + u32PRValue |= pstcLinInit->u32BmcClockDiv; + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, u32PRValue); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcLinInit->u32Baudrate, pf32Error); + } else { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief Set the fields of structure stc_usart_smartcard_init_t to default values. + * @param [out] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL. + */ +int32_t USART_SmartCard_StructInit(stc_usart_smartcard_init_t *pstcSmartCardInit) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + pstcSmartCardInit->u32ClockDiv = USART_CLK_DIV1; + pstcSmartCardInit->u32CKOutput = USART_CK_OUTPUT_DISABLE; + pstcSmartCardInit->u32Baudrate = USART_DEFAULT_BAUDRATE; + pstcSmartCardInit->u32FirstBit = USART_FIRST_BIT_LSB; + i32Ret = LL_OK; + } + + return i32Ret; +} +/** + * @brief Initialize smartcard function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] pstcSmartCardInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR_INVD_PARAM: The pointer pstcSmartCardInit value is NULL or baudrate set unsuccessfully. + */ +int32_t USART_SmartCard_Init(CM_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcSmartCardInit, float32_t *pf32Error) +{ + uint32_t u32CR1Value; + uint32_t u32CR2Value; + uint32_t u32CR3Value; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pstcSmartCardInit) { + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CK_OUTPUT(pstcSmartCardInit->u32CKOutput)); + DDL_ASSERT(IS_USART_CLK_DIV(pstcSmartCardInit->u32ClockDiv)); + DDL_ASSERT(IS_USART_FIRST_BIT(pstcSmartCardInit->u32FirstBit)); + + u32CR1Value = (pstcSmartCardInit->u32FirstBit | USART_CR1_PCE | USART_CR1_SBS); + u32CR2Value = (pstcSmartCardInit->u32CKOutput | USART_CR2_RST_VALUE); + u32CR3Value = USART_CR3_SCEN | USART_SC_ETU_CLK372; + + /* Set control register: CR1/CR2/CR3 */ + WRITE_REG32(USARTx->CR1, u32CR1Value); + WRITE_REG32(USARTx->CR2, u32CR2Value); + WRITE_REG32(USARTx->CR3, u32CR3Value); + + /* Set prescaler register register: PR */ + WRITE_REG32(USARTx->PR, pstcSmartCardInit->u32ClockDiv); + + /* Set baudrate */ + i32Ret = USART_SetBaudrate(USARTx, pstcSmartCardInit->u32Baudrate, pf32Error); + } + + return i32Ret; +} + +/** + * @brief De-Initialize USART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval int32_t: + * - LL_OK: Reset success. + * - LL_ERR_TIMEOUT: Reset time out. + * @note Call LL_PERIPH_WE(LL_PERIPH_PWC_CLK_RMU) unlock RMU_FRSTx register first. + */ +int32_t USART_DeInit(CM_USART_TypeDef *USARTx) +{ + uint32_t i; + int32_t i32Ret = LL_OK; + __IO uint8_t u8TimeOut = 0U; + __IO uint32_t *bCM_RMU_FRST3_USARTx = NULL; + const uint32_t au32USARTx[] = {CM_USART1_BASE, CM_USART2_BASE, CM_USART3_BASE, \ + CM_USART4_BASE, CM_USART5_BASE, CM_USART6_BASE + }; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + for (i = 0UL; i < ARRAY_SZ(au32USARTx); i++) { + if ((uint32_t)USARTx == au32USARTx[i]) { + bCM_RMU_FRST3_USARTx = (__IO uint32_t *)((uint32_t)&bCM_RMU->FRST3_b.USART1 + (i << 2)); + break; + } + } + + /* Reset USART */ + WRITE_REG32(*bCM_RMU_FRST3_USARTx, 0UL); + + /* Ensure reset procedure is completed */ + while (READ_REG32(*bCM_RMU_FRST3_USARTx) != 1UL) { + u8TimeOut++; + if (u8TimeOut > USART_RMU_TIMEOUT) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + } + + return i32Ret; +} + +/** + * @brief Enable/disable USART Transmit/Receive Function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Func USART function type + * This parameter can be any composed value of the macros group @ref USART_Function. + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + * @note In clock synchronization mode, the bit TE or RE of register USART_CR can only be + * written to 1 when TE = 0 and RE = 0 (transmit and receive disabled) + */ +void USART_FuncCmd(CM_USART_TypeDef *USARTx, uint32_t u32Func, en_functional_state_t enNewState) +{ + uint32_t u32BaseFunc; + uint32_t u32LinFunc; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_USART_FUNC(u32Func)); + DDL_ASSERT(IS_USART_LIN_FUNC(USARTx, u32Func)); + DDL_ASSERT(IS_USART_TIMEOUT_FUNC(USARTx, u32Func)); + + u32BaseFunc = (u32Func & 0xFFFFUL); + if (u32BaseFunc > 0UL) { + (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR1, u32BaseFunc) : CLR_REG32_BIT(USARTx->CR1, u32BaseFunc); + } + + u32LinFunc = ((u32Func & USART_LIN_FUNC_MASK) >> USART_LIN_FUNC_OFFSET); + if (u32LinFunc > 0UL) { + (ENABLE == enNewState) ? SET_REG32_BIT(USARTx->CR2, u32LinFunc) : CLR_REG32_BIT(USARTx->CR2, u32LinFunc); + } +} + +/** + * @brief Enable/disable USART Transmit/Receive Function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Func USART function type + * This parameter can be any composed value of the macros group @ref USART_Function. + * @retval An @ref en_functional_state_t enumeration value. + * - ENABLE: DVP capture started + * - DISABLE: DVP capture stopped + * @note In clock synchronization mode, the bit TE or RE of register USART_CR can only be + * written to 1 when TE = 0 and RE = 0 (transmit and receive disabled) + */ +en_functional_state_t USART_GetFuncState(CM_USART_TypeDef *USARTx, uint32_t u32Func) +{ + uint32_t u32BaseFunc; + en_functional_state_t enNewState = DISABLE; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FUNC(u32Func)); + DDL_ASSERT(IS_USART_LIN_FUNC(USARTx, u32Func)); + DDL_ASSERT(IS_USART_TIMEOUT_FUNC(USARTx, u32Func)); + + u32BaseFunc = (u32Func & 0xFFFFUL); + if (0UL != u32BaseFunc) { + if (0UL != READ_REG32_BIT(USARTx->CR1, u32BaseFunc)) { + enNewState = ENABLE; + } + } + u32BaseFunc = u32Func >> USART_LIN_FUNC_OFFSET; + if (0UL != u32BaseFunc) { + if (0UL != READ_REG32_BIT(USARTx->CR2, u32BaseFunc)) { + enNewState = ENABLE; + } + } + return enNewState; +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the macros group @ref USART_Flag. + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t USART_GetStatus(const CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + return (0UL == (READ_REG32_BIT(USARTx->SR, u32Flag)) ? RESET : SET); +} + +/** + * @brief Clear USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the macros group @ref USART_Flag. + * @retval None + */ +void USART_ClearStatus(CM_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + if ((u32Flag & USART_FLAG_ERR_MASK) > 0UL) { + SET_REG32_BIT(USARTx->CR1, (u32Flag & USART_FLAG_ERR_MASK) << USART_CR1_CPE_POS); + } + + /* Timeout flag */ + if ((u32Flag & USART_FLAG_RX_TIMEOUT) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CRTOF); + } + + /* LIN flag */ + if ((u32Flag & USART_FLAG_LIN_ERR) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CBE); + } + + if ((u32Flag & USART_FLAG_LIN_WKUP) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CWKUP); + } + + if ((u32Flag & USART_FLAG_LIN_BREAK) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CLBD); + } + + /* Transmission complete flag */ + if ((u32Flag & USART_FLAG_TX_END) > 0UL) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_CTEND); + } +} + +/** + * @brief Set USART parity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Parity USART parity + * This parameter can be one of the macros group @ref USART_Parity_Control + * @arg USART_PARITY_NONE: Parity control disabled + * @arg USART_PARITY_ODD: Parity control enabled and Odd Parity is selected + * @arg USART_PARITY_EVEN: Parity control enabled and Even Parity is selected + * @retval None + */ +void USART_SetParity(CM_USART_TypeDef *USARTx, uint32_t u32Parity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_PARITY(u32Parity)); + + MODIFY_REG32(USARTx->CR1, (USART_CR1_PS | USART_CR1_PCE), u32Parity); +} + +/** + * @brief Set USART bit direction. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32FirstBit USART bit direction + * This parameter can be one of the macros group @ref USART_First_Bit + * @arg USART_FIRST_BIT_MSB: MSB(Most Significant Bit) + * @arg USART_FIRST_BIT_LSB: LSB(Least Significant Bit) + * @retval None + */ +void USART_SetFirstBit(CM_USART_TypeDef *USARTx, uint32_t u32FirstBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_FIRST_BIT(u32FirstBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_ML, u32FirstBit); +} + +/** + * @brief Set USART stop bit. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32StopBit USART stop bits + * This parameter can be one of the macros group @ref USART_Stop_Bit + * @arg USART_STOPBIT_1BIT: 1 stop bit + * @arg USART_STOPBIT_2BIT: 2 stop bit + * @retval None + */ +void USART_SetStopBit(CM_USART_TypeDef *USARTx, uint32_t u32StopBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_STOPBIT(u32StopBit)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_STOP, u32StopBit); +} + +/** + * @brief Set USART data width. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32DataWidth USART data width + * This parameter can be one of the macros group @ref USART_Data_Width_Bit + * @arg USART_DATA_WIDTH_8BIT: 8 bits word width + * @arg USART_DATA_WIDTH_9BIT: 9 bits word width + * @retval None + */ +void USART_SetDataWidth(CM_USART_TypeDef *USARTx, uint32_t u32DataWidth) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_M, u32DataWidth); +} + +/** + * @brief Set USART oversampling bits. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32OverSampleBit USART over sample bit + * This parameter can be one of the macros group @ref USART_Over_Sample_Bit + * @arg USART_OVER_SAMPLE_8BIT: Oversampling by 8 bit + * @arg USART_OVER_SAMPLE_16BIT: Oversampling by 16 bit + * @retval None + */ +void USART_SetOverSampleBit(CM_USART_TypeDef *USARTx, uint32_t u32OverSampleBit) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_OVER_SAMPLE_BIT(u32OverSampleBit)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_OVER8, u32OverSampleBit); +} + +/** + * @brief Set USART start bit detect polarity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Polarity USART start bit detect polarity + * This parameter can be one of the macros group @ref USART_Start_Bit_Polarity + * @arg USART_START_BIT_LOW: Detect RX pin low level + * @arg USART_START_BIT_FALLING: Detect RX pin falling edge + * @retval None + */ +void USART_SetStartBitPolarity(CM_USART_TypeDef *USARTx, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_START_BIT_POLARITY(u32Polarity)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_SBS, u32Polarity); +} + +/** + * @brief Set USART transmission type. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u16Type USART transmission content type + * This parameter can be one of the macros group @ref USART_Transmission_Type + * @arg USART_TRANS_ID: USART transmission content type is processor ID + * @arg USART_TRANS_DATA: USART transmission content type is frame data + * @retval None + */ +void USART_SetTransType(CM_USART_TypeDef *USARTx, uint16_t u16Type) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_TRANS_TYPE(u16Type)); + + MODIFY_REG16(USARTx->TDR, USART_TDR_MPID, u16Type); +} + +/** + * @brief Set USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockDiv USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_Clock_Division + * @retval None + * @note The clock division function is valid only when clock source is internal clock. + */ +void USART_SetClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_DIV(u32ClockDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_PSC | USART_PR_ULBREN, u32ClockDiv); +} + +/** + * @brief Get USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the macros group @ref USART_Clock_Division + * @note The clock division function is valid only when clock source is internal clock. + */ +uint32_t USART_GetClockDiv(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->PR, USART_PR_PSC | USART_PR_ULBREN); +} + +/** + * @brief Set USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockSrc USART clock source + * This parameter can be one of the macros group @ref USART_Clock_Source + * @arg USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * @arg USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + * @retval None + */ +void USART_SetClockSrc(CM_USART_TypeDef *USARTx, uint32_t u32ClockSrc) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_CLK_SRC(u32ClockSrc)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_CLKC_1, u32ClockSrc); +} + +/** + * @brief Get USART clock source. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_CLK_SRC_EXTCLK: Clock source is external clock(USART_CK). + * - USART_CLK_SRC_INTERNCLK: Clock source is internal clock. + */ +uint32_t USART_GetClockSrc(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC_1); +} + +/** + * @brief Enable or disable USART noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_FilterCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_NFE); + } +} + +/** + * @brief Enable or disable USART silence. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_SilenceCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } else { + CLR_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } +} + +/** + * @brief Set UART hardware flow control CTS/RTS selection. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32HWFlowControl USART hardware flow control CTS/RTS selection + * This parameter can be one of the macros group @ref USART_Hardware_Flow_Control. + * @retval None + */ +void USART_SetHWFlowControl(CM_USART_TypeDef *USARTx, uint32_t u32HWFlowControl) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_HW_FLOWCTRL(u32HWFlowControl)); + + MODIFY_REG32(USARTx->CR3, (USART_CR3_CTSE | USART_CR3_RTSE), u32HWFlowControl); +} + +/** + * @brief USART receive data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Receive data + */ +uint16_t USART_ReadData(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return READ_REG16(USARTx->RDR); +} + +/** + * @brief USART send data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u16Data Transmit data + * @retval None + */ +void USART_WriteData(CM_USART_TypeDef *USARTx, uint16_t u16Data) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16Data)); + + WRITE_REG16(USARTx->TDR, u16Data); +} + +/** + * @brief USART send processor ID. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + ** @param [in] u16ID Processor ID + * @retval None + */ +void USART_WriteID(CM_USART_TypeDef *USARTx, uint16_t u16ID) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + DDL_ASSERT(IS_USART_DATA(u16ID)); + + WRITE_REG16(USARTx->TDR, (USART_TDR_MPID | u16ID)); +} + +/** + * @brief Set USART baudrate. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Baudrate UART baudrate + * @param [out] pf32Error E(%) baudrate error rate + * @retval int32_t: + * - LL_OK: Set successfully. + * - LL_ERR_INVD_PARAM: Set unsuccessfully. + * @note The function uses fraction division to ensure baudrate accuracy if USART unit supports baudrate fraction division. + */ +int32_t USART_SetBaudrate(CM_USART_TypeDef *USARTx, uint32_t u32Baudrate, float32_t *pf32Error) +{ + uint32_t u32Mode; + stc_usart_brr_t stcUsartBrr; + int32_t i32Ret; + + DDL_ASSERT(u32Baudrate > 0UL); + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + /* Get USART clock frequency */ + stcUsartBrr.u32UsartClock = USART_GetUsartClockFreq(USARTx); + stcUsartBrr.u32Baudrate = u32Baudrate; + stcUsartBrr.f32Error = 0.0F; + stcUsartBrr.u32Fraction = 0xFFUL; + + /* Get usart mode */ + u32Mode = READ_REG32_BIT(USARTx->CR1, USART_CR1_MS); + /* Calculate baudrate for BRR */ + if (0UL == u32Mode) { + if (0UL == READ_REG32_BIT(USARTx->CR3, USART_CR3_SCEN)) { + /* uart mode */ + i32Ret = UART_CalculateBrr(USARTx, &stcUsartBrr); + } else { + /* Smart_card function */ + i32Ret = SmartCard_CalculateBrr(USARTx, &stcUsartBrr); + } + } else { + /* Clock sync mode */ + i32Ret = ClockSync_CalculateBrr(USARTx, &stcUsartBrr); + } + + if (LL_OK == i32Ret) { + /* Set BRR value(integer & fraction) */ + MODIFY_REG32(USARTx->BRR, (USART_BRR_DIV_INTEGER | USART_BRR_DIV_FRACTION), \ + (stcUsartBrr.u32Fraction | (stcUsartBrr.u32Integer << USART_BRR_DIV_INTEGER_POS))); + + if (0xFFUL != stcUsartBrr.u32Fraction) { + SET_REG32_BIT(USARTx->CR1, USART_CR1_FBME); + } + } else { + /* rsvd */ + } + if (NULL != pf32Error) { + *pf32Error = stcUsartBrr.f32Error; + } + + return i32Ret; +} + +/** + * @brief Set USART Smartcard ETU Clock. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32EtuClock USART Smartcard ETU Clock. + * This parameter can be one of the macros group @ref USART_Smartcard_ETU_Clock + * @arg USART_SC_ETU_CLK32: 1 etu = 32/f + * @arg USART_SC_ETU_CLK64: 1 etu = 64/f + * @arg USART_SC_ETU_CLK128: 1 etu = 128/f + * @arg USART_SC_ETU_CLK256: 1 etu = 256/f + * @arg USART_SC_ETU_CLK372: 1 etu = 372/f + * @retval None + */ +void USART_SmartCard_SetEtuClock(CM_USART_TypeDef *USARTx, uint32_t u32EtuClock) +{ + DDL_ASSERT(IS_USART_SMARTCARD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(u32EtuClock)); + + MODIFY_REG32(USARTx->CR3, USART_CR3_BCN, u32EtuClock); +} + +/** + * @brief Enable/disable stop mode noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_StopModeNoiseFilterCmd(const CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_STOP_MD_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USART1_NFE); + } else { + CLR_REG32_BIT(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USART1_NFE); + } +} + +/** + * @brief Set stop mode noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Level The noise filter width level value + * This parameter can be one of the macros group @ref USART_Stop_Mode_Noise_Filter_Width_Level + * @arg USART_STOP_MD_FILTER_LVL1: Filter width level 1 + * @arg USART_STOP_MD_FILTER_LVL2: Filter width level 2 + * @arg USART_STOP_MD_FILTER_LVL3: Filter width level 3 + * @arg USART_STOP_MD_FILTER_LVL4: Filter width level 4 + * @retval None + */ +void USART_SetStopModeNoiseFilter(const CM_USART_TypeDef *USARTx, uint32_t u32Level) +{ + DDL_ASSERT(IS_USART_STOP_MD_UNIT(USARTx)); + DDL_ASSERT(IS_USART_STOP_MD_FILTER(u32Level)); + + MODIFY_REG32(CM_PERIC->USART1_NFC, PERIC_USART1_NFC_USASRT1_NFS, u32Level); +} + +/** + * @brief Enable or disable USART loopback function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] enNewState An @ref en_functional_state_t enumeration value. + * @retval None + */ +void USART_LIN_LoopbackCmd(CM_USART_TypeDef *USARTx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (ENABLE == enNewState) { + SET_REG32_BIT(USARTx->CR3, USART_CR3_LOOP); + } else { + CLR_REG32_BIT(USARTx->CR3, USART_CR3_LOOP); + } +} + +/** + * @brief Set USART LIN counter clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32ClockDiv USART USART LIN counter clock prescaler division. + * This parameter can be one of the macros group @ref USART_LIN_BMC_Clock_Division + * @arg USART_LIN_BMC_CLK_DIV1: CLK + * @arg USART_LIN_BMC_CLK_DIV2: CLK/2 + * @arg USART_LIN_BMC_CLK_DIV4: CLK/4 + * @arg USART_LIN_BMC_CLK_DIV8: CLK/8 + * @retval None + * @note The clock division function is valid when clock source is internal clock. + */ +void USART_LIN_SetBmcClockDiv(CM_USART_TypeDef *USARTx, uint32_t u32ClockDiv) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_BMC_CLK_DIV(u32ClockDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_LBMPSC, u32ClockDiv); +} + +/** + * @brief LIN Request break sending + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval None + */ +void USART_LIN_RequestBreakSending(CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + SET_REG32_BIT(USARTx->CR2, USART_CR2_SBK); +} + +/** + * @brief Get request break sending status + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t USART_LIN_GetRequestBreakStatus(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + return (0UL == READ_REG32_BIT(USARTx->CR2, USART_CR2_SBK)) ? RESET : SET; +} + +/** + * @brief Set send break mode for USART LIN. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Mode USART send break mode + * This parameter can be one of the macros group @ref USART_LIN_Send_Break_Mode + * @arg USART_LIN_SEND_BREAK_MD_SBK: Start send break after USART_CR2 SBK bit set 1 value + * @arg USART_LIN_SEND_BREAK_MD_TDR: Start send break after USART_DR TDR write 0x00 value + * @retval None + */ +void USART_LIN_SetBreakMode(CM_USART_TypeDef *USARTx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MD(u32Mode)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_SBKM, u32Mode); +} + +/** + * @brief Get send break mode for USART LIN. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval Returned value can be one of the following values: + * - USART_LIN_SEND_BREAK_MD_SBK: Start send break after USART_CR2 SBK bit set 1 value + * - USART_LIN_SEND_BREAK_MD_TDR: Start send break after USART_DR TDR write 0x00 value + */ +uint32_t USART_LIN_GetBreakMode(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_SBKM); +} + +/** + * @brief Get USART LIN baudrate measure count. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval LIN baudrate measure count value + */ +uint32_t USART_LIN_GetMeasureCount(const CM_USART_TypeDef *USARTx) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + return READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC); +} + +/** + * @brief Get USART LIN baudrate measure count. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @retval LIN baudrate measure count value + */ +uint32_t USART_LIN_GetMeasureBaudrate(const CM_USART_TypeDef *USARTx) +{ + uint32_t u32BmClk; + uint32_t u32LBMC; + + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + + u32BmClk = USART_GetLinBmcClockFreq(USARTx); + u32LBMC = READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC); + + return (u32LBMC > 0UL) ? (u32BmClk / u32LBMC) : 0UL; +} + +/** + * @brief Set USART LIN break detection length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Len USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_LIN_Detect_Break_Length + * @arg USART_LIN_DETECT_BREAK_10BIT: 10-bit break detection + * @arg USART_LIN_DETECT_BREAK_11BIT: 11-bit break detection + * @retval None + */ +void USART_LIN_SetDetectBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(u32Len)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_LBDL, u32Len); +} + +/** + * @brief Set USART LIN break sending length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] u32Len USART clock prescaler division. + * This parameter can be one of the macros group @ref USART_LIN_Send_Break_Length + * @arg USART_LIN_SEND_BREAK_10BIT: Send break 10-bit + * @arg USART_LIN_SEND_BREAK_11BIT: Send break 11-bit + * @arg USART_LIN_SEND_BREAK_13BIT: Send break 13-bit + * @arg USART_LIN_SEND_BREAK_14BIT: Send break 14-bit + * @retval None + */ +void USART_LIN_SetSendBreakLen(CM_USART_TypeDef *USARTx, uint32_t u32Len) +{ + DDL_ASSERT(IS_USART_LIN_UNIT(USARTx)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(u32Len)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_SBKL, u32Len); +} + +/** + * @brief UART transmit data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data transmitted buffer + * @param [in] u32Len Amount of frame to be sent. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or pvBuf is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Trans(CM_USART_TypeDef *USARTx, const void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint32_t u32DataWidth; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + if ((USART_DATA_WIDTH_8BIT == u32DataWidth) || (USART_DATA_WIDTH_9BIT == u32DataWidth)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK != i32Ret) { + break; + } + + if (u32DataWidth == USART_DATA_WIDTH_8BIT) { + USART_WriteData(USARTx, ((const uint8_t *)pvBuf)[i]); + } else { + USART_WriteData(USARTx, ((const uint16_t *)pvBuf)[i]); + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + } + + return i32Ret; +} + +/** + * @brief UART receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] pvBuf The pointer to data received buffer + * @param [in] u32Len Amount of frame to be received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer pvBuf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_UART_Receive(const CM_USART_TypeDef *USARTx, void *pvBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t u32Count; + uint32_t u32DataWidth; + uint16_t u16ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != pvBuf) && (u32Len > 0UL)) { + u32DataWidth = READ_REG32_BIT(USARTx->CR1, USART_CR1_M); + + for (u32Count = 0UL; u32Count < u32Len; u32Count++) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u16ReceiveData = USART_ReadData(USARTx); + if (USART_DATA_WIDTH_8BIT == u32DataWidth) { + ((uint8_t *)pvBuf)[u32Count] = (uint8_t)(u16ReceiveData & 0xFFU); + } else { + ((uint16_t *)pvBuf)[u32Count] = (uint16_t)(u16ReceiveData & 0x1FFU); + } + } else { + break; + } + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8Buf The pointer to data transmitted buffer + * @param [in] u32Len Amount of data to be transmitted. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT + */ +int32_t USART_ClockSync_Trans(CM_USART_TypeDef *USARTx, const uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + for (i = 0UL; i < u32Len; i++) { + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + USART_WriteData(USARTx, au8Buf[i]); + if (READ_REG32_BIT(USARTx->CR1, USART_RX) != 0UL) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + (void)USART_ReadData(USARTx); + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [out] au8Buf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0 or the pointer au8Buf value is NULL. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_Receive(CM_USART_TypeDef *USARTx, uint8_t au8Buf[], uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + en_functional_state_t enTX; + en_functional_state_t enMasterMode; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if ((NULL != au8Buf) && (u32Len > 0UL)) { + i32Ret = LL_OK; + enTX = (READ_REG32_BIT(USARTx->CR1, USART_TX) == 0UL) ? DISABLE : ENABLE; + enMasterMode = (USART_CLK_SRC_EXTCLK == READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC)) ? DISABLE : ENABLE; + + for (i = 0UL; i < u32Len; i++) { + if ((ENABLE == enMasterMode) || (ENABLE == enTX)) { + USART_WriteData(USARTx, 0xFFU); + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + au8Buf[i] = (uint8_t)USART_ReadData(USARTx); + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @brief Clock sync transmit && receive data in polling mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg CM_USARTx: USART unit instance register base + * @param [in] au8TxBuf The pointer to data transmitted buffer + * @param [out] au8RxBuf The pointer to data received buffer + * @param [in] u32Len Amount of data to be sent and received. + * @param [in] u32Timeout Timeout duration(Max value @ref USART_Max_Timeout) + * @retval int32_t: + * - LL_OK: No errors occurred. + * - LL_ERR_TIMEOUT: Communicate timeout. + * - LL_ERR_INVD_PARAM: u32Len value is 0. + * @note Block checking flag if u32Timeout value is USART_MAX_TIMEOUT. + */ +int32_t USART_ClockSync_TransReceive(CM_USART_TypeDef *USARTx, const uint8_t au8TxBuf[], uint8_t au8RxBuf[], + uint32_t u32Len, uint32_t u32Timeout) +{ + uint32_t i; + uint8_t u8ReceiveData; + int32_t i32Ret = LL_ERR_INVD_PARAM; + + DDL_ASSERT(IS_USART_UNIT(USARTx)); + + if (u32Len > 0UL) { + for (i = 0UL; i < u32Len; i++) { + if (NULL != au8TxBuf) { + USART_WriteData(USARTx, au8TxBuf[i]); + } else { + USART_WriteData(USARTx, 0xFFU); + } + + /* Wait TX buffer empty. */ + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_EMPTY, SET, u32Timeout); + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_RX_FULL, SET, u32Timeout); + if (LL_OK == i32Ret) { + u8ReceiveData = (uint8_t)USART_ReadData(USARTx); + if (NULL != au8RxBuf) { + au8RxBuf[i] = u8ReceiveData; + } + } + } + + if (LL_OK != i32Ret) { + break; + } + } + + if (LL_OK == i32Ret) { + i32Ret = USART_WaitStatus(USARTx, USART_FLAG_TX_CPLT, SET, u32Timeout); + } + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_USART_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c new file mode 100644 index 0000000000..7c2a8fb9cd --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_utility.c @@ -0,0 +1,439 @@ +/** + ******************************************************************************* + * @file hc32_ll_utility.c + * @brief This file provides utility functions for DDL. + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-06-30 CDT Modify register USART DR to USART TDR + Prohibit DDL_DelayMS and DDL_DelayUS functions from being optimized + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_UTILITY UTILITY + * @brief DDL Utility Driver + * @{ + */ + +#if (LL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup UTILITY_Local_Variables UTILITY Local Variables + * @{ + */ + +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +#if (LL_PRINT_ENABLE == DDL_ON) +static void *m_pvPrintDevice = NULL; +static uint32_t m_u32PrintTimeout = 0UL; +#endif + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup UTILITY_Local_Functions UTILITY Local Functions + * @{ + */ +#if (LL_PRINT_ENABLE == DDL_ON) + +/** + * @brief Set print device. + * @param [in] pvPrintDevice Pointer to print device + * @retval None + */ +__STATIC_INLINE void LL_SetPrintDevice(void *pvPrintDevice) +{ + m_pvPrintDevice = pvPrintDevice; +} + +/** + * @brief Get print device. + * @param None + * @retval Pointer to print device + */ +__STATIC_INLINE void *LL_GetPrintDevice(void) +{ + return m_pvPrintDevice; +} + +/** + * @brief Set print timeout. + * @param [in] u32Timeout Print timeout value + * @retval None + */ +__STATIC_INLINE void LL_SetPrintTimeout(uint32_t u32Timeout) +{ + m_u32PrintTimeout = u32Timeout; +} + +/** + * @brief Get print timeout. + * @param None + * @retval Print timeout value + */ +__STATIC_INLINE uint32_t LL_GetPrintTimeout(void) +{ + return m_u32PrintTimeout; +} +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @defgroup UTILITY_Global_Functions UTILITY Global Functions + * @{ + */ + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Count ms + * @retval None + */ +#if defined (__CC_ARM) /*!< ARM Compiler */ +#pragma push +#pragma O0 +#endif +__NO_OPTIMIZE void DDL_DelayMS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000UL - 1UL) / 10000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +__NO_OPTIMIZE void DDL_DelayUS(uint32_t u32Count) +{ + __IO uint32_t i; + const uint32_t u32Cyc = (HCLK_VALUE + 10000000UL - 1UL) / 10000000UL; + + while (u32Count-- > 0UL) { + i = u32Cyc; + while (i-- > 0UL) { + } + } +} +#if defined (__CC_ARM) /*!< ARM Compiler */ +#pragma pop +#endif + +/** + * @brief This function Initializes the interrupt frequency of the SysTick. + * @param [in] u32Freq SysTick interrupt frequency (1 to 1000). + * @retval int32_t: + * - LL_OK: SysTick Initializes succeed + * - LL_ERR: SysTick Initializes failed + */ +__WEAKDEF int32_t SysTick_Init(uint32_t u32Freq) +{ + int32_t i32Ret = LL_ERR; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(HCLK_VALUE / u32Freq)) { + i32Ret = LL_OK; + } + } + + return i32Ret; +} + +/** + * @brief This function provides minimum delay (in milliseconds). + * @param [in] u32Delay Delay specifies the delay time. + * @retval None + */ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd = u32Delay; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) { + tickEnd = tickMax; + } + while ((SysTick_GetTick() - tickStart) < tickEnd) { + } + } +} + +/** + * @brief This function is called to increment a global variable "u32TickCount". + * @note This variable is incremented in SysTick ISR. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + * @brief Provides a tick value in millisecond. + * @param None + * @retval Tick value + */ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + * @brief Suspend SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +#ifdef __DEBUG +/** + * @brief DDL assert error handle function + * @param [in] file Point to the current assert the wrong file. + * @param [in] line Point line assert the wrong file in the current. + * @retval None + */ +__WEAKDEF void DDL_AssertHandler(const char *file, int line) +{ + /* Users can re-implement this function to print information */ + DDL_Printf("Wrong parameters value: file %s on line %d\r\n", file, line); + + for (;;) { + } +} +#endif /* __DEBUG */ + +#if (LL_PRINT_ENABLE == DDL_ON) + +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ + (defined (__ICCARM__) && (__VER__ < 9000000)) || (defined (__CC_ARM)) +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (LL_OK == DDL_ConsoleOutputChar((char)ch)) ? ch : -1; +} + +#elif (defined (__ICCARM__) && (__VER__ >= 9000000)) +#include +#pragma module_name = "?__write" +size_t __dwrite(int handle, const unsigned char *buffer, size_t size) +{ + size_t nChars = 0; + size_t i; + + if (buffer == NULL) { + /* + * This means that we should flush internal buffers. Since we + * don't we just return. (Remember, "handle" == -1 means that all + * handles should be flushed.) + */ + return 0; + } + + /* This template only writes to "standard out" and "standard err", + * for all other file handles it returns failure. */ + if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR) { + return _LLIO_ERROR; + } + + for (i = 0; i < size; i++) { + if (DDL_ConsoleOutputChar((char)buffer[i]) < 0) { + return _LLIO_ERROR; + } + + ++nChars; + } + + return nChars; +} + +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) { + if (LL_OK != DDL_ConsoleOutputChar(data[i])) { + break; + } + } + } + + return i ? i : -1; +} +#endif + +/** + * @brief Initialize printf function + * @param [in] vpDevice Pointer to print device + * @param [in] u32Param Print device parameter + * @param [in] pfnPreinit The function pointer for initializing clock, port, print device etc. + * @retval int32_t: + * - LL_OK: Initialize successfully. + * - LL_ERR: The callback function pfnPreinit occurs error. + * - LL_ERR_INVD_PARAM: The pointer pfnPreinit is NULL. + */ +int32_t LL_PrintfInit(void *vpDevice, uint32_t u32Param, int32_t (*pfnPreinit)(void *vpDevice, uint32_t u32Param)) +{ + int32_t i32Ret = LL_ERR_INVD_PARAM; + + if (NULL != pfnPreinit) { + i32Ret = pfnPreinit(vpDevice, u32Param); /* The callback function initialize clock, port, print device etc */ + if (LL_OK == i32Ret) { + LL_SetPrintDevice(vpDevice); + LL_SetPrintTimeout((u32Param == 0UL) ? 0UL : (HCLK_VALUE / u32Param)); + } else { + i32Ret = LL_ERR; + DDL_ASSERT(i32Ret == LL_OK); /* Initialize unsuccessfully */ + } + } + + return i32Ret; +} + +/** + * @brief Transmit character. + * @param [in] cData The character for transmitting + * @retval int32_t: + * - LL_OK: Transmit successfully. + * - LL_ERR_TIMEOUT: Transmit timeout. + * - LL_ERR_INVD_PARAM: The print device is invalid. + */ +__WEAKDEF int32_t DDL_ConsoleOutputChar(char cData) +{ + uint32_t u32TxEmpty = 0UL; + __IO uint32_t u32TmpCount = 0UL; + int32_t i32Ret = LL_ERR_INVD_PARAM; + uint32_t u32Timeout = LL_GetPrintTimeout(); + CM_USART_TypeDef *USARTx = (CM_USART_TypeDef *)LL_GetPrintDevice(); + + if (NULL != USARTx) { + /* Wait TX data register empty */ + while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) { + u32TxEmpty = READ_REG32_BIT(USARTx->SR, USART_SR_TXE); + u32TmpCount++; + } + + if (0UL != u32TxEmpty) { + WRITE_REG16(USARTx->TDR, (uint16_t)cData); + i32Ret = LL_OK; + } else { + i32Ret = LL_ERR_TIMEOUT; + } + } + + return i32Ret; +} + +#endif /* LL_PRINT_ENABLE */ + +/** + * @} + */ + +#endif /* LL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c new file mode 100644 index 0000000000..f7bdff38a0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/drivers/hc32_ll_driver/src/hc32_ll_wdt.c @@ -0,0 +1,257 @@ +/** + ******************************************************************************* + * @file hc32_ll_wdt.c + * @brief This file provides firmware functions to manage the General Watch Dog + * Timer(WDT). + @verbatim + Change Logs: + Date Author Notes + 2023-05-31 CDT First version + 2023-09-30 CDT Optimize WDT_ClearStatus function timeout + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_wdt.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup LL_Driver + * @{ + */ + +/** + * @defgroup LL_WDT WDT + * @brief General Watch Dog Timer + * @{ + */ + +#if (LL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Local_Macros WDT Local Macros + * @{ + */ + +/* WDT Refresh Key */ +#define WDT_REFRESH_KEY_START (0x0123UL) +#define WDT_REFRESH_KEY_END (0x3210UL) + +/* WDT clear flag timeout(ms) */ +#define WDT_CLR_FLAG_TIMEOUT (200UL) + +/* WDT Registers Clear Mask */ +#define WDT_CR_CLR_MASK (WDT_CR_PERI | WDT_CR_CKS | WDT_CR_WDPT | \ + WDT_CR_SLPOFF | WDT_CR_ITS) + +/** + * @defgroup WDT_Check_Parameters_Validity WDT Check Parameters Validity + * @{ + */ +#define IS_WDT_CNT_PERIOD(x) \ +( ((x) == WDT_CNT_PERIOD256) || \ + ((x) == WDT_CNT_PERIOD4096) || \ + ((x) == WDT_CNT_PERIOD16384) || \ + ((x) == WDT_CNT_PERIOD65536)) + +#define IS_WDT_CLK_DIV(x) \ +( ((x) == WDT_CLK_DIV4) || \ + ((x) == WDT_CLK_DIV64) || \ + ((x) == WDT_CLK_DIV128) || \ + ((x) == WDT_CLK_DIV256) || \ + ((x) == WDT_CLK_DIV512) || \ + ((x) == WDT_CLK_DIV1024) || \ + ((x) == WDT_CLK_DIV2048) || \ + ((x) == WDT_CLK_DIV8192)) + +#define IS_WDT_REFRESH_RANGE(x) \ +( ((x) == WDT_RANGE_0TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT) || \ + ((x) == WDT_RANGE_25TO50PCT) || \ + ((x) == WDT_RANGE_0TO50PCT) || \ + ((x) == WDT_RANGE_50TO75PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == WDT_RANGE_25TO75PCT) || \ + ((x) == WDT_RANGE_0TO75PCT) || \ + ((x) == WDT_RANGE_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_50TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == WDT_RANGE_25TO100PCT)) + +#define IS_WDT_LPM_CNT(x) \ +( ((x) == WDT_LPM_CNT_CONT) || \ + ((x) == WDT_LPM_CNT_STOP)) + +#define IS_WDT_EXP_TYPE(x) \ +( ((x) == WDT_EXP_TYPE_INT) || \ + ((x) == WDT_EXP_TYPE_RST)) + +#define IS_WDT_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | WDT_FLAG_ALL) == WDT_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Functions WDT Global Functions + * @{ + */ + +/** + * @brief Initializes WDT. + * @param [in] pstcWdtInit Pointer to a @ref stc_wdt_init_t structure + * @retval int32_t: + * - LL_OK: Initializes success + * - LL_ERR_INVD_PARAM: pstcWdtInit == NULL + */ +int32_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + int32_t i32Ret = LL_OK; + + if (NULL == pstcWdtInit) { + i32Ret = LL_ERR_INVD_PARAM; + } else { + /* Check parameters */ + DDL_ASSERT(IS_WDT_CNT_PERIOD(pstcWdtInit->u32CountPeriod)); + DDL_ASSERT(IS_WDT_CLK_DIV(pstcWdtInit->u32ClockDiv)); + DDL_ASSERT(IS_WDT_REFRESH_RANGE(pstcWdtInit->u32RefreshRange)); + DDL_ASSERT(IS_WDT_LPM_CNT(pstcWdtInit->u32LPMCount)); + DDL_ASSERT(IS_WDT_EXP_TYPE(pstcWdtInit->u32ExceptionType)); + + /* WDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(CM_WDT->CR, WDT_CR_CLR_MASK, + (pstcWdtInit->u32CountPeriod | pstcWdtInit->u32ClockDiv | + pstcWdtInit->u32RefreshRange | pstcWdtInit->u32LPMCount | + pstcWdtInit->u32ExceptionType)); + } + + return i32Ret; +} + +/** + * @brief WDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void WDT_FeedDog(void) +{ + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_START); + WRITE_REG32(CM_WDT->RR, WDT_REFRESH_KEY_END); +} + +/** + * @brief Get WDT flag status. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval An @ref en_flag_status_t enumeration type value. + */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = RESET; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(CM_WDT->SR, u32Flag))) { + enFlagSta = SET; + } + + return enFlagSta; +} + +/** + * @brief Clear WDT flag. + * @param [in] u32Flag WDT flag type + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count underflow flag + * @arg WDT_FLAG_REFRESH: Refresh error flag + * @arg WDT_FLAG_ALL: All of the above + * @retval int32_t: + * - LL_OK: Clear flag success + * - LL_ERR_TIMEOUT: Clear flag timeout + */ +int32_t WDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + int32_t i32Ret = LL_OK; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + /* Waiting for FLAG bit clear */ + u32Count = WDT_CLR_FLAG_TIMEOUT * (HCLK_VALUE / 25000UL); + while (0UL != READ_REG32_BIT(CM_WDT->SR, u32Flag)) { + CLR_REG32_BIT(CM_WDT->SR, u32Flag); + if (0UL == u32Count) { + i32Ret = LL_ERR_TIMEOUT; + break; + } + u32Count--; + } + + return i32Ret; +} + +/** + * @} + */ + +#endif /* LL_WDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h new file mode 100644 index 0000000000..7758a3d83e --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_common.h @@ -0,0 +1,145 @@ +/** + ******************************************************************************* + * @file stl_common.h + * @brief This file contains STL common definitions: enumeration, macros and + * structures definitions. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_COMMON_H__ +#define __STL_COMMON_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ll_def.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Common + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_Common_Global_Macros STL Common Global Macros + * @{ + */ + +/** + * @defgroup STL_Generic_Error_Codes STL Generic Error Codes + * @{ + */ +#define STL_OK (0UL) /*!< No error occurs */ +#define STL_ERR (1UL) /*!< Error occurs */ +/** + * @} + */ + +/** + * @defgroup STL_Module_Switch STL Module Switch + * @{ + */ +#define STL_ON (1U) +#define STL_OFF (0U) +/** + * @} + */ + +/** + * @defgroup Compiler_Macros Compiler Macros + * @{ + */ +#ifdef __CC_ARM /*!< ARM Compiler */ +/* CPU will start executing at the program entry label __main when the CPU is reset */ +extern void __main(void); + +/* CC */ +#define STL_SECTION(x) __attribute__((section(x))) +#define STL_UNUSED __attribute__((unused)) +#define STL_USED __attribute__((used)) +#define STL_ALIGN(n) __attribute__((aligned(n))) +#define STL_WEAK __WEAKDEF +#define STL_INLINE static __inline + +#define CallApplicationStartUp( ) __main() + +#elif defined (__ICCARM__) /*!< IAR Compiler */ +/* CPU will start executing at the program entry label __iar_program_start when the CPU is reset */ +extern void __iar_program_start(void); + +/* CC */ +#define STL_SECTION(x) @ x +#define STL_UNUSED +#define STL_USED __root +#define STL_PRAGMA(x) _Pragma(#x) +#define STL_ALIGN(n) STL_PRAGMA(data_alignment=n) +#define STL_WEAK __WEAKDEF +#define STL_INLINE static inline + +#define CallApplicationStartUp( ) __iar_program_start() +#else +#error Unsupported tool chain +#endif +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h new file mode 100644 index 0000000000..0f5b7d0113 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_conf.h @@ -0,0 +1,106 @@ +/** + ******************************************************************************* + * @file stl_conf.h + * @brief This file contains STL resource configure. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Optimize macros definitions + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_CONF_H__ +#define __STL_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_bsp_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Configure + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup IEC60730_STL_Configure_ROM_CRC32_Parameters IEC60730 STL Configure ROM CRC32 Parameters + * @{ + */ +#define STL_ROM_CRC32_START (STL_ROM_START) +#define STL_ROM_CRC32_END ((uint32_t)(&__checksum)) +#define STL_ROM_CRC32_BLOCK_SIZE (128UL) +#define STL_ROM_CRC32_CC_CHECKSUM (__checksum) +/** + * @} + */ + +/** + * @defgroup IEC60730_STL_Configure_RAM_Parameters IEC60730 STL Configure RAM Parameters + * @{ + */ +#define STL_MARCH_RAM_SIZE (32UL) +#define STL_MARCH_RAM_WORDS (STL_MARCH_RAM_SIZE >> 2) +#define STL_MARCH_RAM_BUF_SIZE (16UL) +#define STL_MARCH_RAM_BUF_WORDS (STL_MARCH_RAM_BUF_SIZE >> 2) + +#define STL_MARCH_RAM_BCKGRND (0x00000000UL) +#define STL_MARCH_RAM_INVBCKGRND (0xFFFFFFFFUL) + +#define STL_STACK_BOUNDARY_WORDS (4UL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h new file mode 100644 index 0000000000..f90268c03c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_sw_crc32.h @@ -0,0 +1,93 @@ +/** + ******************************************************************************* + * @file stl_test_flash.h + * @brief This file contains all the functions prototypes of the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_SW_CRC32_H__ +#define __STL_SW_CRC32_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_CRC32 + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Global_Macros STL IEC60730 CRC32 Global Macros + * @{ + */ +#define STL_CRC32_INIT_VALUE (0xFFFFFFFFUL) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_CRC32_Global_Functions + * @{ + */ +uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_SW_CRC32_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h new file mode 100644 index 0000000000..a5e0df3d48 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_cpu.h @@ -0,0 +1,85 @@ +/** + ******************************************************************************* + * @file stl_test_cpu.h + * @brief This file contains all the functions prototypes of the CPU test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_CPU_H__ +#define __STL_TEST_CPU_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_CPU + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_CPU_Global_Functions + * @{ + */ +uint32_t STL_CpuTestStartup(void); +uint32_t STL_CpuTestRuntime(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_CPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h new file mode 100644 index 0000000000..932b8c3a46 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_flash.h @@ -0,0 +1,85 @@ +/** + ******************************************************************************* + * @file stl_test_flash.h + * @brief This file contains all the functions prototypes of the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_FLASH_H__ +#define __STL_TEST_FLASH_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Flash + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Flash_Global_Functions + * @{ + */ +uint32_t STL_FlashStartupTest(void); +uint32_t STL_FlashRuntimeTest(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_FLASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h new file mode 100644 index 0000000000..fd0ed7c26b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_interrupt.h @@ -0,0 +1,99 @@ +/** + ******************************************************************************* + * @file stl_test_interrupt.h + * @brief This file contains all the functions prototypes of the interrupt test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_INTERRUPT_H__ +#define __STL_TEST_INTERRUPT_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Interrupt + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ +/** + * @defgroup STL_IEC60730_Interrupt_Global_Type STL IEC60730 Interrupt Global Type + * @{ + */ +typedef struct stc_stl_int_params { + uint32_t u32FreqInitVal; + uint32_t u32FreqLowerVal; + uint32_t u32FreqUpperVal; + uint32_t u32PrivateParam; +} stc_stl_int_params_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Interrupt_Global_Functions + * @{ + */ +uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize); +uint32_t STL_IntRuntimeTest(void); +void STL_IntUpdateCount(uint8_t u8ParamIndex); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_INTERRUPT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h new file mode 100644 index 0000000000..dce5b91b8e --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_pc.h @@ -0,0 +1,84 @@ +/** + ******************************************************************************* + * @file stl_test_pc.h + * @brief This file contains all the functions prototypes of the PC test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_PC_H__ +#define __STL_TEST_PC_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_PC + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_PC_Global_Functions + * @{ + */ +uint32_t STL_PcTest(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_PC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h new file mode 100644 index 0000000000..8e7983dc40 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/inc/stl_test_ram.h @@ -0,0 +1,88 @@ +/** + ******************************************************************************* + * @file stl_test_ram.h + * @brief This file contains all the functions prototypes of the RAM test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_RAM_H__ +#define __STL_TEST_RAM_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_RAM + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_RAM_Global_Functions + * @{ + */ +uint32_t STL_StackRuntimeInit(void); +uint32_t STL_StackRuntimeTest(void); +uint32_t STL_RamRuntimeInit(void); +uint32_t STL_RamRuntimeTest(void); +uint32_t STL_FullRamTestStartup(uint32_t u32StartAddr, uint32_t u32EndAddr); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_RAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s new file mode 100644 index 0000000000..94582f336c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm0_startup.s @@ -0,0 +1,372 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-09-14 */ +;/****************************************************************************/ + + SECTION constdata:CONST(2) +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 +data0x50000000 DCD 0x50000000 +data0xA0000000 DCD 0xA0000000 + + ; Exported function + EXPORT STL_CpuTestStartup + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_CpuTestStartup: + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; APSR + MRS R0, APSR + LDR R1, =data0x50000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0xA0000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR APSR,R0 + + ; PRIMASK register + MRS R0, PRIMASK + LDR R1, =data0x00000000 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000001 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R0 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s new file mode 100644 index 0000000000..5abb5a8216 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_cm4_startup.s @@ -0,0 +1,420 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Date Author Notes */ +;/* 2022-09-14 CDT First version */ +;/* 2022-12-20 CDT Load data to R0 before USAT */ +;/* 2023-05-31 CDT Typo: Veriry -> Verify */ +;/****************************************************************************/ + + SECTION constdata:CONST(2) +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 +data0x50000000 DCD 0x50000000 +data0xA8000000 DCD 0xA8000000 +data0x00000050 DCD 0x00000050 +data0x000000A0 DCD 0x000000A0 +data0xFFFFFFFF DCD 0xFFFFFFFF + + ; Exported function + EXPORT STL_CpuTestStartup + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_CpuTestStartup: + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + MOV R0, #0 + MSR APSR, R0 + LDR R0, =data0xFFFFFFFF ; Prepares Saturation test + LDR R0, [R0] + USAT R1, #10, R0 ; Set Q(saturation) flag + MRS R0, APSR ; Get APSR status register + CMP R0, #0x08000000 ; Verify Q=1 + BNE _test_cpu_reg0_reg13_fail ; Fails if Q is set + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; APSR + MRS R0, APSR + LDR R1, =data0x50000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0xA8000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR APSR,R0 + + ; PRIMASK register + MRS R0, PRIMASK + LDR R1, =data0x00000000 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000001 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R0 + + ; FAULTMASK register + MRS R0, FAULTMASK + LDR R1, =data0x00000000 + LDR R1, [R1] + MSR FAULTMASK, R1 + MRS R2, FAULTMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000001 + LDR R1, [R1] + MSR FAULTMASK, R1 + MRS R2, FAULTMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR FAULTMASK, R0 + + ; BASEPRI register + MRS R0, BASEPRI + LDR R1, =data0x000000A0 + LDR R1, [R1] + MSR BASEPRI, R1 + MRS R2, BASEPRI + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000050 + LDR R1, [R1] + MSR BASEPRI, R1 + MRS R2, BASEPRI + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR BASEPRI, R0 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s new file mode 100644 index 0000000000..d02dd7325a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_cpu_runtime.s @@ -0,0 +1,245 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + SECTION constdata:CONST(2) +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 + + ; Exported function + EXPORT STL_CpuTestRuntime + +;******************************************************************************* +; Function Name : STL_CpuTestRuntime +; Description : Test CPU at run-time +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_CpuTestRuntime: + PUSH {R4-R7} ; Save registers + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_fail + CMP R2, #0x02 + BNE _test_cpu_fail + CMP R3, #0x03 + BNE _test_cpu_fail + CMP R4, #0x04 + BNE _test_cpu_fail + CMP R5, #0x05 + BNE _test_cpu_fail + CMP R6, #0x06 + BNE _test_cpu_fail + CMP R7, #0x07 + BNE _test_cpu_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_fail + + ; Link register R14 + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK +_test_exit + POP {R4-R7} ; Restore registers + BX LR ; return + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s new file mode 100644 index 0000000000..71915b20d0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_full_ram_startup.s @@ -0,0 +1,186 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + SECTION constdata:CONST(2) +data0x00000000 DCD 0x00000000 +data0xFFFFFFFF DCD 0xFFFFFFFF + + ; Exported function + EXPORT STL_FullRamTestStartup + +;******************************************************************************* +; Function Name : STL_FullRamTestStartup +; Description : Full RAM test at start-up +; Input : R0 .. RAM begin address +; R1 .. RAM end address +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + THUMB + SECTION .text:CODE(2) +STL_FullRamTestStartup: + MOVS R4, #0x0 ; STL_OK:Test success status by default + + LDR R2, =data0x00000000 ; Prepares background pattern + LDR R2, [R2] + LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern + LDR R3, [R3] + + ; *** Step 1 *** + ; Write background pattern with addresses increasing + MOVS R5, R0 +_step1_loop: + CMP R5, R1 + BHI _step_2 + STR R2, [R5, #+0] + ADDS R5, R5, #+4 + B _step1_loop + + ; *** Step 2 *** + ; Verify background and write inverted background with addresses increasing +_step_2: + MOVS R5, R0 +_step_2_loop: + CMP R5, R1 + BHI _step_3 + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_2_loop + + ; *** Step 3 *** + ; Verify inverted background and write background with addresses increasing +_step_3: + MOVS R5, R0 +_step_3_loop: + CMP R5, R1 + BHI _step_4 + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_3_loop + + ; *** Step 4 *** + ; Verify background and write inverted background with addresses decreasing +_step_4: + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_4_loop: + CMP R5, R0 + BLO _step_5 + + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + + SUBS R5, R5, #+16 + B _step_4_loop + + ; *** Step 5 *** + ; Verify inverted background and write background with addresses decreasing +_step_5: + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_5_loop: + CMP R5, R0 + BLO _step_6 + + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + SUBS R5, R5, #+16 + B _step_5_loop + + ; *** Step 6 *** + ; Verify background with addresses increasing +_step_6: + MOVS R5, R0 +_step_6_loop: + CMP R5, R1 + BHI _full_ram1_test_pass + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + ADDS R5, R5, #+4 + B _step_6_loop + +_full_ram1_test_fail: + MOVS R4, #1 ; STL_ERR + +_full_ram1_test_pass: + MOVS R0, R4 + BX LR ; return to the caller + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s new file mode 100644 index 0000000000..4f180a1d9a --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/EWARM/stl_test_pc.s @@ -0,0 +1,148 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for IAR */ +;/* Date Author Notes */ +;/* 2022-03-31 CDT First version */ +;/* 2023-05-31 CDT Typo: subrouitne -> subroutine */ +;/****************************************************************************/ + + ; Exported function + EXPORT STL_PcTest + +;******************************************************************************* +; Function Name : STL_PcTest +; Description : Test PC +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + + SECTION .text:CODE(2) + THUMB +STL_PcTest + PUSH {R4-R7} ; Save registers + MOVS R0, #0 + MOVS R1, #0 ; clr R0,R1 + MOV R3, LR + +_subroutine_1 + LDR R0, =_return_pc_test_addr_1 + BL _return_pc_test_addr_1 + CMP R0, R1 ; verify return address? + BEQ _subroutine_2 + B _pc_test_fail + +_subroutine_2 + LDR R0, =_return_pc_test_addr_2 + BL _return_pc_test_addr_2 + CMP R0, R1 ; verify return address? + BEQ _subroutine_3 + B _pc_test_fail + +_subroutine_3 + LDR R0, =_return_pc_test_addr_3 + BL _return_pc_test_addr_3 + CMP R0, R1 ; verify return address? + BEQ _subroutine_4 + B _pc_test_fail + +_subroutine_4 + LDR R0, =_return_pc_test_addr_4 + BL _return_pc_test_addr_4 + CMP R0, R1 ; verify return address? + BEQ _subroutine_5 + B _pc_test_fail + +_subroutine_5 + LDR R0, =_return_pc_test_addr_5 + BL _return_pc_test_addr_5 + CMP R0, R1 ; verify return address? + BEQ _subroutine_6 + B _pc_test_fail + +_subroutine_6 + LDR R0, =_return_pc_test_addr_6 + BL _return_pc_test_addr_6 + CMP R0, R1 ; verify return address? + BEQ _subroutine_7 + B _pc_test_fail + +_subroutine_7 + LDR R0, =_return_pc_test_addr_7 + BL _return_pc_test_addr_7 + CMP R0, R1 ; verify return address? + BEQ _subroutine_8 + B _pc_test_fail + +_subroutine_8 + LDR R0, =_return_pc_test_addr_8 + BL _return_pc_test_addr_8 + CMP R0, R1 ; verify return address? + BEQ _pc_test_pass + B _pc_test_fail + +_pc_test_fail + ; when test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _pc_test_exit + +_pc_test_pass + ; when test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _pc_test_exit + +_pc_test_exit: + POP {R4-R7} ; Restore registers + BX R3 ; return + + SECTION .pctestaddr1:CODE(2) +_return_pc_test_addr_1 + LDR R1, =_return_pc_test_addr_1 ; store subroutine address in R1 + BX LR + + SECTION .pctestaddr2:CODE(2) +_return_pc_test_addr_2 + LDR R1, =_return_pc_test_addr_2 ; store subroutine address in R1 + BX LR + + SECTION .pctestaddr3:CODE(2) +_return_pc_test_addr_3 + LDR R1, =_return_pc_test_addr_3 ; store subroutine address in R1 + BX LR + + SECTION .pctestaddr4:CODE(2) +_return_pc_test_addr_4 + LDR R1, =_return_pc_test_addr_4 ; store subroutine address in R1 + BX LR + + SECTION .pctestaddr5:CODE(2) +_return_pc_test_addr_5 + LDR R1, =_return_pc_test_addr_5 ; store subroutine address in R1 + BX LR + + SECTION .pctestaddr6:CODE(2) +_return_pc_test_addr_6 + LDR R1, =_return_pc_test_addr_6 ; store subroutine address in R1 + BX LR + + SECTION .pctestaddr7:CODE(2) +_return_pc_test_addr_7 + LDR R1, =_return_pc_test_addr_7 ; store subroutine address in R1 + BX LR + + SECTION .pctestaddr8:CODE(2) +_return_pc_test_addr_8 + LDR R1, =_return_pc_test_addr_8 ; store subroutine address in R1 + BX LR + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s new file mode 100644 index 0000000000..13bdd9993b --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm0_startup.s @@ -0,0 +1,378 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-09-14 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 +data0x50000000 DCD 0x50000000 +data0xA0000000 DCD 0xA0000000 + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_CpuTestStartup PROC + EXPORT STL_CpuTestStartup + + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; APSR + MRS R0, APSR + LDR R1, =data0x50000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0xA0000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR APSR,R0 + + ; PRIMASK register + MRS R0, PRIMASK + LDR R1, =data0x00000000 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000001 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R0 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s new file mode 100644 index 0000000000..36bb5faf06 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_cm4_startup.s @@ -0,0 +1,426 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Date Author Notes */ +;/* 2022-09-14 CDT First version */ +;/* 2022-12-20 CDT Load data to R0 before USAT */ +;/* 2023-05-31 CDT Typo: Veriry -> Verify */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 +data0x80000000 DCD 0x80000000 +data0xAAAAAAA8 DCD 0xAAAAAAA8 +data0x55555554 DCD 0x55555554 +data0x00000000 DCD 0x00000000 +data0x00000001 DCD 0x00000001 +data0x50000000 DCD 0x50000000 +data0xA8000000 DCD 0xA8000000 +data0x00000050 DCD 0x00000050 +data0x000000A0 DCD 0x000000A0 +data0xFFFFFFFF DCD 0xFFFFFFFF + +;******************************************************************************* +; Function Name : STL_CpuTestStartup +; Description : Test CPU at start-up +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_CpuTestStartup PROC + EXPORT STL_CpuTestStartup + + PUSH {R4-R7} ; Save registers + +_test_cpu_reg0_reg8 + MOVS R0, #0x00 + UXTB R0, R0 + ADDS R0, #0 ; Set Z(ero) Flag + BNE _test_cpu_reg0_reg13_fail ; Fails if Z clear + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + SUBS R0, #1 ; Set N(egative) Flag + BPL _test_cpu_reg0_reg13_fail ; Fails if N clear + ADDS R0, #2 ; Set C(arry) Flag and do not set Z + BCC _test_cpu_reg0_reg13_fail ; Fails if C clear + BEQ _test_cpu_reg0_reg13_fail ; Fails if Z is set + BMI _test_cpu_reg0_reg13_fail ; Fails if N is set + + LDR R0, =data0x80000000 ; Prepares Overflow test + LDR R0, [R0] + ADDS R0, R0, R0 ; Set V(overflow) Flag + BVC _test_cpu_reg0_reg13_fail ; Fails if V clear + + MOV R0, #0 + MSR APSR, R0 + LDR R0, =data0xFFFFFFFF ; Prepares Saturation test + LDR R0, [R0] + USAT R1, #10, R0 ; Set Q(saturation) flag + MRS R0, APSR ; Get APSR status register + CMP R0, #0x08000000 ; Verify Q=1 + BNE _test_cpu_reg0_reg13_fail ; Fails if Q is set + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_reg0_reg13_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_reg0_reg13_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_reg0_reg13_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_reg0_reg13_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_reg0_reg13_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_reg0_reg13_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_reg0_reg13_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_reg0_reg13_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_reg0_reg13_fail + CMP R2, #0x02 + BNE _test_cpu_reg0_reg13_fail + CMP R3, #0x03 + BNE _test_cpu_reg0_reg13_fail + CMP R4, #0x04 + BNE _test_cpu_reg0_reg13_fail + CMP R5, #0x05 + BNE _test_cpu_reg0_reg13_fail + CMP R6, #0x06 + BNE _test_cpu_reg0_reg13_fail + CMP R7, #0x07 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_reg0_reg13_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_reg0_reg13_fail + + ; Process Stack pointer (banked Register R13) + MRS R0, PSP ; Save process stack value + LDR R1, =data0xAAAAAAA8 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 ; Test is different (PSP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR PSP, R1 ; load process stack value + MRS R2, PSP ; Get back process stack value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + MSR PSP, R0 ; Restore process stack value + + ; Stack pointer (Register R13) + MRS R0, MSP ; Save stack pointer value + LDR R1, =data0xAAAAAAA8 ; Test is different (SP is word aligned, 2 LSB cleared) + LDR R1, [R1] + MSR MSP, R1 ; load SP value + MRS R2, MSP ; Get back SP value + CMP R2, R1 ; Verify value + BNE _test_cpu_reg0_reg13_fail + LDR R1, =data0x55555554 + LDR R1, [R1] ; load SP value + MSR MSP, R1 ; Get back SP value + MRS R2, MSP ; Verify value + CMP R2, R1 + BNE _test_cpu_reg0_reg13_fail + MSR MSP, R0 ; Restore stack pointer value + +_test_cpu_r14_sfr + ; Link register R14 + MOV R1, LR + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R14, R0 + CMP R0, R14 + BNE _test_cpu_r14_sfr_fail + MOV LR, R1 + + ; APSR + MRS R0, APSR + LDR R1, =data0x50000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0xA8000000 + LDR R1,[R1] + MSR APSR,R1 + MRS R2, APSR + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR APSR,R0 + + ; PRIMASK register + MRS R0, PRIMASK + LDR R1, =data0x00000000 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000001 + LDR R1, [R1] + MSR PRIMASK, R1 + MRS R2, PRIMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR PRIMASK, R0 + + ; FAULTMASK register + MRS R0, FAULTMASK + LDR R1, =data0x00000000 + LDR R1, [R1] + MSR FAULTMASK, R1 + MRS R2, FAULTMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000001 + LDR R1, [R1] + MSR FAULTMASK, R1 + MRS R2, FAULTMASK + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR FAULTMASK, R0 + + ; BASEPRI register + MRS R0, BASEPRI + LDR R1, =data0x000000A0 + LDR R1, [R1] + MSR BASEPRI, R1 + MRS R2, BASEPRI + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + + LDR R1, =data0x00000050 + LDR R1, [R1] + MSR BASEPRI, R1 + MRS R2, BASEPRI + CMP R1, R2 + BNE _test_cpu_r14_sfr_fail + MSR BASEPRI, R0 + B _test_cpu_pass + +_test_cpu_r14_sfr_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_pass + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _test_exit + +_test_exit + POP {R4-R7} ; Restore registers + BX LR + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s new file mode 100644 index 0000000000..9b92ae536d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_cpu_runtime.s @@ -0,0 +1,251 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +data0xAAAAAAAA DCD 0xAAAAAAAA +data0x55555555 DCD 0x55555555 + +;******************************************************************************* +; Function Name : STL_CpuTestRuntime +; Description : Test CPU at run-time +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_CpuTestRuntime PROC + EXPORT STL_CpuTestRuntime + + PUSH {R4-R7} ; Save registers + + ; Register R1 + LDR R0, =data0xAAAAAAAA + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R1, [R0] + LDR R0, [R0] + CMP R0, R1 + BNE _test_cpu_fail + MOVS R1, #0x1 + + ; Register R2 + LDR R0, =data0xAAAAAAAA + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R2, [R0] + LDR R0, [R0] + CMP R0, R2 + BNE _test_cpu_fail + MOVS R2, #0x2 + + ; Register R3 + LDR R0, =data0xAAAAAAAA + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R3, [R0] + LDR R0, [R0] + CMP R0, R3 + BNE _test_cpu_fail + MOVS R3, #0x3 + + ; Register R4 + LDR R0, =data0xAAAAAAAA + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R4, [R0] + LDR R0, [R0] + CMP R0, R4 + BNE _test_cpu_fail + MOVS R4, #0x4 + + ; Register R5 + LDR R0, =data0xAAAAAAAA + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R5, [R0] + LDR R0, [R0] + CMP R0, R5 + BNE _test_cpu_fail + MOVS R5, #0x5 + + ; Register R6 + LDR R0, =data0xAAAAAAAA + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R6, [R0] + LDR R0, [R0] + CMP R0, R6 + BNE _test_cpu_fail + MOVS R6, #0x6 + + ; Register R7 + LDR R0, =data0xAAAAAAAA + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R7, [R0] + LDR R0, [R0] + CMP R0, R7 + BNE _test_cpu_fail + MOVS R7, #0x7 + + ; Register R8 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R8, R0 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x08 + MOV R8, R0 + + BAL _test_cpu_continue + +_test_cpu_fail + ; test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _test_exit + +_test_cpu_continue + ; Register R9 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R9, R0 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x09 + MOV R9, R0 + + ; Register R10 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R10, R0 + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0A + MOV R10, R0 + + ; Register R11 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R11, R0 + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0B + MOV R11, R0 + + ; Register R12 + LDR R0, =data0xAAAAAAAA + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + LDR R0, =data0x55555555 + LDR R0, [R0] + MOV R12, R0 + CMP R0, R12 + BNE _test_cpu_fail + MOVS R0, #0x0C + MOV R12, R0 + LDR R0, =_test_cpu_continue + + ; pattern verification (R0 is not tested) + CMP R1, #0x01 + BNE _test_cpu_fail + CMP R2, #0x02 + BNE _test_cpu_fail + CMP R3, #0x03 + BNE _test_cpu_fail + CMP R4, #0x04 + BNE _test_cpu_fail + CMP R5, #0x05 + BNE _test_cpu_fail + CMP R6, #0x06 + BNE _test_cpu_fail + CMP R7, #0x07 + BNE _test_cpu_fail + MOVS R0, #0x08 + CMP R0, R8 + BNE _test_cpu_fail + MOVS R0, #0x09 + CMP R0, R9 + BNE _test_cpu_fail + MOVS R0, #0x0A + CMP R0, R10 + BNE _test_cpu_fail + MOVS R0, #0x0B + CMP R0, R11 + BNE _test_cpu_fail + MOVS R0, #0x0C + CMP R0, R12 + BNE _test_cpu_fail + + ; Link register R14 + ; test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK +_test_exit + POP {R4-R7} ; Restore registers + BX LR ; return + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s new file mode 100644 index 0000000000..77d13f5e9c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_full_ram_startup.s @@ -0,0 +1,191 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Version V1.0 */ +;/* Date 2022-03-31 */ +;/****************************************************************************/ + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 +data0x00000000 DCD 0x00000000 +data0xFFFFFFFF DCD 0xFFFFFFFF + +;******************************************************************************* +; Function Name : STL_FullRamTestStartup +; Description : Full RAM test at start-up +; Input : R0 .. RAM begin address +; R1 .. RAM end address +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ +STL_FullRamTestStartup PROC + EXPORT STL_FullRamTestStartup + + MOVS R4, #0x0 ; STL_OK:Test success status by default + + LDR R2, =data0x00000000 ; Prepares background pattern + LDR R2, [R2] + LDR R3, =data0xFFFFFFFF ; Prepares inverted background pattern + LDR R3, [R3] + + ; *** Step 1 *** + ; Write background pattern with addresses increasing + MOVS R5, R0 +_step1_loop + CMP R5, R1 + BHI _step_2 + STR R2, [R5, #+0] + ADDS R5, R5, #+4 + B _step1_loop + + ; *** Step 2 *** + ; Verify background and write inverted background with addresses increasing +_step_2 + MOVS R5, R0 +_step_2_loop + CMP R5, R1 + BHI _step_3 + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_2_loop + + ; *** Step 3 *** + ; Verify inverted background and write background with addresses increasing +_step_3 + MOVS R5, R0 +_step_3_loop + CMP R5, R1 + BHI _step_4 + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + + ADDS R5, R5, #+16 + B _step_3_loop + + ; *** Step 4 *** + ; Verify background and write inverted background with addresses decreasing +_step_4 + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_4_loop + CMP R5, R0 + BLO _step_5 + + LDR R6, [R5, #+12] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + STR R3, [R5, #+0] + + SUBS R5, R5, #+16 + B _step_4_loop + + ; *** Step 5 *** + ; Verify inverted background and write background with addresses decreasing +_step_5 + MOVS R5, R1 + SUBS R5, R5, #+15 +_step_5_loop + CMP R5, R0 + BLO _step_6 + + LDR R6, [R5, #+12] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+12] + LDR R6, [R5, #+8] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+8] + + LDR R6, [R5, #+4] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+4] + LDR R6, [R5, #+0] + CMP R6, R3 + BNE _full_ram1_test_fail + STR R2, [R5, #+0] + SUBS R5, R5, #+16 + B _step_5_loop + + ; *** Step 6 *** + ; Verify background with addresses increasing +_step_6 + MOVS R5, R0 +_step_6_loop + CMP R5, R1 + BHI _full_ram1_test_pass + LDR R6, [R5, #+0] + CMP R6, R2 + BNE _full_ram1_test_fail + ADDS R5, R5, #+4 + B _step_6_loop + +_full_ram1_test_fail + MOVS R4, #1 ; STL_ERR + +_full_ram1_test_pass + MOVS R0, R4 + BX LR ; return to the caller + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s new file mode 100644 index 0000000000..f422011f2e --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/MDK/stl_test_pc.s @@ -0,0 +1,147 @@ +;/***************************************************************************** +; * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. +; * +; * This software component is licensed by XHSC under BSD 3-Clause license +; * (the "License"); You may not use this file except in compliance with the +; * License. You may obtain a copy of the License at: +; * opensource.org/licenses/BSD-3-Clause +; * +; */ +;/****************************************************************************/ +;/* Test for MDK */ +;/* Date Author Notes */ +;/* 2022-03-31 CDT First version */ +;/* 2023-05-31 CDT Typo: subrouitne -> subroutine */ +;/****************************************************************************/ + + THUMB + REQUIRE8 + PRESERVE8 + + AREA |.text|, CODE, READONLY, ALIGN=2 + +;******************************************************************************* +; Function Name : STL_PcTest +; Description : Test PC +; Input : None. +; Output : Perform routine when detect failure at set of self test cases +; Return : STL_OK (=0):test pass; STL_ERR (=1):test fail; +; WARNING : all registers destroyed when exiting this function (including +; preserved registers R4 to R11) and excluding stack point R13) +;*******************************************************************************/ + +STL_PcTest PROC + EXPORT STL_PcTest + + PUSH {R4-R7} ; Save registers + MOVS R0, #0 + MOVS R1, #0 ; clr R0,R1 + MOV R3, LR + +_subroutine_1 + LDR R0, =_return_pc_test_addr_1 + BL _return_pc_test_addr_1 + CMP R0, R1 ; verify return address? + BEQ _subroutine_2 + B _pc_test_fail + +_subroutine_2 + LDR R0, =_return_pc_test_addr_2 + BL _return_pc_test_addr_2 + CMP R0, R1 ; verify return address? + BEQ _subroutine_3 + B _pc_test_fail + +_subroutine_3 + LDR R0, =_return_pc_test_addr_3 + BL _return_pc_test_addr_3 + CMP R0, R1 ; verify return address? + BEQ _subroutine_4 + B _pc_test_fail + +_subroutine_4 + LDR R0, =_return_pc_test_addr_4 + BL _return_pc_test_addr_4 + CMP R0, R1 ; verify return address? + BEQ _subroutine_5 + B _pc_test_fail + +_subroutine_5 + LDR R0, =_return_pc_test_addr_5 + BL _return_pc_test_addr_5 + CMP R0, R1 ; verify return address? + BEQ _subroutine_6 + B _pc_test_fail + +_subroutine_6 + LDR R0, =_return_pc_test_addr_6 + BL _return_pc_test_addr_6 + CMP R0, R1 ; verify return address? + BEQ _subroutine_7 + B _pc_test_fail + +_subroutine_7 + LDR R0, =_return_pc_test_addr_7 + BL _return_pc_test_addr_7 + CMP R0, R1 ; verify return address? + BEQ _subroutine_8 + B _pc_test_fail + +_subroutine_8 + LDR R0, =_return_pc_test_addr_8 + BL _return_pc_test_addr_8 + CMP R0, R1 ; verify return address? + BEQ _pc_test_pass + B _pc_test_fail + +_pc_test_fail + ; when test fail, R0 will hold value 1 + MOVS R0, #0x1 ; STL_ERR + B _pc_test_exit + +_pc_test_pass + ; when test pass, R0 will hold value 0 + MOVS R0, #0x0 ; STL_OK + B _pc_test_exit + +_pc_test_exit + POP {R4-R7} ; Restore registers + BX R3 ; return + +_return_pc_test_addr_1 + LDR R1, =_return_pc_test_addr_1 ; store subroutine address in R1 + BX LR + +_return_pc_test_addr_2 + LDR R1, =_return_pc_test_addr_2 ; store subroutine address in R1 + BX LR + +_return_pc_test_addr_3 + LDR R1, =_return_pc_test_addr_3 ; store subroutine address in R1 + BX LR + +_return_pc_test_addr_4 + LDR R1, =_return_pc_test_addr_4 ; store subroutine address in R1 + BX LR + +_return_pc_test_addr_5 + LDR R1, =_return_pc_test_addr_5 ; store subroutine address in R1 + BX LR + +_return_pc_test_addr_6 + LDR R1, =_return_pc_test_addr_6 ; store subroutine address in R1 + BX LR + +_return_pc_test_addr_7 + LDR R1, =_return_pc_test_addr_7 ; store subroutine address in R1 + BX LR + +_return_pc_test_addr_8 + LDR R1, =_return_pc_test_addr_8 ; store subroutine address in R1 + BX LR + + ENDP + + ALIGN + + END diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c new file mode 100644 index 0000000000..b02345f93c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_sw_crc32.c @@ -0,0 +1,154 @@ +/** + ******************************************************************************* + * @file stl_sw_crc32.c + * @brief This file provides firmware functions to manage the software CRC32. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4 + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_sw_crc32.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_CRC32 STL IEC60730 CRC32 + * @brief IEC60730 software CRC32 + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Local_Variables STL IEC60730 CRC32 Local Variables + * @{ + */ +static const uint32_t m_au32Crc32Table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, + 0xE963A535, 0x9E6495A3, 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, 0x1DB71064, 0x6AB020F2, + 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, + 0xFA0F3D63, 0x8D080DF5, 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, 0x35B5A8FA, 0x42B2986C, + 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, + 0xCFBA9599, 0xB8BDA50F, 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, 0x76DC4190, 0x01DB7106, + 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, + 0x91646C97, 0xE6635C01, 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, 0x65B0D9C6, 0x12B7E950, + 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, + 0xA4D1C46D, 0xD3D6F4FB, 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, 0x5005713C, 0x270241AA, + 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, + 0xB7BD5C3B, 0xC0BA6CAD, 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, 0xE3630B12, 0x94643B84, + 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, + 0x196C3671, 0x6E6B06E7, 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, 0xD6D6A3E8, 0xA1D1937E, + 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, 0xDF60EFC3, 0xA867DF55, + 0x316E8EEF, 0x4669BE79, 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, 0xC5BA3BBE, 0xB2BD0B28, + 0x2BB45A92, 0x5CB36A04, 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, 0x9C0906A9, 0xEB0E363F, + 0x72076785, 0x05005713, 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, 0x86D3D2D4, 0xF1D4E242, + 0x68DDB3F8, 0x1FDA836E, 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, 0x8F659EFF, 0xF862AE69, + 0x616BFFD3, 0x166CCF45, 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, 0xAED16A4A, 0xD9D65ADC, + 0x40DF0B66, 0x37D83BF0, 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, 0xBAD03605, 0xCDD70693, + 0x54DE5729, 0x23D967BF, 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_CRC32_Global_Functions STL IEC60730 CRC32 Global Functions + * @{ + */ + +/** + * @brief Calculate CRC32 value. + * @param [in] u32Crc32Value CRC32 value + * @param [in] pu8Data Pointer to data buffer + * @param [in] u32Len Data length + * @retval CRC32 value + * @note Poly=0x04C11DB7, Init=0xFFFFFFFF, RefIn=true, RefOut=true, XorOut=0x00000000 + */ +uint32_t STL_CalculateCRC32Value(uint32_t u32Crc32Value, uint8_t *pu8Data, uint32_t u32Len) +{ + uint32_t i; + uint32_t u32CurrCrc32Value = u32Crc32Value; + + for (i = 0UL; i < u32Len; i++) { + u32CurrCrc32Value = (u32CurrCrc32Value >> 8) ^ m_au32Crc32Table[(u32CurrCrc32Value & 0xFFUL) ^ pu8Data[i]]; + } + + return u32CurrCrc32Value; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c new file mode 100644 index 0000000000..f465ccefbe --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_flash.c @@ -0,0 +1,179 @@ +/** + ******************************************************************************* + * @file stl_test_flash.c + * @brief This file provides firmware functions to manage the flash test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4 + 2023-01-15 CDT Fix bug: Reading CC Build CRC32 value is error in release project + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_utility.h" +#include "stl_sw_crc32.h" +#include "stl_test_flash.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Flash STL IEC60730 Flash + * @brief IEC60730 flash test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#if defined (__CC_ARM) /* keil Compiler */ +#define STL_CRC32_XOR_VALUE (0xFFFFFFFFUL) +#elif defined (__IAR_SYSTEMS_ICC__) /* IAR Compiler */ +#define STL_CRC32_XOR_VALUE (0x00000000UL) +#endif + +#define SW_CRC32_VALUE_XOR(x) ((x) ^ STL_CRC32_XOR_VALUE) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_Flash_Local_Variables STL IEC60730 Flash Local Variables + * @{ + */ +STL_USED const uint32_t __checksum STL_SECTION(".checksum") = 0UL; +/** + * @} + */ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Flash_Global_Functions STL IEC60730 Flash Global Functions + * @{ + */ + +/** + * @brief Flash test in startup. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Flash CRC value error. + */ +uint32_t STL_FlashStartupTest(void) +{ + uint32_t u32RomStart = STL_ROM_CRC32_START; + uint32_t u32RomEnd = STL_ROM_CRC32_END; + uint32_t u32RomSize = (u32RomEnd - u32RomStart); + uint8_t *pu8CrcData = (uint8_t *)u32RomStart; + uint32_t u32CalcCrc32Value; + volatile uint32_t u32CcBulidCrc32Addr; + volatile uint32_t u32CcBulidCrc32Value; + uint32_t u32Ret = STL_ERR; + + u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM); + u32CcBulidCrc32Value = *(uint32_t *)(u32CcBulidCrc32Addr); + u32CalcCrc32Value = STL_CalculateCRC32Value(STL_CRC32_INIT_VALUE, pu8CrcData, u32RomSize); + u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value); + if (u32CcBulidCrc32Value == u32CalcCrc32Value) { + u32Ret = STL_OK; + } + + return u32Ret; +} + +/** + * @brief Flash test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Flash CRC value error. + */ +uint32_t STL_FlashRuntimeTest(void) +{ + uint32_t u32Ret = STL_OK; + uint32_t u32RomStart = STL_ROM_CRC32_START; + uint32_t u32RomEnd = STL_ROM_CRC32_END; + uint32_t u32RomSize = (u32RomEnd - u32RomStart); + volatile uint32_t u32CcBulidCrc32Addr; + volatile uint32_t u32CcBulidCrc32Value; + const uint32_t u32CheckEndAddr = u32RomSize + 3UL - STL_ROM_CRC32_BLOCK_SIZE; + static uint32_t u32CalcLen; + static uint32_t u32CheckAddr = STL_ROM_CRC32_START; + static uint32_t u32CalcCrc32Value = STL_CRC32_INIT_VALUE; + + if (u32CheckAddr < STL_ROM_CRC32_END) { + if (u32CheckAddr == STL_ROM_CRC32_START) { + u32CalcCrc32Value = STL_CRC32_INIT_VALUE; /* Update CRC32 init value */ + } + + if (u32CheckAddr < u32CheckEndAddr) { + u32CalcLen = STL_ROM_CRC32_BLOCK_SIZE; + } else { + u32CalcLen = u32RomEnd - u32CheckAddr; + } + u32CalcCrc32Value = STL_CalculateCRC32Value(u32CalcCrc32Value, (uint8_t *)u32CheckAddr, u32CalcLen); + + u32CheckAddr += u32CalcLen; /* Update address */ + } else { + u32CcBulidCrc32Addr = (uint32_t)(&STL_ROM_CRC32_CC_CHECKSUM); + u32CcBulidCrc32Value = *(uint32_t *)(u32CcBulidCrc32Addr); + u32CheckAddr = STL_ROM_CRC32_START; /* Update address */ + u32CalcCrc32Value = SW_CRC32_VALUE_XOR(u32CalcCrc32Value); + if (u32CcBulidCrc32Value == u32CalcCrc32Value) { + STL_Printf("******** CRC32 verify ok in runtime ********\r\n"); + } else { + STL_Printf("******** CRC32 verify error in runtime ********\r\n"); + STL_Printf("* Calc_CRC32= 0x%x:CC Build_CRC32= 0x%x *\r\n", u32CalcCrc32Value, u32CcBulidCrc32Value); + u32Ret = STL_ERR; + } + } + + return u32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c new file mode 100644 index 0000000000..67dc0c5fc0 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_interrupt.c @@ -0,0 +1,165 @@ +/** + ******************************************************************************* + * @file stl_test_interrupt.c + * @brief This file provides firmware functions to manage the interrupt test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_test_interrupt.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Interrupt_Runtime STL IEC60730 Interrupt Runtime + * @brief IEC60730 interrupt runtime test + * @{ + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables + * @{ + */ +static uint32_t m_u32TestParamTableSize; +static stc_stl_int_params_t *m_pstcTestParamTable; +/** + * @} + */ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Interrupt_Global_Functions STL IEC60730 Interrupt Global Functions + * @{ + */ + +/** + * @brief Interrupt test table initialize in runtime. + * @param [in] pstcParamsTable Test case table + * @param [in] u32TableSize Test case size + * @retval uint32_t: + * - STL_OK: Initialize successfully. + * - STL_ERR: Initialize unsuccessfully. + */ +uint32_t STL_IntRuntimeTableInit(stc_stl_int_params_t *pstcParamsTable, uint32_t u32TableSize) +{ + uint32_t i; + uint32_t u32Ret = STL_ERR; + + if ((pstcParamsTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + pstcParamsTable[i].u32PrivateParam = 0UL; + } + + m_pstcTestParamTable = pstcParamsTable; + m_u32TestParamTableSize = u32TableSize; + u32Ret = STL_OK; + } + + return u32Ret; +} + +/** + * @brief Interrupt test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test error. + */ +uint32_t STL_IntRuntimeTest(void) +{ + uint32_t i; + uint32_t u32Ret = STL_OK; + stc_stl_int_params_t *pstcTestParam; + static uint32_t u32SystickCount; + + if (++u32SystickCount == STL_SYSTICK_TICK_FREQ) { + for (i = 0UL; i < m_u32TestParamTableSize; i++) { + pstcTestParam = &m_pstcTestParamTable[i]; + + if ((pstcTestParam->u32PrivateParam < pstcTestParam->u32FreqLowerVal) || \ + (pstcTestParam->u32PrivateParam > pstcTestParam->u32FreqUpperVal)) { + u32Ret = STL_ERR; + } + pstcTestParam->u32PrivateParam = 0UL; + } + u32SystickCount = 0UL; + } + + return u32Ret; +} + +/** + * @brief Update interrupt count in runtime. + * @param [in] u8ParamIndex Params index + * @retval None + */ +void STL_IntUpdateCount(uint8_t u8ParamIndex) +{ + stc_stl_int_params_t *pstcTestParam; + + if (u8ParamIndex < m_u32TestParamTableSize) { + pstcTestParam = &m_pstcTestParamTable[u8ParamIndex]; + pstcTestParam->u32PrivateParam++; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c new file mode 100644 index 0000000000..4f010f9e71 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_item/src/stl_test_ram_runtime.c @@ -0,0 +1,269 @@ +/** + ******************************************************************************* + * @file stl_test_ram_runtime.c + * @brief This file provides firmware functions to manage the RAM test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2022-06-30 CDT Fix warning: MISRAC2012-Rule-18.4 + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_conf.h" +#include "stl_test_ram.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_RAM_Runtime STL IEC60730 RAM Runtime + * @brief IEC60730 RAM runtime test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup STL_IEC60730_RAM_Local_Variables STL IEC60730 RAM Local Variables + * @{ + */ +STL_USED uint32_t m_au32MarchRAM[STL_MARCH_RAM_WORDS] STL_SECTION(".march_ram"); +STL_USED uint32_t m_au32MarchRAMBuf[STL_MARCH_RAM_BUF_WORDS] STL_SECTION(".march_ram_buf"); +STL_USED uint32_t *m_pu32MarchRAM STL_SECTION(".march_ram_pointer"); +STL_USED uint32_t m_au32StackBoundary[STL_STACK_BOUNDARY_WORDS] STL_SECTION(".stack_boundary"); +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_RAM_Global_Functions STL IEC60730 RAM Global Functions + * @{ + */ + +/** + * @brief Stack test initialize in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Initialization pass. + */ +uint32_t STL_StackRuntimeInit(void) +{ + m_au32StackBoundary[0] = 0x5A5A5A5AUL; + m_au32StackBoundary[1] = 0xA5A5A5A5UL; + m_au32StackBoundary[2] = 0xAAAAAAAAUL; + m_au32StackBoundary[3] = 0x55555555UL; + return STL_OK; +} + +/** + * @brief Stack test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Stack boundary value error. + */ +uint32_t STL_StackRuntimeTest(void) +{ + if ((m_au32StackBoundary[0] != 0x5A5A5A5AUL) || \ + (m_au32StackBoundary[1] != 0xA5A5A5A5UL) || \ + (m_au32StackBoundary[2] != 0xAAAAAAAAUL) || \ + (m_au32StackBoundary[3] != 0x55555555UL)) { + return STL_ERR; + } + + return STL_OK; +} + +/** + * @brief RAM test initialize in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Initialization pass. + */ +uint32_t STL_RamRuntimeInit(void) +{ + m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START; + return STL_OK; +} + +/** + * @brief RAM test in runtime. + * @param None + * @retval uint32_t: + * - STL_OK: Test pass. + * - STL_ERR: Test fail. + */ +uint32_t STL_RamRuntimeTest(void) +{ + uint32_t i; /* Index for RAM physical addressing */ + uint32_t u32Ret = STL_OK; + + if (m_pu32MarchRAM >= (uint32_t *)STL_MARCH_RAM_END) { + /*------------- March C- to the RAM Buffer itself --------------- */ + m_pu32MarchRAM = &m_au32MarchRAMBuf[0]; + + /*---------------------------- STEP 1 --------------------------------- */ + /* Write background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 2 --------------------------------- */ + /* Verify background and write inverted background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 3 --------------------------------- */ + /* Verify inverted background and write background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 4 --------------------------------- */ + /* Verify background and write inverted background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) { + if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 5 --------------------------------- */ + /* Verify inverted background and write background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL ; --i) { + if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 6 --------------------------------- */ + /* Verify background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + } + + /* Prepare next Tranparent RAM test from the beginning of Class A area */ + m_pu32MarchRAM = (uint32_t *)STL_MARCH_RAM_START; + } else { + /*---------------------------- STEP 1 --------------------------------- */ + /* Save the content of the 6 words to be tested and start MarchC - + Write background with addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + m_au32MarchRAMBuf[i] = m_pu32MarchRAM[i]; + m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 2 --------------------------------- */ + /* Verify background and write inverted background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i] = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 3 --------------------------------- */ + /* Verify inverted background and write background addresses increasing */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (m_pu32MarchRAM[i] != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i] = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 4 --------------------------------- */ + /* Verify background and write inverted background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) { + if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_INVBCKGRND; + } + + /*---------------------------- STEP 5 --------------------------------- */ + /* Verify inverted background and write background addresses decreasing */ + for (i = STL_MARCH_RAM_BUF_WORDS; i > 0UL; --i) { + if (m_pu32MarchRAM[i - 1UL] != STL_MARCH_RAM_INVBCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i - 1UL] = STL_MARCH_RAM_BCKGRND; + } + + /*---------------------------- STEP 6 --------------------------------- */ + /* Verify background with addresses increasing */ + /* and restore the content of the 6 tested words */ + for (i = 0UL; i < STL_MARCH_RAM_BUF_WORDS; ++i) { + if (m_pu32MarchRAM[i] != STL_MARCH_RAM_BCKGRND) { + u32Ret = STL_ERR; + } + m_pu32MarchRAM[i] = m_au32MarchRAMBuf[i]; + } + + /* Prepare next Row Tranparent RAM test */ + m_pu32MarchRAM = &m_pu32MarchRAM[STL_MARCH_RAM_BUF_WORDS]; + } + + return u32Ret; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c new file mode 100644 index 0000000000..2a27a38d19 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.c @@ -0,0 +1,145 @@ +/** + ******************************************************************************* + * @file stl_test_runtime.c + * @brief This file provides firmware functions to manage the runtime self-test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_test_runtime.h" +#include "stl_conf.h" +#include "stl_utility.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Runtime STL IEC60730 Runtime + * @brief IEC60730 runtime test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Macros STL IEC60730 Runtime Global Macros + * @{ + */ + +/** + * @brief Self-test initialization in runtime. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; +#if (STL_PRINT_ENABLE == STL_ON) + static en_flag_status_t enPrintInitActived = RESET; +#endif + +#if (STL_PRINT_ENABLE == STL_ON) + /* startup debug print */ + if (enPrintInitActived == RESET) { + (void)STL_PrintfInit(); + enPrintInitActived = SET; + } +#endif + + STL_Printf("******** Self-test runtime initialize ********\r\n"); + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnInit != NULL) { + if (pstcCaseTable[i].pfnInit() != STL_OK) { + STL_Printf("******** Init fail in runtime: %-20s ********\r\n", pstcCaseTable[i].pcCaseName); + } + } + } + } +} + +/** + * @brief Self-test on runtime. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnTest != NULL) { + if (pstcCaseTable[i].pfnTest() != STL_OK) { + STL_Printf("******** Test fail in runtime: %-20s ********\r\n", pstcCaseTable[i].pcCaseName); + + if (pstcCaseTable[i].pfnFailHandler != NULL) { + pstcCaseTable[i].pfnFailHandler(); + } + } + } + + if (pstcCaseTable[i].pfnFeedDog != NULL) { + pstcCaseTable[i].pfnFeedDog(); + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h new file mode 100644 index 0000000000..29877056e2 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_runtime.h @@ -0,0 +1,114 @@ +/** + ******************************************************************************* + * @file stl_test_runtime.h + * @brief This file contains all the functions prototypes of runtime test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_RUNTIME_H__ +#define __STL_TEST_RUNTIME_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Runtime + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type + * @{ + */ +typedef struct stc_stl_case_runtime { + const char *pcCaseName; + uint32_t (*pfnInit)(void); + uint32_t (*pfnTest)(void); + + void (*pfnFeedDog)(void); + void (*pfnFailHandler)(void); +} stc_stl_case_runtime_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Case STL IEC60730 Runtime Case + * @{ + */ +#define STL_RUNTIME_CASE(CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler) \ + { #CaseName, pfnInit, pfnTest, pfnFeedDog, pfnFailHandler } +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Runtime_Global_Functions + * @{ + */ + +void STL_RuntimeTestInit(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize); +void STL_RuntimeTestCase(const stc_stl_case_runtime_t *pstcCaseTable, uint32_t u32TableSize); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* #include "stl_common.h" */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c new file mode 100644 index 0000000000..fc1e486e0d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.c @@ -0,0 +1,120 @@ +/** + ******************************************************************************* + * @file stl_test_startup.c + * @brief This file provides firmware functions to manage the startup test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" +#include "stl_utility.h" +#include "stl_test_startup.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @defgroup STL_IEC60730_Startup STL IEC60730 Startup + * @brief IEC60730 startup test + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Startup_Global_Macros STL IEC60730 Startup Global Macros + * @{ + */ + +/** + * @brief Power on self-test. + * @param None + * @retval None + */ +STL_WEAK void STL_StartupTest(void) +{ + /* please implement this function. */ + for (;;) { + } +} + +/** + * @brief Power on self-test. + * @param [in] pstcCaseTable Test case table + * @param [in] u32TableSize Test case size + * @retval None + */ +void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize) +{ + uint32_t i; + + if ((pstcCaseTable != NULL) && (u32TableSize != 0UL)) { + for (i = 0UL; i < u32TableSize; i++) { + if (pstcCaseTable[i].pfnTest != NULL) { + if (pstcCaseTable[i].pfnTest() != STL_OK) { + STL_Printf("******** Test fail in startup: %-20s ********\r\n", pstcCaseTable[i].pcCaseName); + + if (pstcCaseTable[i].pfnFailHandler != NULL) { + pstcCaseTable[i].pfnFailHandler(); + } + } + } + } + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h new file mode 100644 index 0000000000..c7e4628a7c --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_test_startup.h @@ -0,0 +1,111 @@ +/** + ******************************************************************************* + * @file stl_test_startup.h + * @brief This file contains all the functions prototypes of startup test. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_TEST_STARTUP_H__ +#define __STL_TEST_STARTUP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" + +/** + * @addtogroup STL_IEC60730 + * @{ + */ + +/** + * @addtogroup STL_IEC60730_Startup + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Runtime_Global_Type STL IEC60730 Runtime Global Type + * @{ + */ +typedef struct stc_stl_case_startup { + const char *pcCaseName; + uint32_t (*pfnTest)(void); + + void (*pfnFailHandler)(void); +} stc_stl_case_startup_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Startup_Case STL IEC60730 Startup Case + * @{ + */ +#define STL_STARTUP_CASE(CaseName, pfnTest, pfnFailHandler) \ + { #CaseName, pfnTest, pfnFailHandler } +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup STL_IEC60730_Startup_Global_Functions + * @{ + */ +void STL_StartupTest(void); +void STL_StartupTestCase(const stc_stl_case_startup_t *pstcCaseTable, uint32_t u32TableSize); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_TEST_STARTUP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c new file mode 100644 index 0000000000..8cef35f95d --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.c @@ -0,0 +1,236 @@ +/** + ******************************************************************************* + * @file stl_utility.c + * @brief This file provides utility functions for STL. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + 2023-01-15 CDT Modify USART_SR_TXE to USART_SR_TC in STL_ConsoleOutputChar() + 2023-05-31 CDT Modify register USART DR to USART TDR + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_utility.h" +#include "hc32_ll_fcg.h" +#include "hc32_ll_gpio.h" +#include "hc32_ll_usart.h" +#include "hc32_ll_utility.h" + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @defgroup IEC60730_STL_Utility IEC60730 STL Utility + * @{ + */ + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup STL_IEC60730_Utility_Global_Functions STL IEC60730 Utility Global Functions + * @{ + */ + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Count us + * @retval None + */ +void STL_DelayUS(uint32_t u32Count) +{ + DDL_DelayUS(u32Count); +} + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Count ms + * @retval None + */ +void STL_DelayMS(uint32_t u32Count) +{ + DDL_DelayMS(u32Count); +} + +/** + * @brief STL test safety failure handle + * @param None + * @retval None + */ +void STL_SafetyFailure(void) +{ +#if (STL_RESET_AT_FAILURE == STL_ON) + NVIC_SystemReset(); /* Generate system reset */ +#endif +} + +#if (STL_PRINT_ENABLE == STL_ON) + +/** + * @brief Transmit character. + * @param [in] cData The character for transmitting + * @retval uint32_t: + * - STL_OK: Transmit successfully. + * - STL_ERR: Transmit timeout. + */ +__WEAKDEF uint32_t STL_ConsoleOutputChar(char cData) +{ + uint32_t u32Ret = STL_ERR; + uint32_t u32TxEmpty = 0UL; + __IO uint32_t u32TmpCount = 0UL; + uint32_t u32Timeout = 10000UL; + + /* Wait TX data register empty */ + while ((u32TmpCount <= u32Timeout) && (0UL == u32TxEmpty)) { + u32TxEmpty = READ_REG32_BIT(STL_PRINTF_DEVICE->SR, USART_SR_TC); + u32TmpCount++; + } + + if (0UL != u32TxEmpty) { + WRITE_REG16(STL_PRINTF_DEVICE->TDR, (uint16_t)cData); + u32Ret = STL_OK; + } + + return u32Ret; +} + +#if (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || \ + (defined (__ICCARM__)) || (defined (__CC_ARM)) +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (STL_OK == STL_ConsoleOutputChar((char)ch)) ? ch : -1; +} + +#elif defined (__GNUC__) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) { + if (STL_OK != STL_ConsoleOutputChar(data[i])) { + break; + } + } + } + + return i ? i : -1; +} +#endif + +/** + * @brief Initialize printf function + * @param None + * @retval None + */ +uint32_t STL_PrintfInit(void) +{ + uint32_t u32Div; + float32_t f32Error; + uint32_t u32Ret = STL_ERR; + stc_usart_uart_init_t stcUartInit; + + /* Set TX port function */ + GPIO_SetFunc(STL_PRINTF_PORT, STL_PRINTF_PIN, STL_PRINTF_PORT_FUNC); + + /* Enable clock */ + STL_PRINTF_DEVICE_FCG_ENALBE(); + + /*************************************************************************** + * Configure UART + *************************************************************************** + * Baud rate: STL_PRINTF_BAUDRATE + * Bit direction: LSB + * Data bits: 8 + * Stop bits: 1 + * Parity: None + * Sampling bits: 8 + **************************************************************************/ + /* Configure UART */ + (void)USART_UART_StructInit(&stcUartInit); + stcUartInit.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; + (void)USART_UART_Init(STL_PRINTF_DEVICE, &stcUartInit, NULL); + + for (u32Div = 0UL; u32Div <= USART_CLK_DIV64; u32Div++) { + USART_SetClockDiv(STL_PRINTF_DEVICE, u32Div); + if ((LL_OK == USART_SetBaudrate(STL_PRINTF_DEVICE, STL_PRINTF_BAUDRATE, &f32Error)) && \ + ((-STL_PRINTF_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= STL_PRINTF_BAUDRATE_ERR_MAX))) { + USART_FuncCmd(STL_PRINTF_DEVICE, USART_TX, ENABLE); + u32Ret = STL_OK; + break; + } + } + + return u32Ret; +} + +#endif /* STL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h new file mode 100644 index 0000000000..afd90a0039 --- /dev/null +++ b/bsp/hc32/libraries/hc32f448_ddl/midwares/hc32/iec60730_class_b_stl/stl_utility.h @@ -0,0 +1,107 @@ +/** + ******************************************************************************* + * @file stl_utility.h + * @brief This file contains all the functions prototypes of utility. + @verbatim + Change Logs: + Date Author Notes + 2022-03-31 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +#ifndef __STL_UTILITY_H__ +#define __STL_UTILITY_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "stl_common.h" +#include "stl_conf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * @addtogroup IEC60730_STL + * @{ + */ + +/** + * @addtogroup IEC60730_STL_Utility + * @{ + */ + +/******************************************************************************* + * Global type definitions ('typedef') +*******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @addtogroup STL_UTILITY_Global_Functions + * @{ + */ + +#if (STL_PRINT_ENABLE == STL_ON) +#include +uint32_t STL_ConsoleOutputChar(char cData); +#define STL_Printf (void)printf +#else +#define STL_Printf(...) +#endif + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addgroup STL_Utility_Global_Functions + * @{ + */ +void STL_DelayUS(uint32_t u32Count); +void STL_DelayMS(uint32_t u32Count); + +void STL_SafetyFailure(void); + +uint32_t STL_PrintfInit(void); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STL_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/

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