[bsp][lpc55sxx] update NXP SDK to 2_12_0

update NXP SDK to 2_12_0
2026-11-09 20:45:41 +08:00 · 2022-11-27 21:01:12 -05:00
1 parent 83d3b3ed62
commit 6c5f9ffb0a
@@ -1,8 +1,8 @@
 /**************************************************************************//**
 * @file     cmsis_compiler.h
 * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
+ * @version  V5.1.0
+ * @date     09. October 2018
 ******************************************************************************/
 /*
 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,9 +35,15 @@


 /*
- * Arm Compiler 6 (armclang)
+ * Arm Compiler 6.6 LTM (armclang)
 */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
  #include "cmsis_armclang.h"


@@ -115,8 +121,11 @@
    #define __ALIGNED(x)                           __attribute__((aligned(x)))
  #endif
  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
  #endif


@@ -187,6 +196,10 @@
    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
    #define __RESTRICT
  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif


 /*
@@ -255,6 +268,10 @@
    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
    #define __RESTRICT
  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif


 #else
@@ -1,11 +1,11 @@
 /**************************************************************************//**
 * @file     cmsis_version.h
 * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.2
- * @date     19. April 2017
+ * @version  V5.0.4
+ * @date     23. July 2019
 ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -33,7 +33,7 @@

 /*  CMSIS Version definitions */
 #define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION_SUB   ( 4U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
 #define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
 #endif
@@ -1,11 +1,11 @@
 /******************************************************************************
 * @file     mpu_armv8.h
- * @brief    CMSIS MPU API for Armv8-M MPU
- * @version  V5.0.4
- * @date     10. January 2018
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.3
+ * @date     03. February 2021
 ******************************************************************************/
 /*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ * Copyright (c) 2017-2021 Arm Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
@@ -44,7 +44,7 @@
 * \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
 */
 #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
-  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+  ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))

 /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
 #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
@@ -62,7 +62,7 @@
 * \param O Outer memory attributes
 * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
 */
-#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))

 /** \brief Normal memory non-shareable  */
 #define ARM_MPU_SH_NON   (0U)
@@ -77,7 +77,7 @@
 * \param RO Read-Only: Set to 1 for read-only memory.
 * \param NP Non-Privileged: Set to 1 for non-privileged memory.
 */
-#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))

 /** \brief Region Base Address Register value
 * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
@@ -87,20 +87,35 @@
 * \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
 */
 #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
-  ((BASE & MPU_RBAR_BASE_Pos) | \
-  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  (((BASE) & MPU_RBAR_BASE_Msk) | \
+  (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
-  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+  (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))

 /** \brief Region Limit Address Register value
 * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
 * \param IDX The attribute index to be associated with this memory region.
 */
 #define ARM_MPU_RLAR(LIMIT, IDX) \
-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
  (MPU_RLAR_EN_Msk))

+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
+  (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
 /**
 * Struct for a single MPU Region
 */
@@ -114,24 +129,26 @@ typedef struct {
 */
 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
 {
-  __DSB();
-  __ISB();
+  __DMB();
  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
+  __DSB();
+  __ISB();
 }

 /** Disable the MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
 }

 #ifdef MPU_NS
@@ -140,24 +157,26 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
 */
 __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
 {
-  __DSB();
-  __ISB();
+  __DMB();
  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
+  __DSB();
+  __ISB();
 }

 /** Disable the Non-secure MPU.
 */
 __STATIC_INLINE void ARM_MPU_Disable_NS(void)
 {
-  __DSB();
-  __ISB();
+  __DMB();
 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
 #endif
  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+  __DSB();
+  __ISB();
 }
 #endif

@@ -262,12 +281,12 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
 }
 #endif

-/** Memcopy with strictly ordered memory access, e.g. for register targets.
+/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
 * \param dst Destination data is copied to.
 * \param src Source data is copied from.
 * \param len Amount of data words to be copied.
 */
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
 {
  uint32_t i;
  for (i = 0U; i < len; ++i) 
@@ -287,7 +306,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  if (cnt == 1U) {
    mpu->RNR = rnr;
-    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
  } else {
    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
@@ -295,7 +314,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
    mpu->RNR = rnrBase;
    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
-      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
      table += c;
      cnt -= c;
      rnrOffset = 0U;
@@ -303,7 +322,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
      mpu->RNR = rnrBase;
    }
    
-    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
  }
 }

@@ -1,121 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_common_tables.h
- * Description:  Extern declaration for common tables
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoef_16_q31[24];
-extern const q31_t twiddleCoef_32_q31[48];
-extern const q31_t twiddleCoef_64_q31[96];
-extern const q31_t twiddleCoef_128_q31[192];
-extern const q31_t twiddleCoef_256_q31[384];
-extern const q31_t twiddleCoef_512_q31[768];
-extern const q31_t twiddleCoef_1024_q31[1536];
-extern const q31_t twiddleCoef_2048_q31[3072];
-extern const q31_t twiddleCoef_4096_q31[6144];
-extern const q15_t twiddleCoef_16_q15[24];
-extern const q15_t twiddleCoef_32_q15[48];
-extern const q15_t twiddleCoef_64_q15[96];
-extern const q15_t twiddleCoef_128_q15[192];
-extern const q15_t twiddleCoef_256_q15[384];
-extern const q15_t twiddleCoef_512_q15[768];
-extern const q15_t twiddleCoef_1024_q15[1536];
-extern const q15_t twiddleCoef_2048_q15[3072];
-extern const q15_t twiddleCoef_4096_q15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-/* floating-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
-#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
-#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
-#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
-
-/* fixed-point bit reversal tables */
-#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
-#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
-#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
-#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
-#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
-#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
-#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
-#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
-#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
-
-/* Tables for Fast Math Sine and Cosine */
-extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
-extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
-extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
-
-#endif /*  ARM_COMMON_TABLES_H */
@@ -1,66 +0,0 @@
-/* ----------------------------------------------------------------------
- * Project:      CMSIS DSP Library
- * Title:        arm_const_structs.h
- * Description:  Constant structs that are initialized for user convenience.
- *               For example, some can be given as arguments to the arm_cfft_f32() function.
- *
- * $Date:        27. January 2017
- * $Revision:    V.1.5.1
- *
- * Target Processor: Cortex-M cores
- * -------------------------------------------------------------------- */
-/*
- * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
-   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
-
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
-   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
-
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
-   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
-
-#endif
@@ -1,74 +0,0 @@
-/**************************************************************************//**
- * @file     cmsis_xcc.h
- * @brief    CMSIS DSP Core Peripheral Access Layer Header File
- * @version  V1.0
- * @date     20. January 2019
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CORE_DSP_H_GENERIC
-#define __CORE_DSP_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-#define __STATIC_INLINE static inline
-
-#define __BKPT(value) do {} while(0)
-#define __NOP() do {} while(0)
-
-#define NVIC_SetPriorityGrouping(value) do {} while(0)
-#define NVIC_GetPriorityGrouping() do {} while(0)
-#define NVIC_EnableIRQ(value) do {} while(0)
-#define NVIC_GetEnableIRQ(value) do {} while(0)
-#define NVIC_DisableIRQ(value) do {} while(0)
-#define NVIC_GetPendingIRQ(value) do {} while(0)
-#define NVIC_SetPendingIRQ(value) do {} while(0)
-#define NVIC_ClearPendingIRQ(value) do {} while(0)
-#define NVIC_GetActive(value) do {} while(0)
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_DSP_H_GENERIC */
@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b210928
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2021 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -47,7 +48,7 @@
 #define  m_text_size                   0x00071E00

 #define  m_core1_image_start           0x00072000
-#define  m_core1_image_size            0x00026000
+#define  m_core1_image_size            0x0002B800

 #if (defined(__use_shmem__))
  #define  m_data_start                0x20000000
@@ -66,12 +67,12 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region

  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
  }

  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
    * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
  }

 #if (defined(__use_shmem__))
@@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
 #endif

  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
  }
  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
  }
@@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
  }

  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
  }

  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
  }
 }

 LR_CORE1_IMAGE m_core1_image_start {
  CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
  }
 }
@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b180921
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -42,18 +43,18 @@

 /* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */
 #define  m_interrupts_start            0x00010000
-#define  m_interrupts_size             0x00000140
+#define  m_interrupts_size             0x00000200

-#define  m_text_start                  0x00010140
-#define  m_text_size                   0x00061EC0
+#define  m_text_start                  0x00010200
+#define  m_text_size                   0x00061E00

 #define  m_core1_image_start           0x00072000
-#define  m_core1_image_size            0x00026000
+#define  m_core1_image_size            0x0002B800

 /* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */
 #if (defined(__use_shmem__))
  #define  m_data_start                0x20008000
-  #define  m_data_size                 0x00028000
+  #define  m_data_size                 0x00029000
  #define  m_rpmsg_sh_mem_start        0x20031800
  #define  m_rpmsg_sh_mem_size         0x00001800
 #else
@@ -65,10 +66,15 @@
 #define  m_usb_sram_size               0x00004000


-LR_m_text m_text_start m_text_size {   ; load region size_region
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
    * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
  }

 #if (defined(__use_shmem__))
@@ -78,34 +84,24 @@ LR_m_text m_text_start m_text_size {   ; load region size_region
 #endif

  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
  }
  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
  }
  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
  }
-}

-LR_m_interrupts m_interrupts_start m_interrupts_size {
-  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
  }
-}

-LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
-  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
-  }
-}
-
-LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
-  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
  }
 }

 LR_CORE1_IMAGE m_core1_image_start {
  CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
  }
 }
@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b180921
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -42,13 +43,13 @@

 /* Only the first 64kB of flash is used as secure memory. */
 #define  m_interrupts_start            0x10000000
-#define  m_interrupts_size             0x00000140
+#define  m_interrupts_size             0x00000200

-#define  m_text_start                  0x10000140
-#define  m_text_size                   0x0000FCC0
+#define  m_text_start                  0x10000200
+#define  m_text_size                   0x0000FC00

 #define  m_core1_image_start           0x10072000
-#define  m_core1_image_size            0x00026000
+#define  m_core1_image_size            0x0002B800

 /* Only first 32kB of data RAM is used as secure memory. */
 #if (defined(__use_shmem__))
@@ -70,10 +71,15 @@
 #define  m_usb_sram_size               0x00004000


-LR_m_text m_text_start m_text_size {   ; load region size_region
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size {   ; load region size_region
+
+  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+    * (.isr_vector,+FIRST)
+  }
+
  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
    * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
  }

 #if (defined(__use_shmem__))
@@ -83,40 +89,28 @@ LR_m_text m_text_start m_text_size {   ; load region size_region
 #endif

  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
  }
  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
  }
  ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
  }
-}

-LR_m_interrupts m_interrupts_start m_interrupts_size {
-  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
-  }
-}
-
-LR_m_veneer_table m_veneer_table_start m_veneer_table_size {
-  ER_m_veneer_table m_veneer_table_start m_veneer_table_size {; veneer table
+  ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
    *(Veneer$$CMSE)
  }
-}

-LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
-  ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+    * (*m_usb_bdt)
  }
-}

-LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
-  ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+    * (*m_usb_global)
  }
 }

 LR_CORE1_IMAGE m_core1_image_start {
  CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
  }
 }
@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core0
-**                          LPC55S69JET98_cm33_core0
+**                          LPC55S69JBD64_cm33_core0
+**                          LPC55S69JEV98_cm33_core0
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2020 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -47,7 +48,7 @@
 #define  m_text_size                   0x00007E00

 #define  m_core1_image_start           0x20033000
-#define  m_core1_image_size            0x00008800
+#define  m_core1_image_size            0x0000C800

 #if (defined(__use_shmem__))
  #define  m_data_start                0x20000000
@@ -66,12 +67,12 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region

  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
  }

  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
    * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
  }

 #if (defined(__use_shmem__))
@@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
 #endif

  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
  }
  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
  }
@@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
  }

  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
  }

  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
  }
 }

 LR_CORE1_IMAGE m_core1_image_start {
  CORE1_REGION m_core1_image_start m_core1_image_size {
-    *(M0CODE)
+    * (.core1_code)
  }
 }
@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core1
-**                          LPC55S69JET98_cm33_core1
+**                          LPC55S69JBD64_cm33_core1
+**                          LPC55S69JEV98_cm33_core1
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b210928
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2021 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -44,7 +45,7 @@
 #define  m_interrupts_size             0x00000200

 #define  m_text_start                  0x00072200
-#define  m_text_size                   0x00025E00
+#define  m_text_size                   0x0002B600


 #define  m_data_start                  0x20033000
@@ -62,17 +63,17 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region

  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
  }

  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
    * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
  }


  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
  }
  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
  }
@@ -80,11 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
  }

  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
  }

  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
+  }
+  #if (defined(__use_shmem__))
+  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+    * (rpmsg_sh_mem_section)
+  }
+  #endif
  }
-}

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core1
-**                          LPC55S69JET98_cm33_core1
+**                          LPC55S69JBD64_cm33_core1
+**                          LPC55S69JEV98_cm33_core1
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b200722
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2020 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -44,11 +45,11 @@
 #define  m_interrupts_size             0x00000200

 #define  m_text_start                  0x20033200
-#define  m_text_size                   0x0000B600
+#define  m_text_size                   0x0000C600


-#define  m_data_start                  0x2003E800
-#define  m_data_size                   0x00005800
+#define  m_data_start                  0x2003F800
+#define  m_data_size                   0x00004800

 #if (defined(__use_shmem__))
  #define  m_rpmsg_sh_mem_start        0x20031800
@@ -62,17 +63,17 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region

  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
  }

  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
    * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
  }


  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
  }
  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
  }
@@ -80,16 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
  }

  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
  }

  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
  }
-#if (defined(__use_shmem__))   
+  #if (defined(__use_shmem__))
  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
    * (rpmsg_sh_mem_section)
  }
-#endif
-}
+  #endif
+  }

@@ -2,18 +2,19 @@
 /*
 ** ###################################################################
 **     Processors:          LPC55S69JBD100_cm33_core1
-**                          LPC55S69JET98_cm33_core1
+**                          LPC55S69JBD64_cm33_core1
+**                          LPC55S69JEV98_cm33_core1
 **
 **     Compiler:            Keil ARM C/C++ Compiler
-**     Reference manual:    LPC55xx/LPC55Sxx User manual Rev.0.2  15 Aug 2018
-**     Version:             rev. 1.0, 2018-08-22
-**     Build:               b181008
+**     Reference manual:    LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3  16 May 2019
+**     Version:             rev. 1.1, 2019-05-16
+**     Build:               b190923
 **
 **     Abstract:
 **         Linker file for the Keil ARM C/C++ Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2018 NXP
+**     Copyright 2016-2019 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -44,11 +45,11 @@
 #define  m_interrupts_size             0x00000200

 #define  m_text_start                  0x30033200
-#define  m_text_size                   0x0000B600
+#define  m_text_size                   0x0000C600


-#define  m_data_start                  0x3003E800
-#define  m_data_size                   0x00005800
+#define  m_data_start                  0x3003F800
+#define  m_data_size                   0x00004800

 #if (defined(__use_shmem__))
  #define  m_rpmsg_sh_mem_start        0x30031800
@@ -62,17 +63,17 @@
 LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region size_region

  VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
-    * (RESET,+FIRST)
+    * (.isr_vector,+FIRST)
  }

  ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
    * (InRoot$$Sections)
-    * (+RO)
+    .ANY (+RO)
  }


  RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
-    * (+RW +ZI)
+    .ANY (+RW +ZI)
  }
  ARM_LIB_HEAP +0 EMPTY Heap_Size {    ; Heap region growing up
  }
@@ -80,11 +81,11 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size {   ; load region siz
  }

  RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
-    * (m_usb_bdt)
+    * (*m_usb_bdt)
  }

  RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
-    * (m_usb_global)
+    * (*m_usb_global)
  }
 #if (defined(__use_shmem__))   
  RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
@@ -0,0 +1,17 @@
+include_guard()
+message("driver_cmsis_flexcomm_i2c component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_flexcomm_i2c_dma_LPC55S69_cm33_core0)
+
+include(CMSIS_Driver_Include_I2C_LPC55S69_cm33_core0)
+
@@ -0,0 +1,17 @@
+include_guard()
+message("driver_cmsis_flexcomm_spi component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_spi_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_flexcomm_spi_dma_LPC55S69_cm33_core0)
+
+include(CMSIS_Driver_Include_SPI_LPC55S69_cm33_core0)
+
@@ -0,0 +1,17 @@
+include_guard()
+message("driver_cmsis_flexcomm_usart component is included.")
+
+target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/fsl_usart_cmsis.c
+)
+
+
+target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
+    ${CMAKE_CURRENT_LIST_DIR}/.
+)
+
+
+include(driver_flexcomm_usart_dma_LPC55S69_cm33_core0)
+
+include(CMSIS_Driver_Include_USART_LPC55S69_cm33_core0)
+
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2020 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _FSL_I2C_CMSIS_H_
+#define _FSL_I2C_CMSIS_H_
+#include "fsl_common.h"
+#include "Driver_I2C.h"
+#include "RTE_Device.h"
+#include "fsl_i2c.h"
+#include "fsl_flexcomm.h"
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_i2c_dma.h"
+#endif
+
+#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0
+extern ARM_DRIVER_I2C Driver_I2C0;
+#endif
+
+#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1
+extern ARM_DRIVER_I2C Driver_I2C1;
+#endif
+
+#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2
+extern ARM_DRIVER_I2C Driver_I2C2;
+#endif
+
+#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3
+extern ARM_DRIVER_I2C Driver_I2C3;
+#endif
+
+#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4
+extern ARM_DRIVER_I2C Driver_I2C4;
+#endif
+
+#if defined(I2C5) && defined(RTE_I2C5) && RTE_I2C5
+extern ARM_DRIVER_I2C Driver_I2C5;
+#endif
+
+#if defined(I2C6) && defined(RTE_I2C6) && RTE_I2C6
+extern ARM_DRIVER_I2C Driver_I2C6;
+#endif
+
+#if defined(I2C7) && defined(RTE_I2C7) && RTE_I2C7
+extern ARM_DRIVER_I2C Driver_I2C7;
+#endif
+
+#if defined(I2C8) && defined(RTE_I2C8) && RTE_I2C8
+extern ARM_DRIVER_I2C Driver_I2C8;
+#endif
+
+#if defined(I2C9) && defined(RTE_I2C9) && RTE_I2C9
+extern ARM_DRIVER_I2C Driver_I2C9;
+#endif
+
+#if defined(I2C10) && defined(RTE_I2C10) && RTE_I2C10
+extern ARM_DRIVER_I2C Driver_I2C10;
+#endif
+
+#if defined(I2C11) && defined(RTE_I2C11) && RTE_I2C11
+extern ARM_DRIVER_I2C Driver_I2C11;
+#endif
+
+#if defined(I2C12) && defined(RTE_I2C12) && RTE_I2C12
+extern ARM_DRIVER_I2C Driver_I2C12;
+#endif
+
+#if defined(I2C13) && defined(RTE_I2C13) && RTE_I2C13
+extern ARM_DRIVER_I2C Driver_I2C13;
+#endif
+
+/* I2C Driver state flags */
+#define I2C_FLAG_UNINIT (0UL)
+#define I2C_FLAG_INIT   (1UL << 0)
+#define I2C_FLAG_POWER  (1UL << 1)
+
+#endif
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2020 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _FSL_SPI_CMSIS_H_
+#define _FSL_SPI_CMSIS_H_
+
+#include "fsl_spi.h"
+#include "RTE_Device.h"
+#include "Driver_SPI.h"
+#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_spi_dma.h"
+#endif
+
+#if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0
+extern ARM_DRIVER_SPI Driver_SPI0;
+#endif /* SPI0 */
+
+#if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1
+extern ARM_DRIVER_SPI Driver_SPI1;
+#endif /* SPI1 */
+
+#if defined(SPI2) && defined(RTE_SPI2) && RTE_SPI2
+extern ARM_DRIVER_SPI Driver_SPI2;
+#endif /* SPI2 */
+
+#if defined(SPI3) && defined(RTE_SPI3) && RTE_SPI3
+extern ARM_DRIVER_SPI Driver_SPI3;
+#endif /* SPI3 */
+
+#if defined(SPI4) && defined(RTE_SPI4) && RTE_SPI4
+extern ARM_DRIVER_SPI Driver_SPI4;
+#endif /* SPI4 */
+
+#if defined(SPI5) && defined(RTE_SPI5) && RTE_SPI5
+extern ARM_DRIVER_SPI Driver_SPI5;
+#endif /* SPI5 */
+
+#if defined(SPI6) && defined(RTE_SPI6) && RTE_SPI6
+extern ARM_DRIVER_SPI Driver_SPI6;
+#endif /* SPI6 */
+
+#if defined(SPI7) && defined(RTE_SPI7) && RTE_SPI7
+extern ARM_DRIVER_SPI Driver_SPI7;
+#endif /* SPI7 */
+
+#if defined(SPI8) && defined(RTE_SPI8) && RTE_SPI8
+extern ARM_DRIVER_SPI Driver_SPI8;
+#endif /* SPI8 */
+
+#if defined(SPI9) && defined(RTE_SPI9) && RTE_SPI9
+extern ARM_DRIVER_SPI Driver_SPI9;
+#endif /* SPI9 */
+
+#if defined(SPI10) && defined(RTE_SPI10) && RTE_SPI10
+extern ARM_DRIVER_SPI Driver_SPI10;
+#endif /* SPI10 */
+
+#if defined(SPI11) && defined(RTE_SPI11) && RTE_SPI11
+extern ARM_DRIVER_SPI Driver_SPI11;
+#endif /* SPI11 */
+
+#if defined(SPI12) && defined(RTE_SPI12) && RTE_SPI12
+extern ARM_DRIVER_SPI Driver_SPI12;
+#endif /* SPI12 */
+
+#if defined(SPI13) && defined(RTE_SPI13) && RTE_SPI13
+extern ARM_DRIVER_SPI Driver_SPI13;
+#endif /* SPI13 */
+
+#define SPI_FLAG_UNINIT     (0UL)
+#define SPI_FLAG_INIT       (1UL << 0)
+#define SPI_FLAG_POWER      (1UL << 1)
+#define SPI_FLAG_CONFIGURED (1UL << 2)
+#define SPI_FLAG_MASTER     (1UL << 3)
+
+#endif
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2013-2016 ARM Limited. All rights reserved.
+ * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
+ * Copyright 2016-2017 NXP. Not a Contribution.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _FSL_USART_CMSIS_H_
+#define _FSL_USART_CMSIS_H_
+
+#include "fsl_common.h"
+#include "Driver_USART.h"
+#include "RTE_Device.h"
+#include "fsl_usart.h"
+#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
+#include "fsl_usart_dma.h"
+#endif
+
+#if defined(USART0) && defined(RTE_USART0) && RTE_USART0
+extern ARM_DRIVER_USART Driver_USART0;
+#endif /* USART0 */
+
+#if defined(USART1) && defined(RTE_USART1) && RTE_USART1
+extern ARM_DRIVER_USART Driver_USART1;
+#endif /* USART1 */
+
+#if defined(USART2) && defined(RTE_USART2) && RTE_USART2
+extern ARM_DRIVER_USART Driver_USART2;
+#endif /* USART2 */
+
+#if defined(USART3) && defined(RTE_USART3) && RTE_USART3
+extern ARM_DRIVER_USART Driver_USART3;
+#endif /* USART3 */
+
+#if defined(USART4) && defined(RTE_USART4) && RTE_USART4
+extern ARM_DRIVER_USART Driver_USART4;
+#endif /* USART4 */
+
+#if defined(USART5) && defined(RTE_USART5) && RTE_USART5
+extern ARM_DRIVER_USART Driver_USART5;
+#endif /* USART5 */
+
+#if defined(USART6) && defined(RTE_USART6) && RTE_USART6
+extern ARM_DRIVER_USART Driver_USART6;
+#endif /* USART6 */
+
+#if defined(USART7) && defined(RTE_USART7) && RTE_USART7
+extern ARM_DRIVER_USART Driver_USART7;
+#endif /* USART7 */
+
+#if defined(USART8) && defined(RTE_USART8) && RTE_USART8
+extern ARM_DRIVER_USART Driver_USART8;
+#endif /* USART8 */
+
+#if defined(USART9) && defined(RTE_USART9) && RTE_USART9
+extern ARM_DRIVER_USART Driver_USART9;
+#endif /* USART9 */
+
+#if defined(USART10) && defined(RTE_USART10) && RTE_USART10
+extern ARM_DRIVER_USART Driver_USART10;
+#endif /* USART10 */
+
+#if defined(USART11) && defined(RTE_USART11) && RTE_USART11
+extern ARM_DRIVER_USART Driver_USART11;
+#endif /* USART11 */
+
+#if defined(USART12) && defined(RTE_USART12) && RTE_USART12
+extern ARM_DRIVER_USART Driver_USART12;
+#endif /* USART12 */
+
+#if defined(USART13) && defined(RTE_USART13) && RTE_USART13
+extern ARM_DRIVER_USART Driver_USART13;
+#endif /* USART13 */
+
+/* USART Driver state flags */
+#define USART_FLAG_UNINIT     (0UL)
+#define USART_FLAG_INIT       (1UL << 0)
+#define USART_FLAG_POWER      (1UL << 1)
+#define USART_FLAG_CONFIGURED (1UL << 2)
+
+#endif /* _FSL_USART_CMSIS_H_ */
@@ -1,9 +1,9 @@
 /*
- * Copyright 2018 NXP
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-3-Clause
-*/
+ * Copyright 2018-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */

 #include "fsl_cmp.h"

@@ -23,33 +23,106 @@
 /*******************************************************************************
 * Code
 ******************************************************************************/
-void CMP_Init(cmp_config_t *config)
+
+/*!
+ * @brief CMP initialization.
+ *
+ * This function enables the CMP module and do necessary settings.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_Init(const cmp_config_t *config)
 {
    assert(NULL != config);

-/*enable the clock to the register interface*/
+    uint32_t tmpReg = 0U;
+
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
    CLOCK_EnableClock(kCLOCK_Comp);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

-/*Clear reset to peripheral cmp*/
 #if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
-    RESET_ClearPeripheralReset(kCMP_RST_SHIFT_RSTn);
-#endif
+    /* Reset the CMP module. */
+    RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn);
+#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */

-    /*clear COMP bits*/
-    PMC->COMP &= ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
+    tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK |
+                            PMC_COMP_FILTERCGF_SAMPLEMODE_MASK));

-    PMC->COMP |= (config->enLowPower << PMC_COMP_LOWPOWER_SHIFT) /*Select if enter low power mode*/
-                 | (config->enHysteris << PMC_COMP_HYST_SHIFT)   /*select if enable hysteresis*/
-                 | config->pmuxInput                             /*pmux input source select*/
-                 | config->nmuxInput;                            /*nmux input source select */
+    if (true == config->enableLowPower)
+    {
+        tmpReg |= PMC_COMP_LOWPOWER_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_LOWPOWER_MASK;
+    }
+
+    if (true == config->enableHysteresis)
+    {
+        tmpReg |= PMC_COMP_HYST_MASK;
+    }
+    else
+    {
+        tmpReg &= ~PMC_COMP_HYST_MASK;
+    }
+
+    tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) |
+               PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode));
+
+    PMC->COMP = tmpReg;
 }

+/*!
+ * @brief CMP deinitialization.
+ *
+ * This function gates the clock for CMP module.
+ */
 void CMP_Deinit(void)
 {
-/*disable the clock to the register interface*/
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
    CLOCK_DisableClock(kCLOCK_Comp);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
+
+/*!
+ * @brief Initializes the CMP user configuration structure.
+ *
+ * This function initializes the user configuration structure to these default values.
+ * @code
+ *   config->enableHysteresis    = true;
+ *   config->enableLowPower      = true;
+ *   config->filterClockDivider  = kCMP_FilterClockDivide1;
+ *   config->filterSampleMode    = kCMP_FilterSampleMode0;
+ * @endcode
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_GetDefaultConfig(cmp_config_t *config)
+{
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    config->enableHysteresis   = true;
+    config->enableLowPower     = true;
+    config->filterClockDivider = kCMP_FilterClockDivide1;
+    config->filterSampleMode   = kCMP_FilterSampleMode0;
+}
+
+/*!
+ * @brief Configures the VREFINPUT.
+ *
+ * @param config Pointer to the configuration structure.
+ */
+void CMP_SetVREF(const cmp_vref_config_t *config)
+{
+    assert(NULL != config);
+    assert(config->vrefValue < 32U);
+
+    uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK);
+
+    tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue);
+
+    PMC->COMP = tmpReg;
+}
@@ -1,13 +1,13 @@
 /*
 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2021 NXP
 * All rights reserved.
 *
- *
 * SPDX-License-Identifier: BSD-3-Clause
 */

 #include "fsl_common.h"
+
 #define SDK_MEM_MAGIC_NUMBER 12345U

 typedef struct _mem_align_control_block
@@ -21,127 +21,65 @@ typedef struct _mem_align_control_block
 #define FSL_COMPONENT_ID "platform.drivers.common"
 #endif

-#ifndef __GIC_PRIO_BITS
-#if defined(ENABLE_RAM_VECTOR_TABLE)
-uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
-{
-/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
-    extern uint32_t Image$$VECTOR_ROM$$Base[];
-    extern uint32_t Image$$VECTOR_RAM$$Base[];
-    extern uint32_t Image$$RW_m_data$$Base[];
-
-#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
-#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
-#elif defined(__ICCARM__)
-    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
-    extern uint32_t __VECTOR_TABLE[];
-    extern uint32_t __VECTOR_RAM[];
-#elif defined(__GNUC__)
-    extern uint32_t __VECTOR_TABLE[];
-    extern uint32_t __VECTOR_RAM[];
-    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
-    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
-#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
-    uint32_t n;
-    uint32_t ret;
-    uint32_t irqMaskValue;
-
-    irqMaskValue = DisableGlobalIRQ();
-    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
-    {
-        /* Copy the vector table from ROM to RAM */
-        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
-        {
-            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
-        }
-        /* Point the VTOR to the position of vector table */
-        SCB->VTOR = (uint32_t)__VECTOR_RAM;
-    }
-
-    ret = __VECTOR_RAM[irq + 16];
-    /* make sure the __VECTOR_RAM is noncachable */
-    __VECTOR_RAM[irq + 16] = irqHandler;
-
-    EnableGlobalIRQ(irqMaskValue);
-
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
-
-    return ret;
-}
-#endif /* ENABLE_RAM_VECTOR_TABLE. */
-#endif /* __GIC_PRIO_BITS. */
-
-#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
-
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t intNumber = (uint32_t)interrupt;
-
-    uint32_t index = 0;
-
-    while (intNumber >= 32u)
-    {
-        index++;
-        intNumber -= 32u;
-    }
-
-    SYSCON->STARTERSET[index] = 1u << intNumber;
-    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
-    uint32_t intNumber = (uint32_t)interrupt;
-
-    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
-    uint32_t index = 0;
-
-    while (intNumber >= 32u)
-    {
-        index++;
-        intNumber -= 32u;
-    }
-
-    SYSCON->STARTERCLR[index] = 1u << intNumber;
-}
-#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
-#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-
+#if !((defined(__DSC__) && defined(__CW__)))
 void *SDK_Malloc(size_t size, size_t alignbytes)
 {
    mem_align_cb_t *p_cb = NULL;
-    uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
-    void *p_align_addr, *p_addr = malloc(alignedsize);
+    uint32_t alignedsize;

-    if (!p_addr)
+    /* Check overflow. */
+    alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes);
+    if (alignedsize < size)
    {
        return NULL;
    }

-    p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes);
+    if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t))
+    {
+        return NULL;
+    }

-    p_cb             = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U);
+    alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t);
+
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc((size_t)alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
-    p_cb->offset     = (uint32_t)p_align_addr - (uint32_t)p_addr;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);

-    return (void *)p_align_addr;
+    return p_align_addr.pointer_value;
 }

 void SDK_Free(void *ptr)
 {
-    mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U);
+    union
+    {
+        void *pointer_value;
+        uintptr_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);

    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
    {
        return;
    }

-    free((void *)((uint32_t)ptr - p_cb->offset));
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
 }
+#endif
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2019-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -57,7 +57,7 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config)
 #endif

    /* configure CRC module and write the seed */
-    base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
+    base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) |
                 CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) |
                 CRC_MODE_CMPL_SUM(config->complementOut);
    base->SEED = config->seed;
@@ -81,7 +81,7 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config)
 void CRC_GetDefaultConfig(crc_config_t *config)
 {
    /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));

    static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL,     CRC_DRIVER_DEFAULT_REVERSE_IN,
                                                CRC_DRIVER_DEFAULT_COMPLEMENT_IN,  CRC_DRIVER_DEFAULT_REVERSE_OUT,
@@ -102,6 +102,18 @@ void CRC_Reset(CRC_Type *base)
    CRC_Init(base, &config);
 }

+/*!
+ * brief Write seed (initial checksum) to CRC peripheral module.
+ *
+ * param base   CRC peripheral address.
+ * param seed   CRC Seed value.
+ */
+void CRC_WriteSeed(CRC_Type *base, uint32_t seed)
+{
+    /*  write the seed (initial checksum) */
+    base->SEED = seed;
+}
+
 /*!
 * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure.
 *
@@ -113,8 +125,9 @@ void CRC_Reset(CRC_Type *base)
 void CRC_GetConfig(CRC_Type *base, crc_config_t *config)
 {
    /* extract CRC mode settings */
-    uint32_t mode         = base->MODE;
-    config->polynomial    = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT);
+    uint32_t mode = base->MODE;
+    config->polynomial =
+        (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT);
    config->reverseIn     = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK);
    config->complementIn  = (bool)(mode & CRC_MODE_CMPL_WR_MASK);
    config->reverseOut    = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK);
@@ -144,7 +157,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
    const uint32_t *data32;

    /* 8-bit reads and writes till source address is aligned 4 bytes */
-    while ((dataSize) && ((uint32_t)data & 3U))
+    while ((0U != dataSize) && (0U != ((uint32_t)data & 3U)))
    {
        *((__O uint8_t *)&(base->WR_DATA)) = *data;
        data++;
@@ -152,7 +165,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
    }

    /* use 32-bit reads and writes as long as possible */
-    data32 = (const uint32_t *)data;
+    data32 = (const uint32_t *)(uint32_t)data;
    while (dataSize >= sizeof(uint32_t))
    {
        *((__O uint32_t *)&(base->WR_DATA)) = *data32;
@@ -163,7 +176,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize)
    data = (const uint8_t *)data32;

    /* 8-bit reads and writes till end of data buffer */
-    while (dataSize)
+    while (0U != dataSize)
    {
        *((__O uint8_t *)&(base->WR_DATA)) = *data;
        data++;
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2019-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -24,17 +24,23 @@

 /*! @name Driver version */
 /*@{*/
-/*! @brief CRC driver version. Version 2.0.1.
+/*! @brief CRC driver version. Version 2.1.1.
 *
- * Current version: 2.0.1
+ * Current version: 2.1.1
 *
 * Change log:
 * - Version 2.0.0
 *   - initial version
 * - Version 2.0.1
 *   - add explicit type cast when writing to WR_DATA
+ * - Version 2.0.2
+ *   - Fix MISRA issue
+ * - Version 2.1.0
+ *   - Add CRC_WriteSeed function
+ * - Version 2.1.1
+ *   - Fix MISRA issue
 */
-#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
 /*@}*/

 #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
@@ -106,6 +112,14 @@ static inline void CRC_Deinit(CRC_Type *base)
 */
 void CRC_Reset(CRC_Type *base);

+/*!
+ * @brief Write seed to CRC peripheral module.
+ *
+ * @param base   CRC peripheral address.
+ * @param seed   CRC Seed value.
+ */
+void CRC_WriteSeed(CRC_Type *base, uint32_t seed);
+
 /*!
 * @brief Loads default values to CRC protocol configuration structure.
 *
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@

 /*! @name Driver version */
 /*@{*/
-#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */
+#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */
 /*@}*/

 /*! @brief List of Timer capture channels */
@@ -31,10 +31,12 @@ typedef enum _ctimer_capture_channel
 {
    kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
    kCTIMER_Capture_1,      /*!< Timer capture channel 1 */
-    kCTIMER_Capture_2,      /*!< Timer capture channel 2 */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+    kCTIMER_Capture_2, /*!< Timer capture channel 2 */
+#endif                 /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
    kCTIMER_Capture_3 /*!< Timer capture channel 3 */
-#endif                /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
+#endif                /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
 } ctimer_capture_channel_t;

 /*! @brief List of capture edge options */
@@ -54,6 +56,15 @@ typedef enum _ctimer_match
    kCTIMER_Match_3       /*!< Timer match register 3 */
 } ctimer_match_t;

+/*! @brief List of external match */
+typedef enum _ctimer_external_match
+{
+    kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */
+    kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */
+    kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */
+    kCTIMER_External_Match_3 = (1U << 3)  /*!< External match 3 */
+} ctimer_external_match_t;
+
 /*! @brief List of output control options */
 typedef enum _ctimer_match_output_control
 {
@@ -82,7 +93,9 @@ typedef enum _ctimer_interrupt_enable
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
    kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
    kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
    kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
+#endif                                                       /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
    kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
 #endif                                                       /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
@@ -99,7 +112,9 @@ typedef enum _ctimer_status_flags
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
    kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
    kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT)
    kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
+#endif                                            /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */
 #if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
    kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
 #endif                                            /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
@@ -211,46 +226,47 @@ void CTIMER_GetDefaultConfig(ctimer_config_t *config);
 *
 * Enables PWM mode on the match channel passed in and will then setup the match value
 * and other match parameters to generate a PWM signal.
- * This function will assign match channel 3 to set the PWM cycle.
+ * This function can manually assign the specified channel to set the PWM cycle.
 *
 * @note When setting PWM output from multiple output pins, all should use the same PWM
 * period
 *
 * @param base             Ctimer peripheral base address
+ * @param pwmPeriodChannel Specify the channel to control the PWM period
 * @param matchChannel     Match pin to be used to output the PWM signal
 * @param pwmPeriod        PWM period match value
 * @param pulsePeriod      Pulse width match value
 * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
- *                         if it is 0 then no interrupt is generated
- *
- * @return kStatus_Success on success
- *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period
+ *                         if it is 0 then no interrupt will be generated.
 */
-status_t CTIMER_SetupPwmPeriod(
-    CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt);
+status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base,
+                               const ctimer_match_t pwmPeriodChannel,
+                               ctimer_match_t matchChannel,
+                               uint32_t pwmPeriod,
+                               uint32_t pulsePeriod,
+                               bool enableInt);

 /*!
 * @brief Configures the PWM signal parameters.
 *
 * Enables PWM mode on the match channel passed in and will then setup the match value
 * and other match parameters to generate a PWM signal.
- * This function will assign match channel 3 to set the PWM cycle.
+ * This function can manually assign the specified channel to set the PWM cycle.
 *
 * @note When setting PWM output from multiple output pins, all should use the same PWM
 * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution.
 *
 * @param base             Ctimer peripheral base address
+ * @param pwmPeriodChannel Specify the channel to control the PWM period
 * @param matchChannel     Match pin to be used to output the PWM signal
 * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100
 * @param pwmFreq_Hz       PWM signal frequency in Hz
 * @param srcClock_Hz      Timer counter clock in Hz
 * @param enableInt        Enable interrupt when the timer value reaches the match value of the PWM pulse,
- *                         if it is 0 then no interrupt is generated
- *
- * @return kStatus_Success on success
- *         kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle
+ *                         if it is 0 then no interrupt will be generated.
 */
 status_t CTIMER_SetupPwm(CTIMER_Type *base,
+                         const ctimer_match_t pwmPeriodChannel,
                         ctimer_match_t matchChannel,
                         uint8_t dutyCyclePercent,
                         uint32_t pwmFreq_Hz,
@@ -273,13 +289,18 @@ static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t
 /*!
 * @brief Updates the duty cycle of an active PWM signal.
 *
- * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution.
+ * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution.
+ * This function can manually assign the specified channel to set the PWM cycle.
 *
 * @param base             Ctimer peripheral base address
+ * @param pwmPeriodChannel Specify the channel to control the PWM period
 * @param matchChannel     Match pin to be used to output the PWM signal
 * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100
 */
-void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent);
+void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base,
+                               const ctimer_match_t pwmPeriodChannel,
+                               ctimer_match_t matchChannel,
+                               uint8_t dutyCyclePercent);

 /*! @}*/

@@ -294,6 +315,21 @@ void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, u
 */
 void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config);

+/*!
+ * @brief Get the status of output match.
+ *
+ * This function gets the status of output MAT, whether or not this output is connected to a pin.
+ * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH.
+ *
+ * @param base         Ctimer peripheral base address
+ * @param matchChannel External match channel, user can obtain the status of multiple match channels
+ *                     at the same time by using the logic of "|"
+ *                     enumeration ::ctimer_external_match_t
+ * @return The mask of external match channel status flags. Users need to use the
+ *         _ctimer_external_match type to decode the return variables.
+ */
+uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel);
+
 /*!
 * @brief Setup the capture.
 *
@@ -347,7 +383,10 @@ static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)

 /* Enable capture interrupts */
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
-    base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+    base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+                         | CTIMER_CCR_CAP2I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
                         | CTIMER_CCR_CAP3I_MASK
 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
@@ -369,7 +408,10 @@ static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)

 /* Disable capture interrupts */
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
-    base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+    base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+                           | CTIMER_CCR_CAP2I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
                           | CTIMER_CCR_CAP3I_MASK
 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
@@ -395,7 +437,10 @@ static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base)

 /* Get all the capture interrupts enabled */
 #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE))
-    enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+    enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK
+#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2)
+                                 | CTIMER_CCR_CAP2I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */
 #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
                                 | CTIMER_CCR_CAP3I_MASK
 #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -17,8 +17,8 @@

 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexCOMM driver version 2.0.1. */
-#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/

 /*! @brief FLEXCOMM peripheral modes. */
@@ -53,7 +53,7 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);

 /*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
 * mode */
-void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle);

 #if defined(__cplusplus)
 }
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2017, NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FRO_CALIB_H_
+#define _FSL_FRO_CALIB_H_
+
+#include "fsl_common.h"
+#include "fsl_device_registers.h"
+#include <stdint.h>
+
+/*!
+ * @addtogroup power
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FRO_CALIB driver version 1.0.0. */
+#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*@}*/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.fro_calib"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Returns the version of the FRO Calibration library */
+unsigned int fro_calib_Get_Lib_Ver(void);
+
+/* ctimer instance */
+/* ctimer clock frquency in KHz */
+void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq);
+
+/* USB_SOF_Event */
+/* Application software should be written to make sure the USB_SOF_EVENT() is */
+/* being called with lower interrupt latency for calibration to work properly */
+void USB_SOF_Event(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+
+#endif /* _FSL_FRO_CALIB_H_ */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -124,11 +124,15 @@ void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t
 void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback)
 {
    uint32_t instance;
+    uint32_t combValue;
+    uint32_t trigValue;

    instance = GINT_GetInstance(base);

-    *comb     = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT);
-    *trig     = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT);
+    combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT;
+    *comb     = (gint_comb_t)combValue;
+    trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT;
+    *trig     = (gint_trig_t)trigValue;
    *callback = s_gintCallback[instance];
 }

@@ -193,7 +197,7 @@ void GINT_EnableCallback(GINT_Type *base)
       Clear status and pending interrupt before enabling the irq in NVIC. */
    GINT_ClrStatus(base);
    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
-    EnableIRQ(s_gintIRQ[instance]);
+    (void)EnableIRQ(s_gintIRQ[instance]);
 }

 /*!
@@ -211,7 +215,7 @@ void GINT_DisableCallback(GINT_Type *base)
    uint32_t instance;

    instance = GINT_GetInstance(base);
-    DisableIRQ(s_gintIRQ[instance]);
+    (void)DisableIRQ(s_gintIRQ[instance]);
    GINT_ClrStatus(base);
    NVIC_ClearPendingIRQ(s_gintIRQ[instance]);
 }
@@ -248,6 +252,7 @@ void GINT_Deinit(GINT_Type *base)

 /* IRQ handler functions overloading weak symbols in the startup */
 #if defined(GINT0)
+void GINT0_DriverIRQHandler(void);
 void GINT0_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -257,15 +262,12 @@ void GINT0_DriverIRQHandler(void)
    {
        s_gintCallback[0]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

 #if defined(GINT1)
+void GINT1_DriverIRQHandler(void);
 void GINT1_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -275,15 +277,12 @@ void GINT1_DriverIRQHandler(void)
    {
        s_gintCallback[1]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

 #if defined(GINT2)
+void GINT2_DriverIRQHandler(void);
 void GINT2_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -293,15 +292,12 @@ void GINT2_DriverIRQHandler(void)
    {
        s_gintCallback[2]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

 #if defined(GINT3)
+void GINT3_DriverIRQHandler(void);
 void GINT3_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -311,15 +307,12 @@ void GINT3_DriverIRQHandler(void)
    {
        s_gintCallback[3]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

 #if defined(GINT4)
+void GINT4_DriverIRQHandler(void);
 void GINT4_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -329,15 +322,12 @@ void GINT4_DriverIRQHandler(void)
    {
        s_gintCallback[4]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

 #if defined(GINT5)
+void GINT5_DriverIRQHandler(void);
 void GINT5_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -347,15 +337,12 @@ void GINT5_DriverIRQHandler(void)
    {
        s_gintCallback[5]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

 #if defined(GINT6)
+void GINT6_DriverIRQHandler(void);
 void GINT6_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -365,15 +352,12 @@ void GINT6_DriverIRQHandler(void)
    {
        s_gintCallback[6]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif

 #if defined(GINT7)
+void GINT7_DriverIRQHandler(void);
 void GINT7_DriverIRQHandler(void)
 {
    /* Clear interrupt before callback */
@@ -383,10 +367,6 @@ void GINT7_DriverIRQHandler(void)
    {
        s_gintCallback[7]();
    }
-/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
-  exception return operation might vector to incorrect interrupt */
-#if defined __CORTEX_M && (__CORTEX_M == 4U)
-    __DSB();
-#endif
+    SDK_ISR_EXIT_BARRIER;
 }
 #endif
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -24,7 +24,7 @@

 /*! @name Driver version */
 /*@{*/
-#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
+#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */
 /*@}*/

 /*! @brief GINT combine inputs type */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -24,14 +24,14 @@

 /*! @name Driver version */
 /*@{*/
-/*! @brief LPC GPIO driver version 2.1.3. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*! @brief LPC GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7))
 /*@}*/

 /*! @brief LPC GPIO direction definition */
 typedef enum _gpio_pin_direction
 {
-    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input*/
+    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
 } gpio_pin_direction_t;

@@ -50,16 +50,16 @@ typedef struct _gpio_pin_config

 #if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
 #define GPIO_PIN_INT_LEVEL 0x00U
-#define GPIO_PIN_INT_EDGE 0x01U
+#define GPIO_PIN_INT_EDGE  0x01U

 #define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
-#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER  0x01U

 /*! @brief GPIO Pin Interrupt enable mode */
 typedef enum _gpio_pin_enable_mode
 {
    kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
-    kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE    /*!< Generate Pin Interrupt on edge mode */
+    kGPIO_PinIntEnableEdge  = GPIO_PIN_INT_EDGE   /*!< Generate Pin Interrupt on edge mode */
 } gpio_pin_enable_mode_t;

 /*! @brief GPIO Pin Interrupt enable polarity */
@@ -81,8 +81,8 @@ typedef enum _gpio_interrupt_index
 /*! @brief Configures the interrupt generation condition. */
 typedef struct _gpio_interrupt_config
 {
-    uint8_t mode;         /* The trigger mode of GPIO interrupts */
-    uint8_t polarity;     /* The polarity of GPIO interrupts */
+    uint8_t mode;     /* The trigger mode of GPIO interrupts */
+    uint8_t polarity; /* The polarity of GPIO interrupts */
 } gpio_interrupt_config_t;
 #endif

@@ -90,8 +90,7 @@ typedef struct _gpio_interrupt_config
 * API
 ******************************************************************************/
 #if defined(__cplusplus)
-extern "C"
-{
+extern "C" {
 #endif

 /*! @name GPIO Configuration */
@@ -115,13 +114,13 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port);
 *
 * This is an example to define an input pin or output pin configuration:
 * @code
- * // Define a digital input pin configuration,
+ * Define a digital input pin configuration,
 * gpio_pin_config_t config =
 * {
 *   kGPIO_DigitalInput,
 *   0,
 * }
- * //Define a digital output pin configuration,
+ * Define a digital output pin configuration,
 * gpio_pin_config_t config =
 * {
 *   kGPIO_DigitalOutput,
@@ -269,7 +268,7 @@ static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)

 #if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
 /*!
- * @brief Configures the gpio pin interrupt.
+ * @brief Set the configuration of pin interrupt.
 *
 * @param base GPIO base pointer.
 * @param port GPIO port number
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -26,9 +26,9 @@ enum _hashcrypt_status
 */
 /*! @name Driver version */
 /*@{*/
-/*! @brief HASHCRYPT driver version. Version 2.0.2.
+/*! @brief HASHCRYPT driver version. Version 2.2.5.
 *
- * Current version: 2.0.2
+ * Current version: 2.2.5
 *
 * Change log:
 * - Version 2.0.0
@@ -37,18 +37,55 @@ enum _hashcrypt_status
 *   - Support loading AES key from unaligned address
 * - Version 2.0.2
 *   - Support loading AES key from unaligned address for different compiler and core variants
+ * - Version 2.0.3
+ *   - Remove SHA512 and AES ICB algorithm definitions
+ * - Version 2.0.4
+ *   - Add SHA context switch support
+ * - Version 2.1.0
+ *   - Update the register name and macro to align with new header.
+ * - Version 2.1.1
+ *   - Fix MISRA C-2012.
+ * - Version 2.1.2
+ *   - Support loading AES input data from unaligned address.
+ * - Version 2.1.3
+ *   - Fix MISRA C-2012.
+ * - Version 2.1.4
+ *   - Fix context switch cannot work when switching from AES.
+ * - Version 2.1.5
+ *   - Add data synchronization barriere inside hashcrypt_sha_ldm_stm_16_words()
+ *     to prevent possible optimization issue.
+ * - Version 2.2.0
+ *   - Add AES-OFB and AES-CFB mixed IP/SW modes.
+ * - Version 2.2.1
+ *   - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words()
+ *     prevent compiler from reordering memory write when -O2 or higher is used.
+ * - Version 2.2.2
+ *   - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words()
+ *     to fix optimization issue
+ * - Version 2.2.3
+ *   - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its
+ * bigger than COUNT field do a multiple runs.
+ * - Version 2.2.4
+ *   - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which
+ * decreases power consumption.
+ * - Version 2.2.5
+ *   - Add data synchronization barrier and instruction  synchronization barrier inside
+ * hashcrypt_sha_process_message_data() to fix optimization issue
 */
-#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 5))
 /*@}*/

+/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/
+#define HASHCRYPT_MODE_SHA1   0x1
+#define HASHCRYPT_MODE_SHA256 0x2
+#define HASHCRYPT_MODE_AES    0x4
+
 /*! @brief Algorithm used for Hashcrypt operation */
 typedef enum _hashcrypt_algo_t
 {
-    kHASHCRYPT_Sha1   = 1, /*!< SHA_1 */
-    kHASHCRYPT_Sha256 = 2, /*!< SHA_256 */
-    kHASHCRYPT_Sha512 = 3, /*!< SHA_512 */
-    kHASHCRYPT_Aes    = 4, /*!< AES */
-    kHASHCRYPT_AesIcb = 5, /*!< AES_ICB */
+    kHASHCRYPT_Sha1   = HASHCRYPT_MODE_SHA1,   /*!< SHA_1 */
+    kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */
+    kHASHCRYPT_Aes    = HASHCRYPT_MODE_AES,    /*!< AES */
 } hashcrypt_algo_t;

 /*! @} */
@@ -63,9 +100,9 @@ typedef enum _hashcrypt_algo_t
 */

 /*! AES block size in bytes */
-#define HASHCRYPT_AES_BLOCK_SIZE 16
-#define AES_ENCRYPT 0
-#define AES_DECRYPT 1
+#define HASHCRYPT_AES_BLOCK_SIZE 16U
+#define AES_ENCRYPT              0
+#define AES_DECRYPT              1

 /*! @brief AES mode */
 typedef enum _hashcrypt_aes_mode_t
@@ -116,7 +153,11 @@ typedef struct _hashcrypt_handle hashcrypt_handle_t;
 */

 /*! @brief HASHCRYPT HASH Context size. */
+#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0)
+#define HASHCRYPT_HASH_CTX_SIZE 30
+#else
 #define HASHCRYPT_HASH_CTX_SIZE 22
+#endif

 /*! @brief Storage type used to save hash context. */
 typedef struct _hashcrypt_hash_ctx_t
@@ -287,6 +328,68 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base,
                                uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE],
                                size_t *szLeft);

+/*!
+ * @brief Encrypts or decrypts AES using OFB block mode.
+ *
+ * Encrypts or decrypts AES using OFB block mode.
+ * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption.
+ * The only difference between encryption and decryption is that, for encryption, the input argument
+ * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
+ * and the output argument is plain text.
+ *
+ * @param base HASHCRYPT peripheral base address
+ * @param handle Handle used for this request.
+ * @param input Input data for OFB block mode
+ * @param[out] output Output data for OFB block mode
+ * @param size Size of input and output data in bytes
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+
+status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base,
+                                hashcrypt_handle_t *handle,
+                                const uint8_t *input,
+                                uint8_t *output,
+                                size_t size,
+                                const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]);
+
+/*!
+ * @brief Encrypts AES using CFB block mode.
+ *
+ * @param base HASHCRYPT peripheral base address
+ * @param handle Handle used for this request.
+ * @param plaintext Input plain text to encrypt
+ * @param[out] ciphertext Output cipher text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+
+status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base,
+                                  hashcrypt_handle_t *handle,
+                                  const uint8_t *plaintext,
+                                  uint8_t *ciphertext,
+                                  size_t size,
+                                  const uint8_t iv[16]);
+
+/*!
+ * @brief Decrypts AES using CFB block mode.
+ *
+ * @param base HASHCRYPT peripheral base address
+ * @param handle Handle used for this request.
+ * @param ciphertext Input cipher text to decrypt
+ * @param[out] plaintext Output plaintext text
+ * @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
+ * @param iv Input initial vector to combine with the first input block.
+ * @return Status from encrypt operation
+ */
+
+status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base,
+                                  hashcrypt_handle_t *handle,
+                                  const uint8_t *ciphertext,
+                                  uint8_t *plaintext,
+                                  size_t size,
+                                  const uint8_t iv[16]);
 /*!
 *@}
 */ /* end of hashcrypt_driver_aes */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -22,8 +22,8 @@

 /*! @name Driver version */
 /*@{*/
-/*! @brief I2C DMA driver version 2.0.3. */
-#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
+/*! @brief I2C DMA driver version. */
+#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
 /*@}*/

 /*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */
@@ -38,6 +38,9 @@ typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base,
                                                   status_t status,
                                                   void *userData);

+/*! @brief Typedef for master dma handler. */
+typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle);
+
 /*! @brief I2C master dma transfer structure. */
 struct _i2c_master_dma_handle
 {
@@ -47,8 +50,9 @@ struct _i2c_master_dma_handle
    uint8_t *buf;               /*!< Buffer pointer for current state. */
    uint32_t remainingSubaddr;
    uint8_t subaddrBuf[4];
-    dma_handle_t *dmaHandle;                               /*!< The DMA handler used. */
-    i2c_master_transfer_t transfer;                        /*!< Copy of the current transfer info. */
+    bool checkAddrNack;             /*!< Whether to check the nack signal is detected during addressing. */
+    dma_handle_t *dmaHandle;        /*!< The DMA handler used. */
+    i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
    i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */
    void *userData;                                        /*!< Callback parameter passed to callback function. */
 };
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_i2c_freertos.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_freertos"
+#endif
+
+static void I2C_RTOS_Callback(I2C_Type *base, i2c_master_handle_t *drv_handle, status_t status, void *userData)
+{
+    i2c_rtos_handle_t *handle = (i2c_rtos_handle_t *)userData;
+    BaseType_t reschedule;
+    handle->async_status = status;
+    (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule);
+    portYIELD_FROM_ISR(reschedule);
+}
+
+/*!
+ * brief Initializes I2C.
+ *
+ * This function initializes the I2C module and the related RTOS context.
+ *
+ * param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context.
+ * param base The pointer base address of the I2C instance to initialize.
+ * param masterConfig Configuration structure to set-up I2C in master mode.
+ * param srcClock_Hz Frequency of input clock of the I2C module.
+ * return status of the operation.
+ */
+status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle,
+                       I2C_Type *base,
+                       const i2c_master_config_t *masterConfig,
+                       uint32_t srcClock_Hz)
+{
+    if (handle == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (base == NULL)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    (void)memset(handle, 0, sizeof(i2c_rtos_handle_t));
+
+    handle->mutex = xSemaphoreCreateMutex();
+    if (handle->mutex == NULL)
+    {
+        return kStatus_Fail;
+    }
+
+    handle->semaphore = xSemaphoreCreateBinary();
+    if (handle->semaphore == NULL)
+    {
+        vSemaphoreDelete(handle->mutex);
+        return kStatus_Fail;
+    }
+
+    handle->base = base;
+
+    I2C_MasterInit(handle->base, masterConfig, srcClock_Hz);
+    I2C_MasterTransferCreateHandle(base, &handle->drv_handle, I2C_RTOS_Callback, (void *)handle);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes the I2C.
+ *
+ * This function deinitializes the I2C module and the related RTOS context.
+ *
+ * param handle The RTOS I2C handle.
+ */
+status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle)
+{
+    I2C_MasterDeinit(handle->base);
+
+    vSemaphoreDelete(handle->semaphore);
+    vSemaphoreDelete(handle->mutex);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs I2C transfer.
+ *
+ * This function performs an I2C transfer according to data given in the transfer structure.
+ *
+ * param handle The RTOS I2C handle.
+ * param transfer Structure specifying the transfer parameters.
+ * return status of the operation.
+ */
+status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer)
+{
+    status_t status;
+
+    /* Lock resource mutex */
+    if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE)
+    {
+        return kStatus_I2C_Busy;
+    }
+
+    status = I2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer);
+    if (status != kStatus_Success)
+    {
+        (void)xSemaphoreGive(handle->mutex);
+        return status;
+    }
+
+    /* Wait for transfer to finish */
+    (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY);
+
+    /* Unlock resource mutex */
+    (void)xSemaphoreGive(handle->mutex);
+
+    /* Return status captured by callback function */
+    return handle->async_status;
+}
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __FSL_I2C_FREERTOS_H__
+#define __FSL_I2C_FREERTOS_H__
+
+#include "FreeRTOS.h"
+#include "portable.h"
+#include "semphr.h"
+
+#include "fsl_i2c.h"
+
+/*!
+ * @addtogroup i2c_freertos_driver I2C FreeRTOS Driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief I2C FreeRTOS driver version 2.0.8. */
+#define FSL_I2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 8))
+/*@}*/
+
+/*! @brief I2C FreeRTOS handle */
+typedef struct _i2c_rtos_handle
+{
+    I2C_Type *base;                 /*!< I2C base address */
+    i2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */
+    status_t async_status;          /*!< Transactional state of the underlying driver */
+    SemaphoreHandle_t mutex;        /*!< A mutex to lock the handle during a transfer */
+    SemaphoreHandle_t semaphore;    /*!< A semaphore to notify and unblock task when the transfer ends */
+#if (configSUPPORT_STATIC_ALLOCATION == 1)
+    StaticSemaphore_t mutexBuffer;     /*!< Statically allocated memory for mutex */
+    StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */
+#endif
+} i2c_rtos_handle_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name I2C RTOS Operation
+ * @{
+ */
+
+/*!
+ * @brief Initializes I2C.
+ *
+ * This function initializes the I2C module and the related RTOS context.
+ *
+ * @param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context.
+ * @param base The pointer base address of the I2C instance to initialize.
+ * @param masterConfig Configuration structure to set-up I2C in master mode.
+ * @param srcClock_Hz Frequency of input clock of the I2C module.
+ * @return status of the operation.
+ */
+status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle,
+                       I2C_Type *base,
+                       const i2c_master_config_t *masterConfig,
+                       uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes the I2C.
+ *
+ * This function deinitializes the I2C module and the related RTOS context.
+ *
+ * @param handle The RTOS I2C handle.
+ */
+status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle);
+
+/*!
+ * @brief Performs I2C transfer.
+ *
+ * This function performs an I2C transfer according to data given in the transfer structure.
+ *
+ * @param handle The RTOS I2C handle.
+ * @param transfer Structure specifying the transfer parameters.
+ * @return status of the operation.
+ */
+status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer);
+
+/*!
+ * @}
+ */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* __FSL_I2C_FREERTOS_H__ */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -26,19 +26,19 @@
 /*! @name Driver version */
 /*@{*/

-/*! @brief I2S driver version 2.1.0. */
-#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief I2S driver version 2.3.1. */
+#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
 /*@}*/

 #ifndef I2S_NUM_BUFFERS

 /*! @brief Number of buffers . */
-#define I2S_NUM_BUFFERS (4)
+#define I2S_NUM_BUFFERS (4U)

 #endif

-/*! @brief I2S status codes. */
-enum _i2s_status
+/*! @brief _i2s_status I2S status codes. */
+enum
 {
    kStatus_I2S_BufferComplete =
        MAKE_STATUS(kStatusGroup_I2S, 0),                /*!< Transfer from/into a single buffer has completed */
@@ -78,8 +78,8 @@ typedef enum _i2s_mode
    kI2S_ModeDspWsLong  = 0x3  /*!< DSP mode, WS having one data slot long pulse */
 } i2s_mode_t;

-/*! @brief I2S secondary channel. */
-enum _i2s_secondary_channel
+/*! @brief _i2s_secondary_channel I2S secondary channel. */
+enum
 {
    kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */
    kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */
@@ -112,8 +112,8 @@ typedef struct _i2s_config
 /*! @brief Buffer to transfer from or receive audio data into. */
 typedef struct _i2s_transfer
 {
-    volatile uint8_t *data;   /*!< Pointer to data buffer. */
-    volatile size_t dataSize; /*!< Buffer size in bytes. */
+    uint8_t *data;   /*!< Pointer to data buffer. */
+    size_t dataSize; /*!< Buffer size in bytes. */
 } i2s_transfer_t;

 /*! @brief Transactional state of the intialized transfer or receive I2S operation. */
@@ -136,20 +136,21 @@ typedef void (*i2s_transfer_callback_t)(I2S_Type *base,
 /*! @brief Members not to be accessed / modified outside of the driver. */
 struct _i2s_handle
 {
-    uint32_t state;                             /*!< State of transfer */
+    volatile uint32_t state;                    /*!< State of transfer */
    i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */
    void *userData;                             /*!< Application data passed to callback */
    bool oneChannel;                            /*!< true mono, false stereo */
    uint8_t dataLength;                         /*!< Data length (4 - 32) */
-    bool pack48;     /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
-                        values) */
-    bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
+    bool pack48;       /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit
+                          values) */
+    uint8_t watermark; /*!< FIFO trigger level */
+    bool useFifo48H;   /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */
+
    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
    volatile uint32_t errorCount;                      /*!< Number of buffer underruns/overruns */
    volatile uint32_t transferCount;                   /*!< Number of bytes transferred */
-    volatile uint8_t watermark;                        /*!< FIFO trigger level */
 };

 /*******************************************************************************
@@ -277,6 +278,18 @@ void I2S_RxGetDefaultConfig(i2s_config_t *config);
 */
 void I2S_Deinit(I2S_Type *base);

+/*!
+ * @brief Transmitter/Receiver bit clock rate configurations.
+ *
+ * @param base SAI base pointer.
+ * @param sourceClockHz bit clock source frequency.
+ * @param sampleRate audio data sample rate.
+ * @param bitWidth audio data bitWidth.
+ * @param channelNumbers audio channel numbers.
+ */
+void I2S_SetBitClockRate(
+    I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
+
 /*! @} */

 /*!
@@ -404,6 +417,10 @@ void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChanne
 */
 static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel)
 {
+#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn
+    assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1);
+#endif
+
    base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK;
 }
 #endif
@@ -461,6 +478,14 @@ static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base)
    return base->FIFOINTENSET;
 }

+/*!
+ * @brief Flush the valid data in TX fifo.
+ *
+ * @param base I2S base pointer.
+ * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success.
+ */
+status_t I2S_EmptyTxFifo(I2S_Type *base);
+
 /*!
 * @brief Invoked from interrupt handler when transmit FIFO level decreases.
 *
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -26,8 +26,8 @@

 /*! @name Driver version */
 /*@{*/
-/*! @brief I2S DMA driver version 2.1.0. */
-#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief I2S DMA driver version 2.3.1. */
+#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
 /*@}*/

 /*! @brief Members not to be accessed / modified outside of the driver. */
@@ -56,6 +56,9 @@ struct _i2s_dma_handle
    volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */
    volatile uint8_t queueUser;                        /*!< Queue index where user's next transfer will be stored */
    volatile uint8_t queueDriver;                      /*!< Queue index of buffer actually used by the driver */
+
+    dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */
+    size_t i2sLoopDMADescriptorNum;         /*!< number of descriptor in descriptors pool */
 };

 /*******************************************************************************
@@ -151,6 +154,76 @@ status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_
 */
 void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds);

+/*!
+ * @brief Install DMA descriptor memory for loop transfer only.
+ *
+ * This function used to register DMA descriptor memory for the i2s loop dma transfer.
+ *
+ * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after
+ * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA.
+ *
+ * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least.
+ *
+ * @param handle Pointer to i2s DMA transfer handle.
+ * @param dmaDescriptorAddr DMA descriptor start address.
+ * @param dmaDescriptorNum DMA descriptor number.
+ */
+void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle,
+                                                void *dmaDescriptorAddr,
+                                                size_t dmaDescriptorNum);
+
+/*!
+ * @brief Send link transfer data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * This function support loop transfer, such as A->B->...->A, the loop transfer chain
+ * will be converted into a chain of descriptor and submit to dma.
+ * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required,
+ * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory.
+ *
+ * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support
+ * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop
+ * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer.
+ *
+ * @param base I2S peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer I2S DMA transfer structure. See #i2s_transfer_t.
+ * @param loopTransferCount loop count
+ * @retval kStatus_Success
+ */
+status_t I2S_TransferSendLoopDMA(I2S_Type *base,
+                                 i2s_dma_handle_t *handle,
+                                 i2s_transfer_t *xfer,
+                                 uint32_t loopTransferCount);
+
+/*!
+ * @brief Receive link transfer data using DMA.
+ *
+ * This function receives data using DMA. This is a non-blocking function, which returns
+ * right away. When all data is received, the receive callback function is called.
+ *
+ * This function support loop transfer, such as A->B->...->A, the loop transfer chain
+ * will be converted into a chain of descriptor and submit to dma.
+ * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required,
+ * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory.
+ *
+ * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support
+ * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop
+ * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer.
+ *
+ * @param base I2S peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param xfer I2S DMA transfer structure. See #i2s_transfer_t.
+ * @param loopTransferCount loop count
+ * @retval kStatus_Success
+ */
+status_t I2S_TransferReceiveLoopDMA(I2S_Type *base,
+                                    i2s_dma_handle_t *handle,
+                                    i2s_transfer_t *xfer,
+                                    uint32_t loopTransferCount);
+
 /*! @} */

 /*! @} */
@@ -1,5 +1,5 @@
 /*
- * Copyright 2018 NXP
+ * Copyright 2018-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -30,15 +30,15 @@
 #endif

 /*! @brief Flash driver version for SDK*/
-#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
+#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */

 /*! @brief Flash driver version for ROM*/
 enum _flash_driver_version_constants
 {
    kFLASH_DriverVersionName   = 'F', /*!< Flash driver version name.*/
    kFLASH_DriverVersionMajor  = 2,   /*!< Major flash driver version.*/
-    kFLASH_DriverVersionMinor  = 0,   /*!< Minor flash driver version.*/
-    kFLASH_DriverVersionBugfix = 0    /*!< Bugfix for flash driver version.*/
+    kFLASH_DriverVersionMinor  = 1,   /*!< Minor flash driver version.*/
+    kFLASH_DriverVersionBugfix = 3    /*!< Bugfix for flash driver version.*/
 };

 /*@}*/
@@ -61,13 +61,13 @@ enum _flash_driver_version_constants
 */
 /*! @brief Flash driver status group. */
 #if defined(kStatusGroup_FlashDriver)
-#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupGeneric     kStatusGroup_Generic
 #define kStatusGroupFlashDriver kStatusGroup_FlashDriver
 #elif defined(kStatusGroup_FLASHIAP)
-#define kStatusGroupGeneric kStatusGroup_Generic
+#define kStatusGroupGeneric     kStatusGroup_Generic
 #define kStatusGroupFlashDriver kStatusGroup_FLASH
 #else
-#define kStatusGroupGeneric 0
+#define kStatusGroupGeneric     0
 #define kStatusGroupFlashDriver 1
 #endif

@@ -350,12 +350,14 @@ status_t FLASH_Init(flash_config_t *config);
 *
 * @param config The pointer to the storage for the driver runtime state.
 * @param start The start address of the desired flash memory to be erased.
- *              The start address does not need to be sector-aligned.
+ *              The start address need to be 512bytes-aligned.
 * @param lengthInBytes The length, given in bytes (not words or long-words)
- *                      to be erased. Must be word-aligned.
+ *                      to be erased. Must be 512bytes-aligned.
 * @param key The value used to validate all flash erase APIs.
 *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully;
+ *         the appropriate number of flash sectors based on the desired
+ *         start address and length were erased successfully.
 * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
 * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline.
 * @retval #kStatus_FLASH_AddressError The address is out of range.
@@ -381,13 +383,14 @@ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBy
 *
 * @param config A pointer to the storage for the driver runtime state.
 * @param start The start address of the desired flash memory to be programmed. Must be
- *              word-aligned.
+ *              512bytes-aligned.
 * @param src A pointer to the source buffer of data that is to be programmed
 *            into the flash.
 * @param lengthInBytes The length, given in bytes (not words or long-words),
- *                      to be programmed. Must be word-aligned.
+ *                      to be programmed. Must be 512bytes-aligned.
 *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully
+ *         into flash based on desired start address and length.
 * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
 * @retval #kStatus_FLASH_AddressError Address is out of range.
@@ -401,6 +404,31 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uin

 /*@}*/

+/*!
+ * @brief Reads flash at locations passed in through parameters.
+ *
+ * This function read the flash memory from a given flash area as determined
+ * by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be read.
+ * @param dest A pointer to the dest buffer of data that is to be read
+ *            from the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be read.
+ *
+ * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
+ * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
+ * @retval #kStatus_FLASH_AddressError Address is out of range.
+ * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
+ * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
+ * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
+ * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
+ */
+status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes);
+
 /*!
 * @name Verification
 * @{
@@ -415,12 +443,11 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uin
 *
 * @param config A pointer to the storage for the driver runtime state.
 * @param start The start address of the desired flash memory to be verified.
- *        The start address does not need to be sector-aligned but must be word-aligned.
+ *        The start address need to be 512bytes-aligned.
 * @param lengthInBytes The length, given in bytes (not words or long-words),
- *        to be verified. Must be word-aligned.
- * @param margin Read margin choice.
+ *        to be verified. Must be 512bytes-aligned.
 *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased.
 * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
 * @retval #kStatus_FLASH_AddressError Address is out of range.
@@ -440,18 +467,19 @@ status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t leng
 * flash area as determined by the start address and length.
 *
 * @param config A pointer to the storage for the driver runtime state.
- * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned.
 * @param lengthInBytes The length, given in bytes (not words or long-words),
- *        to be verified. Must be word-aligned.
+ *        to be verified. need be 512bytes-aligned.
 * @param expectedData A pointer to the expected data that is to be
 *        verified against.
- * @param margin Read margin choice.
 * @param failedAddress A pointer to the returned failing address.
 * @param failedData A pointer to the returned failing data.  Some derivatives do
 *        not include failed data as part of the FCCOBx registers.  In this
 *        case, zeros are returned upon failure.
 *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully;
+ *         the desired data have been successfully programed into specified FLASH region.
+ *
 * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
 * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
 * @retval #kStatus_FLASH_AddressError Address is out of range.
@@ -483,7 +511,7 @@ status_t FLASH_VerifyProgram(flash_config_t *config,
 *        enum flash_property_tag_t
 * @param value A pointer to the value returned for the desired flash property.
 *
- * @retval #kStatus_FLASH_Success API was executed successfully.
+ * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value.
 * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
 * @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
 */
@@ -495,4 +523,6 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro
 }
 #endif

+/*@}*/
+
 #endif /* __FLASH_FLASH_H_ */
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_
+#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup skboot_authenticate
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @brief SKBOOT return status*/
+typedef enum _skboot_status
+{
+    kStatus_SKBOOT_Success               = 0x5ac3c35au, /*!< SKBOOT return success status.*/
+    kStatus_SKBOOT_Fail                  = 0xc35ac35au, /*!< SKBOOT return fail status.*/
+    kStatus_SKBOOT_InvalidArgument       = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/
+    kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/
+    kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess =
+        0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/
+    kStatus_SKBOOT_HashcryptFinishedWithStatusFail =
+        0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/
+} skboot_status_t;
+
+/*! @brief Secure bool flag*/
+typedef enum _secure_bool
+{
+    kSECURE_TRUE                       = 0xc33cc33cU, /*!< Secure true flag.*/
+    kSECURE_FALSE                      = 0x5aa55aa5U, /*!< Secure false flag.*/
+    kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/
+    kSECURE_CALLPROTECT_IS_APP_READY   = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/
+    kSECURE_TRACKER_VERIFIED           = 0x55aacc33U, /*!< Secure tracker verified flag.*/
+} secure_bool_t;
+
+/*******************************************************************************
+ * Externs
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Authenticate entry function with ARENA allocator init
+ *
+ * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface
+ */
+skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified);
+
+/*!
+ * @brief Interface for image authentication API
+ */
+void HASH_IRQHandler(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ *@}
+ */
+
+#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -61,9 +61,9 @@ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connect
    /* extract pmux to be used */
    pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT;
    /*  extract function number */
-    output_id = ((uint32_t)(connection)) & 0xffffU;
+    output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U);
    /* programm signal */
-    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id;
+    *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id;
 }

 #if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA)
@@ -81,20 +81,34 @@ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connect
 void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable)
 {
    uint32_t ena_id;
+    uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U;
    uint32_t bit_offset;

+#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX
+    uint32_t chmux_offset;
+    uint32_t chmux_value;
+
+    /* Only enable need to update channel mux */
+    if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U))
+    {
+        chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL);
+        chmux_value  = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL);
+        *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value;
+    }
+    ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U;
+#endif
    /* extract enable register to be used */
-    ena_id = ((uint32_t)(signal)) >> ENA_SHIFT;
+    ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask;
    /* extract enable bit offset */
-    bit_offset = ((uint32_t)(signal)) & 0xfU;
+    bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U);
    /* set signal */
    if (enable)
    {
-        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset);
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset);
    }
    else
    {
-        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset);
+        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset);
    }
 }
 #endif
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2021 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -27,8 +27,8 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Group interrupt driver version for SDK */
-#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-                                                            /*@}*/
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/

 /*******************************************************************************
 * API
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -69,7 +69,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)

 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
    /* Enable the clock for LPADC instance. */
-    CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
+    (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

    /* Reset the module. */
@@ -119,7 +119,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
    tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay)                /* Power up delay. */
             | ADC_CFG_REFSEL(config->referenceVoltageSource)   /* Reference voltage. */
             | ADC_CFG_PWRSEL(config->powerLevelMode)           /* Power configuration. */
-             | ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */
+             | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */
    base->CFG = tmp32;

    /* ADCx_PAUSE. */
@@ -157,7 +157,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
 *   config->powerUpDelay            = 0x80;
 *   config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
 *   config->powerLevelMode          = kLPADC_PowerLevelAlt1;
- *   config->triggerPrioirtyPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
+ *   config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
 *   config->enableConvPause         = false;
 *   config->convPauseDelay          = 0U;
 *   config->FIFO0Watermark          = 0U;
@@ -169,7 +169,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
 void LPADC_GetDefaultConfig(lpadc_config_t *config)
 {
    /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));

 #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
    config->enableInternalClock = false;
@@ -186,7 +186,7 @@ void LPADC_GetDefaultConfig(lpadc_config_t *config)
    config->powerUpDelay            = 0x80;
    config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
    config->powerLevelMode          = kLPADC_PowerLevelAlt1;
-    config->triggerPrioirtyPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
+    config->triggerPriorityPolicy   = kLPADC_TriggerPriorityPreemptImmediately;
    config->enableConvPause         = false;
    config->convPauseDelay          = 0U;
 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
@@ -209,7 +209,7 @@ void LPADC_Deinit(ADC_Type *base)

 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
    /* Gate the clock. */
-    CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
+    (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }

@@ -294,7 +294,10 @@ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_
            | ADC_TCTRL_TDLY(config->delayPower)    /* Trigger delay select. */
            | ADC_TCTRL_TPRI(config->priority)      /* Trigger priority setting. */
 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
-            | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect)
+            | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect)
+#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B)
+            | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect)
+#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B  */
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
        ;
    if (config->enableHardwareTrigger)
@@ -324,12 +327,12 @@ void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
    assert(config != NULL); /* Check if the input pointer is available. */

    /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));

    config->targetCommandId = 0U;
    config->delayPower      = 0U;
    config->priority        = 0U;
-#if defined(FSL_FEATURE_LPADC_FIFO_COUNT) && FSL_FEATURE_LPADC_FIFO_COUNT
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
    config->channelAFIFOSelect = 0U;
    config->channelBFIFOSelect = 0U;
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
@@ -378,7 +381,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
    }
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
-    tmp32 |= ADC_CMDL_MODE(config->conversionResoultuionMode);
+    tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode);
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
    base->CMD[commandId].CMDL = tmp32;

@@ -433,7 +436,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
 *   config->hardwareCompareMode        = kLPADC_HardwareCompareDisabled;
 *   config->hardwareCompareValueHigh   = 0U;
 *   config->hardwareCompareValueLow    = 0U;
- *   config->conversionResoultuionMode  = kLPADC_ConversionResolutionStandard;
+ *   config->conversionResolutionMode  = kLPADC_ConversionResolutionStandard;
 *   config->enableWaitTrigger          = false;
 * endcode
 * param config Pointer to configuration structure.
@@ -443,7 +446,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
    assert(config != NULL); /* Check if the input pointer is available. */

    /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));

 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
    config->sampleScaleMode = kLPADC_SampleFullScale;
@@ -459,7 +462,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
    config->hardwareCompareValueHigh   = 0U; /* No used. */
    config->hardwareCompareValueLow    = 0U; /* No used. */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
-    config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
+    config->conversionResolutionMode = kLPADC_ConversionResolutionStandard;
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
    config->enableWaitTrigger = false;
@@ -477,7 +480,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
 * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
 *
 * param base LPADC peripheral base address.
- * bool enable switcher to the calibration function.
+ * param enable switcher to the calibration function.
 */
 void LPADC_EnableCalibration(ADC_Type *base, bool enable)
 {
@@ -539,7 +542,7 @@ void LPADC_DoAutoCalibration(ADC_Type *base)
    {
    }
    /* The valid bits of data are bits 14:3 in the RESFIFO register. */
-    LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U);
+    LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL);
    /* Disable the calibration function. */
    LPADC_EnableCalibration(base, false);

@@ -1,7 +1,6 @@
 /*
- * Copyright 2014, NXP
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2018 NXP
+ * Copyright 2016-2019 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -30,8 +29,8 @@

 /*! @name Driver version */
 /*@{*/
-/*! @brief MAILBOX driver version 2.1.0. */
-#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief MAILBOX driver version 2.2.0. */
+#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/

 /*!
@@ -43,13 +42,25 @@ typedef enum _mailbox_cpu_id
    kMAILBOX_CM33_Core1 = 0,
    kMAILBOX_CM33_Core0
 } mailbox_cpu_id_t;
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
 typedef enum _mailbox_cpu_id
 {
    kMAILBOX_CM0Plus = 0,
    kMAILBOX_CM4
 } mailbox_cpu_id_t;
 #endif
+
+#if (defined(CPU_NXH2004J640UK48))
+typedef enum _mailbox_id
+{
+    kMAILBOX_CM0Plus_Core0 = 0,
+    kMAILBOX_CM0Plus_Core1,
+    kMAILBOX_CM0Plus_Sw_Irq0,
+    kMAILBOX_CM0Plus_Sw_Irq1,
+    kMAILBOX_CM0Plus_Sw_Irq2,
+    kMAILBOX_CM0Plus_Sw_Irq3
+} mailbox_id_t;
+#endif
 /*******************************************************************************
 * API
 ******************************************************************************/
@@ -97,6 +108,8 @@ static inline void MAILBOX_Deinit(MAILBOX_Type *base)

 /* @} */

+#if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \
+     (defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
 /*!
 * @brief Set data value in the mailbox based on the CPU ID.
 *
@@ -111,7 +124,7 @@ static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id,
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
    assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
    base->MBOXIRQ[cpu_id].IRQ = mboxData;
@@ -130,7 +143,7 @@ static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
    assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
    return base->MBOXIRQ[cpu_id].IRQ;
@@ -151,7 +164,7 @@ static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
    assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
    base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits;
@@ -172,12 +185,76 @@ static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t c
 {
 #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
    assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1));
-#else
+#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES)))
    assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4));
 #endif
    base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits;
 }

+#elif (defined(CPU_NXH2004J640UK48))
+
+/*!
+ * @brief Set data value in the mailbox based on the Mailbox ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id Mailbox Index for NXH2004 devices
+ * @param mboxData Data to send in the mailbox.
+ *
+ */
+static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxData)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    base->MBOXIRQ[id].IRQ = mboxData;
+}
+
+/*!
+ * @brief Get data in the mailbox based on the Mailbox ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id, Mailbox index for NXH2004 devies.
+ *
+ * @return Current mailbox data.
+ */
+static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_id_t id)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    return base->MBOXIRQ[id].IRQ;
+}
+
+/*!
+ * @brief Set data bits in the mailbox based on the Mailbox Index.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id Mailbox Index for NXH2004 devices
+ * @param mboxSetBits Data bits to set in the mailbox.
+ *
+ * @note Sets data bits to send via the MAILBOX. A value of 0 will
+ * do nothing. Only sets bits selected with a 1 in it's bit position.
+ */
+static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxSetBits)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    base->MBOXIRQ[id].IRQSET = mboxSetBits;
+}
+
+/*!
+ * @brief Clear data bits in the mailbox based on the Mailbox ID.
+ *
+ * @param base MAILBOX peripheral base address.
+ * @param id, Index to Mailbox for NXH2004 devices.
+ * @param mboxClrBits Data bits to clear in the mailbox.
+ *
+ * @note Clear data bits to send via the MAILBOX. A value of 0 will do
+ * nothing. Only clears bits selected with a 1 in it's bit position.
+ */
+static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxClrBits)
+{
+    assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3));
+    base->MBOXIRQ[id].IRQCLR = mboxClrBits;
+}
+
+#endif /*CPU_NXH2004J640UK48*/
+
 /*!
 * @brief Get MUTEX state and lock mutex
 *
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -37,10 +37,10 @@ static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
-#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET
+#if defined(MRT_RSTS_N)
 /*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */
 static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N;
-#else
+#elif defined(MRT_RSTS)
 /*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */
 static const reset_ip_name_t s_mrtResets[] = MRT_RSTS;
 #endif
@@ -79,7 +79,7 @@ static uint32_t MRT_GetInstance(MRT_Type *base)
 */
 void MRT_Init(MRT_Type *base, const mrt_config_t *config)
 {
-    assert(config);
+    assert(config != NULL);

 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
    /* Ungate the MRT clock */
@@ -87,8 +87,10 @@ void MRT_Init(MRT_Type *base, const mrt_config_t *config)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */

 #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
+#if defined(MRT_RSTS_N) || defined(MRT_RSTS)
    /* Reset the module. */
    RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]);
+#endif
 #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */

 #if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK)
@@ -136,10 +138,10 @@ void MRT_Deinit(MRT_Type *base)
 */
 void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);

    uint32_t newValue = count;
-    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad))
+    if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad))
    {
        /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */
        newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK;
@@ -1,6 +1,6 @@
 /*
 * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2020 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
@@ -23,7 +23,7 @@

 /*! @name Driver version */
 /*@{*/
-#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
+#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */
 /*@}*/

 /*! @brief List of MRT channels */
@@ -112,7 +112,7 @@ void MRT_Deinit(MRT_Type *base);
 */
 static inline void MRT_GetDefaultConfig(mrt_config_t *config)
 {
-    assert(config);
+    assert(config != NULL);
 #if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK)
    /* Use hardware status operating mode */
    config->enableMultiTask = false;
@@ -128,14 +128,14 @@ static inline void MRT_GetDefaultConfig(mrt_config_t *config)
 */
 static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);

    uint32_t reg = base->CHANNEL[channel].CTRL;

    /* Clear old value */
    reg &= ~MRT_CHANNEL_CTRL_MODE_MASK;
    /* Add the new mode */
-    reg |= mode;
+    reg |= (uint32_t)mode;

    base->CHANNEL[channel].CTRL = reg;
 }
@@ -157,7 +157,7 @@ static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, cons
 */
 static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
    base->CHANNEL[channel].CTRL |= mask;
 }

@@ -171,7 +171,7 @@ static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint
 */
 static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
    base->CHANNEL[channel].CTRL &= ~mask;
 }

@@ -186,7 +186,7 @@ static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uin
 */
 static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
    return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK);
 }

@@ -208,7 +208,7 @@ static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t chann
 */
 static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
    return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK));
 }

@@ -222,7 +222,7 @@ static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel)
 */
 static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
    base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK);
 }

@@ -264,7 +264,7 @@ void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, b
 */
 static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
    return base->CHANNEL[channel].TIMER;
 }

@@ -285,12 +285,12 @@ static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t chann
 *
 * @param base    Multi-Rate timer peripheral base address
 * @param channel Timer channel number.
- * @param count   Timer period in units of ticks
+ * @param count   Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature.
 */
 static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
-    assert(count < MRT_CHANNEL_INTVAL_IVALUE_MASK);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK);
    /* Write the timer interval value */
    base->CHANNEL[channel].INTVAL = count;
 }
@@ -305,7 +305,7 @@ static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t c
 */
 static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
    /* Stop the timer immediately */
    base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK;
 }
@@ -343,7 +343,7 @@ static inline uint32_t MRT_GetIdleChannel(MRT_Type *base)
 */
 static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel)
 {
-    assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);
+    assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS);

    uint32_t reg = base->CHANNEL[channel].STAT;