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[bsp][lpc55sxx] update NXP SDK to 2_12_0

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update NXP SDK to 2_12_0
This commit is contained in:
yandld
2022-11-27 15:25:35 +08:00
committed by Man, Jianting (Meco)
parent 83d3b3ed62
commit 6c5f9ffb0a
293 changed files with 88210 additions and 67512 deletions
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600
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armcc.h
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1503
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang.h Normal file
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1433
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armclang.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang_ltm.h
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29
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_compiler.h
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@@ -1,8 +1,8 @@
/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
* @version V5.1.0
* @date 09. October 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
@@ -35,9 +35,15 @@
/*
* Arm Compiler 6 (armclang)
* Arm Compiler 6.6 LTM (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
#include "cmsis_armclang_ltm.h"
/*
* Arm Compiler above 6.10.1 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
#include "cmsis_armclang.h"
@@ -115,8 +121,11 @@
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
@@ -187,6 +196,10 @@
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
/*
@@ -255,6 +268,10 @@
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#ifndef __COMPILER_BARRIER
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
#define __COMPILER_BARRIER() (void)0
#endif
#else

1621
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_gcc.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_gcc.h
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143
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_iccarm.h
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@@ -1,13 +1,16 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.5
* @date 10. January 2018
* @version V5.3.0
* @date 14. April 2021
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
// Copyright (c) 2017-2021 IAR Systems
// Copyright (c) 2017-2021 Arm Limited. All rights reserved.
//
// SPDX-License-Identifier: Apache-2.0
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
@@ -110,6 +113,10 @@
#define __ASM __asm
#endif
#ifndef __COMPILER_BARRIER
#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
@@ -150,7 +157,12 @@
#endif
#ifndef __RESTRICT
#define __RESTRICT restrict
#if __ICCARM_V8
#define __RESTRICT __restrict
#else
/* Needs IAR language extensions */
#define __RESTRICT restrict
#endif
#endif
#ifndef __STATIC_INLINE
@@ -226,6 +238,7 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#endif
#undef __WEAK /* undo the definition from DLib_Defaults.h */
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
@@ -234,6 +247,43 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#endif
#ifndef __PROGRAM_START
#define __PROGRAM_START __iar_program_start
#endif
#ifndef __INITIAL_SP
#define __INITIAL_SP CSTACK$$Limit
#endif
#ifndef __STACK_LIMIT
#define __STACK_LIMIT CSTACK$$Base
#endif
#ifndef __VECTOR_TABLE
#define __VECTOR_TABLE __vector_table
#endif
#ifndef __VECTOR_TABLE_ATTRIBUTE
#define __VECTOR_TABLE_ATTRIBUTE @".intvec"
#endif
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#ifndef __STACK_SEAL
#define __STACK_SEAL STACKSEAL$$Base
#endif
#ifndef __TZ_STACK_SEAL_SIZE
#define __TZ_STACK_SEAL_SIZE 8U
#endif
#ifndef __TZ_STACK_SEAL_VALUE
#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL
#endif
__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) {
*((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE;
}
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
@@ -305,7 +355,13 @@ __packed struct __iar_u32 { uint32_t v; };
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
{
__arm_wsr("CONTROL", control);
__iar_builtin_ISB();
}
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
@@ -327,7 +383,13 @@ __packed struct __iar_u32 { uint32_t v; };
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
{
__arm_wsr("CONTROL_NS", control);
__iar_builtin_ISB();
}
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
@@ -340,8 +402,17 @@ __packed struct __iar_u32 { uint32_t v; };
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
@@ -558,7 +629,7 @@ __packed struct __iar_u32 { uint32_t v; };
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
__ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
return(result);
}
@@ -640,6 +711,7 @@ __packed struct __iar_u32 { uint32_t v; };
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
__iar_builtin_ISB();
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
@@ -716,12 +788,25 @@ __packed struct __iar_u32 { uint32_t v; };
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
@@ -784,37 +869,37 @@ __packed struct __iar_u32 { uint32_t v; };
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
__ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
__ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
__ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
__ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
__ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
__ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
@@ -826,78 +911,78 @@ __packed struct __iar_u32 { uint32_t v; };
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory");
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory");
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory");
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
@@ -910,4 +995,8 @@ __packed struct __iar_u32 { uint32_t v; };
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
#endif /* __CMSIS_ICCARM_H__ */

8
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_version.h
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@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
* @version V5.0.4
* @date 23. July 2019
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -33,7 +33,7 @@
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

832
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_cm33.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/core_cm33.h
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69
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/mpu_armv8.h
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@@ -1,11 +1,11 @@
/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
* @version V5.1.3
* @date 03. February 2021
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
@@ -44,7 +44,7 @@
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
@@ -62,7 +62,7 @@
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
@@ -77,7 +77,7 @@
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
@@ -87,20 +87,35 @@
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Pos) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
(((BASE) & MPU_RBAR_BASE_Msk) | \
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#if defined(MPU_RLAR_PXN_Pos)
/** \brief Region Limit Address Register with PXN value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
#endif
/**
* Struct for a single MPU Region
*/
@@ -114,24 +129,26 @@ typedef struct {
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
__DMB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#ifdef MPU_NS
@@ -140,24 +157,26 @@ __STATIC_INLINE void ARM_MPU_Disable(void)
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
__DMB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
__DSB();
__ISB();
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
__DMB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
__DSB();
__ISB();
}
#endif
@@ -262,12 +281,12 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
@@ -287,7 +306,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
@@ -295,7 +314,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
@@ -303,7 +322,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}

0
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/tz_context.h → bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/tz_context.h
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121
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h
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@@ -1,121 +0,0 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoef_16_q31[24];
extern const q31_t twiddleCoef_32_q31[48];
extern const q31_t twiddleCoef_64_q31[96];
extern const q31_t twiddleCoef_128_q31[192];
extern const q31_t twiddleCoef_256_q31[384];
extern const q31_t twiddleCoef_512_q31[768];
extern const q31_t twiddleCoef_1024_q31[1536];
extern const q31_t twiddleCoef_2048_q31[3072];
extern const q31_t twiddleCoef_4096_q31[6144];
extern const q15_t twiddleCoef_16_q15[24];
extern const q15_t twiddleCoef_32_q15[48];
extern const q15_t twiddleCoef_64_q15[96];
extern const q15_t twiddleCoef_128_q15[192];
extern const q15_t twiddleCoef_256_q15[384];
extern const q15_t twiddleCoef_512_q15[768];
extern const q15_t twiddleCoef_1024_q15[1536];
extern const q15_t twiddleCoef_2048_q15[3072];
extern const q15_t twiddleCoef_4096_q15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
/* Tables for Fast Math Sine and Cosine */
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
#endif /* ARM_COMMON_TABLES_H */

66
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h
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@@ -1,66 +0,0 @@
/* ----------------------------------------------------------------------
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
#endif

7160
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h
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1896
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h
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2960
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h
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74
bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h
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@@ -1,74 +0,0 @@
/**************************************************************************//**
* @file cmsis_xcc.h
* @brief CMSIS DSP Core Peripheral Access Layer Header File
* @version V1.0
* @date 20. January 2019
******************************************************************************/
/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CORE_DSP_H_GENERIC
#define __CORE_DSP_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
#define __STATIC_INLINE static inline
#define __BKPT(value) do {} while(0)
#define __NOP() do {} while(0)
#define NVIC_SetPriorityGrouping(value) do {} while(0)
#define NVIC_GetPriorityGrouping() do {} while(0)
#define NVIC_EnableIRQ(value) do {} while(0)
#define NVIC_GetEnableIRQ(value) do {} while(0)
#define NVIC_DisableIRQ(value) do {} while(0)
#define NVIC_GetPendingIRQ(value) do {} while(0)
#define NVIC_SetPendingIRQ(value) do {} while(0)
#define NVIC_ClearPendingIRQ(value) do {} while(0)
#define NVIC_GetActive(value) do {} while(0)
#ifdef __cplusplus
}
#endif
#endif /* __CORE_DSP_H_GENERIC */

13337
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h
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12015
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml
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188
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h
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@@ -1,13 +1,13 @@
/*
** ###################################################################
** Version: rev. 1.0, 2018-08-22
** Build: b190418
** Version: rev. 1.1, 2019-05-16
** Build: b220303
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -18,6 +18,8 @@
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
** - rev. 1.1 (2019-05-16)
** Initial A1 version based on v1.3UM
**
** ###################################################################
*/
@@ -73,7 +75,7 @@
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
/* @brief PUF availability on the SoC. */
#define FSL_FEATURE_SOC_PUF_COUNT (1)
/* @brief RNG1 availability on the SoC. */
/* @brief LPC_RNG1 availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
@@ -136,18 +138,66 @@
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
/* @brief Has offset trim (register OFSTRIM). */
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
/* @brief Has Trigger status register. */
#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
/* @brief Has power select (bitfield CFG[PWRSEL]). */
#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
/* @brief Conversion averaged bitfiled width. */
#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
/* @brief Has internal temperature sensor. */
#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
/* @brief Temperature sensor parameter A (slope). */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
/* @brief Temperature sensor parameter B (offset). */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
/* @brief Temperature sensor parameter Alpha. */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
/* @brief the buffer size of temperature sensor. */
#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
/* ANALOGCTRL module features */
/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)
/* @brief Has auxiliary bias(register AUX_BIAS). */
#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)
/* CASPER module features */
/* @brief Base address of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
/* @brief Interleaving of the CASPER dedicated RAM */
/* @brief SW interleaving of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
/* @brief CASPER dedicated RAM offset */
#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
/* CTIMER module features */
/* @brief CTIMER has no capture channel. */
#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
/* @brief CTIMER has no capture 2 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
/* @brief CTIMER capture 3 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
/* @brief Align size of DMA descriptor */
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
/* @brief DMA head link descriptor table align size */
@@ -155,6 +205,72 @@
/* FLEXCOMM module features */
/* @brief FLEXCOMM0 USART INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
/* @brief FLEXCOMM0 SPI INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
/* @brief FLEXCOMM0 I2C INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
/* @brief FLEXCOMM0 I2S INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
/* @brief FLEXCOMM1 USART INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
/* @brief FLEXCOMM1 SPI INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
/* @brief FLEXCOMM1 I2C INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
/* @brief FLEXCOMM1 I2S INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
/* @brief FLEXCOMM2 USART INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
/* @brief FLEXCOMM2 SPI INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
/* @brief FLEXCOMM2 I2C INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
/* @brief FLEXCOMM2 I2S INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
/* @brief FLEXCOMM3 USART INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
/* @brief FLEXCOMM3 SPI INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
/* @brief FLEXCOMM3 I2C INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
/* @brief FLEXCOMM3 I2S INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
/* @brief FLEXCOMM4 USART INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
/* @brief FLEXCOMM4 SPI INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
/* @brief FLEXCOMM4 I2C INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
/* @brief FLEXCOMM4 I2S INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
/* @brief FLEXCOMM5 USART INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
/* @brief FLEXCOMM5 SPI INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
/* @brief FLEXCOMM5 I2C INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
/* @brief FLEXCOMM5 I2S INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
/* @brief FLEXCOMM6 USART INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
/* @brief FLEXCOMM6 SPI INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
/* @brief FLEXCOMM6 I2C INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
/* @brief FLEXCOMM6 I2S INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
/* @brief FLEXCOMM7 USART INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
/* @brief FLEXCOMM7 SPI INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
/* @brief FLEXCOMM7 I2C INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
/* @brief FLEXCOMM7 I2S INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
@@ -166,9 +282,9 @@
/* I2S module features */
/* @brief I2S support dual channel transfer. */
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
/* @brief I2S has DMIC interconnection. */
#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
/* IOCON module features */
@@ -190,10 +306,22 @@
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
/* PLU module features */
/* @brief Has WAKEINT_CTRL register. */
#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
/* PMC module features */
/* @brief UTICK does not support PD configure. */
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
/* @brief WDT OSC does not support PD configure. */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
/* POWERLIB module features */
/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */
#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1)
/* @brief Powerlib API is different with other LPC series devices. */
#define FSL_FEATURE_POWERLIB_EXTEND (1)
/* POWERQUAD module features */
@@ -207,6 +335,10 @@
/* @brief the shift status value */
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
/* RTC module features */
/* No feature definitions */
/* SCT module features */
/* @brief Number of events */
@@ -221,13 +353,13 @@
/* SDIF module features */
/* @brief FIFO depth, every location is a WORD */
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
/* @brief Max DMA buffer size */
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
/* @brief Max source clock in HZ */
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
/* @brief support 2 cards */
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
/* SECPINT module features */
@@ -236,18 +368,22 @@
/* SYSCON module features */
/* @brief Pointer to ROM IAP entry functions */
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
/* @brief Flash page size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
/* @brief Flash sector size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
/* @brief Flash size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120)
/* @brief Has Power Down mode */
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
/* @brief Starter register discontinuous. */
#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
/* SYSCTL1 module features */
/* No feature definitions */
/* USB module features */
@@ -289,17 +425,23 @@
/* @brief USBHSH version */
#define FSL_FEATURE_USBHSH_VERSION (300)
/* UTICK module features */
/* USBPHY module features */
/* @brief UTICK does not support PD configure. */
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSD version */
#define FSL_FEATURE_USBPHY_VERSION (300)
/* @brief Number of the endpoint in USB HS */
#define FSL_FEATURE_USBPHY_EP_NUM (6)
/* WWDT module features */
/* @brief Has no RESET register. */
#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
/* @brief WWDT does not support oscillator lock. */
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
/* @brief WWDT does not support power down configure */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */

13336
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h
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File diff suppressed because it is too large Load Diff

12015
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml
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File diff suppressed because it is too large Load Diff

188
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h
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@@ -1,13 +1,13 @@
/*
** ###################################################################
** Version: rev. 1.0, 2018-08-22
** Build: b190418
** Version: rev. 1.1, 2019-05-16
** Build: b220303
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -18,6 +18,8 @@
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
** - rev. 1.1 (2019-05-16)
** Initial A1 version based on v1.3UM
**
** ###################################################################
*/
@@ -73,7 +75,7 @@
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
/* @brief PUF availability on the SoC. */
#define FSL_FEATURE_SOC_PUF_COUNT (1)
/* @brief RNG1 availability on the SoC. */
/* @brief LPC_RNG1 availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
@@ -136,18 +138,66 @@
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
/* @brief Has offset trim (register OFSTRIM). */
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
/* @brief Has Trigger status register. */
#define FSL_FEATURE_LPADC_HAS_TSTAT (1)
/* @brief Has power select (bitfield CFG[PWRSEL]). */
#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1)
/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0)
/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0)
/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0)
/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
/* @brief Conversion averaged bitfiled width. */
#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3)
/* @brief Has internal temperature sensor. */
#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
/* @brief Temperature sensor parameter A (slope). */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f)
/* @brief Temperature sensor parameter B (offset). */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f)
/* @brief Temperature sensor parameter Alpha. */
#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f)
/* @brief the buffer size of temperature sensor. */
#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U)
/* ANALOGCTRL module features */
/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */
#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1)
/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */
#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0)
/* @brief Has auxiliary bias(register AUX_BIAS). */
#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1)
/* CASPER module features */
/* @brief Base address of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
/* @brief Interleaving of the CASPER dedicated RAM */
/* @brief SW interleaving of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
/* @brief CASPER dedicated RAM offset */
#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE)
/* CTIMER module features */
/* @brief CTIMER has no capture channel. */
#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0)
/* @brief CTIMER has no capture 2 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0)
/* @brief CTIMER capture 3 interrupt. */
#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1)
/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */
#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23)
/* @brief Align size of DMA descriptor */
#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
/* @brief DMA head link descriptor table align size */
@@ -155,6 +205,72 @@
/* FLEXCOMM module features */
/* @brief FLEXCOMM0 USART INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0)
/* @brief FLEXCOMM0 SPI INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0)
/* @brief FLEXCOMM0 I2C INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0)
/* @brief FLEXCOMM0 I2S INDEX 0 */
#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0)
/* @brief FLEXCOMM1 USART INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1)
/* @brief FLEXCOMM1 SPI INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1)
/* @brief FLEXCOMM1 I2C INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1)
/* @brief FLEXCOMM1 I2S INDEX 1 */
#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1)
/* @brief FLEXCOMM2 USART INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2)
/* @brief FLEXCOMM2 SPI INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2)
/* @brief FLEXCOMM2 I2C INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2)
/* @brief FLEXCOMM2 I2S INDEX 2 */
#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2)
/* @brief FLEXCOMM3 USART INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3)
/* @brief FLEXCOMM3 SPI INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3)
/* @brief FLEXCOMM3 I2C INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3)
/* @brief FLEXCOMM3 I2S INDEX 3 */
#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3)
/* @brief FLEXCOMM4 USART INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4)
/* @brief FLEXCOMM4 SPI INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4)
/* @brief FLEXCOMM4 I2C INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4)
/* @brief FLEXCOMM4 I2S INDEX 4 */
#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4)
/* @brief FLEXCOMM5 USART INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5)
/* @brief FLEXCOMM5 SPI INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5)
/* @brief FLEXCOMM5 I2C INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5)
/* @brief FLEXCOMM5 I2S INDEX 5 */
#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5)
/* @brief FLEXCOMM6 USART INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6)
/* @brief FLEXCOMM6 SPI INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6)
/* @brief FLEXCOMM6 I2C INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6)
/* @brief FLEXCOMM6 I2S INDEX 6 */
#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6)
/* @brief FLEXCOMM7 USART INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7)
/* @brief FLEXCOMM7 SPI INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7)
/* @brief FLEXCOMM7 I2C INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7)
/* @brief FLEXCOMM7 I2S INDEX 7 */
#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7)
/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */
#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8)
/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0)
@@ -166,9 +282,9 @@
/* I2S module features */
/* @brief I2S support dual channel transfer. */
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
/* @brief I2S has DMIC interconnection. */
#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0)
/* @brief I2S has DMIC interconnection */
#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0)
/* IOCON module features */
@@ -190,10 +306,22 @@
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
/* PLU module features */
/* @brief Has WAKEINT_CTRL register. */
#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1)
/* PMC module features */
/* @brief UTICK does not support PD configure. */
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
/* @brief WDT OSC does not support PD configure. */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
/* POWERLIB module features */
/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */
#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1)
/* @brief Powerlib API is different with other LPC series devices. */
#define FSL_FEATURE_POWERLIB_EXTEND (1)
/* POWERQUAD module features */
@@ -207,6 +335,10 @@
/* @brief the shift status value */
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
/* RTC module features */
/* No feature definitions */
/* SCT module features */
/* @brief Number of events */
@@ -221,13 +353,13 @@
/* SDIF module features */
/* @brief FIFO depth, every location is a WORD */
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
/* @brief Max DMA buffer size */
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
/* @brief Max source clock in HZ */
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
/* @brief support 2 cards */
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
/* SECPINT module features */
@@ -236,18 +368,22 @@
/* SYSCON module features */
/* @brief Pointer to ROM IAP entry functions */
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
/* @brief Flash page size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
/* @brief Flash sector size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
/* @brief Flash size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120)
/* @brief Has Power Down mode */
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
/* @brief Starter register discontinuous. */
#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1)
/* SYSCTL1 module features */
/* No feature definitions */
/* USB module features */
@@ -289,17 +425,23 @@
/* @brief USBHSH version */
#define FSL_FEATURE_USBHSH_VERSION (300)
/* UTICK module features */
/* USBPHY module features */
/* @brief UTICK does not support PD configure. */
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSD version */
#define FSL_FEATURE_USBPHY_VERSION (300)
/* @brief Number of the endpoint in USB HS */
#define FSL_FEATURE_USBPHY_EP_NUM (6)
/* WWDT module features */
/* @brief Has no RESET register. */
#define FSL_FEATURE_WWDT_HAS_NO_RESET (1)
/* @brief WWDT does not support oscillator lock. */
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
/* @brief WWDT does not support power down configure */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */

25
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf
View File

@@ -2,18 +2,19 @@
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JET98_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181008
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b210928
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -47,7 +48,7 @@
#define m_text_size 0x00071E00
#define m_core1_image_start 0x00072000
#define m_core1_image_size 0x00026000
#define m_core1_image_size 0x0002B800
#if (defined(__use_shmem__))
#define m_data_start 0x20000000
@@ -66,12 +67,12 @@
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
* (+RO)
.ANY (+RO)
}
#if (defined(__use_shmem__))
@@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
* (+RW +ZI)
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
@@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (m_usb_bdt)
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (m_usb_global)
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
*(M0CODE)
* (.core1_code)
}
}

52
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf
View File

@@ -2,18 +2,19 @@
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JET98_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
** Version: rev. 1.0, 2018-08-22
** Build: b180921
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b190923
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -42,18 +43,18 @@
/* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */
#define m_interrupts_start 0x00010000
#define m_interrupts_size 0x00000140
#define m_interrupts_size 0x00000200
#define m_text_start 0x00010140
#define m_text_size 0x00061EC0
#define m_text_start 0x00010200
#define m_text_size 0x00061E00
#define m_core1_image_start 0x00072000
#define m_core1_image_size 0x00026000
#define m_core1_image_size 0x0002B800
/* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */
#if (defined(__use_shmem__))
#define m_data_start 0x20008000
#define m_data_size 0x00028000
#define m_data_size 0x00029000
#define m_rpmsg_sh_mem_start 0x20031800
#define m_rpmsg_sh_mem_size 0x00001800
#else
@@ -65,10 +66,15 @@
#define m_usb_sram_size 0x00004000
LR_m_text m_text_start m_text_size { ; load region size_region
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
* (+RO)
.ANY (+RO)
}
#if (defined(__use_shmem__))
@@ -78,34 +84,24 @@ LR_m_text m_text_start m_text_size { ; load region size_region
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
* (+RW +ZI)
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
}
LR_m_interrupts m_interrupts_start m_interrupts_size {
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
}
LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (m_usb_bdt)
}
}
LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (m_usb_global)
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
*(M0CODE)
* (.core1_code)
}
}

54
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf
View File

@@ -2,18 +2,19 @@
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JET98_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
** Version: rev. 1.0, 2018-08-22
** Build: b180921
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b190923
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -42,13 +43,13 @@
/* Only the first 64kB of flash is used as secure memory. */
#define m_interrupts_start 0x10000000
#define m_interrupts_size 0x00000140
#define m_interrupts_size 0x00000200
#define m_text_start 0x10000140
#define m_text_size 0x0000FCC0
#define m_text_start 0x10000200
#define m_text_size 0x0000FC00
#define m_core1_image_start 0x10072000
#define m_core1_image_size 0x00026000
#define m_core1_image_size 0x0002B800
/* Only first 32kB of data RAM is used as secure memory. */
#if (defined(__use_shmem__))
@@ -70,10 +71,15 @@
#define m_usb_sram_size 0x00004000
LR_m_text m_text_start m_text_size { ; load region size_region
LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
* (+RO)
.ANY (+RO)
}
#if (defined(__use_shmem__))
@@ -83,40 +89,28 @@ LR_m_text m_text_start m_text_size { ; load region size_region
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
* (+RW +ZI)
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
}
}
LR_m_interrupts m_interrupts_start m_interrupts_size {
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
}
}
LR_m_veneer_table m_veneer_table_start m_veneer_table_size {
ER_m_veneer_table m_veneer_table_start m_veneer_table_size {; veneer table
ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
*(Veneer$$CMSE)
}
}
LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (m_usb_bdt)
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (*m_usb_bdt)
}
}
LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (m_usb_global)
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
*(M0CODE)
* (.core1_code)
}
}

25
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf
View File

@@ -2,18 +2,19 @@
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JET98_cm33_core0
** LPC55S69JBD64_cm33_core0
** LPC55S69JEV98_cm33_core0
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181008
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b200722
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -47,7 +48,7 @@
#define m_text_size 0x00007E00
#define m_core1_image_start 0x20033000
#define m_core1_image_size 0x00008800
#define m_core1_image_size 0x0000C800
#if (defined(__use_shmem__))
#define m_data_start 0x20000000
@@ -66,12 +67,12 @@
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
* (+RO)
.ANY (+RO)
}
#if (defined(__use_shmem__))
@@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz
#endif
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
* (+RW +ZI)
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
@@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (m_usb_bdt)
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (m_usb_global)
* (*m_usb_global)
}
}
LR_CORE1_IMAGE m_core1_image_start {
CORE1_REGION m_core1_image_start m_core1_image_size {
*(M0CODE)
* (.core1_code)
}
}

30
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf
View File

@@ -2,18 +2,19 @@
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core1
** LPC55S69JET98_cm33_core1
** LPC55S69JBD64_cm33_core1
** LPC55S69JEV98_cm33_core1
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181008
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b210928
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2021 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -44,7 +45,7 @@
#define m_interrupts_size 0x00000200
#define m_text_start 0x00072200
#define m_text_size 0x00025E00
#define m_text_size 0x0002B600
#define m_data_start 0x20033000
@@ -62,17 +63,17 @@
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
* (+RO)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
* (+RW +ZI)
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
@@ -80,11 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (m_usb_bdt)
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (m_usb_global)
* (*m_usb_global)
}
#if (defined(__use_shmem__))
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
* (rpmsg_sh_mem_section)
}
#endif
}
}

33
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf
View File

@@ -2,18 +2,19 @@
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core1
** LPC55S69JET98_cm33_core1
** LPC55S69JBD64_cm33_core1
** LPC55S69JEV98_cm33_core1
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181008
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b200722
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2020 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -44,11 +45,11 @@
#define m_interrupts_size 0x00000200
#define m_text_start 0x20033200
#define m_text_size 0x0000B600
#define m_text_size 0x0000C600
#define m_data_start 0x2003E800
#define m_data_size 0x00005800
#define m_data_start 0x2003F800
#define m_data_size 0x00004800
#if (defined(__use_shmem__))
#define m_rpmsg_sh_mem_start 0x20031800
@@ -62,17 +63,17 @@
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
* (+RO)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
* (+RW +ZI)
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
@@ -80,16 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (m_usb_bdt)
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (m_usb_global)
* (*m_usb_global)
}
#if (defined(__use_shmem__))
#if (defined(__use_shmem__))
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
* (rpmsg_sh_mem_section)
}
#endif
}
#endif
}

27
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf
View File

@@ -2,18 +2,19 @@
/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core1
** LPC55S69JET98_cm33_core1
** LPC55S69JBD64_cm33_core1
** LPC55S69JEV98_cm33_core1
**
** Compiler: Keil ARM C/C++ Compiler
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181008
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
** Version: rev. 1.1, 2019-05-16
** Build: b190923
**
** Abstract:
** Linker file for the Keil ARM C/C++ Compiler
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
@@ -44,11 +45,11 @@
#define m_interrupts_size 0x00000200
#define m_text_start 0x30033200
#define m_text_size 0x0000B600
#define m_text_size 0x0000C600
#define m_data_start 0x3003E800
#define m_data_size 0x00005800
#define m_data_start 0x3003F800
#define m_data_size 0x00004800
#if (defined(__use_shmem__))
#define m_rpmsg_sh_mem_start 0x30031800
@@ -62,17 +63,17 @@
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
* (RESET,+FIRST)
* (.isr_vector,+FIRST)
}
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
* (InRoot$$Sections)
* (+RO)
.ANY (+RO)
}
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
* (+RW +ZI)
.ANY (+RW +ZI)
}
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
}
@@ -80,11 +81,11 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz
}
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
* (m_usb_bdt)
* (*m_usb_bdt)
}
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
* (m_usb_global)
* (*m_usb_global)
}
#if (defined(__use_shmem__))
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG

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1533
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s
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732
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s
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1527
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s
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17
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_i2c_LPC55S69_cm33_core0.cmake Normal file
View File

@@ -0,0 +1,17 @@
include_guard()
message("driver_cmsis_flexcomm_i2c component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_i2c_cmsis.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/.
)
include(driver_flexcomm_i2c_dma_LPC55S69_cm33_core0)
include(CMSIS_Driver_Include_I2C_LPC55S69_cm33_core0)

17
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_spi_LPC55S69_cm33_core0.cmake Normal file
View File

@@ -0,0 +1,17 @@
include_guard()
message("driver_cmsis_flexcomm_spi component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_spi_cmsis.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/.
)
include(driver_flexcomm_spi_dma_LPC55S69_cm33_core0)
include(CMSIS_Driver_Include_SPI_LPC55S69_cm33_core0)

17
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_usart_LPC55S69_cm33_core0.cmake Normal file
View File

@@ -0,0 +1,17 @@
include_guard()
message("driver_cmsis_flexcomm_usart component is included.")
target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/fsl_usart_cmsis.c
)
target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
${CMAKE_CURRENT_LIST_DIR}/.
)
include(driver_flexcomm_usart_dma_LPC55S69_cm33_core0)
include(CMSIS_Driver_Include_USART_LPC55S69_cm33_core0)

3279
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.c Normal file
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93
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.h Normal file
View File

@@ -0,0 +1,93 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
* Copyright 2016-2020 NXP. Not a Contribution.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _FSL_I2C_CMSIS_H_
#define _FSL_I2C_CMSIS_H_
#include "fsl_common.h"
#include "Driver_I2C.h"
#include "RTE_Device.h"
#include "fsl_i2c.h"
#include "fsl_flexcomm.h"
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
#include "fsl_i2c_dma.h"
#endif
#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0
extern ARM_DRIVER_I2C Driver_I2C0;
#endif
#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1
extern ARM_DRIVER_I2C Driver_I2C1;
#endif
#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2
extern ARM_DRIVER_I2C Driver_I2C2;
#endif
#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3
extern ARM_DRIVER_I2C Driver_I2C3;
#endif
#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4
extern ARM_DRIVER_I2C Driver_I2C4;
#endif
#if defined(I2C5) && defined(RTE_I2C5) && RTE_I2C5
extern ARM_DRIVER_I2C Driver_I2C5;
#endif
#if defined(I2C6) && defined(RTE_I2C6) && RTE_I2C6
extern ARM_DRIVER_I2C Driver_I2C6;
#endif
#if defined(I2C7) && defined(RTE_I2C7) && RTE_I2C7
extern ARM_DRIVER_I2C Driver_I2C7;
#endif
#if defined(I2C8) && defined(RTE_I2C8) && RTE_I2C8
extern ARM_DRIVER_I2C Driver_I2C8;
#endif
#if defined(I2C9) && defined(RTE_I2C9) && RTE_I2C9
extern ARM_DRIVER_I2C Driver_I2C9;
#endif
#if defined(I2C10) && defined(RTE_I2C10) && RTE_I2C10
extern ARM_DRIVER_I2C Driver_I2C10;
#endif
#if defined(I2C11) && defined(RTE_I2C11) && RTE_I2C11
extern ARM_DRIVER_I2C Driver_I2C11;
#endif
#if defined(I2C12) && defined(RTE_I2C12) && RTE_I2C12
extern ARM_DRIVER_I2C Driver_I2C12;
#endif
#if defined(I2C13) && defined(RTE_I2C13) && RTE_I2C13
extern ARM_DRIVER_I2C Driver_I2C13;
#endif
/* I2C Driver state flags */
#define I2C_FLAG_UNINIT (0UL)
#define I2C_FLAG_INIT (1UL << 0)
#define I2C_FLAG_POWER (1UL << 1)
#endif

3712
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.c Normal file
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bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.h Normal file
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@@ -0,0 +1,93 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
* Copyright 2016-2020 NXP. Not a Contribution.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _FSL_SPI_CMSIS_H_
#define _FSL_SPI_CMSIS_H_
#include "fsl_spi.h"
#include "RTE_Device.h"
#include "Driver_SPI.h"
#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT)
#include "fsl_spi_dma.h"
#endif
#if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0
extern ARM_DRIVER_SPI Driver_SPI0;
#endif /* SPI0 */
#if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1
extern ARM_DRIVER_SPI Driver_SPI1;
#endif /* SPI1 */
#if defined(SPI2) && defined(RTE_SPI2) && RTE_SPI2
extern ARM_DRIVER_SPI Driver_SPI2;
#endif /* SPI2 */
#if defined(SPI3) && defined(RTE_SPI3) && RTE_SPI3
extern ARM_DRIVER_SPI Driver_SPI3;
#endif /* SPI3 */
#if defined(SPI4) && defined(RTE_SPI4) && RTE_SPI4
extern ARM_DRIVER_SPI Driver_SPI4;
#endif /* SPI4 */
#if defined(SPI5) && defined(RTE_SPI5) && RTE_SPI5
extern ARM_DRIVER_SPI Driver_SPI5;
#endif /* SPI5 */
#if defined(SPI6) && defined(RTE_SPI6) && RTE_SPI6
extern ARM_DRIVER_SPI Driver_SPI6;
#endif /* SPI6 */
#if defined(SPI7) && defined(RTE_SPI7) && RTE_SPI7
extern ARM_DRIVER_SPI Driver_SPI7;
#endif /* SPI7 */
#if defined(SPI8) && defined(RTE_SPI8) && RTE_SPI8
extern ARM_DRIVER_SPI Driver_SPI8;
#endif /* SPI8 */
#if defined(SPI9) && defined(RTE_SPI9) && RTE_SPI9
extern ARM_DRIVER_SPI Driver_SPI9;
#endif /* SPI9 */
#if defined(SPI10) && defined(RTE_SPI10) && RTE_SPI10
extern ARM_DRIVER_SPI Driver_SPI10;
#endif /* SPI10 */
#if defined(SPI11) && defined(RTE_SPI11) && RTE_SPI11
extern ARM_DRIVER_SPI Driver_SPI11;
#endif /* SPI11 */
#if defined(SPI12) && defined(RTE_SPI12) && RTE_SPI12
extern ARM_DRIVER_SPI Driver_SPI12;
#endif /* SPI12 */
#if defined(SPI13) && defined(RTE_SPI13) && RTE_SPI13
extern ARM_DRIVER_SPI Driver_SPI13;
#endif /* SPI13 */
#define SPI_FLAG_UNINIT (0UL)
#define SPI_FLAG_INIT (1UL << 0)
#define SPI_FLAG_POWER (1UL << 1)
#define SPI_FLAG_CONFIGURED (1UL << 2)
#define SPI_FLAG_MASTER (1UL << 3)
#endif

3743
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bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.h Normal file
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@@ -0,0 +1,94 @@
/*
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
* Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution.
* Copyright 2016-2017 NXP. Not a Contribution.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _FSL_USART_CMSIS_H_
#define _FSL_USART_CMSIS_H_
#include "fsl_common.h"
#include "Driver_USART.h"
#include "RTE_Device.h"
#include "fsl_usart.h"
#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT)
#include "fsl_usart_dma.h"
#endif
#if defined(USART0) && defined(RTE_USART0) && RTE_USART0
extern ARM_DRIVER_USART Driver_USART0;
#endif /* USART0 */
#if defined(USART1) && defined(RTE_USART1) && RTE_USART1
extern ARM_DRIVER_USART Driver_USART1;
#endif /* USART1 */
#if defined(USART2) && defined(RTE_USART2) && RTE_USART2
extern ARM_DRIVER_USART Driver_USART2;
#endif /* USART2 */
#if defined(USART3) && defined(RTE_USART3) && RTE_USART3
extern ARM_DRIVER_USART Driver_USART3;
#endif /* USART3 */
#if defined(USART4) && defined(RTE_USART4) && RTE_USART4
extern ARM_DRIVER_USART Driver_USART4;
#endif /* USART4 */
#if defined(USART5) && defined(RTE_USART5) && RTE_USART5
extern ARM_DRIVER_USART Driver_USART5;
#endif /* USART5 */
#if defined(USART6) && defined(RTE_USART6) && RTE_USART6
extern ARM_DRIVER_USART Driver_USART6;
#endif /* USART6 */
#if defined(USART7) && defined(RTE_USART7) && RTE_USART7
extern ARM_DRIVER_USART Driver_USART7;
#endif /* USART7 */
#if defined(USART8) && defined(RTE_USART8) && RTE_USART8
extern ARM_DRIVER_USART Driver_USART8;
#endif /* USART8 */
#if defined(USART9) && defined(RTE_USART9) && RTE_USART9
extern ARM_DRIVER_USART Driver_USART9;
#endif /* USART9 */
#if defined(USART10) && defined(RTE_USART10) && RTE_USART10
extern ARM_DRIVER_USART Driver_USART10;
#endif /* USART10 */
#if defined(USART11) && defined(RTE_USART11) && RTE_USART11
extern ARM_DRIVER_USART Driver_USART11;
#endif /* USART11 */
#if defined(USART12) && defined(RTE_USART12) && RTE_USART12
extern ARM_DRIVER_USART Driver_USART12;
#endif /* USART12 */
#if defined(USART13) && defined(RTE_USART13) && RTE_USART13
extern ARM_DRIVER_USART Driver_USART13;
#endif /* USART13 */
/* USART Driver state flags */
#define USART_FLAG_UNINIT (0UL)
#define USART_FLAG_INIT (1UL << 0)
#define USART_FLAG_POWER (1UL << 1)
#define USART_FLAG_CONFIGURED (1UL << 2)
#endif /* _FSL_USART_CMSIS_H_ */

215
bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c
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@@ -1,5 +1,5 @@
/*
* Copyright 2018, NXP
* Copyright 2018-2021, NXP
* All rights reserved.
*
*
@@ -60,9 +60,9 @@ static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base)
}
/*!
* @brief Enable the access to ANACTRL registers and initialize ANACTRL module.
* brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function.
*
* @param base ANACTRL peripheral base address.
* param base ANACTRL peripheral base address.
*/
void ANACTRL_Init(ANACTRL_Type *base)
{
@@ -75,9 +75,9 @@ void ANACTRL_Init(ANACTRL_Type *base)
}
/*!
* @brief De-initialize ANACTRL module.
* brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function.
*
* @param base ANACTRL peripheral base address.
* param base ANACTRL peripheral base address.
*/
void ANACTRL_Deinit(ANACTRL_Type *base)
{
@@ -90,214 +90,144 @@ void ANACTRL_Deinit(ANACTRL_Type *base)
}
/*!
* @brief Set the on-chip high-speed Free Running Oscillator.
* brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output
* and enable/disable 96MHZ clock output.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
* param base ANACTRL peripheral base address.
* param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
*/
void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config)
void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0;
uint32_t tmp32 = base->FRO192M_CTRL;
/* Set FRO trim values. */
base->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_WRTRIM_MASK;
tmp32 |= ANACTRL_FRO192M_CTRL_BIAS_TRIM(config->biasTrim) | ANACTRL_FRO192M_CTRL_TEMP_TRIM(config->tempTrim) |
ANACTRL_FRO192M_CTRL_DAC_TRIM(config->dacTrim);
tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK);
if (config->enable12MHzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK;
}
if (config->enable48MhzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK;
}
if (config->enable96MHzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
}
if (config->enableAnalogTestBus)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK;
}
base->FRO192M_CTRL |= tmp32;
}
/*!
* @brief Get the default configuration of FRO192M.
* brief Gets the default configuration of FRO192M.
* The default values are:
* code
* config->biasTrim = 0x1AU;
* config->tempTrim = 0x20U;
* config->enable12MHzClk = true;
* config->enable48MhzClk = true;
* config->dacTrim = 0x80U;
* config->enableAnalogTestBus = false;
* config->enable96MHzClk = false;
* encode
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
config->enable12MHzClk = true;
config->enable96MHzClk = false;
endcode
* param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure.
*/
void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
(void)memset(config, 0, sizeof(*config));
config->biasTrim = 0x1AU;
config->tempTrim = 0x20U;
config->enable12MHzClk = true;
config->enable48MhzClk = true;
config->dacTrim = 0x80U;
config->enableAnalogTestBus = false;
config->enable96MHzClk = false;
config->enable12MHzClk = true;
config->enable96MHzClk = false;
}
/*!
* @brief Set the 32 MHz Crystal oscillator.
* brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU
* system, and so on.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
* param base ANACTRL peripheral base address.
* param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
*/
void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config)
void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0U;
uint32_t tmp32 = base->XO32M_CTRL;
tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK);
/* Set XO32M CTRL. */
if (config->enableACBufferBypass)
{
tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
}
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
if (config->enablePllUsbOutput)
{
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
}
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
if (config->enableACBufferBypass)
{
tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
}
if (config->enableSysCLkOutput)
{
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
}
base->XO32M_CTRL = tmp32;
/* Set LDO XO32M. */
tmp32 = ANACTRL_LDO_XO32M_HIGHZ(config->LDOOutputMode) | ANACTRL_LDO_XO32M_VOUT(config->LDOOutputLevel) |
ANACTRL_LDO_XO32M_IBIAS(config->bias) | ANACTRL_LDO_XO32M_STABMODE(config->stability);
if (config->enableLDOBypass)
#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
if (config->enableADCOutput)
{
tmp32 |= ANACTRL_LDO_XO32M_BYPASS_MASK;
base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
}
base->LDO_XO32M = tmp32;
else
{
base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK;
}
#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
}
/*!
* @brief Get the default configuration of XO32M.
* brief Gets the default configuration of XO32M.
* The default values are:
* code
* config->enableACBufferBypass = false;
* config->enablePllUsbOutput = false;
* config->enableSysCLkOutput = false;
* config->enableLDOBypass = false;
* config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
* config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
* config->bias = 2U;
* config->stability = 3U;
* encode
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
config->enableSysCLkOutput = false;
config->enableACBufferBypass = false;
endcode
* param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure.
*/
void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
(void)memset(config, 0, sizeof(*config));
config->enableACBufferBypass = false;
config->enablePllUsbOutput = false;
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD)
config->enablePllUsbOutput = false;
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */
config->enableSysCLkOutput = false;
config->enableLDOBypass = false;
config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
config->bias = 2U;
config->stability = 3U;
config->enableACBufferBypass = false;
#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \
FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD)
config->enableADCOutput = true;
#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */
}
#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL)
/*!
* @brief Set the ring oscillators.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
*/
void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0U;
/* Configure the first ring oscillator. */
tmp32 = ANACTRL_RINGO0_CTRL_SL(config->ringOscSel) | ANACTRL_RINGO0_CTRL_FS(config->ringOscFreqOutputDiv) |
ANACTRL_RINGO0_CTRL_SWN_SWP(config->pnRingOscMode) | ANACTRL_RINGO0_CTRL_E_ND0_MASK |
ANACTRL_RINGO0_CTRL_E_ND1_MASK | ANACTRL_RINGO0_CTRL_E_NR0_MASK | ANACTRL_RINGO0_CTRL_E_NR1_MASK |
ANACTRL_RINGO0_CTRL_E_IV0_MASK | ANACTRL_RINGO0_CTRL_E_IV1_MASK | ANACTRL_RINGO0_CTRL_E_PN0_MASK |
ANACTRL_RINGO0_CTRL_E_PN1_MASK | ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK |
ANACTRL_RINGO0_CTRL_DIVISOR(config->ringOscOutClkDiv);
base->RINGO0_CTRL = tmp32;
/* Configure the second and third ring oscillator. */
tmp32 = ANACTRL_RINGO1_CTRL_S(config->ringOscSel) | ANACTRL_RINGO1_CTRL_FS(config->ringOscFreqOutputDiv) |
ANACTRL_RINGO1_CTRL_E_R24_MASK | ANACTRL_RINGO1_CTRL_E_R35_MASK | ANACTRL_RINGO1_CTRL_E_M2_MASK |
ANACTRL_RINGO1_CTRL_E_M3_MASK | ANACTRL_RINGO1_CTRL_E_M4_MASK | ANACTRL_RINGO1_CTRL_E_M5_MASK |
ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK | ANACTRL_RINGO1_CTRL_DIVISOR(config->ringOscOutClkDiv);
base->RINGO1_CTRL = tmp32;
base->RINGO2_CTRL = tmp32;
/* Ensure the Riongo module is enabled. */
base->RINGO0_CTRL &= ~ANACTRL_RINGO0_CTRL_PD_MASK;
base->RINGO1_CTRL &= ~ANACTRL_RINGO1_CTRL_PD_MASK;
base->RINGO2_CTRL &= ~ANACTRL_RINGO2_CTRL_PD_MASK;
}
/*!
* @brief Get the default configuration of ring oscillators.
* The default values are:
* code
* config->ringOscSel = kANACTRL_ShortRingOsc;
* config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
* config->pnRingOscMode = kANACTRL_NormalMode;
* config->ringOscOutClkDiv = 0U;
* encode
* @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
*/
void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->ringOscSel = kANACTRL_ShortRingOsc;
config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
config->pnRingOscMode = kANACTRL_NormalMode;
config->ringOscOutClkDiv = 0U;
}
/*!
* @brief Measure Frequency
* brief Measures the frequency of the target clock source.
*
* This function measures target frequency according to a accurate reference frequency.The formula is:
* Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
*
* @param base ANACTRL peripheral base address.
* @scale Define the power of 2 count that ref counter counts to during measurement.
* @refClkFreq frequency of the reference clock.
* @return frequency of the target clock.
* note Both tartget and reference clocks are selectable by programming the target clock select FREQMEAS_TARGET register
* in INPUTMUX and reference clock select FREQMEAS_REF register in INPUTMUX.
*
* @Note the minimum count (scale) is 2.
* param base ANACTRL peripheral base address.
* param scale Define the power of 2 count that ref counter counts to during measurement, ranges from 2 to 31.
* param refClkFreq frequency of the reference clock.
*
* return frequency of the target clock.
*/
uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq)
{
@@ -314,7 +244,8 @@ uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t re
/* Calculate the target clock frequency. */
capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK);
targetClkFreq = (capval * refClkFreq) / ((1 << scale) - 1);
targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL);
return targetClkFreq;
}
#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */

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